Version 1.3.

Add Blue Pill support.
Switch off red LED for Nitrokey Start.
2017-02-02 12:56:13 +09:00 · 2017-02-01 17:31:52 +09:00 · 2017-02-01 15:24:55 +09:00 · 2016-10-13 10:18:47 +09:00 · 2016-10-12 12:06:37 +09:00 · 2016-07-11 17:21:32 +09:00
100 changed files with 15291 additions and 3068 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -1,7 +1,3 @@
-example-cdc/.dep
-example-cdc/board.h
-example-cdc/build
-example-led/.dep
-example-led/board.h
-example-led/build
+*/build
+*/.dep
 doc/chopstx.info
--- a/51
+++ b/51
@@ -0,0 +1,51 @@
+Aidan Thornton:
+    Added Maple Mini support.
+	board/board-maple-mini.h
+
+Kaz Kojima:
+    Added STM32 Primer2 support.
+	board/board-stm32-primer2.h
+	example-primer2
+
+Kenji Rikitake:
+    Added ST Dongle support.
+	board/board-st-dongle.h
+    Added ST Nucleo F103 support.
+	board/board-st-nucleo-f103.h
+
+Kiwamu Okabe:
+    Wrote an OpenOCD scirpt:
+        example-fsm-55/stlink-v2.cfg
+
+Mateusz Zalega:
+    Added Nitrokey-Start support.
+	board/board-nitrokey-start.h
+
+NIIBE Yutaka:
+    Wrote the library:
+	chopstx.c, entry.c, eventflag.c,
+        chopstx.h, eventflag.h
+    Wrote the drivers mcu/*:
+    	clk_gpio_init-mkl27z.c, clk_gpio_init-stm32.c,
+	sys-stm32f103.c, sys-stm32f030.c, sys-mkl27z.c,
+	adc-stm32f103.c, adc-mkl27z.c
+    Drew the logo:
+	chopstx.svg, chopstx.png
+    Wrote examples:
+        example-led, example-cdc, example-fsm-55, example-fs-bb48
+    Wrote board/*:
+        board-fst-01.h, board-fst-01-00.h,
+	board-olimex-stm32-h103.h, board-stm8s-discovery.h
+	board-cq-starm.h, board-stbee-mini.h, board-stbee.h,
+
+	board-stm32f0-discovery.h, board-fsm-55.h,
+
+	board-fs-bb48.h
+
+Paul Fertser:
+    Added Blue Pill support.
+	board/board-blue-pill.h
+
+Szczepan Zalega:
+    Modified Nitrokey-Start support.
+	board/board-nitrokey-start.h
--- a/770
+++ b/770
@@ -1,3 +1,773 @@
+2017-02-02  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.3.
+	* doc/chopstx.texi (VERSION): 1.3.
+
+2017-02-01  Paul Fertser <fercerpav@gmail.com>
+
+	* board/board-blue-pill.h: New.
+
+2016-12-08  Szczepan Zalega <szczepan@nitrokey.com>
+
+	* board/board-nitrokey-start.h (VAL_GPIO_USB_ODR): Switch off red
+	LED for Nitrokey Start.
+
+2016-10-13  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.2.
+	* doc/chopstx.texi (VERSION): 1.2.
+
+2016-10-12  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_join, chopstx_cancel): chopstx_join is
+	cancellation point.
+
+2016-07-11  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/stm32f103.h: Add more from Gnuk 1.1.9.
+	* example-cdc, example-fs-bb48, example-fsm-55, example-led:
+	Update for stack addr/size.
+
+2016-07-01  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.1.
+	* doc/chopstx.texi (VERSION): 1.1.
+
+	* chopstx.c (chopstx_setpriority): Change the API.
+
+2016-06-30  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb-cdc.c (tty_recv, tty_main): Follow the change of
+	chopstx_poll.
+
+2016-06-29  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-fs-bb48: Update.
+	* example-fs-bb48/touch.c: New.
+
+	* chopstx.c (chopstx_setpriority): Fix sched_lock/unlock.
+
+2016-06-28  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.h (struct chx_poll_head): Declare here.
+
+	* chopstx.c (chopstx_poll): Don't use varargs, but use
+	an array of pointer.
+	(chopstx_intr_wait): Follow the change of chopstx_poll.
+	* eventflag.c (eventflag_wait_timeout): Likewise.
+	* contrib/adc-stm32f103.c (adc_wait_completion): Likewise.
+	* contrib/adc-mkl27z.c (adc_wait_completion): Likewise.
+
+2016-06-16  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.0.
+	* doc/chopstx.texi (VERSION): 1.0.
+
+	* board/board-fst-01g.h: New.
+
+2016-06-15  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_exit): Add "naked" attribute.
+
+2016-06-14  Niibe Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-stm32f103.c (usb_lld_ctrl_recv): Fix the state and make
+	the endpoint 0 RX_VALID.
+
+2016-06-10  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* usb_lld.h (USB_EVENT_OK): Rename.
+	* mcu/usb-stm32f103.c: Update.
+	* mcu/usb-mkl27z.c: Likewise.
+
+	* example-cdc/usb-cdc.c: Follow the change of API.
+	* example-fs-bb48/usb-cdc.c: Likewise.
+
+2016-06-09  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-stm32f103.c (usb_lld_ctrl_recv): Rename.
+	(usb_lld_ctrl_send): Rename.
+	(usb_lld_ctrl_ack): Rename and let have return value.
+	* mcu/usb-mkl27z.c: Likewise.
+
+	* example-cdc/usb-cdc.c: Follow the change of API.
+	* example-fs-bb48/usb-cdc.c: Likewise.
+
+2016-06-08  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-stm32f103.c: Rewrite to be event driven API.
+	* mcu/usb-mkl27z.c: Likewise.
+
+	* example-cdc/usb-cdc.c: Update to new USB API.
+	* example-fs-bb48/usb-cdc.c: Likewise.
+
+	* example-cdc/tty.h: Change tty API to be C string (char*)
+	friendly.
+	* example-fs-bb48/tty.h: Ditto.
+
+2016-06-02  Niibe Yutaka  <gniibe@fsij.org>
+
+	* contrib/adc-mkl27z.c: Move from mcu.
+	* contrib/adc-stm32f103.c: Move from mcu.
+
+	* example-led/Makefile (CHIP): Define as stm32f0.
+
+	* mcu/sys-stm32f0.h: Rename from sys-stm32f030.h,
+	as we share it among STM32F030 and STM32F050.
+	* mcu/sys-stm32f0.c: Likewise.
+
+	* board/board-stm32f0-discovery.h (MCU_STM32F0): Define.
+
+	* sys.h: Support STM32F0.
+
+2016-06-01  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.h (chx_fatal): Remove weak attribute from declaration.
+	* chopstx.c (chx_fatal): Add weak attribute to implementation.
+
+2016-05-31  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.12.
+	* doc/chopstx.texi (VERSION): 0.12.
+
+	* sys.h: New.
+
+	* example-cdc, example-fs-bb48: Update.
+	* example-fsm-55, example-led: Update.
+
+2016-05-30  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-stm32f103.c (usb_lld_setup_endpoint): Start with
+	EP_RX_NAK.
+
+	* mcu/usb-mkl27z.c (handle_transaction): Handle NAK case.
+	(usb_lld_setup_endp): Rename from usb_lld_setup_endpoint.
+	(usb_lld_rx_enable_buf): Rename from usb_lld_rx_enable.
+	(usb_lld_tx_enable_buf): Rename from usb_lld_tx_enable.
+
+	* mcu/adc-stm32f103.c: New from NeuG.
+	* mcu/stm32f103.h: New from NeuG.
+
+	* example-cdc: Update.
+
+2016-05-30  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/adc-mkl27z.c, mcu/sys-mkl27z.c, mcu/usb-mkl27z.c: Moved from
+	example-fs-bb48.
+
+	* mcu/adc-stm32f103.c, mcu/sys-stm32f103.c, mcu/usb-stm32f103.c:
+	Moved from example-cdc.
+
+2016-05-30  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-fs-bb48/sys.c (flash_do_internal, flash_do)
+	(flash_erase_page, flash_program_word): New.
+	* example-fs-bb48/command.c (cmd_fes, cmd_fww): New.
+
+2016-05-27  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-fs-bb48/command.c (cmd_sysinfo): New.
+	* example-fs-bb48/sample.ld: Update.
+	* example-fs-bb48/sys.h: New.
+	Move crc32 functions declarations here.
+	* example-fs-bb48/sys.c: Rename from first-pages.c.
+	Include mcu/clk_gpio_init-kl.c to define clock_init and
+	gpio_init.
+	(set_led): New.
+	(reset): Initialize MSP.
+	(flash_config): Include comparison key.
+	(crc32_init, crc32_u8, crc32_u32): Change the API.
+	Write them in assembler so that the size of functions
+	keep unchanged.
+	(sys_version, sys_board_id, sys_board_name, sys_vector): New.
+
+2016-05-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* entry.c: Follow the move of clk_gpio_init*.c
+	* example-cdc/sys.c: Likewise.
+	* example-led/sys.c: Likewise.  Update to 3.0.
+	* example-primer2/sys.c: Update.
+
+	* mcu/clk_gpio_init-stm32.c: Moved.
+	* mcu/clk_gpio_init-kl.c: Moved.
+	* mcu/kl_sim.h: New (was in example-fs-bb48).
+
+	* example-fs-bb48/adc_kl27z.c: Use DMA0 and DMA1.
+	* example-fs-bb48/adc_kl27z.c (adc_wait_completion): Use only
+	least significant 8-bit (most significant for randomness).
+	* example-fs-bb48/command.c (cmd_adc): Rename from
+	cmd_temperature.
+
+2016-05-24  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-fs-bb48/command.c: New.
+	* example-fs-bb48: Update example CDC device.
+
+2016-05-23  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopst.x (chx_sched) [__ARM_ARCH_6M__]: Maintain PSR.
+
+2016-05-23  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_poll): Fix a race.  Check COUNTER.
+
+	* example-cdc/usb-cdc.c (tty_input_char): Include newline.
+	* example-cdc/sample.c: Handle newline.
+
+	* example-fs-bb48/usb-cdc.c: Update from example-cdc.
+	* example-fs-bb48/tty.h: Likewise.
+	* example-fs-bb48/sample.c: Follow the change.
+
+2016-05-20  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_usec_wait_var): internal function.
+	(chopstx_wakeup_usec_wait): Remove.
+
+2016-05-19  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.11.
+	* doc/chopstx.texi (VERSION): 0.11.
+
+2016-05-18  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* eventflag.c: Update using chopstx_poll and offer API for poll.
+
+	* chopstx.c (requeue): New.
+	(chopstx_mutex_lock, chopstx_join): Fix by requeue.
+	(chopstx_main_init): Remove.
+	(chopstx_setpriority): New.
+
+	* example-cdc/usb-cdc.c: Prepare for multiple TTYs.
+
+2016-05-17  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb-cdc.c: Update as TTY input/output with line
+	editing support.
+	* example-cdc/sample.c: Likewise.
+	* example-cdc/tty.h: Rename from stream.h.
+
+	* chopstx.c (chopstx_poll): Set ->ready = 0.
+	Add spinlock for ll_dequeue.
+
+2016-05-16  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/sys.c (nvic_enable_vector): Remove.
+	(usb_lld_sys_init): Don't setup NVIC priority.
+	(sys_version): sys version 3.0.
+
+2016-05-16  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.h (CHOPSTX_EXIT_SUCCESS, CHOPSTX_EXIT_CANCELED)
+	(CHOPSTX_EXIT_CANCELED_IN_SYNC): Remove.
+	(CHOPSTX_CANCELED): New.
+
+	* chopstx.c (chopstx_testcancel): Use CHOPSTX_CANCELED.
+	(chx_sched, chx_snooze): Re-define return values cleanly.
+	(chopstx_cancel): Use return value of chx_sched to cancel.
+	(chopstx_cond_wait, chopstx_join, chopstx_poll): Implement
+	cancellation rather easier way with return value of chx_sched.
+
+2016-05-15  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_claim_irq): Don't register clean up function.
+	(chx_release_irq): Remove.
+	(chopstx_cancel): Disable IRQ when canceled at POLL.
+	(chopstx_poll): Fix IRQ handling.
+
+2016-05-13  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_handle_intr): Call chx_request_preemption.
+	(chx_wakeup, chopstx_cond_signal, chopstx_cond_broadcast)
+	(chx_intr_hook, chopstx_poll): Cleanup.
+
+2016-05-13  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_exit): Don't call chx_release_irq_thread.
+	(chx_release_irq_thread): Remove.
+	(q_intr): New variable.
+	(intr_top): Remove.
+	(chx_handle_intr, chx_init, chopstx_claim_irq)
+	(chopstx_intr_wait): Use Q_INTR.
+	(chx_intr_hook): New.
+	(chopstx_poll): Support CHOPSTX_POLL_INTR.
+	(chopstx_release_irq): Remove.
+	(chx_release_irq): New internal function.
+	(THREAD_WAIT_INT): Remove.
+	(chopstx_intr_wait): Rewrite by chopstx_poll.
+
+2016-05-13  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_sched) [__ARM_ARCH_6M__]: Fix asm.
+	(chx_handle_intr, chx_wakeup, chopstx_cancel): Fix for polling
+	with no timeout.
+
+	* example-cdc/sample.c (main): Update chopstx_poll example.
+	* example-fs-bb48/sample.c (main): Ditto.
+
+	* chopstx.c (struct chx_px): Add READY_P and LOCK.
+	(chx_proxy_init): Add initialization of new members.
+	(chx_wakeup): Spinlock PX.
+	(chopstx_mutex_lock): Add protection by splinlock.
+	(chx_cond_hook, chx_join_hook): Change arguments.
+	(chx_cond_unhook, chx_join_unhook): Remove.
+	(chopstx_claim_irq): Compatible to chx_poll.
+	(chopstx_join): Fix spinlocking.
+	(chopstx_cancel): Fix spinlocking.
+
+2016-05-12  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/sample.c: Update using chopstx_poll.
+	* example-cdc/sample.ld: Likewise.
+	* example-cdc/stream.h: Likewise.
+	* example-cdc/usb-cdc.c: Likewise.
+
+	* chopstx.c (chopstx_mutex_init): Initialize OWNER, too.
+	(preempt) [__ARM_ARCH_7M__]: Bug fix for register 0 to inhibit
+	scheduling.
+	(chx_sched) [__ARM_ARCH_6M__]: Return YIELD normally.
+	(MAX_USEC_FOR_TIMER): Guarantee 24-bit tick.
+	(chx_snooze): Revert the change of 2016-04-24 and modify
+	chopstx_poll instead.
+	(chopstx_poll): Support waiting forever.
+
+2016-04-24  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_snooze): Wait forever when it's POLL and usec==0.
+
+2016-04-22  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-fs-bb48/first-pages.c: Rename from reset.c and merge
+	crc32.c.
+	* example-fs-bb48/sample.ld: Define section for first two pages.
+	* example-fs-bb48/usb_kl27z.c (__usb_buf__): Remove.
+
+	* chopstx.c (chx_cond_hook): Rename from chopstx_cond_hook and make
+	it internal.
+	(chx_cond_unhook): Likewise.
+	(chx_join_hook, chx_join_unhook): New.
+	(chopstx_poll): Change API, not exposing internals of hook/unhook.
+
+	* example-fs-bb48/sample.c (main): Follow the API change of
+	chopstx_poll.
+
+2016-04-21  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_snooze, chx_wakeup): New.
+	(chopstx_cond_hook, chopstx_cond_unhook): New.
+	(chopstx_cond_signal, chopstx_cond_broadcast): Fix for poll.
+	(chx_proxy_init): Initialize with RUNNING.
+	(chopstx_poll): Fix with chx_snooze.
+	(chx_exit): Use chx_wakeup.
+
+	* example-fs-bb48/sample.c (main): Update with chopstx_poll.
+	* example-fs-bb48/usb-cdc.c (stream_recv): Fix the loop clear
+	FLAG_RECV_AVAIL only after we process it.
+
+2016-04-20  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb_stm32f103.c (usb_lld_reset): Supply FEATURE
+	argument.  Call usb_lld_set_configuration internally and set
+	FEATURE.
+	(usb_lld_set_feature): Remove.
+	* example-cdc/usb-cdc.c (usb_cb_device_reset): Update with new
+	API.
+
+	* example-cdc/sys.c: Include clk_gpio_init-stm32.c.
+	* example-led/sys.c, example-primer2/sys.c: Ditto.
+
+2016-04-19  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-fs-bb48/sample.c (main): Change the example to display
+	CRC32 value from input line.
+
+2016-04-18  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-fs-bb48: New directory for FS-BB48.
+
+	* clk_gpio_init-kl.c: New.
+	* clk_gpio_init-stm32.c: Rename from clk_gpio_init.c.
+
+2016-04-07  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-fsm-55/sys.c: Update for non-SVC Chopstx.
+
+2016-04-07  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb-cdc.c: Update.
+
+	* example-cdc/usb_stm32f103.c (usb_handle_transfer): Don't use
+	weak symbols for callbacks, but use explicit callbacks of
+	usb_cb_tx_done and usb_cb_rx_ready.
+
+	* example-cdc/usb_lld.h (usb_cb_tx_done, usb_cb_rx_ready): New
+	callbacks.
+
+2016-04-07  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_cpu_sched_lock, chx_cpu_sched_unlock): Use SVC
+	for Cortex-M3, because of ICI/IT of ESPR.
+	(chx_sched): Invoke svc for Cortex-M3.
+	(preempt, svc): Change back for Cortex-M3.
+
+2016-04-07  Niibe Yutaka  <gniibe@fsij.org>
+
+	* entry.c (vector_table): Since IDLE thread runs with PSP now, use
+	different value for MSP.
+
+	* chopstx.c (chx_sched): Push LR value to PC slot on stack, so
+	that it returns directly to caller.
+
+2016-04-06  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (struct chx_pq): New struct for priority queue.
+	(struct chx_px): New struct for proxy.
+	(struct chx_thread): New member FLAG_IS_PROXY.
+	(ll_dequeue, ll_insert, ll_pop, ll_prio_push, ll_prio_enqueue)
+	Change API.
+	(THREAD_WAIT_POLL): New thread status.
+	(chx_ready_pop, chx_ready_push, chx_ready_enqueue): Type coercion.
+	(chx_timer_insert, chx_timer_dequeue, chx_timer_expired): Use
+	chx_pq.
+	(chx_handle_intr, chopstx_cancel): Handle THREAD_WAIT_POLL.
+	(chx_init): Type coercion.
+	(chx_exit): Handle proxy for join.
+	(chopstx_create): Initialize the member FLAG_IS_PROXY.
+	(chopstx_cond_signal) Handle proxy.
+	(chx_proxy_init, chopstx_poll): New.
+
+2016-04-06  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.h (struct chx_qh): New struct.
+
+	* chopstx.c (struct chx_queue): Use chx_qh.
+	(struct chx_thread): New member PARENT.
+	(ll_empty): Use chx_qh.
+	(ll_prio_push, ll_prio_enqueue): Set the member PARENT.
+	(chx_ready_pop, chx_ready_push, chx_ready_enqueue): Use the
+	member Q.
+	(chx_timer_insert): Return TP.
+	(chx_timer_dequeue, chx_timer_expired): Use the member Q.
+	(chx_init): Initialize change for Q_READY, Q_TIMER, Q_JOIN.
+	(chx_sched, preempt): Handle return value of chx_timer_insert.
+	(chx_exit, chopstx_mutex_init, chopstx_cond_init): Use the member Q.
+	(chx_mutex_unlock): Type coercion to CHX_THREAD.
+	(chopstx_create): Initialize PARENT field.
+	(chopstx_mutex_lock): Use the PARENT field.
+	(chopstx_join): Use ll_prio_enqueue, instead of ll_insert.
+	(chopstx_wakeup_usec_wait): Set REG_R0 on the stack.
+
+2016-04-06  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (struct chx_thread): Move tcontext field.
+	(chx_cpu_sched_lock, chx_cpu_sched_unlock): Use CPSID/CPSIE.
+	(chx_sched): Don't use SVC.  Return integer value.
+	(chopstx_usec_wait_var): Don't use R8.
+	(preempt): Modify so that we don't use SVC.
+
+2016-04-05  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (struct NVIC): Add volatile qualifier to members.
+	(chx_spin_init): New.
+	(chopstx_mutex_init, chopstx_cond_init): Call chx_spin_init.
+	(chx_init): Initialize the spinlocks for INTR_LOCK, Q_READY,
+	Q_TIMER, and Q_JOIN.
+
+2016-03-08  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.h (CHOPSTX_THREAD_SIZE): Align by 8.
+	* chopstx.c (struct chx_thread): Add W field to align.  This is to
+	comply AAPCS (ARM Architecture Procedure Call Standard).
+	(chx_init): Initialize W.
+
+	* example-cdc/usb_stm32f103.c, usb_lld.h: Update from Gnuk.
+	* example-cdc/usb-cdc.c: Update.
+
+2015-11-05  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/sample.c: Enhanced to be echo service.
+
+2015-09-15  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.10.
+	* doc/chopstx.texi (VERSION): 0.10.
+
+	* example-cdc/usb_stm32f103.c: Update from Gnuk.
+
+2015-09-14  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (q_exit): Remove.
+	(chx_init, chx_exit): Remove access to Q_EXIT.
+	(chx_release_irq_thread): Fix removing from the list.
+
+2015-09-11  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_init, chopstx_create): Fix the initial value
+	of flag_cancelable.
+
+2015-09-10  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.09.
+	* doc/chopstx.texi (VERSION): 0.09.
+
+	* chopstx.c (chx_release_irq_thread): Rename.
+
+2015-09-09  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb-cdc.c (usb_cb_ctrl_write_finish): Distinguish
+	DTR signal.
+	(usb_cb_device_reset): Fix USB reset handling.
+
+	* chopstx.c (chopstx_usec_wait_var, chopstx_cond_wait)
+	(chopstx_intr_wait): Call chopstx_testcancel.
+	(chopstx_setcancelstate): New.
+
+	* chopstx.c (chx_systick_reset, chx_systick_reload)
+	(chx_systick_get): Factor out systick functions.
+	(chx_prio_init): Factor out.
+
+2015-09-08  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_request_preemption): Add PRIO argument and check
+	the condition inside.
+	(chx_timer_expired, chx_handle_intr): Call unconditionally.
+	(intr_lock): New variable.
+	(chx_handle_intr, chopstx_claim_irq, chopstx_release_irq)
+	(chopstx_release_irq_thread): Add spin lock with intr_lock.
+
+	* chopstx.h (chx_intr): Remove member LOCK.
+
+2015-09-07  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-primer2: New from Kazumoto Kojima.
+
+	* board/board-nitrokey-start.h (VAL_GPIO_USB_ODR)
+	(VAL_GPIO_USB_CRL): Fix the values for NeuG settings.
+
+2015-09-04  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/sys.h (BOARD_ID_NITROKEY_START): New.
+	* board/board-nitrokey-start.h (BOARD_ID): Fix the value.
+	* clk_gpio_init.c (AFIO_MAPR_SWJ_CFG_JTAGDISABLE): New.
+
+2015-08-07  Mateusz Zalega <mateusz@nitrokey.com>
+
+	* board/board-nitrokey-start.h: New.
+
+2015-08-06  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-fsm-55/README: Updated.
+
+2015-07-31  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.08.
+	* doc/chopstx.texi (VERSION): 0.08.
+
+	* example-fsm-55/Makefile (DEFS): Remove HAVE_SYS_H.
+	Add MAKE_ENTRY_PUBLIC.
+	* example-fsm-55/hacker-emblem.ld: Put vectors on ROM.
+	* example-fsm-55/sys.c: No system services.
+	* entry.c (entry): Can be public.
+	* clk_gpio_init.c (clock_init) [MCU_STM32F0]: Don't change CFGR1.
+
+2015-07-30  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-st-nucleo-f103.h: New.  Contributed by Kenji
+	Rikitake.
+
+2015-07-29  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-st-dongle.h: New.  Contributed by Kenji Rikitake.
+
+	* board/board-*.h (FLASH_PAGE_SIZE): Remove.
+
+2015-07-28  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb_stm32f103.c: Update from Gnuk.
+	* example-cdc/usb_lld.h: Ditto.
+	* example-cdc/usb-cdc.c: Follow the change.
+
+2015-07-15  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.07.
+	* doc/chopstx.texi (VERSION): 0.07.
+
+2015-07-14  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-*.h (BOARD_ID): New.
+	* example-cdc/sys.c (sys_board_id): New.
+	* example-cdc/sample.ld (.sys.board_id): New.
+	(__flash_start__, __flash_end__): Remove.
+	* entry.c (vector_table) [HAVE_SYS_H]: By undefining STM32F10X_MD,
+	prepare for high density device even compiled for MD device.
+
+2015-07-13  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* board/board-stm32-primer2.h: Update.
+	* entry.c (vector_table): Less or more.
+
+2015-07-13  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-*.h (BOARD_NAME): New.
+	(STM32F10X_MD): Define for medium-density devices.
+	* example-led/sys.c, sample.ld: Update.
+	* example-fsm-55/sys.c, hacker-emblem.ld: Update.
+	* example-cdc/sys.c (sys_board_name): New.
+	* example-cdc/sample.ld: Update.
+
+2015-07-08  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.06.
+	* doc/chopstx.texi (VERSION): 0.06.
+
+2015-07-07  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-fsm-55/sys.c: Include clk_gpio_init.c.
+	* board/board-stm32f0-discovery.h, board/board-fsm-55.h: Update.
+	* clk_gpio_init.c (gpio_init): Use VAL_GPIO_LED_*.
+
+2015-06-29  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-cq-starm.h: New for CQ STARM.
+
+	* clk_gpio_init.c (gpio_init): LED is mandatory, but USB enabler
+	is optional.
+	* board/*.h: Update.
+
+2015-06-22  Niibe Yutaka  <gniibe@fsij.org>
+
+	* clk_gpio_init.c: New, adding ports E/F/G.
+	* entry.c: Include clk_gpio.init.c if not HAVE_SYS_H.
+	* example-led/sys.c: Include clk_gpio_init.c.
+	* example-cdc/sys.c: Ditto.
+
+	* board/board-stm32-primer2.h: New from Kaz Kojima.
+
+2015-04-20  Niibe Yutaka  <gniibe@fsij.org>
+
+	Merge cortex-m0-support branch.
+
+	* VERSION: 0.05.
+
+	* example-led/sys.c (gpio_init): Support MCU_STM32F0.
+	(reset): Support __ARM_ARCH_6M__.
+	* example-led/sample.ld: Change for Cortex-M0.
+
+	* example-fsm-55/*: New example for FSM-55.
+
+	* entry.c (STM32_PPRE1, STM32_PLLSRC, STM32_FLASHBITS)
+	(STM32_PLLCLKIN): Support MCU_STM32F0.
+	(struct RCC, RCC_*): Support MCU_STM32F0.
+	(struct SYSCFG) [MCU_STM32F0]: New.
+	(struct GPIO, GPIO*): Support MCU_STM32F0.
+	(clock_init, gpio_init): Support MCU_STM32F0.
+	(hard_fault, vectors_in_ram, entry): Support Cortex-M0.
+
+	* chopstx.c (chx_cpu_sched_lock, chx_cpu_sched_unlock)
+	(sched, preempt, svc): Support Cortex-M0.
+
+	* board/board-fsm-55.h: New.
+	* board/board-stm32f0-discovery.h: New.
+
+2015-04-17  Niibe Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (CHX_PRIO_MAIN_INIT): New, removing CHX_PRIO_MAIN.
+	(chopstx_main_init): New.
+	(chx_init): Use CHX_PRIO_MAIN_INIT.
+
+2015-04-08  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-maple-mini.h: New from Aidan Thornton.
+
+2015-03-17  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.04a.
+
+2014-12-10  Niibe Yutaka  <gniibe@fsij.org>
+
+	* Version 0.04.
+	* doc/chopstx.texi (VERSION): 0.04.
+
+	* board/*.h: Updated.
+
+	* example-cdc/sys.c: Copied from example-led.
+
+	* example-led/sys.c (clock_init, GPIO_USB): Follow the change of
+	entry.c.
+	(gpio_init): Use RCC_ENR_IOP_EN and RCC_RSTR_IOP_RST.
+	(reset): Use ldr instead of mov.w and movt.
+
+	* entry.c (GPIO_USB) [GPIO_USB_BASE]: Conditionally defined.
+
+	* chopstx.c (preempt): Add ! for stm.
+	(chx_exit): Make sure RETVAL is saved onto r8.
+	(chopstx_usec_wait_var): Make sure USEC_P is saved onto r8.
+
+2013-11-27  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-stbee-mini.h: New.
+
+	* entry.c (AFIO_MAPR_SWJ_CFG_DISABLE): New.
+
+2013-11-26  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-stbee.h: New.
+
+	* rules.mk (OUTFILES) [ENABLE_OUTPUT_HEX]: Add hex generation.
+
+2013-11-21  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb_stm32f103.c, example-cdc/usb_lld.h: Update from
+	Gnuk.
+
+2013-11-08  Niibe Yutaka  <gniibe@fsij.org>
+
+	* Version 0.03.
+	* doc/chopstx.texi (VERSION): 0.03.
+
+	* chopstx.c (preempt): Disable interrupt.
+
+2013-11-08  Niibe Yutaka  <gniibe@fsij.org>
+
+	* Version 0.02.
+	* doc/chopstx.texi (VERSION): 0.02.
+
+	* example-cdc/usb_stm32f103.c: Updated from NeuG.
+
+	* chopstx.c (CPU_EXCEPTION_PRIORITY_SYSTICK): Equals to
+	CPU_EXCEPTION_PRIORITY_INTERRUPT.
+
+2013-11-03  Niibe Yutaka  <gniibe@fsij.org>
+
+	* Version 0.01.
+	* doc/chopstx.texi (VERSION): 0.01.
+
+	* chopstx.c (chx_clr_intr): New.
+	(chopstx_intr_wait): Call chopstx.c.
+	(chx_enable_intr): Let chx_clr_intr clear pending-bit.
+
+2013-11-02  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb_lld.h, example-cdc/usb_stm32f103.c: Update from
+	Gnuk.
+	* example-cdc/usb-cdc.c (usb_cb_get_descriptor): Follow the
+	change.
+
+	* example-cdc/sys.c, example-led/sys.c: Update from Gnuk.
+
+	* chopstx.c (CPU_EXCEPTION_PRIORITY_INTERRUPT)
+	(CPU_EXCEPTION_PRIORITY_PENDSV): Change the value, so that
+	interrupt priority matches USB interrupt priority of old SYS 1.0
+	implementation.
+	(chx_enable_intr, chx_disable_intr): Clear pending bit at
+	chx_enable_intr.
+	(chopstx_intr_wait): Call chx_enable_intr only when it's going to
+	sleep.
+	* entry.c (RCC_APB2RSTR_AFIORST, define RCC_APB2ENR_AFIOEN): New.
+	(AFIO, GPIO_OTHER): New.
+	(gpio_init): Handle AFIO and GPIO_OTHER.
+	* board/board-fst-01.h, board/board-stm8s-discovery.h: Add pin-cir
+	usage.
+
 2013-08-21  Niibe Yutaka  <gniibe@fsij.org>

 	* Version 0.00.
--- a/288
+++ b/288
@@ -0,0 +1,288 @@
+NEWS - Noteworthy changes
+
+
+* Major changes in Chopstx 1.3
+
+  Released 2017-02-02
+
+** New board support: Blue Pill
+It is contributed by Paul Fertser.
+
+
+* Major changes in Chopstx 1.2
+
+  Released 2016-10-13
+
+** Fix: chopstx_join
+chopstx_join is now cancellation point.
+
+
+* Major changes in Chopstx 1.1
+
+  Released 2016-07-01
+
+** API change: chopstx_poll
+In version 1.0, chopstx_poll has variable arguments.  It found that
+it's challenging for ffi or lower level C implementation, if C
+compiler is new for the specific MCU target.  Another example is that
+a program touches FPU registers for varargs, even if no argument is
+float.  So, we decided to avoid use of varargs in Chopstx.
+
+** API change: chopstx_setpriority
+In version 1.0, chopstx_setpriority does not return value.  It is
+changed to return old value of the priority.
+
+
+* Major changes in Chopstx 1.0
+
+  Released 2016-06-16
+
+** New USB API
+Now, USB driver is included in Chopstx.  So, it should be good one.
+It used to be the code which was derived from interrupt driven API
+with callbacks.  It's changed to event driven API, so that a user can
+do as wish, beyond the restriction of callbacks.
+
+** New board support: FST-01G
+FST-01G is a new revision of original FST-01 with fixed pull-up of
+D+ line.
+
+
+* Major changes in Chopstx 0.12
+
+  Released 2016-05-31
+
+** Provide drivers of SYS, USB and ADC
+Those were only offered as examples, but now, Chopstx provides drivers
+of SYS, USB, and ADC.  Please note that the ADC driver is not for
+general use (it's specific to NeuG to get noise).  To use them, enable
+variables in Makefile, like following.
+------------
+CHIP=stm32f103
+USE_ADC = yes
+USE_USB = yes
+USE_SYS = yes
+DEFS  = -DUSE_SYS3 
+------------
+
+** Removal of chopstx_usec_wait_var chopstx_wakeup_usec_wait
+This API was used when we need to wait something with timeout.
+Now, we have better API with chopstx_poll.  Please use chopstx_poll
+and chopstx_cond_signal.
+
+
+* Major changes in Chopstx 0.11
+
+  Released 2016-05-19
+
+** New feature: polling
+New function chopstx_poll is added to watch multiple condition
+variables, threads' exit, or IRQ, simultaneously with timeout.
+
+** Change API of eventflag
+The initialization function eventflag_init only has an argument of EV.
+An eventflag can be waited with timeout or can be waited with no
+timeout, as caller like.  It is not determined at initialization time
+now.  Besides, the eventflag can be waited by any threads.  Functions
+to poll eventflag together with other events (cond, join, and IRQ) are
+provided.
+
+** Removal of the function chopstx_release_irq
+IRQ is enabled only when a thread is blocked in polling.  When it (the
+thread in polling) is canceled, IRQ is disabled.
+
+** Removal of the function chopstx_main_init
+It is removed because it's too special.  Please use
+chopstx_setpriority instead.
+
+** New function: chopstx_setpriority
+This function is not recommended in general.  It is only added to
+support the usage when main thread wants to change the schedule
+priority after creating other threads.
+
+** Function chopstx_intr_wait is deprecated
+Use of chopstx_poll is recommended.
+
+** FS-BB48: Kinetis L MCU
+Support for FS-BB48 board with Kinetis L MCU is added.
+
+** No HardFault at context switch on Cortex-M0
+By its design, Chopstx does context switch holding the scheduler lock.
+This is implemented with the feature of BASEPRI on Cortex-M3.  Because
+Cortex-M0 doesn't have support of BASEPRI, the context switch (before
+version 0.11) always caused HardFault exception.  Since Cortex-M0
+doesn't have complex exception mechism of ICI/IT (which is supported
+on Cortex-M3), it is actually possible to implement the context switch
+in user mode.  This is done.
+
+** New sys.c (3.0)
+Don't touch NVIC in usb_lld_sys_init.
+
+
+* Major changes in Chopstx 0.10
+
+  Released 2015-09-15
+
+** Thread cancellation bug fix
+Thread cancellation didn't work well with 0.09 because
+of initial configuration mistake.  It's fixed.
+
+** Interrupt handler bug fix
+Interrupt handler wasn't unregistered on exit well.
+It's fixed.
+
+
+* Major changes in Chopstx 0.09
+
+  Released 2015-09-10
+
+** New board support: Nitrokey-Start
+It is contributed by Mateusz Zalega.
+
+** Thread cancellation
+Add new API: chopstx_setcancelstate.
+
+
+* Major changes in Chopstx 0.08
+
+  Released 2015-07-31
+
+** New board support: ST Nucleo F103
+It is contributed by Kenji Rikitake.
+
+** New board support: ST Dongle
+It is contributed by Kenji Rikitake.
+It's the ST-Link/V2-1 part of ST Nucleo F103.
+
+
+* Major changes in Chopstx 0.07
+
+  Released 2015-07-15
+
+** New Board macro definitions
+Each board-*.h should have BOARD_ID and BOARD_NAME now.
+FLASH_PAGE_SIZE and NEUG_ADC_SETTING2_* are deprecated.
+
+** New sys.c (2.1)
+Flash memory size is probed at runtime now.  System
+service flash pages now include sys_board_id and sys_board_name.
+
+
+* Major changes in Chopstx 0.06
+
+  Released 2015-07-08
+
+** New file: clk_gpio_init.c
+To avoid duplication of code, clock and GPIO initialization code
+is now in this file.
+
+** New board support: STM32 Primer2
+It is contributed by Kaz Kojima.
+
+** New board support: CQ STARM
+The old board which was "published" by CQ Publishing in 2008 is added.
+
+
+* Major changes in Chopstx 0.05
+
+  Released 2015-04-20, by NIIBE Yutaka
+
+** New function: chopstx_main_init
+chopstx_main_init is the function to change the schedule priority of
+main thread.  This is useful to enter main loop after initialization
+of other threads.
+
+** The use of CHX_PRIO_MAIN
+CHX_PRIO_MAIN is deprecated.  Instead, please use the function
+chopstx_main_init.
+
+** Cortex-M0 support
+Cortex-M0 support has been added.
+
+** New board support: Maple mini
+It is contributed by Aidan Thornton.
+
+** New board support: FSM-55 and STM32F0 Discovery
+Those boards with STM32F0 (Cortex-M0) are now supported.
+
+
+* Major changes in Chopstx 0.04
+
+  Released 2014-12-10, by NIIBE Yutaka
+
+** new board.h macros and sys.c in example
+In board.h, RCC_APB2ENR_IOP_EN was renamed to RCC_ENR_IOP_EN and
+RCC_APB2RSTR_IOP_RST was renamed to RCC_RSTR_IOP_RST.  Example sys.c
+was changed accordingly.
+
+** Bug fix of chopstx_wakeup_usec_wait
+chopstx_usec_wait_var/chopstx_usec_wait won't be woken up
+by chopstx_wakeup_usec_wait.  This is now fixed in 0.04.
+
+** Board support STBee and STBee Mini
+The board STBee and STBee Mini are now supported.
+
+
+* Major changes in Chopstx 0.03
+
+  Released 2013-11-08, by NIIBE Yutaka
+
+** Bug fix of preemption
+In the implementation of preemption, there was a bug which might cause
+not to schedule proper thread.  This is because the routine preepmt
+itself might be interrupted.  This is now fixed in 0.03.
+
+
+* Major changes in Chopstx 0.02
+
+  Released 2013-11-08, by NIIBE Yutaka
+
+** Bug fix of priority
+There was a severe bug about the configuraion of priority setting of
+exceptions.  As we don't use any inter-lock between interrupts hander
+and timer expiration handler, these priorities should be equal.  If
+not, timer expiration handler might interrupt the execution of
+interrupts handers.
+
+
+* Major changes in Chopstx 0.01
+
+  Released 2013-11-03, by NIIBE Yutaka
+
+** Interrupt handling change
+There was a bug in 0.00, which caused spurious interrupts.  Every
+interrupt event caused two events.  Specifically, after valid
+interrupt event (for the caller of chopstx_intr_wait), another
+spurious event was always occurred.  This was fixed.
+
+In the design of Chopstx, interrupt handling is done by a thread.
+Lower level interrupt handler just accepts interrupt, disabling the
+interrupt, and switchs the control to the thread.  It is the thread to
+check the cause of interrupt, to process it, and to clear the cause.
+Next call to chopstx_intr_wait will enable the interrupt again.
+
+The bug was related to pending interrupt flag.  Pending interrupt flag
+for a specific interrupt is set, on return from handler mode if the
+cause is still active.  With traditional interrupt handling, lower
+level interrupt handler processes it and clears the cause.  Thus,
+pending interrupt flag is not set on return.
+
+In Chopstx, pending interrupt flag was always set, because the control
+goes from lower level interrupt handler (in handler mode) to a
+interrupt handling thread which processes the interrupt.  In 0.01, new
+internal routine chx_clr_intr is introduced, and pending interrupt
+flag is cleared within chopstx_intr_wait after waked up.
+
+For detail of interrupt operation, see the section B.3.4, Nested
+Vectored Interrupt Controller (NVIC), in the ARM v7-M Architecture
+Reference Manual.  The subsection, B3.4.1, Theory of operation,
+explains how it works.
+
+
+** gpio_init change
+Now, gpi_init support AFIO mapping and another GPIO (GPIO_OTHER)
+settings.
+
+Local Variables:
+mode: outline
+End:
--- a/33
+++ b/33
@@ -1,17 +1,17 @@
 Chopstx - Threads and only Threads
-							Version 0.00
-							  2013-08-21
+							 Version 1.3
+							  2017-02-02
 							Niibe Yutaka
 					     Flying Stone Technology

 What's Chopstx?
 ===============

-Chopstx is an RT thread library for ARM Cortex-M3, specifically,
-STM32F103.
+Chopstx is an RT thread library for STM32F103 (ARM Cortex-M3),
+STM32F030 (ARM Cortex-M0), and MKL27Z (ARM Cortex-M0plus).

 While most RTOSes come with many features, drivers, and stacks,
-Chopstx just offers a RT thread library.
+Chopstx just offers a simple RT thread library.

 With Chopstx, interrupt handling is also done by a thread.  This
 enables coherent code for ease of maintenance.
@@ -28,11 +28,28 @@ EXCEPTION.
 Example code
 ============

-We have two examples in this distribution, LED blinker and
-USB CDC-ACM function.  You can build it like:
+We have some examples in this distribution; Useful ones are LED
+blinker and USB CDC-ACM function.  For STM32F103, you can build it
+USB CDC-ACM demo by:

   $ cd example-cdc
-   $ ln -s ../board/board-olimex-stm32-h103.h board.h
+   $ ln -sf ../board/board-olimex-stm32-h103.h board.h
   $ make

+For a specific board named FSM-55, an example of LED matrix dynamic
+driver is provided.  See the directory: example-fsm-55.
+
+For STM32 Primer2, see the directory: example-primer2.
+
+
+Future Works
+============
+
+Convenience function to determine the bottom of thread stack,
+configuration of thread size by comiler's output would be next things
+to be done.
+
+Experimental SMP port for Cortex-A7 is under development.  For SMP,
+more careful considerations for shared access to objects of struct
+chx_pq is needed.  So, modifications required will not be small.
 -- 
--- a/1
+++ b/1
@@ -0,0 +1 @@
+release/1.3
--- a/adc.h
+++ b/adc.h
@@ -0,0 +1,8 @@
+int adc_init (void);
+void adc_start (void);
+void adc_stop (void);
+
+extern uint32_t adc_buf[64];
+
+void adc_start_conversion (int offset, int count);
+int adc_wait_completion (void);
--- a/board/board-blue-pill.h
+++ b/board/board-blue-pill.h
@@ -0,0 +1,36 @@
+#define BOARD_NAME "Blue Pill"
+/* http://wiki.stm32duino.com/index.php?title=Blue_Pill */
+/* echo -n "Blue Pill" | shasum -a 256 | sed -e 's/^.*\(........\)  -$/\1/' */
+#define BOARD_ID    0xa1099d43
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOC_BASE
+#define GPIO_LED_CLEAR_TO_EMIT          13
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          12
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ * PCx  - input with pull-up
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFE7FF
+#define VAL_GPIO_USB_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x88811888      /* PA15...PA8 */
+
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x88388888      /* PC15...PC8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPCRST)
--- a/board/board-cq-starm.h
+++ b/board/board-cq-starm.h
@@ -0,0 +1,46 @@
+#define BOARD_NAME "CQ STARM"
+#define BOARD_ID    0xc5480875
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOC_BASE
+#define GPIO_LED_SET_TO_EMIT            6
+#undef  GPIO_USB_BASE		/* No external DISCONNECT/RENUM circuit.  */
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up.  AN0
+ * PA1  - input with pull-up.  AN1
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ */
+#define VAL_GPIO_OTHER_ODR            0xFFFFE7FF
+#define VAL_GPIO_OTHER_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_OTHER_CRH            0x88811888      /* PA15...PA8 */
+
+/*
+ * Port C setup.
+ * PC0  - Push Pull output 50MHz.
+ * PC1  - Push Pull output 50MHz.
+ * Everything input with pull-up except:
+ * PC4  - Normal input      (ADC_IN14 : VoutY of LIS344ALH).
+ * PC5  - Normal input      (ADC_IN15 : VoutZ of LIS344ALH).
+ * PC6  - Push Pull output (LED).
+ * (PC9  - SDCard CD)
+ * (PC12 - SDCard CS)
+ * PC14 - Normal input (XTAL).
+ * PC15 - Normal input (XTAL).
+ */
+#define VAL_GPIO_LED_CRL            0x83448833      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x44888888      /* PC15...PC8 */
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPCEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPCRST)
--- a/board/board-fs-bb48.h
+++ b/board/board-fs-bb48.h
@@ -0,0 +1,5 @@
+#define BOARD_NAME "FS-BB48"
+#define BOARD_ID    0xd1f5119c
+/* echo -n "FST-01" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
+
+#define MCU_KINETIS_L      1
--- a/board/board-fsm-55.h
+++ b/board/board-fsm-55.h
@@ -0,0 +1,42 @@
+#define BOARD_NAME "FSM-55"
+#define BOARD_ID    0x83433c76
+
+/*
+ * Running at 48MHz with HSI as clock source.
+ * 
+ */
+#define MCU_STM32F0 1
+/* __ARM_ARCH_6M__ */
+
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              12
+#define STM32_HSICLK                    8000000
+
+#define GPIO_LED_BASE           GPIOA_BASE
+#define GPIO_LED_SET_TO_EMIT    5
+#define GPIO_OTHER_BASE         GPIOF_BASE /* USER BUTTON */
+
+/*
+ * Port A setup.
+ * PA5  - ON (LED 1:ON 0:OFF)
+ * PA4  - Pull DOWN
+ */
+#define VAL_GPIO_LED_MODER   0x00145555 /* Output Pin0-7, Pin9 and Pin10 */
+#define VAL_GPIO_LED_OTYPER  0x0000001f /* Open-drain for Pin0-4, Push-Pull*/
+#define VAL_GPIO_LED_OSPEEDR 0x003cffff /* High speed */
+#define VAL_GPIO_LED_PUPDR   0x00000000 /* No pull-up/pull-down */
+
+
+#define RCC_ENR_IOP_EN   (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPFEN)
+#define RCC_RSTR_IOP_RST (RCC_AHBRSTR_IOPARST | RCC_AHBRSTR_IOPFRST)
+
+/*
+ * Port F setup.
+ * PF0  - USER Button
+ * PF1  - SPEAKER
+ */
+#define VAL_GPIO_OTHER_MODER   0x00000004 /* Input Pin0, Output Pin1 */
+#define VAL_GPIO_OTHER_OTYPER  0x00000000 /* Push-Pull Pin1 */
+#define VAL_GPIO_OTHER_OSPEEDR 0x00000000
+#define VAL_GPIO_OTHER_PUPDR   0x00000009 /* Pull-up Pin0, Pull-down Pin1 */
--- a/board/board-fst-01-00.h
+++ b/board/board-fst-01-00.h
@@ -1,11 +1,17 @@
-#define FLASH_PAGE_SIZE 1024
+#define BOARD_NAME "FST-01-00"
+#define BOARD_ID    0x613870a9
+
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              9
 #define STM32_HSECLK                    8000000

-#define GPIO_USB_SET_TO_ENABLE		10
+#define GPIO_LED_BASE   GPIOA_BASE
 #define GPIO_LED_SET_TO_EMIT            8
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          10
+#undef  GPIO_OTHER_BASE

 /*
 * Port A setup.
@@ -18,14 +24,9 @@
 * ------------------------ Default
 * PAx  - input with pull-up
 */
-#define VAL_GPIO_ODR            0xFFFFE7FF
-#define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
-#define VAL_GPIO_CRH            0x88811383      /* PA15...PA8 */
+#define VAL_GPIO_LED_ODR            0xFFFFE7FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88811383      /* PA15...PA8 */

-#define GPIO_USB_BASE	GPIOA_BASE
-#define GPIO_LED_BASE	GPIOA_BASE
-
-#define RCC_APB2ENR_IOP_EN	RCC_APB2ENR_IOPAEN
-#define RCC_APB2RSTR_IOP_RST	RCC_APB2RSTR_IOPARST
-
-/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
--- a/board/board-fst-01.h
+++ b/board/board-fst-01.h
@@ -1,11 +1,18 @@
-#define FLASH_PAGE_SIZE 1024
+#define BOARD_NAME "FST-01"
+#define BOARD_ID    0x696886af
+/* echo -n "FST-01" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
+
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              6
 #define STM32_HSECLK                    12000000

-#define GPIO_USB_SET_TO_ENABLE		10
+#define GPIO_LED_BASE   GPIOB_BASE
 #define GPIO_LED_SET_TO_EMIT            0
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          10
+#undef  GPIO_OTHER_BASE

 /*
 * Port A setup.
@@ -27,9 +34,9 @@
 * PA14 - input with pull-up.
 * PA15 - input with pull-up.
 */
-#define VAL_GPIO_ODR            0xFFFFE7FD
-#define VAL_GPIO_CRL            0xBBB38888      /*  PA7...PA0 */
-#define VAL_GPIO_CRH            0x88811388      /* PA15...PA8 */
+#define VAL_GPIO_USB_ODR            0xFFFFE7FD
+#define VAL_GPIO_USB_CRL            0xBBB38888      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x88811388      /* PA15...PA8 */

 /*
 * Port B setup.
@@ -42,16 +49,36 @@
 #define VAL_GPIO_LED_CRL            0x88888883      /*  PA7...PA0 */
 #define VAL_GPIO_LED_CRH            0x88888888      /* PA15...PA8 */

-#define GPIO_USB_BASE	GPIOA_BASE
-#define GPIO_LED_BASE	GPIOB_BASE
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)

-#define RCC_APB2ENR_IOP_EN	(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
-#define RCC_APB2RSTR_IOP_RST	(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
-
-/* NeuG settings for ADC2.  */
-#define NEUG_ADC_SETTING2_SMPR1 0
-#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)    \
-                              | ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5)
-#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)      \
-                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9)
-#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
+/*
+ * Board specific information other than clock and GPIO initial
+ * setting should not be in board-*.h, but each driver should include
+ * information by itself.
+ *
+ * Please see NeuG's ADC driver how board specific handling is done.
+ *
+ * Given the situation of Chopstx's boards support, which is not that
+ * huge, this works well.  If scalability and flexibility will matter,
+ * we will need something like device tree in which boot process can
+ * pass information to application program.
+ *
+ * Following constants are here, because experimental CIR driver is
+ * written before this design decision of Chopstx.
+ *
+ * Those will be removed soon, once such an driver will be improved
+ * in new style.
+ */
+/* For pin-cir settings of Gnuk */
+#define TIMx                  TIM2
+#define INTR_REQ_TIM          TIM2_IRQ
+#define AFIO_EXTICR_INDEX     0
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA
+#define EXTI_PR               EXTI_PR_PR2
+#define EXTI_IMR              EXTI_IMR_MR2
+#define EXTI_FTSR_TR          EXTI_FTSR_TR2
+#define INTR_REQ_EXTI         EXTI2_IRQ
+#define ENABLE_RCC_APB1
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM2EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM2RST
--- a/board/board-fst-01g.h
+++ b/board/board-fst-01g.h
@@ -0,0 +1,84 @@
+#define BOARD_NAME "FST-01G"
+#define BOARD_ID    0x8801277f
+/* echo -n "FST-01G" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
+
+#define GPIO_LED_BASE   GPIOB_BASE
+#define GPIO_LED_SET_TO_EMIT            0
+#define GPIO_USB_BASE   GPIOA_BASE
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up (TIM2_CH1): AN0 for NeuG
+ * PA1  - input with pull-down (TIM2_CH2)
+ * PA2  - input with pull-up (TIM2_CH3) connected to CIR module
+ * PA3  - input with pull-up: external pin available to user
+ * PA4  - Push pull output           (SPI1_NSS)
+ * PA5  - Alternate Push pull output (SPI1_SCK)
+ * PA6  - Alternate Push pull output (SPI1_MISO)
+ * PA7  - Alternate Push pull output (SPI1_MOSI)
+ * PA10 - Push pull output 1 default
+ *        (so that binary for FST-01G also works on FST-01)
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PA8  - input with pull-up.
+ * PA9  - input with pull-up.
+ * PA13 - input with pull-up.
+ * PA14 - input with pull-up.
+ * PA15 - input with pull-up.
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFE7FD
+#define VAL_GPIO_USB_CRL            0xBBB38888      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x88811388      /* PA15...PA8 */
+
+/*
+ * Port B setup.
+ * PB0  - Push pull output   (LED 1:ON 0:OFF)
+ * PB1  - input with pull-up: AN9 for NeuG
+ * ------------------------ Default
+ * PBx  - input with pull-up.
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888883      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88888888      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
+
+/*
+ * Board specific information other than clock and GPIO initial
+ * setting should not be in board-*.h, but each driver should include
+ * information by itself.
+ *
+ * Please see NeuG's ADC driver how board specific handling is done.
+ *
+ * Given the situation of Chopstx's boards support, which is not that
+ * huge, this works well.  If scalability and flexibility will matter,
+ * we will need something like device tree in which boot process can
+ * pass information to application program.
+ *
+ * Following constants are here, because experimental CIR driver is
+ * written before this design decision of Chopstx.
+ *
+ * Those will be removed soon, once such an driver will be improved
+ * in new style.
+ */
+/* For pin-cir settings of Gnuk */
+#define TIMx                  TIM2
+#define INTR_REQ_TIM          TIM2_IRQ
+#define AFIO_EXTICR_INDEX     0
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA
+#define EXTI_PR               EXTI_PR_PR2
+#define EXTI_IMR              EXTI_IMR_MR2
+#define EXTI_FTSR_TR          EXTI_FTSR_TR2
+#define INTR_REQ_EXTI         EXTI2_IRQ
+#define ENABLE_RCC_APB1
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM2EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM2RST
--- a/board/board-maple-mini.h
+++ b/board/board-maple-mini.h
@@ -0,0 +1,41 @@
+#define BOARD_NAME "Maple Mini"
+#define BOARD_ID    0x7a445272
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOB_BASE
+#define GPIO_LED_SET_TO_EMIT            1
+#define GPIO_USB_BASE   GPIOB_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE        9
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up.  AN0
+ * PA1  - input with pull-up.  AN1
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ */
+#define VAL_GPIO_OTHER_ODR            0xFFFFE7FF
+#define VAL_GPIO_OTHER_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_OTHER_CRH            0x88811888      /* PA15...PA8 */
+
+/*
+ * Port B setup.
+ * PB1  - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * PB9  - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * ------------------------ Default
+ * PBx  - input with pull-up
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888838      /*  PB7...PB0 */
+#define VAL_GPIO_LED_CRH            0x88888838      /* PB15...PB8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
--- a/board/board-nitrokey-start.h
+++ b/board/board-nitrokey-start.h
@@ -0,0 +1,59 @@
+#define BOARD_NAME "NITROKEY-START"
+#define BOARD_ID    0xad1e7ebd
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
+
+#define GPIO_LED_BASE   GPIOB_BASE
+#define GPIO_LED_SET_TO_EMIT            0
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          15
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA0 - input with pull-up: AN0 for NeuG
+ * PA1 - input with pull-up: AN1 for NeuG
+ * PA2 - floating input
+ * PA3 - floating input
+ * PA4 - floating input
+ * PA5 - floating input
+ * PA6 - floating input
+ * PA7 - Push pull output   (Red LED1 1:ON 0:OFF)
+ * PA8 - floating input (smartcard, SCDSA)
+ * PA9 - floating input
+ * PA10 - floating input
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * PA15 - Push pull output  (USB_EN 1:ON 0:OFF)
+ * ------------------------ Default
+ * PA8  - input with pull-up.
+ * PA9  - floating input.
+ * PA10 - floating input.
+ * PA13 - input with pull-up.
+ * PA14 - input with pull-up.
+ * PA15 - Push pull output   (USB 1:ON 0:OFF)
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFE77F
+#define VAL_GPIO_USB_CRL            0x34444488      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x38811444      /* PA15...PA8 */
+
+/*
+ * Port B setup.
+ * PB0  - Push pull output   (Green LED2 1:ON 0:OFF)
+ * ------------------------ Default
+ * PBx  - input with pull-up.
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888883      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88888888      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      \
+	(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
+#define RCC_RSTR_IOP_RST    \
+	(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)
+
+#define AFIO_MAPR_SOMETHING   AFIO_MAPR_SWJ_CFG_JTAGDISABLE
--- a/board/board-olimex-stm32-h103.h
+++ b/board/board-olimex-stm32-h103.h
@@ -1,11 +1,17 @@
-#define FLASH_PAGE_SIZE 1024
+#define BOARD_NAME "Olimex STM32-H103"
+#define BOARD_ID    0xf92bb594
+
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              9
 #define STM32_HSECLK                    8000000

-#define GPIO_USB_CLEAR_TO_ENABLE	11
+#define GPIO_LED_BASE   GPIOC_BASE
 #define GPIO_LED_CLEAR_TO_EMIT          12
+#define GPIO_USB_BASE   GPIOC_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE        11
+#undef  GPIO_OTHER_BASE

 /*
 * Port C setup.
@@ -18,15 +24,12 @@
 * ------------------------ Default
 * PCx  - input with pull-up
 */
-#define VAL_GPIO_ODR            0xFFFFFFFF
-#define VAL_GPIO_CRL            0x44888888      /*  PC7...PC0 */
-#define VAL_GPIO_CRH            0x88837888      /* PC15...PC8 */
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x44888888      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x88837888      /* PC15...PC8 */

-#define GPIO_USB_BASE	GPIOC_BASE
-#define GPIO_LED_BASE	GPIOC_BASE
-
-#define RCC_APB2ENR_IOP_EN	RCC_APB2ENR_IOPCEN
-#define RCC_APB2RSTR_IOP_RST	RCC_APB2RSTR_IOPCRST
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPCEN
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPCRST

 /* NeuG settings for ADC2.  */
 #define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \
--- a/board/board-st-dongle.h
+++ b/board/board-st-dongle.h
@@ -0,0 +1,33 @@
+#define BOARD_NAME "ST Dongle"
+/* echo -n "ST Dongle" | shasum -a 256 | sed -e 's/^.*\(........\)  -$/\1/' */
+#define BOARD_ID    0x2cd4e471
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOA_BASE
+#define GPIO_LED_SET_TO_EMIT            9
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          15
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up.  AN0
+ * PA1  - input with pull-up.  AN1
+ * PA9  - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * PA15 - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFE7FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x38811838      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
--- a/board/board-st-nucleo-f103.h
+++ b/board/board-st-nucleo-f103.h
@@ -0,0 +1,45 @@
+#define BOARD_NAME "ST Nucleo F103"
+#define BOARD_ID    0x9b87c16d
+
+/*
+ * Please add X3 and USB cable to ST Nucleo F103.
+ *
+ * Solder X3 XTAL of 8MHz (and put C33 and C34 of 22pF).  
+ * Solder the bridges for R35 and R37, since it's 0 ohm. 
+ *
+ * (Optional) Remove SB54 and SB55.
+ *
+ * At CN10, connect USB cable
+ *  Vbus RED   --> 10 NC   ----------> CN7 (6 E5V)
+ *  D+   GREEN --> 12 PA11 ---[1K5]--> CN6 (4 3V3)
+ *  D-   WHITE --> 14 PA12
+ *  GND  BLACK --> 20 GND
+ */
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOA_BASE
+#define GPIO_LED_SET_TO_EMIT            5
+#undef  GPIO_USB_BASE		/* No external DISCONNECT/RENUM circuit.  */
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up.  AN0
+ * PA1  - input with pull-up.  AN1
+ * PA5  - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFE7FF
+#define VAL_GPIO_LED_CRL            0x88388888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88811888      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
--- a/board/board-stbee-mini.h
+++ b/board/board-stbee-mini.h
@@ -0,0 +1,113 @@
+#define BOARD_NAME "STBee Mini"
+#define BOARD_ID    0x1f341961
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
+
+#define GPIO_LED_BASE           GPIOA_BASE
+#define GPIO_LED_CLEAR_TO_EMIT          13
+#define GPIO_USB_BASE           GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          14
+
+#if defined(PINPAD_CIR_SUPPORT) || defined(PINPAD_DIAL_SUPPORT)
+#define HAVE_7SEGLED	1
+/*
+ * Timer assignment for CIR
+ */
+#define TIMx                  TIM3
+#define INTR_REQ_TIM          TIM3_IRQ
+#define AFIO_EXTICR_INDEX     0
+#endif
+
+#if defined(PINPAD_CIR_SUPPORT)
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI0_PB
+#define EXTI_PR               EXTI_PR_PR0
+#define EXTI_IMR              EXTI_IMR_MR0
+#define EXTI_FTSR_TR          EXTI_FTSR_TR0
+#define INTR_REQ_EXTI         EXTI0_IRQ
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM3EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM3RST
+#elif defined(PINPAD_DIAL_SUPPORT)
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PB
+#define EXTI_PR               EXTI_PR_PR2
+#define EXTI_IMR              EXTI_IMR_MR2
+#define EXTI_FTSR_TR          EXTI_FTSR_TR2
+#define INTR_REQ_EXTI         EXTI2_IRQ
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM4EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM4RST
+#endif
+#define ENABLE_RCC_APB1
+
+#if defined(PINPAD_CIR_SUPPORT) || defined(PINPAD_DIAL_SUPPORT)
+/*
+ * Port A setup.
+ * PA1  - Digital input with PullUp.  AN1 for NeuG
+ * PA2  - Digital input with PullUp.  AN2 for NeuG
+ * PA6  - (TIM3_CH1) input with pull-up
+ * PA7  - (TIM3_CH2) input with pull-down
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * PA13 - Open Drain output (LED1 0:ON 1:OFF)
+ * PA14 - Push pull output  (USB ENABLE 0:DISABLE 1:ENABLE)
+ * PA15 - Open Drain output (LED2 0:ON 1:OFF)
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFE77F
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x63611888      /* PA15...PA8 */
+
+#define GPIO_OTHER_BASE          GPIOB_BASE
+/*
+ * Port B setup.
+ * PB0  - Push pull output   (LED 1:ON 0:OFF)
+ * ------------------------ Default
+ * PBx  - input with pull-up.
+ */
+#define VAL_GPIO_OTHER_ODR            0xFFFFFFFF
+#define VAL_GPIO_OTHER_CRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIO_OTHER_CRH            0x66666666      /* PB15...PB8 */
+
+/* Port B setup. */
+#define GPIOB_CIR               0
+#define GPIOB_BUTTON            2
+#define GPIOB_ROT_A             6
+#define GPIOB_ROT_B             7
+
+#define GPIOB_7SEG_DP           15
+#define GPIOB_7SEG_A            14
+#define GPIOB_7SEG_B            13
+#define GPIOB_7SEG_C            12
+#define GPIOB_7SEG_D            11
+#define GPIOB_7SEG_E            10
+#define GPIOB_7SEG_F            9
+#define GPIOB_7SEG_G            8
+
+#define RCC_ENR_IOP_EN      \
+        (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
+#define RCC_RSTR_IOP_RST    \
+        (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)
+#else
+/*
+ * Port A setup.
+ * PA1  - Digital input with PullUp.  AN1 for NeuG
+ * PA2  - Digital input with PullUp.  AN2 for NeuG
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * PA13 - Open Drain output (LED1 0:ON 1:OFF)
+ * PA14 - Push pull output  (USB ENABLE 0:DISABLE 1:ENABLE)
+ * PA15 - Open Drain output (LED2 0:ON 1:OFF)
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFE7FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x63611888      /* PA15...PA8 */
+
+#undef  GPIO_OTHER_BASE
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_AFIORST)
+#endif
+
+
+#define AFIO_MAPR_SOMETHING     AFIO_MAPR_SWJ_CFG_DISABLE
--- a/board/board-stbee.h
+++ b/board/board-stbee.h
@@ -0,0 +1,34 @@
+#define BOARD_NAME "STBee"
+#define BOARD_ID    0x945c37e8
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
+
+#define GPIO_LED_BASE   GPIOD_BASE
+#define GPIO_LED_CLEAR_TO_EMIT          4
+#define GPIO_USB_BASE   GPIOD_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE        3
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/*
+ * Port A setup.
+ * PA0  - Normal input.
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ */
+#define VAL_GPIO_OTHER_ODR      0xFFFFE7FF
+#define VAL_GPIO_OTHER_CRL      0x88888884      /*  PA7...PA0 */
+#define VAL_GPIO_OTHER_CRH      0x88811888      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPDEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPDRST)
+
+/*
+ * Port D setup.
+ * PD3  - Push pull output  (USB_DISC 1:USB-DISABLE 0:USB-ENABLE) 2MHz
+ * PD4  - Open Drain output 2MHz (LED1).
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88862888      /*  PD7...PD0 */
+#define VAL_GPIO_LED_CRH            0x88888888      /* PD15...PD8 */
--- a/board/board-stm32-primer2.h
+++ b/board/board-stm32-primer2.h
@@ -0,0 +1,56 @@
+#define BOARD_NAME "STM32 Primer2"
+#define BOARD_ID    0x21e5798d
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
+
+#define GPIO_LED_BASE   GPIOE_BASE
+#define GPIO_LED_SET_TO_EMIT            0
+#define GPIO_USB_BASE   GPIOD_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE        3
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up.  AN0
+ * PA1  - input with pull-up.  AN1
+ * PA8  - Input with pull-down (PBUTTON).
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ */
+#define VAL_GPIO_OTHER_ODR            0xFFFFE6FF
+#define VAL_GPIO_OTHER_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_OTHER_CRH            0x88811888      /* PA15...PA8 */
+
+/*
+ * Port D setup.
+ * PD3  - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * ------------------------ Default
+ * PDx  - input with pull-up
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFFFFF
+#define VAL_GPIO_USB_CRL            0x88883888      /*  PD7...PD0 */
+#define VAL_GPIO_USB_CRH            0x88888888      /* PD15...PD8 */
+
+/*
+ * Port E setup.
+ * PE0  - Push pull output   (LED 1:ON 0:OFF)
+ * PE1  - Push pull output   (LED 1:ON 0:OFF)
+ * PE3  - Input with pull-down (JOYSTICK L).
+ * PE4  - Input with pull-down (JOYSTICK R).
+ * PE5  - Input with pull-down (JOYSTICK U).
+ * PE6  - Input with pull-down (JOYSTICK D).
+ * ------------------------ Default
+ * PEx  - input with pull-up
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFFF87
+#define VAL_GPIO_LED_CRL            0x88888833      /*  PE7...PE0 */
+#define VAL_GPIO_LED_CRH            0x88888888      /* PE15...PE8 */
+
+#define RCC_ENR_IOP_EN \
+	(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_IOPEEN)
+#define RCC_RSTR_IOP_RST \
+	(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPDRST | RCC_APB2RSTR_IOPERST)
--- a/board/board-stm32f0-discovery.h
+++ b/board/board-stm32f0-discovery.h
@@ -0,0 +1,50 @@
+#define BOARD_NAME "STM32F0 Discovery"
+#define BOARD_ID    0xde4b4bc1
+
+#define MCU_STM32F0 1
+
+/*
+ * Running at 48MHz with HSI as clock source.
+ * 
+ */
+#define MCU_STM32F0 1
+/* __ARM_ARCH_6M__ */
+
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              12
+#define STM32_HSICLK                    8000000
+
+#define GPIO_LED_BASE           GPIOC_BASE
+#define GPIO_LED_SET_TO_EMIT    8
+#define GPIO_OTHER_BASE         GPIOA_BASE /* USER BUTTON */
+
+/*
+ * Port C setup.
+ * PC9  - LED3 (LED 1:ON 0:OFF)
+ * PC8  - LED4 (LED 1:ON 0:OFF)
+ */
+#define VAL_GPIO_LED_MODER   0x00050000 /* Output Pin9 and Pin8 */
+#define VAL_GPIO_LED_OTYPER  0x00000000 /* Push-Pull */
+#define VAL_GPIO_LED_OSPEEDR 0x000f0000 /* High speed: Pin9 and Pin8 */
+#define VAL_GPIO_LED_PUPDR   0x00000000 /* No pull-up/pull-down */
+
+
+#if 0
+#define RCC_ENR_IOP_EN   (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPCEN)
+#define RCC_RSTR_IOP_RST (RCC_AHBRSTR_IOPARST | RCC_AHBRSTR_IOPCRST)
+#else
+#define RCC_ENR_IOP_EN   RCC_AHBENR_IOPCEN
+#define RCC_RSTR_IOP_RST RCC_AHBRSTR_IOPCRST
+#endif
+
+/* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */
+
+/*
+ * Port A setup.
+ * PA0  - USER Button
+ */
+#define VAL_GPIO_OTHER_MODER   0x00000000 /* Input Pin0 */
+#define VAL_GPIO_OTHER_OTYPER  0x00000000 /* Push-Pull */
+#define VAL_GPIO_OTHER_OSPEEDR 0x00000000
+#define VAL_GPIO_OTHER_PUPDR   0x00000000 /* No pull-up/pull-down */
--- a/board/board-stm8s-discovery.h
+++ b/board/board-stm8s-discovery.h
@@ -1,11 +1,16 @@
-#define FLASH_PAGE_SIZE 1024
+#define BOARD_NAME "STM8S Discovery"
+#define BOARD_ID    0x2f0976bb
+
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              9
 #define STM32_HSECLK                    8000000

-#undef  GPIO_USB_CLEAR_TO_ENABLE
+#define GPIO_LED_BASE   GPIOA_BASE
 #define GPIO_LED_SET_TO_EMIT            8
+#undef  GPIO_USB_BASE		/* No external DISCONNECT/RENUM circuit.  */
+#define GPIO_OTHER_BASE GPIOB_BASE

 /*
 * Port A setup.
@@ -17,14 +22,38 @@
 * ------------------------ Default
 * PAx  - input with pull-up
 */
-#define VAL_GPIO_ODR            0xFFFFE7FF
-#define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
-#define VAL_GPIO_CRH            0x88811881      /* PA15...PA8 */
+#define VAL_GPIO_LED_ODR            0xFFFFE7FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88811881      /* PA15...PA8 */

-#define GPIO_USB_BASE	GPIOA_BASE
-#define GPIO_LED_BASE	GPIOA_BASE
+#define RCC_ENR_IOP_EN   \
+  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
+#define RCC_RSTR_IOP_RST \
+  (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)

-#define RCC_APB2ENR_IOP_EN	(RCC_APB2ENR_IOPAEN)
-#define RCC_APB2RSTR_IOP_RST	(RCC_APB2RSTR_IOPARST)
+/*
+ * Port B setup.
+ * PB4  - (TIM3_CH1) input with pull-up
+ * PB5  - (TIM3_CH2) input with pull-up, connected to CIR module
+ * Everything input with pull-up except:
+ * PB0  - (TIM3_CH3) input with pull-down
+ */
+#define VAL_GPIO_OTHER_ODR 0xFFFFFFFE
+#define VAL_GPIO_OTHER_CRL 0x88888888      /*  PB7...PB0 */
+#define VAL_GPIO_OTHER_CRH 0x88888888      /* PB15...PB8 */

-/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */
+
+/* For pin-cir settings of Gnuk */
+#define TIMx                  TIM3
+#define INTR_REQ_TIM          TIM3_IRQ
+#define AFIO_EXTICR_INDEX     1
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR2_EXTI5_PB
+#define EXTI_PR               EXTI_PR_PR5
+#define EXTI_IMR              EXTI_IMR_MR5
+#define EXTI_FTSR_TR          EXTI_FTSR_TR5
+#define INTR_REQ_EXTI         EXTI9_5_IRQ
+#define ENABLE_RCC_APB1
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM3EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM3RST
+#define AFIO_MAPR_SOMETHING   AFIO_MAPR_TIM3_REMAP_PARTIALREMAP
+                              /* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */
--- a/chopstx.c
+++ b/chopstx.c
--- a/chopstx.h
+++ b/chopstx.h
@@ -1,7 +1,7 @@
 /*
 * chopstx.h - Threads and only threads.
 *
- * Copyright (C) 2013 Flying Stone Technology
+ * Copyright (C) 2013, 2016 Flying Stone Technology
 * Author: NIIBE Yutaka <gniibe@fsij.org>
 *
 * This file is a part of Chopstx, a thread library for embedded.
@@ -26,11 +26,16 @@
 *
 */

+struct chx_qh {
+  struct chx_pq *next, *prev;
+};
+
 typedef uint32_t chopstx_t;
 typedef uint8_t chopstx_prio_t;

 extern chopstx_t chopstx_main;

+
 /* NOTE: This signature is different to PTHREAD's one.  */
 chopstx_t
 chopstx_create (uint32_t flags_and_prio,
@@ -42,8 +47,6 @@ chopstx_create (uint32_t flags_and_prio,

 #define CHOPSTX_PRIO_INHIBIT_PREEMPTION 248

-void chopstx_usec_wait_var (uint32_t *arg);
-
 void chopstx_usec_wait (uint32_t usec);

 struct chx_spinlock {
@@ -51,9 +54,7 @@ struct chx_spinlock {
 };

 typedef struct chx_mtx {
-  struct {
-    struct chx_thread *next, *prev;
-  } q;
+  struct chx_qh q;
  struct chx_spinlock lock;
  struct chx_thread *owner;
  struct chx_mtx *list;
@@ -67,9 +68,7 @@ void chopstx_mutex_lock (chopstx_mutex_t *mutex);
 void chopstx_mutex_unlock (chopstx_mutex_t *mutex);

 typedef struct chx_cond {
-  struct {
-    struct chx_thread *next, *prev;
-  } q;
+  struct chx_qh q;
  struct chx_spinlock lock;
 } chopstx_cond_t;

@@ -80,26 +79,13 @@ void chopstx_cond_wait (chopstx_cond_t *cond, chopstx_mutex_t *mutex);
 void chopstx_cond_signal (chopstx_cond_t *cond);
 void chopstx_cond_broadcast (chopstx_cond_t *cond);

-typedef struct chx_intr {
-  struct chx_intr *next;
-  struct chx_spinlock lock;
-  struct chx_thread *tp;
-  uint32_t ready;
-  uint8_t irq_num;
-} chopstx_intr_t;
-
-void chopstx_claim_irq (chopstx_intr_t *intr, uint8_t irq_num);
-void chopstx_release_irq (chopstx_intr_t *intr);
-
-void chopstx_intr_wait (chopstx_intr_t *intr);
-
 /*
 * Library provides default implementation as weak reference.
 * User can replace it.
  */
-void chx_fatal (uint32_t err_code) __attribute__((__weak__, __noreturn__));
+void chx_fatal (uint32_t err_code) __attribute__((__noreturn__));

-void chopstx_join (chopstx_t, void **);
+int chopstx_join (chopstx_t, void **);
 void chopstx_exit (void *retval) __attribute__((__noreturn__));


@@ -109,26 +95,69 @@ enum {
  CHOPSTX_ERR_JOIN,
 };

-enum {
-  CHOPSTX_EXIT_SUCCESS = 0,
-  CHOPSTX_EXIT_CANCELED         = 256,
-  CHOPSTX_EXIT_CANCELED_IN_SYNC = 257,
-};
+#define CHOPSTX_CANCELED ((void *) -1)

 void chopstx_cancel (chopstx_t thd);
 void chopstx_testcancel (void);

-struct chx_cleanup {
+/* NOTE: This signature is different to PTHREAD's one.  */
+int chopstx_setcancelstate (int);
+
+typedef struct chx_cleanup {
  struct chx_cleanup *next;
  void (*routine) (void *);
  void *arg;
-};
+} chopstx_cleanup_t;

 /* NOTE: This signature is different to PTHREAD's one.  */
-void chopstx_cleanup_push (struct chx_cleanup *clp);
+void chopstx_cleanup_push (chopstx_cleanup_t *clp);
 void chopstx_cleanup_pop (int execute);

+chopstx_prio_t chopstx_setpriority (chopstx_prio_t);

-void chopstx_wakeup_usec_wait (chopstx_t thd);
+enum {
+  CHOPSTX_POLL_COND = 0,
+  CHOPSTX_POLL_INTR,
+  CHOPSTX_POLL_JOIN,
+};

-#define CHOPSTX_THREAD_SIZE 60
+struct chx_poll_head {
+  uint16_t type;
+  uint16_t ready;
+};
+
+struct chx_poll_cond {
+  uint16_t type;
+  uint16_t ready;
+  /**/
+  chopstx_cond_t *cond;
+  chopstx_mutex_t *mutex;
+  int (*check) (void *);
+  void *arg;
+};
+typedef struct chx_poll_cond chopstx_poll_cond_t;
+
+struct chx_poll_join {
+  uint16_t type;
+  uint16_t ready;
+  /**/
+  chopstx_t thd;
+};
+typedef struct chx_poll_join chopstx_poll_join_t;
+
+struct chx_intr {
+  uint16_t type;
+  uint16_t ready;
+  /**/
+  uint8_t irq_num;
+};
+typedef struct chx_intr chopstx_intr_t;
+
+void chopstx_claim_irq (chopstx_intr_t *intr, uint8_t irq_num);
+
+void chopstx_intr_wait (chopstx_intr_t *intr); /* DEPRECATED */
+
+
+int chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *pd_array[]);
+
+#define CHOPSTX_THREAD_SIZE 64
--- a/contrib/adc-mkl27z.c
+++ b/contrib/adc-mkl27z.c
@@ -0,0 +1,321 @@
+/*
+ * adc-mkl27z.c - ADC driver for MKL27Z
+ *               In this ADC driver, there are NeuG specific parts.
+ *               It only records lower 8-bit of 16-bit data.
+ *               You need to modify to use this as generic ADC driver.
+ *
+ * Copyright (C) 2016  Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <mcu/mkl27z.h>
+
+struct DMAMUX {
+  volatile uint32_t CHCFG0;
+  volatile uint32_t CHCFG1;
+  volatile uint32_t CHCFG2;
+  volatile uint32_t CHCFG3;
+};
+static struct DMAMUX *const DMAMUX = (struct DMAMUX *)0x40021000;
+
+#define INTR_REQ_DMA0 0
+
+struct DMA {
+  volatile uint32_t SAR;
+  volatile uint32_t DAR;
+  volatile uint32_t DSR_BCR;
+  volatile uint32_t DCR;
+};
+static struct DMA *const DMA0 = (struct DMA *)0x40008100;
+static struct DMA *const DMA1 = (struct DMA *)0x40008110;
+
+
+/* We don't use ADC interrupt.  Just for reference.  */
+#define INTR_REQ_ADC 15
+
+struct ADC {
+  volatile uint32_t SC1[2];/* Status and Control Registers 1 */
+  volatile uint32_t CFG1;  /* Configuration Register 1       */
+  volatile uint32_t CFG2;  /* Configuration Register 2       */
+  volatile uint32_t R[2];  /* Data Result Register           */
+
+  /* Compare Value Registers 1, 2 */
+  volatile uint32_t CV1;
+  volatile uint32_t CV2;
+
+  volatile uint32_t SC2;   /* Status and Control Register 2  */
+  volatile uint32_t SC3;   /* Status and Control Register 3  */
+
+  volatile uint32_t OFS;   /* Offset Correction Register     */
+  volatile uint32_t PG;    /* Plus-Side Gain Register        */
+  volatile uint32_t MG;    /* Minus-Side Gain Register       */
+
+  /* Plus-Side General Calibration Value Registers */
+  volatile uint32_t CLPD;
+  volatile uint32_t CLPS;
+  volatile uint32_t CLP4;
+  volatile uint32_t CLP3;
+  volatile uint32_t CLP2;
+  volatile uint32_t CLP1;
+  volatile uint32_t CLP0;
+  uint32_t rsvd0;
+  /* Minus-Side General Calibration Value Registers */
+  volatile uint32_t CLMD;
+  volatile uint32_t CLMS;
+  volatile uint32_t CLM4;
+  volatile uint32_t CLM3;
+  volatile uint32_t CLM2;
+  volatile uint32_t CLM1;
+  volatile uint32_t CLM0;
+};
+static struct ADC *const ADC0 = (struct ADC *)0x4003B000;
+
+/* SC1 */
+#define ADC_SC1_DIFF            (1 << 5)
+#define ADC_SC1_AIEN            (1 << 6)
+#define ADC_SC1_COCO            (1 << 7)
+#define ADC_SC1_TEMPSENSOR      26
+#define ADC_SC1_BANDGAP         27
+#define ADC_SC1_ADCSTOP         31
+
+/* CFG1 */
+#define ADC_CLOCK_SOURCE_ASYNCH (3 << 0)
+#define ADC_MODE_16BIT          (3 << 2)
+#define ADC_ADLSMP_SHORT        (0 << 4)
+#define ADC_ADLSMP_LONG         (1 << 4)
+#define ADC_ADIV_1              (0 << 5)
+#define ADC_ADIV_8              (3 << 5)
+#define ADC_ADLPC_NORMAL        (0 << 7)
+#define ADC_ADLPC_LOWPOWER      (1 << 7)
+/**/
+#define ADC_CLOCK_SOURCE ADC_CLOCK_SOURCE_ASYNCH
+#define ADC_MODE         ADC_MODE_16BIT
+#define ADC_ADLSMP       ADC_ADLSMP_SHORT
+#define ADC_ADIV         ADC_ADIV_1
+#define ADC_ADLPC        ADC_ADLPC_LOWPOWER
+
+/* CFG2 */
+#define ADC_ADLSTS_DEFAULT      0 /* 24 cycles if CFG1.ADLSMP=1, 4 if not.  */
+#define ADC_ADHSC_NORMAL        (0 << 2)
+#define ADC_ADHSC_HIGHSPEED     (1 << 2)
+#define ADC_ADACK_DISABLE       (0 << 3)
+#define ADC_ADACK_ENABLE        (1 << 3)
+#define ADC_MUXSEL_A            (0 << 4)
+#define ADC_MUXSEL_B            (1 << 4)
+/**/
+#define ADC_ADLSTS       ADC_ADLSTS_DEFAULT 
+#define ADC_ADHSC        ADC_ADHSC_NORMAL
+#define ADC_ADACKEN      ADC_ADACK_ENABLE
+#define ADC_MUXSEL       ADC_MUXSEL_A
+
+/* SC2 */
+#define ADC_SC2_REFSEL_DEFAULT  1 /* Internal Voltage Reference??? */
+#define ADC_SC2_DMAEN           (1 << 2)
+#define ADC_SC2_ACREN           (1 << 3)
+#define ADC_SC2_ACFGT           (1 << 4)
+#define ADC_SC2_ACFE            (1 << 5)
+#define ADC_SC2_ADTRG		(1 << 6) /* For hardware trigger */
+
+/* SC3 */
+#define ADC_SC3_AVGS11          0x03
+#define ADC_SC3_AVGE            (1 << 2)
+#define ADC_SC3_ADCO            (1 << 3)
+#define ADC_SC3_CALF            (1 << 6)
+#define ADC_SC3_CAL             (1 << 7)
+
+#define ADC_DMA_SLOT_NUM 40
+
+/*
+ * Buffer to save ADC data.
+ */
+uint32_t adc_buf[64];
+
+static const uint32_t adc0_sc1_setting = ADC_SC1_TEMPSENSOR;
+
+static chopstx_intr_t adc_intr;
+
+struct adc_internal {
+  uint32_t buf[64];
+  uint8_t *p;
+  int phase : 8;
+  int count : 8;
+};
+struct adc_internal adc;
+
+/*
+ * Initialize ADC module, do calibration.
+ *
+ * This is called by MAIN, only once, hopefully before creating any
+ * other threads (to be accurate).
+ *
+ * We configure ADC0 to kick DMA0, configure DMA0 to kick DMA1.
+ * DMA0 records output of ADC0 to the ADC.BUF.
+ * DMA1 kicks ADC0 again to get another value.
+ *
+ * ADC0 --[finish conversion]--> DMA0 --[Link channel 1]--> DMA1
+ */
+int
+adc_init (void)
+{
+  uint32_t v;
+
+  /* Enable ADC0 and DMAMUX clock.  */
+  SIM->SCGC6 |= (1 << 27) | (1 << 1);
+  /* Enable DMA clock.  */
+  SIM->SCGC7 |= (1 << 8);
+
+  /* ADC0 setting for calibration.  */
+  ADC0->CFG1 = ADC_CLOCK_SOURCE | ADC_MODE | ADC_ADLSMP | ADC_ADIV | ADC_ADLPC;
+  ADC0->CFG2 = ADC_ADLSTS | ADC_ADHSC | ADC_ADACKEN | ADC_MUXSEL;
+  ADC0->SC2 = ADC_SC2_REFSEL_DEFAULT;
+  ADC0->SC3 = ADC_SC3_CAL | ADC_SC3_CALF | ADC_SC3_AVGE | ADC_SC3_AVGS11;
+
+  /* Wait ADC completion */
+  while ((ADC0->SC1[0] & ADC_SC1_COCO) == 0)
+    if ((ADC0->SC3 & ADC_SC3_CALF) != 0)
+      /* Calibration failure */
+      return -1;
+
+  if ((ADC0->SC3 & ADC_SC3_CALF) != 0)
+    /* Calibration failure */
+    return -1;
+
+  /* Configure PG by the calibration values.  */
+  v = ADC0->CLP0 + ADC0->CLP1 + ADC0->CLP2 + ADC0->CLP3 + ADC0->CLP4 + ADC0->CLPS;
+  ADC0->PG = 0x8000 | (v >> 1);
+
+  /* Configure MG by the calibration values.  */
+  v = ADC0->CLM0 + ADC0->CLM1 + ADC0->CLM2 + ADC0->CLM3 + ADC0->CLM4 + ADC0->CLMS;
+  ADC0->MG = 0x8000 | (v >> 1);
+
+  ADC0->SC1[0] = ADC_SC1_ADCSTOP;
+
+  /* DMAMUX setting.  */
+  DMAMUX->CHCFG0 = (1 << 7) | ADC_DMA_SLOT_NUM;
+
+  /* DMA0 initial setting.  */
+  DMA0->SAR = (uint32_t)&ADC0->R[0];
+
+  /* DMA1 initial setting.  */
+  DMA1->SAR = (uint32_t)&adc0_sc1_setting;
+  DMA1->DAR = (uint32_t)&ADC0->SC1[0];
+  
+  chopstx_claim_irq (&adc_intr, INTR_REQ_DMA0);
+  return 0;
+}
+
+/*
+ * Start using ADC.
+ */
+void
+adc_start (void)
+{
+  ADC0->CFG1 = ADC_CLOCK_SOURCE | ADC_MODE | ADC_ADLSMP | ADC_ADIV | ADC_ADLPC;
+  ADC0->CFG2 = ADC_ADLSTS | ADC_ADHSC | ADC_ADACKEN | ADC_MUXSEL;
+  ADC0->SC2 = ADC_SC2_REFSEL_DEFAULT | ADC_SC2_DMAEN;
+  ADC0->SC3 = 0;
+}
+
+/*
+ * Kick getting data for COUNT times.
+ * Data will be saved in ADC_BUF starting at OFFSET.
+ */
+static void
+adc_start_conversion_internal (int count)
+{
+  /* DMA0 setting.  */
+  DMA0->DAR = (uint32_t)&adc.buf[0];
+  DMA0->DSR_BCR = 4 * count;
+  DMA0->DCR = (1 << 31) | (1 << 30) | (1 << 29) | (0 << 20) | (1 << 19)
+            | (0 << 17) | (1 <<  7) | (2 <<  4) | (1 <<  2);
+
+  /* Kick DMA1.  */
+  DMA1->DSR_BCR = 4 * count;
+  DMA1->DCR = (1 << 30) | (1 << 29) | (0 << 19) | (0 << 17) | (1 << 16) | (1 << 7);
+}
+
+
+/*
+ * Kick getting data for COUNT times.
+ * Data will be saved in ADC_BUF starting at OFFSET.
+ */
+void
+adc_start_conversion (int offset, int count)
+{
+  adc.p = (uint8_t *)&adc_buf[offset];
+  adc.phase = 0;
+  adc.count = count;
+  adc_start_conversion_internal (count);
+}
+
+
+static void
+adc_stop_conversion (void)
+{
+  ADC0->SC1[0] = ADC_SC1_ADCSTOP;
+}
+
+/*
+ * Stop using ADC.
+ */
+void
+adc_stop (void)
+{
+  SIM->SCGC6 &= ~(1 << 27);
+}
+
+/*
+ * Return 0 on success.
+ * Return 1 on error.
+ */
+int
+adc_wait_completion (void)
+{
+  struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&adc_intr };
+  int i;
+
+  while (1)
+    {
+      /* Wait DMA completion */
+      chopstx_poll (NULL, 1, pd_array);
+
+      DMA0->DSR_BCR = (1 << 24);
+      DMA1->DSR_BCR = (1 << 24);
+
+      adc_stop_conversion ();
+
+      for (i = 0; i < adc.count; i++)
+	*adc.p++ = (uint8_t)adc.buf[i];
+
+      if (++adc.phase >= 4)
+	break;
+
+      adc_start_conversion_internal (adc.count);
+    }
+
+  return 0;
+}
--- a/contrib/adc-stm32f103.c
+++ b/contrib/adc-stm32f103.c
@@ -0,0 +1,329 @@
+/*
+ * adc_stm32f103.c - ADC driver for STM32F103
+ *                   In this ADC driver, there are NeuG specific parts.
+ *                   You need to modify to use this as generic ADC driver.
+ *
+ * Copyright (C) 2011, 2012, 2013, 2015, 2016
+ *               Free Software Initiative of Japan
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <mcu/stm32f103.h>
+#include "adc.h"
+
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+
+#define ADC_SMPR1_SMP_VREF(n)   ((n) << 21)
+#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18)
+
+#define ADC_SMPR1_SMP_AN10(n)   ((n) << 0)
+#define ADC_SMPR1_SMP_AN11(n)   ((n) << 3)
+
+#define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)
+#define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)
+#define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)
+#define ADC_SMPR2_SMP_AN9(n)    ((n) << 27)
+
+#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
+
+#define ADC_SQR3_SQ1_N(n)       ((n) << 0)
+#define ADC_SQR3_SQ2_N(n)       ((n) << 5)
+#define ADC_SQR3_SQ3_N(n)       ((n) << 10)
+#define ADC_SQR3_SQ4_N(n)       ((n) << 15)
+
+#define ADC_SAMPLE_1P5          0
+
+#define ADC_CHANNEL_IN0         0
+#define ADC_CHANNEL_IN1         1
+#define ADC_CHANNEL_IN2         2
+#define ADC_CHANNEL_IN9         9
+#define ADC_CHANNEL_IN10        10
+#define ADC_CHANNEL_IN11        11
+#define ADC_CHANNEL_SENSOR      16
+#define ADC_CHANNEL_VREFINT     17
+
+#define DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
+#define DELIBARATELY_DO_IT_WRONG_START_STOP
+
+#ifdef DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
+#define ADC_SAMPLE_VREF ADC_SAMPLE_1P5
+#define ADC_SAMPLE_SENSOR ADC_SAMPLE_1P5
+#else
+#define ADC_SAMPLE_VREF ADC_SAMPLE_239P5
+#define ADC_SAMPLE_SENSOR ADC_SAMPLE_239P5
+#endif
+
+#define NEUG_DMA_CHANNEL STM32_DMA1_STREAM1
+#define NEUG_DMA_MODE							\
+  (  STM32_DMA_CR_PL (STM32_ADC_ADC1_DMA_PRIORITY)			\
+     | STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD		\
+     | STM32_DMA_CR_MINC       | STM32_DMA_CR_TCIE			\
+     | STM32_DMA_CR_TEIE  )
+
+#define NEUG_ADC_SETTING1_SMPR1 ADC_SMPR1_SMP_VREF(ADC_SAMPLE_VREF)     \
+                              | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_SENSOR)
+#define NEUG_ADC_SETTING1_SMPR2 0
+#define NEUG_ADC_SETTING1_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_VREFINT)     \
+                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_SENSOR)      \
+                              | ADC_SQR3_SQ3_N(ADC_CHANNEL_SENSOR)      \
+                              | ADC_SQR3_SQ4_N(ADC_CHANNEL_VREFINT)
+#define NEUG_ADC_SETTING1_NUM_CHANNELS 4
+
+/*
+ * ADC finish interrupt
+ */
+#define INTR_REQ_DMA1_Channel1 11
+
+static chopstx_intr_t adc_intr;
+
+/*
+ * Do calibration for both of ADCs.
+ */
+int
+adc_init (void)
+{
+  RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
+  RCC->APB2RSTR = (RCC_APB2RSTR_ADC1RST | RCC_APB2RSTR_ADC2RST);
+  RCC->APB2RSTR = 0;
+
+  ADC1->CR1 = 0;
+  ADC1->CR2 = ADC_CR2_ADON;
+  ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+  while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
+    ;
+  ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+  while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
+    ;
+  ADC1->CR2 = 0;
+
+  ADC2->CR1 = 0;
+  ADC2->CR2 = ADC_CR2_ADON;
+  ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+  while ((ADC2->CR2 & ADC_CR2_RSTCAL) != 0)
+    ;
+  ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+  while ((ADC2->CR2 & ADC_CR2_CAL) != 0)
+    ;
+  ADC2->CR2 = 0;
+  RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
+
+  chopstx_claim_irq (&adc_intr, INTR_REQ_DMA1_Channel1);
+  return 0;
+}
+
+#include "board.h"
+#include "sys.h"
+
+static void
+get_adc_config (uint32_t config[4])
+{
+  config[2] = ADC_SQR1_NUM_CH(2);
+  switch (SYS_BOARD_ID)
+    {
+    case BOARD_ID_FST_01:
+      config[0] = 0;
+      config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
+		| ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5);
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
+		| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9);
+      break;
+
+    case BOARD_ID_OLIMEX_STM32_H103:
+    case BOARD_ID_STBEE:
+      config[0] = ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5)
+		| ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5);
+      config[1] = 0;
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)
+		| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11);
+      break;
+
+    case BOARD_ID_STBEE_MINI:
+      config[0] = 0;
+      config[1] = ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5)
+		| ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5);
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1)
+		| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2);
+      break;
+
+    case BOARD_ID_CQ_STARM:
+    case BOARD_ID_FST_01_00:
+    case BOARD_ID_MAPLE_MINI:
+    case BOARD_ID_STM32_PRIMER2:
+    case BOARD_ID_STM8S_DISCOVERY:
+    case BOARD_ID_ST_DONGLE:
+    case BOARD_ID_ST_NUCLEO_F103:
+    case BOARD_ID_NITROKEY_START:
+    default:
+      config[0] = 0;
+      config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
+		| ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5);
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
+		| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN1);
+      break;
+    }
+}
+
+
+void
+adc_start (void)
+{
+  uint32_t config[4];
+
+  get_adc_config (config);
+
+  /* Use DMA channel 1.  */
+  RCC->AHBENR |= RCC_AHBENR_DMA1EN;
+  DMA1_Channel1->CCR = STM32_DMA_CCR_RESET_VALUE;
+  DMA1->IFCR = 0xffffffff;
+
+  RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
+
+  ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+	       | ADC_CR1_SCAN);
+  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+  ADC1->SMPR1 = NEUG_ADC_SETTING1_SMPR1;
+  ADC1->SMPR2 = NEUG_ADC_SETTING1_SMPR2;
+  ADC1->SQR1 = ADC_SQR1_NUM_CH(NEUG_ADC_SETTING1_NUM_CHANNELS);
+  ADC1->SQR2 = 0;
+  ADC1->SQR3 = NEUG_ADC_SETTING1_SQR3;
+
+  ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+	       | ADC_CR1_SCAN);
+  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  ADC2->SMPR1 = config[0];
+  ADC2->SMPR2 = config[1];
+  ADC2->SQR1 = config[2];
+  ADC2->SQR2 = 0;
+  ADC2->SQR3 = config[3];
+
+#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
+  /*
+   * We could just let ADC run continuously always and only enable DMA
+   * to receive stable data from ADC.  But our purpose is not to get
+   * correct data but noise.  In fact, we can get more noise when we
+   * start/stop ADC each time.
+   */
+  ADC2->CR2 = 0;
+  ADC1->CR2 = 0;
+#else
+  /* Start conversion.  */
+  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+#endif
+}
+
+uint32_t adc_buf[64];
+
+void
+adc_start_conversion (int offset, int count)
+{
+  DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR;        /* SetPeripheral */
+  DMA1_Channel1->CMAR = (uint32_t)&adc_buf[offset]; /* SetMemory0    */
+  DMA1_Channel1->CNDTR = count;                     /* Counter       */
+  DMA1_Channel1->CCR = NEUG_DMA_MODE | DMA_CCR1_EN; /* Mode   */
+
+#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
+  /* Power on */
+  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+  /*
+   * Start conversion.  tSTAB is 1uS, but we don't follow the spec, to
+   * get more noise.
+   */
+  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+#endif
+}
+
+
+static void adc_stop_conversion (void)
+{
+  DMA1_Channel1->CCR &= ~DMA_CCR1_EN;
+
+#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
+  ADC2->CR2 = 0;
+  ADC1->CR2 = 0;
+#endif
+}
+
+void
+adc_stop (void)
+{
+  ADC1->CR1 = 0;
+  ADC1->CR2 = 0;
+
+  ADC2->CR1 = 0;
+  ADC2->CR2 = 0;
+
+  RCC->AHBENR &= ~RCC_AHBENR_DMA1EN;
+  RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
+}
+
+
+static uint32_t adc_err;
+
+/*
+ * Return 0 on success.
+ * Return 1 on error.
+ */
+int
+adc_wait_completion (void)
+{
+  uint32_t flags;
+  struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&adc_intr };
+
+  while (1)
+    {
+      chopstx_poll (NULL, 1, pd_array);
+      flags = DMA1->ISR & STM32_DMA_ISR_MASK; /* Channel 1 interrupt cause.  */
+      /*
+       * Clear interrupt cause of channel 1.
+       *
+       * Note that CGIFx=0, as CGIFx=1 clears all of GIF, HTIF, TCIF
+       * and TEIF.
+       */
+      DMA1->IFCR = (flags & ~1);
+
+      if ((flags & STM32_DMA_ISR_TEIF) != 0)  /* DMA errors  */
+	{
+	  /* Should never happened.  If any, it's coding error. */
+	  /* Access an unmapped address space or alignment violation.  */
+	  adc_err++;
+	  adc_stop_conversion ();
+	  return 1;
+	}
+      else if ((flags & STM32_DMA_ISR_TCIF) != 0) /* Transfer complete */
+	{
+	  adc_stop_conversion ();
+	  return 0;
+	}
+    }
+}
--- a/doc/chopstx-api.texi
+++ b/doc/chopstx-api.texi
@@ -20,16 +20,7 @@ stop further execution of code.  It never returns.

@var{arg}: Argument to the thread entry function

-Create a thread.
-@end deftypefun
-
-@subheading chopstx_usec_wait_var
-@anchor{chopstx_usec_wait_var}
-@deftypefun {void} {chopstx_usec_wait_var} (uint32_t * @var{var})
-@var{var}: Pointer to usec
-
-Sleep for micro second specified by @var{var}.
-Another thread can clear @var{var} on condition (to avoid this thread going into sleep).
+Create a thread.  Returns thread ID.
@end deftypefun

@subheading chopstx_usec_wait
@@ -95,7 +86,7 @@ Wake up a thread waiting on @var{cond}.
@deftypefun {void} {chopstx_cond_broadcast} (chopstx_cond_t * @var{cond})
@var{cond}: Condition Variable

-Wake up all thread winting on @var{cond}.
+Wake up all threads waiting on @var{cond}.
@end deftypefun

@subheading chopstx_claim_irq
@@ -105,15 +96,7 @@ Wake up all thread winting on @var{cond}.

@var{irq_num}: IRQ Number (hardware specific)

-Claim interrupt @var{intr} with @var{irq_num} for this thread.
-@end deftypefun
-
-@subheading chopstx_release_irq
-@anchor{chopstx_release_irq}
-@deftypefun {void} {chopstx_release_irq} (chopstx_intr_t * @var{intr0})
-@var{intr0}: Interrupt request to be unregistered
-
-Release the interrupt request specified by @var{intr0}.
+Claim interrupt @var{intr} with @var{irq_num}
@end deftypefun

@subheading chopstx_intr_wait
@@ -146,29 +129,21 @@ clean-up will be executed.
@deftypefun {void} {chopstx_exit} (void * @var{retval})
@var{retval}: Return value (to be caught by a joining thread)

-Calling this function terminates the execution of thread, after
-calling clean up functions.  If the calling thread still holds
-mutexes, they will be released.  If the calling thread claiming
-IRQ, it will be released, too.  This function never returns.
+Calling this function terminates the execution of running thread,
+after calling clean up functions.  If the calling thread still
+holds mutexes, they will be released.  This function never
+returns.
@end deftypefun

@subheading chopstx_join
@anchor{chopstx_join}
-@deftypefun {void} {chopstx_join} (chopstx_t @var{thd}, void ** @var{ret})
+@deftypefun {int} {chopstx_join} (chopstx_t @var{thd}, void ** @var{ret})
@var{thd}: Thread to wait

@var{ret}: Pointer to void * to store return value

 Waits for the thread of @var{thd} to terminate.
-@end deftypefun
-
-@subheading chopstx_wakeup_usec_wait
-@anchor{chopstx_wakeup_usec_wait}
-@deftypefun {void} {chopstx_wakeup_usec_wait} (chopstx_t @var{thd})
-@var{thd}: Thread to be awakened
-
-Canceling the timer, wakup the sleeping thread for it.
-No return value.
+Returns 0 on success, 1 when waiting is interrupted.
@end deftypefun

@subheading chopstx_cancel
@@ -176,7 +151,7 @@ No return value.
@deftypefun {void} {chopstx_cancel} (chopstx_t @var{thd})
@var{thd}: Thread to be canceled

-This function requests a cancellation th the thread @var{thd}.
+This function requests a cancellation of a thread @var{thd}.
 No return value.
@end deftypefun

@@ -189,3 +164,40 @@ No return value.  If the thread is canceled, this function
 does not return.
@end deftypefun

+@subheading chopstx_setcancelstate
+@anchor{chopstx_setcancelstate}
+@deftypefun {int} {chopstx_setcancelstate} (int @var{cancel_disable})
+@var{cancel_disable}: 0 to enable cancelation, otherwise disabled.
+
+Calling chopstx_setcancelstate sets cancelability state.
+
+Returns old state which is 0 when it was enabled.
+@end deftypefun
+
+@subheading chopstx_poll
+@anchor{chopstx_poll}
+@deftypefun {int} {chopstx_poll} (uint32_t * @var{usec_p}, int @var{n}, struct chx_poll_head * [] @var{pd_array})
+@var{usec_p}: Pointer to usec for timeout.  Forever if NULL.
+
+@var{n}: Number of poll descriptors
+
+@var{pd_array}: Pointer to an array of poll descriptor pointer which
+should be one of:
+chopstx_poll_cond_t, chopstx_poll_join_t, or chopstx_intr_t.
+
+Returns number of active descriptors.
+@end deftypefun
+
+@subheading chopstx_setpriority
+@anchor{chopstx_setpriority}
+@deftypefun {chopstx_prio_t} {chopstx_setpriority} (chopstx_prio_t @var{prio_new})
+Change the schedule priority with @var{prio}.
+Returns the old priority.
+
+In general, it is not recommended to use this function because
+dynamically changing schedule priorities complicates the system.
+Only a possible valid usage of this function is in the main thread
+which starts its execution with priority of CHX_PRIO_MAIN_INIT, and
+let it change its priority after initialization of other threads.
+@end deftypefun
+
--- a/doc/chopstx.texi
+++ b/doc/chopstx.texi
@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
@c %**start of header
@setfilename chopstx.info
-@set VERSION 0.00
+@set VERSION 1.3
@settitle Chopstx Reference Manual
@c Unify some of the indices.
@syncodeindex tp fn
@@ -11,7 +11,7 @@
 This manual is for Chopstx (version @value{VERSION}).

@noindent
-Copyright @copyright{} 2013 Flying Stone Technology @*
+Copyright @copyright{} 2013, 2015, 2016 Flying Stone Technology @*

@quotation
 Permission is granted to copy, distribute and/or modify this document
@@ -83,7 +83,8 @@ Indexes
@node Introduction
@chapter Introduction

-Chopstx is an RT thread library for ARM Cortex-M3, specifically,
+Chopstx is an RT thread library for ARM Cortex-M0, Cortex-M0plus and
+Cortex-M3.  Specifically, it is used for STM32F030, MKL27Z and
 STM32F103.

 While most RTOSes come with many features, drivers, and stacks,
--- a/entry.c
+++ b/entry.c
@@ -1,7 +1,8 @@
 /*
 * entry.c - Entry routine when reset and interrupt vectors.
 *
- * Copyright (C) 2013 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015, 2016
+ *               Flying Stone Technology
 * Author: NIIBE Yutaka <gniibe@fsij.org>
 *
 * This file is a part of Chopstx, a thread library for embedded.
@@ -30,194 +31,38 @@
 #include <stdlib.h>
 #include <chopstx.h>

-#ifdef HAVE_SYS_H
-#define INLINE __attribute__ ((used))
-#include "sys.h"
-#else
 #include "board.h"
-
-#define STM32_SW_PLL		(2 << 0)
-#define STM32_PLLSRC_HSE	(1 << 16)
-
-#define STM32_PLLXTPRE_DIV1	(0 << 17)
-#define STM32_PLLXTPRE_DIV2	(1 << 17)
-
-#define STM32_HPRE_DIV1		(0 << 4)
-
-#define STM32_PPRE1_DIV2	(4 << 8)
-
-#define STM32_PPRE2_DIV1        (0 << 11)
-#define STM32_PPRE2_DIV2	(4 << 11)
-
-#define STM32_ADCPRE_DIV4	(1 << 14)
-#define STM32_ADCPRE_DIV6       (2 << 14)
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)
-
-#define STM32_MCO_NOCLOCK	(0 << 24)
-
-#define STM32_SW		STM32_SW_PLL
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_HPRE		STM32_HPRE_DIV1
-#define STM32_PPRE1		STM32_PPRE1_DIV2
-#define STM32_PPRE2		STM32_PPRE2_DIV1
-#define STM32_ADCPRE		STM32_ADCPRE_DIV6
-#define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
-
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
-#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK		STM32_PLLCLKOUT
-#define STM32_HCLK		(STM32_SYSCLK / 1)
-
-#define STM32_FLASHBITS		0x00000012
-
-#define PERIPH_BASE	0x40000000
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN	0x00800000
-#define RCC_APB1RSTR_USBRST	0x00800000
-
-#define RCC_CR_HSION		0x00000001
-#define RCC_CR_HSIRDY		0x00000002
-#define RCC_CR_HSITRIM		0x000000F8
-#define RCC_CR_HSEON		0x00010000
-#define RCC_CR_HSERDY		0x00020000
-#define RCC_CR_PLLON		0x01000000
-#define RCC_CR_PLLRDY		0x02000000
-
-#define RCC_CFGR_SWS		0x0000000C
-#define RCC_CFGR_SWS_HSI	0x00000000
-
-#define RCC_AHBENR_CRCEN        0x0040
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void __attribute__((used))
-clock_init (void)
-{
-  /* HSI setup */
-  RCC->CR |= RCC_CR_HSION;
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
-  RCC->CFGR = 0;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;
-
-  /* HSE setup */
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;
-
-  /* PLL setup */
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-
-  /* Clock settings */
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
-    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /* Flash setup */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* CRC */
-  RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
-  /* Switching on the configured clock source. */
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-}
-
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-
-static void __attribute__((used))
-gpio_init (void)
-{
-  /* Enable GPIO clock. */
-  RCC->APB2ENR |= RCC_APB2ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
-  RCC->APB2RSTR = 0;
-
-  GPIO_USB->ODR = VAL_GPIO_ODR;
-  GPIO_USB->CRH = VAL_GPIO_CRH;
-  GPIO_USB->CRL = VAL_GPIO_CRL;
-
-#if GPIO_USB_BASE != GPIO_LED_BASE
-  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
-  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
-  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
+#if defined(USE_SYS3) || defined(USE_SYS_CLOCK_GPIO_SETTING)
+#define REQUIRE_CLOCK_GPIO_SETTING_IN_SYS
+#include "sys.h"
+/*
+ * Avoid medium density specific code and prepare for high density
+ * device, too.
+ */
+#undef STM32F10X_MD
+#else
+#if defined (MCU_KINETIS_L)
+#include "mcu/clk_gpio_init-mkl27z.c"
+#else
+#include "mcu/clk_gpio_init-stm32.c"
 #endif
-}
 #endif


+#ifdef MAKE_ENTRY_PUBLIC
+#define STATIC_ENTRY
+#else
+#define STATIC_ENTRY static
+#endif
+
+extern uint8_t __main_stack_end__;
+#if defined(__ARM_ARCH_7M__)
+extern void svc (void);
+#endif
+extern void preempt (void);
+extern void chx_timer_expired (void);
+extern void chx_handle_intr (void);
+
 static void nmi (void)
 {
  for (;;);
@@ -250,11 +95,17 @@ static void none (void)
 #define C_S_SUB(arg0, arg1, arg2) arg0 #arg1 arg2
 #define COMPOSE_STATEMENT(arg0,arg1,arg2)  C_S_SUB (arg0, arg1, arg2)

+#if defined(__ARM_ARCH_6M__)
+__attribute__ ((used,section(".bss.startup.0")))
+uint32_t vectors_in_ram[48];
+#endif
+
 /*
 * This routine only changes PSP and not MSP.
 */
-static __attribute__ ((naked,section(".text.startup.0")))
-void entry (void)
+STATIC_ENTRY __attribute__ ((naked,section(".text.startup.0")))
+void
+entry (void)
 {
  asm volatile ("bl	clock_init\n\t"
 		/* Clear BSS section.  */
@@ -264,7 +115,12 @@ void entry (void)
 	"0:\n\t"
 		"cmp	r1, r2\n\t"
 		"beq	1f\n\t"
+#if defined(__ARM_ARCH_6M__)
+		"str	r0, [r1]\n\t"
+		"add	r1, #4\n\t"
+#else
 		"str	r0, [r1], #4\n\t"
+#endif
 		"b	0b\n"
 	"1:\n\t"
 		/* Copy data section.  */
@@ -274,8 +130,15 @@ void entry (void)
 	"2:\n\t"
 		"cmp	r1, r2\n\t"
 		"beq	3f\n\t"
+#if defined(__ARM_ARCH_6M__)
+		"ldr	r0, [r3]\n\t"
+		"str	r0, [r1]\n\t"
+		"add	r3, #4\n\t"
+		"add	r1, #4\n\t"
+#else
 		"ldr	r0, [r3], #4\n\t"
 		"str	r0, [r1], #4\n\t"
+#endif
 		"b	2b\n"
 	"3:\n\t"
 		/* Switch to PSP.  */
@@ -289,8 +152,10 @@ void entry (void)
 		"bl	chx_systick_init\n\t"
 		"bl	gpio_init\n\t"
 		/* Enable interrupts.  */
+#if defined(__ARM_ARCH_7M__)
 		"mov	r0, #0\n\t"
 		"msr	BASEPRI, r0\n\t"
+#endif
 		"cpsie	i\n\t"
 		/* Call main.  */
 		"mov	r1, r0\n\t"
@@ -302,15 +167,9 @@ void entry (void)


 typedef void (*handler)(void);
-extern uint8_t __main_stack_end__;
-
-extern void svc (void);
-extern void preempt (void);
-extern void chx_timer_expired (void);
-extern void chx_handle_intr (void);

 handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
-  (handler)&__main_stack_end__,
+  (handler)(&__main_stack_end__ - 32),
  entry,
  nmi,		/* nmi */
  hard_fault,		/* hard fault */
@@ -321,7 +180,11 @@ handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
  none,
  /* 0x20 */
  none, none, none,		/* reserved */
+#if defined(__ARM_ARCH_6M__)
+  none,				/* SVCall */
+#elif defined(__ARM_ARCH_7M__)
  svc,				/* SVCall */
+#endif  
  none,				/* Debug */
  none,				/* reserved */
  preempt,			/* PendSV */
@@ -340,12 +203,25 @@ handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
  chx_handle_intr /* DMA1 CH6 */, chx_handle_intr /* DMA1 CH7 */,
  chx_handle_intr /* ADC1_2 */,   chx_handle_intr /* USB HP */,
  /* 0x90 */
-  chx_handle_intr,		/* USB LP */
-  /* ... and more.  CAN, EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr /* USB LP */,   chx_handle_intr /* CAN */,
+  /* ... and more.  EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
  chx_handle_intr,                chx_handle_intr,
+  /* 0xA0 */
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  /* 0xc0 */
+#if !defined(__ARM_ARCH_6M__)
+  /* STM32F0 doesn't have more.  */
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+#endif
+#if !defined(STM32F10X_MD)
+  /* High-density chips have more; RTCAlarm, USBWakeup, ... , DMA2_Channel4_5 */
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+#endif
 };
--- a/eventflag.c
+++ b/eventflag.c
@@ -1,7 +1,7 @@
 /*
- * eventflag.c - Eventflag with/without timeout
+ * eventflag.c - Eventflag
 *
- * Copyright (C) 2013 Flying Stone Technology
+ * Copyright (C) 2013, 2016  Flying Stone Technology
 * Author: NIIBE Yutaka <gniibe@fsij.org>
 *
 * This file is a part of Chopstx, a thread library for embedded.
@@ -31,24 +31,55 @@
 #include <chopstx.h>
 #include <eventflag.h>

-enum {
-  EVENTFLAG_ERR_WAIT = CHOPSTX_ERR_JOIN + 1,
-  EVENTFLAG_ERR_TIMED_WAIT,
-};
+
+void
+eventflag_init (struct eventflag *ev)
+{
+  ev->flags = 0;
+  chopstx_cond_init (&ev->cond);
+  chopstx_mutex_init (&ev->mutex);
+}
+
+
+static int
+eventflag_check (void *arg)
+{
+  struct eventflag *ev = arg;
+
+  return ev->flags != 0;
+}


 void
-eventflag_init (struct eventflag *ev, chopstx_t sleeper)
+eventflag_prepare_poll (struct eventflag *ev, chopstx_poll_cond_t *poll_desc)
 { 
-  ev->sleeper = sleeper;
+  poll_desc->type = CHOPSTX_POLL_COND;
+  poll_desc->ready = 0;
+  poll_desc->cond = &ev->cond;
+  poll_desc->mutex = &ev->mutex;
+  poll_desc->check = eventflag_check;
+  poll_desc->arg = ev;
+}

-  if (sleeper)
-    ev->u.wait_usec = 0;
+
+eventmask_t
+eventflag_get (struct eventflag *ev)
+{
+  int n;
+  eventmask_t m;
+
+  chopstx_mutex_lock (&ev->mutex);
+  n = __builtin_ffs (ev->flags);
+  if (n)
+    {
+      m = (1 << (n - 1));
+      ev->flags &= ~m;
+    }
  else
-    chopstx_cond_init (&ev->u.cond);
+    m = 0;
+  chopstx_mutex_unlock (&ev->mutex);

-  ev->flag = 0;
-  chopstx_mutex_init (&ev->mutex);
+  return m;
 }


@@ -56,50 +87,35 @@ eventmask_t
 eventflag_wait (struct eventflag *ev)
 {
  int n;
-
-  if (ev->sleeper)
-    chx_fatal (EVENTFLAG_ERR_WAIT);
+  eventmask_t m;

  chopstx_mutex_lock (&ev->mutex);
-  if (!ev->flag)
-    chopstx_cond_wait (&ev->u.cond, &ev->mutex);
+  if (!ev->flags)
+    chopstx_cond_wait (&ev->cond, &ev->mutex);

-  n = __builtin_ffs (ev->flag);
-  ev->flag &= ~(1 << (n - 1));
+  n = __builtin_ffs (ev->flags);
+  if (n) /* Always n > 0 when waked up, but make sure no bad things.  */
+    {
+      m = (1 << (n - 1));
+      ev->flags &= ~m;
+    }
+  else
+    m = 0;
  chopstx_mutex_unlock (&ev->mutex);

-  return (1 << (n - 1));
+  return m;
 }

+
 eventmask_t
 eventflag_wait_timeout (struct eventflag *ev, uint32_t usec)
 {
-  eventmask_t em = 0;
-  int n;
+  chopstx_poll_cond_t poll_desc;
+  struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&poll_desc };

-  if (ev->sleeper == 0)
-    chx_fatal (EVENTFLAG_ERR_TIMED_WAIT);
-
-  chopstx_mutex_lock (&ev->mutex);
-
-  if (!ev->flag)
-    {
-      ev->u.wait_usec = usec;
-      chopstx_mutex_unlock (&ev->mutex);
-      chopstx_usec_wait_var (&ev->u.wait_usec);
-      chopstx_mutex_lock (&ev->mutex);
-      ev->u.wait_usec = 0;
-    }
-
-  n = __builtin_ffs (ev->flag);
-  if (n)
-    {
-      em = (1 << (n - 1));
-      ev->flag &= ~em;
-    }
-
-  chopstx_mutex_unlock (&ev->mutex);
-  return em;
+  eventflag_prepare_poll (ev, &poll_desc);
+  chopstx_poll (&usec, 1, pd_array);
+  return eventflag_get (ev);
 }


@@ -107,16 +123,7 @@ void
 eventflag_signal (struct eventflag *ev, eventmask_t m)
 {
  chopstx_mutex_lock (&ev->mutex);
-  ev->flag |= m;
-  if (ev->sleeper)
-    {
-      if (ev->u.wait_usec)
-	{
-	  ev->u.wait_usec = 0;
-	  chopstx_wakeup_usec_wait (ev->sleeper);
-	}
-    }
-  else
-    chopstx_cond_signal (&ev->u.cond);
+  ev->flags |= m;
+  chopstx_cond_signal (&ev->cond);
  chopstx_mutex_unlock (&ev->mutex);
 }
--- a/eventflag.h
+++ b/eventflag.h
@@ -1,16 +1,16 @@
 typedef uint32_t eventmask_t;

 struct eventflag {
-  chopstx_t sleeper;
-  eventmask_t flag;
+  eventmask_t flags;
  chopstx_mutex_t mutex;
-  union {
-    uint32_t wait_usec;
  chopstx_cond_t cond;
-  } u;
 };

-void eventflag_init (struct eventflag *ev, chopstx_t owner);
+void eventflag_init (struct eventflag *ev);
 eventmask_t eventflag_wait (struct eventflag *ev);
 eventmask_t eventflag_wait_timeout (struct eventflag *ev, uint32_t usec);
 void eventflag_signal (struct eventflag *ev, eventmask_t m);
+
+/* For polling */
+void eventflag_prepare_poll (struct eventflag *ev, chopstx_poll_cond_t *p);
+eventmask_t eventflag_get (struct eventflag *ev);
--- a/example-cdc/Makefile
+++ b/example-cdc/Makefile
@@ -4,7 +4,12 @@ PROJECT = sample

 CHOPSTX = ..
 LDSCRIPT= sample.ld
-CSRC = sys.c aes-constant-ft.c sample.c usb-cdc.c usb_stm32f103.c
+CSRC = sample.c usb-cdc.c
+
+CHIP=stm32f103
+
+USE_SYS = yes
+USE_USB = yes

 ###################################
 CROSS = arm-none-eabi-
@@ -14,7 +19,7 @@ OBJCOPY   = $(CROSS)objcopy

 MCU   = cortex-m3
 CWARN = -Wall -Wextra -Wstrict-prototypes
-DEFS  = -DHAVE_SYS_H -DFREE_STANDING
+DEFS  = -DUSE_SYS3 -DFREE_STANDING
 OPT   = -O3 -Os -g
 LIBS  =

--- a/example-cdc/aes-constant-ft.c
+++ b/example-cdc/aes-constant-ft.c
@@ -1,145 +0,0 @@
-/*
- * aes-constant-ft.c - AES forward tables.
- *
- * We need something useful for the initial flash ROM page (4 Ki
- * bytes), which cannot be modified after installation.  Even after
- * upgrade of the firmware, it stays intact.
- *
- * We decide to put 3/4 of AES forward tables to fill 3 Ki bytes, as
- * its useful and it won't change.
- *
- * The code was taken from aes.c of PolarSSL version 0.14, and then,
- * modified to add section names.
- *
- * Since this is just a data, it wouldn't be copyright-able, but the
- * original auther would claim so.  Thus, we put original copyright
- * notice here.  It is highly likely that there will be no such a
- * thing for copyright.  Nevertheless, we think that PolarSSL is good
- * software to address here, and encourage people using it.
- *
- */
-
-#include <stdint.h>
-
-/*
- * Original copyright notice is below:
- */
-
-/*
- *  FIPS-197 compliant AES implementation
- *
- *  Copyright (C) 2006-2010, Brainspark B.V.
- *
- *  This file is part of PolarSSL (http://www.polarssl.org)
- *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-/*
- *  The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
- *
- *  http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
- *  http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
- */
-
-/*
- * Forward tables
- */
-#define FT \
-\
-    V(A5,63,63,C6), V(84,7C,7C,F8), V(99,77,77,EE), V(8D,7B,7B,F6), \
-    V(0D,F2,F2,FF), V(BD,6B,6B,D6), V(B1,6F,6F,DE), V(54,C5,C5,91), \
-    V(50,30,30,60), V(03,01,01,02), V(A9,67,67,CE), V(7D,2B,2B,56), \
-    V(19,FE,FE,E7), V(62,D7,D7,B5), V(E6,AB,AB,4D), V(9A,76,76,EC), \
-    V(45,CA,CA,8F), V(9D,82,82,1F), V(40,C9,C9,89), V(87,7D,7D,FA), \
-    V(15,FA,FA,EF), V(EB,59,59,B2), V(C9,47,47,8E), V(0B,F0,F0,FB), \
-    V(EC,AD,AD,41), V(67,D4,D4,B3), V(FD,A2,A2,5F), V(EA,AF,AF,45), \
-    V(BF,9C,9C,23), V(F7,A4,A4,53), V(96,72,72,E4), V(5B,C0,C0,9B), \
-    V(C2,B7,B7,75), V(1C,FD,FD,E1), V(AE,93,93,3D), V(6A,26,26,4C), \
-    V(5A,36,36,6C), V(41,3F,3F,7E), V(02,F7,F7,F5), V(4F,CC,CC,83), \
-    V(5C,34,34,68), V(F4,A5,A5,51), V(34,E5,E5,D1), V(08,F1,F1,F9), \
-    V(93,71,71,E2), V(73,D8,D8,AB), V(53,31,31,62), V(3F,15,15,2A), \
-    V(0C,04,04,08), V(52,C7,C7,95), V(65,23,23,46), V(5E,C3,C3,9D), \
-    V(28,18,18,30), V(A1,96,96,37), V(0F,05,05,0A), V(B5,9A,9A,2F), \
-    V(09,07,07,0E), V(36,12,12,24), V(9B,80,80,1B), V(3D,E2,E2,DF), \
-    V(26,EB,EB,CD), V(69,27,27,4E), V(CD,B2,B2,7F), V(9F,75,75,EA), \
-    V(1B,09,09,12), V(9E,83,83,1D), V(74,2C,2C,58), V(2E,1A,1A,34), \
-    V(2D,1B,1B,36), V(B2,6E,6E,DC), V(EE,5A,5A,B4), V(FB,A0,A0,5B), \
-    V(F6,52,52,A4), V(4D,3B,3B,76), V(61,D6,D6,B7), V(CE,B3,B3,7D), \
-    V(7B,29,29,52), V(3E,E3,E3,DD), V(71,2F,2F,5E), V(97,84,84,13), \
-    V(F5,53,53,A6), V(68,D1,D1,B9), V(00,00,00,00), V(2C,ED,ED,C1), \
-    V(60,20,20,40), V(1F,FC,FC,E3), V(C8,B1,B1,79), V(ED,5B,5B,B6), \
-    V(BE,6A,6A,D4), V(46,CB,CB,8D), V(D9,BE,BE,67), V(4B,39,39,72), \
-    V(DE,4A,4A,94), V(D4,4C,4C,98), V(E8,58,58,B0), V(4A,CF,CF,85), \
-    V(6B,D0,D0,BB), V(2A,EF,EF,C5), V(E5,AA,AA,4F), V(16,FB,FB,ED), \
-    V(C5,43,43,86), V(D7,4D,4D,9A), V(55,33,33,66), V(94,85,85,11), \
-    V(CF,45,45,8A), V(10,F9,F9,E9), V(06,02,02,04), V(81,7F,7F,FE), \
-    V(F0,50,50,A0), V(44,3C,3C,78), V(BA,9F,9F,25), V(E3,A8,A8,4B), \
-    V(F3,51,51,A2), V(FE,A3,A3,5D), V(C0,40,40,80), V(8A,8F,8F,05), \
-    V(AD,92,92,3F), V(BC,9D,9D,21), V(48,38,38,70), V(04,F5,F5,F1), \
-    V(DF,BC,BC,63), V(C1,B6,B6,77), V(75,DA,DA,AF), V(63,21,21,42), \
-    V(30,10,10,20), V(1A,FF,FF,E5), V(0E,F3,F3,FD), V(6D,D2,D2,BF), \
-    V(4C,CD,CD,81), V(14,0C,0C,18), V(35,13,13,26), V(2F,EC,EC,C3), \
-    V(E1,5F,5F,BE), V(A2,97,97,35), V(CC,44,44,88), V(39,17,17,2E), \
-    V(57,C4,C4,93), V(F2,A7,A7,55), V(82,7E,7E,FC), V(47,3D,3D,7A), \
-    V(AC,64,64,C8), V(E7,5D,5D,BA), V(2B,19,19,32), V(95,73,73,E6), \
-    V(A0,60,60,C0), V(98,81,81,19), V(D1,4F,4F,9E), V(7F,DC,DC,A3), \
-    V(66,22,22,44), V(7E,2A,2A,54), V(AB,90,90,3B), V(83,88,88,0B), \
-    V(CA,46,46,8C), V(29,EE,EE,C7), V(D3,B8,B8,6B), V(3C,14,14,28), \
-    V(79,DE,DE,A7), V(E2,5E,5E,BC), V(1D,0B,0B,16), V(76,DB,DB,AD), \
-    V(3B,E0,E0,DB), V(56,32,32,64), V(4E,3A,3A,74), V(1E,0A,0A,14), \
-    V(DB,49,49,92), V(0A,06,06,0C), V(6C,24,24,48), V(E4,5C,5C,B8), \
-    V(5D,C2,C2,9F), V(6E,D3,D3,BD), V(EF,AC,AC,43), V(A6,62,62,C4), \
-    V(A8,91,91,39), V(A4,95,95,31), V(37,E4,E4,D3), V(8B,79,79,F2), \
-    V(32,E7,E7,D5), V(43,C8,C8,8B), V(59,37,37,6E), V(B7,6D,6D,DA), \
-    V(8C,8D,8D,01), V(64,D5,D5,B1), V(D2,4E,4E,9C), V(E0,A9,A9,49), \
-    V(B4,6C,6C,D8), V(FA,56,56,AC), V(07,F4,F4,F3), V(25,EA,EA,CF), \
-    V(AF,65,65,CA), V(8E,7A,7A,F4), V(E9,AE,AE,47), V(18,08,08,10), \
-    V(D5,BA,BA,6F), V(88,78,78,F0), V(6F,25,25,4A), V(72,2E,2E,5C), \
-    V(24,1C,1C,38), V(F1,A6,A6,57), V(C7,B4,B4,73), V(51,C6,C6,97), \
-    V(23,E8,E8,CB), V(7C,DD,DD,A1), V(9C,74,74,E8), V(21,1F,1F,3E), \
-    V(DD,4B,4B,96), V(DC,BD,BD,61), V(86,8B,8B,0D), V(85,8A,8A,0F), \
-    V(90,70,70,E0), V(42,3E,3E,7C), V(C4,B5,B5,71), V(AA,66,66,CC), \
-    V(D8,48,48,90), V(05,03,03,06), V(01,F6,F6,F7), V(12,0E,0E,1C), \
-    V(A3,61,61,C2), V(5F,35,35,6A), V(F9,57,57,AE), V(D0,B9,B9,69), \
-    V(91,86,86,17), V(58,C1,C1,99), V(27,1D,1D,3A), V(B9,9E,9E,27), \
-    V(38,E1,E1,D9), V(13,F8,F8,EB), V(B3,98,98,2B), V(33,11,11,22), \
-    V(BB,69,69,D2), V(70,D9,D9,A9), V(89,8E,8E,07), V(A7,94,94,33), \
-    V(B6,9B,9B,2D), V(22,1E,1E,3C), V(92,87,87,15), V(20,E9,E9,C9), \
-    V(49,CE,CE,87), V(FF,55,55,AA), V(78,28,28,50), V(7A,DF,DF,A5), \
-    V(8F,8C,8C,03), V(F8,A1,A1,59), V(80,89,89,09), V(17,0D,0D,1A), \
-    V(DA,BF,BF,65), V(31,E6,E6,D7), V(C6,42,42,84), V(B8,68,68,D0), \
-    V(C3,41,41,82), V(B0,99,99,29), V(77,2D,2D,5A), V(11,0F,0F,1E), \
-    V(CB,B0,B0,7B), V(FC,54,54,A8), V(D6,BB,BB,6D), V(3A,16,16,2C)
-
-#define V(a,b,c,d) 0x##a##b##c##d
-const uint32_t FT0[256] __attribute__((section(".sys.0"))) = { FT };
-#undef V
-
-#define V(a,b,c,d) 0x##b##c##d##a
-const uint32_t FT1[256] __attribute__((section(".sys.1"))) = { FT };
-#undef V
-
-#define V(a,b,c,d) 0x##c##d##a##b
-const uint32_t FT2[256] __attribute__((section(".sys.2"))) = { FT };
-#undef V
-
-#ifdef ORIGINAL_IMPLEMENTATION 
-#define V(a,b,c,d) 0x##d##a##b##c
-const uint32_t FT3[256] = { FT };
-#undef V
-#endif
--- a/example-cdc/board.h
+++ b/example-cdc/board.h
@@ -0,0 +1 @@
+../board/board-fst-01.h
--- a/example-cdc/sample.c
+++ b/example-cdc/sample.c
@@ -2,16 +2,18 @@
 #include <stdlib.h>
 #include <string.h>
 #include <chopstx.h>
-#include "sys.h" /* for set_led */
-#include "usb_lld.h" /* for set_led */
+
+#include "usb_lld.h"
+#include "tty.h"
+
+/* For set_led */
+#include "board.h"
+#include "sys.h"

 static chopstx_mutex_t mtx;
 static chopstx_cond_t cnd0;
 static chopstx_cond_t cnd1;

-chopstx_mutex_t usb_mtx;
-chopstx_cond_t cnd_usb;
-
 static uint8_t u, v;
 static uint8_t m;		/* 0..100 */

@@ -55,67 +57,23 @@ blk (void *arg)
  return NULL;
 }

-#define INTR_REQ_USB 20
-
-static void *
-usb_intr (void *arg)
-{
-  extern void usb_lld_init (uint8_t feature);
-  extern void usb_interrupt_handler (void);
-
-  chopstx_intr_t interrupt;
-
-  (void)arg;
-  usb_lld_init (0x80);		/* Bus powered. */
-  chopstx_claim_irq (&interrupt, INTR_REQ_USB);
-
-  /*
-   * When USB interrupt occurs between usb_lld_init (which assumes
-   * ISR) and chopstx_claim_irq (which clears pending interrupt),
-   * invocation of usb_interrupt_handler won't occur.
-   *
-   * We can't call usb_lld_init after chopstx_claim_irq, as
-   * usb_lld_init does its own setting for NVIC.  Calling
-   * chopstx_claim_irq after usb_lld_init overrides that.
-   *
-   * Calling usb_interrupt_handler is no harm even if there were no
-   * interrupts, thus, we call it unconditionally here, just in case
-   * if there is a request.
-   *
-   */
-  usb_interrupt_handler ();
-
-  while (1)
-    {
-      chopstx_intr_wait (&interrupt);
-
-      /* Process interrupt. */
-      usb_interrupt_handler ();
-    }
-
-  chopstx_release_irq (&interrupt);
-  return NULL;
-}

 #define PRIO_PWM 3
 #define PRIO_BLK 2
-#define PRIO_INTR 4

-extern uint8_t __process1_stack_base__, __process1_stack_size__;
-extern uint8_t __process2_stack_base__, __process2_stack_size__;
-extern uint8_t __process3_stack_base__, __process3_stack_size__;
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];

-const uint32_t __stackaddr_pwm = (uint32_t)&__process1_stack_base__;
-const size_t __stacksize_pwm = (size_t)&__process1_stack_size__;
+#define STACK_ADDR_PWM ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_PWM ((uint32_t)__process1_stack_size__)

-const uint32_t __stackaddr_blk = (uint32_t)&__process2_stack_base__;
-const size_t __stacksize_blk = (size_t)&__process2_stack_size__;
+#define STACK_ADDR_BLK ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BLK ((uint32_t)__process2_stack_size__)

-const uint32_t __stackaddr_intr = (uint32_t)&__process3_stack_base__;
-const size_t __stacksize_intr = (size_t)&__process3_stack_size__;

 static char hexchar (uint8_t x)
 {
+  x &= 0x0f;
  if (x <= 0x09)
    return '0' + x;
  else if (x <= 0x0f)
@@ -128,6 +86,7 @@ static char hexchar (uint8_t x)
 int
 main (int argc, const char *argv[])
 {
+  struct tty *tty;
  uint8_t count;

  (void)argc;
@@ -137,15 +96,10 @@ main (int argc, const char *argv[])
  chopstx_cond_init (&cnd0);
  chopstx_cond_init (&cnd1);

-  chopstx_mutex_init (&usb_mtx);
-  chopstx_cond_init (&cnd_usb);
-
  m = 10;

-  chopstx_create (PRIO_PWM, __stackaddr_pwm, __stacksize_pwm, pwm, NULL);
-  chopstx_create (PRIO_BLK, __stackaddr_blk, __stacksize_blk, blk, NULL);
-  chopstx_create (PRIO_INTR, __stackaddr_intr, __stacksize_intr,
-		  usb_intr, NULL);
+  chopstx_create (PRIO_PWM, STACK_ADDR_PWM, STACK_SIZE_PWM, pwm, NULL);
+  chopstx_create (PRIO_BLK, STACK_ADDR_BLK, STACK_SIZE_BLK, blk, NULL);

  chopstx_usec_wait (200*1000);

@@ -154,41 +108,59 @@ main (int argc, const char *argv[])
  chopstx_cond_signal (&cnd1);
  chopstx_mutex_unlock (&mtx);

-  while (1)
-    {
-      extern uint8_t connected;
-
-      count= 0;
  u = 1;
-      /* waiting USB connection */
-      chopstx_mutex_lock (&usb_mtx);
-      if (!connected)
-	chopstx_cond_wait (&cnd_usb, &usb_mtx);
-      chopstx_mutex_unlock (&usb_mtx);

+  tty = tty_open ();
+  tty_wait_configured (tty);
+
+  count = 0;
+  m = 50;
  while (1)
    {
-	  char s[32];
+      char s[LINEBUFSIZE];

-	  u ^= 1;
-	  chopstx_usec_wait (200*1000*6);
+      u = 1;
+      tty_wait_connection (tty);
+
+      chopstx_usec_wait (50*1000);
+
+      /* Send ZLP at the beginning.  */
+      tty_send (tty, s, 0);

      memcpy (s, "xx: Hello, World with Chopstx!\r\n", 32);
      s[0] = hexchar (count >> 4);
      s[1] = hexchar (count & 0x0f);
      count++;

-	  chopstx_mutex_lock (&usb_mtx);
-	  if (connected)
+      if (tty_send (tty, s, 32) < 0)
+	continue;
+
+      while (1)
 	{
-	      usb_lld_write (ENDP1, s, 32);
-	      chopstx_cond_wait (&cnd_usb, &usb_mtx);
-	    }
-	  else
+	  int size;
+	  uint32_t usec;
+
+	  usec = 3000000;	/* 3.0 seconds */
+	  size = tty_recv (tty, s + 4, &usec);
+	  if (size < 0)
+	    break;
+
+	  if (size)
+	    {
+	      size--;
+
+	      s[0] = hexchar (size >> 4);
+	      s[1] = hexchar (size & 0x0f);
+	      s[2] = ':';
+	      s[3] = ' ';
+	      s[size + 4] = '\r';
+	      s[size + 5] = '\n';
+	      if (tty_send (tty, s, size + 6) < 0)
 		break;
-	  chopstx_mutex_unlock (&usb_mtx);
 	    }
-      chopstx_mutex_unlock (&usb_mtx);
+
+	  u ^= 1;
+	}
    }

  return 0;
--- a/example-cdc/sample.ld
+++ b/example-cdc/sample.ld
@@ -1,11 +1,11 @@
 /*
 * ST32F103 memory setup.
 */
-__main_stack_size__     = 0x0100;  /* Exception handlers     */
-__process0_stack_size__  = 0x0100;  /* Main program           */
-__process1_stack_size__  = 0x0100; /* first thread program */
-__process2_stack_size__  = 0x0100; /* second thread program */
-__process3_stack_size__  = 0x0100; /* third thread program */
+__main_stack_size__      = 0x0100; /* Idle+Exception handlers */
+__process0_stack_size__  = 0x0400; /* Main program            */
+__process1_stack_size__  = 0x0200; /* first thread program    */
+__process2_stack_size__  = 0x0200; /* second thread program   */
+__process3_stack_size__  = 0x0200; /* third thread program    */

 MEMORY
 {
@@ -14,9 +14,6 @@ MEMORY
    ram : org = 0x20000000, len = 20k
 }

-__flash_start__ = 0x08001000;
-__flash_end__   = 0x08020000;
-
 __ram_start__           = ORIGIN(ram);
 __ram_size__            = 20k;
 __ram_end__             = __ram_start__ + __ram_size__;
@@ -25,16 +22,18 @@ SECTIONS
 {
    . = 0;

-    .sys : ALIGN(16) SUBALIGN(16)
+    .sys : ALIGN(4) SUBALIGN(4)
    {
 	_sys = .;
 	KEEP(*(.vectors))
 	. = ALIGN(16);
-	*(.sys.version)
-	build/sys.o(.text)
-	build/sys.o(.text.*)
-        build/sys.o(.rodata)
-	build/sys.o(.rodata.*)
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
 	. = ALIGN(1024);
 	*(.sys.0)
 	*(.sys.1)
@@ -59,6 +58,7 @@ SECTIONS
        *(.glue_7t)
        *(.glue_7)
        *(.gcc*)
+	. = ALIGN(8);
    } > flash

    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
--- a/example-cdc/tty.h
+++ b/example-cdc/tty.h
@@ -0,0 +1,9 @@
+#define LINEBUFSIZE 128
+
+struct tty;
+
+struct tty *tty_open (void);
+void tty_wait_configured (struct tty *tty);
+void tty_wait_connection (struct tty *tty);
+int tty_send (struct tty *tty, const char *buf, int count);
+int tty_recv (struct tty *tty, char *buf, uint32_t *timeout);
--- a/example-cdc/usb-cdc.c
+++ b/example-cdc/usb-cdc.c
--- a/example-cdc/usb_lld.h
+++ b/example-cdc/usb_lld.h
@@ -1,141 +0,0 @@
-#define USB_DEVICE_DESCRIPTOR_TYPE              0x01
-#define USB_CONFIGURATION_DESCRIPTOR_TYPE       0x02
-#define USB_STRING_DESCRIPTOR_TYPE              0x03
-#define USB_INTERFACE_DESCRIPTOR_TYPE           0x04
-#define USB_ENDPOINT_DESCRIPTOR_TYPE            0x05
-
-#define STANDARD_ENDPOINT_DESC_SIZE             0x09
-
-/* endpoints enumeration */
-#define ENDP0       ((uint8_t)0)
-#define ENDP1       ((uint8_t)1)
-#define ENDP2       ((uint8_t)2)
-#define ENDP3       ((uint8_t)3)
-#define ENDP4       ((uint8_t)4)
-#define ENDP5       ((uint8_t)5)
-#define ENDP6       ((uint8_t)6)
-#define ENDP7       ((uint8_t)7)
-
-/* EP_TYPE[1:0] EndPoint TYPE */
-#define EP_BULK        (0x0000) /* EndPoint BULK        */
-#define EP_CONTROL     (0x0200) /* EndPoint CONTROL     */
-#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
-#define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT   */
-
-enum RECIPIENT_TYPE
-{
-  DEVICE_RECIPIENT,     /* Recipient device    */
-  INTERFACE_RECIPIENT,  /* Recipient interface */
-  ENDPOINT_RECIPIENT,   /* Recipient endpoint  */
-  OTHER_RECIPIENT
-};
-
-enum DESCRIPTOR_TYPE
-{
-  DEVICE_DESCRIPTOR = 1,
-  CONFIG_DESCRIPTOR,
-  STRING_DESCRIPTOR,
-  INTERFACE_DESCRIPTOR,
-  ENDPOINT_DESCRIPTOR
-};
-
-#define REQUEST_DIR       0x80  /* Mask to get request dir  */
-#define REQUEST_TYPE      0x60  /* Mask to get request type */
-#define STANDARD_REQUEST  0x00  /* Standard request         */
-#define CLASS_REQUEST     0x20  /* Class request            */
-#define VENDOR_REQUEST    0x40  /* Vendor request           */
-#define RECIPIENT         0x1F  /* Mask to get recipient    */
-
-#define USB_SETUP_SET(req) ((req & REQUEST_DIR) == 0)
-#define USB_SETUP_GET(req) ((req & REQUEST_DIR) != 0)
-
-enum
-{
-  USB_UNSUPPORT = 0,
-  USB_SUCCESS = 1,
-};
-
-void usb_cb_device_reset (void);
-void usb_cb_ctrl_write_finish (uint8_t req, uint8_t req_no,
-			       uint16_t value, uint16_t index, uint16_t len);
-int usb_cb_setup (uint8_t req, uint8_t req_no, uint16_t value,
-		  uint16_t index, uint16_t len);
-int usb_cb_get_descriptor (uint8_t desc_type, uint16_t index, uint16_t value);
-int usb_cb_handle_event (uint8_t event_type, uint16_t value);
-int usb_cb_interface (uint8_t cmd, uint16_t interface, uint16_t value);
-
-enum {
-  USB_EVENT_ADDRESS,
-  USB_EVENT_CONFIG,
-  USB_EVENT_SUSPEND,
-  USB_EVENT_WAKEUP,
-  USB_EVENT_STALL,
-};
-
-enum {
-  USB_SET_INTERFACE,
-  USB_GET_INTERFACE,
-  USB_QUERY_INTERFACE,
-};
-
-enum DEVICE_STATE
-{
-  UNCONNECTED,
-  ATTACHED,
-  POWERED,
-  SUSPENDED,
-  ADDRESSED,
-  CONFIGURED
-};
-
-extern const uint8_t usb_initial_feature;
-
-#define STM32_USB_IRQ_PRIORITY     11
-
-extern void usb_lld_init (uint8_t feature);
-
-extern void usb_lld_to_pmabuf (const void *src, uint16_t addr, size_t n);
-
-extern void usb_lld_from_pmabuf (void *dst, uint16_t addr, size_t n);
-
-extern void usb_lld_stall_tx (int ep_num);
-
-extern void usb_lld_stall_rx (int ep_num);
-
-extern int usb_lld_tx_data_len (int ep_num);
-
-extern void usb_lld_txcpy (const void *src, int ep_num, int offset, size_t len);
-
-extern void usb_lld_tx_enable (int ep_num, size_t len);
-
-extern void usb_lld_write (uint8_t ep_num, const void *buf, size_t len);
-
-extern void usb_lld_rx_enable (int ep_num);
-
-extern int usb_lld_rx_data_len (int ep_num);
-
-extern void usb_lld_rxcpy (uint8_t *dst, int ep_num, int offset, size_t len);
-
-extern void usb_lld_reset (void);
-
-extern void usb_lld_setup_endpoint (int ep_num, int ep_type, int ep_kind,
-				    int ep_rx_addr, int ep_tx_addr,
-				    int ep_rx_memory_size);
-
-extern void usb_lld_set_configuration (uint8_t config);
-
-extern uint8_t usb_lld_current_configuration (void);
-
-extern void usb_lld_set_feature (uint8_t feature);
-
-extern void usb_lld_set_data_to_send (const void *p, size_t len);
-
-extern inline void usb_lld_set_data_to_recv (void *p, size_t len)
-{
-  usb_lld_set_data_to_send ((const void *)p, len);
-}
-
-extern void usb_lld_prepare_shutdown (void);
-extern void usb_lld_shutdown (void);
-
-extern void usb_interrupt_handler (void);
--- a/example-fs-bb48/Makefile
+++ b/example-fs-bb48/Makefile
@@ -0,0 +1,36 @@
+# Makefile for example application of Chopstx
+
+PROJECT = sample
+
+### Currently, it's for FS-BB48.
+
+CHOPSTX = ..
+LDSCRIPT= sample.ld
+CSRC = sample.c usb-cdc.c command.c touch.c
+CHIP=mkl27z
+
+USE_SYS = yes
+USE_USB = yes
+USE_ADC = yes
+
+###################################
+CROSS = arm-none-eabi-
+CC   = $(CROSS)gcc
+LD   = $(CROSS)gcc
+OBJCOPY   = $(CROSS)objcopy
+
+MCU   = cortex-m0plus
+CWARN = -Wall -Wextra -Wstrict-prototypes
+DEFS  = -DFREE_STANDING -DMHZ=48 -DUSE_SYS3
+OPT   = -O3 -Os -g
+LIBS  =
+
+####################
+include ../rules.mk
+
+board.h:
+	@echo Please make a symbolic link \'board.h\' to a file in ../board;
+	@exit 1
+
+distclean: clean
+	rm -f board.h
--- a/example-fs-bb48/board.h
+++ b/example-fs-bb48/board.h
@@ -0,0 +1 @@
+../board/board-fs-bb48.h
--- a/example-fs-bb48/command.c
+++ b/example-fs-bb48/command.c
@@ -0,0 +1,542 @@
+#include <string.h>
+#include <stdint.h>
+#include <chopstx.h>
+#include "tty.h"
+#include "config.h"
+#ifdef ADC_SUPPORT
+#include "adc.h"
+static int adc_initialized = 0;
+#endif
+#include "board.h"
+#include "sys.h"
+
+struct command_table
+{
+  const char *name;
+  void (*handler) (struct tty *tty, const char *line);
+};
+
+/*
+ * Put a line (or lines) to TTY.
+ * LINE should be terminated with newline.
+ */
+static void
+put_line (struct tty *tty, const char *line)
+{
+  tty_send (tty, line, strlen (line));
+}
+
+static const char *help_string = 
+  "mdw ADDR [COUNT];       memory display word\r\n"
+  "mww ADDR VALUE [COUNT]; memory write word\r\n"
+  "fes ADDR [COUNT];       flash erase sector\r\n"
+  "fww ADDR VALUE [COUNT]; flash write word\r\n"
+#ifdef CRC32_SUPPORT
+  "crc32 string;           CRC32 calc string\r\n"
+#endif
+#ifdef ADC_SUPPORT
+  "adc;                    get 256-byte from ADC\r\n"
+#endif
+  "sysinfo;                system information\r\n"
+  "help\r\n";
+
+static char hexchar (uint8_t x)
+{
+  x &= 0x0f;
+  if (x <= 0x09)
+    return '0' + x;
+  else if (x <= 0x0f)
+    return 'a' + x - 10;
+  else
+    return '?';
+}
+
+static char *
+compose_decimal (char *s, int value)
+{
+  uint32_t v;
+  int col = 1000000000;
+  int d;
+  int digit_output = 0;
+
+  if (value < 0)
+    {
+      *s++ = '-';
+      v = 1 + ~((uint32_t)value);
+    }
+  else
+    v = (uint32_t)value;
+
+  while (col >= 10)
+    {
+      if (v >= (uint32_t)col)
+	{
+	  d = v / col;
+	  v = v - d * col;
+	  *s++ = d + '0';
+	  digit_output = 1;
+	}
+      else if (digit_output)
+	*s++ = '0';
+
+      col = col / 10;
+    }
+
+  *s++ = v + '0';
+
+  return s;
+}
+
+
+static char *
+compose_hex (char *s, uint32_t v)
+{
+  s[0] = hexchar (v >> 28);
+  s[1] = hexchar (v >> 24);
+  s[2] = hexchar (v >> 20);
+  s[3] = hexchar (v >> 16);
+  s[4] = hexchar (v >> 12);
+  s[5] = hexchar (v >> 8);
+  s[6] = hexchar (v >> 4);
+  s[7] = hexchar (v);
+  return s+8;
+}
+
+static const char *
+get_hex (struct tty *tty, const char *s, uint32_t *v_p)
+{
+  uint32_t v = 0;
+  char c;
+
+  if (s[0] == '0' && s[1] == 'x')
+    s = s + 2;
+  while (1)
+    {
+      c = *s++;
+
+      if (c == 0)
+	{
+	  s--;
+	  break;
+	}
+
+      if (c == ' ')
+	break;
+
+      v = (v << 4);
+      if (c >= '0' && c <= '9')
+	v += (c - '0');
+      else if (c >= 'a' && c <= 'f')
+	v += (c - 'a') + 10;
+      else if (c >= 'A' && c <= 'F')
+	v += (c - 'A') + 10;
+      else
+	{
+	  put_line (tty, "hex error\r\n");
+	  return NULL;
+	}
+    }
+
+  *v_p = v;
+  return s;
+}
+
+
+#define TOUCH_VALUE_HIGH 100
+#define TOUCH_VALUE_LOW  50
+static void
+cmd_button (struct tty *tty, const char *line)
+{
+  int i = 0;
+  extern uint16_t touch_get (void);
+  uint16_t v0 = 0;
+  int touched = 0;
+
+  (void)line;
+  put_line (tty, "Please touch the bear.\r\n");
+
+  while (i < 16)
+    {
+      uint16_t v = touch_get ();
+      v0 = (v0 * 2 + v)/3;
+
+      if (touched == 0 && v0 > TOUCH_VALUE_HIGH)
+	{
+	  tty_send (tty, "!", 1);
+	  touched = 1;
+	}
+      else if (touched == 1 && v0 < TOUCH_VALUE_LOW)
+	{
+	  tty_send (tty, ".", 1);
+	  touched = 0;
+	  i++;
+	}
+
+      chopstx_usec_wait (10*1000);
+    }
+
+  tty_send (tty, "\r\n", 2);
+}
+
+
+static void
+cmd_touch (struct tty *tty, const char *line)
+{
+  int i;
+  extern uint16_t touch_get (void);
+
+  (void)line;
+  put_line (tty, "Please touch the bear.\r\n");
+
+  for (i = 0; i < 20; i++)
+    {
+      uint16_t v;
+      char output[8];
+      char *s;
+
+      chopstx_usec_wait (1000*1000);
+      v = touch_get ();
+      s = compose_decimal (output, v);
+      *s++ = '\r';
+      *s++ = '\n';
+      tty_send (tty, output, s - output);
+    }
+}
+
+
+static void
+cmd_mdw (struct tty *tty, const char *line)
+{
+  int i;
+  uint32_t addr = 0;
+  int count = 0;
+  char c;
+  const char *s = line;
+  
+  s = get_hex (tty, s, &addr);
+  addr &= ~3;
+  if (s == NULL)
+    return;
+
+  if (*s == 0)
+    count = 1;
+  else
+    {
+      while (1)
+	{
+	  c = *s++;
+
+	  if (c == 0 || c == ' ')
+	    break;
+
+	  count = count * 10;
+	  if (c >= '0' && c <= '9')
+	    count += c - '0';
+	  else
+	    {
+	      put_line (tty, "mdw error\r\n");
+	      return;
+	    }
+	}
+    }
+
+  i = 0;
+  while (i < count)
+    {
+      uint32_t v;
+      char output[48];
+      char *s;
+
+      s = compose_hex (output, addr);
+      *s++ = ':';
+      *s++ = ' ';
+
+      while (1)
+	{
+	  v = *(uint32_t *)addr;
+	  s = compose_hex (s, v);
+	  i++;
+	  addr += 4;
+	  if (i >= count || (i % 4) == 0)
+	    break;
+	  *s++ = ' ';
+	}
+
+      *s++ = '\r';
+      *s++ = '\n';
+      tty_send (tty, output, s - output);
+    }
+}
+
+static void
+cmd_mww (struct tty *tty, const char *line)
+{
+  (void)tty;
+  (void)line;
+  put_line (tty, "mww not yet supported\r\n");
+}
+
+static void
+cmd_fes (struct tty *tty, const char *line)
+{
+  int i;
+  uint32_t addr = 0;
+  int count = 0;
+  char c;
+  const char *s = line;
+  
+  s = get_hex (tty, s, &addr);
+  if (s == NULL)
+    return;
+
+  if (*s == 0)
+    count = 1;
+  else
+    {
+      while (1)
+	{
+	  c = *s++;
+
+	  if (c == 0 || c == ' ')
+	    break;
+
+	  count = count * 10;
+	  if (c >= '0' && c <= '9')
+	    count += c - '0';
+	  else
+	    {
+	      put_line (tty, "fww error\r\n");
+	      return;
+	    }
+	}
+    }
+
+  for (i = 0; i < count; i++)
+    {
+      flash_erase_page (addr);
+      addr += 1024;
+    }
+}
+
+static void
+cmd_fww (struct tty *tty, const char *line)
+{
+  int i;
+  uint32_t addr = 0;
+  uint32_t value = 0;
+  int count = 0;
+  char c;
+  const char *s = line;
+  
+  s = get_hex (tty, s, &addr);
+  if (s == NULL)
+    return;
+
+  if (*s == 0)
+    return;
+
+  s = get_hex (tty, s, &value);
+  if (s == NULL)
+    return;
+
+  if (*s == 0)
+    count = 1;
+  else
+    {
+      while (1)
+	{
+	  c = *s++;
+
+	  if (c == 0 || c == ' ')
+	    break;
+
+	  count = count * 10;
+	  if (c >= '0' && c <= '9')
+	    count += c - '0';
+	  else
+	    {
+	      put_line (tty, "fww error\r\n");
+	      return;
+	    }
+	}
+    }
+
+  for (i = 0; i < count; i++)
+    {
+      flash_program_word (addr, value);
+      addr += 4;
+    }
+}
+
+
+#ifdef CRC32_SUPPORT
+static unsigned int crc_value;
+
+static void
+cmd_crc32  (struct tty *tty, const char *line)
+{
+  uint32_t v;
+  char string[10];
+  char *s;
+
+  crc32_init (&crc_value);
+  while (*line)
+    crc32_u8 (&crc_value, *line++);
+  v = crc_value ^ 0xffffffff;
+
+  s = compose_hex (string, v);
+  *s++ = '\r';
+  *s++ = '\n';
+  tty_send (tty, string, sizeof (string));
+}
+#endif
+
+#ifdef ADC_SUPPORT
+static void
+cmd_adc  (struct tty *tty, const char *line)
+{
+  int i;
+  char output[73];
+  char *s;
+
+  (void)line;
+
+  if (!adc_initialized)
+    {
+      if (adc_init ())
+	{
+	  put_line (tty, "adc_init error\r\n");
+	  return;
+	}
+      else
+	{
+	  adc_start ();
+	  adc_initialized = 1;
+	}
+    }
+
+  adc_start_conversion (0, 64);
+  adc_wait_completion ();
+
+  i = 0;
+  s = output;
+  while (1)
+    {
+      s = compose_hex (s, adc_buf[i]);
+      i++;
+      if ((i % 8))
+	*s++ = ' ';
+      else
+	{
+	  *s++ = '\r';
+	  *s++ = '\n';
+	  tty_send (tty, output, s - output);
+	  s = output;
+	  if (i >= 64)
+	    break;
+	}
+    }
+}
+#endif
+
+static void
+cmd_sysinfo (struct tty *tty, const char *line)
+{
+  char output[73];
+  char *s;
+  int i;
+
+  (void)line;
+  memcpy (output, "SYS version: ", 13);
+  s = output + 13; 
+  *s++ = sys_version[2];
+  *s++ = sys_version[4];
+  *s++ = sys_version[6];
+  *s++ = '\r';
+  *s++ = '\n';
+  tty_send (tty, output, s - output);
+
+  memcpy (output, "Board ID: ", 10);
+  s = output + 10; 
+  s = compose_hex (s, sys_board_id);
+  *s++ = '\r';
+  *s++ = '\n';
+  tty_send (tty, output, s - output);
+
+  memcpy (output, "Board name: ", 12);
+  s = output + 12; 
+  for (i = 0; i < (int)sizeof (output) - 2; i ++)
+    if ((*s = sys_board_name[i]) == 0)
+      break;
+    else
+      s++;
+
+  *s++ = '\r';
+  *s++ = '\n';
+  tty_send (tty, output, s - output);
+}
+
+
+static void
+cmd_help (struct tty *tty, const char *line)
+{
+  (void)line;
+  put_line (tty, help_string);
+}
+
+
+struct command_table command_table[] = {
+  { "button", cmd_button },
+  { "touch", cmd_touch },
+  { "mdw", cmd_mdw },
+  { "mww", cmd_mww },
+  { "fes", cmd_fes },
+  { "fww", cmd_fww },
+#ifdef CRC32_SUPPORT
+  { "crc32", cmd_crc32 },
+#endif
+#ifdef ADC_SUPPORT
+  { "adc", cmd_adc },
+#endif
+  { "sysinfo", cmd_sysinfo },
+  { "help", cmd_help },
+};
+
+#define N_CMDS (int)(sizeof (command_table) / sizeof (struct command_table))
+
+
+/*
+ * Dispatch a command parsing LINE.
+ * Line is NULL terminated with no newline.
+ */
+void
+cmd_dispatch (struct tty *tty, const char *line)
+{
+  int i;
+  const char *p;
+  unsigned int n = 0;
+
+  p = line;
+  while (*p)
+    {
+      if (*p++ == ' ')
+	break;
+      n++;
+    }
+
+  for (i = 0; i < N_CMDS; i++)
+    if (n == strlen (command_table[i].name)
+	&& strncmp ((const char *)line, command_table[i].name, n) == 0)
+      break;
+
+  if (i != N_CMDS)
+    (*command_table[i].handler) (tty, p);
+  else
+    {
+      char crlf[] = { '\r', '\n' };
+
+      put_line (tty, "No such command: ");
+      tty_send (tty, line, n);
+      tty_send (tty, crlf, sizeof (crlf));
+    }
+}
--- a/example-fs-bb48/command.h
+++ b/example-fs-bb48/command.h
@@ -0,0 +1 @@
+void cmd_dispatch (struct tty *tty, const char *line);
--- a/example-fs-bb48/config.h
+++ b/example-fs-bb48/config.h
@@ -0,0 +1,2 @@
+#define CRC32_SUPPORT
+#define ADC_SUPPORT
--- a/example-fs-bb48/crc32.c
+++ b/example-fs-bb48/crc32.c
@@ -0,0 +1,22 @@
+const unsigned int *const crc32_table= (const unsigned int *)0x00000480;
+
+void
+crc32_init (unsigned int *p)
+{
+  *p = 0xffffffff;
+}
+
+static void
+crc32_u8 (unsigned int *p, unsigned char v)
+{
+  *p = crc32_table[(*p & 0xff) ^ v] ^ (*p >> 8);
+}
+
+void
+crc32_u32 (unsigned int *p, unsigned int u)
+{
+  crc32_u8 (p, u & 0xff);
+  crc32_u8 (p, (u >> 8)& 0xff);
+  crc32_u8 (p, (u >> 16)& 0xff);
+  crc32_u8 (p, (u >> 24)& 0xff);
+}
--- a/example-fs-bb48/gen_crc_table.py
+++ b/example-fs-bb48/gen_crc_table.py
@@ -0,0 +1,22 @@
+# 
+# Polynomial for CRC32:
+#    x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
+#
+# When it is represented in binary, it's:
+#    0x04C11DB7
+#    =
+#    0000 0100 1100 0001 0001 1101 1011 0111
+# 
+# When we put in reverse bit-order, it's
+#    0xedb88320
+
+for i in range(0,256):
+    c = i
+    for j in range(0,8):
+        if (c&1):
+            c = 0xEDB88320 ^ (c >> 1)
+        else:
+            c = c >> 1
+    print("0x%08x," % c),
+    if (i % 6) == 5:
+        print("")
--- a/example-fs-bb48/sample.c
+++ b/example-fs-bb48/sample.c
@@ -0,0 +1,189 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <chopstx.h>
+
+#include "usb_lld.h"
+#include "tty.h"
+#include "board.h"
+#include "command.h"
+#include <sys.h>
+
+static chopstx_mutex_t mtx;
+static chopstx_cond_t cnd0;
+static chopstx_cond_t cnd1;
+
+uint8_t u;
+static uint8_t v;
+static uint8_t m;		/* 0..100 */
+
+static void
+wait_for (uint32_t usec)
+{
+#if defined(BUSY_LOOP)
+  uint32_t count = usec * 6;
+  uint32_t i;
+
+  for (i = 0; i < count; i++)
+    asm volatile ("" : : "r" (i) : "memory");
+#else
+  chopstx_usec_wait (usec);
+#endif
+}
+
+static void *
+pwm (void *arg)
+{
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd0, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (1)
+    {
+      set_led (u&v);
+      wait_for (m);
+      set_led (0);
+      wait_for (100-m);
+    }
+
+  return NULL;
+}
+
+static void *
+blk (void *arg)
+{
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd1, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (1)
+    {
+      v = 0;
+      wait_for (200*1000);
+      v = 1;
+      wait_for (200*1000);
+    }
+
+  return NULL;
+}
+
+
+#define PRIO_PWM 3
+#define PRIO_BLK 2
+
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
+
+#define STACK_ADDR_PWM ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_PWM ((uint32_t)__process1_stack_size__)
+
+#define STACK_ADDR_BLK ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BLK ((uint32_t)__process2_stack_size__)
+
+
+static char hexchar (uint8_t x)
+{
+  x &= 0x0f;
+  if (x <= 0x09)
+    return '0' + x;
+  else if (x <= 0x0f)
+    return 'a' + x - 10;
+  else
+    return '?';
+}
+
+
+extern void touch_init (void);
+
+int
+main (int argc, const char *argv[])
+{
+  struct tty *tty;
+  uint8_t count;
+
+  (void)argc;
+  (void)argv;
+
+  chopstx_mutex_init (&mtx);
+  chopstx_cond_init (&cnd0);
+  chopstx_cond_init (&cnd1);
+
+  m = 10;
+
+  chopstx_create (PRIO_PWM, STACK_ADDR_PWM, STACK_SIZE_PWM, pwm, NULL);
+  chopstx_create (PRIO_BLK, STACK_ADDR_BLK, STACK_SIZE_BLK, blk, NULL);
+
+  chopstx_usec_wait (200*1000);
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_signal (&cnd0);
+  chopstx_cond_signal (&cnd1);
+  chopstx_mutex_unlock (&mtx);
+
+  u = 1;
+
+  touch_init ();
+
+  tty = tty_open ();
+  tty_wait_configured (tty);
+
+  count = 0;
+  m = 50;
+  while (1)
+    {
+      char s[LINEBUFSIZE];
+
+    connection_loop:
+      u = 1;
+      tty_wait_connection (tty);
+
+      chopstx_usec_wait (50*1000);
+
+      /* Send ZLP at the beginning.  */
+      tty_send (tty, s, 0);
+
+      memcpy (s, "xx: Hello, World with Chopstx!\r\n", 32);
+      s[0] = hexchar (count >> 4);
+      s[1] = hexchar (count & 0x0f);
+      count++;
+
+      if (tty_send (tty, s, 32) < 0)
+	continue;
+
+      while (1)
+	{
+	  uint32_t usec;
+
+	  /* Prompt */
+	  if (tty_send (tty, "> ", 2) < 0)
+	    break;
+
+	  usec = 3000000;	/* 3.0 seconds */
+	  while (1)
+	    {
+	      int size = tty_recv (tty, s, &usec);
+	      u ^= 1;
+
+	      if (size < 0)
+		goto connection_loop;
+
+	      if (size == 1)
+		/* Do nothing but prompt again.  */
+		break;
+	      else if (size)
+		{
+		  /* Newline into NUL */
+		  s[size - 1] = 0;
+		  cmd_dispatch (tty, (char *)s);
+		  break;
+		}
+	    }
+	}
+    }
+
+  return 0;
+}
--- a/example-fs-bb48/sample.ld
+++ b/example-fs-bb48/sample.ld
@@ -0,0 +1,150 @@
+/*
+ * MK27Z memory setup.
+ */
+__main_stack_size__      = 0x0100; /* Idle+Exception handlers */
+__process0_stack_size__  = 0x0300; /* Main program            */
+__process1_stack_size__  = 0x0200; /* first thread program    */
+__process2_stack_size__  = 0x0100; /* second thread program   */
+__process3_stack_size__  = 0x0200; /* third thread program    */
+
+MEMORY
+{
+    flash  : org = 0x00000000, len = 256k
+    ram : org = 0x1fffe000, len = 32k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 32k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    _text = .;
+
+    .text : ALIGN(16) SUBALIGN(8)
+    {
+        KEEP(*(.first_page.first_words))
+        KEEP(*(.sys.version))
+        KEEP(*(.sys.board_info))
+        KEEP(*(.sys.vectors))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+        KEEP(*(.flash_config))
+	KEEP(*(.fixed_function.reset))
+	KEEP(*(.fixed_function.flash_do_internal))
+	KEEP(*(.fixed_function.flash_do))
+	KEEP(*(.fixed_function.flash_erase_page))
+	KEEP(*(.fixed_function.flash_program_word))
+	KEEP(*(.fixed_function.crc32_init))
+	KEEP(*(.fixed_function.crc32_u8))
+	KEEP(*(.fixed_function.crc32_u32))
+	/*
+	 * Because of alignment requirement
+	 * of startup.vectors, align to 256.
+	 */
+	. = ALIGN(256);
+        KEEP(*(.crc32_table))
+        KEEP(*(.startup.vectors))
+	. = ALIGN(16);
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash =0xffffffff
+
+    /DISCARD/ :
+    {
+        *(.bss.startup.0)
+    }
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash =0xffffffff
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .process_stack :
+    {
+        . = ALIGN(8);
+        __process3_stack_base__ = .;
+        . += __process3_stack_size__;
+        . = ALIGN(8);
+        __process3_stack_end__ = .;
+        __process2_stack_base__ = .;
+        . += __process2_stack_size__;
+        . = ALIGN(8);
+        __process2_stack_end__ = .;
+        __process1_stack_base__ = .;
+        . += __process1_stack_size__;
+        . = ALIGN(8);
+        __process1_stack_end__ = .;
+        __process0_stack_base__ = .;
+        . += __process0_stack_size__;
+        . = ALIGN(8);
+        __process0_stack_end__ = .;
+    } > ram
+
+    .main_stack :
+    {
+        . = ALIGN(8);
+        __main_stack_base__ = .;
+        . += __main_stack_size__;
+        . = ALIGN(8);
+        __main_stack_end__ = .;
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash =0xffffffff
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(512);
+	__usb_bdt__ = .;
+        . += 512;
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;
--- a/example-fs-bb48/touch.c
+++ b/example-fs-bb48/touch.c
@@ -0,0 +1,98 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <mcu/mkl27z.h>
+
+struct TPM {
+  volatile uint32_t SC;
+  volatile uint32_t CNT;
+  volatile uint32_t MOD;
+  volatile uint32_t C0SC;
+  volatile uint32_t C0V;
+  volatile uint32_t C1SC;
+  volatile uint32_t C1V;
+  uint32_t rsvd0[13];
+  volatile uint32_t STATUS;
+  uint32_t rsvd1[7];
+  volatile uint32_t POL;
+  uint32_t rsvd2[4];
+  volatile uint32_t CONF;
+};
+
+static struct TPM *const TPM1 = (struct TPM *)0x40039000;
+
+static chopstx_intr_t tpm1_intr;
+#define INTR_REQ_TPM1 18
+
+static void
+gpio_assert_low (void)
+{
+  /* Assert LOW.  */ 
+  PORTB->PCR1 = (1<<8) /* GPIO                  */
+              | (0<<6) /* DriveStrengthEnable=0 */
+              | (0<<4) /* PassiveFilterEnable=0 */
+              | (1<<2) /* SlewRateEnable = slow */
+              | (0<<1) /* pull enable = 0       */ 
+              | (0<<0) /* pull up select= 0         */
+              ;
+
+  GPIOB->PCOR = (1 << 1);            /* PTB1: Clear: Output 0  */
+}
+
+uint16_t
+touch_get (void)
+{
+  chopstx_prio_t prio_old;
+  uint16_t v;
+
+  prio_old = chopstx_setpriority (CHOPSTX_PRIO_INHIBIT_PREEMPTION);
+  /* 
+   * Start the timer's counter. 
+   * TOF clear, TOIE=1, CPWMS=0, CMOD=1, PS=011.
+   */
+  TPM1->SC = 0xcb;
+
+  /* Let the register to pull it up.  */
+  PORTB->PCR1 = (3<<8) /* TPM1_CH1              */
+              | (0<<6) /* DriveStrengthEnable=0 */
+              | (0<<4) /* PassiveFilterEnable=0 */
+              | (1<<2) /* SlewRateEnable = slow */
+              | (0<<1) /* pull enable = 0       */ 
+              | (0<<0) /* pullup select= 0      */
+              ;
+
+  chopstx_setpriority (prio_old);
+
+  chopstx_intr_wait (&tpm1_intr);
+  gpio_assert_low ();
+
+  v = TPM1->C1V;
+
+  /* Clear overflow and CH1 capture.  */
+  TPM1->STATUS = 0x102;
+  /* Stop the timer.  */
+  TPM1->SC = 0;
+  TPM1->CNT = 0xffff;	   /* Writing causes reset of the counter.  */
+
+  return v;
+}
+
+
+void
+touch_init (void)
+{
+  chopstx_claim_irq (&tpm1_intr, INTR_REQ_TPM1);
+
+  /* Input capture mode: MSB = 0, MSA = 0 */
+  /*   Rising edge: ELSB=0 ELSA=1 */
+  TPM1->C1SC = 0x84;
+  TPM1->POL=0;
+
+  /* No trigger.   */
+  /* Stop on overflow: CSOO=1 */ 
+  /* Run the timer in the debug mode */
+  TPM1->CONF = 0x000200c0;
+
+  TPM1->CNT = 0xffff;	   /* Writing causes reset of the counter.  */
+  gpio_assert_low ();
+}
--- a/example-fs-bb48/tty.h
+++ b/example-fs-bb48/tty.h
@@ -0,0 +1,9 @@
+#define LINEBUFSIZE 128
+
+struct tty;
+
+struct tty *tty_open (void);
+void tty_wait_configured (struct tty *tty);
+void tty_wait_connection (struct tty *tty);
+int tty_send (struct tty *tty, const char *buf, int count);
+int tty_recv (struct tty *tty, char *buf, uint32_t *timeout);
--- a/example-fs-bb48/usb-cdc.c
+++ b/example-fs-bb48/usb-cdc.c
@@ -0,0 +1,952 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <string.h>
+#include "board.h"
+#include "usb_lld.h"
+#include "tty.h"
+
+static chopstx_intr_t usb_intr;
+
+struct line_coding
+{
+  uint32_t bitrate;
+  uint8_t format;
+  uint8_t paritytype;
+  uint8_t datatype;
+}  __attribute__((packed));
+
+static const struct line_coding line_coding0 = {
+  115200, /* baud rate: 115200    */
+  0x00,   /* stop bits: 1         */
+  0x00,   /* parity:    none      */
+  0x08    /* bits:      8         */
+};
+
+/*
+ * Currently, we only support a single TTY.
+ *
+ * It is possible to extend to support multiple TTYs, for multiple
+ * interfaces.
+ *
+ * In that case, add argument to TTY_OPEN function and
+ * modify TTY_GET function to get the TTY structure.  Functions which
+ * directy accesses TTY0 (usb_device_reset and usb_set_configuration)
+ * should be modified, too.
+ *
+ * Modification of TTY_MAIN thread will be also needed to echo back
+ * input for each TTY, and the thread should run if one of TTY is
+ * opened.
+ */
+
+struct tty {
+  chopstx_mutex_t mtx;
+  chopstx_cond_t cnd;
+  uint8_t inputline[LINEBUFSIZE];   /* Line editing is supported */
+  uint8_t send_buf[LINEBUFSIZE];    /* Sending ring buffer for echo back */
+  uint8_t send_buf0[64];
+  uint8_t recv_buf0[64];
+  uint32_t inputline_len    : 8;
+  uint32_t send_head        : 8;
+  uint32_t send_tail        : 8;
+  uint32_t flag_connected   : 1;
+  uint32_t flag_send_ready  : 1;
+  uint32_t flag_input_avail : 1;
+  uint32_t                  : 2;
+  uint32_t device_state     : 3;     /* USB device status */
+  struct line_coding line_coding;
+};
+
+static struct tty tty0;
+
+/*
+ * Locate TTY structure from interface number or endpoint number.
+ * Currently, it always returns tty0, because we only have the one.
+ */
+static struct tty *
+tty_get (int interface, uint8_t ep_num)
+{
+  struct tty *t = &tty0;
+
+  if (interface >= 0)
+    {
+      if (interface == 0)
+	t = &tty0;
+    }
+  else
+    {
+      if (ep_num == ENDP1 || ep_num == ENDP2 || ep_num == ENDP3)
+	t = &tty0;
+    }
+
+  return t;
+}
+
+
+#define USB_CDC_REQ_SET_LINE_CODING             0x20
+#define USB_CDC_REQ_GET_LINE_CODING             0x21
+#define USB_CDC_REQ_SET_CONTROL_LINE_STATE      0x22
+#define USB_CDC_REQ_SEND_BREAK                  0x23
+
+/* USB Device Descriptor */
+static const uint8_t vcom_device_desc[18] = {
+  18,   /* bLength */
+  DEVICE_DESCRIPTOR,		/* bDescriptorType */
+  0x10, 0x01,			/* bcdUSB = 1.1 */
+  0x02,				/* bDeviceClass (CDC).              */
+  0x00,				/* bDeviceSubClass.                 */
+  0x00,				/* bDeviceProtocol.                 */
+  0x40,				/* bMaxPacketSize.                  */
+  0xFF, 0xFF, /* idVendor  */
+  0x01, 0x00, /* idProduct */
+  0x00, 0x01, /* bcdDevice  */
+  1,				/* iManufacturer.                   */
+  2,				/* iProduct.                        */
+  3,				/* iSerialNumber.                   */
+  1				/* bNumConfigurations.              */
+};
+
+#define VCOM_FEATURE_BUS_POWERED	0x80
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_config_desc[67] = {
+  9,
+  CONFIG_DESCRIPTOR,		/* bDescriptorType: Configuration */
+  /* Configuration Descriptor.*/
+  67, 0x00,			/* wTotalLength.                    */
+  0x02,				/* bNumInterfaces.                  */
+  0x01,				/* bConfigurationValue.             */
+  0,				/* iConfiguration.                  */
+  VCOM_FEATURE_BUS_POWERED,	/* bmAttributes.                    */
+  50,				/* bMaxPower (100mA).               */
+  /* Interface Descriptor.*/
+  9,
+  INTERFACE_DESCRIPTOR,
+  0x00,		   /* bInterfaceNumber.                */
+  0x00,		   /* bAlternateSetting.               */
+  0x01,		   /* bNumEndpoints.                   */
+  0x02,		   /* bInterfaceClass (Communications Interface Class,
+		      CDC section 4.2).  */
+  0x02,		   /* bInterfaceSubClass (Abstract Control Model, CDC
+		      section 4.3).  */
+  0x01,		   /* bInterfaceProtocol (AT commands, CDC section
+		      4.4).  */
+  0,	           /* iInterface.                      */
+  /* Header Functional Descriptor (CDC section 5.2.3).*/
+  5,	      /* bLength.                         */
+  0x24,	      /* bDescriptorType (CS_INTERFACE).  */
+  0x00,	      /* bDescriptorSubtype (Header Functional Descriptor). */
+  0x10, 0x01, /* bcdCDC.                          */
+  /* Call Management Functional Descriptor. */
+  5,            /* bFunctionLength.                 */
+  0x24,         /* bDescriptorType (CS_INTERFACE).  */
+  0x01,         /* bDescriptorSubtype (Call Management Functional
+		   Descriptor). */
+  0x03,         /* bmCapabilities (D0+D1).          */
+  0x01,         /* bDataInterface.                  */
+  /* ACM Functional Descriptor.*/
+  4,            /* bFunctionLength.                 */
+  0x24,         /* bDescriptorType (CS_INTERFACE).  */
+  0x02,         /* bDescriptorSubtype (Abstract Control Management
+		   Descriptor).  */
+  0x02,         /* bmCapabilities.                  */
+  /* Union Functional Descriptor.*/
+  5,            /* bFunctionLength.                 */
+  0x24,         /* bDescriptorType (CS_INTERFACE).  */
+  0x06,         /* bDescriptorSubtype (Union Functional
+		   Descriptor).  */
+  0x00,         /* bMasterInterface (Communication Class
+		   Interface).  */
+  0x01,         /* bSlaveInterface0 (Data Class Interface).  */
+  /* Endpoint 2 Descriptor.*/
+  7,
+  ENDPOINT_DESCRIPTOR,
+  ENDP2|0x80,    /* bEndpointAddress.    */
+  0x03,          /* bmAttributes (Interrupt).        */
+  0x08, 0x00,	 /* wMaxPacketSize.                  */
+  0xFF,		 /* bInterval.                       */
+  /* Interface Descriptor.*/
+  9,
+  INTERFACE_DESCRIPTOR, /* bDescriptorType: */
+  0x01,          /* bInterfaceNumber.                */
+  0x00,          /* bAlternateSetting.               */
+  0x02,          /* bNumEndpoints.                   */
+  0x0A,          /* bInterfaceClass (Data Class Interface, CDC section 4.5). */
+  0x00,          /* bInterfaceSubClass (CDC section 4.6). */
+  0x00,          /* bInterfaceProtocol (CDC section 4.7). */
+  0x00,		 /* iInterface.                      */
+  /* Endpoint 3 Descriptor.*/
+  7,
+  ENDPOINT_DESCRIPTOR,		/* bDescriptorType: Endpoint */
+  ENDP3,    /* bEndpointAddress. */
+  0x02,				/* bmAttributes (Bulk).             */
+  0x40, 0x00,			/* wMaxPacketSize.                  */
+  0x00,				/* bInterval.                       */
+  /* Endpoint 1 Descriptor.*/
+  7,
+  ENDPOINT_DESCRIPTOR,		/* bDescriptorType: Endpoint */
+  ENDP1|0x80,			/* bEndpointAddress. */
+  0x02,				/* bmAttributes (Bulk).             */
+  0x40, 0x00,			/* wMaxPacketSize.                  */
+  0x00				/* bInterval.                       */
+};
+
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[4] = {
+  4,				/* bLength */
+  STRING_DESCRIPTOR,
+  0x09, 0x04			/* LangID = 0x0409: US-English */
+};
+
+static const uint8_t vcom_string1[] = {
+  23*2+2,			/* bLength */
+  STRING_DESCRIPTOR,		/* bDescriptorType */
+  /* Manufacturer: "Flying Stone Technology" */
+  'F', 0, 'l', 0, 'y', 0, 'i', 0, 'n', 0, 'g', 0, ' ', 0, 'S', 0,
+  't', 0, 'o', 0, 'n', 0, 'e', 0, ' ', 0, 'T', 0, 'e', 0, 'c', 0,
+  'h', 0, 'n', 0, 'o', 0, 'l', 0, 'o', 0, 'g', 0, 'y', 0, 
+};
+
+static const uint8_t vcom_string2[] = {
+  14*2+2,			/* bLength */
+  STRING_DESCRIPTOR,		/* bDescriptorType */
+  /* Product name: "Chopstx Sample" */
+  'C', 0, 'h', 0, 'o', 0, 'p', 0, 's', 0, 't', 0, 'x', 0, ' ', 0,
+  'S', 0, 'a', 0, 'm', 0, 'p', 0, 'l', 0, 'e', 0,
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[28] = {
+  28,				    /* bLength */
+  STRING_DESCRIPTOR,		    /* bDescriptorType */
+  '0', 0,  '.', 0,  '0', 0, '0', 0, /* Version number */
+};
+
+
+#define NUM_INTERFACES 2
+
+
+static void
+usb_device_reset (struct usb_dev *dev)
+{
+  usb_lld_reset (dev, VCOM_FEATURE_BUS_POWERED);
+
+  /* Initialize Endpoint 0 */
+  usb_lld_setup_endp (dev, ENDP0, 1, 1);
+
+  chopstx_mutex_lock (&tty0.mtx);
+  tty0.inputline_len = 0;
+  tty0.send_head = tty0.send_tail = 0;
+  tty0.flag_connected = 0;
+  tty0.flag_send_ready = 1;
+  tty0.flag_input_avail = 0;
+  tty0.device_state = ATTACHED;
+  memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
+  chopstx_mutex_unlock (&tty0.mtx);
+}
+
+
+#define CDC_CTRL_DTR            0x0001
+
+static void
+usb_ctrl_write_finish (struct usb_dev *dev)
+{
+  struct device_req *arg = &dev->dev_req;
+  uint8_t type_rcp = arg->type & (REQUEST_TYPE|RECIPIENT);
+
+  if (type_rcp == (CLASS_REQUEST | INTERFACE_RECIPIENT) && arg->index == 0
+      && USB_SETUP_SET (arg->type)
+      && arg->request == USB_CDC_REQ_SET_CONTROL_LINE_STATE)
+    {
+      struct tty *t = tty_get (arg->index, 0);
+
+      /* Open/close the connection.  */
+      chopstx_mutex_lock (&t->mtx);
+      t->flag_connected = ((arg->value & CDC_CTRL_DTR) != 0);
+      chopstx_cond_signal (&t->cnd);
+      chopstx_mutex_unlock (&t->mtx);
+    }
+}
+
+
+static int
+vcom_port_data_setup (struct usb_dev *dev)
+{
+  struct device_req *arg = &dev->dev_req;
+
+  if (USB_SETUP_GET (arg->type))
+    {
+      struct tty *t = tty_get (arg->index, 0);
+
+      if (arg->request == USB_CDC_REQ_GET_LINE_CODING)
+	return usb_lld_ctrl_send (dev, &t->line_coding,
+				  sizeof (struct line_coding));
+    }
+  else  /* USB_SETUP_SET (req) */
+    {
+      if (arg->request == USB_CDC_REQ_SET_LINE_CODING
+	  && arg->len == sizeof (struct line_coding))
+	{
+	  struct tty *t = tty_get (arg->index, 0);
+
+	  return usb_lld_ctrl_recv (dev, &t->line_coding,
+				    sizeof (struct line_coding));
+	}
+      else if (arg->request == USB_CDC_REQ_SET_CONTROL_LINE_STATE)
+	return usb_lld_ctrl_ack (dev);
+    }
+
+  return -1;
+}
+
+static int
+usb_setup (struct usb_dev *dev)
+{
+  struct device_req *arg = &dev->dev_req;
+  uint8_t type_rcp = arg->type & (REQUEST_TYPE|RECIPIENT);
+
+  if (type_rcp == (CLASS_REQUEST | INTERFACE_RECIPIENT) && arg->index == 0)
+    return vcom_port_data_setup (dev);
+
+  return -1;
+}
+
+static int
+usb_get_descriptor (struct usb_dev *dev)
+{
+  struct device_req *arg = &dev->dev_req;
+  uint8_t rcp = arg->type & RECIPIENT;
+  uint8_t desc_type = (arg->value >> 8);
+  uint8_t desc_index = (arg->value & 0xff);
+
+  if (rcp != DEVICE_RECIPIENT)
+    return -1;
+
+  if (desc_type == DEVICE_DESCRIPTOR)
+    return usb_lld_ctrl_send (dev,
+			      vcom_device_desc, sizeof (vcom_device_desc));
+  else if (desc_type == CONFIG_DESCRIPTOR)
+    return usb_lld_ctrl_send (dev,
+			      vcom_config_desc, sizeof (vcom_config_desc));
+  else if (desc_type == STRING_DESCRIPTOR)
+    {
+      const uint8_t *str;
+      int size;
+
+      switch (desc_index)
+	{
+	case 0:
+	  str = vcom_string0;
+	  size = sizeof (vcom_string0);
+	  break;
+	case 1:
+	  str = vcom_string1;
+	  size = sizeof (vcom_string1);
+	  break;
+	case 2:
+	  str = vcom_string2;
+	  size = sizeof (vcom_string2);
+	  break;
+	case 3:
+	  str = vcom_string3;
+	  size = sizeof (vcom_string3);
+	  break;
+	default:
+	  return -1;
+	}
+
+      return usb_lld_ctrl_send (dev, str, size);
+    }
+
+  return -1;
+}
+
+static void
+vcom_setup_endpoints_for_interface (struct usb_dev *dev,
+				    uint16_t interface, int stop)
+{
+  if (interface == 0)
+    {
+      if (!stop)
+	usb_lld_setup_endp (dev, ENDP2, 0, 1);
+      else
+	usb_lld_stall (ENDP2);
+    }
+  else if (interface == 1)
+    {
+      if (!stop)
+	{
+	  usb_lld_setup_endp (dev, ENDP1, 0, 1);
+	  usb_lld_setup_endp (dev, ENDP3, 1, 0);
+	  /* Start with no data receiving (ENDP3 not enabled)*/
+	}
+      else
+	{
+	  usb_lld_stall (ENDP1);
+	  usb_lld_stall (ENDP3);
+	}
+    }
+}
+
+static int
+usb_set_configuration (struct usb_dev *dev)
+{
+  int i;
+  uint8_t current_conf;
+
+  current_conf = usb_lld_current_configuration (dev);
+  if (current_conf == 0)
+    {
+      if (dev->dev_req.value != 1)
+	return -1;
+
+      usb_lld_set_configuration (dev, 1);
+      for (i = 0; i < NUM_INTERFACES; i++)
+	vcom_setup_endpoints_for_interface (dev, i, 0);
+      chopstx_mutex_lock (&tty0.mtx);
+      tty0.device_state = CONFIGURED;
+      chopstx_cond_signal (&tty0.cnd);
+      chopstx_mutex_unlock (&tty0.mtx);
+    }
+  else if (current_conf != dev->dev_req.value)
+    {
+      if (dev->dev_req.value != 0)
+	return -1;
+
+      usb_lld_set_configuration (dev, 0);
+      for (i = 0; i < NUM_INTERFACES; i++)
+	vcom_setup_endpoints_for_interface (dev, i, 1);
+      chopstx_mutex_lock (&tty0.mtx);
+      tty0.device_state = ADDRESSED;
+      chopstx_cond_signal (&tty0.cnd);
+      chopstx_mutex_unlock (&tty0.mtx);
+    }
+
+  return usb_lld_ctrl_ack (dev);
+}
+
+
+static int
+usb_set_interface (struct usb_dev *dev)
+{
+  uint16_t interface = dev->dev_req.index;
+  uint16_t alt = dev->dev_req.value;
+
+  if (interface >= NUM_INTERFACES)
+    return -1;
+
+  if (alt != 0)
+    return -1;
+  else
+    {
+      vcom_setup_endpoints_for_interface (dev, interface, 0);
+      return usb_lld_ctrl_ack (dev);
+    }
+}
+
+static int
+usb_get_interface (struct usb_dev *dev)
+{
+  const uint8_t zero = 0;
+  uint16_t interface = dev->dev_req.index;
+
+  if (interface >= NUM_INTERFACES)
+    return -1;
+
+  /* We don't have alternate interface, so, always return 0.  */
+  return usb_lld_ctrl_send (dev, &zero, 1);
+}
+
+static int
+usb_get_status_interface (struct usb_dev *dev)
+{
+  const uint16_t status_info = 0;
+  uint16_t interface = dev->dev_req.index;
+
+  if (interface >= NUM_INTERFACES)
+    return -1;
+
+  return usb_lld_ctrl_send (dev, &status_info, 2);
+}
+
+
+/*
+ * Put a character into the ring buffer to be send back.
+ */
+static void
+put_char_to_ringbuffer (struct tty *t, int c)
+{
+  uint32_t next = (t->send_tail + 1) % LINEBUFSIZE;
+
+  if (t->send_head == next)
+    /* full */
+    /* All that we can do is ignore this char. */
+    return;
+  
+  t->send_buf[t->send_tail] = c;
+  t->send_tail = next;
+}
+
+/*
+ * Get characters from ring buffer into S.
+ */
+static int
+get_chars_from_ringbuffer (struct tty *t, uint8_t *s, int len)
+{
+  int i = 0;
+
+  if (t->send_head == t->send_tail)
+    /* Empty */
+    return i;
+
+  do
+    {
+      s[i++] = t->send_buf[t->send_head];
+      t->send_head = (t->send_head + 1) % LINEBUFSIZE;
+    }
+  while (t->send_head != t->send_tail && i < len);
+
+  return i;
+}
+
+
+static void
+tty_echo_char (struct tty *t, int c)
+{
+  put_char_to_ringbuffer (t, c);
+}
+
+static void
+usb_tx_done (uint8_t ep_num, uint16_t len)
+{
+  struct tty *t = tty_get (-1, ep_num);
+
+  (void)len;
+
+  if (ep_num == ENDP1)
+    {
+      chopstx_mutex_lock (&t->mtx);
+      if (t->flag_send_ready == 0)
+	{
+	  t->flag_send_ready = 1;
+	  chopstx_cond_signal (&t->cnd);
+	}
+      chopstx_mutex_unlock (&t->mtx);
+    }
+  else if (ep_num == ENDP2)
+    {
+      /* Nothing */
+    }
+}
+
+
+static int
+tty_input_char (struct tty *t, int c)
+{
+  unsigned int i;
+  int r = 0;
+
+  /* Process DEL, C-U, C-R, and RET as editing command. */
+  chopstx_mutex_lock (&t->mtx);
+  switch (c)
+    {
+    case 0x0d: /* Control-M */
+      t->inputline[t->inputline_len++] = '\n';
+      tty_echo_char (t, 0x0d);
+      tty_echo_char (t, 0x0a);
+      t->flag_input_avail = 1;
+      r = 1;
+      chopstx_cond_signal (&t->cnd);
+      break;
+    case 0x12: /* Control-R */
+      tty_echo_char (t, '^');
+      tty_echo_char (t, 'R');
+      tty_echo_char (t, 0x0d);
+      tty_echo_char (t, 0x0a);
+      for (i = 0; i < t->inputline_len; i++)
+	tty_echo_char (t, t->inputline[i]);
+      break;
+    case 0x15: /* Control-U */
+      for (i = 0; i < t->inputline_len; i++)
+	{
+	  tty_echo_char (t, 0x08);
+	  tty_echo_char (t, 0x20);
+	  tty_echo_char (t, 0x08);
+	}
+      t->inputline_len = 0;
+      break;
+    case 0x7f: /* DEL    */
+      if (t->inputline_len > 0)
+	{
+	  tty_echo_char (t, 0x08);
+	  tty_echo_char (t, 0x20);
+	  tty_echo_char (t, 0x08);
+	  t->inputline_len--;
+	}
+      break;
+    default:
+      if (t->inputline_len < sizeof (t->inputline) - 1)
+	{
+	  tty_echo_char (t, c);
+	  t->inputline[t->inputline_len++] = c;
+	}
+      else
+	/* Beep */
+	tty_echo_char (t, 0x0a);
+      break;
+    }
+  chopstx_mutex_unlock (&t->mtx);
+  return r;
+}
+
+static void
+usb_rx_ready (uint8_t ep_num, uint16_t len)
+{
+  struct tty *t = tty_get (-1, ep_num);
+
+  if (ep_num == ENDP3)
+    {
+      int i;
+
+      for (i = 0; i < len; i++)
+	if (tty_input_char (t, t->recv_buf0[i]))
+	  break;
+
+      chopstx_mutex_lock (&t->mtx);
+      if (t->flag_input_avail == 0)
+	usb_lld_rx_enable_buf (ENDP3, t->recv_buf0, 64);
+      chopstx_mutex_unlock (&t->mtx);
+    }
+}
+
+static void *tty_main (void *arg);
+
+#define INTR_REQ_USB 24
+#define PRIO_TTY      4
+
+extern uint8_t __process3_stack_base__[], __process3_stack_size__[];
+#define STACK_ADDR_TTY ((uint32_t)__process3_stack_base__)
+#define STACK_SIZE_TTY ((uint32_t)__process3_stack_size__)
+
+struct tty *
+tty_open (void)
+{
+  chopstx_mutex_init (&tty0.mtx);
+  chopstx_cond_init (&tty0.cnd);
+  tty0.inputline_len = 0;
+  tty0.send_head = tty0.send_tail = 0;
+  tty0.flag_connected = 0;
+  tty0.flag_send_ready = 1;
+  tty0.flag_input_avail = 0;
+  tty0.device_state = UNCONNECTED;
+  memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
+
+  chopstx_create (PRIO_TTY, STACK_ADDR_TTY, STACK_SIZE_TTY, tty_main, &tty0);
+  return &tty0;
+}
+
+
+static void *
+tty_main (void *arg)
+{
+  struct tty *t = arg;
+  struct usb_dev dev;
+  int e;
+
+#if defined(OLDER_SYS_H)
+  /*
+   * Historically (before sys < 3.0), NVIC priority setting for USB
+   * interrupt was done in usb_lld_sys_init.  Thus this code.
+   *
+   * When USB interrupt occurs between usb_lld_init (which assumes
+   * ISR) and chopstx_claim_irq (which clears pending interrupt),
+   * invocation of usb_lld_event_handler won't occur.
+   *
+   * Calling usb_lld_event_handler is no harm even if there were no
+   * interrupts, thus, we call it unconditionally here, just in case
+   * if there is a request.
+   *
+   * We can't call usb_lld_init after chopstx_claim_irq, as
+   * usb_lld_init does its own setting for NVIC.  Calling
+   * chopstx_claim_irq after usb_lld_init overrides that.
+   *
+   */
+  usb_lld_init (&dev, VCOM_FEATURE_BUS_POWERED);
+  chopstx_claim_irq (&usb_intr, INTR_REQ_USB);
+  goto event_handle;
+#else
+  chopstx_claim_irq (&usb_intr, INTR_REQ_USB);
+  usb_lld_init (&dev, VCOM_FEATURE_BUS_POWERED);
+#endif
+
+  while (1)
+    {
+      struct chx_poll_head *pd_array[1] = {
+	(struct chx_poll_head *)&usb_intr
+      };
+      chopstx_poll (NULL, 1, pd_array);
+      if (usb_intr.ready)
+	{
+	  uint8_t ep_num;
+#if defined(OLDER_SYS_H)
+	event_handle:
+#endif
+	  /*
+	   * When interrupt is detected, call usb_lld_event_handler.
+	   * The event may be one of following:
+	   *    (1) Transfer to endpoint (bulk or interrupt)
+	   *        In this case EP_NUM is encoded in the variable E.
+	   *    (2) "NONE" event: some trasfer was done, but all was
+	   *        done by lower layer, no other work is needed in
+	   *        upper layer.
+	   *    (3) Device events: Reset or Suspend
+	   *    (4) Device requests to the endpoint zero.
+	   *        
+	   */
+	  e = usb_lld_event_handler (&dev);
+	  ep_num = USB_EVENT_ENDP (e);
+
+	  if (ep_num != 0)
+	    {
+	      if (USB_EVENT_TXRX (e))
+		usb_tx_done (ep_num, USB_EVENT_LEN (e));
+	      else
+		usb_rx_ready (ep_num, USB_EVENT_LEN (e));
+	    }
+	  else
+	    switch (USB_EVENT_ID (e))
+	      {
+	      case USB_EVENT_DEVICE_RESET:
+		usb_device_reset (&dev);
+		continue;
+
+	      case USB_EVENT_DEVICE_ADDRESSED:
+		/* The addres is assigned to the device.  We don't
+		 * need to do anything for this actually, but in this
+		 * application, we maintain the USB status of the
+		 * device.  Usually, just "continue" as EVENT_OK is
+		 * OK.
+		 */
+		chopstx_mutex_lock (&tty0.mtx);
+		tty0.device_state = ADDRESSED;
+		chopstx_cond_signal (&tty0.cnd);
+		chopstx_mutex_unlock (&tty0.mtx);
+		continue;
+
+	      case USB_EVENT_GET_DESCRIPTOR:
+		if (usb_get_descriptor (&dev) < 0)
+		  usb_lld_ctrl_error (&dev);
+		continue;
+
+	      case USB_EVENT_SET_CONFIGURATION:
+		if (usb_set_configuration (&dev) < 0)
+		  usb_lld_ctrl_error (&dev);
+		continue;
+
+	      case USB_EVENT_SET_INTERFACE:
+		if (usb_set_interface (&dev) < 0)
+		  usb_lld_ctrl_error (&dev);
+		continue;
+
+	      case USB_EVENT_CTRL_REQUEST:
+		/* Device specific device request.  */
+		if (usb_setup (&dev) < 0)
+		  usb_lld_ctrl_error (&dev);
+		continue;
+
+	      case USB_EVENT_GET_STATUS_INTERFACE:
+		if (usb_get_status_interface (&dev) < 0)
+		  usb_lld_ctrl_error (&dev);
+		continue;
+
+	      case USB_EVENT_GET_INTERFACE:
+		if (usb_get_interface (&dev) < 0)
+		  usb_lld_ctrl_error (&dev);
+		continue;
+
+	      case USB_EVENT_SET_FEATURE_DEVICE:
+	      case USB_EVENT_SET_FEATURE_ENDPOINT:
+	      case USB_EVENT_CLEAR_FEATURE_DEVICE:
+	      case USB_EVENT_CLEAR_FEATURE_ENDPOINT:
+		usb_lld_ctrl_ack (&dev);
+		continue;
+
+	      case USB_EVENT_CTRL_WRITE_FINISH:
+		/* Control WRITE transfer finished.  */
+		usb_ctrl_write_finish (&dev);
+		continue;
+
+	      case USB_EVENT_OK:
+	      case USB_EVENT_DEVICE_SUSPEND:
+	      default:
+		continue;
+	      }
+	}
+
+      chopstx_mutex_lock (&t->mtx);
+      if (t->device_state == CONFIGURED && t->flag_connected
+	  && t->flag_send_ready)
+	{
+	  uint8_t line[32];
+	  int len = get_chars_from_ringbuffer (t, line, sizeof (len));
+
+	  if (len)
+	    {
+	      memcpy (t->send_buf0, line, len);
+	      usb_lld_tx_enable_buf (ENDP1, t->send_buf0, len);
+	      t->flag_send_ready = 0;
+	    }
+	}
+      chopstx_mutex_unlock (&t->mtx);
+    }
+
+  return NULL;
+}
+
+
+void
+tty_wait_configured (struct tty *t)
+{
+  chopstx_mutex_lock (&t->mtx);
+  while (t->device_state != CONFIGURED)
+    chopstx_cond_wait (&t->cnd, &t->mtx);
+  chopstx_mutex_unlock (&t->mtx);
+}
+
+
+void
+tty_wait_connection (struct tty *t)
+{
+  chopstx_mutex_lock (&t->mtx);
+  while (t->flag_connected == 0)
+    chopstx_cond_wait (&t->cnd, &t->mtx);
+  t->flag_send_ready = 1;
+  t->flag_input_avail = 0;
+  t->send_head = t->send_tail = 0;
+  t->inputline_len = 0;
+  usb_lld_rx_enable_buf (ENDP3, t->recv_buf0, 64); /* Accept input for line */
+  chopstx_mutex_unlock (&t->mtx);
+}
+
+static int
+check_tx (struct tty *t)
+{
+  if (t->flag_send_ready)
+    /* TX done */
+    return 1;
+  if (t->flag_connected == 0)
+    /* Disconnected */
+    return -1;
+  return 0;
+}
+
+int
+tty_send (struct tty *t, const char *buf, int len)
+{
+  int r;
+  const char *p;
+  int count;
+
+  p = buf;
+  count = len >= 64 ? 64 : len;
+
+  while (1)
+    {
+      chopstx_mutex_lock (&t->mtx);
+      while ((r = check_tx (t)) == 0)
+	chopstx_cond_wait (&t->cnd, &t->mtx);
+      if (r > 0)
+	{
+	  usb_lld_tx_enable_buf (ENDP1, p, count);
+	  t->flag_send_ready = 0;
+	}
+      chopstx_mutex_unlock (&t->mtx);
+
+      len -= count;
+      p += count;
+      if (len == 0 && count != 64)
+	/*
+	 * The size of the last packet should be != 0
+	 * If 64, send ZLP (zelo length packet)
+	 */
+	break;
+      count = len >= 64 ? 64 : len;
+    }
+
+  /* Wait until all sent. */
+  chopstx_mutex_lock (&t->mtx);
+  while ((r = check_tx (t)) == 0)
+    chopstx_cond_wait (&t->cnd, &t->mtx);
+  chopstx_mutex_unlock (&t->mtx);
+  return r;
+}
+
+
+static int
+check_rx (void *arg)
+{
+  struct tty *t = arg;
+
+  if (t->flag_input_avail)
+    /* RX */
+    return 1;
+  if (t->flag_connected == 0)
+    /* Disconnected */
+    return 1;
+  return 0;
+}
+
+/*
+ * Returns -1 on connection close
+ *          0 on timeout.
+ *          >0 length of the inputline (including final \n) 
+ *
+ */
+int
+tty_recv (struct tty *t, char *buf, uint32_t *timeout)
+{
+  int r;
+  chopstx_poll_cond_t poll_desc;
+
+  poll_desc.type = CHOPSTX_POLL_COND;
+  poll_desc.ready = 0;
+  poll_desc.cond = &t->cnd;
+  poll_desc.mutex = &t->mtx;
+  poll_desc.check = check_rx;
+  poll_desc.arg = t;
+
+  while (1)
+    {
+      struct chx_poll_head *pd_array[1] = {
+	(struct chx_poll_head *)&poll_desc
+      };
+      chopstx_poll (timeout, 1, pd_array);
+      chopstx_mutex_lock (&t->mtx);
+      r = check_rx (t);
+      chopstx_mutex_unlock (&t->mtx);
+      if (r || (timeout != NULL && *timeout == 0))
+	break;
+    }
+
+  chopstx_mutex_lock (&t->mtx);
+  if (t->flag_connected == 0)
+    r = -1;
+  else if (t->flag_input_avail)
+    {
+      r = t->inputline_len;
+      memcpy (buf, t->inputline, r);
+      t->flag_input_avail = 0;
+      usb_lld_rx_enable_buf (ENDP3, t->recv_buf0, 64);
+      t->inputline_len = 0;
+    }
+  else
+    r = 0;
+  chopstx_mutex_unlock (&t->mtx);
+
+  return r;
+}
--- a/example-fsm-55/Makefile
+++ b/example-fsm-55/Makefile
@@ -0,0 +1,42 @@
+# Makefile for Hacker Emblem application of Chopstx
+
+PROJECT = hacker-emblem
+
+CHOPSTX = ..
+LDSCRIPT= hacker-emblem.ld
+
+CSRC = reset.c hh.c
+
+# Hacker Emblem and "Happy Hacking!" demonstration
+# CSRC = reset.c hh.c
+
+# Debian logo demonstration
+# CSRC = reset.c debian-logo.c
+
+# "Hiroshi & Ayumi with Tulip" demonstration
+# CSRC = reset.c hiroshi-ayumi.c
+
+###################################
+CROSS = arm-none-eabi-
+CC   = $(CROSS)gcc
+LD   = $(CROSS)gcc
+OBJCOPY   = $(CROSS)objcopy
+
+MCU   = cortex-m0 # -save-temps
+CWARN = -Wall -Wextra -Wstrict-prototypes
+DEFS  = -DMAKE_ENTRY_PUBLIC \
+        -DFREE_STANDING -DMHZ=48 -DUSE_WFI_FOR_IDLE
+OPT   = -O3 -Os -g
+LIBS  =
+
+####################
+include ../rules.mk
+
+board.h:
+	@echo Please make a symbolic link \'board.h\' to a file in ../board;
+	@exit 1
+
+reset.c: board.h
+
+distclean: clean
+	rm -f board.h
--- a/example-fsm-55/README
+++ b/example-fsm-55/README
@@ -0,0 +1,17 @@
+FSM-55 LED Matrix Display Board is a simple board to play 5x5 LED
+Display.  Please see the product page:
+
+    http://www.seeedstudio.com/depot/FSM55-LED-Matrix-Display-p-2121.html
+
+There are three demonstrations and default is Hacker Emblem and "Happy
+Hacking!".  Please edit CSRC variable in the Makefile to select other
+applications.
+
+
+The file stlink-v2.cfg can be used for ST-Link/V2 with OpenOCD.  You
+can flash by typing:
+
+    $ openocd -f ./stlink-v2.cfg -c "program build/hacker-emblem.elf; reset run; shutdown"
+
+Thanks to Kiwamu Okabe who kindly tested OpenOCD and wrote the
+configuration.
--- a/example-fsm-55/board.h
+++ b/example-fsm-55/board.h
@@ -0,0 +1 @@
+../board/board-fsm-55.h
--- a/example-fsm-55/debian-logo.c
+++ b/example-fsm-55/debian-logo.c
@@ -0,0 +1,473 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+
+#include "board.h"
+
+static uint8_t main_finished;
+
+#define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
+
+struct GPIO {
+  volatile uint32_t MODER;
+  volatile uint16_t OTYPER;
+  uint16_t dummy0;
+  volatile uint32_t OSPEEDR;
+  volatile uint32_t PUPDR;
+  volatile uint16_t IDR;
+  uint16_t dummy1;
+  volatile uint16_t ODR;
+  uint16_t dummy2;
+  volatile uint16_t BSRR;
+  uint16_t dummy3;
+  volatile uint32_t LCKR;
+  volatile uint32_t AFR[2];
+  volatile uint16_t BRR;
+  uint16_t dummy4;
+};
+#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
+#define GPIOF		((struct GPIO *) GPIOF_BASE)
+
+static struct GPIO *const GPIO_LED = ((struct GPIO *)GPIO_LED_BASE);
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *)GPIO_OTHER_BASE);
+
+static chopstx_mutex_t mtx;
+static chopstx_cond_t cnd0, cnd1;
+
+#define BUTTON_PUSHED 1
+static uint8_t button_state;
+
+static uint8_t
+user_button (void)
+{
+  return button_state;
+}
+
+
+static uint8_t l_data[5];
+#define LED_FULL ((0x1f << 20)|(0x1f << 15)|(0x1f << 10)|(0x1f << 5)|0x1f)
+
+static void
+set_led_display (uint32_t data)
+{
+  l_data[0] = (data >>  0) & 0x1f;
+  l_data[1] = (data >>  5) & 0x1f;
+  l_data[2] = (data >> 10) & 0x1f;
+  l_data[3] = (data >> 15) & 0x1f;
+  l_data[4] = (data >> 20) & 0x1f;
+}
+
+static void
+scroll_led_display (uint8_t row)
+{
+  l_data[0] = (l_data[0] << 1) | ((row >> 0) & 1);
+  l_data[1] = (l_data[1] << 1) | ((row >> 1) & 1);
+  l_data[2] = (l_data[2] << 1) | ((row >> 2) & 1);
+  l_data[3] = (l_data[3] << 1) | ((row >> 3) & 1);
+  l_data[4] = (l_data[4] << 1) | ((row >> 4) & 1);
+}
+
+
+static void
+wait_for (uint32_t usec)
+{
+  chopstx_usec_wait (usec);
+}
+
+static void
+led_prepare_row (uint8_t col)
+{
+  uint16_t data = 0x1f;
+
+  data |= ((l_data[0] & (1 << col)) ? 1 : 0) << 5;
+  data |= ((l_data[1] & (1 << col)) ? 1 : 0) << 6;
+  data |= ((l_data[2] & (1 << col)) ? 1 : 0) << 7;
+  data |= ((l_data[3] & (1 << col)) ? 1 : 0) << 9;
+  data |= ((l_data[4] & (1 << col)) ? 1 : 0) << 10;
+  GPIO_LED->ODR = data;
+}
+
+
+static void
+led_enable_column (uint8_t col)
+{
+  GPIO_LED->BRR = (1 << col);
+}
+
+static void *
+led (void *arg)
+{
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd0, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (!main_finished)
+    {
+      int i;
+
+      for (i = 0; i < 5; i++)
+	{
+	  led_prepare_row (i);
+	  led_enable_column (i);
+	  wait_for (1000);
+	}
+    }
+
+  GPIO_LED->ODR = 0x0000;	/* Off all LEDs.  */
+  GPIO_LED->OSPEEDR = 0;
+  GPIO_LED->OTYPER = 0;
+  GPIO_LED->MODER = 0;		/* Input mode.  */
+  GPIO_OTHER->PUPDR = 0x0000;	/* No pull-up.  */
+
+  return NULL;
+}
+
+
+static uint8_t get_button_sw (void) { return (GPIO_OTHER->IDR & 1) == 0; }
+
+static void *
+button (void *arg)
+{
+  uint8_t last_button = 0;
+
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd1, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (!main_finished)
+    {
+      uint8_t button = get_button_sw ();
+
+      if (last_button == button && button != button_state)
+	{
+	  wait_for (1000);
+	  button = get_button_sw ();
+	  if (last_button == button)
+	    button_state = button;
+	}
+
+      wait_for (2000);
+      last_button = button;
+    }
+
+  return NULL;
+}
+
+#define PRIO_LED 3
+#define PRIO_BUTTON 2
+
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
+
+#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
+
+#define STACK_ADDR_BUTTON ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BUTTON ((uint32_t)__process2_stack_size__)
+
+#define DATA55(x0,x1,x2,x3,x4) (x0<<20)|(x1<<15)|(x2<<10)|(x3<< 5)|(x4<< 0)
+#define SIZE55(img) (sizeof (img) / sizeof (uint32_t))
+
+static uint32_t logo55[] = {
+  DATA55 (0x00, 0x00, 0x00, 0x00, 0x00),
+  DATA55 (0x00, 0x00, 0x04, 0x00, 0x00),
+  DATA55 (0x00, 0x00, 0x04, 0x02, 0x00),
+  DATA55 (0x00, 0x00, 0x05, 0x02, 0x00),
+  DATA55 (0x00, 0x01, 0x05, 0x02, 0x00),
+  DATA55 (0x02, 0x01, 0x05, 0x02, 0x00),
+  DATA55 (0x06, 0x01, 0x05, 0x02, 0x00),
+  DATA55 (0x0e, 0x01, 0x05, 0x02, 0x00),
+  DATA55 (0x0e, 0x11, 0x05, 0x02, 0x00),
+  DATA55 (0x0e, 0x11, 0x15, 0x02, 0x00),
+  DATA55 (0x0e, 0x11, 0x15, 0x12, 0x00),
+  DATA55 (0x0e, 0x11, 0x15, 0x12, 0x08),
+  DATA55 (0x0e, 0x11, 0x15, 0x12, 0x08),
+  DATA55 (0x0e, 0x11, 0x16, 0x10, 0x0c),
+  DATA55 (0x0e, 0x11, 0x16, 0x10, 0x0c),
+  DATA55 (0x0e, 0x11, 0x16, 0x10, 0x0e),
+  DATA55 (0x0c, 0x12, 0x14, 0x10, 0x0f),
+  DATA55 (0x0c, 0x12, 0x14, 0x11, 0x0e),
+  DATA55 (0x08, 0x14, 0x15, 0x11, 0x0e),
+  DATA55 (0x08, 0x15, 0x15, 0x11, 0x0e),
+  DATA55 (0x01, 0x09, 0x15, 0x11, 0x0e),
+  DATA55 (0x02, 0x09, 0x15, 0x11, 0x0e),
+  DATA55 (0x06, 0x01, 0x0d, 0x11, 0x0e),
+  DATA55 (0x0e, 0x01, 0x0d, 0x11, 0x0e),
+  DATA55 (0x1e, 0x01, 0x0d, 0x11, 0x0e),
+  DATA55 (0x0e, 0x11, 0x05, 0x09, 0x06),
+  DATA55 (0x0e, 0x11, 0x15, 0x05, 0x02),
+  DATA55 (0x0e, 0x11, 0x15, 0x15, 0x02),
+  DATA55 (0x0e, 0x11, 0x15, 0x12, 0x10),
+  DATA55 (0x0e, 0x11, 0x15, 0x12, 0x08),
+  DATA55 (0x0e, 0x11, 0x15, 0x12, 0x08),
+};
+
+#define DATA55V(x0,x1,x2,x3,x4) (x0<<0)|(x1<<5)|(x2<<10)|(x3<< 15)|(x4<< 20)
+
+#define CHAR_SPC 0
+#define CHAR_H   1
+#define CHAR_A   2
+#define CHAR_P   3
+#define CHAR_Y   4
+#define CHAR_C   5
+#define CHAR_K   6
+#define CHAR_I   7
+#define CHAR_N   8
+#define CHAR_G   9
+#define CHAR_EXC 10
+#define CHAR_W   11
+#define CHAR_h   12
+#define CHAR_t   13
+#define CHAR_AP  14
+#define CHAR_s   15
+#define CHAR_U   16
+#define CHAR_QT  17
+#define CHAR_o   18
+#define CHAR_X   19
+#define CHAR_D   20
+#define CHAR_e   21
+#define CHAR_b   22
+#define CHAR_i   23
+#define CHAR_a   24
+#define CHAR_n   25
+
+static uint8_t hh[] = {
+  CHAR_H, CHAR_A, CHAR_P, CHAR_P, CHAR_Y,
+  CHAR_SPC,
+  CHAR_H, CHAR_A, CHAR_C, CHAR_K, CHAR_I, CHAR_N, CHAR_G,
+  CHAR_EXC,
+  CHAR_SPC, CHAR_SPC, CHAR_SPC,
+};
+
+static uint8_t debian[] = {
+  CHAR_SPC,
+  CHAR_D, CHAR_e, CHAR_b, CHAR_i, CHAR_a, CHAR_n,
+  CHAR_SPC, CHAR_SPC,
+};
+
+struct { uint8_t width; uint32_t data; } chargen[] = {
+  { 3, 0 },						/* SPACE */
+  { 4, DATA55V (0x1f, 0x04, 0x04, 0x1f, 0x00) },	/* H */
+  { 3, DATA55V (0x17, 0x15, 0x0f, 0x00, 0x00) },	/* A */
+  { 4, DATA55V (0x1f, 0x14, 0x14, 0x08, 0x00) },	/* P */
+  { 4, DATA55V (0x19, 0x05, 0x05, 0x1e, 0x00) },	/* Y */
+  { 4, DATA55V (0x0e, 0x11, 0x11, 0x0a, 0x00) },	/* C */
+  { 4, DATA55V (0x1f, 0x04, 0x0c, 0x13, 0x00) },	/* K */
+  { 3, DATA55V (0x11, 0x1f, 0x11, 0x00, 0x00) },	/* I */
+  { 4, DATA55V (0x1f, 0x08, 0x06, 0x1f, 0x00) },	/* N */
+  { 4, DATA55V (0x0e, 0x11, 0x15, 0x07, 0x00) },	/* G */
+  { 2, DATA55V (0x1d, 0x1c, 0x00, 0x00, 0x00) },	/* ! */
+  { 5, DATA55V (0x1e, 0x01, 0x0e, 0x01, 0x1e) },	/* W */
+  { 3, DATA55V (0x1f, 0x04, 0x07, 0x00, 0x00) },	/* h */
+  { 4, DATA55V (0x08, 0x1e, 0x09, 0x09, 0x00) },	/* t */
+  { 3, DATA55V (0x04, 0x18, 0x18, 0x00, 0x00) },	/* ' */
+  { 4, DATA55V (0x09, 0x15, 0x15, 0x12, 0x00) },	/* s */
+  { 4, DATA55V (0x1e, 0x01, 0x01, 0x1e, 0x00) },	/* U */
+  { 4, DATA55V (0x08, 0x10, 0x15, 0x08, 0x00) },	/* ? */
+  { 4, DATA55V (0x06, 0x09, 0x09, 0x06, 0x00) },	/* o */
+  { 5, DATA55V (0x11, 0x0a, 0x04, 0x0a, 0x11) },	/* X */
+  { 4, DATA55V (0x1f, 0x11, 0x11, 0x0e, 0x00) },	/* D */
+  { 4, DATA55V (0x0e, 0x15, 0x15, 0x0d, 0x00) },	/* e */
+  { 4, DATA55V (0x1f, 0x05, 0x05, 0x06, 0x00) },	/* b */
+  { 1, DATA55V (0x17, 0x00, 0x00, 0x00, 0x00) },	/* i */
+  { 4, DATA55V (0x02, 0x15, 0x15, 0x0f, 0x00) },	/* a */
+  { 4, DATA55V (0x1f, 0x08, 0x10, 0x1f, 0x00) },	/* n */
+};
+
+
+#define REPEAT_COUNT 10
+
+static int
+logo_display (void)
+{
+  unsigned int i;
+  uint8_t state = 0;
+
+  for (i = 0; i < SIZE55 (logo55); i++)
+    {
+      if (user_button ())
+	{
+	  set_led_display (LED_FULL);
+	  state = 1;
+	}
+      else if (state == 1)
+	return 0;
+      else
+	set_led_display (logo55[i]);
+      wait_for (350*1000);
+    }
+
+  return 1;
+}
+
+
+static int
+text_display (uint8_t kind)
+{
+  unsigned int i, j;
+  uint8_t *text;
+  uint8_t len;
+  uint8_t state = 0;
+
+  if (kind)
+    {
+      text = debian;
+      len = sizeof (debian);
+    }
+  else
+    {
+      text = hh;
+      len = sizeof (hh);
+    }
+
+#if 0
+  set_led_display (0);
+#endif
+  for (i = 0; i < len; i++)
+    {
+      for (j = 0; j < chargen[text[i]].width; j++)
+	{
+	  if (user_button ())
+	    {
+	      set_led_display (LED_FULL);
+	      state = 1;
+	    }
+	  else if (state == 1)
+	    return 0;
+	  else
+	    scroll_led_display ((chargen[text[i]].data >> j * 5) & 0x1f);
+	  wait_for (120*1000);
+	}
+
+      if (user_button ())
+	{
+	  set_led_display (LED_FULL);
+	  state = 1;
+	}
+      else if (state == 1)
+	return 0;
+      else
+	scroll_led_display (0);
+      wait_for (120*1000);
+    }
+
+  return 1;
+}
+
+
+static void setup_scr_sleepdeep (void);
+
+int
+main (int argc, const char *argv[])
+{
+  chopstx_t led_thd;
+  chopstx_t button_thd;
+  uint8_t happy = 1;
+  uint8_t count = 0;
+
+  (void)argc;
+  (void)argv;
+
+  chopstx_mutex_init (&mtx);
+  chopstx_cond_init (&cnd0);
+  chopstx_cond_init (&cnd1);
+
+  led_thd = chopstx_create (PRIO_LED, STACK_ADDR_LED,
+			    STACK_SIZE_LED, led, NULL);
+  button_thd = chopstx_create (PRIO_BUTTON, STACK_ADDR_BUTTON,
+			       STACK_SIZE_BUTTON, button, NULL);
+
+  chopstx_usec_wait (200*1000);
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_signal (&cnd0);
+  chopstx_cond_signal (&cnd1);
+  chopstx_mutex_unlock (&mtx);
+
+  wait_for (100*1000);
+  if (user_button ())
+    {
+      /* Wait button release.  */
+      while (user_button ())
+	wait_for (100*1000);
+
+      happy = 0;
+      goto do_text;
+    }
+
+  while (count++ < REPEAT_COUNT)
+    {
+      if (!logo_display ())
+	break;
+    do_text:
+      if (!text_display (happy))
+	break;
+    }
+
+  main_finished = 1;
+  chopstx_join (button_thd, NULL);
+  chopstx_join (led_thd, NULL);
+
+  setup_scr_sleepdeep ();
+  for (;;)
+    asm volatile ("wfi" : : : "memory");
+
+  return 0;
+}
+
+struct SCB
+{
+  volatile uint32_t CPUID;
+  volatile uint32_t ICSR;
+  volatile uint32_t VTOR;
+  volatile uint32_t AIRCR;
+  volatile uint32_t SCR;
+  volatile uint32_t CCR;
+  volatile uint8_t  SHP[12];
+  volatile uint32_t SHCSR;
+  volatile uint32_t CFSR;
+  volatile uint32_t HFSR;
+  volatile uint32_t DFSR;
+  volatile uint32_t MMFAR;
+  volatile uint32_t BFAR;
+  volatile uint32_t AFSR;
+  volatile uint32_t PFR[2];
+  volatile uint32_t DFR;
+  volatile uint32_t ADR;
+  volatile uint32_t MMFR[4];
+  volatile uint32_t ISAR[5];
+};
+
+#define SCS_BASE	(0xE000E000)
+#define SCB_BASE	(SCS_BASE +  0x0D00)
+static struct SCB *const SCB = ((struct SCB *)SCB_BASE);
+
+#define SCB_SCR_SLEEPDEEP (1 << 2)
+
+struct PWR
+{
+  volatile uint32_t CR;
+  volatile uint32_t CSR;
+};
+#define PWR_CR_PDDS 0x0002
+#define PWR_CR_CWUF 0x0004
+
+#define PWR_BASE	(APBPERIPH_BASE + 0x00007000)
+#define PWR		((struct PWR *) PWR_BASE)
+
+static void setup_scr_sleepdeep (void)
+{
+  PWR->CR |= PWR_CR_CWUF;
+  PWR->CR |= PWR_CR_PDDS;
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+}
--- a/example-fsm-55/debian-logo.txt
+++ b/example-fsm-55/debian-logo.txt
@@ -0,0 +1,594 @@
+.....
+.....
+.....
+.....
+.....
+
+.....
+.....
+..o..
+.....
+.....
+
+.....
+.....
+..o..
+...o.
+.....
+
+.....
+.....
+..o.o
+...o.
+.....
+
+.....
+....o
+..o.o
+...o.
+.....
+
+...o.
+....o
+..o.o
+...o.
+.....
+
+..oo.
+....o
+..o.o
+...o.
+.....
+
+.ooo.
+....o
+..o.o
+...o.
+.....
+
+.ooo.
+o...o
+..o.o
+...o.
+.....
+
+.ooo.
+o...o
+o.o.o
+...o.
+.....
+
+.ooo.
+o...o
+o.o.o
+o..o.
+.....
+
+.ooo.
+o...o
+o.o.o
+o..o.
+.o...
+
+.ooo.
+o...o
+o.o.o
+o..o.
+.o...
+
+.ooo.
+o...o
+o.oo.
+o....
+.oo..
+
+.ooo.
+o...o
+o.oo.
+o....
+.ooo.
+
+.oo..
+o..o.
+o.o..
+o....
+.oooo
+
+.oo..
+o..o.
+o.o..
+o...o
+.ooo.
+
+.oo..
+o.o..
+o.o.o
+o...o
+.ooo.
+
+.o...
+o.o.o
+o.o.o
+o...o
+.ooo.
+
+....o
+.o..o
+o.o.o
+o...o
+.ooo.
+
+...o.
+....o
+.oo.o
+o...o
+.ooo.
+
+.ooo.
+....o
+.oo.o
+o...o
+.ooo.
+
+oooo.
+....o
+.oo.o
+o...o
+.ooo.
+
+.ooo.
+o...o
+..o.o
+.o..o
+..oo.
+
+.ooo.
+o...o
+o.o.o
+..o.o
+...o.
+
+.ooo.
+o...o
+o.o.o
+o.o.o
+...o.
+
+.ooo.
+o...o
+o.o.o
+o..o.
+o....
+
+.ooo.
+o...o
+o.o.o
+o..o.
+.o...
+
+.ooo.
+o...o
+o.o.o
+o..o.
+.o...
+
+ooo.
+o..o
+o..o
+o..o
+ooo.
+
+.oo.
+o..o
+oooo
+o...
+.ooo
+
+o...
+o...
+oooo
+o..o
+ooo.
+
+o
+.
+o
+o
+o
+
+.oo.
+...o
+.ooo
+o..o
+oooo
+
+....
+oooo
+o..o
+o..o
+o..o
+
+..... 00
+..... 00
+..... 00
+..... 00
+..... 00
+
+..... 00
+..... 00
+..o.. 04
+..... 00
+..... 00
+
+..... 00
+..... 00
+..o.. 04
+...o. 02
+..... 00
+
+..... 00
+..... 00
+..o.o 05
+...o. 02
+..... 00
+
+..... 00
+....o 01
+..o.o 05
+...o. 02
+..... 00
+
+...o. 02
+....o 01
+..o.o 05
+...o. 02
+..... 00
+
+..oo. 06
+....o 01
+..o.o 05
+...o. 02
+..... 00
+
+.ooo. 0e
+....o 01
+..o.o 05
+...o. 02
+..... 00
+
+.ooo. 0e
+o...o 11
+..o.o 05
+...o. 02
+..... 00
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+...o. 02
+..... 00
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+o..o. 12
+..... 00
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+o..o. 12
+.o... 08
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+o..o. 12
+.o... 08
+
+.ooo. 0e
+o...o 11
+o.oo. 16
+o.... 10
+.oo.. 0c
+
+.ooo. 0e
+o...o 11
+o.oo. 16
+o.... 10
+.ooo. 0e
+
+.oo.. 0c
+o..o. 12
+o.o.. 14
+o.... 10
+.oooo 0f
+
+.oo.. 0c
+o..o. 12
+o.o.. 14
+o...o 11
+.ooo. 0e
+
+.o... 08
+o.o.. 14
+o.o.o 15
+o...o 11
+.ooo. 0e
+
+.o... 08
+o.o.o 15
+o.o.o 15
+o...o 11
+.ooo. 0e
+
+...o. 02
+.o..o 09
+o.o.o 15
+o...o 11
+.ooo. 0e
+
+....o 01
+.o..o 09
+o.o.o 15
+o...o 11
+.ooo. 0e
+
+...o. 02
+.o..o 09
+o.o.o 15
+o...o 11
+.ooo. 0e
+
+..oo. 06
+....o 01
+.oo.o 0d
+o...o 11
+.ooo. 0e
+
+.ooo. 0e
+....o 01
+.oo.o 0d
+o...o 11
+.ooo. 0e
+
+oooo. 1e
+....o 01
+.oo.o 0d
+o...o 11
+.ooo. 0e
+
+.ooo. 0e
+o...o 11
+..o.o 05
+.o..o 09
+..oo. 06
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+..o.o 05
+...o. 02
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+o.o.o 15
+...o. 02
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+o..o. 12
+o.... 10
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+o..o. 12
+.o... 08
+
+.ooo. 0e
+o...o 11
+o.o.o 15
+o..o. 12
+.o... 08
+
+ooo.
+o..o
+o..o
+o..o
+ooo.
+
+.oo.
+o..o
+oooo
+o...
+.ooo
+
+o...
+o...
+oooo
+o..o
+ooo.
+
+o
+.
+o
+o
+o
+
+.oo.
+...o
+.ooo
+o..o
+.ooo
+
+o.oo
+oo.o
+o..o
+o..o
+o..o
+
+
+00
+00
+00
+00
+00
+  
+00
+00
+04
+00
+00
+  
+00
+00
+04
+02
+00
+  
+00
+00
+05
+02
+00
+  
+00
+01
+05
+02
+00
+  
+02
+01
+05
+02
+00
+  
+06
+01
+05
+02
+00
+  
+0e
+01
+05
+02
+00
+  
+0e
+11
+05
+02
+00
+  
+0e
+11
+15
+02
+00
+  
+0e
+11
+15
+12
+00
+  
+0e
+11
+15
+12
+08
+  
+0e
+11
+15
+12
+08
+  
+0e
+11
+16
+10
+0e
+  
+0c
+12
+14
+11
+0e
+  
+0c
+14
+15
+11
+0e
+  
+08
+15
+15
+11
+0e
+  
+02
+09
+15
+11
+0e
+  
+06
+01
+0d
+11
+0e
+  
+0e
+01
+1d
+11
+0e
+  
+1e
+01
+0d
+11
+0e
+  
+0e
+11
+05
+09
+0e
+  
+0e
+11
+15
+05
+06
+  
+0e
+11
+15
+15
+02
+  
+0e
+11
+15
+13
+08
+  
+0e
+11
+15
+12
+08
+  
+0e
+11
+15
+12
+08
--- a/example-fsm-55/gnu.txt
+++ b/example-fsm-55/gnu.txt
@@ -0,0 +1,54 @@
+o...o
+o.o.o
+o.o.o
+o.o.o
+.o.o.
+
+o..
+o..
+ooo
+o.o
+o.o
+
+.o..
+oooo
+.o..
+.o..
+..oo
+
+.oo
+.oo
+o..
+...
+...
+
+....
+.ooo
+o...
+.oo.
+...o
+ooo.
+
+o..o
+o..o
+o..o
+o..o
+.oo.
+
+.oo.
+o..o
+..o.
+....
+..o.
+
+....
+.oo.
+o..o
+o..o
+.oo.
+
+o...o
+.o.o.
+..o..
+.o.o.
+o...o
--- a/example-fsm-55/hacker-emblem.ld
+++ b/example-fsm-55/hacker-emblem.ld
@@ -0,0 +1,125 @@
+/*
+ * ST32F0 memory setup.
+ */
+__main_stack_size__     = 0x0100;  /* Idle+Exception handlers */
+__process0_stack_size__  = 0x0100; /* Main program            */
+__process1_stack_size__  = 0x0100; /* first thread program    */
+__process2_stack_size__  = 0x0100; /* second thread program   */
+__process3_stack_size__  = 0x0100; /* third thread program    */
+
+MEMORY
+{
+    flash  : org = 0x08000000, len = 16k
+    ram : org = 0x20000000, len = 4k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 4k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    _text = .;
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+	KEEP(*(.vectors))
+	. = ALIGN(16);
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    /DISCARD/ :
+    {
+        *(.startup.vectors)
+        *(.bss.startup.0)
+    }
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .process_stack :
+    {
+        . = ALIGN(8);
+        __process3_stack_base__ = .;
+        . += __process3_stack_size__;
+        . = ALIGN(8);
+        __process3_stack_end__ = .;
+        __process2_stack_base__ = .;
+        . += __process2_stack_size__;
+        . = ALIGN(8);
+        __process2_stack_end__ = .;
+        __process1_stack_base__ = .;
+        . += __process1_stack_size__;
+        . = ALIGN(8);
+        __process1_stack_end__ = .;
+        __process0_stack_base__ = .;
+        . += __process0_stack_size__;
+        . = ALIGN(8);
+        __process0_stack_end__ = .;
+    } > ram
+
+    .main_stack :
+    {
+        . = ALIGN(8);
+        __main_stack_base__ = .;
+        . += __main_stack_size__;
+        . = ALIGN(8);
+        __main_stack_end__ = .;
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;
--- a/example-fsm-55/hh.c
+++ b/example-fsm-55/hh.c
@@ -0,0 +1,461 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+
+#include "board.h"
+
+static uint8_t main_finished;
+
+#define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
+
+struct GPIO {
+  volatile uint32_t MODER;
+  volatile uint16_t OTYPER;
+  uint16_t dummy0;
+  volatile uint32_t OSPEEDR;
+  volatile uint32_t PUPDR;
+  volatile uint16_t IDR;
+  uint16_t dummy1;
+  volatile uint16_t ODR;
+  uint16_t dummy2;
+  volatile uint16_t BSRR;
+  uint16_t dummy3;
+  volatile uint32_t LCKR;
+  volatile uint32_t AFR[2];
+  volatile uint16_t BRR;
+  uint16_t dummy4;
+};
+#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
+#define GPIOF		((struct GPIO *) GPIOF_BASE)
+
+static struct GPIO *const GPIO_LED = ((struct GPIO *)GPIO_LED_BASE);
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *)GPIO_OTHER_BASE);
+
+static chopstx_mutex_t mtx;
+static chopstx_cond_t cnd0, cnd1;
+
+#define BUTTON_PUSHED 1
+static uint8_t button_state;
+
+static uint8_t
+user_button (void)
+{
+  return button_state;
+}
+
+
+static uint8_t l_data[5];
+#define LED_FULL ((0x1f << 20)|(0x1f << 15)|(0x1f << 10)|(0x1f << 5)|0x1f)
+
+static void
+set_led_display (uint32_t data)
+{
+  l_data[0] = (data >>  0) & 0x1f;
+  l_data[1] = (data >>  5) & 0x1f;
+  l_data[2] = (data >> 10) & 0x1f;
+  l_data[3] = (data >> 15) & 0x1f;
+  l_data[4] = (data >> 20) & 0x1f;
+}
+
+static void
+scroll_led_display (uint8_t row)
+{
+  l_data[0] = (l_data[0] << 1) | ((row >> 0) & 1);
+  l_data[1] = (l_data[1] << 1) | ((row >> 1) & 1);
+  l_data[2] = (l_data[2] << 1) | ((row >> 2) & 1);
+  l_data[3] = (l_data[3] << 1) | ((row >> 3) & 1);
+  l_data[4] = (l_data[4] << 1) | ((row >> 4) & 1);
+}
+
+
+static void
+wait_for (uint32_t usec)
+{
+  chopstx_usec_wait (usec);
+}
+
+static void
+led_prepare_row (uint8_t col)
+{
+  uint16_t data = 0x1f;
+
+  data |= ((l_data[0] & (1 << col)) ? 1 : 0) << 5;
+  data |= ((l_data[1] & (1 << col)) ? 1 : 0) << 6;
+  data |= ((l_data[2] & (1 << col)) ? 1 : 0) << 7;
+  data |= ((l_data[3] & (1 << col)) ? 1 : 0) << 9;
+  data |= ((l_data[4] & (1 << col)) ? 1 : 0) << 10;
+  GPIO_LED->ODR = data;
+}
+
+
+static void
+led_enable_column (uint8_t col)
+{
+  GPIO_LED->BRR = (1 << col);
+}
+
+static void *
+led (void *arg)
+{
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd0, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (!main_finished)
+    {
+      int i;
+
+      for (i = 0; i < 5; i++)
+	{
+	  led_prepare_row (i);
+	  led_enable_column (i);
+	  wait_for (1000);
+	}
+    }
+
+  GPIO_LED->ODR = 0x0000;	/* Off all LEDs.  */
+  GPIO_LED->OSPEEDR = 0;
+  GPIO_LED->OTYPER = 0;
+  GPIO_LED->MODER = 0;		/* Input mode.  */
+  GPIO_OTHER->PUPDR = 0x0000;	/* No pull-up.  */
+
+  return NULL;
+}
+
+
+static uint8_t get_button_sw (void) { return (GPIO_OTHER->IDR & 1) == 0; }
+
+static void *
+button (void *arg)
+{
+  uint8_t last_button = 0;
+
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd1, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (!main_finished)
+    {
+      uint8_t button = get_button_sw ();
+
+      if (last_button == button && button != button_state)
+	{
+	  wait_for (1000);
+	  button = get_button_sw ();
+	  if (last_button == button)
+	    button_state = button;
+	}
+
+      wait_for (2000);
+      last_button = button;
+    }
+
+  return NULL;
+}
+
+#define PRIO_LED 3
+#define PRIO_BUTTON 2
+
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
+
+#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
+
+#define STACK_ADDR_BUTTON ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BUTTON ((uint32_t)__process2_stack_size__)
+
+#define DATA55(x0,x1,x2,x3,x4) (x0<<20)|(x1<<15)|(x2<<10)|(x3<< 5)|(x4<< 0)
+#define SIZE55(img) (sizeof (img) / sizeof (uint32_t))
+
+static uint32_t l55[] = {
+  DATA55 (0x08, 0x04, 0x1c, 0x00, 0x00),
+  DATA55 (0x00, 0x14, 0x0c, 0x08, 0x00),
+  DATA55 (0x00, 0x04, 0x14, 0x0c, 0x00),
+  DATA55 (0x00, 0x08, 0x06, 0x0c, 0x00),
+  DATA55 (0x00, 0x04, 0x02, 0x0e, 0x00),
+  DATA55 (0x00, 0x00, 0x0a, 0x06, 0x04),
+  DATA55 (0x00, 0x00, 0x02, 0x0a, 0x06),
+  DATA55 (0x00, 0x00, 0x04, 0x03, 0x06),
+  DATA55 (0x00, 0x00, 0x02, 0x01, 0x07),
+  DATA55 (0x02, 0x00, 0x00, 0x05, 0x03),
+  DATA55 (0x03, 0x00, 0x00, 0x01, 0x05),
+  DATA55 (0x03, 0x00, 0x00, 0x02, 0x11),
+  DATA55 (0x13, 0x00, 0x00, 0x01, 0x10),
+  DATA55 (0x11, 0x01, 0x00, 0x00, 0x12),
+  DATA55 (0x12, 0x11, 0x00, 0x00, 0x10),
+  DATA55 (0x18, 0x11, 0x00, 0x00, 0x01),
+  DATA55 (0x08, 0x19, 0x00, 0x00, 0x10),
+  DATA55 (0x09, 0x18, 0x10, 0x00, 0x00),
+  DATA55 (0x08, 0x09, 0x18, 0x00, 0x00),
+  DATA55 (0x10, 0x0c, 0x18, 0x00, 0x00),
+};
+
+#define DATA55V(x0,x1,x2,x3,x4) (x0<<0)|(x1<<5)|(x2<<10)|(x3<< 15)|(x4<< 20)
+
+#define CHAR_SPC 0
+#define CHAR_H   1
+#define CHAR_A   2
+#define CHAR_P   3
+#define CHAR_Y   4
+#define CHAR_C   5
+#define CHAR_K   6
+#define CHAR_I   7
+#define CHAR_N   8
+#define CHAR_G   9
+#define CHAR_EXC 10
+#define CHAR_W   11
+#define CHAR_h   12
+#define CHAR_t   13
+#define CHAR_AP  14
+#define CHAR_s   15
+#define CHAR_U   16
+#define CHAR_QT  17
+#define CHAR_o   18
+#define CHAR_X   19
+
+static uint8_t hh[] = {
+  CHAR_H, CHAR_A, CHAR_P, CHAR_P, CHAR_Y,
+  CHAR_SPC,
+  CHAR_H, CHAR_A, CHAR_C, CHAR_K, CHAR_I, CHAR_N, CHAR_G,
+  CHAR_EXC,
+  CHAR_SPC, CHAR_SPC, CHAR_SPC,
+};
+
+static uint8_t gnu[] = {
+  CHAR_W, CHAR_h, CHAR_A, CHAR_t, CHAR_AP, CHAR_s, CHAR_SPC,
+  CHAR_G, CHAR_N, CHAR_U, CHAR_QT, 
+  CHAR_SPC, CHAR_SPC,
+  CHAR_G, CHAR_N, CHAR_U, CHAR_AP, CHAR_s, CHAR_SPC,
+  CHAR_N, CHAR_o, CHAR_t, CHAR_SPC,
+  CHAR_U, CHAR_N, CHAR_I, CHAR_X,
+  CHAR_EXC,
+  CHAR_SPC, CHAR_SPC,
+};
+
+struct { uint8_t width; uint32_t data; } chargen[] = {
+  { 3, 0 },						/* SPACE */
+  { 4, DATA55V (0x1f, 0x04, 0x04, 0x1f, 0x00) },	/* H */
+  { 3, DATA55V (0x17, 0x15, 0x0f, 0x00, 0x00) },	/* A */
+  { 4, DATA55V (0x1f, 0x14, 0x14, 0x08, 0x00) },	/* P */
+  { 4, DATA55V (0x19, 0x05, 0x05, 0x1e, 0x00) },	/* Y */
+  { 4, DATA55V (0x0e, 0x11, 0x11, 0x0a, 0x00) },	/* C */
+  { 4, DATA55V (0x1f, 0x04, 0x0c, 0x13, 0x00) },	/* K */
+  { 3, DATA55V (0x11, 0x1f, 0x11, 0x00, 0x00) },	/* I */
+  { 4, DATA55V (0x1f, 0x08, 0x06, 0x1f, 0x00) },	/* N */
+  { 4, DATA55V (0x0e, 0x11, 0x15, 0x07, 0x00) },	/* G */
+  { 2, DATA55V (0x1d, 0x1c, 0x00, 0x00, 0x00) },	/* ! */
+  { 5, DATA55V (0x1e, 0x01, 0x0e, 0x01, 0x1e) },	/* W */
+  { 3, DATA55V (0x1f, 0x04, 0x07, 0x00, 0x00) },	/* h */
+  { 4, DATA55V (0x08, 0x1e, 0x09, 0x09, 0x00) },	/* t */
+  { 3, DATA55V (0x04, 0x18, 0x18, 0x00, 0x00) },	/* ' */
+  { 4, DATA55V (0x09, 0x15, 0x15, 0x12, 0x00) },	/* s */
+  { 4, DATA55V (0x1e, 0x01, 0x01, 0x1e, 0x00) },	/* U */
+  { 4, DATA55V (0x08, 0x10, 0x15, 0x08, 0x00) },	/* ? */
+  { 4, DATA55V (0x06, 0x09, 0x09, 0x06, 0x00) },	/* o */
+  { 5, DATA55V (0x11, 0x0a, 0x04, 0x0a, 0x11) },	/* X */
+  { 4, DATA55V (0x1f, 0x11, 0x11, 0x0e, 0x00) },	/* D */
+  { 4, DATA55V (0x0e, 0x15, 0x15, 0x0d, 0x00) },	/* e */
+  { 4, DATA55V (0x1f, 0x05, 0x05, 0x06, 0x00) },	/* b */
+  { 1, DATA55V (0x17, 0x00, 0x00, 0x00, 0x00) },	/* i */
+  { 4, DATA55V (0x02, 0x15, 0x15, 0x0f, 0x00) },	/* a */
+  { 4, DATA55V (0x0f, 0x08, 0x08, 0x0f, 0x00) },	/* n */
+};
+
+
+#define REPEAT_COUNT 10
+
+static int
+life_display (void)
+{
+  unsigned int i;
+  uint8_t count = 0;
+  uint8_t state = 0;
+
+  while (count++ < REPEAT_COUNT)
+    for (i = 0; i < SIZE55 (l55); i++)
+      {
+	if (user_button ())
+	  {
+	    set_led_display (LED_FULL);
+	    state = 1;
+	  }
+	else if (state == 1)
+	  return 0;
+	else
+	  set_led_display (l55[i]);
+	wait_for (350*1000);
+      }
+
+  return 1;
+}
+
+
+static int
+text_display (uint8_t kind)
+{
+  unsigned int i, j;
+  uint8_t *text;
+  uint8_t len;
+  uint8_t count = 0;
+  uint8_t state = 0;
+
+  if (kind)
+    {
+      text = hh;
+      len = sizeof (hh);
+    }
+  else
+    {
+      text = gnu;
+      len = sizeof (gnu);
+    }
+
+  set_led_display (0);
+  while (count++ < REPEAT_COUNT)
+    for (i = 0; i < len; i++)
+      {
+	for (j = 0; j < chargen[text[i]].width; j++)
+	  {
+	    if (user_button ())
+	      {
+		set_led_display (LED_FULL);
+		state = 1;
+	      }
+	    else if (state == 1)
+	      return 0;
+	    else
+	      scroll_led_display ((chargen[text[i]].data >> j * 5) & 0x1f);
+	    wait_for (120*1000);
+	  }
+
+	if (user_button ())
+	  {
+	    set_led_display (LED_FULL);
+	    state = 1;
+	  }
+	else if (state == 1)
+	  return 0;
+	else
+	  scroll_led_display (0);
+	wait_for (120*1000);
+      }
+
+  return 1;
+}
+
+
+static void setup_scr_sleepdeep (void);
+
+int
+main (int argc, const char *argv[])
+{
+  chopstx_t led_thd;
+  chopstx_t button_thd;
+  uint8_t happy = 1;
+  (void)argc;
+  (void)argv;
+
+  chopstx_mutex_init (&mtx);
+  chopstx_cond_init (&cnd0);
+  chopstx_cond_init (&cnd1);
+
+  led_thd = chopstx_create (PRIO_LED, STACK_ADDR_LED,
+			    STACK_SIZE_LED, led, NULL);
+  button_thd = chopstx_create (PRIO_BUTTON, STACK_ADDR_BUTTON,
+			       STACK_SIZE_BUTTON, button, NULL);
+
+  chopstx_usec_wait (200*1000);
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_signal (&cnd0);
+  chopstx_cond_signal (&cnd1);
+  chopstx_mutex_unlock (&mtx);
+
+  wait_for (100*1000);
+  if (user_button ())
+    {
+      /* Wait button release.  */
+      while (user_button ())
+	wait_for (100*1000);
+
+      happy = 0;
+      goto do_text;
+    }
+
+  while (1)
+    {
+      if (life_display ())
+	break;
+    do_text:
+      if (text_display (happy))
+	break;
+    }
+
+  main_finished = 1;
+  chopstx_join (button_thd, NULL);
+  chopstx_join (led_thd, NULL);
+
+  setup_scr_sleepdeep ();
+  for (;;)
+    asm volatile ("wfi" : : : "memory");
+
+  return 0;
+}
+
+struct SCB
+{
+  volatile uint32_t CPUID;
+  volatile uint32_t ICSR;
+  volatile uint32_t VTOR;
+  volatile uint32_t AIRCR;
+  volatile uint32_t SCR;
+  volatile uint32_t CCR;
+  volatile uint8_t  SHP[12];
+  volatile uint32_t SHCSR;
+  volatile uint32_t CFSR;
+  volatile uint32_t HFSR;
+  volatile uint32_t DFSR;
+  volatile uint32_t MMFAR;
+  volatile uint32_t BFAR;
+  volatile uint32_t AFSR;
+  volatile uint32_t PFR[2];
+  volatile uint32_t DFR;
+  volatile uint32_t ADR;
+  volatile uint32_t MMFR[4];
+  volatile uint32_t ISAR[5];
+};
+
+#define SCS_BASE	(0xE000E000)
+#define SCB_BASE	(SCS_BASE +  0x0D00)
+static struct SCB *const SCB = ((struct SCB *)SCB_BASE);
+
+#define SCB_SCR_SLEEPDEEP (1 << 2)
+
+struct PWR
+{
+  volatile uint32_t CR;
+  volatile uint32_t CSR;
+};
+#define PWR_CR_PDDS 0x0002
+#define PWR_CR_CWUF 0x0004
+
+#define PWR_BASE	(APBPERIPH_BASE + 0x00007000)
+#define PWR		((struct PWR *) PWR_BASE)
+
+static void setup_scr_sleepdeep (void)
+{
+  PWR->CR |= PWR_CR_CWUF;
+  PWR->CR |= PWR_CR_PDDS;
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+}
--- a/example-fsm-55/hh.txt
+++ b/example-fsm-55/hh.txt
@@ -0,0 +1,59 @@
+o..o
+o..o
+oooo
+o..o
+o..o
+
+oo.
+..o
+ooo
+o.o
+ooo
+
+ooo.
+o..o
+ooo.
+o...
+o...
+
+o..o
+o..o
+.ooo
+...o
+ooo.
+
+.oo.
+o..o
+o...
+o..o
+.oo.
+
+o..o
+o.o.
+ooo.
+o..o
+o..o
+
+ooo
+.o.
+.o.
+.o.
+ooo
+
+o..o
+oo.o
+o.oo
+o.oo
+o..o
+
+.oo.
+o...
+o.oo
+o..o
+.ooo
+
+oo
+oo
+oo
+..
+o.
--- a/example-fsm-55/hiroshi-ayumi.c
+++ b/example-fsm-55/hiroshi-ayumi.c
@@ -0,0 +1,385 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <chopstx.h>
+
+#include "board.h"
+
+#define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
+
+struct GPIO {
+  volatile uint32_t MODER;
+  volatile uint16_t OTYPER;
+  uint16_t dummy0;
+  volatile uint32_t OSPEEDR;
+  volatile uint32_t PUPDR;
+  volatile uint16_t IDR;
+  uint16_t dummy1;
+  volatile uint16_t ODR;
+  uint16_t dummy2;
+  volatile uint16_t BSRR;
+  uint16_t dummy3;
+  volatile uint32_t LCKR;
+  volatile uint32_t AFR[2];
+  volatile uint16_t BRR;
+  uint16_t dummy4;
+};
+#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
+#define GPIOF		((struct GPIO *) GPIOF_BASE)
+
+#define GPIO_SPEAKER_PIN    1
+
+static struct GPIO *const GPIO_LED = ((struct GPIO *)GPIO_LED_BASE);
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *)GPIO_OTHER_BASE);
+
+static chopstx_mutex_t mtx;
+static chopstx_cond_t cnd;
+
+static uint8_t
+user_button (void)
+{
+  return (GPIO_OTHER->IDR & 1) == 0;
+}
+
+static uint8_t l_data[5];
+
+static void
+set_led_display (uint32_t data)
+{
+  l_data[0] = (data >>  0) & 0x1f;
+  l_data[1] = (data >>  5) & 0x1f;
+  l_data[2] = (data >> 10) & 0x1f;
+  l_data[3] = (data >> 15) & 0x1f;
+  l_data[4] = (data >> 20) & 0x1f;
+}
+
+
+static void
+wait_for (uint32_t usec)
+{
+  chopstx_usec_wait (usec);
+}
+
+static void
+led_prepare_row (uint8_t col)
+{
+  uint16_t data = 0x1f;
+
+  data |= ((l_data[0] & (1 << col)) ? 1 : 0) << 5;
+  data |= ((l_data[1] & (1 << col)) ? 1 : 0) << 6;
+  data |= ((l_data[2] & (1 << col)) ? 1 : 0) << 7;
+  data |= ((l_data[3] & (1 << col)) ? 1 : 0) << 9;
+  data |= ((l_data[4] & (1 << col)) ? 1 : 0) << 10;
+  GPIO_LED->ODR = data;
+}
+
+static void
+led_enable_column (uint8_t col)
+{
+  GPIO_LED->BRR = (1 << col);
+}
+
+
+#define PRIO_LED 3
+
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+
+#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
+
+static void *
+led (void *arg)
+{
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (1)
+    {
+      int i;
+
+      for (i = 0; i < 5; i++)
+	{
+	  led_prepare_row (i);
+	  led_enable_column (i);
+	  wait_for (1000);
+	}
+    }
+
+  return NULL;
+}
+
+
+#define PRIO_SPK 4
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
+
+#define STACK_ADDR_SPK ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_SPK ((uint32_t)__process2_stack_size__)
+
+static chopstx_mutex_t spk_mtx;
+static chopstx_cond_t spk_cnd;
+static chopstx_cond_t spk_cnd_no_tone;
+
+static uint8_t tone;
+#define NO_TONE 255
+
+
+static uint16_t tone_table[] = {
+  568, /* a = 880Hz */
+  /* 536, */
+  506, /* b */
+  478, /* c */
+  /* 451, */
+  426, /* d */
+  /* 402, */
+  379, /* e */
+  358, /* f*/
+  /* 338, */
+  319, /* g */
+  /* 301, */
+  284, /* A = 1760Hz */
+  /* 268 */
+  253, /* B */
+  239, /* C */
+};
+
+static void
+change_tone (uint8_t t)
+{
+  chopstx_mutex_lock (&spk_mtx);
+  tone = t;
+  chopstx_cond_signal (&spk_cnd_no_tone);
+  chopstx_cond_wait (&spk_cnd, &spk_mtx);
+  chopstx_mutex_unlock (&spk_mtx);
+}
+
+static void *
+spk (void *arg)
+{
+  (void)arg;
+
+  while (1)
+    {
+      uint8_t t;
+      uint16_t w;
+
+      chopstx_mutex_lock (&spk_mtx);
+      t = tone;
+      chopstx_cond_signal (&spk_cnd);
+      if (t == NO_TONE)
+	{
+	  chopstx_cond_wait (&spk_cnd_no_tone, &spk_mtx);
+	  t = tone;
+	}
+      chopstx_mutex_unlock (&spk_mtx);
+
+      w = tone_table[t]*5/3;
+      GPIO_OTHER->BSRR = (1 << GPIO_SPEAKER_PIN);
+      wait_for (w);
+      GPIO_OTHER->BRR = (1 << GPIO_SPEAKER_PIN);
+      wait_for (w);
+    }
+
+  return NULL;
+}
+
+
+#define PRIO_MUSIC 2
+extern uint8_t __process3_stack_base__[], __process3_stack_size__[];
+
+#define STACK_ADDR_MUSIC ((uint32_t)__process3_stack_base__)
+#define STACK_SIZE_MUSIC ((uint32_t)__process3_stack_size__)
+
+#define C 0
+#define D 1
+#define E 2
+#define F 3
+#define G 4
+#define A 5
+#define B 6
+
+#if 0 /* twinkle stars */
+static const char *musical_score = 
+  "c4c4g4g4A4A4g2f4f4e4e4d4d4c2"
+  "g4g4f4f4e4e4d2g4g4f4f4e4e4d2"
+  "c4c4g4g4A4A4g2f4f4e4e4d4d4c2";
+#else /* tulip */
+static const char *musical_score = 
+  "c4d4e2c4d4e2g4e4d4c4d4e4d2"
+  "c4d4e2c4d4e2g4e4d4c4d4e4c2"
+  "g4g4e4g4A4A4g2e4e4d4d4c2";
+#endif
+
+static int get_t_and_l (char *tp, char *lp)
+{
+  static unsigned int i = 0;
+  char tl, ll;
+
+  tl = musical_score[i++];
+  ll = musical_score[i++];
+
+  if (tl >= 'a')
+    *tp = tl - 'a';
+  else
+    *tp = tl - 'A' + 7;
+
+  *lp = ll - '0';
+
+  if (i >= strlen (musical_score))
+    {
+      i = 0;
+      return 0;
+    }
+  else
+    return 1;
+}
+
+#define WAIT_FOR_NO_TONE (1000*20)
+#define WAIT_FOR_TONE (1000000*3/2)
+
+static void *
+music (void *arg)
+{
+  (void)arg;
+
+  chopstx_mutex_init (&spk_mtx);
+  chopstx_cond_init (&spk_cnd);
+  chopstx_cond_init (&spk_cnd_no_tone);
+
+  chopstx_create (PRIO_SPK, STACK_ADDR_SPK, STACK_SIZE_SPK, spk, NULL);
+
+  while (1)
+    {
+      char t, l;
+      int r;
+
+      r = get_t_and_l (&t, &l);
+
+      change_tone (NO_TONE);
+      wait_for (WAIT_FOR_NO_TONE);
+      change_tone (t);
+      wait_for (WAIT_FOR_TONE / l);
+
+      if (!r)
+	{
+	  change_tone (NO_TONE);
+	  wait_for (WAIT_FOR_TONE * 3);
+	}
+    }
+
+  return NULL;
+}
+
+
+
+#define DATA55(x0,x1,x2,x3,x4) (x0<<20)|(x1<<15)|(x2<<10)|(x3<< 5)|(x4<< 0)
+#define SIZE55(img) (sizeof (img) / sizeof (uint32_t))
+
+static uint32_t image0[] = {
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x01,0x00,0x00,0x00),
+  DATA55 (0x01,0x03,0x01,0x01,0x00),
+  DATA55 (0x02,0x06,0x02,0x02,0x01),
+  DATA55 (0x05,0x0d,0x05,0x05,0x03),
+  DATA55 (0x0b,0x1a,0x0a,0x0a,0x06),
+  DATA55 (0x16,0x14,0x14,0x14,0x0c),
+  DATA55 (0x0d,0x08,0x09,0x08,0x19),
+  DATA55 (0x1b,0x11,0x12,0x10,0x13),
+  DATA55 (0x17,0x03,0x04,0x00,0x07),
+  DATA55 (0x0f,0x06,0x09,0x01,0x0e),
+  DATA55 (0x1e,0x0c,0x12,0x02,0x1c),
+  DATA55 (0x1d,0x19,0x05,0x05,0x18),
+  DATA55 (0x1a,0x12,0x0a,0x0a,0x11),
+  DATA55 (0x14,0x04,0x14,0x14,0x03),
+  DATA55 (0x08,0x08,0x08,0x09,0x06),
+  DATA55 (0x10,0x10,0x10,0x12,0x0c),
+  DATA55 (0x00,0x00,0x00,0x04,0x18),
+  DATA55 (0x00,0x00,0x00,0x08,0x10),
+  DATA55 (0x00,0x00,0x00,0x10,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+};
+
+static uint32_t image1[] = {
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x01,0x00,0x00,0x00,0x01),
+  DATA55 (0x03,0x00,0x00,0x01,0x03),
+  DATA55 (0x07,0x01,0x01,0x03,0x06),
+  DATA55 (0x0f,0x02,0x02,0x06,0x0c),
+  DATA55 (0x1f,0x05,0x05,0x0c,0x18),
+  DATA55 (0x1e,0x0a,0x0a,0x18,0x11),
+  DATA55 (0x1d,0x14,0x14,0x10,0x03),
+  DATA55 (0x1b,0x08,0x08,0x00,0x07),
+  DATA55 (0x17,0x11,0x11,0x01,0x0f),
+  DATA55 (0x0e,0x02,0x02,0x02,0x1f),
+  DATA55 (0x1c,0x04,0x04,0x04,0x1e),
+  DATA55 (0x19,0x08,0x09,0x08,0x1d),
+  DATA55 (0x13,0x10,0x13,0x10,0x1b),
+  DATA55 (0x07,0x00,0x07,0x00,0x17),
+  DATA55 (0x0f,0x00,0x0f,0x00,0x0f),
+  DATA55 (0x1e,0x00,0x1e,0x00,0x1e),
+  DATA55 (0x1c,0x00,0x1c,0x00,0x1c),
+  DATA55 (0x18,0x00,0x18,0x00,0x18),
+  DATA55 (0x10,0x00,0x10,0x00,0x10),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+  DATA55 (0x00,0x00,0x00,0x00,0x00),
+};
+
+int
+main (int argc, const char *argv[])
+{
+  uint8_t state = 0;
+
+  (void)argc;
+  (void)argv;
+
+  chopstx_mutex_init (&mtx);
+  chopstx_cond_init (&cnd);
+
+  chopstx_create (PRIO_LED, STACK_ADDR_LED, STACK_SIZE_LED, led, NULL);
+  chopstx_create (PRIO_MUSIC, STACK_ADDR_MUSIC, STACK_SIZE_MUSIC, music, NULL);
+
+  chopstx_usec_wait (200*1000);
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_signal (&cnd);
+  chopstx_mutex_unlock (&mtx);
+
+  while (1)
+    {
+      unsigned int i;
+
+      if (state)
+	for (i = 0; i < SIZE55 (image1); i++)
+	  {
+	    if (user_button ())
+	      state = 0;
+	    set_led_display (image1[i]);
+	    wait_for (200*1000);
+	  }
+      else
+	for (i = 0; i < SIZE55 (image0); i++)
+	  {
+	    if (user_button ())
+	      state = 1;
+	    set_led_display (image0[i]);
+	    wait_for (200*1000);
+	  }
+    }
+
+  return 0;
+}
--- a/example-fsm-55/l55.txt
+++ b/example-fsm-55/l55.txt
@@ -0,0 +1,119 @@
+_*___  08
+__*__  04
+***__  1c
+_____  00
+_____  00
+
+_____  00
+*_*__  14
+_**__  0c
+_*___  08
+_____  00
+
+_____  00
+__*__  04
+*_*__  14
+_**__  0c
+_____  00
+
+_____  00
+_*__   08
+__**_  06
+_**__  0c
+_____  00
+
+_____  00
+__*__  04
+___*_  02
+_***_  0e
+_____  00
+
+_____  00
+_____  00
+_*_*_  0a
+__**_  06
+__*__  04
+
+_____  00
+_____  00
+___*_  02
+_*_*_  0a
+__**_  06
+
+_____  00
+_____  00
+__*__  04
+___**  03
+__**_  06
+
+_____  00
+_____  00
+ __*_  02
+____*  01
+__***  07
+
+___*_  02
+_____  00
+_____  00
+__*_*  05
+___**  03
+
+___**  03
+_____  00
+_____  00
+____*  01
+__*_*  05
+
+___**  03
+_____  00
+_____  00
+_ _*_  02
+*___*  11
+
+*__**  13
+_____  00
+_____  00
+____*  01
+*____  10
+
+*___*  11
+____*  01
+_____  00
+_____  00
+*__*_  12
+
+*__*_  12
+*___*  11
+_____  00
+_____  00
+*____  10
+
+**___  18
+*___*  11
+_____  00
+_____  00
+____*  01
+
+_*___  08
+**__*  19
+_____  00
+_____  00
+*____  10
+
+_*__*  09
+**___  18
+*____  10
+_____  00
+_____  00
+
+_*___  08
+_*__*  09
+**___  18
+_____  00
+_____  00
+
+*____  10
+_**__  0c
+**___  18
+_____  00
+_____  00
--- a/example-fsm-55/name.txt
+++ b/example-fsm-55/name.txt
@@ -0,0 +1,287 @@
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+_____ 00
+____* 01
+_____ 00
+_____ 00
+_____ 00
+
+____* 01
+___** 03
+____* 01
+____* 01
+_____ 00
+
+___*_ 02
+__**_ 06
+___*_ 02
+___*_ 02
+____* 01
+
+__*_* 05
+_**_* 0d
+__*_* 05
+__*_* 05
+___** 03
+
+_*_** 0b
+**_*_ 1a
+_*_*_ 0a
+_*_*_ 0a
+__**_ 06
+
+*_**_ 16
+*_*__ 14
+*_*__ 14
+*_*__ 14
+_**__ 0c
+
+_**_* 0d
+_*___ 08
+_*__* 09
+_*___ 08
+**__* 19
+
+**_** 1b
+*___* 11
+*__*_ 12
+*____ 10
+*__** 13
+
+*_*** 17
+___** 03
+__*__ 04
+_____ 00
+__*** 07
+
+_**** 0f
+__**_ 06
+_*__* 09
+____* 01
+_***_ 0e
+
+****_ 1e
+_**__ 0c
+*__*_ 12
+___*_ 02
+***__ 1c
+
+***_* 1d
+**__* 19
+__*_* 05
+__*_* 05
+**___ 18
+
+**_*_ 1a
+*__*_ 12
+_*_*_ 0a
+_*_*_ 0a
+*___* 11
+
+*_*__ 14
+__*__ 04
+*_*__ 14
+*_*__ 14
+___** 03
+
+_*___ 08
+_*___ 08
+_*___ 08
+_*__* 09
+__**_ 06
+
+*____ 10
+*____ 10
+*____ 10
+*__*_ 12
+_**__ 0c
+
+_____ 00
+_____ 00
+_____ 00
+__*__ 04
+**___ 18
+
+_____ 00
+_____ 00
+_____ 00
+_*___ 08
+*____ 10
+
+_____ 00
+_____ 00
+_____ 00
+*____ 10
+_____ 00
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+____* 01
+_____ 00
+_____ 00
+_____ 00
+____* 01
+
+___** 03
+_____ 00
+_____ 00
+____* 01
+___** 03
+
+__*** 07
+____* 01
+____* 01
+___** 03
+__**_ 06
+
+_**** 0f
+___*_ 02
+___*_ 02
+__**_ 06
+_**__ 0c
+
+***** 1f
+__*_* 05
+__*_* 05
+_**__ 0c
+**___ 18
+
+****_ 1e
+_*_*_ 0a
+_*_*_ 0a
+**___ 18
+*___* 11
+
+***_* 1d
+*_*__ 14
+*_*__ 14
+*____ 10
+___** 03
+
+**_** 1b
+_*___ 08
+_*___ 08
+_____ 00
+__*** 07
+
+*_*** 17
+*___* 11
+*___* 11
+____* 01
+_**** 0f
+
+_***_ 0e
+___*_ 02
+___*_ 02
+___*_ 02
+***** 1f
+
+***__ 1c
+__*__ 04
+__*__ 04
+__*__ 04
+****_ 1e
+
+**__* 19
+_*___ 08
+_*__* 09
+_*___ 08
+***_* 1d
+
+*__** 13
+*____ 10
+*__** 13
+*____ 10
+**_** 1b
+
+__*** 07
+_____ 00
+__*** 07
+_____ 00
+*_*** 17
+
+_**** 0f
+_____ 00
+_**** 0f
+_____ 00
+_**** 0f
+
+****_ 1e
+_____ 00
+****_ 1e
+_____ 00
+****_ 1e
+
+***__ 1c
+_____ 00
+***__ 1c
+_____ 00
+***__ 1c
+
+**___ 18
+_____ 00
+**___ 18
+_____ 00
+**___ 18
+
+*____ 10
+_____ 00
+*____ 10
+_____ 00
+*____ 10
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+
+_____ 00
+_____ 00
+_____ 00
+_____ 00
+_____ 00
--- a/example-fsm-55/reset.c
+++ b/example-fsm-55/reset.c
@@ -0,0 +1,110 @@
+/*
+ * reset.c - No system routines, but only RESET handler for STM32F030.
+ *
+ * Copyright (C) 2015 Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * Copying and distribution of this file, with or without modification,
+ * are permitted in any medium without royalty provided the copyright
+ * notice and this notice are preserved.  This file is offered as-is,
+ * without any warranty.
+ *
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+
+static void __attribute__ ((naked))
+reset (void)
+{
+  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
+		"mov	r0, pc\n\t"	/* r0 = PC & ~0x0fff */
+		"mov	r1, #0x10\n\t"
+		"lsl	r1, #8\n\t"
+		"sub	r1, r1, #1\n\t"
+		"bic	r0, r0, r1\n\t"
+		"ldr	r2, [r0]\n\t"
+		"msr	MSP, r2\n\t"	/* Main (exception handler) stack. */
+		"b	entry\n\t"
+		: /* no output */ : /* no input */ : "memory");
+  /* Never reach here. */
+}
+
+extern uint8_t __main_stack_end__;
+extern void preempt (void);
+extern void chx_timer_expired (void);
+extern void chx_handle_intr (void);
+
+static void nmi (void)
+{
+  for (;;);
+}
+
+static void __attribute__ ((naked))
+hard_fault (void)
+{
+  for (;;);
+}
+
+static void mem_manage (void)
+{
+  for (;;);
+}
+
+static void bus_fault (void)
+{
+  for (;;);
+}
+
+static void usage_fault (void)
+{
+  for (;;);
+}
+
+static void none (void)
+{
+}
+
+
+typedef void (*handler)(void);
+extern uint8_t __main_stack_end__;
+
+handler vector[] __attribute__ ((section(".vectors"))) = {
+  (handler)(&__main_stack_end__ - 32),
+  reset,
+  nmi,		/* nmi */
+  hard_fault,		/* hard fault */
+  /* 0x10 */
+  mem_manage,		/* mem manage */
+  bus_fault,		/* bus fault */
+  usage_fault,		/* usage fault */
+  none,
+  /* 0x20 */
+  none, none, none,		/* reserved */
+  none,				/* SVCall */
+  none,				/* Debug */
+  none,				/* reserved */
+  preempt,			/* PendSV */
+  chx_timer_expired,		/* SysTick */
+  /* 0x40 */
+  chx_handle_intr /* WWDG */,     chx_handle_intr /* PVD */,
+  chx_handle_intr /* TAMPER */,   chx_handle_intr /* RTC */,
+  chx_handle_intr /* FLASH */,    chx_handle_intr /* RCC */,
+  chx_handle_intr /* EXTI0 */,    chx_handle_intr /* EXTI1 */,
+  /* 0x60 */
+  chx_handle_intr /* EXTI2 */,    chx_handle_intr /* EXTI3 */,
+  chx_handle_intr /* EXTI4 */,    chx_handle_intr /* DMA1 CH1 */,
+  chx_handle_intr /* DMA1 CH2 */, chx_handle_intr /* DMA1 CH3 */,
+  chx_handle_intr /* DMA1 CH4 */, chx_handle_intr /* DMA1 CH5 */,
+  /* 0x80 */
+  chx_handle_intr /* DMA1 CH6 */, chx_handle_intr /* DMA1 CH7 */,
+  chx_handle_intr /* ADC1_2 */,   chx_handle_intr /* USB HP */,
+  /* 0x90 */
+  chx_handle_intr /* USB LP */,   chx_handle_intr /* CAN */, 
+  /* ... and more.  EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
+  chx_handle_intr,                chx_handle_intr,
+  /* 0xA0 */
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  /* 0xc0 */
+};
--- a/example-fsm-55/stlink-v2.cfg
+++ b/example-fsm-55/stlink-v2.cfg
@@ -0,0 +1,12 @@
+# Contributed by Kiwamu Okabe
+
+source [find interface/stlink-v2.cfg]
+transport select hla_swd
+
+# The STM32F030F4P6 is a *tightly* constrained chip; the work area size must be
+# similarly constrained.
+set WORKAREASIZE 0x1000
+source [find target/stm32f0x.cfg]
+
+# use hardware reset, connect under reset
+reset_config srst_only srst_nogate connect_assert_srst
--- a/example-led/Makefile
+++ b/example-led/Makefile
@@ -2,9 +2,16 @@

 PROJECT = sample

+### Currently, it's for STM32F0 Discovery.
+### Please change lines started with '###' for Cortex-M3 board.
+
 CHOPSTX = ..
 LDSCRIPT= sample.ld
-CSRC = sys.c aes-constant-ft.c sample.c
+### LDSCRIPT= sample.ld.m3
+CSRC = sample.c
+
+CHIP=stm32f0
+USE_SYS = yes

 ###################################
 CROSS = arm-none-eabi-
@@ -12,10 +19,11 @@ CC   = $(CROSS)gcc
 LD   = $(CROSS)gcc
 OBJCOPY   = $(CROSS)objcopy

-MCU   = cortex-m3
+### MCU   = cortex-m3
+MCU   = cortex-m0
 CWARN = -Wall -Wextra -Wstrict-prototypes
-DEFS  = -DHAVE_SYS_H -DFREE_STANDING
-# DEFS  = -DFREE_STANDING -DHAVE_SYS_H -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
+DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=48
+### DEFS  = -DFREE_STANDING -DUSE_SYS3 -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
 OPT   = -O3 -Os -g
 LIBS  =

--- a/example-led/aes-constant-ft.c
+++ b/example-led/aes-constant-ft.c
@@ -1,145 +0,0 @@
-/*
- * aes-constant-ft.c - AES forward tables.
- *
- * We need something useful for the initial flash ROM page (4 Ki
- * bytes), which cannot be modified after installation.  Even after
- * upgrade of the firmware, it stays intact.
- *
- * We decide to put 3/4 of AES forward tables to fill 3 Ki bytes, as
- * its useful and it won't change.
- *
- * The code was taken from aes.c of PolarSSL version 0.14, and then,
- * modified to add section names.
- *
- * Since this is just a data, it wouldn't be copyright-able, but the
- * original auther would claim so.  Thus, we put original copyright
- * notice here.  It is highly likely that there will be no such a
- * thing for copyright.  Nevertheless, we think that PolarSSL is good
- * software to address here, and encourage people using it.
- *
- */
-
-#include <stdint.h>
-
-/*
- * Original copyright notice is below:
- */
-
-/*
- *  FIPS-197 compliant AES implementation
- *
- *  Copyright (C) 2006-2010, Brainspark B.V.
- *
- *  This file is part of PolarSSL (http://www.polarssl.org)
- *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-/*
- *  The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
- *
- *  http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
- *  http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
- */
-
-/*
- * Forward tables
- */
-#define FT \
-\
-    V(A5,63,63,C6), V(84,7C,7C,F8), V(99,77,77,EE), V(8D,7B,7B,F6), \
-    V(0D,F2,F2,FF), V(BD,6B,6B,D6), V(B1,6F,6F,DE), V(54,C5,C5,91), \
-    V(50,30,30,60), V(03,01,01,02), V(A9,67,67,CE), V(7D,2B,2B,56), \
-    V(19,FE,FE,E7), V(62,D7,D7,B5), V(E6,AB,AB,4D), V(9A,76,76,EC), \
-    V(45,CA,CA,8F), V(9D,82,82,1F), V(40,C9,C9,89), V(87,7D,7D,FA), \
-    V(15,FA,FA,EF), V(EB,59,59,B2), V(C9,47,47,8E), V(0B,F0,F0,FB), \
-    V(EC,AD,AD,41), V(67,D4,D4,B3), V(FD,A2,A2,5F), V(EA,AF,AF,45), \
-    V(BF,9C,9C,23), V(F7,A4,A4,53), V(96,72,72,E4), V(5B,C0,C0,9B), \
-    V(C2,B7,B7,75), V(1C,FD,FD,E1), V(AE,93,93,3D), V(6A,26,26,4C), \
-    V(5A,36,36,6C), V(41,3F,3F,7E), V(02,F7,F7,F5), V(4F,CC,CC,83), \
-    V(5C,34,34,68), V(F4,A5,A5,51), V(34,E5,E5,D1), V(08,F1,F1,F9), \
-    V(93,71,71,E2), V(73,D8,D8,AB), V(53,31,31,62), V(3F,15,15,2A), \
-    V(0C,04,04,08), V(52,C7,C7,95), V(65,23,23,46), V(5E,C3,C3,9D), \
-    V(28,18,18,30), V(A1,96,96,37), V(0F,05,05,0A), V(B5,9A,9A,2F), \
-    V(09,07,07,0E), V(36,12,12,24), V(9B,80,80,1B), V(3D,E2,E2,DF), \
-    V(26,EB,EB,CD), V(69,27,27,4E), V(CD,B2,B2,7F), V(9F,75,75,EA), \
-    V(1B,09,09,12), V(9E,83,83,1D), V(74,2C,2C,58), V(2E,1A,1A,34), \
-    V(2D,1B,1B,36), V(B2,6E,6E,DC), V(EE,5A,5A,B4), V(FB,A0,A0,5B), \
-    V(F6,52,52,A4), V(4D,3B,3B,76), V(61,D6,D6,B7), V(CE,B3,B3,7D), \
-    V(7B,29,29,52), V(3E,E3,E3,DD), V(71,2F,2F,5E), V(97,84,84,13), \
-    V(F5,53,53,A6), V(68,D1,D1,B9), V(00,00,00,00), V(2C,ED,ED,C1), \
-    V(60,20,20,40), V(1F,FC,FC,E3), V(C8,B1,B1,79), V(ED,5B,5B,B6), \
-    V(BE,6A,6A,D4), V(46,CB,CB,8D), V(D9,BE,BE,67), V(4B,39,39,72), \
-    V(DE,4A,4A,94), V(D4,4C,4C,98), V(E8,58,58,B0), V(4A,CF,CF,85), \
-    V(6B,D0,D0,BB), V(2A,EF,EF,C5), V(E5,AA,AA,4F), V(16,FB,FB,ED), \
-    V(C5,43,43,86), V(D7,4D,4D,9A), V(55,33,33,66), V(94,85,85,11), \
-    V(CF,45,45,8A), V(10,F9,F9,E9), V(06,02,02,04), V(81,7F,7F,FE), \
-    V(F0,50,50,A0), V(44,3C,3C,78), V(BA,9F,9F,25), V(E3,A8,A8,4B), \
-    V(F3,51,51,A2), V(FE,A3,A3,5D), V(C0,40,40,80), V(8A,8F,8F,05), \
-    V(AD,92,92,3F), V(BC,9D,9D,21), V(48,38,38,70), V(04,F5,F5,F1), \
-    V(DF,BC,BC,63), V(C1,B6,B6,77), V(75,DA,DA,AF), V(63,21,21,42), \
-    V(30,10,10,20), V(1A,FF,FF,E5), V(0E,F3,F3,FD), V(6D,D2,D2,BF), \
-    V(4C,CD,CD,81), V(14,0C,0C,18), V(35,13,13,26), V(2F,EC,EC,C3), \
-    V(E1,5F,5F,BE), V(A2,97,97,35), V(CC,44,44,88), V(39,17,17,2E), \
-    V(57,C4,C4,93), V(F2,A7,A7,55), V(82,7E,7E,FC), V(47,3D,3D,7A), \
-    V(AC,64,64,C8), V(E7,5D,5D,BA), V(2B,19,19,32), V(95,73,73,E6), \
-    V(A0,60,60,C0), V(98,81,81,19), V(D1,4F,4F,9E), V(7F,DC,DC,A3), \
-    V(66,22,22,44), V(7E,2A,2A,54), V(AB,90,90,3B), V(83,88,88,0B), \
-    V(CA,46,46,8C), V(29,EE,EE,C7), V(D3,B8,B8,6B), V(3C,14,14,28), \
-    V(79,DE,DE,A7), V(E2,5E,5E,BC), V(1D,0B,0B,16), V(76,DB,DB,AD), \
-    V(3B,E0,E0,DB), V(56,32,32,64), V(4E,3A,3A,74), V(1E,0A,0A,14), \
-    V(DB,49,49,92), V(0A,06,06,0C), V(6C,24,24,48), V(E4,5C,5C,B8), \
-    V(5D,C2,C2,9F), V(6E,D3,D3,BD), V(EF,AC,AC,43), V(A6,62,62,C4), \
-    V(A8,91,91,39), V(A4,95,95,31), V(37,E4,E4,D3), V(8B,79,79,F2), \
-    V(32,E7,E7,D5), V(43,C8,C8,8B), V(59,37,37,6E), V(B7,6D,6D,DA), \
-    V(8C,8D,8D,01), V(64,D5,D5,B1), V(D2,4E,4E,9C), V(E0,A9,A9,49), \
-    V(B4,6C,6C,D8), V(FA,56,56,AC), V(07,F4,F4,F3), V(25,EA,EA,CF), \
-    V(AF,65,65,CA), V(8E,7A,7A,F4), V(E9,AE,AE,47), V(18,08,08,10), \
-    V(D5,BA,BA,6F), V(88,78,78,F0), V(6F,25,25,4A), V(72,2E,2E,5C), \
-    V(24,1C,1C,38), V(F1,A6,A6,57), V(C7,B4,B4,73), V(51,C6,C6,97), \
-    V(23,E8,E8,CB), V(7C,DD,DD,A1), V(9C,74,74,E8), V(21,1F,1F,3E), \
-    V(DD,4B,4B,96), V(DC,BD,BD,61), V(86,8B,8B,0D), V(85,8A,8A,0F), \
-    V(90,70,70,E0), V(42,3E,3E,7C), V(C4,B5,B5,71), V(AA,66,66,CC), \
-    V(D8,48,48,90), V(05,03,03,06), V(01,F6,F6,F7), V(12,0E,0E,1C), \
-    V(A3,61,61,C2), V(5F,35,35,6A), V(F9,57,57,AE), V(D0,B9,B9,69), \
-    V(91,86,86,17), V(58,C1,C1,99), V(27,1D,1D,3A), V(B9,9E,9E,27), \
-    V(38,E1,E1,D9), V(13,F8,F8,EB), V(B3,98,98,2B), V(33,11,11,22), \
-    V(BB,69,69,D2), V(70,D9,D9,A9), V(89,8E,8E,07), V(A7,94,94,33), \
-    V(B6,9B,9B,2D), V(22,1E,1E,3C), V(92,87,87,15), V(20,E9,E9,C9), \
-    V(49,CE,CE,87), V(FF,55,55,AA), V(78,28,28,50), V(7A,DF,DF,A5), \
-    V(8F,8C,8C,03), V(F8,A1,A1,59), V(80,89,89,09), V(17,0D,0D,1A), \
-    V(DA,BF,BF,65), V(31,E6,E6,D7), V(C6,42,42,84), V(B8,68,68,D0), \
-    V(C3,41,41,82), V(B0,99,99,29), V(77,2D,2D,5A), V(11,0F,0F,1E), \
-    V(CB,B0,B0,7B), V(FC,54,54,A8), V(D6,BB,BB,6D), V(3A,16,16,2C)
-
-#define V(a,b,c,d) 0x##a##b##c##d
-const uint32_t FT0[256] __attribute__((section(".sys.0"))) = { FT };
-#undef V
-
-#define V(a,b,c,d) 0x##b##c##d##a
-const uint32_t FT1[256] __attribute__((section(".sys.1"))) = { FT };
-#undef V
-
-#define V(a,b,c,d) 0x##c##d##a##b
-const uint32_t FT2[256] __attribute__((section(".sys.2"))) = { FT };
-#undef V
-
-#ifdef ORIGINAL_IMPLEMENTATION 
-#define V(a,b,c,d) 0x##d##a##b##c
-const uint32_t FT3[256] = { FT };
-#undef V
-#endif
--- a/example-led/board.h
+++ b/example-led/board.h
@@ -0,0 +1 @@
+../board/board-stm32f0-discovery.h
--- a/example-led/sample.c
+++ b/example-led/sample.c
@@ -72,14 +72,14 @@ blk (void *arg)
 #define PRIO_BLK 2
 #endif

-extern uint8_t __process1_stack_base__, __process1_stack_size__;
-extern uint8_t __process2_stack_base__, __process2_stack_size__;
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];

-const uint32_t __stackaddr_pwm = (uint32_t)&__process1_stack_base__;
-const size_t __stacksize_pwm = (size_t)&__process1_stack_size__;
+#define STACK_ADDR_PWM ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_PWM ((uint32_t)__process1_stack_size__)

-const uint32_t __stackaddr_blk = (uint32_t)&__process2_stack_base__;
-const size_t __stacksize_blk = (size_t)&__process2_stack_size__;
+#define STACK_ADDR_BLK ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BLK ((uint32_t)__process2_stack_size__)


 int
@@ -94,8 +94,8 @@ main (int argc, const char *argv[])

  m = 10;

-  chopstx_create (PRIO_PWM, __stackaddr_pwm, __stacksize_pwm, pwm, NULL);
-  chopstx_create (PRIO_BLK, __stackaddr_blk, __stacksize_blk, blk, NULL);
+  chopstx_create (PRIO_PWM, STACK_ADDR_PWM, STACK_SIZE_PWM, pwm, NULL);
+  chopstx_create (PRIO_BLK, STACK_ADDR_BLK, STACK_SIZE_BLK, blk, NULL);

  chopstx_usec_wait (200*1000);

--- a/example-led/sample.ld
+++ b/example-led/sample.ld
@@ -1,7 +1,7 @@
 /*
- * ST32F103 memory setup.
+ * ST32F0 memory setup.
 */
-__main_stack_size__     = 0x0100;  /* Exception handlers     */
+__main_stack_size__      = 0x0100; /* Idle+Exception handlers */
 __process0_stack_size__  = 0x0100; /* Main program            */
 __process1_stack_size__  = 0x0100; /* first thread program    */
 __process2_stack_size__  = 0x0100; /* second thread program   */
@@ -14,9 +14,6 @@ MEMORY
    ram : org = 0x20000000, len = 20k
 }

-__flash_start__ = 0x08001000;
-__flash_end__   = 0x08020000;
-
 __ram_start__           = ORIGIN(ram);
 __ram_size__            = 20k;
 __ram_end__             = __ram_start__ + __ram_size__;
@@ -25,21 +22,25 @@ SECTIONS
 {
    . = 0;

-    .sys : ALIGN(16) SUBALIGN(16)
+    .sys : ALIGN(4) SUBALIGN(4)
    {
 	_sys = .;
 	KEEP(*(.vectors))
 	. = ALIGN(16);
-	*(.sys.version)
-	build/sys.o(.text)
-	build/sys.o(.text.*)
-        build/sys.o(.rodata)
-	build/sys.o(.rodata.*)
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
 	. = ALIGN(1024);
+/*
 	*(.sys.0)
 	*(.sys.1)
 	*(.sys.2)
-    } > flash0
+*/
+    } > flash0 =0xffffffff

    _text = .;

@@ -59,6 +60,7 @@ SECTIONS
        *(.glue_7t)
        *(.glue_7)
        *(.gcc*)
+	. = ALIGN(8);
    } > flash

    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
@@ -78,21 +80,28 @@ SECTIONS
    _etext = .;
    _textdata = _etext;

+    .vectors_in_ram :
+    {
+        . = ALIGN(8);
+        __vector_ram_addr__ = .;
+	KEEP(*(.bss.startup.*))
+    } > ram
+
    .process_stack :
    {
        . = ALIGN(8);
        __process3_stack_base__ = .;
        . += __process3_stack_size__;
        . = ALIGN(8);
-        __process_stack3_end__ = .;
+        __process3_stack_end__ = .;
        __process2_stack_base__ = .;
        . += __process2_stack_size__;
        . = ALIGN(8);
-        __process_stack2_end__ = .;
+        __process2_stack_end__ = .;
        __process1_stack_base__ = .;
        . += __process1_stack_size__;
        . = ALIGN(8);
-        __process_stack1_end__ = .;
+        __process1_stack_end__ = .;
        __process0_stack_base__ = .;
        . += __process0_stack_size__;
        . = ALIGN(8);
--- a/example-led/sample.ld.m3
+++ b/example-led/sample.ld.m3
@@ -0,0 +1,142 @@
+/*
+ * ST32F103 memory setup.
+ */
+__main_stack_size__      = 0x0100; /* Idle+Exception handlers */
+__process0_stack_size__  = 0x0100; /* Main program            */
+__process1_stack_size__  = 0x0100; /* first thread program    */
+__process2_stack_size__  = 0x0100; /* second thread program   */
+__process3_stack_size__  = 0x0100; /* third thread program    */
+
+MEMORY
+{
+    flash0 : org = 0x08000000, len = 4k
+    flash  : org = 0x08000000+0x1000, len = 60k
+    ram : org = 0x20000000, len = 20k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    .sys : ALIGN(4) SUBALIGN(4)
+    {
+	_sys = .;
+	KEEP(*(.vectors))
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+	*(.sys.0)
+	*(.sys.1)
+	*(.sys.2)
+    } > flash0
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN (16);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .process_stack :
+    {
+        . = ALIGN(8);
+        __process3_stack_base__ = .;
+        . += __process3_stack_size__;
+        . = ALIGN(8);
+        __process3_stack_end__ = .;
+        __process2_stack_base__ = .;
+        . += __process2_stack_size__;
+        . = ALIGN(8);
+        __process2_stack_end__ = .;
+        __process1_stack_base__ = .;
+        . += __process1_stack_size__;
+        . = ALIGN(8);
+        __process1_stack_end__ = .;
+        __process0_stack_base__ = .;
+        . += __process0_stack_size__;
+        . = ALIGN(8);
+        __process0_stack_end__ = .;
+    } > ram
+
+    .main_stack :
+    {
+        . = ALIGN(8);
+        __main_stack_base__ = .;
+        . += __main_stack_size__;
+        . = ALIGN(8);
+        __main_stack_end__ = .;
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;
--- a/example-led/sys.c
+++ b/example-led/sys.c
@@ -1,599 +0,0 @@
-/*
- * sys.c - system routines for the initial page for STM32F103.
- *
- * Copyright (C) 2013 Flying Stone Technology
- * Author: NIIBE Yutaka <gniibe@fsij.org>
- *
- * Copying and distribution of this file, with or without modification,
- * are permitted in any medium without royalty provided the copyright
- * notice and this notice are preserved.  This file is offered as-is,
- * without any warranty.
- *
- * When the flash ROM is protected, we cannot modify the initial page.
- * We put some system routines (which is useful for any program) here.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include "board.h"
-
-
-#define CORTEX_PRIORITY_BITS    4
-#define CORTEX_PRIORITY_MASK(n)  ((n) << (8 - CORTEX_PRIORITY_BITS))
-#define USB_LP_CAN1_RX0_IRQn	 20
-#define STM32_USB_IRQ_PRIORITY   11
-
-
-#define STM32_SW_PLL		(2 << 0)
-#define STM32_PLLSRC_HSE	(1 << 16)
-
-#define STM32_PLLXTPRE_DIV1	(0 << 17)
-#define STM32_PLLXTPRE_DIV2	(1 << 17)
-
-#define STM32_HPRE_DIV1		(0 << 4)
-
-#define STM32_PPRE1_DIV2	(4 << 8)
-
-#define STM32_PPRE2_DIV1        (0 << 11)
-#define STM32_PPRE2_DIV2	(4 << 11)
-
-#define STM32_ADCPRE_DIV4	(1 << 14)
-#define STM32_ADCPRE_DIV6       (2 << 14)
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)
-
-#define STM32_MCO_NOCLOCK	(0 << 24)
-
-#define STM32_SW		STM32_SW_PLL
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_HPRE		STM32_HPRE_DIV1
-#define STM32_PPRE1		STM32_PPRE1_DIV2
-#define STM32_PPRE2		STM32_PPRE2_DIV1
-#define STM32_ADCPRE		STM32_ADCPRE_DIV6
-#define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
-
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
-#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK		STM32_PLLCLKOUT
-#define STM32_HCLK		(STM32_SYSCLK / 1)
-
-#define STM32_FLASHBITS		0x00000012
-
-struct NVIC {
-  uint32_t ISER[8];
-  uint32_t unused1[24];
-  uint32_t ICER[8];
-  uint32_t unused2[24];
-  uint32_t ISPR[8];
-  uint32_t unused3[24];
-  uint32_t ICPR[8];
-  uint32_t unused4[24];
-  uint32_t IABR[8];
-  uint32_t unused5[56];
-  uint32_t IPR[60];
-};
-
-static struct NVIC *const NVICBase = ((struct NVIC *const)0xE000E100);
-#define NVIC_ISER(n)	(NVICBase->ISER[n >> 5])
-#define NVIC_ICPR(n)	(NVICBase->ICPR[n >> 5])
-#define NVIC_IPR(n)	(NVICBase->IPR[n >> 2])
-
-static void
-nvic_enable_vector (uint32_t n, uint32_t prio)
-{
-  unsigned int sh = (n & 3) << 3;
-
-  NVIC_IPR (n) = (NVIC_IPR(n) & ~(0xFF << sh)) | (prio << sh);
-  NVIC_ICPR (n) = 1 << (n & 0x1F);
-  NVIC_ISER (n) = 1 << (n & 0x1F);
-}
-
-
-#define PERIPH_BASE	0x40000000
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN	0x00800000
-#define RCC_APB1RSTR_USBRST	0x00800000
-
-#define RCC_CR_HSION		0x00000001
-#define RCC_CR_HSIRDY		0x00000002
-#define RCC_CR_HSITRIM		0x000000F8
-#define RCC_CR_HSEON		0x00010000
-#define RCC_CR_HSERDY		0x00020000
-#define RCC_CR_PLLON		0x01000000
-#define RCC_CR_PLLRDY		0x02000000
-
-#define RCC_CFGR_SWS		0x0000000C
-#define RCC_CFGR_SWS_HSI	0x00000000
-
-#define RCC_AHBENR_CRCEN        0x0040
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void
-clock_init (void)
-{
-  /* HSI setup */
-  RCC->CR |= RCC_CR_HSION;
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
-  RCC->CFGR = 0;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;
-
-  /* HSE setup */
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;
-
-  /* PLL setup */
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-
-  /* Clock settings */
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
-    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /* Flash setup */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* CRC */
-  RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
-  /* Switching on the configured clock source. */
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-}
-
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-
-static void
-gpio_init (void)
-{
-  /* Enable GPIO clock. */
-  RCC->APB2ENR |= RCC_APB2ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
-  RCC->APB2RSTR = 0;
-
-  GPIO_USB->ODR = VAL_GPIO_ODR;
-  GPIO_USB->CRH = VAL_GPIO_CRH;
-  GPIO_USB->CRL = VAL_GPIO_CRL;
-
-#if GPIO_USB_BASE != GPIO_LED_BASE
-  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
-  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
-  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-#endif
-}
-
-static void
-usb_cable_config (int enable)
-{
-#if defined(GPIO_USB_SET_TO_ENABLE)
-  if (enable)
-    GPIO_USB->BSRR = (1 << GPIO_USB_SET_TO_ENABLE);
-  else
-    GPIO_USB->BRR = (1 << GPIO_USB_SET_TO_ENABLE);
-#elif defined(GPIO_USB_CLEAR_TO_ENABLE)
-  if (enable)
-    GPIO_USB->BRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
-  else
-    GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
-#else
-  (void)enable;
-#endif
-}
-
-void
-set_led (int on)
-{
-#if defined(GPIO_LED_CLEAR_TO_EMIT)
-  if (on)
-    GPIO_LED->BRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
-  else
-    GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
-#else
-  if (on)
-    GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT);
-  else
-    GPIO_LED->BRR = (1 << GPIO_LED_SET_TO_EMIT);
-#endif
-}
-
-static void wait (int count)
-{
-  int i;
-
-  for (i = 0; i < count; i++)
-    asm volatile ("" : : "r" (i) : "memory");
-}
-
-#define USB_IRQ 20
-#define USB_IRQ_PRIORITY ((11) << 4)
-
-static void
-usb_lld_sys_shutdown (void)
-{
-  RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
-  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
-  usb_cable_config (0);
-}
-
-static void
-usb_lld_sys_init (void)
-{
-  if ((RCC->APB1ENR & RCC_APB1ENR_USBEN)
-      && (RCC->APB1RSTR & RCC_APB1RSTR_USBRST) == 0)
-    /* Make sure the device is disconnected, even after core reset.  */
-    {
-      usb_lld_sys_shutdown ();
-      /* Disconnect requires SE0 (>= 2.5uS).  */
-      wait (300);
-    }
-
-  usb_cable_config (1);
-  RCC->APB1ENR |= RCC_APB1ENR_USBEN;
-  nvic_enable_vector (USB_LP_CAN1_RX0_IRQn,
-		      CORTEX_PRIORITY_MASK (STM32_USB_IRQ_PRIORITY));
-  /*
-   * Note that we also have other IRQ(s):
-   * 	USB_HP_CAN1_TX_IRQn (for double-buffered or isochronous)
-   * 	USBWakeUp_IRQn (suspend/resume)
-   */
-  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
-  RCC->APB1RSTR = 0;
-}
-
-#define FLASH_KEY1               0x45670123UL
-#define FLASH_KEY2               0xCDEF89ABUL
-
-enum flash_status
-{
-  FLASH_BUSY = 1,
-  FLASH_ERROR_PG,
-  FLASH_ERROR_WRP,
-  FLASH_COMPLETE,
-  FLASH_TIMEOUT
-};
-
-static void __attribute__ ((used))
-flash_unlock (void)
-{
-  FLASH->KEYR = FLASH_KEY1;
-  FLASH->KEYR = FLASH_KEY2;
-}
-
-
-#define intr_disable()  asm volatile ("cpsid   i" : : : "memory")
-#define intr_enable()  asm volatile ("cpsie   i" : : : "memory")
-
-#define FLASH_SR_BSY		0x01
-#define FLASH_SR_PGERR		0x04
-#define FLASH_SR_WRPRTERR	0x10
-#define FLASH_SR_EOP		0x20
-
-#define FLASH_CR_PG	0x0001
-#define FLASH_CR_PER	0x0002
-#define FLASH_CR_MER	0x0004
-#define FLASH_CR_OPTPG	0x0010
-#define FLASH_CR_OPTER	0x0020
-#define FLASH_CR_STRT	0x0040
-#define FLASH_CR_LOCK	0x0080
-#define FLASH_CR_OPTWRE	0x0200
-#define FLASH_CR_ERRIE	0x0400
-#define FLASH_CR_EOPIE	0x1000
-
-static int
-flash_wait_for_last_operation (uint32_t timeout)
-{
-  int status;
-
-  do
-    {
-      status = FLASH->SR;
-      if (--timeout == 0)
-	break;
-    }
-  while ((status & FLASH_SR_BSY) != 0);
-
-  return status & (FLASH_SR_BSY|FLASH_SR_PGERR|FLASH_SR_WRPRTERR);
-}
-
-#define FLASH_PROGRAM_TIMEOUT 0x00010000
-#define FLASH_ERASE_TIMEOUT   0x01000000
-
-static int
-flash_program_halfword (uint32_t addr, uint16_t data)
-{
-  int status;
-
-  status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
-
-  intr_disable ();
-  if (status == 0)
-    {
-      FLASH->CR |= FLASH_CR_PG;
-
-      *(volatile uint16_t *)addr = data;
-
-      status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
-      FLASH->CR &= ~FLASH_CR_PG;
-    }
-  intr_enable ();
-
-  return status;
-}
-
-static int
-flash_erase_page (uint32_t addr)
-{
-  int status;
-
-  status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
-
-  intr_disable ();
-  if (status == 0)
-    {
-      FLASH->CR |= FLASH_CR_PER;
-      FLASH->AR = addr;
-      FLASH->CR |= FLASH_CR_STRT;
-
-      status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
-      FLASH->CR &= ~FLASH_CR_PER;
-    }
-  intr_enable ();
-
-  return status;
-}
-
-static int
-flash_check_blank (const uint8_t *p_start, size_t size)
-{
-  const uint8_t *p;
-
-  for (p = p_start; p < p_start + size; p++)
-    if (*p != 0xff)
-      return 0;
-
-  return 1;
-}
-
-extern uint8_t __flash_start__, __flash_end__;
-
-static int
-flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
-{
-  int status;
-  uint32_t flash_start = (uint32_t)&__flash_start__;
-  uint32_t flash_end = (uint32_t)&__flash_end__;
-
-  if (dst_addr < flash_start || dst_addr + len > flash_end)
-    return 0;
-
-  while (len)
-    {
-      uint16_t hw = *src++;
-
-      hw |= (*src++ << 8);
-      status = flash_program_halfword (dst_addr, hw);
-      if (status != 0)
-	return 0;		/* error return */
-
-      dst_addr += 2;
-      len -= 2;
-    }
-
-  return 1;
-}
-
-#define OPTION_BYTES_ADDR 0x1ffff800
-
-static int
-flash_protect (void)
-{
-  int status;
-  uint32_t option_bytes_value;
-
-  status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
-
-  intr_disable ();
-  if (status == 0)
-    {
-      FLASH->OPTKEYR = FLASH_KEY1;
-      FLASH->OPTKEYR = FLASH_KEY2;
-
-      FLASH->CR |= FLASH_CR_OPTER;
-      FLASH->CR |= FLASH_CR_STRT;
-
-      status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
-      FLASH->CR &= ~FLASH_CR_OPTER;
-    }
-  intr_enable ();
-
-  if (status != 0)
-    return 0;
-
-  option_bytes_value = *(uint32_t *)OPTION_BYTES_ADDR;
-  return (option_bytes_value & 0xff) == 0xff ? 1 : 0;
-}
-
-static void __attribute__((naked))
-flash_erase_all_and_exec (void (*entry)(void))
-{
-  uint32_t addr = (uint32_t)&__flash_start__;
-  uint32_t end = (uint32_t)&__flash_end__;
-  int r;
-
-  while (addr < end)
-    {
-      r = flash_erase_page (addr);
-      if (r != 0)
-	break;
-
-      addr += FLASH_PAGE_SIZE;
-    }
-
-  if (addr >= end)
-    (*entry) ();
-
-  for (;;);
-}
-
-struct SCB
-{
-  volatile uint32_t CPUID;
-  volatile uint32_t ICSR;
-  volatile uint32_t VTOR;
-  volatile uint32_t AIRCR;
-  volatile uint32_t SCR;
-  volatile uint32_t CCR;
-  volatile uint8_t  SHP[12];
-  volatile uint32_t SHCSR;
-  volatile uint32_t CFSR;
-  volatile uint32_t HFSR;
-  volatile uint32_t DFSR;
-  volatile uint32_t MMFAR;
-  volatile uint32_t BFAR;
-  volatile uint32_t AFSR;
-  volatile uint32_t PFR[2];
-  volatile uint32_t DFR;
-  volatile uint32_t ADR;
-  volatile uint32_t MMFR[4];
-  volatile uint32_t ISAR[5];
-};
-
-#define SCS_BASE	(0xE000E000)
-#define SCB_BASE	(SCS_BASE +  0x0D00)
-static struct SCB *const SCB = ((struct SCB *const) SCB_BASE);
-
-#define SYSRESETREQ 0x04
-static void
-nvic_system_reset (void)
-{
-  SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
-  asm volatile ("dsb");
-  for (;;);
-}
-
-static void __attribute__ ((naked))
-reset (void)
-{
-  extern const unsigned long *FT0, *FT1, *FT2;
-
-  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
-		"mov.w	r0, #0xed00\n\t" /* r0 = SCR */
-		"movt	r0, #0xe000\n\t"
-		"mov	r1, pc\n\t"	 /* r1 = (PC + 0x1000) & ~0x0fff */
-		"mov	r2, #0x1000\n\t"
-		"add	r1, r1, r2\n\t"
-		"sub	r2, r2, #1\n\t"
-		"bic	r1, r1, r2\n\t"
-		"str	r1, [r0, #8]\n\t"	/* Set SCR->VCR */
-		"ldr	r0, [r1], #4\n\t"
-		"msr	MSP, r0\n\t"	/* Main (exception handler) stack. */
-		"ldr	r0, [r1]\n\t"	/* Reset handler.                  */
-		"bx	r0\n"
-		: /* no output */ : /* no input */ : "memory");
-
-  /* Never reach here. */
-  /* Artificial entry to refer FT0, FT1, and FT2.  */
-  asm volatile (""
-		: : "r" (FT0), "r" (FT1), "r" (FT2));
-}
-
-typedef void (*handler)(void);
-extern uint8_t __ram_end__;
-
-handler vector[] __attribute__ ((section(".vectors"))) = {
-  (handler)&__ram_end__,
-  reset,
-  (handler)set_led,
-  flash_unlock,
-  (handler)flash_program_halfword,
-  (handler)flash_erase_page,
-  (handler)flash_check_blank,
-  (handler)flash_write,
-  (handler)flash_protect,
-  (handler)flash_erase_all_and_exec,
-  usb_lld_sys_init,
-  usb_lld_sys_shutdown,
-  nvic_system_reset,
-  clock_init,
-  gpio_init,
-  NULL,
-};
-
-const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
-  3*2+2,	     /* bLength */
-  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
-  /* sys version: "2.0" */
-  '2', 0, '.', 0, '0', 0,
-};
--- a/example-primer2/Makefile
+++ b/example-primer2/Makefile
@@ -0,0 +1,45 @@
+# Makefile for example application of Chopstx
+
+PROJECT = lcd
+
+CHOPSTX = ..
+NEUGSRC = ./neug/src
+LDSCRIPT= lcd.ld
+CSRC = primer2-switches.c primer2-ts.c lcd.c main.c \
+       neug.c sha256.c
+
+CHIP=stm32f103
+USE_SYS = yes
+USE_USB = yes
+USE_ADC = yes
+
+###################################
+CROSS = arm-none-eabi-
+CC   = $(CROSS)gcc
+LD   = $(CROSS)gcc
+OBJCOPY   = $(CROSS)objcopy
+MCU   = cortex-m3
+CWARN = -Wall -Wextra -Wstrict-prototypes
+DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=48
+# DEFS  = -DFREE_STANDING -DUSE_SYS3 -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
+OPT   = -O3 -Os -g
+INCDIR = $(NEUGSRC)
+LIBS  =
+
+####################
+include ../rules.mk
+
+board.h: ../board/board-stm32-primer2.h neug
+	ln -s ../board/board-stm32-primer2.h ./board.h
+
+sys.c: board.h
+
+neug:
+	@echo Please make a symbolic link \'neug\' to the neug directory;
+	@exit 1
+
+adc_stm32f103.c neug.c sha256.c:
+	ln -s $(NEUGSRC)/$@ $@
+
+distclean: clean
+	rm -f board.h neug adc_stm32f103.c neug.c sha256.c
--- a/example-primer2/README
+++ b/example-primer2/README
@@ -0,0 +1,18 @@
+Example for STM32 Primer2 by Kazmoto Kojima
+
+It is taken from:
+
+   http://www.rr.iij4u.or.jp/~kkojima/letschopstx.html
+
+From the original tar archive, chopstx-logo.data is removed because
+it's too big.
+
+You can generate it by ImageMagick.
+
+  $ convert ../chopstx.svg -depth 8 -flip \( +clone -channel B -fx R \) +swap -channel R -fx v.B -resize 128x160 -background white -compress none -flatten chopstx.ppm
+
+  $ tail -n +4 chopstx.ppm | sed -e 's/ /, /g' > chopstx-logo.data
+
+
+Since it was written for Chopstx 0.06, you would need to change a bit,
+perhaps.
--- a/example-primer2/lcd.c
+++ b/example-primer2/lcd.c
@@ -0,0 +1,388 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include "sys.h" /* for set_led */
+#include "st7732.h"
+#include "board.h"
+
+#define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+
+struct GPIO {
+  volatile uint32_t CRL;
+  volatile uint32_t CRH;
+  volatile uint32_t IDR;
+  volatile uint32_t ODR;
+  volatile uint32_t BSRR;
+  volatile uint32_t BRR;
+  volatile uint32_t LCKR;
+};
+
+#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
+#define GPIOE		((struct GPIO *) GPIOE_BASE)
+
+static struct GPIO *const GPIO_LCD = ((struct GPIO *const) GPIO_LED_BASE);
+static struct GPIO *const GPIO_LCD_CTRL = ((struct GPIO *const) GPIO_USB_BASE);
+
+#define GPIO_LCD_RD	4
+#define GPIO_LCD_WR	5
+#define GPIO_LCD_RST	6
+#define GPIO_LCD_CS	7
+#define GPIO_LCD_RS	11
+/* PE7:LCD_D0 - PE14:LCD_D7 */
+#define GPIO_DATA_SHIFT	7
+#define GPIO_DATA_MASK (0xff << GPIO_DATA_SHIFT)
+
+static void
+lcd_command_common (st7732_cmd_t cmd)
+{
+  /* Set command. */
+  GPIO_LCD->BRR = GPIO_DATA_MASK & ~(cmd << GPIO_DATA_SHIFT);
+  GPIO_LCD->BSRR = GPIO_DATA_MASK & (cmd << GPIO_DATA_SHIFT);
+  /* Set CMD mode.  */
+  GPIO_LCD_CTRL->BRR = (1 << GPIO_LCD_RS);
+  /* Asert /CS.  */
+  GPIO_LCD_CTRL->BRR = (1<< GPIO_LCD_CS);
+  /* Asert /WR.  */
+  GPIO_LCD_CTRL->BRR = (1<< GPIO_LCD_WR);
+  // chopstx_usec_wait (1);
+  /* Negate /WR.  */
+  GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_WR);
+
+  /* Return DATA mode.  */
+  GPIO_LCD_CTRL->BSRR = (1 << GPIO_LCD_RS);
+}
+
+/* Issue command with no data read/write.  */
+void
+lcd_command_no (st7732_cmd_t cmd)
+{
+  lcd_command_common (cmd);
+
+  /* Negate /CS.  */
+  GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_CS);
+}
+
+#if 0
+void
+lcd_command_readn (st7732_cmd_t cmd, uint8_t *data, size_t n)
+{
+  volatile int dummy __attribute__ ((unused));
+
+  lcd_command_common (cmd);
+
+  /* Set GPIO_LCD to input mode.  */
+  GPIO_LCD->CRH = 0x88888888;
+  GPIO_LCD->CRL = 0x88888833;
+
+  /* Assert /RD.  */
+  GPIO_LCD_CTRL->BRR = (1<< GPIO_LCD_RD);
+  // chopstx_usec_wait (1);
+  /* Dummy read.  */
+  dummy = GPIO_LCD->IDR;
+  /* Negate /RD.  */
+  GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_RD);
+
+  /* Read loop.  */
+  while (n-- > 0)
+    {
+      /* Assert /RD.  */
+      GPIO_LCD_CTRL->BRR = (1<< GPIO_LCD_RD);
+      // chopstx_usec_wait (1);
+      /* Negate /RD.  */
+      GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_RD);
+      *data++ = GPIO_LCD->IDR >> GPIO_DATA_SHIFT;
+    }
+	  
+  /* Negate /CS.  */
+  GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_CS);
+
+  /* Set GPIO_LCD to output mode.  */
+  GPIO_LCD->CRH = 0x83333333;
+  GPIO_LCD->CRL = 0x38888833;
+}
+#endif
+
+/* Issue command with N data write.  */
+void
+lcd_command_writen (st7732_cmd_t cmd, uint8_t *data, size_t n)
+{
+  lcd_command_common (cmd);
+
+  /* Write loop.  */
+  while (n-- > 0)
+    {
+      uint8_t b = *data++;
+
+      GPIO_LCD->BRR = GPIO_DATA_MASK & ~(b << GPIO_DATA_SHIFT);
+      GPIO_LCD->BSRR = GPIO_DATA_MASK & (b << GPIO_DATA_SHIFT);
+      /* Assert /WR.  */
+      GPIO_LCD_CTRL->BRR = (1<< GPIO_LCD_WR);
+      // chopstx_usec_wait (1);
+      /* Negate /WR.  */
+      GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_WR);
+    }
+
+  /* Negate /CS.  */
+  GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_CS);
+}
+
+/* Issue command with N same data write.  */
+void
+lcd_command_filln (st7732_cmd_t cmd, uint8_t b, size_t n)
+{
+  lcd_command_common (cmd);
+
+  /* Write loop.  */
+  while (n-- > 0)
+    {
+      GPIO_LCD->BRR = GPIO_DATA_MASK & ~(b << GPIO_DATA_SHIFT);
+      GPIO_LCD->BSRR = GPIO_DATA_MASK & (b << GPIO_DATA_SHIFT);
+      /* Assert /WR.  */
+      GPIO_LCD_CTRL->BRR = (1<< GPIO_LCD_WR);
+      // chopstx_usec_wait (1);
+      /* Negate /WR.  */
+      GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_WR);
+    }
+
+  /* Negate /CS.  */
+  GPIO_LCD_CTRL->BSRR = (1<< GPIO_LCD_CS);
+}
+
+static chopstx_mutex_t lcd_mtx;
+static chopstx_cond_t lcd_cnd0;
+static chopstx_cond_t lcd_cnd1;
+
+/* Process for initializing ST7732.  */
+static void *
+lcd_initializer (void *arg __attribute__((unused)))
+{
+  uint8_t args[16];
+
+  chopstx_mutex_lock (&lcd_mtx);
+  chopstx_cond_wait (&lcd_cnd0, &lcd_mtx);
+  chopstx_mutex_unlock (&lcd_mtx);
+
+ /* Set GPIO_LCD to write mode.  */
+  GPIO_LCD->CRH = 0x83333333;
+  GPIO_LCD->CRL = 0x38888833;
+
+  /* Set GPIO_LCD_CTRL IO mode.  */
+  GPIO_LCD_CTRL->CRH = 0x88883888;
+  GPIO_LCD_CTRL->CRL = 0x33333888;
+
+  /* Restart ST7732.  */
+  /* Hard reset.  */
+  chopstx_usec_wait (100000);
+  GPIO_LCD_CTRL->BRR = (1 << GPIO_LCD_RST);
+  chopstx_usec_wait (100000);
+  GPIO_LCD_CTRL->BSRR = (1 << GPIO_LCD_RST);
+  chopstx_usec_wait (100000);
+
+  /* Software reset.  */
+  lcd_command_no (SWRESET);
+  chopstx_usec_wait (150000);
+
+  /* Sleep in.  */
+  lcd_command_no (SLPIN);
+  chopstx_usec_wait (100000);
+
+  /* Sleep out.  */
+  lcd_command_no (SLPOUT);
+  chopstx_usec_wait (100000);
+
+  /* Configure ST7732.  Set display mode, pixel mode, etc.  */
+  /* FRMCTR1, 6, 3, 2  */
+  args[0] = 0x06; args[1] = 0x03; args[2] = 0x02;
+  lcd_command_writen (FRMCTR1, args, 3);
+  /* INVCTR, 3  */
+  args[0] = 0x03;
+  lcd_command_writen (INVCTR, args, 1);
+  /* DISSET5, 2, eh  */
+  args[0] = 0x02; args[1] = 0x0e;
+  lcd_command_writen (DISSET5, args, 2);
+  /* DISPCTRL, 1ah  */
+  args[0] = 0x1a;
+  lcd_command_writen (DISPCTRL, args, 1);
+  /* PWCTR1, 2, 0  */
+  args[0] = 0x02; args[1] = 0x00;
+  lcd_command_writen (PWCTR1, args, 2);
+  /* PWCTR2, 5  */
+  args[0] = 0x05;
+  lcd_command_writen (PWCTR2, args, 1);
+  /* PWCTR3, 2, 2  */
+  args[0] = 0x02; args[1] = 0x02;
+  lcd_command_writen (PWCTR3, args, 2);
+  /* PWCTR4, 1, 2  */
+  args[0] = 0x01; args[1] = 0x00;
+  lcd_command_writen (PWCTR4, args, 2);
+  /* PWCTR5, 1, 2  */
+  args[0] = 0x01; args[1] = 0x00;
+  lcd_command_writen (PWCTR5, args, 2);
+  /* VMCTR1, 47h, 2ah  */
+  args[0] = 0x47; args[1] = 0x2a;
+  lcd_command_writen (VMCTR1, args, 2);
+  /* OSCADJ, 4ch  */
+  args[0] = 0x4c;
+  lcd_command_writen (OSCADJ, args, 1);
+  /* DEFADJ, 6  */
+  args[0] = 0x06;
+  lcd_command_writen (DEFADJ, args, 1);
+
+  /* gamma adjust  */
+
+  /* MADCTL, c0h  MY=1, MX=1  */
+  args[0] = 0xc0;
+  lcd_command_writen (MADCTL, args, 1);
+
+  /* Set RA and CA.  */
+  /* RASET, 0, 0, 0, 159  */
+  args[0] = 0x00; args[1] = 0x00; args[2] = 0x00; args[3] = LCD_ROW-1;
+  lcd_command_writen (RASET, args, 4);
+  /* CASET, 0, 0, 0, 127  */
+  args[0] = 0x00; args[1] = 0x00; args[2] = 0x00; args[3] = LCD_COLUMN-1;
+  lcd_command_writen (CASET, args, 4);
+
+  /* 0x06: RGB 6-6-6-bit.  */
+  args[0] = 0x06;
+  lcd_command_writen (COLMOD, args, 1);
+
+  args[0] = 0;
+  lcd_command_writen (TEON, args, 1);
+
+  lcd_command_no (DISPON);
+
+  /* Wait 20ms.  */
+  chopstx_usec_wait (20000);
+
+  chopstx_mutex_lock (&lcd_mtx);
+  chopstx_cond_signal (&lcd_cnd1);
+  chopstx_mutex_unlock (&lcd_mtx);
+
+  return NULL;
+}
+
+/* Plot a point with rgb color.  2 LSBs of rgb values will be ignored.  */
+void
+lcd_draw_point (int x, int y, int r, int g, int b)
+{
+  uint8_t args[4];
+
+  /* Set RA and CA.  */
+  /* RASET, 0, y, 0, y  */
+  args[0] = 0x00; args[1] = y; args[2] = 0x00; args[3] = y;
+  lcd_command_writen (RASET, args, 4);
+  /* CASET, 0, x, 0, x  */
+  args[0] = 0x00; args[1] = x; args[2] = 0x00; args[3] = x;
+  lcd_command_writen (CASET, args, 4);
+
+  args[0] = r; args[1] = g; args[2] = b; 
+  lcd_command_writen (RAMWR, args, 3);
+}
+
+static uint8_t hexfont5x8[16*5] = {
+  0x7e, 0x89, 0x91, 0xa1, 0x7e, /* 0 */
+  0x00, 0x41, 0xff, 0x01, 0x00, /* 1 */
+  0x43, 0x85, 0x89, 0x91, 0x61, /* 2 */
+  0x42, 0x81, 0x91, 0x91, 0x6e, /* 3 */
+  0x18, 0x28, 0x48, 0xff, 0x08, /* 4 */
+  0xf2, 0x91, 0x91, 0x91, 0x8e, /* 5 */
+  0x1e, 0x29, 0x49, 0x89, 0x86, /* 6 */
+  0x80, 0x8f, 0x90, 0xa0, 0xc0, /* 7 */
+  0x6e, 0x91, 0x91, 0x91, 0x6e, /* 8 */
+  0x70, 0x89, 0x89, 0x8a, 0x7c, /* 9 */
+  0x7f, 0x88, 0x88, 0x88, 0x7f, /* A */
+  0xff, 0x91, 0x91, 0x91, 0x6e, /* B */
+  0x7e, 0x81, 0x81, 0x81, 0x42, /* C */
+  0xff, 0x81, 0x81, 0x42, 0x3c, /* D */
+  0xff, 0x91, 0x91, 0x91, 0x81, /* E */
+  0xff, 0x90, 0x90, 0x90, 0x80, /* F */
+};
+
+/* Draw hex number with rgb color.  */
+void
+lcd_draw_hexfont5x8 (uint32_t hex, int x, int y, int r, int g, int b, int bg)
+{
+  int i, j;
+  uint8_t *p;
+  uint8_t args[5*8*3];
+
+  p = &hexfont5x8[(hex & 0xf)*5];
+
+  /* Set RA and CA.  */
+  /* RASET, 0, y, 0, y+8-1  */
+  args[0] = 0x00; args[1] = y; args[2] = 0x00; args[3] = y+7;
+  lcd_command_writen (RASET, args, 4);
+  /* CASET, 0, x, 0, x+5-1  */
+  args[0] = 0x00; args[1] = x; args[2] = 0x00; args[3] = x+4;
+  lcd_command_writen (CASET, args, 4);
+
+  for (i = 0; i < 5; i++)
+    {
+      uint8_t rb = *p++;
+      for (j = 0; j < 8; j++)
+	{
+	  int k = (5*j+i)*3;
+	  if (rb & (0x80 >> j))
+	    {
+	      args[k] = r; args[k+1] = g; args[k+2] = b;
+	    }
+	  else
+	    {
+	      args[k] = bg; args[k+1] = bg; args[k+2] = bg;
+	    }
+	}
+    }
+
+  lcd_command_writen (RAMWR, args, 5*8*3);
+}
+
+void
+lcd_printhex (uint32_t hex, int x, int y, int r, int g, int b, int bg)
+{
+  int i;
+
+  if (y < 0 || y >= LCD_ROW - 8)
+    return;
+  for (i = 7; i >= 0; i--)
+    {
+      lcd_draw_hexfont5x8 ((hex >> 4*i)&0xf, x, y, r, g, b, bg);
+      x += 5;
+      if (x >= LCD_COLUMN - 5)
+	break;
+    }
+}
+
+#define PRIO_LCD 3
+
+extern uint8_t __process1_stack_base__, __process1_stack_size__;
+const uint32_t __stackaddr_lcd = (uint32_t)&__process1_stack_base__;
+const size_t __stacksize_lcd = (size_t)&__process1_stack_size__;
+
+/* Initialize LCD.  */
+void
+lcd_init (void)
+{
+  chopstx_mutex_init (&lcd_mtx);
+  chopstx_cond_init (&lcd_cnd0);
+  chopstx_cond_init (&lcd_cnd1);
+
+  chopstx_create (PRIO_LCD, __stackaddr_lcd, __stacksize_lcd,
+		  lcd_initializer, NULL);
+
+  chopstx_usec_wait (200*1000);
+
+  chopstx_mutex_lock (&lcd_mtx);
+  chopstx_cond_signal (&lcd_cnd0);
+  chopstx_cond_wait (&lcd_cnd1, &lcd_mtx);
+  chopstx_mutex_unlock (&lcd_mtx);
+}
--- a/example-primer2/lcd.ld
+++ b/example-primer2/lcd.ld
@@ -0,0 +1,148 @@
+/*
+ * ST32F103 memory setup.
+ */
+__main_stack_size__      = 0x0100;      /* Idle+Exception handlers */
+__process0_stack_size__  = 0x0200;      /* main */
+__process1_stack_size__  = 0x0100;      /* lcd init */
+__process2_stack_size__  = 0x0180;      /* rng */
+__process3_stack_size__  = 0x0100;      /* None yet */
+
+MEMORY
+{
+    flash0 : org = 0x08000000, len = 4k
+    flash : org = 0x08000000+0x1000, len = 512k - 4k
+    ram : org = 0x20000000, len = 64k
+}
+
+/* __flash_start__: flash ROM start address regardless of DFU_SUPPORT */
+__flash_start__         = 0x08001000;
+__flash_end__           = ORIGIN(flash) + LENGTH(flash);
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = LENGTH(ram);
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    .sys : ALIGN(4) SUBALIGN(4)
+    {
+        _sys = .;
+        KEEP(*(.vectors))
+        . = ALIGN(16);
+        *(.sys.version)
+        build/sys.o(.text)
+        build/sys.o(.text.*)
+        build/sys.o(.rodata)
+        build/sys.o(.rodata.*)
+        . = ALIGN(1024);
+        *(.sys.0)
+        *(.sys.1)
+        *(.sys.2)
+    } > flash0
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN (16);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .stacks :
+    {
+        . = ALIGN(8);
+        __main_stack_base__ = .;
+        . += __main_stack_size__;
+        . = ALIGN(8);
+        __main_stack_end__ = .;
+        __process0_stack_base__ = .;
+        . += __process0_stack_size__;
+        . = ALIGN(8);
+        __process0_stack_end__ = .;
+        __process1_stack_base__ = .;
+        . += __process1_stack_size__;
+        . = ALIGN(8);
+        __process1_stack_end__ = .;
+        __process2_stack_base__ = .;
+        . += __process2_stack_size__;
+        . = ALIGN(8);
+        __process2_stack_end__ = .;
+        __process3_stack_base__ = .;
+        . += __process3_stack_size__;
+        . = ALIGN(8);
+        __process3_stack_end__ = .;
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+    . = ALIGN(512);
+    /* reGNUal is now relocatable, it's OK not using fixed address. */
+    _regnual_start = .;
+
+    .fill_ffff :
+    {
+        . = ALIGN (2048);
+	*(.passwd)
+    } > flash =0xffffffff
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;
--- a/example-primer2/main.c
+++ b/example-primer2/main.c
@@ -0,0 +1,266 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include "neug.h"
+#include "sys.h" /* for set_led */
+#include "stm32f103.h"
+#include "adc.h"
+#include "st7732.h"
+#include "primer2-switches.h"
+#include "primer2-ts.h"
+#include "board.h"
+
+#ifdef TEST_DISPLAY_LOGO
+static uint8_t buf[LCD_COLUMN*LCD_ROW*BYTES_PER_PIXEL] = {
+#include "chopstx-logo.data"
+};
+
+void
+lcd_logo (void)
+{
+  uint8_t args[4];
+
+  /* Set RA and CA.  */
+  /* RASET, 0, 0, 0, 159  */
+  args[0] = 0x00; args[1] = 0; args[2] = 0x00; args[3] = LCD_ROW-1;
+  lcd_command_writen (RASET, args, 4);
+  /* CASET, 0, 0, 0, 127  */
+  args[0] = 0x00; args[1] = 0; args[2] = 0x00; args[3] = LCD_COLUMN-1;
+  lcd_command_writen (CASET, args, 4);
+
+  /* Write logo.  */
+  lcd_command_writen (RAMWR, buf, LCD_COLUMN*LCD_ROW*BYTES_PER_PIXEL);
+}
+#endif
+
+/* Table of 32*(cos, sin) for range 0 to pi/2 with step pi/256.  */
+static uint8_t ctable[128*2] = {
+32, 0, 31, 0, 31, 0, 31, 1, 31, 1, 31, 1, 31, 2, 31, 2,
+31, 3, 31, 3, 31, 3, 31, 4, 31, 4, 31, 5, 31, 5, 31, 5,
+31, 6, 31, 6, 31, 7, 31, 7, 31, 7, 30, 8, 30, 8, 30, 8,
+30, 9, 30, 9, 30, 10, 30, 10, 30, 10, 29, 11, 29, 11, 29, 11,
+29, 12, 29, 12, 29, 12, 29, 13, 28, 13, 28, 14, 28, 14, 28, 14,
+28, 15, 28, 15, 27, 15, 27, 16, 27, 16, 27, 16, 27, 17, 26, 17,
+26, 17, 26, 18, 26, 18, 25, 18, 25, 19, 25, 19, 25, 19, 24, 19,
+24, 20, 24, 20, 24, 20, 23, 21, 23, 21, 23, 21, 23, 22, 22, 22,
+22, 22, 22, 22, 22, 23, 21, 23, 21, 23, 21, 23, 20, 24, 20, 24,
+20, 24, 19, 24, 19, 25, 19, 25, 19, 25, 18, 25, 18, 26, 18, 26,
+17, 26, 17, 26, 17, 27, 16, 27, 16, 27, 16, 27, 15, 27, 15, 28,
+15, 28, 14, 28, 14, 28, 14, 28, 13, 28, 13, 29, 12, 29, 12, 29,
+12, 29, 11, 29, 11, 29, 11, 29, 10, 30, 10, 30, 10, 30, 9, 30,
+9, 30, 8, 30, 8, 30, 8, 30, 7, 31, 7, 31, 7, 31, 6, 31,
+6, 31, 5, 31, 5, 31, 5, 31, 4, 31, 4, 31, 3, 31, 3, 31,
+3, 31, 2, 31, 2, 31, 1, 31, 1, 31, 1, 31, 0, 31, 0, 31,
+};
+
+#ifdef TEST_LCD_CIRCLE
+void
+lcd_circle (void)
+{
+  int i, j;
+  uint8_t *p;
+  int x, y;
+
+  /* Clear display.  */
+  /* Set RA and CA.  */
+  /* RASET, 0, 0, 0, 159  */
+  args[0] = 0x00; args[1] = 0; args[2] = 0x00; args[3] = LCD_ROW-1;
+  lcd_command_writen (RASET, args, 4);
+  /* CASET, 0, 0, 0, 127  */
+  args[0] = 0x00; args[1] = 0; args[2] = 0x00; args[3] = LCD_COLUMN-1;
+  lcd_command_writen (CASET, args, 4);
+
+  lcd_command_writen (RAMWR, 0, LCD_COLUMN*LCD_ROW*BYTES_PER_PIXEL);
+
+  /* Draw a circle.  */
+  for (i = 0; i < 128; i++)
+    {
+      x = 64 + ctable[2*i];
+      y = 80 + ctable[2*i+1];
+      lcd_draw_point (x, y, 0xfc, 0xfc, 0xfc);
+    }
+  for (i = 0; i < 128; i++)
+    {
+      x = 64 - ctable[2*i+1];
+      y = 80 + ctable[2*i];
+      lcd_draw_point (x, y, 0xfc, 0, 0xfc);
+    }
+  for (i = 0; i < 128; i++)
+    {
+      x = 64 - ctable[2*i];
+      y = 80 - ctable[2*i+1];
+      lcd_draw_point (x, y, 0, 0xfc, 0xfc);
+    }
+  for (i = 0; i < 128; i++)
+    {
+      x = 64 + ctable[2*i+1];
+      y = 80 - ctable[2*i];
+      lcd_draw_point (x, y, 0xfc, 0xfc, 0);
+    }
+}
+#endif
+
+#define RANDOM_BYTES_LENGTH 64
+static uint32_t random_word[RANDOM_BYTES_LENGTH/sizeof (uint32_t)];
+
+int
+main (int argc, const char *argv[])
+{
+  int count;
+  int vx, vy;
+  int r, g, b;
+  uint8_t args[4];
+
+  (void)argc;
+  (void)argv;
+
+  set_led (1);
+  set_backlight (1);
+
+  adc_init ();
+  neug_init (random_word, RANDOM_BYTES_LENGTH/sizeof (uint32_t));
+
+  lcd_init ();
+
+#ifdef TEST_LCD_LOGO
+  lcd_logo ();
+
+  while (! joystick ())
+    chopstx_usec_wait (500*1000);
+#endif
+
+  /* Set RA and CA.  */
+  /* RASET, 0, 0, 0, 159  */
+  args[0] = 0x00; args[1] = 0; args[2] = 0x00; args[3] = LCD_ROW-1;
+  lcd_command_writen (RASET, args, 4);
+  /* CASET, 0, 0, 0, 127  */
+  args[0] = 0x00; args[1] = 0; args[2] = 0x00; args[3] = LCD_COLUMN-1;
+  lcd_command_writen (CASET, args, 4);
+
+  /* Fill display.  */
+  lcd_command_filln (RAMWR, 0xfc, LCD_COLUMN*LCD_ROW*BYTES_PER_PIXEL);
+
+  vx = (LCD_COLUMN/2) << 5;
+  vy = (LCD_ROW/2) << 5;
+  r = g = b = 0;
+#if 1
+  adc3_init ();
+  adc3_start ();
+
+  count = 0;
+  while (1)
+    {
+      uint32_t resv[4];
+
+      adc3_conversion (resv);
+      if (ts_pushed (resv[2]))
+	{
+	  int reg[3], point[2];
+
+	  ts_conversion (resv, reg);
+#if 0
+	  lcd_printhex (reg[0], 5,  8, 0x00, 0x00, 0xfc, 0xfc);
+	  lcd_printhex (reg[1], 5,  18, 0x00, 0x00, 0xfc, 0xfc);
+	  lcd_printhex (reg[2], 5,  28, 0x00, 0x00, 0xfc, 0xfc);
+#endif
+	  if (!ts_adjust (reg, point))
+	    {
+	      chopstx_usec_wait (50*1000);
+	      continue;
+	    }
+
+	  lcd_draw_point (point[0], point[1], r, g, b);
+	}
+      else
+	ts_adjust (NULL, NULL);
+
+      chopstx_usec_wait (50*1000);
+      count++;
+      if ((count/10) & 1)
+	set_led (0);
+      else
+	set_led (1);
+      if (pbutton())
+	break;
+    }
+
+  adc3_stop ();
+#endif
+
+  count = 0;
+  while (1)
+    {
+      int jo;
+      uint32_t th = neug_get (NEUG_KICK_FILLING) & 0x1ff;
+
+      /* Get random point on a circle with the radius of 32 and walk
+	 towards it.  */
+      if (th < 128)
+	{
+	  vx += ctable[2*th];
+	  vy += ctable[2*th+1];
+	}
+      else if (th < 256)
+	{
+	  vx -= ctable[2*(th & 0x7f)+1];
+	  vy += ctable[2*(th & 0x7f)];
+	}
+      else if (th < 384)
+	{
+	  vx -= ctable[2*(th & 0x7f)];
+	  vy -= ctable[2*(th & 0x7f)+1];
+	}
+      else
+	{
+	  vx += ctable[2*(th & 0x7f)+1];
+	  vy -= ctable[2*(th & 0x7f)];
+	}
+
+      if (vx < 0)
+	vx += (LCD_COLUMN << 5);
+      if (vy < 0)
+	vy += (LCD_ROW << 5);
+
+      /* Change draw color with joystick.  */
+      jo = joystick ();
+      if (JOYSTICK_L (jo))
+	r = 0xfc;
+      if (JOYSTICK_R (jo))
+	g = 0xfc;
+      if (JOYSTICK_U (jo))
+	b = 0xfc;
+      if (JOYSTICK_D (jo))
+	r = g = b = 0;
+
+      /* 2-dim random walk on torus.  */
+      lcd_draw_point ((vx>>5)%LCD_COLUMN, (vy>>5)%LCD_ROW, r, g, b);
+      chopstx_usec_wait (10*1000);
+
+      if (pbutton ())
+	count++;
+      /* Shutdown when p-button is held down for 5 sec.  */
+      if (count > 500)
+	{
+	  set_led (0);
+	  shutdown ();
+	}
+      else
+	{
+	  /* Disable backlight when p-button is held down for 3 sec.  */
+	  if (count > 300)
+	    set_backlight (0);
+
+	  /* Blink led when p-button is held.  */
+	  if ((count/50) & 1)
+	    set_led (0);
+	  else
+	    set_led (1);
+	}
+#if 1
+      lcd_printhex (count, 5,  8, 0x00, 0x00, 0xfc, 0xfc);
+#endif
+
+    }
+
+  return 0;
+}
--- a/example-primer2/primer2-switches.c
+++ b/example-primer2/primer2-switches.c
@@ -0,0 +1,73 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include "board.h"
+
+#define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+
+struct GPIO {
+  volatile uint32_t CRL;
+  volatile uint32_t CRH;
+  volatile uint32_t IDR;
+  volatile uint32_t ODR;
+  volatile uint32_t BSRR;
+  volatile uint32_t BRR;
+  volatile uint32_t LCKR;
+};
+
+#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
+#define GPIOE		((struct GPIO *) GPIOE_BASE)
+
+static struct GPIO *const GPIO_STICK = ((struct GPIO *const) GPIO_LED_BASE);
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
+static struct GPIO *const GPIO_OTHER1 = ((struct GPIO *const) GPIOC_BASE);
+static struct GPIO *const GPIO_OTHER2 = ((struct GPIO *const) GPIOB_BASE);
+
+#define GPIO_STICK_L	3
+#define GPIO_STICK_R	4
+#define GPIO_STICK_U	5
+#define GPIO_STICK_D	6
+#define GPIO_SHUTDOWN	13
+#define GPIO_PBUTTON	8
+#define GPIO_BACKLIGHT	8
+
+void
+shutdown (void)
+{
+  GPIO_OTHER1->BRR = (1 << GPIO_SHUTDOWN);
+  GPIO_OTHER1->BSRR = (1 << GPIO_SHUTDOWN);
+
+  while (1)
+    chopstx_usec_wait (500*1000);
+}
+
+void
+set_backlight (int on)
+{
+  if (on)
+    GPIO_OTHER2->BSRR = (1 << GPIO_BACKLIGHT);
+  else
+    GPIO_OTHER2->BRR = (1 << GPIO_BACKLIGHT);
+}
+
+int
+joystick (void)
+{
+  return (GPIO_STICK->IDR >> GPIO_STICK_L) & 0xf;
+}
+
+int
+pbutton (void)
+{
+  return (GPIO_OTHER->IDR >> GPIO_PBUTTON) & 1;
+}
--- a/example-primer2/primer2-switches.h
+++ b/example-primer2/primer2-switches.h
@@ -0,0 +1,9 @@
+extern void shutdown (void);
+extern void set_backlight (int on);
+extern int pbutton (void);
+extern int joystick (void);
+
+#define JOYSTICK_L(x) ((x) & 1)
+#define JOYSTICK_R(x) ((x) & 2)
+#define JOYSTICK_U(x) ((x) & 4)
+#define JOYSTICK_D(x) ((x) & 8)
--- a/example-primer2/primer2-ts.c
+++ b/example-primer2/primer2-ts.c
@@ -0,0 +1,219 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include "stm32f103.h"
+#include "st7732.h"
+#include "primer2-ts.h"
+
+/* ADC3 routines.  */
+
+#define ADC3_BASE		(APB2PERIPH_BASE + 0x3c00)
+static struct ADC *const ADC3 = (struct ADC *const)ADC3_BASE;
+
+#define RCC_APB2ENR_ADC3EN	0x8000
+#define RCC_APB2RSTR_ADC3RST	0x8000
+
+#define ADC_SR_JEOC		0x0004
+
+#define ADC_CR1_JEOCIE		(1 << 7)
+
+#define ADC_CR2_JSWSTART	(1 << 21)
+#define ADC_CR2_JEXTTRIG        (1 << 15)
+#define ADC_CR2_JEXTSEL(n)	((n) << 12)
+
+#define ADC_JSQR_NUM_CH(n)      (((n) - 1) << 20)
+#define ADC_JSQR_JSQ1_N(n)      ((n) << 0)
+#define ADC_JSQR_JSQ2_N(n)      ((n) << 5)
+#define ADC_JSQR_JSQ3_N(n)      ((n) << 10)
+#define ADC_JSQR_JSQ4_N(n)      ((n) << 15)
+
+#define ADC_CHANNEL_IN10        10
+#define ADC_CHANNEL_IN11        11
+#define ADC_CHANNEL_IN12        12
+#define ADC_CHANNEL_IN13        13
+
+#define USE_ADC3_INTR		1
+#define INTR_REQ_ADC3		47
+
+/*
+ * Do calibration for ADC3.
+ */
+void adc3_init (void)
+{
+  RCC->APB2ENR |= RCC_APB2ENR_ADC3EN;
+  RCC->APB2RSTR = RCC_APB2RSTR_ADC3RST;
+  RCC->APB2RSTR = 0;
+
+  ADC3->CR1 = 0;
+  ADC3->CR2 = ADC_CR2_ADON;
+  ADC3->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+  while ((ADC3->CR2 & ADC_CR2_RSTCAL) != 0)
+    ;
+  ADC3->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+  while ((ADC3->CR2 & ADC_CR2_CAL) != 0)
+    ;
+  ADC3->CR2 = 0;
+  RCC->APB2ENR &= ~RCC_APB2ENR_ADC3EN;
+}
+
+static chopstx_intr_t adc3_intr;
+
+void
+adc3_start (void)
+{
+  RCC->APB2ENR |= RCC_APB2ENR_ADC3EN;
+
+#if USE_ADC3_INTR
+  ADC3->CR1 = ADC_CR1_SCAN | ADC_CR1_JEOCIE;
+#else
+  ADC3->CR1 = ADC_CR1_SCAN;
+#endif
+  ADC3->CR2 = ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL(7) | ADC_CR2_ADON;
+  ADC3->SMPR1 = 0xfff;
+  ADC3->SMPR2 = 0;
+  ADC3->JSQR = (ADC_JSQR_NUM_CH(4) | ADC_JSQR_JSQ4_N(ADC_CHANNEL_IN13)
+		| ADC_JSQR_JSQ3_N(ADC_CHANNEL_IN12)
+		| ADC_JSQR_JSQ2_N(ADC_CHANNEL_IN11)
+		| ADC_JSQR_JSQ1_N(ADC_CHANNEL_IN10));
+
+#if USE_ADC3_INTR
+  chopstx_claim_irq (&adc3_intr, INTR_REQ_ADC3);
+#endif
+}
+
+void adc3_conversion (uint32_t *result)
+{
+
+  /* Start conversion.  */
+  ADC3->CR2 |= ADC_CR2_JSWSTART;
+
+#if USE_ADC3_INTR
+  chopstx_intr_wait (&adc3_intr);
+#else
+  while (1)
+    {
+      chopstx_usec_wait (1000);
+      if (ADC3->SR & ADC_SR_JEOC)
+	break;
+    }
+#endif
+  ADC3->SR &= ~ADC_SR_JEOC;
+
+  result[0] = ADC3->JDR1;
+  result[1] = ADC3->JDR2;
+  result[2] = ADC3->JDR3;
+  result[3] = ADC3->JDR4;
+
+  /* Stop conversion.  */
+  ADC3->CR2 &= ~ADC_CR2_JSWSTART;
+
+  return;
+}
+
+void adc3_stop (void)
+{
+
+  /* Power off.  */
+  ADC3->CR1 = 0;
+  ADC3->CR2 = 0;
+
+  RCC->APB2ENR &= ~RCC_APB2ENR_ADC3EN;
+}
+
+/* Touch screen routines.  */
+
+int
+ts_pushed (uint32_t u)
+{
+  return (u < 0xc00);
+}
+
+#define FILTER_SIZE	8
+
+static void
+ts_filter (int buf[FILTER_SIZE][2], int result[2])
+{
+  int s0, s1;
+  int i;
+
+  s0 = 0;
+  s1 = 0;
+  for (i = 0; i < FILTER_SIZE; i++)
+    {
+      s0 += buf[i][0];
+      s1 += buf[i][1];
+    }
+
+  result[0] = s0/FILTER_SIZE;
+  result[1] = s1/FILTER_SIZE;
+}
+
+/* Simple model of primer2 touch screen:
+    Vdd-[R1]-[Ry]-[Rp]-[Rx]-Vss
+            U    D    l    R
+   where R1=1k external register, Rx(resp. Ry)=resisitive component on
+   X(resp. Y) film and Rp=resisitive component of contact point.
+   Convert [L, R, U, D] to [Rx, Ry, Rp].  */
+void
+ts_conversion (uint32_t a[], int r[])
+{
+  int l, u, d, ir1;
+  int x, y, rp;
+
+  l = a[0] & 0xfff;
+  u = a[2] & 0xfff;
+  d = a[3] & 0xfff;
+  ir1 = 4096 - u;
+  /* r1 = 1000 */
+  x = (1000 * l)/ir1;
+  y = (1000 * (u - d))/ir1;
+  rp = (1000 * (d - l))/ir1;
+  r[0] = x;
+  r[1] = y;
+  r[2] = rp;
+}
+
+int
+ts_adjust (int *r, int *cord)
+{
+  int x, y;
+  static int buf[FILTER_SIZE][2];
+  static int i = 0;
+  static int fill = 0;
+
+  if (!r)
+    {
+      i = 0;
+      fill = 0;
+      return 0;
+    }
+
+  /* TODO: We might need calibration.  */
+  x = (LCD_COLUMN * (r[0] - 0x20))/0x100;
+  y = (LCD_ROW * (0x1e0 - r[1]))/0x1c0;
+
+  if (x < 0)
+    x = 0;
+  if (x >= LCD_COLUMN)
+    x = LCD_COLUMN - 1;
+  if (y < 0)
+    y = 0;
+  if (y >= LCD_ROW)
+    y = LCD_ROW - 1;
+
+  buf[i][0] = x;
+  buf[i][1] = y;
+
+  i++;
+  if (i >= FILTER_SIZE)
+    {
+      i = 0;
+      fill = 1;
+    }
+
+  if (!fill)
+    return 0;
+
+  ts_filter (buf, cord);
+  return 1;
+}
--- a/example-primer2/primer2-ts.h
+++ b/example-primer2/primer2-ts.h
@@ -0,0 +1,8 @@
+extern void adc3_init (void);
+extern void adc3_start (void);
+extern void adc3_conversion (uint32_t *result);
+extern void adc3_stop (void);
+
+extern int ts_pushed (uint32_t u);
+extern void ts_conversion (uint32_t a[], int r[]);
+extern int ts_adjust (int r[], int cord[]);
--- a/example-primer2/st7732.h
+++ b/example-primer2/st7732.h
@@ -0,0 +1,83 @@
+/* ST7732 LCD driver chip command byte.
+  command_name = value  read_n_bytes:write_n_bytes: simple description  */
+enum st7732_cmd {
+  NOP = 0x00,		/* 0:0: No Operatin */
+  SWRESET = 0x01,	/* 0:0: Software reset */
+  RDDID = 0x04,		/* 0:3: Read Display ID */
+  RDRST = 0x09,		/* 0:4: Read Display Status */
+  RDDPM = 0x0a,		/* 0:1: Read Display Power Mode */
+  RDD_MADCTL = 0x0b,	/* 0:1: Read Display MADCTL */
+  RDD_COLMOD = 0x0c,	/* 0:1: Read Display Pixel Format */
+  RDDIM = 0x0d,		/* 0:1: Read Display Image Mode */
+  RDDSM = 0x0e,		/* 0:1: Read Display Signal Mode */
+  RDDSDR = 0x0f,	/* 0:1: Read Display Self-diagnostic result */
+  SLPIN = 0x10,		/* 0:0: Sleep in & booster off */
+  SLPOUT = 0x11,	/* 0:0: Sleep out & booster on */
+  PTLON = 0x12,		/* 0:0: Pertial mode on */
+  NORON = 0x13,		/* 0:0: Normal mode on (Pertial off) */
+  INVOFF = 0x20,	/* 0:0: Display inversion off */
+  INVON = 0x21,		/* 0:0: Display inversion on */
+  GAMSET = 0x26,	/* 1:0: Gamma curve select */
+  DISPOFF = 0x28,	/* 0:0: Display off */
+  DISPON = 0x29,	/* 0:0: Display on */
+  CASET = 0x2a,		/* 4:0: Column address set */
+  RASET = 0x2b,		/* 4:0: Raw address set */
+  RAMWR = 0x2c,		/* 1:0: Memory write */
+  RAMRD = 0x2e,		/* 0:1: Memory read */
+  PTLAR = 0x30,		/* 4:0: Partial start/end address set */
+  SCRLAR = 0x33,	/* 6:0: Scroll area set */
+  TEOFF = 0x34,		/* 0:0: Tearing effect line off */
+  TEON = 0x35,		/* 1:0: Tearing effect mode set & on */
+  MADCTL = 0x36,	/* 1:0: Memory data access control */
+  VSCSAD = 0x37,	/* 2:0: Scroll start address of RAM */
+  IDMOFF = 0x38,	/* 0:0: Idle mode off */
+  IDMON = 0x39,		/* 0:0: Idle mode on */
+  COLMOD = 0x3a,	/* 1:0: Interface pixel format */
+  RDID1 = 0xda,		/* 0:1: Read ID1 */
+  RDID2 = 0xdb,		/* 0:1: Read ID2 */
+  RDID3 = 0xdc,		/* 0:1: Read ID3 */
+  RGBCTR = 0xb0,	/* 1:0: Set RGB signal control */
+  FRMCTR1 = 0xb1,	/* 3:0: In normal mode */
+  FRMCTR2 = 0xb2,	/* 3:0: In Idel mode (8-colors) */
+  FRMCTR3 = 0xb3,	/* 6:0: In partial mode + Full colors */
+  INVCTR = 0xb4,	/* 1:0: Display inversion control */
+  RGB_BPCTR = 0xb5,	/* 4:0: RGB I/F Blanking porch setting */
+  DISSET5 = 0xb6,	/* 2:0: Display function setting */
+  PWCTR1 = 0xc0,	/* 2:0: Power control setting */
+  PWCTR2 = 0xc1,	/* 1:0: Power control setting */
+  PWCTR3 = 0xc2,	/* 2:0: Power control setting (Full colors) */
+  PWCTR4 = 0xc3,	/* 2:0: Power control setting (8-colors) */
+  PWCTR5 = 0xc4,	/* 2:0: Power control setting (In partial mode) */
+  VMCTR1 = 0xc5,	/* 2:0: VCOM control */
+  VMOFCTR = 0xc6,	/* 1:0: VCOM offset control */
+  WRID2 = 0xd1,		/* 1:0: Write ID2 value to NV */
+  WRID3 = 0xd2,		/* 1:0: Write ID3 value to NV */
+  RDID4 = 0xd3,		/* 0:4: IC Vender code */
+  NVCTR1 = 0xd9,	/* 0:1:no-fummy NVM control status */
+  NVCTR2 = 0xde,	/* 3:0: NVM read command (aa, 0f, a5) */
+  NVCTR3 = 0xdf,	/* 3:0: NVM write command (55, f0, 5a) */
+  GAMCTRP1 = 0xe0,	/* 13:0: Set Gamma correction + */
+  GAMCTRN1 = 0xe1,	/* 13:0: Set Gamma correction - */
+  AUTO_CTRL = 0xf1,	/* 1:0: NVM write function ON/OFF */
+  OSCADJ = 0xf2,	/* 1:0: Osillator frequency setting */
+  DISPCTRL = 0xf5,	/* 1:0: Display function control */
+  DEFADJ = 0xf6,	/* 1:0: Default mode setting */
+};
+
+typedef enum st7732_cmd st7732_cmd_t;
+
+extern void lcd_command_no (st7732_cmd_t cmd);
+extern void lcd_command_readn (st7732_cmd_t cmd, uint8_t *p, size_t n);
+extern void lcd_command_writen (st7732_cmd_t cmd, uint8_t *p, size_t n);
+extern void lcd_command_filln (st7732_cmd_t cmd, uint8_t b, size_t n);
+extern void lcd_init (void);
+
+extern void lcd_draw_point (int x, int y, int r, int g, int b);
+extern void lcd_draw_hexfont5x8 (uint32_t hex, int x, int y, int r, int g,
+				 int b, int bg);
+extern void lcd_printhex (uint32_t hex, int x, int y, int r, int g, int b,
+			  int bg);
+
+#define LCD_COLUMN	128
+#define LCD_ROW		160
+#define BYTES_PER_PIXEL	3
--- a/mcu/ABOUT-SYS
+++ b/mcu/ABOUT-SYS
@@ -0,0 +1,239 @@
+Consideration about SYS and the first pages of flash ROM
+========================================================
+
+Now, I'm developing something like SYS for Kinetis L MCU, so, I write
+this document.
+
+* Compatibility
+
+  SYS 1.0: The first verson
+  SYS 2.0: Added clock_init, gpio_init 
+  SYS 2.1: Added sys_board_id, sys_board_name 
+  SYS 3.0: Don't setup NVIC priority by usb_lld_sys_init
+
+
+* Macro definition by DEFS in Makefile
+
+  - USE_SYS_CLOCK_GPIO_SETTING
+
+    Define this macro to ask chopstx/entry.c (the runtime code before
+    MAIN function) to use function entries in SYS for clock_init and
+    gpio_init.
+
+    If not defined, entry.c includes the code for clock_init and
+    gpio_init which might be different to a board, and use them (entries
+    in SYS will not be used).  This works well with the ROM of SYS
+    1.0.
+
+    Note that SYS entries of clock_init and gpio_init were introduced
+    in SYS 2.0.  So, enable this macro only if the ROM is SYS 2.0 or
+    later.
+
+  - USE_SYS_BOARD_ID
+
+    Define this macro in a driver to get "sys_board_id" in SYS, so
+    that the driver can support various boards at runtime by changing
+    the settings according to the board.
+
+    A simple driver could only support a single board, by the compile
+    time (BOARD_ID in board-*.h) choice of of a settings.
+
+    Note that SYS entries of sys_board_id and sys_board_name were
+    introduced in SYS 2.1.  So, enable this macro only if the ROM is
+    SYS 2.1 or later.
+
+  - USE_SYS3
+
+    By defining this, it will have same effect of defining both of
+    USE_SYS_CLOCK_GPIO_SETTING and USE_SYS_BOARD_ID internally.
+
+
+About SYS on STM32F103
+======================
+
+In the development of Gnuk, we developed:
+
+	SYS: The system predefined routines for STM32F103
+
+It is now maintained as example-cdc/sys.c.
+
+There is another version in example-led/sys.c, which also support
+STM32F030, as well as STM32F103.  But, it wouldn't be useful for
+STM32F030.  In fact, the file example-fsm-55/sys.c has name sys.c
+but it doesn't include any system routines.
+
+The original issue was:
+
+    (1) When it's protected, STM32F103 can't change the first 4KiB of
+        flash ROM at run time.
+
+    (2) We want to support firmware upgrade through its USB.
+
+Later on, we add another point.
+
+    (3) It is good if the executable of Gnuk could be shared among
+        different boards.
+
+For (1) and (2), we decided put some useful routines and data which is
+not need to be changed.
+
+Now, the first 4KiB of flash ROM consists of:
+
+     1KiB: SYS
+     3KiB: 3/4 of AES forward tables
+
+SYS consists of:
+
+  Internal: reset entry, end of RAM
+  Data: board identification
+  Routines: board specific
+            board independent
+
+and here is the list of all.
+
+* Internal routines
+
+  reset entry
+  end of RAM
+
+* Board identification
+
+  sys_version
+  sys_board_id
+  sys_board_name
+
+* Board specific routines
+
+  * led
+    set_led
+
+  * mcu/board lower level
+    clock_init
+    gpio_init
+
+  * usb
+    usb_lld_sys_init
+    usb_lld_sys_shutdown
+
+* Board independent routines
+
+  * flash ROM access routines
+
+    unlock
+    write halfword
+    erase page
+    brank check
+    write page
+    protect
+    erase_all & exec to ram
+
+  * system reset routine
+
+    nvic_system_reset
+
+The routines of clock_init and gpio_init are here because of some
+historical reasons.  (We could design a system with no such exported
+routines: by defining: those things done internally after reset and
+before calling the application.)
+
+Those are exported as entries of SYS, and it is the responsibility of
+the application which do initialize clock and GPIO, calling those
+routines.
+
+USB routines are needed because of hardware practice of STM32F103.
+With STM32F103, each board has different way for handling the pull up
+of USB D+ and how the device asks re-enumeration to host PC.  In my
+opinion, if it's defined as full speed device and it's OK for us not
+to use high impedance (but asserting to LOW, instead) of D+ to ask
+re-enumeration, we can just pull up D+ always.  And we wouldn't need
+such routines in SYS.
+
+
+
+About SYS on Kinetis L
+======================
+
+For Kinetis L, because it's ROM has the original firmware upgrade
+support by the vendor (though USB HID), all that we needed for
+firmware upgrade would be just erasing to factory settings.
+
+And it has no limitation like STM32F103's first 4KiB flash ROM.
+All pages can be updated at run time.
+
+Nevertheless, the first two pages (2KiB) of KL27Z is still difficult
+to use.
+
+So, I decide to introduce something like SYS for Kinetis L.
+
+
+* Layout
+
+Three pages (3KiB) usage:
+
+  ------------ The first page
+  End of RAM <-- not used but hardware defines this
+  Address of reset entry
+  sys_version
+  sys_board_info (id, name)
+  sys_vector
+
+  other SYS routines and data...
+
+  ------------ The second page
+  FLASH CONFIG: 16-byte
+  Reset entry function
+  flash routines
+  CRC-32 routines
+  CRC-32 table (768-byte of CRC-32 table)
+
+  ------------ The third page
+  MAGIC 256-byte (256-byte of the last part of CRC-32 table)
+  ...
+  vectors (initial MSP, reset, ...) 
+  ...
+
+
+* data: Board identification
+
+  sys_version
+  sys_board_id
+  sys_board_name ; null terminated
+
+* Board specific routines
+
+  * mcu/board lower level
+    clock_init
+    gpio_init
+
+  * led
+    set_led
+
+* data: Board independent routines
+
+  * flash ROM access code to be loaded on to RAM
+
+* system reset routine???
+
+    nvic_system_reset
+
+
+* data: vectors for routines and data
+  sys_version
+  sys_board_id
+  address of sys_board_name
+  address of set_led
+  address of clock_init 
+  address of gpio_init 
+  address of ...
+
+
+
+An Example of No-use of SYS
+===========================
+
+See example-fsm-55 for an example of no use of SYS.
+
+While chopstx/entry.c defines vectors in ROM and RAM, those are simply
+discarded by example-fsm-55/hacker-emblem.ld.
+
+--
--- a/mcu/clk_gpio_init-mkl27z.c
+++ b/mcu/clk_gpio_init-mkl27z.c
@@ -0,0 +1,104 @@
+/*
+ * clk_gpio_init-mkl27z.c - Clock and GPIO initialization for Kinetis L.
+ *
+ * Copyright (C) 2016  Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#include <mcu/mkl27z.h>
+
+struct MCG {
+  volatile uint8_t C1;   /* MCG Control Register 1             */
+  volatile uint8_t C2;   /* MCG Control Register 2             */
+  uint8_t reserved0[4];  /*                                    */
+  volatile uint8_t S;    /* MCG Status Register                */
+  uint8_t reserved1[1];  /*                                    */
+  volatile uint8_t SC;   /* MCG Status and Control Register    */
+  uint8_t reserved2[15]; /*                                    */
+  volatile uint8_t MC;   /* MCG Miscellaneous Control Register */
+};
+static struct MCG *const MCG = (struct MCG *)0x40064000;
+
+struct USB_CLK_RECOVER {
+  volatile uint8_t CTRL;           /* USB Clock             */
+  uint8_t rsvd38[3];               /*     recovery control  */
+  volatile uint8_t IRC_EN;         /* IRC48M oscillator     */
+  uint8_t rsvd39[3];               /*     enable register   */
+  volatile uint8_t INT_EN;         /* Clock recovery        */
+  uint8_t rsvd40[3];               /*     interrupt enable  */
+  volatile uint8_t INT_STATUS;     /* Clock recovery        */
+                                   /*     interrupt status  */
+};
+static struct USB_CLK_RECOVER *const USB_CLK_RECOVER =
+  (struct USB_CLK_RECOVER *)0x40072140;
+
+static void __attribute__((used))
+clock_init (void)
+{
+  SIM->CLKDIV1 = (SIM->CLKDIV1 & 0xF0070000)
+               | (1 << 16)	/* OUTDIV4 = 001: Divide-by-2 */
+               ;
+
+  MCG->MC = 0x80; /* HIRC Enable, LIRC_DIV2=000: Division factor=1 */
+  MCG->C1 = 0x00; /* Select HIRC clock, LIRC disabled. */
+  /* Make sure HIRC clock is selected.  */
+  while ((MCG->S & 0x0c) != 0)
+    ;
+
+  /* TPMSRC=IRC48M, USBSRC=IRC48M, CLOKOUTSEL=LPO, RTC-clock */
+  SIM->SOPT2 = 0x01040060;
+
+  SIM->SCGC4 = (1 << 18);	/* Enable USB FS clock        */
+  SIM->SCGC5 = (1 << 10);	/* Enable Port B clock        */
+  SIM->SCGC6 = (1 << 25)|1;	/* Enable TPM1 clock          */
+  SIM->COPC = 0;		/* COP disabled               */
+
+  /* Crystal-less USB setup.  */
+  USB_CLK_RECOVER->IRC_EN = 0x02;
+  USB_CLK_RECOVER->CTRL = 0x80;
+}
+
+
+static void __attribute__((used))
+gpio_init (void)
+{
+  PORTB->PCR0 = (1<<8) /* GPIO                  */
+              | (0<<6) /* DriveStrengthEnable=0 */
+              | (0<<4) /* PassiveFilterEnable=0 */
+              | (1<<2) /* SlewRateEnable = slow */
+              | (0<<1) /* pull enable = 0       */ 
+              | (0<<0) /* pull up select= 0     */
+              ;
+  PORTB->PCR1 = (1<<8) /* GPIO                  */
+              | (0<<6) /* DriveStrengthEnable=0 */
+              | (0<<4) /* PassiveFilterEnable=0 */
+              | (1<<2) /* SlewRateEnable = slow */
+              | (0<<1) /* pull enable = 0       */ 
+              | (0<<0) /* pull up select= 0     */
+              ;
+
+  GPIOB->PDDR = (1 << 1) | (1 << 0); /* PTB0, PTB1 : Output    */
+  GPIOB->PSOR = (1 << 0);            /* PTB0: Set  : Light off */
+  GPIOB->PCOR = (1 << 1);            /* PTB1: Clear: Output 0  */
+}
--- a/mcu/clk_gpio_init-stm32.c
+++ b/mcu/clk_gpio_init-stm32.c
@@ -0,0 +1,368 @@
+/*
+ * clk_gpio_init-stm32.c - Clock and GPIO initialization for STM32.
+ *
+ * Copyright (C) 2015  Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#define STM32_SW_HSI		(0 << 0)
+#define STM32_SW_PLL		(2 << 0)
+#define STM32_PLLSRC_HSI	(0 << 16)
+#define STM32_PLLSRC_HSE	(1 << 16)
+
+#define STM32_PLLXTPRE_DIV1	(0 << 17)
+#define STM32_PLLXTPRE_DIV2	(1 << 17)
+
+#define STM32_HPRE_DIV1		(0 << 4)
+
+#define STM32_PPRE1_DIV1	(0 << 8)
+#define STM32_PPRE1_DIV2	(4 << 8)
+
+#define STM32_PPRE2_DIV1        (0 << 11)
+#define STM32_PPRE2_DIV2	(4 << 11)
+
+#define STM32_ADCPRE_DIV4	(1 << 14)
+#define STM32_ADCPRE_DIV6       (2 << 14)
+
+#define STM32_USBPRE_DIV1P5     (0 << 22)
+
+#define STM32_MCO_NOCLOCK	(0 << 24)
+
+#if defined(MCU_STM32F0)
+#define STM32_PPRE1		STM32_PPRE1_DIV1
+#define STM32_PLLSRC		STM32_PLLSRC_HSI
+#define STM32_FLASHBITS		0x00000011
+#define STM32_PLLCLKIN		(STM32_HSICLK / 2)
+#else
+#define STM32_PPRE1		STM32_PPRE1_DIV2
+#define STM32_PLLSRC		STM32_PLLSRC_HSE
+#define STM32_FLASHBITS		0x00000012
+#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
+#endif
+
+#define STM32_SW		STM32_SW_PLL
+#define STM32_HPRE		STM32_HPRE_DIV1
+#define STM32_PPRE2		STM32_PPRE2_DIV1
+#define STM32_ADCPRE		STM32_ADCPRE_DIV6
+#define STM32_MCOSEL		STM32_MCO_NOCLOCK
+#define STM32_USBPRE            STM32_USBPRE_DIV1P5
+
+#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
+#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+#define STM32_SYSCLK		STM32_PLLCLKOUT
+#define STM32_HCLK		(STM32_SYSCLK / 1)
+
+
+#define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
+
+struct RCC {
+  volatile uint32_t CR;
+  volatile uint32_t CFGR;
+  volatile uint32_t CIR;
+  volatile uint32_t APB2RSTR;
+  volatile uint32_t APB1RSTR;
+  volatile uint32_t AHBENR;
+  volatile uint32_t APB2ENR;
+  volatile uint32_t APB1ENR;
+  volatile uint32_t BDCR;
+  volatile uint32_t CSR;
+#if defined(MCU_STM32F0)
+  volatile uint32_t AHBRSTR;
+  volatile uint32_t CFGR2;
+  volatile uint32_t CFGR3;
+  volatile uint32_t CR2;
+#endif
+};
+
+#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
+static struct RCC *const RCC = (struct RCC *)RCC_BASE;
+
+#define RCC_APB1ENR_USBEN	0x00800000
+#define RCC_APB1RSTR_USBRST	0x00800000
+
+#define RCC_CR_HSION		0x00000001
+#define RCC_CR_HSIRDY		0x00000002
+#define RCC_CR_HSITRIM		0x000000F8
+#define RCC_CR_HSEON		0x00010000
+#define RCC_CR_HSERDY		0x00020000
+#define RCC_CR_PLLON		0x01000000
+#define RCC_CR_PLLRDY		0x02000000
+
+#define RCC_CFGR_SWS		0x0000000C
+#define RCC_CFGR_SWS_HSI	0x00000000
+
+#define RCC_AHBENR_CRCEN        0x0040
+
+#if defined(MCU_STM32F0)
+#define RCC_AHBRSTR_IOPARST	0x00020000
+#define RCC_AHBRSTR_IOPBRST	0x00040000
+#define RCC_AHBRSTR_IOPCRST	0x00080000
+#define RCC_AHBRSTR_IOPDRST	0x00100000
+#define RCC_AHBRSTR_IOPFRST	0x00400000
+
+#define RCC_AHBENR_IOPAEN	0x00020000
+#define RCC_AHBENR_IOPBEN	0x00040000
+#define RCC_AHBENR_IOPCEN	0x00080000
+#define RCC_AHBENR_IOPDEN	0x00100000
+#define RCC_AHBENR_IOPFEN	0x00400000
+
+#define RCC_APB2RSTR_SYSCFGRST	0x00000001
+#define RCC_APB2ENR_SYSCFGEN	0x00000001
+#else
+#define RCC_APB2RSTR_AFIORST	0x00000001
+#define RCC_APB2RSTR_IOPARST	0x00000004
+#define RCC_APB2RSTR_IOPBRST	0x00000008
+#define RCC_APB2RSTR_IOPCRST	0x00000010
+#define RCC_APB2RSTR_IOPDRST	0x00000020
+#define RCC_APB2RSTR_IOPERST	0x00000040
+#define RCC_APB2RSTR_IOPFRST	0x00000080
+#define RCC_APB2RSTR_IOPGRST	0x00000100
+
+#define RCC_APB2ENR_AFIOEN	0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+#define RCC_APB2ENR_IOPEEN	0x00000040
+#define RCC_APB2ENR_IOPFEN	0x00000080
+#define RCC_APB2ENR_IOPGEN	0x00000100
+#endif
+
+#if defined(MCU_STM32F0)
+struct SYSCFG {
+  volatile uint32_t CFGR1;
+  uint32_t dummy0;
+  volatile uint32_t EXTICR[4];
+  volatile uint32_t CFGR2;
+};
+#define SYSCFG_CFGR1_MEM_MODE 0x03
+
+#define SYSCFG_BASE	(APBPERIPH_BASE + 0x00010000)
+static struct SYSCFG *const SYSCFG = (struct SYSCFG *)SYSCFG_BASE;
+#endif
+
+struct FLASH {
+  volatile uint32_t ACR;
+  volatile uint32_t KEYR;
+  volatile uint32_t OPTKEYR;
+  volatile uint32_t SR;
+  volatile uint32_t CR;
+  volatile uint32_t AR;
+  volatile uint32_t RESERVED;
+  volatile uint32_t OBR;
+  volatile uint32_t WRPR;
+};
+
+#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
+static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;
+
+static void __attribute__((used))
+clock_init (void)
+{
+  /* HSI setup */
+  RCC->CR |= RCC_CR_HSION;
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;
+  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
+  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
+  RCC->CFGR = 0;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;
+
+#if !defined(MCU_STM32F0)
+  /* HSE setup */
+  RCC->CR |= RCC_CR_HSEON;
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;
+#endif
+
+  /* PLL setup */
+  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;
+
+  /* Clock settings */
+  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
+    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+  /*
+   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
+   */
+
+  /* Flash setup */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* CRC */
+  RCC->AHBENR |= RCC_AHBENR_CRCEN;
+
+  /* Switching on the configured clock source. */
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;
+
+#if defined(MCU_STM32F0)
+  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+  RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
+  RCC->APB2RSTR = 0;
+
+# if defined(STM32F0_USE_VECTOR_ON_RAM)
+  /* Use vectors on RAM */
+  SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
+# endif
+#endif
+}
+
+
+#if defined(MCU_STM32F0)
+struct GPIO {
+  volatile uint32_t MODER;
+  volatile uint16_t OTYPER;
+  uint16_t dummy0;
+  volatile uint32_t OSPEEDR;
+  volatile uint32_t PUPDR;
+  volatile uint16_t IDR;
+  uint16_t dummy1;
+  volatile uint16_t ODR;
+  uint16_t dummy2;
+  volatile uint16_t BSRR;
+  uint16_t dummy3;
+  volatile uint32_t LCKR;
+  volatile uint32_t AFR[2];
+  volatile uint16_t BRR;
+  uint16_t dummy4;
+};
+
+#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
+#define GPIOF		((struct GPIO *) GPIOF_BASE)
+#else
+struct AFIO
+{
+  volatile uint32_t EVCR;
+  volatile uint32_t MAPR;
+  volatile uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  volatile uint32_t MAPR2;
+};
+
+#define AFIO_BASE 0x40010000
+static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE;
+
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE     0x02000000
+
+
+struct GPIO {
+  volatile uint32_t CRL;
+  volatile uint32_t CRH;
+  volatile uint32_t IDR;
+  volatile uint32_t ODR;
+  volatile uint32_t BSRR;
+  volatile uint32_t BRR;
+  volatile uint32_t LCKR;
+};
+
+#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
+#define GPIOE		((struct GPIO *) GPIOE_BASE)
+#endif
+
+static struct GPIO *const GPIO_LED = (struct GPIO *)GPIO_LED_BASE;
+#ifdef GPIO_USB_BASE
+static struct GPIO *const GPIO_USB = (struct GPIO *)GPIO_USB_BASE;
+#endif
+#ifdef GPIO_OTHER_BASE
+static struct GPIO *const GPIO_OTHER = (struct GPIO *)GPIO_OTHER_BASE;
+#endif
+
+static void __attribute__((used))
+gpio_init (void)
+{
+  /* Enable GPIO clock. */
+#if defined(MCU_STM32F0)
+  RCC->AHBENR |= RCC_ENR_IOP_EN;
+  RCC->AHBRSTR = RCC_RSTR_IOP_RST;
+  RCC->AHBRSTR = 0;
+#else
+  RCC->APB2ENR |= RCC_ENR_IOP_EN;
+  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
+  RCC->APB2RSTR = 0;
+#endif
+
+#if defined(MCU_STM32F0)
+  GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
+  GPIO_LED->OTYPER  = VAL_GPIO_LED_OTYPER;
+  GPIO_LED->MODER   = VAL_GPIO_LED_MODER;
+  GPIO_LED->PUPDR   = VAL_GPIO_LED_PUPDR;
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
+  GPIO_OTHER->OTYPER  = VAL_GPIO_OTHER_OTYPER;
+  GPIO_OTHER->MODER   = VAL_GPIO_OTHER_MODER;
+  GPIO_OTHER->PUPDR   = VAL_GPIO_OTHER_PUPDR;
+#endif
+#else
+#ifdef AFIO_MAPR_SOMETHING
+  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
+#endif
+
+  /* LED is mandatory.  If it's on an independent port, we configure it.  */
+  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
+  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
+  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
+
+  /* If there is USB enabler pin and it's independent, we configure it.  */
+#if defined(GPIO_USB_BASE) && GPIO_USB_BASE != GPIO_LED_BASE
+  GPIO_USB->ODR = VAL_GPIO_USB_ODR;
+  GPIO_USB->CRH = VAL_GPIO_USB_CRH;
+  GPIO_USB->CRL = VAL_GPIO_USB_CRL;
+#endif
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
+  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
+  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
+#endif
+#endif
+}
--- a/mcu/mkl27z.h
+++ b/mcu/mkl27z.h
@@ -0,0 +1,70 @@
+/* System Integration Module.  */
+struct SIM {
+  volatile uint32_t SOPT1;    /* System Options Register 1               */
+  volatile uint32_t SOPT1CFG; /* SOPT1 Configuration Register            */
+  uint32_t reserved0[1023];   /*                                         */
+  volatile uint32_t SOPT2;    /* System Options Register 2               */
+  uint32_t reserved1[1];      /*                                         */
+  volatile uint32_t SOPT4;    /* System Options Register 4               */
+  volatile uint32_t SOPT5;    /* System Options Register 5               */
+  uint32_t reserved2[1];      /*                                         */
+  volatile uint32_t SOPT7;    /* System Options Register 7               */
+  uint32_t reserved3[2];       /*                                         */
+  volatile uint32_t SDID;     /* System Device Identification Register   */
+  uint32_t reserved4[3];      /*                                         */
+  volatile uint32_t SCGC4;    /* System Clock Gating Control Register 4  */
+  volatile uint32_t SCGC5;    /* System Clock Gating Control Register 5  */
+  volatile uint32_t SCGC6;    /* System Clock Gating Control Register 6  */
+  volatile uint32_t SCGC7;    /* System Clock Gating Control Register 7  */
+  volatile uint32_t CLKDIV1;  /* System Clock Divider Register 1         */
+  uint32_t reserved5[1];      /*                                         */
+  volatile uint32_t FCFG1;    /* Flash Configuration Register 1          */
+  volatile uint32_t FCFG2;    /* Flash Configuration Register 2          */
+  uint32_t reserved6[1];      /*                                         */
+  volatile uint32_t UIDMH;    /* Unique Identification Register Mid-High */
+  volatile uint32_t UIDML;    /* Unique Identification Register Mid Low  */
+  volatile uint32_t UIDL;     /* Unique Identification Register Low      */
+  uint32_t reserved7[39];     /*                                         */
+  volatile uint32_t COPC;     /* COP Control Register                    */
+  volatile uint32_t SRVCOP;   /* Service COP                             */
+};
+
+/* Port control. */
+struct PORT {
+  volatile uint32_t PCR0;  volatile uint32_t PCR1;
+  volatile uint32_t PCR2;  volatile uint32_t PCR3;
+  volatile uint32_t PCR4;  volatile uint32_t PCR5;
+  volatile uint32_t PCR6;  volatile uint32_t PCR7;
+  volatile uint32_t PCR8;  volatile uint32_t PCR9;
+  volatile uint32_t PCR10; volatile uint32_t PCR11;
+  volatile uint32_t PCR12; volatile uint32_t PCR13;
+  volatile uint32_t PCR14; volatile uint32_t PCR15;
+  volatile uint32_t PCR16; volatile uint32_t PCR17;
+  volatile uint32_t PCR18; volatile uint32_t PCR19;
+  volatile uint32_t PCR20; volatile uint32_t PCR21;
+  volatile uint32_t PCR22; volatile uint32_t PCR23;
+  volatile uint32_t PCR24; volatile uint32_t PCR25;
+  volatile uint32_t PCR26; volatile uint32_t PCR27;
+  volatile uint32_t PCR28; volatile uint32_t PCR29;
+  volatile uint32_t PCR30; volatile uint32_t PCR31;
+  volatile uint32_t GPCLR; volatile uint32_t GPCHR;
+  uint32_t reserved[6];
+  volatile uint32_t ISFR;
+};
+
+struct GPIO {
+  volatile uint32_t PDOR; /* Port Data Output Register    */
+  volatile uint32_t PSOR; /* Port Set Output Register     */
+  volatile uint32_t PCOR; /* Port Clear Output Register   */
+  volatile uint32_t PTOR; /* Port Toggle Output Register  */
+  volatile uint32_t PDIR; /* Port Data Input Register     */
+  volatile uint32_t PDDR; /* Port Data Direction Register */
+};
+
+static struct SIM *const SIM = (struct SIM *)0x40047000;
+static struct PORT *const PORTB = (struct PORT *)0x4004A000;
+static struct PORT *const PORTD = (struct PORT *)0x4004C000;
+static struct PORT *const PORTE = (struct PORT *)0x4004D000;
+static struct GPIO *const GPIOB = (struct GPIO *)0x400FF040;
+static struct GPIO *const GPIOD = (struct GPIO *)0x400FF0C0;
+static struct GPIO *const GPIOE = (struct GPIO *)0x400FF100;
--- a/mcu/stm32f103.h
+++ b/mcu/stm32f103.h
@@ -0,0 +1,700 @@
+#define PERIPH_BASE	0x40000000
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+
+struct RCC {
+  volatile uint32_t CR;
+  volatile uint32_t CFGR;
+  volatile uint32_t CIR;
+  volatile uint32_t APB2RSTR;
+  volatile uint32_t APB1RSTR;
+  volatile uint32_t AHBENR;
+  volatile uint32_t APB2ENR;
+  volatile uint32_t APB1ENR;
+  volatile uint32_t BDCR;
+  volatile uint32_t CSR;
+};
+
+#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
+static struct RCC *const RCC = (struct RCC *)RCC_BASE;
+
+#define RCC_AHBENR_DMA1EN       0x00000001
+#define RCC_AHBENR_CRCEN        0x00000040
+
+#define RCC_APB2ENR_ADC1EN      0x00000200
+#define RCC_APB2ENR_ADC2EN      0x00000400
+#define RCC_APB2ENR_TIM1EN      0x00000800
+#define RCC_APB1ENR_TIM2EN      0x00000001
+#define RCC_APB1ENR_TIM3EN      0x00000002
+#define RCC_APB1ENR_TIM4EN      0x00000004
+
+#define RCC_APB2RSTR_ADC1RST    0x00000200
+#define RCC_APB2RSTR_ADC2RST    0x00000400
+#define RCC_APB2RSTR_TIM1RST    0x00000800
+#define RCC_APB1RSTR_TIM2RST    0x00000001
+#define RCC_APB1RSTR_TIM3RST    0x00000002
+#define RCC_APB1RSTR_TIM4RST    0x00000004
+
+#define  CRC_CR_RESET                        0x00000001
+
+struct CRC {
+  volatile uint32_t DR;
+  volatile uint8_t  IDR;
+  uint8_t   RESERVED0;
+  uint16_t  RESERVED1;
+  volatile uint32_t CR;
+};
+
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+static struct CRC *const CRC = (struct CRC *)CRC_BASE;
+
+
+struct ADC {
+  volatile uint32_t SR;
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t SMPR1;
+  volatile uint32_t SMPR2;
+  volatile uint32_t JOFR1;
+  volatile uint32_t JOFR2;
+  volatile uint32_t JOFR3;
+  volatile uint32_t JOFR4;
+  volatile uint32_t HTR;
+  volatile uint32_t LTR;
+  volatile uint32_t SQR1;
+  volatile uint32_t SQR2;
+  volatile uint32_t SQR3;
+  volatile uint32_t JSQR;
+  volatile uint32_t JDR1;
+  volatile uint32_t JDR2;
+  volatile uint32_t JDR3;
+  volatile uint32_t JDR4;
+  volatile uint32_t DR;
+};
+
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+
+static struct ADC *const ADC1 = (struct ADC *)ADC1_BASE;
+static struct ADC *const ADC2 = (struct ADC *)ADC2_BASE;
+
+#define  ADC_CR1_DUALMOD_0       0x00010000
+#define  ADC_CR1_DUALMOD_1       0x00020000
+#define  ADC_CR1_DUALMOD_2       0x00040000
+#define  ADC_CR1_DUALMOD_3       0x00080000
+
+#define  ADC_CR1_SCAN            0x00000100
+
+#define  ADC_CR2_ADON            0x00000001
+#define  ADC_CR2_CONT            0x00000002
+#define  ADC_CR2_CAL             0x00000004
+#define  ADC_CR2_RSTCAL          0x00000008
+#define  ADC_CR2_DMA             0x00000100
+#define  ADC_CR2_ALIGN           0x00000800
+#define  ADC_CR2_EXTSEL          0x000E0000
+#define  ADC_CR2_EXTSEL_0        0x00020000
+#define  ADC_CR2_EXTSEL_1        0x00040000
+#define  ADC_CR2_EXTSEL_2        0x00080000
+#define  ADC_CR2_EXTTRIG         0x00100000
+#define  ADC_CR2_SWSTART         0x00400000
+#define  ADC_CR2_TSVREFE         0x00800000
+
+struct DMA_Channel {
+  volatile uint32_t CCR;
+  volatile uint32_t CNDTR;
+  volatile uint32_t CPAR;
+  volatile uint32_t CMAR;
+};
+
+struct DMA {
+  volatile uint32_t ISR;
+  volatile uint32_t IFCR;
+};
+
+#define STM32_DMA_CR_MINC           DMA_CCR1_MINC
+#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR1_MSIZE_1
+#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR1_PSIZE_1
+#define STM32_DMA_CR_TCIE           DMA_CCR1_TCIE
+#define STM32_DMA_CR_TEIE           DMA_CCR1_TEIE
+#define STM32_DMA_CR_HTIE           DMA_CCR1_HTIE
+#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
+#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
+#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
+
+#define STM32_DMA_ISR_MASK          0x0F
+#define STM32_DMA_CCR_RESET_VALUE   0x00000000
+#define STM32_DMA_CR_PL_MASK        DMA_CCR1_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 12)
+
+#define  DMA_CCR1_EN                         0x00000001
+#define  DMA_CCR1_TCIE                       0x00000002
+#define  DMA_CCR1_HTIE                       0x00000004
+#define  DMA_CCR1_TEIE                       0x00000008
+#define  DMA_CCR1_DIR                        0x00000010
+#define  DMA_CCR1_CIRC                       0x00000020
+#define  DMA_CCR1_PINC                       0x00000040
+#define  DMA_CCR1_MINC                       0x00000080
+#define  DMA_CCR1_PSIZE                      0x00000300
+#define  DMA_CCR1_PSIZE_0                    0x00000100
+#define  DMA_CCR1_PSIZE_1                    0x00000200
+#define  DMA_CCR1_MSIZE                      0x00000C00
+#define  DMA_CCR1_MSIZE_0                    0x00000400
+#define  DMA_CCR1_MSIZE_1                    0x00000800
+#define  DMA_CCR1_PL                         0x00003000
+#define  DMA_CCR1_PL_0                       0x00001000
+#define  DMA_CCR1_PL_1                       0x00002000
+#define  DMA_CCR1_MEM2MEM                    0x00004000
+
+#define  DMA_ISR_GIF1                        0x00000001
+#define  DMA_ISR_TCIF1                       0x00000002
+#define  DMA_ISR_HTIF1                       0x00000004
+#define  DMA_ISR_TEIF1                       0x00000008
+#define  DMA_ISR_GIF2                        0x00000010
+#define  DMA_ISR_TCIF2                       0x00000020
+#define  DMA_ISR_HTIF2                       0x00000040
+#define  DMA_ISR_TEIF2                       0x00000080
+#define  DMA_ISR_GIF3                        0x00000100
+#define  DMA_ISR_TCIF3                       0x00000200
+#define  DMA_ISR_HTIF3                       0x00000400
+#define  DMA_ISR_TEIF3                       0x00000800
+#define  DMA_ISR_GIF4                        0x00001000
+#define  DMA_ISR_TCIF4                       0x00002000
+#define  DMA_ISR_HTIF4                       0x00004000
+#define  DMA_ISR_TEIF4                       0x00008000
+#define  DMA_ISR_GIF5                        0x00010000
+#define  DMA_ISR_TCIF5                       0x00020000
+#define  DMA_ISR_HTIF5                       0x00040000
+#define  DMA_ISR_TEIF5                       0x00080000
+#define  DMA_ISR_GIF6                        0x00100000
+#define  DMA_ISR_TCIF6                       0x00200000
+#define  DMA_ISR_HTIF6                       0x00400000
+#define  DMA_ISR_TEIF6                       0x00800000
+#define  DMA_ISR_GIF7                        0x01000000
+#define  DMA_ISR_TCIF7                       0x02000000
+#define  DMA_ISR_HTIF7                       0x04000000
+#define  DMA_ISR_TEIF7                       0x08000000
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
+static struct DMA *const DMA1 = (struct DMA *)DMA1_BASE;
+
+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
+static struct DMA_Channel *const DMA1_Channel1 =
+  (struct DMA_Channel *)DMA1_Channel1_BASE;
+
+/* System Control Block */
+struct SCB
+{
+  volatile uint32_t CPUID;
+  volatile uint32_t ICSR;
+  volatile uint32_t VTOR;
+  volatile uint32_t AIRCR;
+  volatile uint32_t SCR;
+  volatile uint32_t CCR;
+  volatile uint8_t  SHP[12];
+  volatile uint32_t SHCSR;
+  volatile uint32_t CFSR;
+  volatile uint32_t HFSR;
+  volatile uint32_t DFSR;
+  volatile uint32_t MMFAR;
+  volatile uint32_t BFAR;
+  volatile uint32_t AFSR;
+  volatile uint32_t PFR[2];
+  volatile uint32_t DFR;
+  volatile uint32_t ADR;
+  volatile uint32_t MMFR[4];
+  volatile uint32_t ISAR[5];
+  uint32_t RESERVED0[5];
+  volatile uint32_t CPACR;
+};
+
+#define SCS_BASE 0xE000E000
+#define SCB_BASE (SCS_BASE + 0x0D00)
+static struct SCB *const SCB = (struct SCB *)SCB_BASE;
+
+/* Timer */
+struct TIM
+{
+  volatile uint16_t CR1;   uint16_t  RESERVED0;
+  volatile uint16_t CR2;   uint16_t  RESERVED1;
+  volatile uint16_t SMCR;  uint16_t  RESERVED2;
+  volatile uint16_t DIER;  uint16_t  RESERVED3;
+  volatile uint16_t SR;    uint16_t  RESERVED4;
+  volatile uint16_t EGR;   uint16_t  RESERVED5;
+  volatile uint16_t CCMR1; uint16_t  RESERVED6;
+  volatile uint16_t CCMR2; uint16_t  RESERVED7;
+  volatile uint16_t CCER;  uint16_t  RESERVED8;
+  volatile uint16_t CNT;   uint16_t  RESERVED9;
+  volatile uint16_t PSC;   uint16_t  RESERVED10;
+  volatile uint16_t ARR;   uint16_t  RESERVED11;
+  volatile uint16_t RCR;   uint16_t  RESERVED12;
+  volatile uint16_t CCR1;  uint16_t  RESERVED13;
+  volatile uint16_t CCR2;  uint16_t  RESERVED14;
+  volatile uint16_t CCR3;  uint16_t  RESERVED15;
+  volatile uint16_t CCR4;  uint16_t  RESERVED16;
+  volatile uint16_t BDTR;  uint16_t  RESERVED17;
+  volatile uint16_t DCR;   uint16_t  RESERVED18;
+  volatile uint16_t DMAR;  uint16_t  RESERVED19;
+};
+
+#define TIM2_BASE 0x40000000
+#define TIM3_BASE 0x40000400
+#define TIM4_BASE 0x40000800
+static struct TIM *const TIM2 = (struct TIM *)TIM2_BASE;
+static struct TIM *const TIM3 = (struct TIM *)TIM3_BASE;
+static struct TIM *const TIM4 = (struct TIM *)TIM4_BASE;
+
+#define  TIM_CR1_CEN   	0x0001
+#define  TIM_CR1_UDIS  	0x0002
+#define  TIM_CR1_URS   	0x0004
+#define  TIM_CR1_OPM   	0x0008
+#define  TIM_CR1_DIR   	0x0010
+#define  TIM_CR1_CMS   	0x0060
+#define  TIM_CR1_CMS_0 	0x0020
+#define  TIM_CR1_CMS_1 	0x0040
+#define  TIM_CR1_ARPE  	0x0080
+#define  TIM_CR1_CKD   	0x0300
+#define  TIM_CR1_CKD_0 	0x0100
+#define  TIM_CR1_CKD_1 	0x0200
+
+#define  TIM_CR2_CCPC  	0x0001
+#define  TIM_CR2_CCUS  	0x0004
+#define  TIM_CR2_CCDS  	0x0008
+#define  TIM_CR2_MMS   	0x0070
+#define  TIM_CR2_MMS_0 	0x0010
+#define  TIM_CR2_MMS_1 	0x0020
+#define  TIM_CR2_MMS_2 	0x0040
+#define  TIM_CR2_TI1S  	0x0080
+#define  TIM_CR2_OIS1  	0x0100
+#define  TIM_CR2_OIS1N 	0x0200
+#define  TIM_CR2_OIS2  	0x0400
+#define  TIM_CR2_OIS2N 	0x0800
+#define  TIM_CR2_OIS3  	0x1000
+#define  TIM_CR2_OIS3N 	0x2000
+#define  TIM_CR2_OIS4  	0x4000
+
+#define  TIM_SMCR_SMS   0x0007
+#define  TIM_SMCR_SMS_0 0x0001
+#define  TIM_SMCR_SMS_1 0x0002
+#define  TIM_SMCR_SMS_2 0x0004
+#define  TIM_SMCR_TS    0x0070
+#define  TIM_SMCR_TS_0  0x0010
+#define  TIM_SMCR_TS_1  0x0020
+#define  TIM_SMCR_TS_2  0x0040
+#define  TIM_SMCR_MSM   0x0080
+
+#define  TIM_SMCR_ETF   0x0F00
+#define  TIM_SMCR_ETF_0 0x0100
+#define  TIM_SMCR_ETF_1 0x0200
+#define  TIM_SMCR_ETF_2 0x0400
+#define  TIM_SMCR_ETF_3 0x0800
+
+#define  TIM_SMCR_ETPS   0x3000
+#define  TIM_SMCR_ETPS_0 0x1000
+#define  TIM_SMCR_ETPS_1 0x2000
+
+#define  TIM_SMCR_ECE    0x4000
+#define  TIM_SMCR_ETP    0x8000
+
+#define  TIM_DIER_UIE    0x0001
+#define  TIM_DIER_CC1IE  0x0002
+#define  TIM_DIER_CC2IE  0x0004
+#define  TIM_DIER_CC3IE  0x0008
+#define  TIM_DIER_CC4IE  0x0010
+#define  TIM_DIER_COMIE  0x0020
+#define  TIM_DIER_TIE    0x0040
+#define  TIM_DIER_BIE    0x0080
+#define  TIM_DIER_UDE    0x0100
+#define  TIM_DIER_CC1DE  0x0200
+#define  TIM_DIER_CC2DE  0x0400
+#define  TIM_DIER_CC3DE  0x0800
+#define  TIM_DIER_CC4DE  0x1000
+#define  TIM_DIER_COMDE  0x2000
+#define  TIM_DIER_TDE    0x4000
+
+#define  TIM_SR_UIF      0x0001
+#define  TIM_SR_CC1IF    0x0002
+#define  TIM_SR_CC2IF    0x0004
+#define  TIM_SR_CC3IF    0x0008
+#define  TIM_SR_CC4IF    0x0010
+#define  TIM_SR_COMIF    0x0020
+#define  TIM_SR_TIF      0x0040
+#define  TIM_SR_BIF      0x0080
+#define  TIM_SR_CC1OF    0x0200
+#define  TIM_SR_CC2OF    0x0400
+#define  TIM_SR_CC3OF    0x0800
+#define  TIM_SR_CC4OF    0x1000
+
+#define  TIM_EGR_UG      0x01
+#define  TIM_EGR_CC1G    0x02
+#define  TIM_EGR_CC2G    0x04
+#define  TIM_EGR_CC3G    0x08
+#define  TIM_EGR_CC4G    0x10
+#define  TIM_EGR_COMG    0x20
+#define  TIM_EGR_TG      0x40
+#define  TIM_EGR_BG      0x80
+
+#define  TIM_CCMR1_CC1S   0x0003
+#define  TIM_CCMR1_CC1S_0 0x0001
+#define  TIM_CCMR1_CC1S_1 0x0002
+
+#define  TIM_CCMR1_OC1FE  0x0004
+#define  TIM_CCMR1_OC1PE  0x0008
+
+#define  TIM_CCMR1_OC1M   0x0070
+#define  TIM_CCMR1_OC1M_0 0x0010
+#define  TIM_CCMR1_OC1M_1 0x0020
+#define  TIM_CCMR1_OC1M_2 0x0040
+
+#define  TIM_CCMR1_OC1CE  0x0080
+
+#define  TIM_CCMR1_CC2S   0x0300
+#define  TIM_CCMR1_CC2S_0 0x0100
+#define  TIM_CCMR1_CC2S_1 0x0200
+
+#define  TIM_CCMR1_OC2FE  0x0400
+#define  TIM_CCMR1_OC2PE  0x0800
+
+#define  TIM_CCMR1_OC2M   0x7000
+#define  TIM_CCMR1_OC2M_0 0x1000
+#define  TIM_CCMR1_OC2M_1 0x2000
+#define  TIM_CCMR1_OC2M_2 0x4000
+
+#define  TIM_CCMR1_OC2CE  0x8000
+
+
+#define  TIM_CCMR1_IC1PSC   0x000C
+#define  TIM_CCMR1_IC1PSC_0 0x0004
+#define  TIM_CCMR1_IC1PSC_1 0x0008
+
+#define  TIM_CCMR1_IC1F     0x00F0
+#define  TIM_CCMR1_IC1F_0   0x0010
+#define  TIM_CCMR1_IC1F_1   0x0020
+#define  TIM_CCMR1_IC1F_2   0x0040
+#define  TIM_CCMR1_IC1F_3   0x0080
+
+#define  TIM_CCMR1_IC2PSC   0x0C00
+#define  TIM_CCMR1_IC2PSC_0 0x0400
+#define  TIM_CCMR1_IC2PSC_1 0x0800
+
+#define  TIM_CCMR1_IC2F     0xF000
+#define  TIM_CCMR1_IC2F_0   0x1000
+#define  TIM_CCMR1_IC2F_1   0x2000
+#define  TIM_CCMR1_IC2F_2   0x4000
+#define  TIM_CCMR1_IC2F_3   0x8000
+
+#define  TIM_CCMR2_CC3S     0x0003
+#define  TIM_CCMR2_CC3S_0   0x0001
+#define  TIM_CCMR2_CC3S_1   0x0002
+
+#define  TIM_CCMR2_OC3FE    0x0004
+#define  TIM_CCMR2_OC3PE    0x0008
+
+#define  TIM_CCMR2_OC3M     0x0070
+#define  TIM_CCMR2_OC3M_0   0x0010
+#define  TIM_CCMR2_OC3M_1   0x0020
+#define  TIM_CCMR2_OC3M_2   0x0040
+
+#define  TIM_CCMR2_OC3CE    0x0080
+
+#define  TIM_CCMR2_CC4S     0x0300
+#define  TIM_CCMR2_CC4S_0   0x0100
+#define  TIM_CCMR2_CC4S_1   0x0200
+
+#define  TIM_CCMR2_OC4FE    0x0400
+#define  TIM_CCMR2_OC4PE    0x0800
+
+#define  TIM_CCMR2_OC4M     0x7000
+#define  TIM_CCMR2_OC4M_0   0x1000
+#define  TIM_CCMR2_OC4M_1   0x2000
+#define  TIM_CCMR2_OC4M_2   0x4000
+
+#define  TIM_CCMR2_OC4CE    0x8000
+
+
+#define  TIM_CCMR2_IC3PSC   0x000C
+#define  TIM_CCMR2_IC3PSC_0 0x0004
+#define  TIM_CCMR2_IC3PSC_1 0x0008
+
+#define  TIM_CCMR2_IC3F     0x00F0
+#define  TIM_CCMR2_IC3F_0   0x0010
+#define  TIM_CCMR2_IC3F_1   0x0020
+#define  TIM_CCMR2_IC3F_2   0x0040
+#define  TIM_CCMR2_IC3F_3   0x0080
+
+#define  TIM_CCMR2_IC4PSC   0x0C00
+#define  TIM_CCMR2_IC4PSC_0 0x0400
+#define  TIM_CCMR2_IC4PSC_1 0x0800
+
+#define  TIM_CCMR2_IC4F     0xF000
+#define  TIM_CCMR2_IC4F_0   0x1000
+#define  TIM_CCMR2_IC4F_1   0x2000
+#define  TIM_CCMR2_IC4F_2   0x4000
+#define  TIM_CCMR2_IC4F_3   0x8000
+
+#define  TIM_CCER_CC1E      0x0001
+#define  TIM_CCER_CC1P      0x0002
+#define  TIM_CCER_CC1NE     0x0004
+#define  TIM_CCER_CC1NP     0x0008
+#define  TIM_CCER_CC2E      0x0010
+#define  TIM_CCER_CC2P      0x0020
+#define  TIM_CCER_CC2NE     0x0040
+#define  TIM_CCER_CC2NP     0x0080
+#define  TIM_CCER_CC3E      0x0100
+#define  TIM_CCER_CC3P      0x0200
+#define  TIM_CCER_CC3NE     0x0400
+#define  TIM_CCER_CC3NP     0x0800
+#define  TIM_CCER_CC4E      0x1000
+#define  TIM_CCER_CC4P      0x2000
+
+#define  TIM_CNT_CNT        0xFFFF
+
+#define  TIM_PSC_PSC        0xFFFF
+
+#define  TIM_ARR_ARR        0xFFFF
+
+#define  TIM_RCR_REP        0xFF
+
+#define  TIM_CCR1_CCR1      0xFFFF
+#define  TIM_CCR2_CCR2      0xFFFF
+#define  TIM_CCR3_CCR3      0xFFFF
+#define  TIM_CCR4_CCR4      0xFFFF
+
+#define  TIM_BDTR_DTG       0x00FF
+#define  TIM_BDTR_DTG_0     0x0001
+#define  TIM_BDTR_DTG_1     0x0002
+#define  TIM_BDTR_DTG_2     0x0004
+#define  TIM_BDTR_DTG_3     0x0008
+#define  TIM_BDTR_DTG_4     0x0010
+#define  TIM_BDTR_DTG_5     0x0020
+#define  TIM_BDTR_DTG_6     0x0040
+#define  TIM_BDTR_DTG_7     0x0080
+
+#define  TIM_BDTR_LOCK      0x0300
+#define  TIM_BDTR_LOCK_0    0x0100
+#define  TIM_BDTR_LOCK_1    0x0200
+
+#define  TIM_BDTR_OSSI      0x0400
+#define  TIM_BDTR_OSSR      0x0800
+#define  TIM_BDTR_BKE       0x1000
+#define  TIM_BDTR_BKP       0x2000
+#define  TIM_BDTR_AOE       0x4000
+#define  TIM_BDTR_MOE       0x8000
+
+#define  TIM_DCR_DBA        0x001F
+#define  TIM_DCR_DBA_0      0x0001
+#define  TIM_DCR_DBA_1      0x0002
+#define  TIM_DCR_DBA_2      0x0004
+#define  TIM_DCR_DBA_3      0x0008
+#define  TIM_DCR_DBA_4      0x0010
+
+#define  TIM_DCR_DBL        0x1F00
+#define  TIM_DCR_DBL_0      0x0100
+#define  TIM_DCR_DBL_1      0x0200
+#define  TIM_DCR_DBL_2      0x0400
+#define  TIM_DCR_DBL_3      0x0800
+#define  TIM_DCR_DBL_4      0x1000
+
+#define  TIM_DMAR_DMAB      0xFFFF
+
+struct EXTI
+{
+  volatile uint32_t IMR;
+  volatile uint32_t EMR;
+  volatile uint32_t RTSR;
+  volatile uint32_t FTSR;
+  volatile uint32_t SWIER;
+  volatile uint32_t PR;
+};
+
+#define EXTI_BASE 0x40010400
+static struct EXTI *const EXTI = (struct EXTI *)EXTI_BASE;
+
+#define  EXTI_IMR_MR0       0x00000001
+#define  EXTI_IMR_MR1       0x00000002
+#define  EXTI_IMR_MR2       0x00000004
+#define  EXTI_IMR_MR3       0x00000008
+#define  EXTI_IMR_MR4       0x00000010
+#define  EXTI_IMR_MR5       0x00000020
+#define  EXTI_IMR_MR6       0x00000040
+#define  EXTI_IMR_MR7       0x00000080
+#define  EXTI_IMR_MR8       0x00000100
+#define  EXTI_IMR_MR9       0x00000200
+#define  EXTI_IMR_MR10      0x00000400
+#define  EXTI_IMR_MR11      0x00000800
+#define  EXTI_IMR_MR12      0x00001000
+#define  EXTI_IMR_MR13      0x00002000
+#define  EXTI_IMR_MR14      0x00004000
+#define  EXTI_IMR_MR15      0x00008000
+#define  EXTI_IMR_MR16      0x00010000
+#define  EXTI_IMR_MR17      0x00020000
+#define  EXTI_IMR_MR18      0x00040000
+#define  EXTI_IMR_MR19      0x00080000
+
+#define  EXTI_EMR_MR0       0x00000001
+#define  EXTI_EMR_MR1       0x00000002
+#define  EXTI_EMR_MR2       0x00000004
+#define  EXTI_EMR_MR3       0x00000008
+#define  EXTI_EMR_MR4       0x00000010
+#define  EXTI_EMR_MR5       0x00000020
+#define  EXTI_EMR_MR6       0x00000040
+#define  EXTI_EMR_MR7       0x00000080
+#define  EXTI_EMR_MR8       0x00000100
+#define  EXTI_EMR_MR9       0x00000200
+#define  EXTI_EMR_MR10      0x00000400
+#define  EXTI_EMR_MR11      0x00000800
+#define  EXTI_EMR_MR12      0x00001000
+#define  EXTI_EMR_MR13      0x00002000
+#define  EXTI_EMR_MR14      0x00004000
+#define  EXTI_EMR_MR15      0x00008000
+#define  EXTI_EMR_MR16      0x00010000
+#define  EXTI_EMR_MR17      0x00020000
+#define  EXTI_EMR_MR18      0x00040000
+#define  EXTI_EMR_MR19      0x00080000
+
+#define  EXTI_RTSR_TR0      0x00000001
+#define  EXTI_RTSR_TR1      0x00000002
+#define  EXTI_RTSR_TR2      0x00000004
+#define  EXTI_RTSR_TR3      0x00000008
+#define  EXTI_RTSR_TR4      0x00000010
+#define  EXTI_RTSR_TR5      0x00000020
+#define  EXTI_RTSR_TR6      0x00000040
+#define  EXTI_RTSR_TR7      0x00000080
+#define  EXTI_RTSR_TR8      0x00000100
+#define  EXTI_RTSR_TR9      0x00000200
+#define  EXTI_RTSR_TR10     0x00000400
+#define  EXTI_RTSR_TR11     0x00000800
+#define  EXTI_RTSR_TR12     0x00001000
+#define  EXTI_RTSR_TR13     0x00002000
+#define  EXTI_RTSR_TR14     0x00004000
+#define  EXTI_RTSR_TR15     0x00008000
+#define  EXTI_RTSR_TR16     0x00010000
+#define  EXTI_RTSR_TR17     0x00020000
+#define  EXTI_RTSR_TR18     0x00040000
+#define  EXTI_RTSR_TR19     0x00080000
+
+#define  EXTI_FTSR_TR0      0x00000001
+#define  EXTI_FTSR_TR1      0x00000002
+#define  EXTI_FTSR_TR2      0x00000004
+#define  EXTI_FTSR_TR3      0x00000008
+#define  EXTI_FTSR_TR4      0x00000010
+#define  EXTI_FTSR_TR5      0x00000020
+#define  EXTI_FTSR_TR6      0x00000040
+#define  EXTI_FTSR_TR7      0x00000080
+#define  EXTI_FTSR_TR8      0x00000100
+#define  EXTI_FTSR_TR9      0x00000200
+#define  EXTI_FTSR_TR10     0x00000400
+#define  EXTI_FTSR_TR11     0x00000800
+#define  EXTI_FTSR_TR12     0x00001000
+#define  EXTI_FTSR_TR13     0x00002000
+#define  EXTI_FTSR_TR14     0x00004000
+#define  EXTI_FTSR_TR15     0x00008000
+#define  EXTI_FTSR_TR16     0x00010000
+#define  EXTI_FTSR_TR17     0x00020000
+#define  EXTI_FTSR_TR18     0x00040000
+#define  EXTI_FTSR_TR19     0x00080000
+
+#define  EXTI_SWIER_SWIER0  0x00000001
+#define  EXTI_SWIER_SWIER1  0x00000002
+#define  EXTI_SWIER_SWIER2  0x00000004
+#define  EXTI_SWIER_SWIER3  0x00000008
+#define  EXTI_SWIER_SWIER4  0x00000010
+#define  EXTI_SWIER_SWIER5  0x00000020
+#define  EXTI_SWIER_SWIER6  0x00000040
+#define  EXTI_SWIER_SWIER7  0x00000080
+#define  EXTI_SWIER_SWIER8  0x00000100
+#define  EXTI_SWIER_SWIER9  0x00000200
+#define  EXTI_SWIER_SWIER10 0x00000400
+#define  EXTI_SWIER_SWIER11 0x00000800
+#define  EXTI_SWIER_SWIER12 0x00001000
+#define  EXTI_SWIER_SWIER13 0x00002000
+#define  EXTI_SWIER_SWIER14 0x00004000
+#define  EXTI_SWIER_SWIER15 0x00008000
+#define  EXTI_SWIER_SWIER16 0x00010000
+#define  EXTI_SWIER_SWIER17 0x00020000
+#define  EXTI_SWIER_SWIER18 0x00040000
+#define  EXTI_SWIER_SWIER19 0x00080000
+
+#define  EXTI_PR_PR0        0x00000001
+#define  EXTI_PR_PR1        0x00000002
+#define  EXTI_PR_PR2        0x00000004
+#define  EXTI_PR_PR3        0x00000008
+#define  EXTI_PR_PR4        0x00000010
+#define  EXTI_PR_PR5        0x00000020
+#define  EXTI_PR_PR6        0x00000040
+#define  EXTI_PR_PR7        0x00000080
+#define  EXTI_PR_PR8        0x00000100
+#define  EXTI_PR_PR9        0x00000200
+#define  EXTI_PR_PR10       0x00000400
+#define  EXTI_PR_PR11       0x00000800
+#define  EXTI_PR_PR12       0x00001000
+#define  EXTI_PR_PR13       0x00002000
+#define  EXTI_PR_PR14       0x00004000
+#define  EXTI_PR_PR15       0x00008000
+#define  EXTI_PR_PR16       0x00010000
+#define  EXTI_PR_PR17       0x00020000
+#define  EXTI_PR_PR18       0x00040000
+#define  EXTI_PR_PR19       0x00080000
+
+#define EXTI0_IRQ    6
+#define EXTI1_IRQ    7
+#define EXTI2_IRQ    8
+#define EXTI9_5_IRQ 23
+#define TIM2_IRQ    28
+#define TIM3_IRQ    29
+#define TIM4_IRQ    30
+
+struct AFIO
+{
+  volatile uint32_t EVCR;
+  volatile uint32_t MAPR;
+  volatile uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  volatile uint32_t MAPR2;
+};
+
+#define AFIO_BASE 0x40010000
+static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE;
+
+#define AFIO_EXTICR1_EXTI0_PA 0x0000
+#define AFIO_EXTICR1_EXTI0_PB 0x0001
+#define AFIO_EXTICR1_EXTI0_PC 0x0002
+#define AFIO_EXTICR1_EXTI0_PD 0x0003
+
+#define AFIO_EXTICR1_EXTI1_PA 0x0000
+#define AFIO_EXTICR1_EXTI1_PB 0x0010
+#define AFIO_EXTICR1_EXTI1_PC 0x0020
+#define AFIO_EXTICR1_EXTI1_PD 0x0030
+
+#define AFIO_EXTICR1_EXTI2_PA 0x0000
+#define AFIO_EXTICR1_EXTI2_PB 0x0100
+#define AFIO_EXTICR1_EXTI2_PC 0x0200
+#define AFIO_EXTICR1_EXTI2_PD 0x0300
+
+#define AFIO_EXTICR1_EXTI3_PA 0x0000
+#define AFIO_EXTICR1_EXTI3_PB 0x1000
+#define AFIO_EXTICR1_EXTI3_PC 0x2000
+#define AFIO_EXTICR1_EXTI3_PD 0x3000
+
+#define AFIO_EXTICR2_EXTI4_PA 0x0000
+#define AFIO_EXTICR2_EXTI4_PB 0x0001
+#define AFIO_EXTICR2_EXTI4_PC 0x0002
+#define AFIO_EXTICR2_EXTI4_PD 0x0003
+
+#define AFIO_EXTICR2_EXTI5_PA 0x0000
+#define AFIO_EXTICR2_EXTI5_PB 0x0010
+#define AFIO_EXTICR2_EXTI5_PC 0x0020
+#define AFIO_EXTICR2_EXTI5_PD 0x0030
+
+#define AFIO_EXTICR2_EXTI6_PA 0x0000
+#define AFIO_EXTICR2_EXTI6_PB 0x0100
+#define AFIO_EXTICR2_EXTI6_PC 0x0200
+#define AFIO_EXTICR2_EXTI6_PD 0x0300
+
+#define AFIO_EXTICR2_EXTI7_PA 0x0000
+#define AFIO_EXTICR2_EXTI7_PB 0x1000
+#define AFIO_EXTICR2_EXTI7_PC 0x2000
+#define AFIO_EXTICR2_EXTI7_PD 0x3000
+
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
--- a/mcu/sys-mkl27z.c
+++ b/mcu/sys-mkl27z.c
@@ -0,0 +1,414 @@
+/*
+ * sys.c - First pages for MKL27Z256.
+ *
+ * Copyright (C) 2016 Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * Copying and distribution of this file, with or without modification,
+ * are permitted in any medium without royalty provided the copyright
+ * notice and this notice are preserved.  This file is offered as-is,
+ * without any warranty.
+ *
+ *
+ * First two pages of Flash ROM is difficult to use because of
+ * predefined purposes.  It's defined as a default vector page and
+ * a flash configuration page.
+ *
+ * We put something useful to those two pages, together with the
+ * data for predefined purposes.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "board.h"
+
+#define ADDR_VECTORS (0x00000900)
+#define ADDR_SCR_VTOR 0xe000ed08
+
+static void __attribute__ ((naked,section(".fixed_function.reset")))
+reset (void)
+{
+  uint32_t r3 = ADDR_SCR_VTOR;
+
+  asm volatile ("str	%2, [%0]\n\t"	  /* Set SCR->VTOR     */
+		"ldr	%0, [%2]\n\t"     /* Stack address     */
+		"msr	MSP, %0\n\t"	  /* Exception handler stack. */
+		"ldr	%0, [%2, #4]\n\t" /* The entry address */
+		"bx	%0\n\t"           /* Jump to the entry */
+		".align	2"
+		: "=r" (r3)
+		: "0" (r3), "r" (ADDR_VECTORS)
+		: "memory");
+
+  /* Never reach here. */
+}
+
+
+static uint32_t
+stack_entry[] __attribute__ ((section(".first_page.first_words"),used)) = {
+  /* Since MSP are soon modified in RESET, we put 0 here.  */
+  0,
+  (uint32_t)reset,
+};
+
+#include "mcu/clk_gpio_init-mkl27z.c"
+
+static void
+set_led (int on)
+{
+  if (on)
+    GPIOB->PCOR = (1 << 0); /* PTB0: Clear: Light on  */
+  else
+    GPIOB->PSOR = (1 << 0); /* PTB0: Set  : Light off */
+}
+
+/*
+ * Here comes other SYS routines and data.
+ */
+
+const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
+  3*2+2,	     /* bLength */
+  0x03,		     /* bDescriptorType = STRING_DESCRIPTOR */
+  /* sys version: "3.0" */
+  '3', 0, '.', 0, '0', 0,
+};
+
+static const uint8_t board_name_string[] = BOARD_NAME;
+
+const uint8_t __attribute__((section(".sys.board_info")))
+*const sys_board_name = board_name_string;
+
+const uint32_t __attribute__((section(".sys.board_info")))
+sys_board_id = BOARD_ID;
+
+typedef void (*handler)(void);
+
+handler sys_vector[] __attribute__ ((section(".sys.vectors"))) = {
+  clock_init,
+  gpio_init,
+  (handler)set_led,
+  NULL,
+};
+
+static uint32_t
+flash_config[] __attribute__ ((section(".flash_config"),used)) = {
+  0xffffffff, 0xffffffff, /* Comparison Key */
+  0xffffffff, /* Protection bytes */
+  0xffff3ffe, /* FSEC=0xfe, FOPT=0x3f */
+  /* FOPT=0x3f:
+   * BOOTSRC_SEL=00: Boot from flash
+   */
+  /* FSEC=0xfe:
+   * unsecure
+   */
+};
+
+
+/*
+ * Flash memory routine
+ */
+struct FTFA {
+  volatile uint8_t FSTAT;
+  volatile uint8_t FCNFG;
+  volatile uint8_t FSEC;
+  volatile uint8_t FOPT;
+  /* Note: addressing (3,2,1,0, 7,6,5,4, B,A,9,8) */
+  /* Use Bx macro. */
+  volatile uint8_t FCCO[12];
+  /* Note: addressing (3,2,1,0).  Use Bx macro.  */
+  volatile uint8_t FPROT[4];
+};
+static struct FTFA *const FTFA = (struct FTFA *)0x40020000;
+
+#define FSTAT_CCIF 0x80
+#define B3 0
+#define B2 1
+#define B1 2
+#define B0 3
+#define B7 4
+#define B6 5
+#define B5 6
+#define B4 7
+#define BB 8
+#define BA 9
+#define B9 10
+#define B8 11
+
+uint32_t __attribute__ ((naked,section(".fixed_function.flash_do_internal")))
+flash_do_internal (void)
+{
+#ifdef ORIGINAL_IN_C
+  uint8_t r;
+
+  asm volatile ("cpsid	i" : : : "memory");
+  FTFA->FSTAT |= FSTAT_CCIF;
+  while (((r = FTFA->FSTAT) & FSTAT_CCIF) == 0)
+    ;
+  r &= ~FSTAT_CCIF;
+  asm volatile ("cpsie	i" : : : "memory");
+
+  return (uint32_t)r;
+#else
+  register unsigned int r0 asm ("r0");
+  register unsigned int r1 asm ("r1") = (unsigned int)FTFA;
+  register unsigned int r2 asm ("r2") = FSTAT_CCIF;
+
+  asm volatile ("cpsid	i\n\t"
+		"ldrb	%0, [%1]\n\t"
+		"orr	%0, %2\n\t"
+		"strb	%0, [%1]\n"
+	"0:\t"
+		"ldrb	%0, [%1]\n\t"
+		"uxtb	%0, %0\n\t"
+		"tst	%0, %2\n\t"
+		"beq	0b\n\t"
+		"cpsie	i\n\t"
+		"bic	%0, %2\n\t"
+		"bx	lr"
+		: "=r" (r0)
+		: "r" (r1), "r" (r2)
+		: "memory");
+  return r0;
+#endif
+}
+
+/*
+ * Let execute flash command.
+ * Since the code should be on RAM, we copy the code onto stack
+ * and let it go.
+ */
+uint32_t __attribute__ ((naked,section(".fixed_function.flash_do")))
+flash_do (void)
+{
+  register unsigned int r0 asm ("r0");
+  register unsigned int r1 asm ("r1");
+  register unsigned int r2 asm ("r2");
+  register unsigned int r3 asm ("r3") = (unsigned int)flash_do_internal&~3;
+  /* Address of Thumb code &1 == 1, so, we clear the last bits.    ------^ */
+
+  asm volatile ("sub	sp, #32\n\t"
+		"mov	%1, sp\n\t"
+		"mov	%2, #0\n"
+	"0:\t"
+		"cmp	%2, #32\n\t"
+		"beq	1f\n\t"
+		"ldr	%0, [%3, %2]\n\t"
+		"str	%0, [%1, %2]\n\t"
+		"add	%2, #4\n\t"
+		"b	0b\n"
+	"1:\t"
+		"add	%1, #1\n\t" /* Thumb code requires LSB=1.  */
+		"mov	%3, lr\n\t"
+		"blx	%1\n\t"
+		"add	sp, #32\n\t"
+		"bx	%3"
+		: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
+		: "3" (r3));
+}
+
+#define FLASH_COMMAND_PROGRAM_LONGWORD   0x06
+#define FLASH_COMMAND_ERASE_FLASH_SECTOR 0x09
+
+int __attribute__ ((naked,section(".fixed_function.flash_erase_page")))
+flash_erase_page (uint32_t addr)
+{
+#ifdef ORIGINAL_IN_C
+  FTFA->FCCO[B0] = FLASH_COMMAND_ERASE_FLASH_SECTOR;
+  FTFA->FCCO[B3] = (addr >>  0) & 0xff;
+  FTFA->FCCO[B2] = (addr >>  8) & 0xff;
+  FTFA->FCCO[B1] = (addr >> 16) & 0xff;
+  flash_do ();
+#else
+  register unsigned int r0 asm ("r0") = addr;
+  register unsigned int r1 asm ("r1");
+  register unsigned int r2 asm ("r2") = FLASH_COMMAND_ERASE_FLASH_SECTOR;
+  register unsigned int r3 asm ("r3") = (unsigned int)FTFA;
+
+  asm volatile ("strb	%2, [%3, #7]\n\t"
+		"strb	%0, [%3, #4]\n\t"
+		"lsr	%0, #8\n\t"
+		"strb	%0, [%3, #5]\n\t"
+		"lsr	%0, #8\n\t"
+		"strb	%0, [%3, #6]\n\t"
+		"b	flash_do"
+		: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
+		: "0" (r0), "2" (r2), "3" (r3));
+#endif
+}
+
+int __attribute__ ((naked,section(".fixed_function.flash_program_word")))
+flash_program_word (uint32_t addr, uint32_t word)
+{
+#ifdef ORIGINAL_IN_C
+  FTFA->FCCO[B0] = FLASH_COMMAND_PROGRAM_LONGWORD;
+  FTFA->FCCO[B3] = (addr >>  0) & 0xff;
+  FTFA->FCCO[B2] = (addr >>  8) & 0xff;
+  FTFA->FCCO[B1] = (addr >> 16) & 0xff;
+  FTFA->FCCO[B4] = (word >>  0) & 0xff;
+  FTFA->FCCO[B5] = (word >>  8) & 0xff;
+  FTFA->FCCO[B6] = (word >> 16) & 0xff;
+  FTFA->FCCO[B7] = (word >> 24) & 0xff;
+  flash_do ();
+#else
+  register unsigned int r0 asm ("r0") = addr;
+  register unsigned int r1 asm ("r1") = word;
+  register unsigned int r2 asm ("r2") = FLASH_COMMAND_PROGRAM_LONGWORD;
+  register unsigned int r3 asm ("r3") = (unsigned int)FTFA;
+
+  asm volatile ("strb	%2, [%3, #7]\n\t"
+		"strb	%0, [%3, #4]\n\t"
+		"lsr	%0, #8\n\t"
+		"strb	%0, [%3, #5]\n\t"
+		"lsr	%0, #8\n\t"
+		"strb	%0, [%3, #6]\n\t"
+		"strb	%1, [%3, #11]\n\t"
+		"lsr	%1, #8\n\t"
+		"strb	%1, [%3, #10]\n\t"
+		"lsr	%1, #8\n\t"
+		"strb	%1, [%3, #9]\n\t"
+		"lsr	%1, #8\n\t"
+		"strb	%1, [%3, #8]\n\t"
+		"b	flash_do"
+		: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
+		: "0" (r0), "1" (r1), "2" (r2), "3" (r3));
+#endif
+}
+
+
+/*
+ * CRC32 calculation routines.
+ */
+void __attribute__ ((naked,section(".fixed_function.crc32_init")))
+crc32_init  (unsigned int *p)
+{
+#ifdef ORIGINAL_IN_C
+  *p = 0xffffffff;
+#else
+  register unsigned int r3 asm ("r3");
+
+  asm volatile ("mov	%0, #1\n\t"
+		"neg	%0, %0\n\t"
+		"str	%0, [%1]\n\t"
+		"bx	lr"
+		: "=r" (r3)
+		: "r" (p)
+		: "memory");
+#endif
+}
+
+#ifdef ORIGINAL_IN_C
+const unsigned int *const crc32_table= (const unsigned int *)0x00000500;
+#endif
+
+void __attribute__ ((naked,section(".fixed_function.crc32_u8")))
+crc32_u8 (unsigned int *p, unsigned char v)
+{
+#ifdef ORIGINAL_IN_C
+  *p = crc32_table[(*p & 0xff) ^ v] ^ (*p >> 8);
+#else
+  register unsigned int r2 asm ("r2");
+  register unsigned int r3 asm ("r3");
+
+  asm volatile ("ldrb	%2, [%4]\n\t"
+		"eor	%0, %2\n\t"
+		"mov	%2, #0xa0\n\t" /* (0x0500 >> 3) */
+		"lsl	%0, %0, #2\n\t"
+		"lsl	%2, %2, #3\n\t"
+		"add	%0, %0, %2\n\t"
+		"ldr	%2, [%4]\n\t"
+		"ldr	%1, [%0]\n\t"
+		"lsr	%2, %2, #8\n\t"
+		"eor	%2, %1\n\t"
+		"str	%2, [%4]\n\t"
+		"bx	lr"
+		: "=r" (v), "=r" (r2), "=r" (r3)
+		: "0" (v), "r" (p)
+		: "memory");
+#endif
+}
+
+void __attribute__ ((naked,section(".fixed_function.crc32_u32")))
+crc32_u32 (unsigned int *p, unsigned int u)
+{
+#ifdef ORIGINAL_IN_C
+  crc32_u8 (p, u & 0xff);
+  crc32_u8 (p, (u >> 8)& 0xff);
+  crc32_u8 (p, (u >> 16)& 0xff);
+  crc32_u8 (p, (u >> 24)& 0xff);
+#else
+  register unsigned int r3 asm ("r3");
+  register unsigned int r4 asm ("r4");
+  register unsigned int r5 asm ("r5");
+
+  asm volatile ("push	{%1, %2, %3, lr}\n\t"
+		"mov	%2, %0\n\t"
+		"mov	%3, %5\n\t"
+		"uxtb	%0, %0\n\t"
+		"bl	crc32_u8\n\t"
+		"lsr	%0, %2, #8\n\t"
+		"mov	%5, %3\n\t"
+		"uxtb	%0, %0\n\t"
+		"bl	crc32_u8\n\t"
+		"lsr	%0, %2, #16\n\t"
+		"mov	%5, %3\n\t"
+		"uxtb	%0, %0\n\t"
+		"bl	crc32_u8\n\t"
+		"mov	%5, %3\n\t"
+		"lsr	%0, %2, #24\n\t"
+		"bl	crc32_u8\n\t"
+		"pop	{%1, %2, %3, pc}"
+		: "=r" (u), "=r" (r3), "=r" (r4), "=r" (r5)
+		: "0" (u), "r" (p)
+		: "memory");
+#endif
+}
+
+/*
+ * Table of CRC32, generated by gen_crc_table.py
+ */
+const unsigned int
+crc32_table[256] __attribute__ ((section(".crc32_table"))) = {
+  0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 
+  0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 
+  0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, 
+  0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 
+  0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 
+  0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 
+  0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, 
+  0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 
+  0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 
+  0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 
+  0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, 
+  0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, 
+  0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 
+  0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 
+  0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, 
+  0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, 
+  0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 
+  0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 
+  0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 
+  0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, 
+  0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 
+  0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 
+  0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, 
+  0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 
+  0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 
+  0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 
+  0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, 
+  0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 
+  0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 
+  0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 
+  0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, 
+  0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, 
+  0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 
+  0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 
+  0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, 
+  0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, 
+  0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 
+  0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 
+  0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 
+  0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, 
+  0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 
+  0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 
+  0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
--- a/mcu/sys-mkl27z.h
+++ b/mcu/sys-mkl27z.h
@@ -0,0 +1,39 @@
+extern const uint8_t sys_version[8];
+#if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)
+extern const uint32_t sys_board_id;
+extern const char *const sys_board_name;
+#endif
+
+typedef void (*handler)(void);
+extern handler sys_vector[16];
+
+static inline void
+set_led (int on)
+{
+  void (*func) (int) = (void (*)(int))sys_vector[2];
+
+  return (*func) (on);
+}
+
+void crc32_init (unsigned int *);
+void crc32_u8 (unsigned int *, unsigned char);
+void crc32_u32 (unsigned int *, unsigned int);
+
+int flash_erase_page (uint32_t addr);
+int flash_program_word (uint32_t addr, uint32_t word);
+
+#ifdef REQUIRE_CLOCK_GPIO_SETTING_IN_SYS
+/* Provide the function entries.  */
+
+static void __attribute__ ((used))
+clock_init (void)
+{
+  (*sys_vector[0]) ();
+}
+
+static void __attribute__ ((used))
+gpio_init (void)
+{
+  (*sys_vector[1]) ();
+}
+#endif
--- a/mcu/sys-stm32f0.c
+++ b/mcu/sys-stm32f0.c
@@ -1,7 +1,7 @@
 /*
- * sys.c - system routines for the initial page for STM32F103.
+ * sys.c - system routines for the initial page for STM32F030 / STM32F103.
 *
- * Copyright (C) 2013 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015, 2016 Flying Stone Technology
 * Author: NIIBE Yutaka <gniibe@fsij.org>
 *
 * Copying and distribution of this file, with or without modification,
@@ -17,222 +17,9 @@
 #include <stdlib.h>
 #include "board.h"

+#define STM32F0_USE_VECTOR_ON_RAM
+#include "mcu/clk_gpio_init-stm32.c"

-#define CORTEX_PRIORITY_BITS    4
-#define CORTEX_PRIORITY_MASK(n)  ((n) << (8 - CORTEX_PRIORITY_BITS))
-#define USB_LP_CAN1_RX0_IRQn	 20
-#define STM32_USB_IRQ_PRIORITY   11
-
-
-#define STM32_SW_PLL		(2 << 0)
-#define STM32_PLLSRC_HSE	(1 << 16)
-
-#define STM32_PLLXTPRE_DIV1	(0 << 17)
-#define STM32_PLLXTPRE_DIV2	(1 << 17)
-
-#define STM32_HPRE_DIV1		(0 << 4)
-
-#define STM32_PPRE1_DIV2	(4 << 8)
-
-#define STM32_PPRE2_DIV1        (0 << 11)
-#define STM32_PPRE2_DIV2	(4 << 11)
-
-#define STM32_ADCPRE_DIV4	(1 << 14)
-#define STM32_ADCPRE_DIV6       (2 << 14)
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)
-
-#define STM32_MCO_NOCLOCK	(0 << 24)
-
-#define STM32_SW		STM32_SW_PLL
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_HPRE		STM32_HPRE_DIV1
-#define STM32_PPRE1		STM32_PPRE1_DIV2
-#define STM32_PPRE2		STM32_PPRE2_DIV1
-#define STM32_ADCPRE		STM32_ADCPRE_DIV6
-#define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
-
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
-#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK		STM32_PLLCLKOUT
-#define STM32_HCLK		(STM32_SYSCLK / 1)
-
-#define STM32_FLASHBITS		0x00000012
-
-struct NVIC {
-  uint32_t ISER[8];
-  uint32_t unused1[24];
-  uint32_t ICER[8];
-  uint32_t unused2[24];
-  uint32_t ISPR[8];
-  uint32_t unused3[24];
-  uint32_t ICPR[8];
-  uint32_t unused4[24];
-  uint32_t IABR[8];
-  uint32_t unused5[56];
-  uint32_t IPR[60];
-};
-
-static struct NVIC *const NVICBase = ((struct NVIC *const)0xE000E100);
-#define NVIC_ISER(n)	(NVICBase->ISER[n >> 5])
-#define NVIC_ICPR(n)	(NVICBase->ICPR[n >> 5])
-#define NVIC_IPR(n)	(NVICBase->IPR[n >> 2])
-
-static void
-nvic_enable_vector (uint32_t n, uint32_t prio)
-{
-  unsigned int sh = (n & 3) << 3;
-
-  NVIC_IPR (n) = (NVIC_IPR(n) & ~(0xFF << sh)) | (prio << sh);
-  NVIC_ICPR (n) = 1 << (n & 0x1F);
-  NVIC_ISER (n) = 1 << (n & 0x1F);
-}
-
-
-#define PERIPH_BASE	0x40000000
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN	0x00800000
-#define RCC_APB1RSTR_USBRST	0x00800000
-
-#define RCC_CR_HSION		0x00000001
-#define RCC_CR_HSIRDY		0x00000002
-#define RCC_CR_HSITRIM		0x000000F8
-#define RCC_CR_HSEON		0x00010000
-#define RCC_CR_HSERDY		0x00020000
-#define RCC_CR_PLLON		0x01000000
-#define RCC_CR_PLLRDY		0x02000000
-
-#define RCC_CFGR_SWS		0x0000000C
-#define RCC_CFGR_SWS_HSI	0x00000000
-
-#define RCC_AHBENR_CRCEN        0x0040
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void
-clock_init (void)
-{
-  /* HSI setup */
-  RCC->CR |= RCC_CR_HSION;
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
-  RCC->CFGR = 0;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;
-
-  /* HSE setup */
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;
-
-  /* PLL setup */
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-
-  /* Clock settings */
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
-    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /* Flash setup */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* CRC */
-  RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
-  /* Switching on the configured clock source. */
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-}
-
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-
-static void
-gpio_init (void)
-{
-  /* Enable GPIO clock. */
-  RCC->APB2ENR |= RCC_APB2ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
-  RCC->APB2RSTR = 0;
-
-  GPIO_USB->ODR = VAL_GPIO_ODR;
-  GPIO_USB->CRH = VAL_GPIO_CRH;
-  GPIO_USB->CRL = VAL_GPIO_CRL;
-
-#if GPIO_USB_BASE != GPIO_LED_BASE
-  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
-  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
-  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-#endif
-}

 static void
 usb_cable_config (int enable)
@@ -276,8 +63,6 @@ static void wait (int count)
    asm volatile ("" : : "r" (i) : "memory");
 }

-#define USB_IRQ 20
-#define USB_IRQ_PRIORITY ((11) << 4)

 static void
 usb_lld_sys_shutdown (void)
@@ -301,13 +86,6 @@ usb_lld_sys_init (void)

  usb_cable_config (1);
  RCC->APB1ENR |= RCC_APB1ENR_USBEN;
-  nvic_enable_vector (USB_LP_CAN1_RX0_IRQn,
-		      CORTEX_PRIORITY_MASK (STM32_USB_IRQ_PRIORITY));
-  /*
-   * Note that we also have other IRQ(s):
-   * 	USB_HP_CAN1_TX_IRQn (for double-buffered or isochronous)
-   * 	USBWakeUp_IRQn (suspend/resume)
-   */
  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
  RCC->APB1RSTR = 0;
 }
@@ -426,16 +204,25 @@ flash_check_blank (const uint8_t *p_start, size_t size)
  return 1;
 }

-extern uint8_t __flash_start__, __flash_end__;
+#define FLASH_START_ADDR 0x08000000 /* Fixed for all STM32F0/F1.  */
+#define FLASH_OFFSET     0x1000     /* First pages are not-writable
+				       when protected.  */
+#if defined(__ARM_ARCH_6M__)
+#define FLASH_SIZE_REG   ((uint16_t *)0x1ffff7cc)
+#define CHIP_ID_REG      ((uint32_t *)0x40015800)
+#else
+#define FLASH_SIZE_REG   ((uint16_t *)0x1ffff7e0)
+#define CHIP_ID_REG      ((uint32_t *)0xe0042000)
+#endif
+#define FLASH_START      (FLASH_START_ADDR+FLASH_OFFSET)

 static int
 flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
 {
  int status;
-  uint32_t flash_start = (uint32_t)&__flash_start__;
-  uint32_t flash_end = (uint32_t)&__flash_end__;
+  uint32_t flash_end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;

-  if (dst_addr < flash_start || dst_addr + len > flash_end)
+  if (dst_addr < FLASH_START || dst_addr + len > flash_end)
    return 0;

  while (len)
@@ -488,17 +275,21 @@ flash_protect (void)
 static void __attribute__((naked))
 flash_erase_all_and_exec (void (*entry)(void))
 {
-  uint32_t addr = (uint32_t)&__flash_start__;
-  uint32_t end = (uint32_t)&__flash_end__;
+  uint32_t addr = FLASH_START;
+  uint32_t end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
+  uint32_t page_size = 1024;
  int r;

+  if (((*CHIP_ID_REG) & 0xfff) == 0x0414)
+    page_size = 2048;
+
  while (addr < end)
    {
      r = flash_erase_page (addr);
      if (r != 0)
 	break;

-      addr += FLASH_PAGE_SIZE;
+      addr += page_size;
    }

  if (addr >= end)
@@ -532,7 +323,7 @@ struct SCB

 #define SCS_BASE	(0xE000E000)
 #define SCB_BASE	(SCS_BASE +  0x0D00)
-static struct SCB *const SCB = ((struct SCB *const) SCB_BASE);
+static struct SCB *const SCB = (struct SCB *)SCB_BASE;

 #define SYSRESETREQ 0x04
 static void
@@ -546,11 +337,35 @@ nvic_system_reset (void)
 static void __attribute__ ((naked))
 reset (void)
 {
-  extern const unsigned long *FT0, *FT1, *FT2;
-
+  /*
+   * This code may not be at the start of flash ROM, because of DFU.
+   * So, we take the address from PC.
+   */
+#if defined(__ARM_ARCH_6M__)
  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
-		"mov.w	r0, #0xed00\n\t" /* r0 = SCR */
-		"movt	r0, #0xe000\n\t"
+		"ldr	r0, 1f\n\t"     /* r0 = RAM start */
+		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
+		"mov	r2, #0x10\n\t"
+		"lsl	r2, #8\n\t"
+		"add	r1, r1, r2\n\t"
+		"sub	r2, r2, #1\n\t"
+		"bic	r1, r1, r2\n\t"
+		"mov	r2, #188\n"
+	"2:\n\t" /* Copy vectors.  It will be enabled later by clock_init.  */
+		"ldr	r3, [r1, r2]\n\t"
+		"str	r3, [r0, r2]\n\t"
+		"sub	r2, #4\n\t"
+		"bcs	2b\n\t"
+		"msr	MSP, r3\n\t"	/* Main (exception handler) stack. */
+		"ldr	r0, [r1, #4]\n\t" /* Reset handler.                */
+		"bx	r0\n\t"
+		".align	2\n"
+	"1:	.word	0x20000000"
+		: /* no output */ : /* no input */ : "memory");
+#else
+  extern const uint32_t FT0[256], FT1[256], FT2[256];
+  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
+		"ldr	r0, 1f\n\t"     /* r0 = SCR */
 		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
 		"mov	r2, #0x1000\n\t"
 		"add	r1, r1, r2\n\t"
@@ -560,13 +375,15 @@ reset (void)
 		"ldr	r0, [r1], #4\n\t"
 		"msr	MSP, r0\n\t"	/* Main (exception handler) stack. */
 		"ldr	r0, [r1]\n\t"	/* Reset handler.                  */
-		"bx	r0\n"
+		"bx	r0\n\t"
+		".align	2\n"
+	"1:	.word	0xe000ed00"
 		: /* no output */ : /* no input */ : "memory");
-
-  /* Never reach here. */
  /* Artificial entry to refer FT0, FT1, and FT2.  */
  asm volatile (""
 		: : "r" (FT0), "r" (FT1), "r" (FT2));
+#endif
+  /* Never reach here. */
 }

 typedef void (*handler)(void);
@@ -593,7 +410,13 @@ handler vector[] __attribute__ ((section(".vectors"))) = {

 const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
  3*2+2,	     /* bLength */
-  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
-  /* sys version: "2.0" */
-  '2', 0, '.', 0, '0', 0,
+  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
+  /* sys version: "3.0" */
+  '3', 0, '.', 0, '0', 0,
 };
+
+const uint32_t __attribute__((section(".sys.board_id")))
+sys_board_id = BOARD_ID;
+
+const uint8_t __attribute__((section(".sys.board_name")))
+sys_board_name[] = BOARD_NAME;
--- a/mcu/sys-stm32f0.h
+++ b/mcu/sys-stm32f0.h
@@ -1,4 +1,27 @@
+#if defined(__ARM_ARCH_6M__)
+#define BOARD_ID_STM32F0_DISCOVERY 0xde4b4bc1
+#define BOARD_ID_FSM_55            0x83433c76
+#else
+#define BOARD_ID_CQ_STARM          0xc5480875
+#define BOARD_ID_FST_01_00         0x613870a9
+#define BOARD_ID_FST_01            0x696886af
+#define BOARD_ID_MAPLE_MINI        0x7a445272
+#define BOARD_ID_OLIMEX_STM32_H103 0xf92bb594
+#define BOARD_ID_STBEE_MINI        0x1f341961
+#define BOARD_ID_STBEE             0x945c37e8
+#define BOARD_ID_STM32_PRIMER2     0x21e5798d
+#define BOARD_ID_STM8S_DISCOVERY   0x2f0976bb
+#define BOARD_ID_ST_DONGLE         0x2cd4e471
+#define BOARD_ID_ST_NUCLEO_F103    0x9b87c16d
+#endif
+
 extern const uint8_t sys_version[8];
+#if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)
+extern const uint32_t sys_board_id;
+extern const uint8_t sys_board_name[];
+#else
+# define SYS_BOARD_ID BOARD_ID
+#endif

 typedef void (*handler)(void);
 extern handler vector[16];
@@ -94,22 +117,18 @@ nvic_system_reset (void)
  (*vector[12]) ();
 }

-/*
- * Users can override INLINE by 'attribute((used))' to have an
- * implementation defined.
- */
-#if !defined(INLINE)
-#define INLINE __inline__
-#endif
+#ifdef REQUIRE_CLOCK_GPIO_SETTING_IN_SYS
+/* Provide the function entries.  */

-static INLINE void
+static void __attribute__ ((used))
 clock_init (void)
 {
  (*vector[13]) ();
 }

-static INLINE void
+static void __attribute__ ((used))
 gpio_init (void)
 {
  (*vector[14]) ();
 }
+#endif
--- a/mcu/sys-stm32f103.c
+++ b/mcu/sys-stm32f103.c
@@ -0,0 +1,540 @@
+/*
+ * sys.c - system routines for the initial page for STM32F103.
+ *
+ * Copyright (C) 2013, 2014, 2015, 2016  Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * Copying and distribution of this file, with or without modification,
+ * are permitted in any medium without royalty provided the copyright
+ * notice and this notice are preserved.  This file is offered as-is,
+ * without any warranty.
+ *
+ * When the flash ROM is protected, we cannot modify the initial page.
+ * We put some system routines (which is useful for any program) here.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "board.h"
+
+#include "mcu/clk_gpio_init-stm32.c"
+
+
+static void
+usb_cable_config (int enable)
+{
+#if defined(GPIO_USB_SET_TO_ENABLE)
+  if (enable)
+    GPIO_USB->BSRR = (1 << GPIO_USB_SET_TO_ENABLE);
+  else
+    GPIO_USB->BRR = (1 << GPIO_USB_SET_TO_ENABLE);
+#elif defined(GPIO_USB_CLEAR_TO_ENABLE)
+  if (enable)
+    GPIO_USB->BRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
+  else
+    GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
+#else
+  (void)enable;
+#endif
+}
+
+void
+set_led (int on)
+{
+#if defined(GPIO_LED_CLEAR_TO_EMIT)
+  if (on)
+    GPIO_LED->BRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
+  else
+    GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
+#else
+  if (on)
+    GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT);
+  else
+    GPIO_LED->BRR = (1 << GPIO_LED_SET_TO_EMIT);
+#endif
+}
+
+static void wait (int count)
+{
+  int i;
+
+  for (i = 0; i < count; i++)
+    asm volatile ("" : : "r" (i) : "memory");
+}
+
+
+static void
+usb_lld_sys_shutdown (void)
+{
+  RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
+  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
+  usb_cable_config (0);
+}
+
+static void
+usb_lld_sys_init (void)
+{
+  if ((RCC->APB1ENR & RCC_APB1ENR_USBEN)
+      && (RCC->APB1RSTR & RCC_APB1RSTR_USBRST) == 0)
+    /* Make sure the device is disconnected, even after core reset.  */
+    {
+      usb_lld_sys_shutdown ();
+      /* Disconnect requires SE0 (>= 2.5uS).  */
+      wait (300);
+    }
+
+  usb_cable_config (1);
+  RCC->APB1ENR |= RCC_APB1ENR_USBEN;
+  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
+  RCC->APB1RSTR = 0;
+}
+
+#define FLASH_KEY1               0x45670123UL
+#define FLASH_KEY2               0xCDEF89ABUL
+
+enum flash_status
+{
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PG,
+  FLASH_ERROR_WRP,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+};
+
+static void __attribute__ ((used))
+flash_unlock (void)
+{
+  FLASH->KEYR = FLASH_KEY1;
+  FLASH->KEYR = FLASH_KEY2;
+}
+
+
+#define intr_disable()  asm volatile ("cpsid   i" : : : "memory")
+#define intr_enable()  asm volatile ("cpsie   i" : : : "memory")
+
+#define FLASH_SR_BSY		0x01
+#define FLASH_SR_PGERR		0x04
+#define FLASH_SR_WRPRTERR	0x10
+#define FLASH_SR_EOP		0x20
+
+#define FLASH_CR_PG	0x0001
+#define FLASH_CR_PER	0x0002
+#define FLASH_CR_MER	0x0004
+#define FLASH_CR_OPTPG	0x0010
+#define FLASH_CR_OPTER	0x0020
+#define FLASH_CR_STRT	0x0040
+#define FLASH_CR_LOCK	0x0080
+#define FLASH_CR_OPTWRE	0x0200
+#define FLASH_CR_ERRIE	0x0400
+#define FLASH_CR_EOPIE	0x1000
+
+static int
+flash_wait_for_last_operation (uint32_t timeout)
+{
+  int status;
+
+  do
+    {
+      status = FLASH->SR;
+      if (--timeout == 0)
+	break;
+    }
+  while ((status & FLASH_SR_BSY) != 0);
+
+  return status & (FLASH_SR_BSY|FLASH_SR_PGERR|FLASH_SR_WRPRTERR);
+}
+
+#define FLASH_PROGRAM_TIMEOUT 0x00010000
+#define FLASH_ERASE_TIMEOUT   0x01000000
+
+static int
+flash_program_halfword (uint32_t addr, uint16_t data)
+{
+  int status;
+
+  status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
+
+  intr_disable ();
+  if (status == 0)
+    {
+      FLASH->CR |= FLASH_CR_PG;
+
+      *(volatile uint16_t *)addr = data;
+
+      status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
+      FLASH->CR &= ~FLASH_CR_PG;
+    }
+  intr_enable ();
+
+  return status;
+}
+
+static int
+flash_erase_page (uint32_t addr)
+{
+  int status;
+
+  status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
+
+  intr_disable ();
+  if (status == 0)
+    {
+      FLASH->CR |= FLASH_CR_PER;
+      FLASH->AR = addr;
+      FLASH->CR |= FLASH_CR_STRT;
+
+      status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
+      FLASH->CR &= ~FLASH_CR_PER;
+    }
+  intr_enable ();
+
+  return status;
+}
+
+static int
+flash_check_blank (const uint8_t *p_start, size_t size)
+{
+  const uint8_t *p;
+
+  for (p = p_start; p < p_start + size; p++)
+    if (*p != 0xff)
+      return 0;
+
+  return 1;
+}
+
+#define FLASH_START_ADDR 0x08000000 /* Fixed for all STM32F1.  */
+#define FLASH_OFFSET     0x1000     /* First pages are not-writable.  */
+#define FLASH_START      (FLASH_START_ADDR+FLASH_OFFSET)
+#define CHIP_ID_REG      ((uint32_t *)0xe0042000)
+#define FLASH_SIZE_REG   ((uint16_t *)0x1ffff7e0)
+
+static int
+flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
+{
+  int status;
+  uint32_t flash_end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
+
+  if (dst_addr < FLASH_START || dst_addr + len > flash_end)
+    return 0;
+
+  while (len)
+    {
+      uint16_t hw = *src++;
+
+      hw |= (*src++ << 8);
+      status = flash_program_halfword (dst_addr, hw);
+      if (status != 0)
+	return 0;		/* error return */
+
+      dst_addr += 2;
+      len -= 2;
+    }
+
+  return 1;
+}
+
+#define OPTION_BYTES_ADDR 0x1ffff800
+
+static int
+flash_protect (void)
+{
+  int status;
+  uint32_t option_bytes_value;
+
+  status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
+
+  intr_disable ();
+  if (status == 0)
+    {
+      FLASH->OPTKEYR = FLASH_KEY1;
+      FLASH->OPTKEYR = FLASH_KEY2;
+
+      FLASH->CR |= FLASH_CR_OPTER;
+      FLASH->CR |= FLASH_CR_STRT;
+
+      status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
+      FLASH->CR &= ~FLASH_CR_OPTER;
+    }
+  intr_enable ();
+
+  if (status != 0)
+    return 0;
+
+  option_bytes_value = *(uint32_t *)OPTION_BYTES_ADDR;
+  return (option_bytes_value & 0xff) == 0xff ? 1 : 0;
+}
+
+static void __attribute__((naked))
+flash_erase_all_and_exec (void (*entry)(void))
+{
+  uint32_t addr = FLASH_START;
+  uint32_t end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
+  uint32_t page_size = 1024;
+  int r;
+
+  if (((*CHIP_ID_REG) & 0xfff) == 0x0414)
+    page_size = 2048;
+
+  while (addr < end)
+    {
+      r = flash_erase_page (addr);
+      if (r != 0)
+	break;
+
+      addr += page_size;
+    }
+
+  if (addr >= end)
+    (*entry) ();
+
+  for (;;);
+}
+
+struct SCB
+{
+  volatile uint32_t CPUID;
+  volatile uint32_t ICSR;
+  volatile uint32_t VTOR;
+  volatile uint32_t AIRCR;
+  volatile uint32_t SCR;
+  volatile uint32_t CCR;
+  volatile uint8_t  SHP[12];
+  volatile uint32_t SHCSR;
+  volatile uint32_t CFSR;
+  volatile uint32_t HFSR;
+  volatile uint32_t DFSR;
+  volatile uint32_t MMFAR;
+  volatile uint32_t BFAR;
+  volatile uint32_t AFSR;
+  volatile uint32_t PFR[2];
+  volatile uint32_t DFR;
+  volatile uint32_t ADR;
+  volatile uint32_t MMFR[4];
+  volatile uint32_t ISAR[5];
+};
+
+#define SCS_BASE	(0xE000E000)
+#define SCB_BASE	(SCS_BASE +  0x0D00)
+static struct SCB *const SCB = (struct SCB *)SCB_BASE;
+
+#define SYSRESETREQ 0x04
+static void
+nvic_system_reset (void)
+{
+  SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
+  asm volatile ("dsb");
+  for (;;);
+}
+
+static void __attribute__ ((naked))
+reset (void)
+{
+  extern const uint32_t FT0[256], FT1[256], FT2[256];
+
+  /*
+   * This code may not be at the start of flash ROM, because of DFU.
+   * So, we take the address from PC.
+   */
+  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
+		"ldr	r0, 1f\n\t"     /* r0 = SCR */
+		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
+		"mov	r2, #0x1000\n\t"
+		"add	r1, r1, r2\n\t"
+		"sub	r2, r2, #1\n\t"
+		"bic	r1, r1, r2\n\t"
+		"str	r1, [r0, #8]\n\t"	/* Set SCR->VCR */
+		"ldr	r0, [r1], #4\n\t"
+		"msr	MSP, r0\n\t"	/* Main (exception handler) stack. */
+		"ldr	r0, [r1]\n\t"	/* Reset handler.                  */
+		"bx	r0\n\t"
+		".align	2\n"
+	"1:	.word	0xe000ed00"
+		: /* no output */ : /* no input */ : "memory");
+
+  /* Never reach here. */
+  /* Artificial entry to refer FT0, FT1, and FT2.  */
+  asm volatile (""
+		: : "r" (FT0), "r" (FT1), "r" (FT2));
+}
+
+typedef void (*handler)(void);
+extern uint8_t __ram_end__;
+
+handler vector[] __attribute__ ((section(".vectors"))) = {
+  (handler)&__ram_end__,
+  reset,
+  (handler)set_led,
+  flash_unlock,
+  (handler)flash_program_halfword,
+  (handler)flash_erase_page,
+  (handler)flash_check_blank,
+  (handler)flash_write,
+  (handler)flash_protect,
+  (handler)flash_erase_all_and_exec,
+  usb_lld_sys_init,
+  usb_lld_sys_shutdown,
+  nvic_system_reset,
+  clock_init,
+  gpio_init,
+  NULL,
+};
+
+const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
+  3*2+2,	     /* bLength */
+  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
+  /* sys version: "3.0" */
+  '3', 0, '.', 0, '0', 0,
+};
+
+const uint32_t __attribute__((section(".sys.board_id")))
+sys_board_id = BOARD_ID;
+
+const uint8_t __attribute__((section(".sys.board_name")))
+sys_board_name[] = BOARD_NAME;
+
+/*
+ * aes-constant-ft.c - AES forward tables.
+ *
+ * We need something useful for the initial flash ROM page (4 Ki
+ * bytes), which cannot be modified after installation.  Even after
+ * upgrade of the firmware, it stays intact.
+ *
+ * We decide to put 3/4 of AES forward tables to fill 3 Ki bytes, as
+ * its useful and it won't change.
+ *
+ * The code was taken from aes.c of PolarSSL version 0.14, and then,
+ * modified to add section names.
+ *
+ * Since this is just a data, it wouldn't be copyright-able, but the
+ * original auther would claim so.  Thus, we put original copyright
+ * notice here.  It is highly likely that there will be no such a
+ * thing for copyright.  Nevertheless, we think that PolarSSL is good
+ * software to address here, and encourage people using it.
+ *
+ */
+
+#include <stdint.h>
+
+/*
+ * Original copyright notice is below:
+ */
+
+/*
+ *  FIPS-197 compliant AES implementation
+ *
+ *  Copyright (C) 2006-2010, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+/*
+ *  The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
+ *
+ *  http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
+ *  http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
+ */
+
+/*
+ * Forward tables
+ */
+#define FT \
+\
+    V(A5,63,63,C6), V(84,7C,7C,F8), V(99,77,77,EE), V(8D,7B,7B,F6), \
+    V(0D,F2,F2,FF), V(BD,6B,6B,D6), V(B1,6F,6F,DE), V(54,C5,C5,91), \
+    V(50,30,30,60), V(03,01,01,02), V(A9,67,67,CE), V(7D,2B,2B,56), \
+    V(19,FE,FE,E7), V(62,D7,D7,B5), V(E6,AB,AB,4D), V(9A,76,76,EC), \
+    V(45,CA,CA,8F), V(9D,82,82,1F), V(40,C9,C9,89), V(87,7D,7D,FA), \
+    V(15,FA,FA,EF), V(EB,59,59,B2), V(C9,47,47,8E), V(0B,F0,F0,FB), \
+    V(EC,AD,AD,41), V(67,D4,D4,B3), V(FD,A2,A2,5F), V(EA,AF,AF,45), \
+    V(BF,9C,9C,23), V(F7,A4,A4,53), V(96,72,72,E4), V(5B,C0,C0,9B), \
+    V(C2,B7,B7,75), V(1C,FD,FD,E1), V(AE,93,93,3D), V(6A,26,26,4C), \
+    V(5A,36,36,6C), V(41,3F,3F,7E), V(02,F7,F7,F5), V(4F,CC,CC,83), \
+    V(5C,34,34,68), V(F4,A5,A5,51), V(34,E5,E5,D1), V(08,F1,F1,F9), \
+    V(93,71,71,E2), V(73,D8,D8,AB), V(53,31,31,62), V(3F,15,15,2A), \
+    V(0C,04,04,08), V(52,C7,C7,95), V(65,23,23,46), V(5E,C3,C3,9D), \
+    V(28,18,18,30), V(A1,96,96,37), V(0F,05,05,0A), V(B5,9A,9A,2F), \
+    V(09,07,07,0E), V(36,12,12,24), V(9B,80,80,1B), V(3D,E2,E2,DF), \
+    V(26,EB,EB,CD), V(69,27,27,4E), V(CD,B2,B2,7F), V(9F,75,75,EA), \
+    V(1B,09,09,12), V(9E,83,83,1D), V(74,2C,2C,58), V(2E,1A,1A,34), \
+    V(2D,1B,1B,36), V(B2,6E,6E,DC), V(EE,5A,5A,B4), V(FB,A0,A0,5B), \
+    V(F6,52,52,A4), V(4D,3B,3B,76), V(61,D6,D6,B7), V(CE,B3,B3,7D), \
+    V(7B,29,29,52), V(3E,E3,E3,DD), V(71,2F,2F,5E), V(97,84,84,13), \
+    V(F5,53,53,A6), V(68,D1,D1,B9), V(00,00,00,00), V(2C,ED,ED,C1), \
+    V(60,20,20,40), V(1F,FC,FC,E3), V(C8,B1,B1,79), V(ED,5B,5B,B6), \
+    V(BE,6A,6A,D4), V(46,CB,CB,8D), V(D9,BE,BE,67), V(4B,39,39,72), \
+    V(DE,4A,4A,94), V(D4,4C,4C,98), V(E8,58,58,B0), V(4A,CF,CF,85), \
+    V(6B,D0,D0,BB), V(2A,EF,EF,C5), V(E5,AA,AA,4F), V(16,FB,FB,ED), \
+    V(C5,43,43,86), V(D7,4D,4D,9A), V(55,33,33,66), V(94,85,85,11), \
+    V(CF,45,45,8A), V(10,F9,F9,E9), V(06,02,02,04), V(81,7F,7F,FE), \
+    V(F0,50,50,A0), V(44,3C,3C,78), V(BA,9F,9F,25), V(E3,A8,A8,4B), \
+    V(F3,51,51,A2), V(FE,A3,A3,5D), V(C0,40,40,80), V(8A,8F,8F,05), \
+    V(AD,92,92,3F), V(BC,9D,9D,21), V(48,38,38,70), V(04,F5,F5,F1), \
+    V(DF,BC,BC,63), V(C1,B6,B6,77), V(75,DA,DA,AF), V(63,21,21,42), \
+    V(30,10,10,20), V(1A,FF,FF,E5), V(0E,F3,F3,FD), V(6D,D2,D2,BF), \
+    V(4C,CD,CD,81), V(14,0C,0C,18), V(35,13,13,26), V(2F,EC,EC,C3), \
+    V(E1,5F,5F,BE), V(A2,97,97,35), V(CC,44,44,88), V(39,17,17,2E), \
+    V(57,C4,C4,93), V(F2,A7,A7,55), V(82,7E,7E,FC), V(47,3D,3D,7A), \
+    V(AC,64,64,C8), V(E7,5D,5D,BA), V(2B,19,19,32), V(95,73,73,E6), \
+    V(A0,60,60,C0), V(98,81,81,19), V(D1,4F,4F,9E), V(7F,DC,DC,A3), \
+    V(66,22,22,44), V(7E,2A,2A,54), V(AB,90,90,3B), V(83,88,88,0B), \
+    V(CA,46,46,8C), V(29,EE,EE,C7), V(D3,B8,B8,6B), V(3C,14,14,28), \
+    V(79,DE,DE,A7), V(E2,5E,5E,BC), V(1D,0B,0B,16), V(76,DB,DB,AD), \
+    V(3B,E0,E0,DB), V(56,32,32,64), V(4E,3A,3A,74), V(1E,0A,0A,14), \
+    V(DB,49,49,92), V(0A,06,06,0C), V(6C,24,24,48), V(E4,5C,5C,B8), \
+    V(5D,C2,C2,9F), V(6E,D3,D3,BD), V(EF,AC,AC,43), V(A6,62,62,C4), \
+    V(A8,91,91,39), V(A4,95,95,31), V(37,E4,E4,D3), V(8B,79,79,F2), \
+    V(32,E7,E7,D5), V(43,C8,C8,8B), V(59,37,37,6E), V(B7,6D,6D,DA), \
+    V(8C,8D,8D,01), V(64,D5,D5,B1), V(D2,4E,4E,9C), V(E0,A9,A9,49), \
+    V(B4,6C,6C,D8), V(FA,56,56,AC), V(07,F4,F4,F3), V(25,EA,EA,CF), \
+    V(AF,65,65,CA), V(8E,7A,7A,F4), V(E9,AE,AE,47), V(18,08,08,10), \
+    V(D5,BA,BA,6F), V(88,78,78,F0), V(6F,25,25,4A), V(72,2E,2E,5C), \
+    V(24,1C,1C,38), V(F1,A6,A6,57), V(C7,B4,B4,73), V(51,C6,C6,97), \
+    V(23,E8,E8,CB), V(7C,DD,DD,A1), V(9C,74,74,E8), V(21,1F,1F,3E), \
+    V(DD,4B,4B,96), V(DC,BD,BD,61), V(86,8B,8B,0D), V(85,8A,8A,0F), \
+    V(90,70,70,E0), V(42,3E,3E,7C), V(C4,B5,B5,71), V(AA,66,66,CC), \
+    V(D8,48,48,90), V(05,03,03,06), V(01,F6,F6,F7), V(12,0E,0E,1C), \
+    V(A3,61,61,C2), V(5F,35,35,6A), V(F9,57,57,AE), V(D0,B9,B9,69), \
+    V(91,86,86,17), V(58,C1,C1,99), V(27,1D,1D,3A), V(B9,9E,9E,27), \
+    V(38,E1,E1,D9), V(13,F8,F8,EB), V(B3,98,98,2B), V(33,11,11,22), \
+    V(BB,69,69,D2), V(70,D9,D9,A9), V(89,8E,8E,07), V(A7,94,94,33), \
+    V(B6,9B,9B,2D), V(22,1E,1E,3C), V(92,87,87,15), V(20,E9,E9,C9), \
+    V(49,CE,CE,87), V(FF,55,55,AA), V(78,28,28,50), V(7A,DF,DF,A5), \
+    V(8F,8C,8C,03), V(F8,A1,A1,59), V(80,89,89,09), V(17,0D,0D,1A), \
+    V(DA,BF,BF,65), V(31,E6,E6,D7), V(C6,42,42,84), V(B8,68,68,D0), \
+    V(C3,41,41,82), V(B0,99,99,29), V(77,2D,2D,5A), V(11,0F,0F,1E), \
+    V(CB,B0,B0,7B), V(FC,54,54,A8), V(D6,BB,BB,6D), V(3A,16,16,2C)
+
+#define V(a,b,c,d) 0x##a##b##c##d
+const uint32_t FT0[256] __attribute__((section(".sys.0"))) = { FT };
+#undef V
+
+#define V(a,b,c,d) 0x##b##c##d##a
+const uint32_t FT1[256] __attribute__((section(".sys.1"))) = { FT };
+#undef V
+
+#define V(a,b,c,d) 0x##c##d##a##b
+const uint32_t FT2[256] __attribute__((section(".sys.2"))) = { FT };
+#undef V
+
+#ifdef ORIGINAL_IMPLEMENTATION 
+#define V(a,b,c,d) 0x##d##a##b##c
+const uint32_t FT3[256] = { FT };
+#undef V
+#endif
--- a/mcu/sys-stm32f103.h
+++ b/mcu/sys-stm32f103.h
@@ -1,4 +1,24 @@
+#define BOARD_ID_CQ_STARM          0xc5480875
+#define BOARD_ID_FST_01_00         0x613870a9
+#define BOARD_ID_FST_01            0x696886af
+#define BOARD_ID_MAPLE_MINI        0x7a445272
+#define BOARD_ID_OLIMEX_STM32_H103 0xf92bb594
+#define BOARD_ID_STBEE_MINI        0x1f341961
+#define BOARD_ID_STBEE             0x945c37e8
+#define BOARD_ID_STM32_PRIMER2     0x21e5798d
+#define BOARD_ID_STM8S_DISCOVERY   0x2f0976bb
+#define BOARD_ID_ST_DONGLE         0x2cd4e471
+#define BOARD_ID_ST_NUCLEO_F103    0x9b87c16d
+#define BOARD_ID_NITROKEY_START    0xad1e7ebd
+
 extern const uint8_t sys_version[8];
+#if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)
+extern const uint32_t sys_board_id;
+extern const uint8_t sys_board_name[];
+# define SYS_BOARD_ID sys_board_id
+#else
+# define SYS_BOARD_ID BOARD_ID
+#endif

 typedef void (*handler)(void);
 extern handler vector[16];
@@ -94,22 +114,18 @@ nvic_system_reset (void)
  (*vector[12]) ();
 }

-/*
- * Users can override INLINE by 'attribute((used))' to have an
- * implementation defined.
- */
-#if !defined(INLINE)
-#define INLINE __inline__
-#endif
+#ifdef REQUIRE_CLOCK_GPIO_SETTING_IN_SYS
+/* Provide the function entries.  */

-static INLINE void
+static void __attribute__ ((used))
 clock_init (void)
 {
  (*vector[13]) ();
 }

-static INLINE void
+static void __attribute__ ((used))
 gpio_init (void)
 {
  (*vector[14]) ();
 }
+#endif
--- a/mcu/usb-mkl27z.c
+++ b/mcu/usb-mkl27z.c
--- a/example-cdc/usb_stm32f103.c
+++ b/example-cdc/usb_stm32f103.c
--- a/rules.mk
+++ b/rules.mk
@@ -6,10 +6,24 @@ ifneq ($(USE_EVENTFLAG),)
 CSRC += $(CHOPSTX)/eventflag.c
 endif

+ifneq ($(USE_SYS),)
+CSRC += $(CHOPSTX)/mcu/sys-$(CHIP).c
+endif
+ifneq ($(USE_USB),)
+CSRC += $(CHOPSTX)/mcu/usb-$(CHIP).c
+endif
+ifneq ($(USE_ADC),)
+CSRC += $(CHOPSTX)/contrib/adc-$(CHIP).c
+endif
+
 INCDIR += $(CHOPSTX)

 BUILDDIR = build
 OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).bin
+ifneq ($(ENABLE_OUTPUT_HEX),)
+OUTFILES += $(BUILDDIR)/$(PROJECT).hex
+endif
+

 OPT += -ffunction-sections -fdata-sections -fno-common

@@ -49,6 +63,9 @@ $(OBJS) : $(BUILDDIR)/%.o : %.c Makefile
 %.bin: %.elf $(LDSCRIPT)
 	$(OBJCOPY) -O binary $< $@

+%.hex: %.elf $(LDSCRIPT)
+	$(OBJCOPY) -O ihex $< $@
+
 clean:
 	-rm -f -r .dep $(BUILDDIR)

--- a/sys.h
+++ b/sys.h
@@ -0,0 +1,7 @@
+#if  defined(MCU_KINETIS_L)
+#include "mcu/sys-mkl27z.h"
+#elif defined(MCU_STM32F0)
+#include "mcu/sys-stm32f0.h"
+#else
+#include "mcu/sys-stm32f103.h"
+#endif
--- a/usb_lld.h
+++ b/usb_lld.h
@@ -0,0 +1,164 @@
+#define STANDARD_ENDPOINT_DESC_SIZE             0x09
+
+/* endpoints enumeration */
+#define ENDP0       ((uint8_t)0)
+#define ENDP1       ((uint8_t)1)
+#define ENDP2       ((uint8_t)2)
+#define ENDP3       ((uint8_t)3)
+#define ENDP4       ((uint8_t)4)
+#define ENDP5       ((uint8_t)5)
+#define ENDP6       ((uint8_t)6)
+#define ENDP7       ((uint8_t)7)
+
+enum RECIPIENT_TYPE
+{
+  DEVICE_RECIPIENT = 0, /* Recipient device    */
+  INTERFACE_RECIPIENT,  /* Recipient interface */
+  ENDPOINT_RECIPIENT,   /* Recipient endpoint  */
+  OTHER_RECIPIENT
+};
+
+enum DESCRIPTOR_TYPE
+{
+  DEVICE_DESCRIPTOR = 1,
+  CONFIG_DESCRIPTOR,
+  STRING_DESCRIPTOR,
+  INTERFACE_DESCRIPTOR,
+  ENDPOINT_DESCRIPTOR
+};
+
+#define REQUEST_DIR       0x80  /* Mask to get request dir  */
+#define REQUEST_TYPE      0x60  /* Mask to get request type */
+#define STANDARD_REQUEST  0x00  /* Standard request         */
+#define CLASS_REQUEST     0x20  /* Class request            */
+#define VENDOR_REQUEST    0x40  /* Vendor request           */
+#define RECIPIENT         0x1F  /* Mask to get recipient    */
+
+#define USB_SETUP_SET(req) ((req & REQUEST_DIR) == 0)
+#define USB_SETUP_GET(req) ((req & REQUEST_DIR) != 0)
+
+struct device_req {
+  uint8_t type;
+  uint8_t request;
+  uint16_t value;
+  uint16_t index;
+  uint16_t len;
+};
+
+struct ctrl_data {
+  uint8_t *addr;
+  uint16_t len;
+  uint8_t require_zlp;
+};
+
+struct usb_dev {
+  uint8_t configuration;
+  uint8_t feature;
+  uint8_t state;
+  struct device_req dev_req;
+  struct ctrl_data ctrl_data;
+};
+
+enum {
+  USB_EVENT_OK=0,		/* Processed in lower layer.  */
+  /* Device reset and suspend.  */
+  USB_EVENT_DEVICE_RESET,
+  USB_EVENT_DEVICE_SUSPEND,
+  /* Device Requests (Control WRITE Transfer): Standard */
+  USB_EVENT_SET_CONFIGURATION,
+  USB_EVENT_SET_INTERFACE,
+  USB_EVENT_SET_FEATURE_DEVICE,
+  USB_EVENT_SET_FEATURE_ENDPOINT,
+  USB_EVENT_CLEAR_FEATURE_DEVICE,
+  USB_EVENT_CLEAR_FEATURE_ENDPOINT,
+  /* Device Requests (Control READ Transfer): Standard */
+  USB_EVENT_GET_STATUS_INTERFACE,
+  USB_EVENT_GET_DESCRIPTOR,
+  USB_EVENT_GET_INTERFACE,
+  /* Device Requests (Control READ/WRITE Transfer): Non-Standard */
+  USB_EVENT_CTRL_REQUEST,
+  USB_EVENT_CTRL_WRITE_FINISH,
+  /* Device addressed.  */
+  USB_EVENT_DEVICE_ADDRESSED,
+};
+
+enum DEVICE_STATE {
+  UNCONNECTED,
+  ATTACHED,
+  POWERED,
+  SUSPENDED,
+  ADDRESSED,
+  CONFIGURED
+};
+
+void usb_lld_init (struct usb_dev *dev, uint8_t feature);
+
+/*
+ * Return value is encoded integer:
+ *     event-no:    8-bit, 0 if TX/RX
+ *     tx/rx-flag:  1-bit, 0 if rx, 1 if tx
+ *     endpoint no: 7-bit
+ *     length:      16-bit
+ */
+#define USB_EVENT_TXRX(e) ((e >> 23) & 1)
+#define USB_EVENT_LEN(e) (e & 0xffff)
+#define USB_EVENT_ENDP(e) ((e >> 16) & 0x7f)
+#define USB_EVENT_ID(e) ((e >> 24))
+int usb_lld_event_handler (struct usb_dev *dev);
+
+/*
+ * Control Endpoint ENDP0 does device requests handling.
+ * In response to an event of
+ *     USB_EVENT_SET_CONFIGURATION
+ *     USB_EVENT_SET_INTERFACE
+ *     USB_EVENT_SET_FEATURE_DEVICE
+ *     USB_EVENT_SET_FEATURE_ENDPOINT
+ *     USB_EVENT_CLEAR_FEATURE_DEVICE
+ *     USB_EVENT_CLEAR_FEATURE_ENDPOINT
+ *     USB_EVENT_GET_STATUS_INTERFACE
+ *     USB_EVENT_GET_DESCRIPTOR
+ *     USB_EVENT_GET_INTERFACE
+ *     USB_EVENT_CTRL_REQUEST
+ *  a single action should be done, which is SEND, RECV, or,
+ *  ACKNOWLEDGE (no data to be sent, or to be received).
+ *  Otherwise, it's an error.
+ */
+int usb_lld_ctrl_send (struct usb_dev *dev, const void *buf, size_t buflen);
+int usb_lld_ctrl_recv (struct usb_dev *dev, void *p, size_t len);
+int usb_lld_ctrl_ack (struct usb_dev *dev);
+void usb_lld_ctrl_error (struct usb_dev *dev);
+
+void usb_lld_reset (struct usb_dev *dev, uint8_t feature);
+void usb_lld_set_configuration (struct usb_dev *dev, uint8_t config);
+uint8_t usb_lld_current_configuration (struct usb_dev *dev);
+void usb_lld_prepare_shutdown (void);
+void usb_lld_shutdown (void);
+
+#ifdef MCU_KINETIS_L
+void usb_lld_tx_enable_buf (int ep_num, const void *buf, size_t len);
+void usb_lld_rx_enable_buf (int ep_num, void *buf, size_t len);
+
+void usb_lld_setup_endp (struct usb_dev *dev, int ep_num, int rx_en, int tx_en);
+void usb_lld_stall (int ep_num);
+#else
+/* EP_TYPE[1:0] EndPoint TYPE */
+#define EP_BULK        (0x0000) /* EndPoint BULK        */
+#define EP_CONTROL     (0x0200) /* EndPoint CONTROL     */
+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
+#define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT   */
+
+void usb_lld_tx_enable (int ep_num, size_t len);
+void usb_lld_rx_enable (int ep_num);
+
+void usb_lld_setup_endpoint (int ep_num, int ep_type, int ep_kind,
+			     int ep_rx_addr, int ep_tx_addr,
+			     int ep_rx_memory_size);
+void usb_lld_stall_tx (int ep_num);
+void usb_lld_stall_rx (int ep_num);
+
+void usb_lld_txcpy (const void *src, int ep_num, int offset, size_t len);
+void usb_lld_write (uint8_t ep_num, const void *buf, size_t len);
+void usb_lld_rxcpy (uint8_t *dst, int ep_num, int offset, size_t len);
+void usb_lld_to_pmabuf (const void *src, uint16_t addr, size_t n);
+void usb_lld_from_pmabuf (void *dst, uint16_t addr, size_t n);
+#endif
Author	SHA1	Message	Date
NIIBE Yutaka	89eb54929e	Version 1.3.	2017-02-02 12:56:13 +09:00
NIIBE Yutaka	a96f84ff74	Add Blue Pill support.	2017-02-01 17:31:52 +09:00
Szczepan Zalega	9d84537c13	Switch off red LED for Nitrokey Start. Signed-off-by: Szczepan Zalega <szczepan@nitrokey.com>	2017-02-01 15:24:55 +09:00
NIIBE Yutaka	d448d3c678	Version 1.2	2016-10-13 10:18:47 +09:00
NIIBE Yutaka	bc664fe943	chopstx_join is cancellation point.	2016-10-12 12:06:37 +09:00
NIIBE Yutaka	08cca6b9f8	stackaddr/size change	2016-07-11 17:21:32 +09:00
NIIBE Yutaka	c9d59a3f3f	mcu/stm32f103.h: Add more constants from Gnuk 1.1.9	2016-07-11 11:38:58 +09:00
NIIBE Yutaka	09f27704f5	Version 1.1	2016-07-01 11:50:25 +09:00
NIIBE Yutaka	1f23bd4048	Change touch button for MKL27Z	2016-07-01 10:58:05 +09:00
NIIBE Yutaka	f5880ee5d5	Change API of chopstx_setpriority	2016-07-01 09:51:32 +09:00
NIIBE Yutaka	c7e571eca0	update doc	2016-06-30 16:41:32 +09:00
NIIBE Yutaka	0decd305b9	chopstx_poll example fix	2016-06-30 16:26:52 +09:00
NIIBE Yutaka	a2a29146a6	const pointer cleanup	2016-06-30 16:23:29 +09:00
NIIBE Yutaka	e7bd234a0d	Update for MKL27Z	2016-06-30 16:16:39 +09:00
NIIBE Yutaka	c71a24ddcb	MKL27Z touch	2016-06-29 17:05:33 +09:00
NIIBE Yutaka	663cbabe7c	Fix MKL27Z TPM registers	2016-06-29 16:51:16 +09:00
NIIBE Yutaka	41ac81a66b	Update example for fs-bb48	2016-06-29 16:38:18 +09:00
NIIBE Yutaka	986518fba7	fix setpriority	2016-06-29 16:36:53 +09:00
NIIBE Yutaka	15a4403f24	chopstx_poll change	2016-06-28 15:48:15 +09:00
Niibe Yutaka	40adf95c24	Version 1.0	2016-06-16 11:46:38 +09:00
Niibe Yutaka	5a7381ece6	Add FST-01G	2016-06-16 11:31:10 +09:00
Niibe Yutaka	52626a3368	chopstx_exit change	2016-06-15 12:41:12 +09:00
Niibe Yutaka	440188c373	Fix USB for STM32	2016-06-14 15:10:07 +09:00
NIIBE Yutaka	a6541cbcc6	NONE sounds bad, use OK instead	2016-06-10 08:25:00 +09:00
NIIBE Yutaka	74c7b5bcb3	minor comment change	2016-06-09 10:07:31 +09:00
NIIBE Yutaka	4d7e97028e	More update of USB API	2016-06-09 09:53:15 +09:00
NIIBE Yutaka	d061e6f931	USB for FS-BB48	2016-06-08 15:43:11 +09:00
NIIBE Yutaka	5f1c26ff17	USB API major change	2016-06-08 15:40:55 +09:00
NIIBE Yutaka	78718e57df	Move files	2016-06-02 11:01:11 +09:00
NIIBE Yutaka	a756987d2a	Fix chx_fatal	2016-06-01 07:47:58 +09:00
NIIBE Yutaka	b6e3a1aba1	Relicense ADC driver with GPLv3+ plus EXCEPTION	2016-05-31 21:41:40 +09:00
NIIBE Yutaka	c79a41870a	Version 0.12	2016-05-31 15:18:10 +09:00
NIIBE Yutaka	4889a5386b	STM32F030: Fix use of vector on RAM	2016-05-31 15:12:55 +09:00
NIIBE Yutaka	e02f2e71e6	Fix `f2a8b01607`	2016-05-31 14:18:12 +09:00
NIIBE Yutaka	1fa89d1754	Change USB API a bit	2016-05-31 13:13:14 +09:00
NIIBE Yutaka	03a1d46c08	Fix sys-stm32f103.h	2016-05-31 12:00:25 +09:00
NIIBE Yutaka	3a4e1f2bd5	Cleanup of sys and its macro	2016-05-31 11:49:01 +09:00
NIIBE Yutaka	421fd8019b	; ABOUT-SYS	2016-05-30 20:34:06 +09:00
NIIBE Yutaka	e8eaeced77	Update USB for stm32f103	2016-05-30 20:11:18 +09:00
NIIBE Yutaka	1ae3caf7fc	USB cleanup	2016-05-30 20:06:43 +09:00
NIIBE Yutaka	a933eebfd5	Update for STM32F103	2016-05-30 15:13:55 +09:00
NIIBE Yutaka	fae4c58d99	AES table is included in sys-stm32f103.c	2016-05-30 14:57:51 +09:00
NIIBE Yutaka	9f16e5e051	consolidate mcu-chip specific code	2016-05-30 14:57:10 +09:00
NIIBE Yutaka	b90e58f763	Move CHIP specific things to mcu/	2016-05-30 14:39:02 +09:00
NIIBE Yutaka	8209f38755	example-fs-bb48: Add flash ROM handling	2016-05-30 14:06:18 +09:00
NIIBE Yutaka	781ad1847c	example-fs-bb48: rm crc32.h	2016-05-27 17:29:36 +09:00
NIIBE Yutaka	8eb2130664	example-fs-bb48: rm crc32.h	2016-05-27 17:29:08 +09:00
NIIBE Yutaka	960921f537	example-fs-bb48: SYS implementation	2016-05-27 17:17:44 +09:00
NIIBE Yutaka	f2a8b01607	Fix IDLE thread	2016-05-27 16:19:02 +09:00
NIIBE Yutaka	890d108114	Add document for ABOUT-SYS	2016-05-27 11:22:29 +09:00
NIIBE Yutaka	5f57222b73	Move clk_gpio_init to mcu/	2016-05-26 17:40:47 +09:00
NIIBE Yutaka	d81767b7c7	example-fs-bb48: Only use LS-8-bit	2016-05-26 17:29:06 +09:00
NIIBE Yutaka	91823d0fc1	Move kl_sim.h	2016-05-26 10:21:30 +09:00
NIIBE Yutaka	51cd47c3b7	example-fs-bb48: ADC use DIV1	2016-05-26 09:54:44 +09:00
NIIBE Yutaka	cf81e7a6dc	example-fs-bb48: ADC added	2016-05-26 09:50:07 +09:00
NIIBE Yutaka	2578fc0f30	Update example-fs-bb48	2016-05-24 17:34:20 +09:00
NIIBE Yutaka	2704416c38	Fix PSR handling (ORRS instruction changes PSR)	2016-05-23 20:15:47 +09:00
NIIBE Yutaka	77255b0c1d	Fix chopstx_poll	2016-05-23 17:45:10 +09:00
NIIBE Yutaka	eeb354119c	Change example-cdc	2016-05-23 17:42:21 +09:00
NIIBE Yutaka	72c3d59555	Change example-fs-bb48	2016-05-23 17:42:01 +09:00
NIIBE Yutaka	8ba91f5db6	Fix example-fs-bb48 to support 16 endpoints	2016-05-23 17:36:31 +09:00
NIIBE Yutaka	b6603f6771	Update example-fs-bb48	2016-05-23 13:48:24 +09:00
NIIBE Yutaka	ee92bb15b3	Remove deprecated API	2016-05-23 13:00:33 +09:00
NIIBE Yutaka	5458b77d36	Version 0.11	2016-05-19 12:22:30 +09:00
NIIBE Yutaka	03bba13005	eventflag API addtiion	2016-05-19 11:48:01 +09:00
NIIBE Yutaka	1b0fe5a6e8	Add eventflag_set_poll_desc	2016-05-18 21:32:32 +09:00
NIIBE Yutaka	5e33e7f468	fix eventflag	2016-05-18 17:00:25 +09:00
NIIBE Yutaka	db413813b6	eventflag rewrite	2016-05-18 16:52:00 +09:00
NIIBE Yutaka	7f009dbb5d	update ChangeLog	2016-05-18 14:43:30 +09:00
NIIBE Yutaka	cea3200e48	Cleanup chopstx.c	2016-05-18 13:27:00 +09:00
NIIBE Yutaka	d93206882d	Fix mutex_lock and join	2016-05-18 11:40:15 +09:00
NIIBE Yutaka	a17d12192f	Fix example-cdc more	2016-05-18 09:55:23 +09:00
NIIBE Yutaka	4c1aa50f13	Fix example-cdc	2016-05-18 08:51:50 +09:00
NIIBE Yutaka	cf76b0bf13	example-cdc cleanup more	2016-05-17 21:33:58 +09:00
NIIBE Yutaka	76cbff737b	example-cdc cleanup	2016-05-17 20:49:17 +09:00
NIIBE Yutaka	dce6c70ffc	more fix for chopstx_poll	2016-05-17 17:51:41 +09:00
NIIBE Yutaka	3651aa64b4	ll_dequeue for PX only when not ready	2016-05-16 20:37:33 +09:00
NIIBE Yutaka	98977937cb	fix chx_wakeup	2016-05-16 18:00:41 +09:00
NIIBE Yutaka	06d046b963	Improve system routines API for STM32F103	2016-05-16 14:59:05 +09:00
NIIBE Yutaka	b7c6dadcfb	Fix IRQ handling and improve cancellation implementation	2016-05-16 14:50:04 +09:00
NIIBE Yutaka	a82acac8df	Bug fix for interrupt preemption	2016-05-13 22:27:56 +09:00
NIIBE Yutaka	206f2a5f07	Fix intr_wait	2016-05-13 17:51:12 +09:00
NIIBE Yutaka	5046dd45f2	IRQ handling is now merged into polling	2016-05-13 16:35:35 +09:00
NIIBE Yutaka	db6e668524	more fixes for chopstx_poll	2016-05-13 14:52:38 +09:00
NIIBE Yutaka	daa7aebd6f	Add READY field for chx_poll_XXX so that we can check if it's ready	2016-05-13 14:22:12 +09:00
NIIBE Yutaka	5fc2617ae5	Fix changelog	2016-05-13 11:11:01 +09:00
NIIBE Yutaka	fabd271196	Update example-cdc	2016-05-12 18:14:47 +09:00
NIIBE Yutaka	5730641ffd	Bug fixes for Cortex-M3 and chopstx_poll	2016-05-12 18:12:52 +09:00
NIIBE Yutaka	5c1638c023	Fix mutex init	2016-05-12 11:17:17 +09:00
NIIBE Yutaka	420bd135af	Adding ADC example for FS-BB48	2016-05-11 12:34:17 +09:00
NIIBE Yutaka	a538113c07	change poll behavior	2016-04-24 12:24:36 +09:00
NIIBE Yutaka	8668c8a88a	update sys.c in examples	2016-04-22 17:21:50 +09:00
NIIBE Yutaka	fba1dc05ea	Clean up FS-BB48 example	2016-04-22 17:21:29 +09:00
NIIBE Yutaka	1b12a78054	Modify chopstx_poll API	2016-04-22 13:42:01 +09:00
NIIBE Yutaka	5d40ffbffa	Implement chopstx_poll (2)	2016-04-21 16:10:06 +09:00
NIIBE Yutaka	06d28b62fb	Implement chopstx_poll	2016-04-21 15:59:34 +09:00
NIIBE Yutaka	437b2dc43c	Update for STM32	2016-04-20 17:30:41 +09:00
NIIBE Yutaka	3eac245981	fix	2016-04-19 16:40:25 +09:00
NIIBE Yutaka	7c2cdaa6e4	Example for FS-BB48 to compute CRC32.	2016-04-19 15:58:26 +09:00
NIIBE Yutaka	0bbb43dd3a	Fix USB driver and example	2016-04-18 17:23:10 +09:00
NIIBE Yutaka	82749ab97a	Add support for FS-BB48	2016-04-18 11:46:14 +09:00
NIIBE Yutaka	92e17d3bdf	USB stack for STM32F103 improvement	2016-04-07 14:52:39 +09:00
NIIBE Yutaka	674c19c495	SVC is required for Cortex-M3	2016-04-07 14:36:41 +09:00
NIIBE Yutaka	35426d7715	Fix MSP initial value and improve chx_sched	2016-04-07 09:59:13 +09:00
NIIBE Yutaka	6db2dd96c5	New function: chopstx_poll	2016-04-06 21:04:24 +09:00
NIIBE Yutaka	5e6a433457	New struct: chx_qh	2016-04-06 20:34:28 +09:00
NIIBE Yutaka	fa8dd7afc8	Don't use SVC for context switch	2016-04-06 19:49:18 +09:00
NIIBE Yutaka	8e40065311	Initialization of chx_spinlock	2016-04-05 19:27:25 +09:00
NIIBE Yutaka	a99c5c6048	fix struct NVIC	2016-04-05 19:17:44 +09:00
NIIBE Yutaka	e092a56c17	Fix USB GET	2016-03-15 10:31:16 +09:00
NIIBE Yutaka	25e5f21847	AAPCS stack alignment	2016-03-08 20:27:24 +09:00
NIIBE Yutaka	90ac7f7c13	update usb stack from Gnuk development branch	2016-03-08 20:20:49 +09:00
NIIBE Yutaka	fd8aee3cb0	CDC to be echo service.	2015-11-05 13:54:49 +09:00
NIIBE Yutaka	a30a069ed8	Version 0.10	2015-09-15 10:39:36 +09:00
NIIBE Yutaka	8fed803085	bug fixes around cancel/join/exit	2015-09-15 10:26:40 +09:00
NIIBE Yutaka	4705e2fb15	fix cancellation	2015-09-11 17:04:28 +09:00
NIIBE Yutaka	14ad395523	Version 0.09	2015-09-10 20:22:32 +09:00
NIIBE Yutaka	acd4460a6e	Update API doc	2015-09-09 17:06:51 +09:00
NIIBE Yutaka	79b13fb4a9	Cancellation fixes	2015-09-09 17:04:59 +09:00
NIIBE Yutaka	e9521648d5	move exception handling routines	2015-09-09 11:55:17 +09:00
NIIBE Yutaka	2bd7a8e6db	move svc, preempt, and sched	2015-09-09 11:35:20 +09:00
NIIBE Yutaka	c57b13bedc	factor out chx_prio_init	2015-09-09 11:06:52 +09:00
NIIBE Yutaka	06e4459c21	factoring: systick	2015-09-09 09:47:25 +09:00
NIIBE Yutaka	baef99bf11	fix white spaces	2015-09-08 17:19:14 +09:00
NIIBE Yutaka	1b25cc5dcb	fix more spin lock	2015-09-08 17:14:43 +09:00
NIIBE Yutaka	ee3c5d4e6f	prepare kkojima's patch for Cortex-A7	2015-09-08 17:06:53 +09:00
NIIBE Yutaka	80408902d7	fix spin-locking of INTR_TOP	2015-09-08 14:46:11 +09:00
NIIBE Yutaka	f6d79e6821	Add Mateusz Zalega	2015-09-07 17:10:42 +09:00
NIIBE Yutaka	014dbf25f6	Add example-primer2	2015-09-07 17:06:05 +09:00
NIIBE Yutaka	41610443d4	Netrokey Start change	2015-09-07 15:52:38 +09:00
NIIBE Yutaka	46468760a3	Nitrokey start support	2015-09-04 17:09:56 +09:00
NIIBE Yutaka	85ef4a5391	Fix for Nitrokey-start	2015-09-04 16:43:45 +09:00
Mateusz Zalega	8650bde8a0	board: add Nitrokey Start Signed-off-by: Mateusz Zalega <mateusz@nitrokey.com>	2015-09-04 16:38:01 +09:00
NIIBE Yutaka	6e7334dcff	Fix the score about A and tone-table change	2015-08-08 13:50:20 +09:00
NIIBE Yutaka	04a948024a	Celebrate Happy Hacking Day.	2015-08-06 11:10:48 +09:00
NIIBE Yutaka	1bbbaabe0d	Add a speaker	2015-08-06 11:02:34 +09:00
NIIBE Yutaka	218102c5c4	Version 0.08	2015-07-31 17:58:20 +09:00
NIIBE Yutaka	2c9e6b69d2	update example-fsm-55	2015-07-31 17:56:35 +09:00
NIIBE Yutaka	1d38c24233	Add Nucleo	2015-07-30 20:35:21 +09:00
NIIBE Yutaka	a9de53c36b	board update, adding ST Dongle	2015-07-29 17:06:17 +09:00
NIIBE Yutaka	83486efd5f	update USB driver	2015-07-28 15:09:43 +09:00
NIIBE Yutaka	bdaae5661d	Version 0.07	2015-07-15 12:09:07 +09:00
NIIBE Yutaka	2de0e2c405	Update example CDC	2015-07-15 12:04:45 +09:00
NIIBE Yutaka	d19570954e	Update example for FSM-55	2015-07-15 12:03:49 +09:00
NIIBE Yutaka	44b4bf640f	Update example for LED blink	2015-07-15 12:01:53 +09:00
NIIBE Yutaka	9898639165	Update Cortex-M0 boards	2015-07-15 11:48:36 +09:00
NIIBE Yutaka	cd61ff5653	share sys with example-fsm-55	2015-07-15 09:51:24 +09:00
NIIBE Yutaka	27f42c8522	ADC settings are consolidated into the driver	2015-07-14 21:31:18 +09:00
NIIBE Yutaka	a48ffaef47	fix sys.c	2015-07-14 21:26:10 +09:00
NIIBE Yutaka	27f71ff5c0	New sys.c	2015-07-14 16:10:07 +09:00
NIIBE Yutaka	3ba8234cec	sys_board and stm32 primer2	2015-07-13 16:45:32 +09:00
NIIBE Yutaka	2bb0e0de5d	Version 0.06	2015-07-08 08:38:18 +09:00
NIIBE Yutaka	4dc10d6b18	Update for FSM-55	2015-07-07 12:31:15 +09:00
NIIBE Yutaka	43bd3bcefd	fix STBee Mini	2015-06-30 10:47:07 +09:00
NIIBE Yutaka	6d13bd3770	fix clk_gpio_init	2015-06-30 10:20:11 +09:00
NIIBE Yutaka	6665723154	Add support for CQ STARM.	2015-06-29 15:59:30 +09:00
NIIBE Yutaka	97b4471cee	Make it clear LED is mandatory.	2015-06-29 15:58:21 +09:00
NIIBE Yutaka	15ae2d8b32	cleanup entry.c	2015-06-29 13:48:30 +09:00
NIIBE Yutaka	48273b3cb6	Clean up clock/gpio code	2015-06-22 17:34:17 +09:00
NIIBE Yutaka	b298648079	Kaz Kojima add STM32 Primer2 support	2015-06-22 16:18:44 +09:00
NIIBE Yutaka	fc26cf0889	Version 0.05 Merge branch 'cortex-m0-support'	2015-04-20 14:17:40 +09:00
NIIBE Yutaka	18b38533f7	Merge branch 'master' of git.gniibe.org:chopstx/chopstx Conflicts: ChangeLog	2015-04-18 12:28:00 +09:00
NIIBE Yutaka	a0f33c1036	New: chopstx_main_init	2015-04-18 12:23:35 +09:00
NIIBE Yutaka	431e62a077	Add board-maple-mini.h	2015-04-08 09:16:25 +09:00
NIIBE Yutaka	2fb7fb6826	Version 0.04a	2015-03-17 12:50:56 +09:00
NIIBE Yutaka	7c022432d1	fix rebase	2014-12-10 18:53:00 +09:00
NIIBE Yutaka	b0992073d7	Add debian-logo.c (from Portland).	2014-12-10 18:50:11 +09:00
NIIBE Yutaka	5f4cca00fc	It should be BSS section not to output data to .hex.	2014-12-10 18:50:10 +09:00
NIIBE Yutaka	1fcfc846b8	Button pushed, then another demo.	2014-12-10 18:50:10 +09:00
NIIBE Yutaka	f4fb26a56a	add button thread and join on exit.	2014-12-10 18:50:10 +09:00
NIIBE Yutaka	98e25c1cb2	Add GNU as hidden command.	2014-12-10 18:50:10 +09:00
NIIBE Yutaka	aeb8bd5a95	l55 and hh only.	2014-12-10 18:50:10 +09:00
NIIBE Yutaka	447b11fd1c	Add Happy Hacking.	2014-12-10 18:50:10 +09:00
NIIBE Yutaka	f4f2afd0ad	Use SIZE55.	2014-12-10 18:50:10 +09:00
NIIBE Yutaka	dffcf2d4bf	fix col/row.	2014-12-10 18:50:10 +09:00
NIIBE Yutaka	b05e4030d2	Add example-fsm-55.	2014-12-10 18:50:09 +09:00
NIIBE Yutaka	f865e5149c	Add FSM-55.	2014-12-10 18:50:09 +09:00
NIIBE Yutaka	5137db8290	Cortex-M0 works.	2014-12-10 18:50:09 +09:00
NIIBE Yutaka	522380097e	Support Cortex-M0.	2014-12-10 18:49:02 +09:00
NIIBE Yutaka	23893d9b73	Version 0.04	2014-12-10 18:39:39 +09:00
NIIBE Yutaka	0276d0825e	.gitignore updated	2014-12-10 13:51:22 +09:00
NIIBE Yutaka	f344d926c1	STBee Mini support	2013-11-27 12:45:20 +09:00
NIIBE Yutaka	2327cd9013	add STBee support	2013-11-26 17:01:15 +09:00
NIIBE Yutaka	5968e2a053	Add hex generation	2013-11-26 13:21:26 +09:00
NIIBE Yutaka	a528292476	example usb stack update from Gnuk	2013-11-21 12:10:50 +09:00
NIIBE Yutaka	51a862e200	Version 0.03	2013-11-08 12:37:55 +09:00
NIIBE Yutaka	21c3f461c5	Version 0.02	2013-11-08 11:37:53 +09:00
NIIBE Yutaka	e957d1aff8	Version 0.01	2013-11-03 12:10:22 +09:00
NIIBE Yutaka	05e6bda381	bDeviceState removal for usb_lld.h	2013-11-02 15:26:25 +09:00
NIIBE Yutaka	5a4a71d1ff	Update from Gnuk	2013-11-02 15:17:48 +09:00
NIIBE Yutaka	9fe6cefdc0	fix spurious interrupts, Gnuk pin-cir support	2013-11-02 14:23:44 +09:00
				`@@ -0,0 +1 @@`
				`void cmd_dispatch (struct tty tty, const char line);`