Version 0.01

ChangeLog

@@ -1,3 +1,35 @@
+2013-11-03  Niibe Yutaka  <gniibe@fsij.org>
+
+	* Version 0.01.
+	* doc/chopstx.texi (VERSION): 0.01.
+
+	* chopstx.c (chx_clr_intr): New.
+	(chopstx_intr_wait): Call chopstx.c.
+	(chx_enable_intr): Let chx_clr_intr clear pending-bit.
+
+2013-11-02  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb_lld.h, example-cdc/usb_stm32f103.c: Update from
+	Gnuk.
+	* example-cdc/usb-cdc.c (usb_cb_get_descriptor): Follow the
+	change.
+
+	* example-cdc/sys.c, example-led/sys.c: Update from Gnuk.
+
+	* chopstx.c (CPU_EXCEPTION_PRIORITY_INTERRUPT)
+	(CPU_EXCEPTION_PRIORITY_PENDSV): Change the value, so that
+	interrupt priority matches USB interrupt priority of old SYS 1.0
+	implementation.
+	(chx_enable_intr, chx_disable_intr): Clear pending bit at
+	chx_enable_intr.
+	(chopstx_intr_wait): Call chx_enable_intr only when it's going to
+	sleep.
+	* entry.c (RCC_APB2RSTR_AFIORST, define RCC_APB2ENR_AFIOEN): New.
+	(AFIO, GPIO_OTHER): New.
+	(gpio_init): Handle AFIO and GPIO_OTHER.
+	* board/board-fst-01.h, board/board-stm8s-discovery.h: Add pin-cir
+	usage.
+
 2013-08-21  Niibe Yutaka  <gniibe@fsij.org>
 
 	* Version 0.00.

NEWS

@@ -0,0 +1,43 @@
+NEWS - Noteworthy changes
+
+* Major changes in Chopstx 0.01
+
+  Released 2013-11-03, by NIIBE Yutaka
+
+** Interrupt handling change
+There was a bug in 0.00, which caused spurious interrupts.  Every
+interrupt event caused two events.  Specifically, after valid
+interrupt event (for the caller of chopstx_intr_wait), another
+spurious event was always occurred.  This was fixed.
+
+In the design of Chopstx, interrupt handling is done by a thread.
+Lower level interrupt handler just accepts interrupt, disabling the
+interrupt, and switchs the control to the thread.  It is the thread to
+check the cause of interrupt, to process it, and to clear the cause.
+Next call to chopstx_intr_wait will enable the interrupt again.
+
+The bug was related to pending interrupt flag.  Pending interrupt flag
+for a specific interrupt is set, on return from handler mode if the
+cause is still active.  With traditional interrupt handling, lower
+level interrupt handler processes it and clears the cause.  Thus,
+pending interrupt flag is not set on return.
+
+In Chopstx, pending interrupt flag was always set, because the control
+goes from lower level interrupt handler (in handler mode) to a
+interrupt handling thread which processes the interrupt.  In 0.01, new
+internal routine chx_clr_intr is introduced, and pending interrupt
+flag is cleared within chopstx_intr_wait after waked up.
+
+For detail of interrupt operation, see the section B.3.4, Nested
+Vectored Interrupt Controller (NVIC), in the ARM v7-M Architecture
+Reference Manual.  The subsection, B3.4.1, Theory of operation,
+explains how it works.
+
+
+** gpio_init change
+Now, gpi_init support AFIO mapping and another GPIO (GPIO_OTHER)
+settings.
+
+Local Variables:
+mode: outline
+End:

README

@@ -1,6 +1,6 @@
 Chopstx - Threads and only Threads
-							Version 0.00
-							  2013-08-21
+							Version 0.01
+							  2013-11-03
 							Niibe Yutaka
 					     Flying Stone Technology
 

board/board-fst-01-00.h

@@ -1,11 +1,11 @@
 #define FLASH_PAGE_SIZE 1024
 
-#define STM32_PLLXTPRE			STM32_PLLXTPRE_DIV1
-#define STM32_PLLMUL_VALUE		9
-#define STM32_HSECLK			8000000
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
 
-#define GPIO_USB_SET_TO_ENABLE		10
-#define GPIO_LED_SET_TO_EMIT		8
+#define GPIO_USB_SET_TO_ENABLE          10
+#define GPIO_LED_SET_TO_EMIT            8
 
 /*
  * Port A setup.
@@ -22,10 +22,10 @@
 #define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
 #define VAL_GPIO_CRH            0x88811383      /* PA15...PA8 */
 
-#define GPIO_USB_BASE	GPIOA_BASE
-#define GPIO_LED_BASE	GPIOA_BASE
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_LED_BASE   GPIOA_BASE
 
-#define RCC_APB2ENR_IOP_EN	RCC_APB2ENR_IOPAEN
-#define RCC_APB2RSTR_IOP_RST	RCC_APB2RSTR_IOPARST
+#define RCC_APB2ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+#define RCC_APB2RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
 
 /* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */

board/board-fst-01.h

@@ -1,11 +1,24 @@
 #define FLASH_PAGE_SIZE 1024
 
-#define STM32_PLLXTPRE			STM32_PLLXTPRE_DIV1
-#define STM32_PLLMUL_VALUE		6
-#define STM32_HSECLK			12000000
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
 
-#define GPIO_USB_SET_TO_ENABLE		10
-#define GPIO_LED_SET_TO_EMIT		0
+#define GPIO_USB_SET_TO_ENABLE          10
+#define GPIO_LED_SET_TO_EMIT            0
+
+/* For pin-cir settings of Gnuk */
+#define TIMx                  TIM2
+#define INTR_REQ_TIM          TIM2_IRQ
+#define AFIO_EXTICR_INDEX     0
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA
+#define EXTI_PR               EXTI_PR_PR2
+#define EXTI_IMR              EXTI_IMR_MR2
+#define EXTI_FTSR_TR          EXTI_FTSR_TR2
+#define INTR_REQ_EXTI         EXTI2_IRQ
+#define ENABLE_RCC_APB1
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM2EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM2RST
 
 /*
  * Port A setup.
@@ -42,11 +55,11 @@
 #define VAL_GPIO_LED_CRL            0x88888883      /*  PA7...PA0 */
 #define VAL_GPIO_LED_CRH            0x88888888      /* PA15...PA8 */
 
-#define GPIO_USB_BASE	GPIOA_BASE
-#define GPIO_LED_BASE	GPIOB_BASE
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_LED_BASE   GPIOB_BASE
 
-#define RCC_APB2ENR_IOP_EN	(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
-#define RCC_APB2RSTR_IOP_RST	(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
+#define RCC_APB2ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
+#define RCC_APB2RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
 
 /* NeuG settings for ADC2.  */
 #define NEUG_ADC_SETTING2_SMPR1 0

board/board-olimex-stm32-h103.h

@@ -1,11 +1,11 @@
 #define FLASH_PAGE_SIZE 1024
 
-#define STM32_PLLXTPRE			STM32_PLLXTPRE_DIV1
-#define STM32_PLLMUL_VALUE		9
-#define STM32_HSECLK			8000000
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
 
-#define GPIO_USB_CLEAR_TO_ENABLE	11
-#define GPIO_LED_CLEAR_TO_EMIT		12
+#define GPIO_USB_CLEAR_TO_ENABLE        11
+#define GPIO_LED_CLEAR_TO_EMIT          12
 
 /*
  * Port C setup.
@@ -22,11 +22,11 @@
 #define VAL_GPIO_CRL            0x44888888      /*  PC7...PC0 */
 #define VAL_GPIO_CRH            0x88837888      /* PC15...PC8 */
 
-#define GPIO_USB_BASE	GPIOC_BASE
-#define GPIO_LED_BASE	GPIOC_BASE
+#define GPIO_USB_BASE   GPIOC_BASE
+#define GPIO_LED_BASE   GPIOC_BASE
 
-#define RCC_APB2ENR_IOP_EN	RCC_APB2ENR_IOPCEN
-#define RCC_APB2RSTR_IOP_RST	RCC_APB2RSTR_IOPCRST
+#define RCC_APB2ENR_IOP_EN      RCC_APB2ENR_IOPCEN
+#define RCC_APB2RSTR_IOP_RST    RCC_APB2RSTR_IOPCRST
 
 /* NeuG settings for ADC2.  */
 #define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \

board/board-stm8s-discovery.h

@@ -1,11 +1,26 @@
 #define FLASH_PAGE_SIZE 1024
 
-#define STM32_PLLXTPRE			STM32_PLLXTPRE_DIV1
-#define STM32_PLLMUL_VALUE		9
-#define STM32_HSECLK			8000000
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
 
 #undef  GPIO_USB_CLEAR_TO_ENABLE
-#define GPIO_LED_SET_TO_EMIT		8
+#define GPIO_LED_SET_TO_EMIT            8
+
+/* For pin-cir settings of Gnuk */
+#define TIMx                  TIM3
+#define INTR_REQ_TIM          TIM3_IRQ
+#define AFIO_EXTICR_INDEX     1
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR2_EXTI5_PB
+#define EXTI_PR               EXTI_PR_PR5
+#define EXTI_IMR              EXTI_IMR_MR5
+#define EXTI_FTSR_TR          EXTI_FTSR_TR5
+#define INTR_REQ_EXTI         EXTI9_5_IRQ
+#define ENABLE_RCC_APB1
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM3EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM3RST
+#define AFIO_MAPR_SOMETHING   AFIO_MAPR_TIM3_REMAP_PARTIALREMAP
+                              /* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */
 
 /*
  * Port A setup.
@@ -21,10 +36,24 @@
 #define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
 #define VAL_GPIO_CRH            0x88811881      /* PA15...PA8 */
 
-#define GPIO_USB_BASE	GPIOA_BASE
-#define GPIO_LED_BASE	GPIOA_BASE
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_LED_BASE   GPIOA_BASE
 
-#define RCC_APB2ENR_IOP_EN	(RCC_APB2ENR_IOPAEN)
-#define RCC_APB2RSTR_IOP_RST	(RCC_APB2RSTR_IOPARST)
+#define RCC_APB2ENR_IOP_EN   \
+  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
+#define RCC_APB2RSTR_IOP_RST \
+  (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)
 
 /* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */
+
+#define GPIO_OTHER_BASE GPIOB_BASE
+/*
+ * Port B setup.
+ * PB4  - (TIM3_CH1) input with pull-up
+ * PB5  - (TIM3_CH2) input with pull-up, connected to CIR module
+ * Everything input with pull-up except:
+ * PB0  - (TIM3_CH3) input with pull-down
+ */
+#define VAL_GPIO_OTHER_ODR 0xFFFFFFFE
+#define VAL_GPIO_OTHER_CRL 0x88888888      /*  PB7...PB0 */
+#define VAL_GPIO_OTHER_CRH 0x88888888      /* PB15...PB8 */

chopstx.c

@@ -55,8 +55,9 @@
  * ---------------------
  * Prio 0x40: thread temporarily inhibiting schedule for critical region
  * Prio 0x50: systick
- * Prio 0x60: external interrupt
- * Prio 0x70: pendsv
+ * ...
+ * Prio 0xb0: external interrupt
+ * Prio 0xc0: pendsv
  */
 
 #define CPU_EXCEPTION_PRIORITY_CLEAR         0
@@ -65,8 +66,9 @@
 
 #define CPU_EXCEPTION_PRIORITY_INHIBIT_SCHED 0x40
 #define CPU_EXCEPTION_PRIORITY_SYSTICK       0x50
-#define CPU_EXCEPTION_PRIORITY_INTERRUPT     0x60
-#define CPU_EXCEPTION_PRIORITY_PENDSV        0x70
+/* ... */
+#define CPU_EXCEPTION_PRIORITY_INTERRUPT     0xb0
+#define CPU_EXCEPTION_PRIORITY_PENDSV        0xc0
 
 /**
  * chx_fatal - Fatal error point.
@@ -168,11 +170,11 @@ struct NVIC {
   uint32_t IPR[60];
 };
 
-static struct NVIC *const NVICBase = (struct NVIC *const)0xE000E100;
-#define NVIC_ISER(n)	(NVICBase->ISER[n >> 5])
-#define NVIC_ICER(n)	(NVICBase->ICER[n >> 5])
-#define NVIC_ICPR(n)	(NVICBase->ICPR[n >> 5])
-#define NVIC_IPR(n)	(NVICBase->IPR[n >> 2])
+static struct NVIC *const NVIC = (struct NVIC *const)0xE000E100;
+#define NVIC_ISER(n)	(NVIC->ISER[n >> 5])
+#define NVIC_ICER(n)	(NVIC->ICER[n >> 5])
+#define NVIC_ICPR(n)	(NVIC->ICPR[n >> 5])
+#define NVIC_IPR(n)	(NVIC->IPR[n >> 2])
 
 #define USB_LP_CAN1_RX0_IRQn	 20
 
@@ -643,12 +645,16 @@ chx_enable_intr (uint8_t irq_num)
   NVIC_ISER (irq_num) = 1 << (irq_num & 0x1f);
 }
 
+static void
+chx_clr_intr (uint8_t irq_num)
+{				/* Clear pending interrupt.  */
+  NVIC_ICPR (irq_num) = 1 << (irq_num & 0x1f);
+}
+
 static void
 chx_disable_intr (uint8_t irq_num)
 {
   NVIC_ICER (irq_num) = 1 << (irq_num & 0x1f);
-  /* Clear pending, too.  */
-  NVIC_ICPR (irq_num) = 1 << (irq_num & 0x1f);
 }
 
 
@@ -1244,14 +1250,15 @@ void
 chopstx_intr_wait (chopstx_intr_t *intr)
 {
   chx_cpu_sched_lock ();
-  chx_enable_intr (intr->irq_num);
   if (intr->ready == 0)
     {
+      chx_enable_intr (intr->irq_num);
       if (running->flag_sched_rr)
 	chx_timer_dequeue (running);
       running->state = THREAD_WAIT_INT;
       running->v = 0;
       chx_sched (CHX_SLEEP);
+      chx_clr_intr (intr->irq_num);
     }
   else
     chx_cpu_sched_unlock ();

doc/chopstx.texi

@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
 @c %**start of header
 @setfilename chopstx.info
-@set VERSION 0.00
+@set VERSION 0.01
 @settitle Chopstx Reference Manual
 @c Unify some of the indices.
 @syncodeindex tp fn

entry.c

@@ -163,15 +163,33 @@ clock_init (void)
     ;
 }
 
-#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2RSTR_AFIORST	0x00000001
 #define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
 #define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
 #define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
 #define RCC_APB2RSTR_IOPDRST	0x00000020
 
+#define RCC_APB2ENR_AFIOEN	0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+
+
+struct AFIO
+{
+  volatile uint32_t EVCR;
+  volatile uint32_t MAPR;
+  volatile uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  volatile uint32_t MAPR2;
+};
+
+#define AFIO_BASE 0x40010000
+static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
+
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+
 
 struct GPIO {
   volatile uint32_t CRL;
@@ -196,6 +214,9 @@ struct GPIO {
 
 static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
 static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
+#ifdef GPIO_OTHER_BASE
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
+#endif
 
 static void __attribute__((used))
 gpio_init (void)
@@ -205,6 +226,10 @@ gpio_init (void)
   RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
   RCC->APB2RSTR = 0;
 
+#ifdef AFIO_MAPR_SOMETHING
+  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
+#endif
+
   GPIO_USB->ODR = VAL_GPIO_ODR;
   GPIO_USB->CRH = VAL_GPIO_CRH;
   GPIO_USB->CRL = VAL_GPIO_CRL;
@@ -214,6 +239,12 @@ gpio_init (void)
   GPIO_LED->CRH = VAL_GPIO_LED_CRH;
   GPIO_LED->CRL = VAL_GPIO_LED_CRL;
 #endif
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
+  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
+  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
+#endif
 }
 #endif
 

example-cdc/sys.c

@@ -181,15 +181,33 @@ clock_init (void)
     ;
 }
 
-#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2RSTR_AFIORST    0x00000001
 #define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
 #define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
 #define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
 #define RCC_APB2RSTR_IOPDRST	0x00000020
 
+#define RCC_APB2ENR_AFIOEN      0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+
+
+struct AFIO
+{
+  volatile uint32_t EVCR;
+  volatile uint32_t MAPR;
+  volatile uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  volatile uint32_t MAPR2;
+};
+
+#define AFIO_BASE 0x40010000
+static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
+
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+
 
 struct GPIO {
   volatile uint32_t CRL;
@@ -214,6 +232,9 @@ struct GPIO {
 
 static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
 static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
+#ifdef GPIO_OTHER_BASE
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
+#endif
 
 static void
 gpio_init (void)
@@ -223,6 +244,10 @@ gpio_init (void)
   RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
   RCC->APB2RSTR = 0;
 
+#ifdef AFIO_MAPR_SOMETHING
+  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
+#endif
+
   GPIO_USB->ODR = VAL_GPIO_ODR;
   GPIO_USB->CRH = VAL_GPIO_CRH;
   GPIO_USB->CRL = VAL_GPIO_CRL;
@@ -232,6 +257,12 @@ gpio_init (void)
   GPIO_LED->CRH = VAL_GPIO_LED_CRH;
   GPIO_LED->CRL = VAL_GPIO_LED_CRL;
 #endif
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
+  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
+  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
+#endif
 }
 
 static void
@@ -276,8 +307,6 @@ static void wait (int count)
     asm volatile ("" : : "r" (i) : "memory");
 }
 
-#define USB_IRQ 20
-#define USB_IRQ_PRIORITY ((11) << 4)
 
 static void
 usb_lld_sys_shutdown (void)

example-cdc/usb-cdc.c

@@ -253,9 +253,13 @@ usb_cb_setup (uint8_t req, uint8_t req_no,
 }
 
 int
-usb_cb_get_descriptor (uint8_t desc_type, uint16_t index, uint16_t value)
+usb_cb_get_descriptor (uint8_t rcp, uint8_t desc_type, uint8_t desc_index,
+		       uint16_t index)
 {
   (void)index;
+  if (rcp != DEVICE_RECIPIENT)
+    return USB_UNSUPPORT;
+
   if (desc_type == DEVICE_DESCRIPTOR)
     {
       usb_lld_set_data_to_send (vcom_device_desc, sizeof (vcom_device_desc));
@@ -269,7 +273,6 @@ usb_cb_get_descriptor (uint8_t desc_type, uint16_t index, uint16_t value)
     }
   else if (desc_type == STRING_DESCRIPTOR)
     {
-      uint8_t desc_index = value & 0xff;
       const uint8_t *str;
       int size;
 

example-cdc/usb_lld.h

@@ -60,7 +60,8 @@ void usb_cb_ctrl_write_finish (uint8_t req, uint8_t req_no,
 			       uint16_t value, uint16_t index, uint16_t len);
 int usb_cb_setup (uint8_t req, uint8_t req_no, uint16_t value,
 		  uint16_t index, uint16_t len);
-int usb_cb_get_descriptor (uint8_t desc_type, uint16_t index, uint16_t value);
+int usb_cb_get_descriptor (uint8_t rcp, uint8_t desc_type, uint8_t desc_index,
+			   uint16_t index);
 int usb_cb_handle_event (uint8_t event_type, uint16_t value);
 int usb_cb_interface (uint8_t cmd, uint16_t interface, uint16_t value);
 
@@ -90,8 +91,6 @@ enum DEVICE_STATE
 
 extern const uint8_t usb_initial_feature;
 
-#define STM32_USB_IRQ_PRIORITY     11
-
 extern void usb_lld_init (uint8_t feature);
 
 extern void usb_lld_to_pmabuf (const void *src, uint16_t addr, size_t n);

example-cdc/usb_stm32f103.c

@@ -697,10 +697,7 @@ static int std_get_descriptor (uint8_t req, uint16_t value,
     return USB_UNSUPPORT;
 
   (void)length;
-  if (rcp == DEVICE_RECIPIENT)
-    return usb_cb_get_descriptor ((value >> 8), index, value);
-
-  return USB_UNSUPPORT;
+  return usb_cb_get_descriptor (rcp, (value >> 8), (value & 0xff), index);
 }
 
 static int std_get_configuration (uint8_t req, uint16_t value,

example-led/sys.c

@@ -181,15 +181,33 @@ clock_init (void)
     ;
 }
 
-#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2RSTR_AFIORST    0x00000001
 #define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
 #define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
 #define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
 #define RCC_APB2RSTR_IOPDRST	0x00000020
 
+#define RCC_APB2ENR_AFIOEN      0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+
+
+struct AFIO
+{
+  volatile uint32_t EVCR;
+  volatile uint32_t MAPR;
+  volatile uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  volatile uint32_t MAPR2;
+};
+
+#define AFIO_BASE 0x40010000
+static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
+
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+
 
 struct GPIO {
   volatile uint32_t CRL;
@@ -214,6 +232,9 @@ struct GPIO {
 
 static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
 static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
+#ifdef GPIO_OTHER_BASE
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
+#endif
 
 static void
 gpio_init (void)
@@ -223,6 +244,10 @@ gpio_init (void)
   RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
   RCC->APB2RSTR = 0;
 
+#ifdef AFIO_MAPR_SOMETHING
+  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
+#endif
+
   GPIO_USB->ODR = VAL_GPIO_ODR;
   GPIO_USB->CRH = VAL_GPIO_CRH;
   GPIO_USB->CRL = VAL_GPIO_CRL;
@@ -232,6 +257,12 @@ gpio_init (void)
   GPIO_LED->CRH = VAL_GPIO_LED_CRH;
   GPIO_LED->CRL = VAL_GPIO_LED_CRL;
 #endif
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
+  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
+  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
+#endif
 }
 
 static void
@@ -276,8 +307,6 @@ static void wait (int count)
     asm volatile ("" : : "r" (i) : "memory");
 }
 
-#define USB_IRQ 20
-#define USB_IRQ_PRIORITY ((11) << 4)
 
 static void
 usb_lld_sys_shutdown (void)