Version 1.16.

I should have called version 1.10 as 2.0, becase it introduced API
change.

.gitlab-ci.yml

@@ -0,0 +1,15 @@
+image: debian:stable
+
+before_script:
+  - apt-get update && apt-get -y install texi2html
+
+pages:
+  stage: deploy
+  script:
+  - mkdir -p html && (cd html && texi2html ../doc/chopstx.texi)
+  - mv html/ public
+  artifacts:
+    paths:
+    - public
+  only:
+    - master

AUTHORS

@@ -2,6 +2,10 @@ Aidan Thornton:
     Added Maple Mini support.
 	board/board-maple-mini.h
 
+Evangelos Rigas:
+    Added Gnukey-DS support.
+	board/board-gnukey-ds.h
+
 Jeremy Drake:
     Modified STM32F103 support.
 	mcu/sys-stm32f103.c
@@ -19,7 +23,7 @@ Kenji Rikitake:
 
 Kiwamu Okabe:
     Wrote an OpenOCD scirpt:
-        example-fsm-55/stlink-v2.cfg
+	example-fsm-55/stlink-v2.cfg
 
 Mateusz Zalega:
     Added Nitrokey-Start support.
@@ -27,18 +31,30 @@ Mateusz Zalega:
 
 NIIBE Yutaka:
     Wrote the library:
-	chopstx.c, entry.c, eventflag.c,
+	chopstx.c, chopstx.h,
-        chopstx.h, eventflag.h
+	chopstx-cortex-m.c, chopstx-cortex-m.h,
+	chopstx-gnu-linux.c, chopstx-gnu-linux.h,
+	entry.c,
+	eventflag.c, eventflag.h
     Wrote the drivers mcu/*:
-    	clk_gpio_init-mkl27z.c, clk_gpio_init-stm32.c,
+	chx-gnu-linux.c, chx-mkl27z.c, chx-stm32f0.c, chx-stm32f103.c,
-	sys-stm32f103.c, sys-stm32f030.c, sys-mkl27z.c,
+    	clk_gpio_init-mkl27z.c, clk_gpio_init-stm32f.c,
-	adc-stm32f103.c, adc-mkl27z.c
+	cortex-m.h, mkl27z.h, stm32.h, stm32f103.h,
+	sys-gnu-linux.c,sys-gnu-linux.h,
+	sys-mkl27z.c, sys-mkl27z.h,
+	sys-stm32f0.c, sys-stm32f0.h
+	sys-stm32f103.c, sys-stm32f103.h,
+	usb-stm32f103.c, usb-mkl27z.c
+    Wrote the drivers:
+	controb/adc-mkl27z.c
     Drew the logo:
 	chopstx.svg, chopstx.png
     Wrote examples:
-        example-led, example-cdc, example-fsm-55, example-fs-bb48
+	example-led, example-cdc, example-fsm-55, example-fs-bb48,
+	example-usb-serial, example-cdc-gnu-linux
     Wrote board/*:
-        board-fst-01.h, board-fst-01-00.h,
+        board-fst-01sz.h,
+	board-fst-01g.h, board-fst-01.h, board-fst-01-00.h,
 	board-olimex-stm32-h103.h, board-stm8s-discovery.h
 	board-cq-starm.h, board-stbee-mini.h, board-stbee.h,
 
@@ -46,8 +62,14 @@ NIIBE Yutaka:
 
 	board-fs-bb48.h
 
+    For Free Software Initiative of Japan, wrote:
+	contrib/adc-stm32f103.c,
+	contrib/adc-gnu-linux.c
+
     Under contract of g10 Code GmbH, wrote:
-        mcu/usb-usbip.c
+	mcu/usb-usbip.c
+	contrib/usart-stm32f103.c
+	contrib/ackbtn-stm32f103.c
 
 Paul Fertser:
     Added Blue Pill support.

ChangeLog

@@ -1,3 +1,459 @@
+2019-05-22  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.16.
+	* doc/chopstx.texi (VERSION): 1.16.
+
+2019-05-22  Evangelos Rigas <erigas@rnd2.org>
+
+	* board/board-gnukey-ds.h: New.
+
+2019-05-14  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.15.
+	* doc/chopstx.texi (VERSION): 1.15.
+
+2019-05-13  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-maple-mini.h: Assert USB D+ pull-up.
+	* board/board-olimex-stm32-h103.h: Likewise.
+	* board/board-stbee.h:Likewise.
+	* board/board-stm32-primer2.h: Likewise.
+
+	* mcu/usb-stm32f103.c: Don't use usb_lld_sys_init and
+	usb_lld_sys_shutdown in SYS.
+	* mcu/usb-stm32l4.c: Ditto.
+
+2019-05-10  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_claim_irq): Check INTR before the call.
+
+	* chopstx-cortex-m.c (chx_disable_intr): Have return value.
+	* chopstx-gnu-linux.c (chx_disable_intr): Likewise.
+
+2019-05-10  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/sys-stm32f103.c: SYS version 4.0.
+	* mcu/sys-gnu-linux.c: Likewise.
+	* mcu/sys-mkl27z.c: Likewise.
+	* mcu/sys-stm32l4.c: Likewise.
+	* mcu/sys-stm32f0.c: Likewise.
+
+2019-05-08  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/sys-stm32f103.c (usb_lld_sys_shutdown, usb_lld_sys_init):
+	Only cable config.
+
+	* mcu/sys-stm32l4.c (usb_lld_sys_shutdown, usb_lld_sys_init):
+	Likewise.
+
+	* mcu/usb-st-common.c (usb_lld_init): Call chip specific routine.
+	(usb_lld_shutdown): Likewise.
+
+	* mcu/usb-stm32l4.c (usb_lld_init_chip_specific)
+	(usb_lld_shutdown_chip_specific): New.
+
+	* mcu/usb-stm32f103.c (usb_lld_init_chip_specific)
+	(usb_lld_shutdown_chip_specific): New.
+
+	* rules.mk (DEFS): Add -DUSE_SYS when USE_SYS.
+
+2019-04-25  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart.h (BSCARD1, BSCARD2...): New.
+	(BSCARD): Remove.
+
+	* contrib/usart-stm32f103.c (usart_config_baud): Rename
+	from usart_config_brr, changing API.
+	* contrib/usart-stm32l4.c (usart_config_baud): Likewise.
+
+2019-04-24  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/sys-stm32l4.c: New.
+	* mcu/chx-stm32l4.c: New.  Not support suspend yet.
+	* mcu/stm32l.h: New.
+	* mcu/clk_gpio_init-stm32l.c: New.
+
+2019-04-17  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-stm32l4.c: New.
+	* mcu/usb-st-common.c: Factor out from usb-stm32f103.c.
+
+2019-04-12  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32l4.c: New.
+	* contrib/usart-common.c: Factor out from usart-stm32f103.c.
+
+	* entry.c [__ARM_ARCH_7EM__] (entry): Fix for Cortex-M4.
+
+2019-04-11  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx-cortex-m.c: Support Cortex-M4 (not touching FPU).
+
+2019-04-10  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/clk_gpio_init-stm32f.c: Rename from clk_gpio_init-stm32.c.
+
+	* entry.c: Use STM32F10X_HD.
+	* board/board-stbee.h (STM32F10X_HD): Add.
+	* board/board-stm32-primer2.h (STM32F10X_HD): Add.
+
+2019-04-09  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32f103.c (usart_block_sendrecv): Support
+	busy-wait when timeout_block_p == 0.
+
+2019-04-08  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32f103.c (usart_block_sendrecv): New.
+	(usart_init0): New.
+
+2019-03-30  Niibe Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32f103.c (usart_config_brr): New.
+	(usart_config_re): New internal function.
+	(handle_intr, handle_tx_ready): Use TC for smartcard.
+	(usart_wait_write_completion): New internal function.
+	(usart_write): Support half-duplex smartcard mode.
+
+2019-03-29  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32f103.c (usart_read_ext): New.
+	(usart_read_prepare_poll): New.
+
+2019-03-02  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.14.
+	* doc/chopstx.texi (VERSION): 1.14.
+
+2019-03-01  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32f103.c (usart_config): Fix SCEN setting
+	procedure.
+
+2019-03-01  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32f103.c (usart_config): Support parity error
+	interrupt setting.
+	(usart_init): Don't call usart_config here.
+	* example-usb-serial/sample.c: It's application calling
+	usart_config.
+
+2019-02-28  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart.h (BSCARD): New.
+	* contrib/usart-stm32f103.c (BSCARD): Baudrate for smartcard.
+	(usart_config_clken): New.
+	(usart_config): Fix for MODE_SMARTCARD.
+
+	* board/board-st-nucleo-f103.h: Define pins for smartcard
+	interface.
+
+2019-02-21  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart.h (MODE_SMARTCARD, MODE_IRDA, MODE_IRDA_LP)
+	(MASK_MODE): New.
+
+	* contrib/usart-stm32f103.c (usart_config): Add support for
+	those modes.
+
+2018-12-19  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.13.
+	* doc/chopstx.texi (VERSION): 1.13.
+
+2018-12-08  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_timer_dequeue): Fix calculation of return value.
+
+2018-12-07  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_timer_dequeue): Return ticks remained.
+	(chx_wakeup, chopstx_mutex_lock): Use return value of
+	chx_timer_dequeue.
+	(chx_snooze): Update *USEC_P, accordingly.
+
+2018-11-12  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.12.
+	* doc/chopstx.texi (VERSION): 1.12.
+
+	* contrib/ackbtn-stm32f103.c (ackbtn_init): Support FST-01 and
+	FST-01G, using PA2.
+	(ackbtn_disable): Fix to correctly clear pending interrupt.
+
+2018-11-09  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* eventflag.c (eventflag_set_mask): New.
+
+2018-10-02  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.11.
+	* doc/chopstx.texi (VERSION): 1.11.
+
+2018-10-01  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/ackbtn-stm32f103.c (PINCFG_EDGE): New.
+	(ackbtn_init): Use PINCFG_EDGE bit.
+	(ackbtn_enable): Configure the edge detector here.
+	(ackbtn_disable): Disable the edge detector.
+
+	* chopstx.c (chopstx_poll): Don't clear ->ready here.
+	(chx_cond_hook): Set ->ready = 0 when condition does
+	not meet.
+	(chopstx_claim_irq): Make sure clearing the interrupt.
+	(chx_intr_hook): Add the case when ->ready == 1.
+	(chopstx_intr_done): Set ->ready = 0.
+	(chx_join_hook): Set ->ready = 0 when it is still alive.
+
+2018-09-29  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.10.
+	* doc/chopstx.texi (VERSION): 1.10.
+
+2018-09-27  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/ackbtn-stm32f103.c: New.
+	* rules.mk [USE_ACKBTN] (CSRC): Add ack-button support.
+
+2018-09-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+	Fix for chopstx_intr_done.  No spurious interrupts.
+	* contrib/adc-mkl27z.c (adc_wait_completion): Fix.
+	* contrib/adc-stm32f103.c (adc_wait_completion): Likewise.
+	* contrib/usart-stm32f103.c (usart_main): Likewise.
+	* example-cdc-gnu-linux/usb-cdc.c (tty_main): Likewise.
+	* example-cdc/usb-cdc.c (tty_main): Likewise.
+	* example-fraucheky/main.c (usb_main): Likewise.
+	* example-fs-bb48/touch.c (touch_get): Likewise.
+	* example-fs-bb48/usb-cdc.c (tty_main): Likewise.
+	* example-primer2/primer2-ts.c (adc3_conversion): Likewise.
+	* example-usb-serial/usb-cdc.c (cdc_main): Likewise.
+
+2018-09-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.h (chopstx_intr_done): New function.
+	* chopstx.c (chopstx_intr_done): New function.
+	(chopstx_poll): Don't call chx_clr_intr.
+	Ensure data memory barrier for interrupt handling.
+
+	* chopstx-cortex-m.c (chx_dmb): New static function.
+	* chopstx-gnu-linux.c (chx_dmb): Ditto.
+
+2018-09-21  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/stm32.h (struct GPIO, struct FLASH): Moved from...
+	* mcu/clk_gpio_init-stm32.c: ... here.
+	(AFIO_MAPR_SWJ_CFG_JTAGDISABLE): Move to ...
+	* mcu/stm32f103.h: ... here.
+	* mcu/sys-stm32f103.c: Don't include "mcu/cortex-m.h".
+
+	* board/board-fst-01sz.h: New.
+	* mcu/sys-stm32f103.h (BOARD_ID_FST_01SZ): New.
+	* contrib/adc-stm32f103.c (get_adc_config): Add BOARD_ID_FST_01SZ.
+
+2018-08-20  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-stm32f103.c (usb_lld_ctrl_send): Fix for ZLP.
+	* mcu/usb-usbip.c (usb_lld_ctrl_send): Likewise.
+	* mcu/usb-mkl27z.c (usb_lld_ctrl_send): Likewise.
+
+2018-05-09  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.9.
+	* doc/chopstx.texi (VERSION): 1.9.
+
+2018-05-08  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-blue-pill.h (GPIO_USB_SET_TO_ENABLE): Remove.
+
+	* doc/chopstx.texi (Compile-time macro): New chapter.
+
+	* mcu/sys-stm32f103.c (usb_lld_sys_init): Use MHZ.
+	(flash_protect): Fix for GD32F103.
+
+2018-04-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-blue-pill-g.h: New.  Define STM32_ADCPRE and
+	STM32_USBPRE for 96MHz clock.
+	* mcu/stm32.h (STM32_USBPRE_DIV2): New for GD32F103.
+	* mcu/clk_gpio_init-stm32.c: Allow constants, which are defined by
+	board.h	(STM32_ADCPRE and STM32_USBPRE).
+	* mcu/chx-stm32f103.c: Use STM32_ADCPRE and STM32_USBPRE.
+
+	* mcu/usb-stm32f103.c (usb_lld_init): BTABLE setting at
+	initialization.
+	(usb_lld_reset): Not at each reset.
+
+	* contrib/adc-stm32f103.c [MCU_STM32F1_GD32F1]: Use continuous
+	sampling with no DELIBARATELY_DO_IT_WRONG_START_STOP.
+	(adc_init): Wait after ADC_CR2_ADON.
+	(adc_start): Likewise.  Enabling by ADC_CR2_ADON after all other
+	registers configuration.
+
+2018-01-19  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.8.
+	* doc/chopstx.texi (VERSION): 1.8.
+
+2018-01-18  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/stm32f103.h: Include stm32.h and cortex-m.h.
+
+2018-01-09  Anthony Romano <romanoanthony061@gmail.com>
+
+	* contrib/adc-stm32f103.c: Support IN8 config.
+
+2017-12-19  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.7.
+	* doc/chopstx.texi (VERSION): 1.7.
+
+2017-12-18  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32f103.c: New.
+	* example-usb-serial: New example.
+
+2017-12-16  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_timer_expired): Bug fix of wake up.
+	(chx_mutex_unlock): Avoid non-deterministic thing.
+
+2017-12-14  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-st-nucleo-f103.h: Update.
+
+	* mcu/sys-stm32f103.h (BOARD_ID_FST_01G): New.
+
+	* contrib/adc-stm32f103.c (get_adc_config): Add a case for
+	BOARD_ID_FST_01G and BOARD_ID_ST_NUCLEO_F103.
+
+2017-11-24  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.6.
+	* doc/chopstx.texi (VERSION): 1.6.
+	* doc/chopstx-api.texi: Regenerated.
+
+2017-11-21  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-fsm-55: Update using stack-def.h.
+
+2017-11-20  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-led: Update using stack-def.h.
+
+	* chopstx-cortex-m.c [__ARM_ARCH_6M__] (chx_sched): Fix.
+
+2017-11-18  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-fsm-55/hh.c (main): Just return.
+
+2017-11-17  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/chx-stm32f103.c (configure_clock): Change prescaler on
+	sleep.
+
+	* mcu/clk_gpio_init-stm32.c (clock_init): Don't turn on CRC
+	module.
+
+	* mcu/clk_gpio_init-stm32.c (STM32_*): Move to...
+	* mcu/stm32.h (STM32_*): ... this header file.
+
+	* mcu/stm32f103.h, mcu/clk_gpio_init-stm32.c (RCC): Move to...
+	* mcu/stm32.h (RCC): ... this header file.
+
+	* example-fsm-55: Update for new sleep API.
+
+	* rules.mk (CSRC): Add mcu/chx-$(CHIP).c.
+
+	* chopstx-cortex-m.c (idle, chx_sleep_mode): Remove.
+	(chx_sched, preempt): Call chx_idle.
+	* mcu/chx-mkl27z.c, mcu/chx-stm32f0.c, mcu/chx-stm32f103.c: New.
+	* mcu/stm32.h: New.
+
+	* chopstx-gnu-linux.c (chx_sleep_mode): Move to...
+	* mcu/chx-gnu-linux.c: Here.
+
+	* mcu/stm32f103.h (DBGMCU): New.
+
+	* mcu/cortex-m.h: New.
+	* mcu/sys-stm32f0.c, mcu/sys-stm32f103.c: Use mcu/cortex-m.h.
+
+	* chopstx.c (chopstx_conf_idle): Call chx_sleep_mode before
+	changing chx_allow_sleep.
+
+	* board/board-blue-pill.h, board/board-cq-starm.h,
+	board/board-fst-01-00.h, board/board-fst-01.h,
+	board/board-fst-01g.h, board/board-maple-mini.h,
+	board/board-nitrokey-start.h, board/board-olimex-stm32-h103.h,
+	board/board-st-dongle.h, board/board-st-nucleo-f103.h,
+	board/board-stbee-mini.h, board/board-stbee.h,
+	board/board-stm32-primer2.h: Add MCU_STM32F1.
+
+2017-11-16  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.h (chopstx_poll): API change.
+	* chopstx.c (chopstx_poll): Use const pointer.
+
+	* chopstx-cortex-m.c (idle): Support WFE.
+	[!MCU_STM32F0] (chx_sleep_mode): Clock feed by HSI.
+
+2017-11-15  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_conf_idle): Call chx_sleep_mode.
+	* chopstx-cortex-m.c (chx_sleep_mode): New.
+	* chopstx-gnu-linux.c (chx_sleep_mode): New.
+
+2017-11-15  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* example-fsm-55/hh.c (main): Add call to chopstx_conf_idle.
+	* example-fsm-55/Makefile (DEFS): Remove USE_WFI_FOR_IDLE.
+
+	* chopstx.c (chx_init): Initialize sleep lock.
+	(chopstx_conf_idle): New.
+	* chopstx-cortex-m.c (idle): Support sleep.
+
+	* mcu/usb-stm32f103.c (usb_lld_event_handler): Fix suspend/resume.
+
+2017-11-14  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* usb_lld.h (DEVICE_STATE): Add prefix USB_DEVICE_STATE_.
+	(USB_DEVICE_STATE_DEFAULT): New.
+
+	* mcu/usb-stm32f103.c (usb_lld_init): Suspend/resume init.
+	(usb_lld_event_handler): Add suspend/resume support.
+
+	* example-cdc/usb-cdc.c: Follow the change of usb_lld.h.
+	* example-cdc-gnu-linux/usb-cdc.c: Ditto.
+	* example-fs-bb48/usb-cdc.c: Ditto.
+	* example-fraucheky/main.c: Ditto.
+	* example-fraucheky/Makefile (USE_SYS): Add for debug.
+
+2017-11-13  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-stm32f103.c (usb_lld_init): Set up interrupt on errors.
+
+	* usb_lld.h (USB_EVENT_DEVICE_WAKEUP): New.
+	(INTR_REQ_USB): Define here.
+	* mcu/usb-usbip.c, example-cdc/usb-cdc.c,
+	example-fraucheky/main.c, example-fs-bb48/usb-cdc.c: Change
+	for INTR_REQ_USB.
+
+2017-11-10  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx-cortex-m.c (svc): Replace stack top to TP.
+	(chx_sched): Return ->v correctly.
+
+	* chopstx.c (chx_timer_expired): Fix timeout.
+
+2017-10-11  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/sys-stm32f103.h (nonreturn_handler0, nonreturn_handler1): New.
+
+2017-10-10  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-usbip.c (usbip_run_server): Shutdown support.
+	(usb_lld_shutdown): Shutdown glace-fully.
+
 2017-10-10  NIIBE Yutaka  <gniibe@fsij.org>
 
 	* VERSION: 1.5.

EXCEPTION

@@ -5,7 +5,7 @@ include following exception to GNU GPL.
 --------------------
 As additional permission under GNU GPL version 3 section 7, you may
 distribute non-source form of the Program without the copy of the GNU
-GPL normally required by section 4, provided you inform the receipents
+GPL normally required by section 4, provided you inform the recipients
 of GNU GPL by a written offer.
 --------------------
 

NEWS

@@ -1,6 +1,195 @@
 NEWS - Noteworthy changes
 
 
+* Major changes in Chopstx 1.16
+
+  Released 2019-05-22
+
+** New board support: Gnukey-DS
+It is contributed by Evangelos Rigas.
+
+
+* Major changes in Chopstx 1.15
+
+  Released 2019-05-14
+
+** SYS version 4.0
+USB initialization/finalization API has been changed.  SYS routines
+only handle USB cable configuration when supported by a board.
+
+** USB driver change
+Enabling/disabling USB module is done by USB driver.  It's
+responsibility of board configuration to enable external transistor
+for pull-up D+-line by board/*.h.  For all boards, USB driver doesn't
+use usb_lld_sys_init or usb_lld_sys_shutdown (those routines only can
+be used for USB self powered system, which Chopstx does not support
+yet).
+
+** Board configuration change
+For USB driver change, board-maple-mini.h, board-olimex-stm32-h103.h,
+board-stbee.h, and board-stm32-primer2.h were changed.  Pull-up is
+enabled at the time of gpio_init.
+
+** Cortex-M4 support
+Cortex-M4 support has been added.  Not supporting use of FPU or DSP,
+yet.  Note that it's not intend to be used by Gnuk.
+
+** STM32L432 support
+USART and USB drivers are added.
+
+** New board support: ST Nucleo-32 L432
+ST Nucleo-32 L432 is a small board with ST-Link/V2-1.
+
+** Minor implementation change: chopstx_claim_irq
+If the interrupt is disabled (possibly by chx_intr) when
+chopstx_claim_irq is called, INTR->ready is set to 1.  This allows
+calling chopstx_claim_irq after hardware initialization which may
+cause an interrupt before the call of chopstx_claim_irq.
+
+
+* Major changes in Chopstx 1.14
+
+  Released 2019-03-02
+
+** Enhancement of driver: USART for STM32
+Now, it supports smartcard communication.
+
+
+* Major changes in Chopstx 1.13
+
+  Released 2018-12-19
+
+** API fix (redefinition): chopstx_poll
+In old implementations, when chopstx_poll returns by non-timeout
+event, *USEC_P is not updated.  Now, it is updated.
+
+
+* Major changes in Chopstx 1.12
+
+  Released 2018-11-12
+
+** Enhance API of eventflag
+New function eventflag_set_mask is added, so that we can only handle
+specified events.  See Gnuk 1.2.12 for an example (while USB Tx is
+busy, the USB thread only accepts EV_TX_FINISHED event, leaving
+other events).
+
+** Acknowledge button support for FST-01 and FST-01G
+While FST-01 and FST-01G don't have any button in the original design,
+it may be PA2 when user put a hall sensor or a switch.
+
+
+* Major changes in Chopstx 1.11
+
+  Released 2018-10-02
+
+** Support calling chopstx_poll with intr->ready==1
+In version <= 1.10, it assumed that all events should be handled after
+chopstx_poll, before calling chopstx_poll again.  With having
+chopstx_intr_done, it's OK now that chopstx_poll can be called again
+not examining/handling all poll descriptors, but only parts of them.
+
+** Acknowledge button change
+In 1.10, the action was able to be "memorized" by the edge detector.
+Now, the edge detector is disabled by ackbtn_disable, and it is
+enabled by ackbtn_enable.  So, the status is cleared correctly.
+
+** New board support: FST-01SZ
+It's still under development.  Programming-wise, it will be kept same.
+
+
+* Major changes in Chopstx 1.10
+
+  Released 2018-09-29
+
+** Function chopstx_intr_wait is not deprecated, now
+Once, it was said that it's deprecated, but it's active again
+to match the new function of chopstx_intr_done.
+
+** API change: chopstx_poll, chopstx_intr_wait, chopstx_intr_done
+To avoid spurious interrupt, we introduce new function
+chopstx_intr_done, which should be called after interrupt handling.
+
+** New driver: Acknowledge button for FST-01SZ
+The use case is waiting user's acknowledge.  We use EXTI interrupt
+feature of STM32.
+
+
+* Major changes in Chopstx 1.9
+
+  Released 2018-05-09
+
+** GD32F103 support
+GD32F103 is an alternative implementation of STM32F103 by Giga Device,
+which can run at 96MHz.
+
+** Minor USB driver fix for STM32F103/GD32F103
+BTABLE setting should be done at initialization, not at USB RESET.
+
+** Minor SYS driver fix for GD32F103
+flash_protect should check FLASH_CR_OPTWRE.
+
+** Minor ADC driver change for GD32F103
+ADC on GD32F103 is another implementation and its behavior is somewhat
+different.  It requires waits after enabling.  So, we use continuous
+sampling, instead of start and stop for each sample.  Still, we
+observe enough noise (> 4.7 bit/byte) for each ADC sampling.
+
+
+* Major changes in Chopstx 1.8
+
+  Released 2018-01-19
+
+** Minor driver API fix
+In version 1.6, part of mcu/stm32f103.h was moved into mcu/cortex-m.h
+and mcu/stm32.h.  Now, mcu/stm32f103.h automatically includes
+mcu/cortex-m.h and mcu/stm32.h, so that it doesn't break existing
+applications.
+
+
+* Major changes in Chopstx 1.7
+
+  Released 2017-12-19
+
+** Fix: timer wakeup
+Timer expiration had a bug.  When it is waken up, the wake up doesn't
+handle as a timer expiration when there are multiple threads on same
+timing of expire.  It confuses as if it were forced wakeup.
+
+** New driver: USART for STM32
+USART driver for STM32 is added.
+
+
+* Major changes in Chopstx 1.6
+
+  Released 2017-11-24
+
+** Fix cancellation
+In Chopstx 1.4 and 1.5, cancellation doesn't work for real MCU.  This
+is due to the change of chx_sched interface, introduced for GNU/Linux
+emulation.  This bug is fixed.
+
+** New feature: sleep mode
+New function chopstx_conf_idle is added to support sleep.  Note that
+use of sleep by this feature requires careful preparation.  For
+example, enabling sleep, a board with no RESET pin cannot be debugged
+by JTAG/SWD.  Setting of DBGMCU_CR (0xE0042004) is required beforehand
+(hardware default is zero).
+
+** API change: chopstx_poll
+This is a kind of clarification.  The third argument is now an array
+of constant pointers.  We don't touch the array itself, just use it.
+This allows having the array in read-only memory and can contribute
+less use of RAM.
+
+** USB API changes
+INTR_REQ_USB is now defined by usb_lld.h.  Enumeration type of
+DEVICE_STATE now has USB_DEVICE_STATE_ prefix.
+
+** USB driver change
+USB suspend and wakeup events are supported for STM32F103.
+
+
 * Major changes in Chopstx 1.5
 
   Released 2017-10-10
@@ -302,11 +491,11 @@ Vectored Interrupt Controller (NVIC), in the ARM v7-M Architecture
 Reference Manual.  The subsection, B3.4.1, Theory of operation,
 explains how it works.
 
-
 ** gpio_init change
 Now, gpi_init support AFIO mapping and another GPIO (GPIO_OTHER)
 settings.
 
-Local Variables:
+
-mode: outline
+# Local Variables:
-End:
+# mode: outline
+# End:

README

@@ -1,15 +1,15 @@
 Chopstx - Threads and only Threads
-							 Version 1.5
+							Version 1.15
-							  2017-10-10
+							  2018-05-14
 							Niibe Yutaka
 					     Flying Stone Technology
 
 What's Chopstx?
 ===============
 
-Chopstx is an RT thread library for STM32F103 (ARM Cortex-M3),
+Chopstx is an RT thread library for STM32F103 and GD32F103 (ARM
-STM32F030 (ARM Cortex-M0), MKL27Z (ARM Cortex-M0plus), and
+Cortex-M3), STM32F030 (ARM Cortex-M0), MKL27Z (ARM Cortex-M0plus),
-emulation on GNU/Linux.
+STM32L432 (ARM Cortex-M4), and emulation on GNU/Linux.
 
 While most RTOSes come with many features, drivers, and protocol
 stacks, Chopstx just offers a simple RT thread library.
@@ -17,12 +17,17 @@ stacks, Chopstx just offers a simple RT thread library.
 With Chopstx, interrupt handling is also done by a thread.  This
 enables coherent code for ease of maintenance.
 
-This library is _not_ related to the hand game:
+While threads are important, we don't need more threads than
+necessary.  Chopstx provides a feature of poll, so that we can
+handle multiple events by a single thread.
+
+
+Note that this library is _not_ related to the hand game:
 
     https://en.wikipedia.org/wiki/Chopsticks_(hand_game)
 
-Thanks to Yao Wei and Enrico Zini for giving me the opportunity
+Thanks to Yao Wei and Enrico Zini for giving me an opportunity
-visiting the wiki page.
+visiting the wiki page above, when my children were playing the game.
 
 
 License
@@ -44,6 +49,8 @@ CDC-ACM demo by:
    $ ln -sf ../board/board-olimex-stm32-h103.h board.h
    $ make
 
+If you want to try GD32F103, Add -DMHZ=96 to DEFS in Makefile.
+
 For a specific board named FSM-55, an example of LED matrix dynamic
 driver is provided.  See the directory: example-fsm-55.
 

VERSION

@@ -1 +1 @@
-release/1.5
+release/1.16

board/board-blue-pill-g.h

@@ -0,0 +1,42 @@
+#define BOARD_NAME "Blue Pill GD32F103"
+/* http://wiki.stm32duino.com/index.php?title=Blue_Pill */
+/* echo -n "Blue Pill GD32F103" | shasum -a 256 | sed -e 's/^.*\(........\)  -$/\1/' */
+#define BOARD_ID    0xed415594
+
+#define MCU_STM32F1_GD32F1 1
+#define STM32_USBPRE                    STM32_USBPRE_DIV2
+#define STM32_ADCPRE                    STM32_ADCPRE_DIV8
+
+#define MCU_STM32F1 1
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              12
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOC_BASE
+#define GPIO_LED_CLEAR_TO_EMIT          13
+#define GPIO_USB_BASE   GPIOA_BASE
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ *
+ * Port C setup.
+ * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ * PCx  - input with pull-up
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFE7FF
+#define VAL_GPIO_USB_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x88811888      /* PA15...PA8 */
+
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x88388888      /* PC15...PC8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPCRST)

board/board-blue-pill.h

@@ -3,6 +3,7 @@
 /* echo -n "Blue Pill" | shasum -a 256 | sed -e 's/^.*\(........\)  -$/\1/' */
 #define BOARD_ID    0xa1099d43
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -12,13 +13,14 @@
 #define GPIO_LED_BASE   GPIOC_BASE
 #define GPIO_LED_CLEAR_TO_EMIT          13
 #define GPIO_USB_BASE   GPIOA_BASE
-#define GPIO_USB_SET_TO_ENABLE          12
 #undef  GPIO_OTHER_BASE
 
 /*
  * Port A setup.
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ *
+ * Port C setup.
  * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF)
  * ------------------------ Default
  * PAx  - input with pull-up

board/board-cq-starm.h

@@ -1,6 +1,7 @@
 #define BOARD_NAME "CQ STARM"
 #define BOARD_ID    0xc5480875
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1

board/board-fst-01-00.h

@@ -1,6 +1,7 @@
 #define BOARD_NAME "FST-01-00"
 #define BOARD_ID    0x613870a9
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -18,7 +19,7 @@
  * PA0  - input with pull-up.  AN0
  * PA1  - input with pull-up.  AN1
  * PA8  - Push pull output 50MHz (LED 1:ON 0:OFF)
- * PA10 - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * PA10 - Push pull output 50MHz (USB 1:ON 0:OFF) default 1
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
  * ------------------------ Default

board/board-fst-01.h

@@ -2,6 +2,7 @@
 #define BOARD_ID    0x696886af
 /* echo -n "FST-01" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -24,7 +25,7 @@
  * PA5  - Alternate Push pull output (SPI1_SCK)
  * PA6  - Alternate Push pull output (SPI1_MISO)
  * PA7  - Alternate Push pull output (SPI1_MOSI)
- * PA10 - Push pull output   (USB 1:ON 0:OFF)
+ * PA10 - Push pull output   (USB 1:ON 0:OFF) default 1
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
  * ------------------------ Default
@@ -70,6 +71,7 @@
  * Those will be removed soon, once such an driver will be improved
  * in new style.
  */
+#if defined(PINPAD_CIR_SUPPORT)
 /* For pin-cir settings of Gnuk */
 #define TIMx                  TIM2
 #define INTR_REQ_TIM          TIM2_IRQ
@@ -82,3 +84,4 @@
 #define ENABLE_RCC_APB1
 #define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM2EN
 #define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM2RST
+#endif

board/board-fst-01g.h

@@ -2,6 +2,7 @@
 #define BOARD_ID    0x8801277f
 /* echo -n "FST-01G" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -70,7 +71,7 @@
  * Those will be removed soon, once such an driver will be improved
  * in new style.
  */
-/* For pin-cir settings of Gnuk */
+#if defined(PINPAD_CIR_SUPPORT)
 #define TIMx                  TIM2
 #define INTR_REQ_TIM          TIM2_IRQ
 #define AFIO_EXTICR_INDEX     0
@@ -82,3 +83,4 @@
 #define ENABLE_RCC_APB1
 #define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM2EN
 #define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM2RST
+#endif

board/board-fst-01sz.h

@@ -0,0 +1,43 @@
+#define BOARD_NAME "FST-01SZ"
+#define BOARD_ID    0x7e6fb084
+/* echo -n "FST-01SZ" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
+
+#define MCU_STM32F1_GD32F1 1
+#define STM32_USBPRE                    STM32_USBPRE_DIV2
+#define STM32_ADCPRE                    STM32_ADCPRE_DIV8
+
+#define MCU_STM32F1 1
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              8
+#define STM32_HSECLK                    12000000
+
+#define GPIO_LED_BASE   GPIOA_BASE
+#define GPIO_LED_SET_TO_EMIT            8
+#define GPIO_USB_BASE   GPIOA_BASE
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up: AN0 for NeuG
+ * PA1  - input with pull-up: AN1 for NeuG
+ * PA3  - input with pull-up: Hall effect sensor output
+ * PA8  - Push pull output 10MHz 0 default (LED 1:ON 0:OFF)
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up.
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFE6FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88811881      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
+
+/*
+ * Board specific information other than clock and GPIO initial
+ * setting should not be in board-*.h, but each driver should include
+ * such specific information by itself.
+ */

board/board-gnukey-ds.h

@@ -0,0 +1,39 @@
+#define BOARD_NAME "Gnukey DS"
+#define BOARD_ID    0x67ee65a3
+/* echo -n "Gnukey DS" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
+
+#define MCU_STM32F1 1
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9 // 8MHz * 9 = 72 MHz
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOA_BASE
+#define GPIO_LED_SET_TO_EMIT            3
+#define GPIO_USB_BASE   GPIOA_BASE
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up: AN0 for NeuG
+ * PA1  - input with pull-up: AN1 for NeuG
+ * PA2  - input with pull-up: Hall effect sensor output
+ * PA3  - Push pull output 10MHz 0 default (LED 1:ON 0:OFF)
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up.
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFE7F7      /* 0/1 Pull Down/Up */
+#define VAL_GPIO_LED_CRL            0x88881888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88811888      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
+
+/*
+ * Board specific information other than clock and GPIO initial
+ * setting should not be in board-*.h, but each driver should include
+ * such specific information by itself.
+ */

board/board-maple-mini.h

@@ -1,6 +1,7 @@
 #define BOARD_NAME "Maple Mini"
 #define BOARD_ID    0x7a445272
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -29,11 +30,11 @@
 /*
  * Port B setup.
  * PB1  - Push pull output 50MHz (LED 1:ON 0:OFF)
- * PB9  - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * PB9  - Push pull output 50MHz (USB 0:ON 1:OFF) default 0
  * ------------------------ Default
  * PBx  - input with pull-up
  */
-#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_ODR            0xFFFFFDFF
 #define VAL_GPIO_LED_CRL            0x88888838      /*  PB7...PB0 */
 #define VAL_GPIO_LED_CRH            0x88888838      /* PB15...PB8 */
 

board/board-nitrokey-start.h

@@ -1,6 +1,7 @@
 #define BOARD_NAME "NITROKEY-START"
 #define BOARD_ID    0xad1e7ebd
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -28,7 +29,7 @@
  * PA10 - floating input
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
- * PA15 - Push pull output  (USB_EN 1:ON 0:OFF)
+ * PA15 - Push pull output  (USB_EN 1:ON 0:OFF) default 1
  * ------------------------ Default
  * PA8  - input with pull-up.
  * PA9  - floating input.

board/board-olimex-stm32-h103.h

@@ -1,6 +1,7 @@
 #define BOARD_NAME "Olimex STM32-H103"
 #define BOARD_ID    0xf92bb594
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -19,22 +20,14 @@
  * PC1  - input with pull-up.  AN11 for NeuG
  * PC6  - input without pull-up/down
  * PC7  - input without pull-up/down
- * PC11 - Open-drain output 50MHz (USB disconnect).
+ * PC11 - Open-drain output 50MHz (USB 0:ON 1:OFF)  default 0
  * PC12 - Push Pull output 50MHz (LED).
  * ------------------------ Default
  * PCx  - input with pull-up
  */
-#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_ODR            0xFFFFF7FF
 #define VAL_GPIO_LED_CRL            0x44888888      /*  PC7...PC0 */
 #define VAL_GPIO_LED_CRH            0x88837888      /* PC15...PC8 */
 
 #define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPCEN
 #define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPCRST
-
-/* NeuG settings for ADC2.  */
-#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \
-                              | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5)
-#define NEUG_ADC_SETTING2_SMPR2 0
-#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)   \
-                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11)
-#define NEUG_ADC_SETTING2_NUM_CHANNELS 2

board/board-st-dongle.h

@@ -2,6 +2,7 @@
 /* echo -n "ST Dongle" | shasum -a 256 | sed -e 's/^.*\(........\)  -$/\1/' */
 #define BOARD_ID    0x2cd4e471
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -21,7 +22,7 @@
  * PA9  - Push pull output 50MHz (LED 1:ON 0:OFF)
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
- * PA15 - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * PA15 - Push pull output 50MHz (USB 1:ON 0:OFF) default 1
  * ------------------------ Default
  * PAx  - input with pull-up
  */

board/board-st-nucleo-f103.h

@@ -11,11 +11,14 @@
  *
  * At CN10, connect USB cable
  *  Vbus RED   --> 10 NC   ----------> CN7 (6 E5V)
- *  D+   GREEN --> 12 PA11 ---[1K5]--> CN6 (4 3V3)
+ *  D+   GREEN --> 12 PA12 ---[1K5]--> CN6 (4 3V3)
- *  D-   WHITE --> 14 PA12
+ *  D-   WHITE --> 14 PA11
+ *                 16 PB12 (USART3-CK) ---> smartcard CK
+ *                 18
  *  GND  BLACK --> 20 GND
  */
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -25,21 +28,49 @@
 #define GPIO_LED_BASE   GPIOA_BASE
 #define GPIO_LED_SET_TO_EMIT            5
 #undef  GPIO_USB_BASE		/* No external DISCONNECT/RENUM circuit.  */
-#undef  GPIO_OTHER_BASE
+#define GPIO_OTHER_BASE GPIOB_BASE
 
 /*
  * Port A setup.
- * PA0  - input with pull-up.  AN0
+ * PA0  - Input with pull-up                       USART2-CTS
- * PA1  - input with pull-up.  AN1
+ * PA1  - Alternate function push pull output 2MHz USART2-RTS
- * PA5  - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * PA2  - Alternate function push pull output 2MHz USART2-TX
+ * PA3  - Input with pull-up                       USART2-RX
+ * PA4  - Alternate function push pull output 2MHz USART2-CK
+ * PA5  - Push pull output 2MHz (LED 1:ON 0:OFF)
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
  * ------------------------ Default
  * PAx  - input with pull-up
  */
 #define VAL_GPIO_LED_ODR            0xFFFFE7FF
-#define VAL_GPIO_LED_CRL            0x88388888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRL            0x882A8AA8      /*  PA7...PA0 */
 #define VAL_GPIO_LED_CRH            0x88811888      /* PA15...PA8 */
 
-#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+/*
-#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
+ * Port B setup.
+ * PB0  - input with pull-up: AN8 for NeuG
+ * PB1  - input with pull-up: AN9 for NeuG
+ * ---
+ * ---
+ * PB4  - Input with pull-up: Card insertion detect: 0 when detected
+ * ---
+ * PB6  - Output push pull 2MHz: Vcc for card: default 0
+ * ---
+ * PB8  - Output push pull 2MHz: Vpp for card: default 0
+ * PB9  - Output push pull 2MHz: RST for card: default 0
+ * PB10 - Alternate function open-drain output 50MHz USART3-TX
+ * PB11 - Input with pull-up                         USART3-RX
+ * PB12 - Alternate function push pull output  50MHz USART3-CK
+ * PB13 - Input with pull-up                         USART3-CTS
+ * PB14 - Alternate function push pull output  50MHz USART3-RTS
+ * ---
+ * ------------------------ Default
+ * PBx  - input with pull-up.
+ */
+#define VAL_GPIO_OTHER_ODR          0xFFFFFCBF
+#define VAL_GPIO_OTHER_CRL          0x82888888      /*  PB7...PB0 */
+#define VAL_GPIO_OTHER_CRH          0x8B8B8F22      /* PB15...PB8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)

board/board-st-nucleo-l432.h

@@ -0,0 +1,75 @@
+#define BOARD_NAME "ST Nucleo L432"
+#define BOARD_ID    0x3a8d5116
+
+/*
+ * When using USB, please add USB cable to ST Nucleo L432.
+ *
+ * At CN4, connect USB cable, only when ST Link is not connected
+ *  Vbus RED   -->  4
+ *
+ * At CN3, connect USB cable
+ *  D-   WHITE --> 13 PA11
+ *  D+   GREEN -->  5 PA12
+ *  GND  BLACK -->  4 GND
+ *
+ * Smartcard VCC:    PA3
+ * Smartcard GND:    GND --+
+ * Smartcard RST:    PA1   |
+ * Smartcard VPP:    PA4   |
+ * Smartcard CLK:    PA8   |
+ * Smartcard I/O:    PA9   |
+ *                   GND --+
+ * Smartcard DETECT: PA0
+ */
+
+#define MCU_STM32L4 1
+
+#define GPIO_LED_BASE   GPIOB_BASE
+#define GPIO_LED_SET_TO_EMIT            3
+#undef  GPIO_USB_BASE		/* No external DISCONNECT/RENUM circuit.  */
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/*
+ * Port A setup.
+ *
+ * MODER: 10 10 - 10 10 - 10 11 - 10 10    11 11 - 11 01 - 01 10 - 01 00
+ *
+ * PA0  - Input with pull-up: Card insertion detect: 0 when detected
+ * PA1  - Output push-pull default 0: Card RST
+ * PA2  - USART2-TX (AF7): output push-pull
+ * PA3  - Output push-pull default 0: Card Vcc
+ * PA4  - Output push-pull default 0: Card Vpp
+ * PA8  - USART1-CK (AF7): output push-pull: Card CLK
+ * PA9  - USART1-TX (AF7): output(input) Open-drain pull-up: Card I/O
+ * PA11 - USBDM (AF10): input/output
+ * PA12 - USBDP (AF10): input/output
+ * PA13 - SWDIO (AF0)
+ * PA14 - SWDCLK (AF0)
+ * PA15 - USART2-RX (AF3): input with pull-up
+ * ------------------------ Default
+ * PAx  - analog input
+ */
+#define VAL_GPIO_OTHER_MODER   0xAABAFD64
+#define VAL_GPIO_OTHER_OTYPER  0x00000200
+#define VAL_GPIO_OTHER_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIO_OTHER_PUPDR   0x40040001
+#define VAL_GPIO_OTHER_AFRL    0x00000700
+#define VAL_GPIO_OTHER_AFRH    0x300AA077
+
+/*
+ * Port B setup.
+ *
+ * MODER: 11 11 - 11 11 - 11 11 - 11 11    11 11 - 11 11 - 01 11 - 11 11
+ *
+ * PB3  - ON (LED 1:ON 0:OFF)
+ * ------------------------ Default
+ * PBx  - analog input
+ */
+#define VAL_GPIO_LED_MODER   0xFFFFFF7F
+#define VAL_GPIO_LED_OTYPER  0x00000000
+#define VAL_GPIO_LED_OSPEEDR 0x00000000
+#define VAL_GPIO_LED_PUPDR   0x00000000
+#define VAL_GPIO_LED_AFRL    0x00000000
+#define VAL_GPIO_LED_AFRH    0x00000000
+
+#define RCC_AHB2_GPIO   (RCC_AHB2_GPIOA | RCC_AHB2_GPIOB)

board/board-stbee-mini.h

@@ -1,6 +1,7 @@
 #define BOARD_NAME "STBee Mini"
 #define BOARD_ID    0x1f341961
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -51,7 +52,7 @@
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
  * PA13 - Open Drain output (LED1 0:ON 1:OFF)
- * PA14 - Push pull output  (USB ENABLE 0:DISABLE 1:ENABLE)
+ * PA14 - Push pull output  (USB  1:ON 0:OFF) default 1
  * PA15 - Open Drain output (LED2 0:ON 1:OFF)
  */
 #define VAL_GPIO_LED_ODR            0xFFFFE77F

board/board-stbee.h

@@ -1,6 +1,9 @@
 #define BOARD_NAME "STBee"
 #define BOARD_ID    0x945c37e8
 
+#define MCU_STM32F1 1
+#define STM32F10X_HD		/* High-density device */
+
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              6
 #define STM32_HSECLK                    12000000
@@ -26,9 +29,9 @@
 
 /*
  * Port D setup.
- * PD3  - Push pull output  (USB_DISC 1:USB-DISABLE 0:USB-ENABLE) 2MHz
+ * PD3  - Push pull output  (USB 1:OFF 0:ON) 2MHz default 0
  * PD4  - Open Drain output 2MHz (LED1).
  */
-#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_ODR            0xFFFFFFF7
 #define VAL_GPIO_LED_CRL            0x88862888      /*  PD7...PD0 */
 #define VAL_GPIO_LED_CRH            0x88888888      /* PD15...PD8 */

board/board-stm32-primer2.h

@@ -1,6 +1,9 @@
 #define BOARD_NAME "STM32 Primer2"
 #define BOARD_ID    0x21e5798d
 
+#define MCU_STM32F1 1
+#define STM32F10X_HD		/* High-density device */
+
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              6
 #define STM32_HSECLK                    12000000
@@ -27,11 +30,11 @@
 
 /*
  * Port D setup.
- * PD3  - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * PD3  - Push pull output 50MHz (USB 0:ON 1:OFF) default 0
  * ------------------------ Default
  * PDx  - input with pull-up
  */
-#define VAL_GPIO_USB_ODR            0xFFFFFFFF
+#define VAL_GPIO_USB_ODR            0xFFFFFFF7
 #define VAL_GPIO_USB_CRL            0x88883888      /*  PD7...PD0 */
 #define VAL_GPIO_USB_CRH            0x88888888      /* PD15...PD8 */
 

board/board-stm32f0-discovery.h

@@ -1,8 +1,6 @@
 #define BOARD_NAME "STM32F0 Discovery"
 #define BOARD_ID    0xde4b4bc1
 
-#define MCU_STM32F0 1
-
 /*
  * Running at 48MHz with HSI as clock source.
  * 

board/board-stm8s-discovery.h

@@ -1,6 +1,7 @@
 #define BOARD_NAME "STM8S Discovery"
 #define BOARD_ID    0x2f0976bb
 
+#define MCU_STM32F1 1
 #define STM32F10X_MD		/* Medium-density device */
 
 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
@@ -43,7 +44,7 @@
 #define VAL_GPIO_OTHER_CRH 0x88888888      /* PB15...PB8 */
 
 
-/* For pin-cir settings of Gnuk */
+#if defined(PINPAD_CIR_SUPPORT)
 #define TIMx                  TIM3
 #define INTR_REQ_TIM          TIM3_IRQ
 #define AFIO_EXTICR_INDEX     1
@@ -57,3 +58,4 @@
 #define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM3RST
 #define AFIO_MAPR_SOMETHING   AFIO_MAPR_TIM3_REMAP_PARTIALREMAP
                               /* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */
+#endif

chopstx-cortex-m.c

@@ -1,8 +1,8 @@
 /*
  * chopstx-cortex-m.c - Threads and only threads: Arch specific code
- *                      for Cortex-M0/M3
+ *                      for Cortex-M0/M3/M4
  *
- * Copyright (C) 2013, 2014, 2015, 2016, 2017
+ * Copyright (C) 2013, 2014, 2015, 2016, 2017, 2018, 2019
  *               Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -24,10 +24,17 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 
+/* Data Memory Barrier.  */
+static void
+chx_dmb (void)
+{
+  asm volatile ("dmb"  : : : "memory");
+}
+
 /* Saved registers on the stack.  */
 struct chx_stack_regs {
   uint32_t reg[8];	       /* r0, r1, r2, r3, r12, lr, pc, xpsr */
@@ -77,7 +84,7 @@ struct chx_stack_regs {
 #define CPU_EXCEPTION_PRIORITY_INTERRUPT     0x40
 #define CPU_EXCEPTION_PRIORITY_PENDSV        0x80
 #define CPU_EXCEPTION_PRIORITY_SVC           0x80 /* No use in this arch */
-#elif defined(__ARM_ARCH_7M__)
+#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
 #define CPU_EXCEPTION_PRIORITY_SVC           0x30
 
 #define CPU_EXCEPTION_PRIORITY_INHIBIT_SCHED 0x40
@@ -99,30 +106,34 @@ struct chx_stack_regs {
  * System tick
  */
 /* SysTick registers.  */
-static volatile uint32_t *const SYST_CSR = (uint32_t *)0xE000E010;
+struct SYST {
-static volatile uint32_t *const SYST_RVR = (uint32_t *)0xE000E014;
+  volatile uint32_t CSR;
-static volatile uint32_t *const SYST_CVR = (uint32_t *)0xE000E018;
+  volatile uint32_t RVR;
+  volatile uint32_t CVR;
+  const uint32_t CALIB;
+};
+static struct SYST *const SYST = (struct SYST *)0xE000E010;
 
 static void
 chx_systick_reset (void)
 {
-  *SYST_RVR = 0;
+  SYST->RVR = 0;
-  *SYST_CVR = 0;
+  SYST->CVR = 0;
-  *SYST_CSR = 7;
+  SYST->CSR = 7;
 }
 
 static void
 chx_systick_reload (uint32_t ticks)
 {
-  *SYST_RVR = ticks;
+  SYST->RVR = ticks;
-  *SYST_CVR = 0;  /* write (any) to clear the counter to reload.  */
+  SYST->CVR = 0;  /* write (any) to clear the counter to reload.  */
-  *SYST_RVR = 0;
+  SYST->RVR = 0;
 }
 
 static uint32_t
 chx_systick_get (void)
 {
-  return *SYST_CVR;
+  return SYST->CVR;
 }
 
 static uint32_t usec_to_ticks (uint32_t usec)
@@ -168,10 +179,13 @@ chx_clr_intr (uint8_t irq_num)
   NVIC_ICPR (irq_num) = 1 << (irq_num & 0x1f);
 }
 
-static void
+static int
 chx_disable_intr (uint8_t irq_num)
 {
+  int already_disabled = !!(NVIC_ICER (irq_num) & (1 << (irq_num & 0x1f)));
+
   NVIC_ICER (irq_num) = 1 << (irq_num & 0x1f);
+  return already_disabled;
 }
 
 static void
@@ -229,18 +243,6 @@ chx_cpu_sched_unlock (void)
 }
 
 
-static void __attribute__((naked, used))
-idle (void)
-{
-#if defined(USE_WFI_FOR_IDLE)
-  for (;;)
-    asm volatile ("wfi" : : : "memory");
-#else
-  for (;;);
-#endif
-}
-
-
 void
 chx_handle_intr (void)
 {
@@ -298,8 +300,8 @@ chx_request_preemption (uint16_t prio)
  * 	AAPCS: ARM Architecture Procedure Call Standard
  *
  * Returns:
- *          1 on wakeup by others.
+ *       >= 1 on wakeup by others, value means ticks remained for sleep.
- *          0 on normal wakeup.
+ *          0 on normal wakeup (timer expiration, lock acquirement).
  *         -1 on cancellation.
  */
 static uintptr_t __attribute__ ((naked, noinline))
@@ -307,27 +309,26 @@ chx_sched (uint32_t yield)
 {
   register struct chx_thread *tp asm ("r0");
 
-#if defined(__ARM_ARCH_7M__)
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
   asm volatile (
-	"svc	#0\n\t"
+	"svc	#0"
-	"bx	lr"
 	: "=r" (tp) : "0" (yield): "memory");
 #else
   register uint32_t arg_yield asm ("r1");
 
   /* Build stack data as if it were an exception entry.  */
   /*
-   * r0:  0                     scratch
+   * r0:  TP                    scratch
    * r1:  0                     scratch
    * r2:  0                     scratch
    * r3:  0                     scratch
    * r12: 0                     scratch
    * lr   as-is
-   * pc:  return address (= lr)
+   * pc:  return address (= .L_CONTEXT_SWITCH_FINISH)
    * psr: INITIAL_XPSR          scratch
    */
   asm ("mov	r1, lr\n\t"
-       "mov	r2, r1\n\t"
+       "ldr	r2, =.L_CONTEXT_SWITCH_FINISH\n\t"
        "mov	r3, #128\n\t"
        "lsl	r3, #17\n\t"
        "push	{r1, r2, r3}\n\t"
@@ -335,16 +336,16 @@ chx_sched (uint32_t yield)
        "mov	r2, r1\n\t"
        "mov	r3, r1\n\t"
        "push	{r1, r2, r3}\n\t"
-       "push	{r1, r2}"
+       "mov	r1, r0\n\t"
-       : /* no output*/
-       : /* no input */
-       : "r1", "r2", "r3", "memory");
-
-  /* Save registers onto CHX_THREAD struct.  */
-  asm ("mov	r1, r0\n\t"
        "ldr	r2, =running\n\t"
        "ldr	r0, [r2]\n\t"
-       "add	r0, #20\n\t"
+       "push	{r0, r3}"
+       :  "=r" (tp), "=r" (arg_yield)
+       : "0" (yield)
+       : "r2", "r3", "memory");
+
+  /* Save registers onto CHX_THREAD struct.  */
+  asm ("add	r0, #20\n\t"
        "stm	r0!, {r4, r5, r6, r7}\n\t"
        "mov	r2, r8\n\t"
        "mov	r3, r9\n\t"
@@ -353,8 +354,8 @@ chx_sched (uint32_t yield)
        "mov	r6, sp\n\t"
        "stm	r0!, {r2, r3, r4, r5, r6}\n\t"
        "sub	r0, #56"
-       : "=r" (tp), "=r" (arg_yield)
+       : /* no output */
-       : "0" (yield)
+       : "r" (tp)
        : "r2", "r3", "r4", "r5", "r6", "r7", "memory");
 
   if (arg_yield)
@@ -383,7 +384,7 @@ chx_sched (uint32_t yield)
 		/* Spawn an IDLE thread.  */
 		"ldr	r1, =__main_stack_end__\n\t"
 		"mov	sp, r1\n\t"
-		"ldr	r0, =idle\n\t"	     /* PC = idle */
+		"ldr	r0, =chx_idle\n\t" /* PC = idle */
 		/**/
 		/* Unmask interrupts.  */
 		"cpsie	i\n\t"
@@ -391,11 +392,7 @@ chx_sched (uint32_t yield)
 
 		/* Normal context switch */
 	"0:\n\t"
-		"add	r0, #16\n\t" /* ->V */
+		"add	r0, #20\n\t"
-		"ldr	r1, [r0]\n\t"
-		"str	r1, [sp]\n\t"
-		/**/
-		"add	r0, #4\n\t"
 		"ldm	r0!, {r4, r5, r6, r7}\n\t"
 		"ldm	r0!, {r1, r2, r3}\n\t"
 		"mov	r8, r1\n\t"
@@ -455,12 +452,17 @@ chx_sched (uint32_t yield)
 		"mov	r12, r0\n\t"
 		"pop	{r0, r1, r2, r3}\n\t"
 		"add	sp, #12\n\t"
-		"pop	{pc}"
+		"pop	{pc}\n\t"
+	".L_CONTEXT_SWITCH_FINISH:"
 		: "=r" (tp)		/* Return value in R0 */
 		: "0" (tp)
 		: "memory");
 #endif
 
+  asm volatile ("bx	lr"
+		: "=r" (tp)
+		: "0" (tp->v)
+		: "memory");
   return (uintptr_t)tp;
 }
 
@@ -631,7 +633,7 @@ preempt (void)
 	"mov	r3, #0\n\t"
 	"stm	r0!, {r1, r2, r3}\n\t"
 	"stm	r0!, {r1, r2, r3}\n\t"
-	"ldr	r1, =idle\n\t"	     /* PC = idle */
+	"ldr	r1, =chx_idle\n\t" /* PC = idle */
 	"mov	r2, #0x010\n\t"
 	"lsl	r2, r2, #20\n\t" /* xPSR = T-flag set (Thumb) */
 	"stm	r0!, {r1, r2}\n\t"
@@ -649,7 +651,7 @@ preempt (void)
 	: /* no output */ : "r" (tp) : "memory");
 }
 
-#if defined(__ARM_ARCH_7M__)
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
 /*
  * System call: switch to another thread.
  * There are two cases:
@@ -675,7 +677,8 @@ svc (void)
        "mov	r5, r11\n\t"
        "mrs	r6, PSP\n\t" /* r13(=SP) in user space.  */
        "stm	r1!, {r2, r3, r4, r5, r6}\n\t"
-       "ldr	r1, [r6]"
+       "ldr	r1, [r6]\n\t"
+       "str	r0, [r6]"
        : "=r" (tp), "=r" (orig_r0)
        : /* no input */
        : "r2", "r3", "r4", "r5", "r6", "memory");
@@ -697,10 +700,6 @@ svc (void)
     }
 
   asm volatile (
-	"cbz	r0, 0f\n\t"
-	"ldr	r1, [r0, #16]\n\t" /* ->V */
-	"str	r1, [sp]\n\t"
-    "0:\n\t"
 	"b	.L_CONTEXT_SWITCH"
 	: /* no output */ : "r" (tp) : "memory");
 }

chopstx-gnu-linux.c

@@ -2,7 +2,7 @@
  * chopstx-gnu-linux.c - Threads and only threads: Arch specific code
  *                       for GNU/Linux emulation
  *
- * Copyright (C) 2017 Flying Stone Technology
+ * Copyright (C) 2017, 2018, 2019 Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -23,7 +23,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 
@@ -32,6 +32,13 @@
 #include <signal.h>
 #include <sys/time.h>
 
+/* Data Memory Barrier.  */
+static void
+chx_dmb (void)
+{
+}
+
+
 static sigset_t ss_cur;
 
 static void
@@ -82,10 +89,13 @@ chx_clr_intr (uint8_t irq_num)
   (void)irq_num;
 }
 
-static void
+static int
 chx_disable_intr (uint8_t irq_num)
 {
+  int already_disabled = sigismember (&ss_cur, irq_num);
+
   sigaddset (&ss_cur, irq_num);
+  return already_disabled;
 }
 
 static void

chopstx.c

@@ -1,7 +1,7 @@
 /*
  * chopstx.c - Threads and only threads.
  *
- * Copyright (C) 2013, 2014, 2015, 2016, 2017
+ * Copyright (C) 2013, 2014, 2015, 2016, 2017, 2018, 2019
  *               Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -23,7 +23,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 
@@ -79,7 +79,11 @@ chx_fatal (uint32_t err_code)
 #include "chopstx-cortex-m.h"
 #endif
 
-/* RUNNING: the current thread. */
+/* ALLOW_SLEEP for the idle thread.  */
+int chx_allow_sleep;
+static struct chx_spinlock chx_enable_sleep_lock;
+
+/* RUNNING: the current thread.  */
 struct chx_thread *running;
 
 struct chx_queue {
@@ -103,7 +107,7 @@ static struct chx_queue q_intr;
 static void chx_request_preemption (uint16_t prio);
 static int chx_wakeup (struct chx_pq *p);
 static struct chx_thread * chx_timer_insert (struct chx_thread *tp, uint32_t usec);
-static void chx_timer_dequeue (struct chx_thread *tp);
+static uint32_t chx_timer_dequeue (struct chx_thread *tp);
 
 
 
@@ -345,29 +349,35 @@ chx_timer_insert (struct chx_thread *tp, uint32_t usec)
 }
 
 
-static void
+static uint32_t
 chx_timer_dequeue (struct chx_thread *tp)
 {
   struct chx_thread *tp_prev;
+  uint32_t ticks_remained;
 
   chx_spin_lock (&q_timer.lock);
+  ticks_remained = chx_systick_get ();
   tp_prev = (struct chx_thread *)tp->prev;
   if (tp_prev == (struct chx_thread *)&q_timer.q)
     {
       if (tp->next == (struct chx_pq *)&q_timer.q)
-	chx_set_timer (tp_prev, 0); /* Cancel timer*/
+	chx_systick_reload (0);                      /* Cancel timer.  */
       else
-	{			/* Update timer.  */
+	chx_systick_reload (ticks_remained + tp->v); /* Update timer.  */
-	  uint32_t next_ticks = chx_systick_get () + tp->v;
-
-	  chx_set_timer (tp_prev, next_ticks);
-	}
     }
   else
-    tp_prev->v += tp->v;
+    {
+      struct chx_pq *p;
+
+      for (p = q_timer.q.next; p != (struct chx_pq *)tp; p = p->next)
+	ticks_remained += p->v;
+
+      tp_prev->v += tp->v;
+    }
   ll_dequeue ((struct chx_pq *)tp);
   tp->v = 0;
   chx_spin_unlock (&q_timer.lock);
+  return ticks_remained;
 }
 
 
@@ -382,6 +392,7 @@ chx_timer_expired (void)
     {
       uint32_t next_tick = tp->v;
 
+      tp->v = (uintptr_t)0;
       chx_ready_enqueue (tp);
       if (tp == running)	/* tp->flag_sched_rr == 1 */
 	prio = MAX_PRIO;
@@ -398,6 +409,7 @@ chx_timer_expired (void)
 	       tp = tp_next)
 	    {
 	      next_tick = tp->v;
+	      tp->v = (uintptr_t)0;
 	      tp_next = (struct chx_thread *)tp->next;
 	      ll_dequeue ((struct chx_pq *)tp);
 	      chx_ready_enqueue (tp);
@@ -440,6 +452,7 @@ chx_init (struct chx_thread *tp)
 {
   chx_prio_init ();
   chx_init_arch (tp);
+  chx_spin_init (&chx_enable_sleep_lock);
 
   q_ready.q.next = q_ready.q.prev = (struct chx_pq *)&q_ready.q;
   chx_spin_init (&q_ready.lock);
@@ -495,9 +508,11 @@ chx_wakeup (struct chx_pq *pq)
       tp = px->master;
       if (tp->state == THREAD_WAIT_POLL)
 	{
-	  tp->v = (uintptr_t)1;
 	  if (tp->parent == &q_timer.q)
-	    chx_timer_dequeue (tp);
+	    tp->v = (uintptr_t)chx_timer_dequeue (tp);
+	  else
+	    tp->v = (uintptr_t)1;
+
 	  chx_ready_enqueue (tp);
 	  if (!running || tp->prio > running->prio)
 	    yield = 1;
@@ -552,23 +567,26 @@ chx_exit (void *retval)
 
 /*
  * Lower layer mutex unlocking.  Called with schedule lock held.
+ * Return PRIO of the thread which is waken up.
  */
 static chopstx_prio_t
 chx_mutex_unlock (chopstx_mutex_t *mutex)
 {
   struct chx_thread *tp;
-  chopstx_prio_t prio = 0;
 
   mutex->owner = NULL;
   running->mutex_list = mutex->list;
   mutex->list = NULL;
 
   tp = (struct chx_thread *)ll_pop (&mutex->q);
-  if (tp)
+  if (!tp)
+    return 0;
+  else
     {
       uint16_t newprio = running->prio_orig;
       chopstx_mutex_t *m;
 
+      tp->v = (uintptr_t)0;
       chx_ready_enqueue (tp);
 
       /* Examine mutexes we hold, and determine new priority for running.  */
@@ -579,11 +597,8 @@ chx_mutex_unlock (chopstx_mutex_t *mutex)
       /* Then, assign it.  */
       running->prio = newprio;
 
-      if (prio < tp->prio)
+      return tp->prio;
-	prio = tp->prio;
     }
-
-  return prio;
 }
 
 #define CHOPSTX_PRIO_MASK ((1 << CHOPSTX_PRIO_BITS) - 1)
@@ -671,6 +686,11 @@ chx_snooze (uint32_t state, uint32_t *usec_p)
   r = chx_sched (CHX_SLEEP);
   if (r == 0)
     *usec_p -= usec0;
+  else if (r > 0)
+    {
+      *usec_p -= (usec0 - r / MHZ);
+      r = 1;
+    }
 
   return r;
 }
@@ -795,9 +815,10 @@ chopstx_mutex_lock (chopstx_mutex_t *mutex)
 	  if (tp0->state == THREAD_WAIT_TIME
 	      || tp0->state == THREAD_WAIT_POLL)
 	    {
-	      tp0->v = (uintptr_t)1;
 	      if (tp0->parent == &q_timer.q)
-		chx_timer_dequeue (tp0);
+		tp0->v = (uintptr_t)chx_timer_dequeue (tp0);
+	      else
+		tp0->v = (uintptr_t)1;
 
 	      chx_ready_enqueue (tp0);
 	      tp0 = NULL;
@@ -961,6 +982,7 @@ chx_cond_hook (struct chx_px *px, struct chx_poll_head *pd)
     { /* Condition doesn't met.
        * Register the proxy to wait for the condition.
        */
+      pc->ready = 0;
       chx_cpu_sched_lock ();
       chx_spin_lock (&pc->cond->lock);
       ll_prio_enqueue ((struct chx_pq *)px, &pc->cond->q);
@@ -983,16 +1005,21 @@ chx_cond_hook (struct chx_px *px, struct chx_poll_head *pd)
 void
 chopstx_claim_irq (chopstx_intr_t *intr, uint8_t irq_num)
 {
+  int intr_before_claim;
+
   intr->type = CHOPSTX_POLL_INTR;
   intr->ready = 0;
   intr->irq_num = irq_num;
 
   chx_cpu_sched_lock ();
   chx_spin_lock (&q_intr.lock);
-  chx_disable_intr (irq_num);
+  intr_before_claim = chx_disable_intr (irq_num);
+  chx_clr_intr (irq_num);
   chx_set_intr_prio (irq_num);
   chx_spin_unlock (&q_intr.lock);
   chx_cpu_sched_unlock ();
+  if (intr_before_claim)
+    intr->ready = 1;
 }
 
 
@@ -1004,10 +1031,19 @@ chx_intr_hook (struct chx_px *px, struct chx_poll_head *pd)
   chopstx_testcancel ();
   chx_cpu_sched_lock ();
   px->v = intr->irq_num;
-  chx_spin_lock (&q_intr.lock);
+  if (intr->ready)
-  ll_prio_enqueue ((struct chx_pq *)px, &q_intr.q);
+    {
-  chx_enable_intr (intr->irq_num);
+      chx_spin_lock (&px->lock);
-  chx_spin_unlock (&q_intr.lock);
+      (*px->counter_p)++;
+      chx_spin_unlock (&px->lock);
+    }
+  else
+    {
+      chx_spin_lock (&q_intr.lock);
+      ll_prio_enqueue ((struct chx_pq *)px, &q_intr.q);
+      chx_enable_intr (intr->irq_num);
+      chx_spin_unlock (&q_intr.lock);
+    }
   chx_cpu_sched_unlock ();
 }
 
@@ -1026,6 +1062,26 @@ chopstx_intr_wait (chopstx_intr_t *intr)
 }
 
 
+/**
+ * chopstx_intr_done - Finish an IRQ handling
+ * @intr: Pointer to INTR structure
+ *
+ * Finish for the interrupt @intr occurred.
+ *
+ */
+void
+chopstx_intr_done (chopstx_intr_t *intr)
+{
+  chx_dmb ();
+
+  if (intr->ready)
+    {
+      chx_clr_intr (intr->irq_num);
+      intr->ready = 0;
+    }
+}
+
+
 /**
  * chopstx_cleanup_push - Register a clean-up
  * @clp: Pointer to clean-up structure
@@ -1190,6 +1246,7 @@ chx_join_hook (struct chx_px *px, struct chx_poll_head *pd)
     { /* Not yet exited.
        * Register the proxy to wait for TP's exit.
        */
+      pj->ready = 0;
       px->v = (uintptr_t)tp;
       chx_spin_lock (&q_join.lock);
       ll_prio_enqueue ((struct chx_pq *)px, &q_join.q);
@@ -1307,7 +1364,8 @@ chx_proxy_init (struct chx_px *px, uint32_t *cp)
 
 /**
  * chopstx_poll - wait for condition variable, thread's exit, or IRQ
- * @usec_p: Pointer to usec for timeout.  Forever if NULL.
+ * @usec_p: Pointer to usec for timeout.  Forever if NULL.  It is
+ * updated on return
  * @n: Number of poll descriptors
  * @pd_array: Pointer to an array of poll descriptor pointer which
  * should be one of:
@@ -1316,7 +1374,7 @@ chx_proxy_init (struct chx_px *px, uint32_t *cp)
  * Returns number of active descriptors.
  */
 int
-chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *pd_array[])
+chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *const pd_array[])
 {
   uint32_t counter = 0;
   int i;
@@ -1324,6 +1382,7 @@ chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *pd_array[])
   struct chx_poll_head *pd;
   int r = 0;
 
+  chx_dmb ();
   chopstx_testcancel ();
 
   for (i = 0; i < n; i++)
@@ -1332,7 +1391,6 @@ chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *pd_array[])
   for (i = 0; i < n; i++)
     {
       pd = pd_array[i];
-      pd->ready = 0;
       px[i].ready_p = &pd->ready;
       if (pd->type == CHOPSTX_POLL_COND)
 	chx_cond_hook (&px[i], pd);
@@ -1376,6 +1434,7 @@ chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *pd_array[])
       while (r == 0);
     }
 
+  chx_dmb ();
   for (i = 0; i < n; i++)
     {
       pd = pd_array[i];
@@ -1396,9 +1455,7 @@ chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *pd_array[])
 	{
 	  struct chx_intr *intr = (struct chx_intr *)pd;
 
-	  if (intr->ready)
+	  if (intr->ready == 0)
-	    chx_clr_intr (intr->irq_num);
-	  else
 	    {
 	      chx_spin_lock (&q_intr.lock);
 	      ll_dequeue ((struct chx_pq *)&px[i]);
@@ -1469,3 +1526,38 @@ chopstx_setpriority (chopstx_prio_t prio_new)
 
   return prio_orig;
 }
+
+
+/**
+ * chopstx_conf_idle - Configure IDLE thread
+ * @enable_sleep: Enable sleep on idle or not
+ *
+ * If @enable_sleep is > 0, allow sleep for the idle thread.
+ *
+ * Behavior of @enable_sleep >= 1 depends on MCU.
+ *
+ * For STM32F0, 1 for Sleep (CPU clock OFF only), 2 for Stop (Wakeup
+ * by EXTI, voltage regulator on), 3 for Stop (Wakeup by EXTI, voltage
+ * regulator low-power), 4 for Standby (Wakeup by RESET, voltage
+ * regulator off).
+ *
+ * For STM32F103, 1 for normal sleep, and 2 for sleep with lower 8MHz
+ * clock.
+ *
+ * Return previous value of @enable_sleep.
+ */
+extern void chx_sleep_mode (int enable_sleep);
+
+int
+chopstx_conf_idle (int enable_sleep)
+{
+  int r;
+
+  chx_spin_lock (&chx_enable_sleep_lock);
+  r = chx_allow_sleep;
+  chx_sleep_mode (enable_sleep);
+  chx_allow_sleep = enable_sleep;
+  chx_spin_unlock (&chx_enable_sleep_lock);
+
+  return r;
+}

chopstx.h

@@ -1,7 +1,7 @@
 /*
  * chopstx.h - Threads and only threads.
  *
- * Copyright (C) 2013, 2016 Flying Stone Technology
+ * Copyright (C) 2013, 2016, 2017, 2018  Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -22,7 +22,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 
@@ -155,9 +155,13 @@ typedef struct chx_intr chopstx_intr_t;
 
 void chopstx_claim_irq (chopstx_intr_t *intr, uint8_t irq_num);
 
-void chopstx_intr_wait (chopstx_intr_t *intr); /* DEPRECATED */
+void chopstx_intr_wait (chopstx_intr_t *intr);
+void chopstx_intr_done (chopstx_intr_t *intr);
 
 
-int chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *pd_array[]);
+int chopstx_poll (uint32_t *usec_p, int n,
+		  struct chx_poll_head *const pd_array[]);
+
+int chopstx_conf_idle (int enable_sleep);
 
 #define CHOPSTX_THREAD_SIZE 64

contrib/ackbtn-stm32f103.c

@@ -0,0 +1,116 @@
+/*
+ * ackbtn-stm32f103.c - Acknowledge button support for STM32F103
+ *
+ * Copyright (C) 2018  g10 Code GmbH
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * recipients of GNU GPL by a written offer.
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <chopstx.h>
+#include <mcu/stm32f103.h>
+
+#include "board.h"
+#include "sys.h"
+
+/*
+ * All EXTI registers (EXTI_IMR, EXTI_EMR, EXTI_PR , EXTI_RTSR, and
+ * EXTI_FTSR) have same structure, where each bit of X is used for
+ * line X, from 0 up to 19.
+ *
+ * We use 31-bit of PIN_CONFIG to represent if it's for rising edge or
+ * falling edge.
+ */
+static uint32_t pin_config;
+#define PINCFG_EDGE        0x80000000
+#define PINCFG_EDGE_RISING PINCFG_EDGE
+
+void
+ackbtn_init (chopstx_intr_t *intr)
+{
+  uint8_t irq_num;
+  uint32_t afio_exticr_index;
+  uint32_t afio_exticr_extiX_pY;
+
+  switch (SYS_BOARD_ID)
+    {
+    case BOARD_ID_FST_01:
+    case BOARD_ID_FST_01G:
+    case BOARD_ID_GNUKEY_DS:
+      /* PA2 can be connected to a hall sensor or a switch */
+      afio_exticr_index = 0;
+      afio_exticr_extiX_pY = AFIO_EXTICR1_EXTI2_PA;
+      irq_num = EXTI2_IRQ;
+      pin_config = 0x0004; /* EXTI_PR_PR2 == EXTI_IMR_MR2 == EXTI_RTSR_TR2 */
+      pin_config |= PINCFG_EDGE_RISING;
+      break;
+
+    case BOARD_ID_FST_01SZ:
+    default:
+      /* PA3 is connected to a hall sensor DRV5032FA */
+      afio_exticr_index = 0;
+      afio_exticr_extiX_pY = AFIO_EXTICR1_EXTI3_PA;
+      irq_num = EXTI3_IRQ;
+      pin_config = 0x0008; /* EXTI_PR_PR3 == EXTI_IMR_MR3 == EXTI_RTSR_TR3 */
+      pin_config |= PINCFG_EDGE_RISING;
+      break;
+    }
+
+  /* Configure EXTI line */
+  if (afio_exticr_extiX_pY)
+    AFIO->EXTICR[afio_exticr_index] |= afio_exticr_extiX_pY;
+
+  /* Interrupt is masked, now */
+  EXTI->IMR &= ~(pin_config & ~PINCFG_EDGE);
+
+  chopstx_claim_irq (intr, irq_num);
+}
+
+void
+ackbtn_enable (void)
+{
+  /* Clear pending interrupt */
+  EXTI->PR |= (pin_config & ~PINCFG_EDGE);
+  /* Enable interrupt, clearing the mask */
+  EXTI->IMR |= (pin_config & ~PINCFG_EDGE);
+
+  /* Configure which edge is detected */
+  if ((pin_config & PINCFG_EDGE))
+    EXTI->RTSR |= (pin_config & ~PINCFG_EDGE);
+  else
+    EXTI->FTSR |= (pin_config & ~PINCFG_EDGE);
+}
+
+void
+ackbtn_disable (void)
+{
+  /* Disable interrupt having the mask */
+  EXTI->IMR &= ~(pin_config & ~PINCFG_EDGE);
+  /* Clear pending interrupt */
+  EXTI->PR |= (pin_config & ~PINCFG_EDGE);
+
+  /* Disable edge detection */
+  EXTI->RTSR &= ~(pin_config & ~PINCFG_EDGE);
+  EXTI->FTSR &= ~(pin_config & ~PINCFG_EDGE);
+}

contrib/ackbtn.h

@@ -0,0 +1,3 @@
+void ackbtn_init (chopstx_intr_t *intr);
+void ackbtn_enable (void);
+void ackbtn_disable (void);

contrib/adc-gnu-linux.c

@@ -24,7 +24,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 

contrib/adc-mkl27z.c

@@ -25,7 +25,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 
@@ -295,19 +295,20 @@ adc_stop (void)
 int
 adc_wait_completion (void)
 {
-  struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&adc_intr };
   int i;
 
   while (1)
     {
       /* Wait DMA completion */
-      chopstx_poll (NULL, 1, pd_array);
+      chopstx_intr_wait (&adc_intr);
 
       DMA0->DSR_BCR = (1 << 24);
       DMA1->DSR_BCR = (1 << 24);
 
       adc_stop_conversion ();
 
+      chopstx_intr_done (&adc_intr);
+
       for (i = 0; i < adc.count; i++)
 	*adc.p++ = (uint8_t)adc.buf[i];
 

contrib/adc-stm32f103.c

@@ -3,7 +3,7 @@
  *                   In this ADC driver, there are NeuG specific parts.
  *                   You need to modify to use this as generic ADC driver.
  *
- * Copyright (C) 2011, 2012, 2013, 2015, 2016
+ * Copyright (C) 2011, 2012, 2013, 2015, 2016, 2017, 2018
  *               Free Software Initiative of Japan
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -25,7 +25,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 
@@ -34,6 +34,8 @@
 #include <chopstx.h>
 #include <mcu/stm32f103.h>
 #include "adc.h"
+#include "board.h"
+#include "sys.h"
 
 #define STM32_ADC_ADC1_DMA_PRIORITY         2
 
@@ -46,6 +48,7 @@
 #define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)
 #define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)
 #define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)
+#define ADC_SMPR2_SMP_AN8(n)    ((n) << 24)
 #define ADC_SMPR2_SMP_AN9(n)    ((n) << 27)
 
 #define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
@@ -60,6 +63,7 @@
 #define ADC_CHANNEL_IN0         0
 #define ADC_CHANNEL_IN1         1
 #define ADC_CHANNEL_IN2         2
+#define ADC_CHANNEL_IN8         8
 #define ADC_CHANNEL_IN9         9
 #define ADC_CHANNEL_IN10        10
 #define ADC_CHANNEL_IN11        11
@@ -67,7 +71,9 @@
 #define ADC_CHANNEL_VREFINT     17
 
 #define DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
+#ifndef MCU_STM32F1_GD32F1
 #define DELIBARATELY_DO_IT_WRONG_START_STOP
+#endif
 
 #ifdef DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
 #define ADC_SAMPLE_VREF ADC_SAMPLE_1P5
@@ -112,6 +118,8 @@ adc_init (void)
 
   ADC1->CR1 = 0;
   ADC1->CR2 = ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
+
   ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
   while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
     ;
@@ -122,6 +130,8 @@ adc_init (void)
 
   ADC2->CR1 = 0;
   ADC2->CR2 = ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
+
   ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
   while ((ADC2->CR2 & ADC_CR2_RSTCAL) != 0)
     ;
@@ -135,15 +145,13 @@ adc_init (void)
   return 0;
 }
 
-#include "board.h"
-#include "sys.h"
-
 static void
 get_adc_config (uint32_t config[4])
 {
   config[2] = ADC_SQR1_NUM_CH(2);
   switch (SYS_BOARD_ID)
     {
+    case BOARD_ID_FST_01G:
     case BOARD_ID_FST_01:
       config[0] = 0;
       config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
@@ -169,14 +177,22 @@ get_adc_config (uint32_t config[4])
 		| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2);
       break;
 
+    case BOARD_ID_ST_NUCLEO_F103:
+      config[0] = 0;
+      config[1] = ADC_SMPR2_SMP_AN8(ADC_SAMPLE_1P5)
+		| ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5);
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN8)
+		| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9);
+      break;
+
     case BOARD_ID_CQ_STARM:
     case BOARD_ID_FST_01_00:
     case BOARD_ID_MAPLE_MINI:
     case BOARD_ID_STM32_PRIMER2:
     case BOARD_ID_STM8S_DISCOVERY:
     case BOARD_ID_ST_DONGLE:
-    case BOARD_ID_ST_NUCLEO_F103:
     case BOARD_ID_NITROKEY_START:
+    case BOARD_ID_FST_01SZ:
     default:
       config[0] = 0;
       config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
@@ -202,24 +218,26 @@ adc_start (void)
 
   RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
 
-  ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
-	       | ADC_CR1_SCAN);
-  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
-	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
   ADC1->SMPR1 = NEUG_ADC_SETTING1_SMPR1;
   ADC1->SMPR2 = NEUG_ADC_SETTING1_SMPR2;
   ADC1->SQR1 = ADC_SQR1_NUM_CH(NEUG_ADC_SETTING1_NUM_CHANNELS);
   ADC1->SQR2 = 0;
   ADC1->SQR3 = NEUG_ADC_SETTING1_SQR3;
-
+  ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
-  ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
 	       | ADC_CR1_SCAN);
-  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+  chopstx_usec_wait (1000);
+
   ADC2->SMPR1 = config[0];
   ADC2->SMPR2 = config[1];
   ADC2->SQR1 = config[2];
   ADC2->SQR2 = 0;
   ADC2->SQR3 = config[3];
+  ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+	       | ADC_CR1_SCAN);
+  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
 
 #ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
   /*
@@ -298,11 +316,10 @@ int
 adc_wait_completion (void)
 {
   uint32_t flags;
-  struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&adc_intr };
 
   while (1)
     {
-      chopstx_poll (NULL, 1, pd_array);
+      chopstx_intr_wait (&adc_intr);
       flags = DMA1->ISR & STM32_DMA_ISR_MASK; /* Channel 1 interrupt cause.  */
       /*
        * Clear interrupt cause of channel 1.
@@ -311,6 +328,7 @@ adc_wait_completion (void)
        * and TEIF.
        */
       DMA1->IFCR = (flags & ~1);
+      chopstx_intr_done (&adc_intr);
 
       if ((flags & STM32_DMA_ISR_TEIF) != 0)  /* DMA errors  */
 	{

contrib/usart-common.c

@@ -0,0 +1,428 @@
+static void *usart_main (void *arg);
+
+/*
+ * Ring buffer
+ */
+#define MAX_RB_BUF 1024
+
+struct rb {
+  uint8_t *buf;
+  chopstx_mutex_t m;
+  chopstx_cond_t data_available;
+  chopstx_cond_t space_available;
+  uint32_t head  :10;
+  uint32_t tail  :10;
+  uint32_t size  :10;
+  uint32_t full  : 1;
+  uint32_t empty : 1;
+};
+/* full && empty -> data is consumed fully */
+
+/*
+ * Note: size = 1024 can still work, regardless of the limit of 10-bit.
+ */
+static void
+rb_init (struct rb *rb, uint8_t *p, uint16_t size)
+{
+  rb->buf = p;
+  rb->size = size;
+  chopstx_mutex_init (&rb->m);
+  chopstx_cond_init (&rb->data_available);
+  chopstx_cond_init (&rb->space_available);
+  rb->head = rb->tail = 0;
+  rb->full = 0;
+  rb->empty = 1;
+}
+
+static void
+rb_add (struct rb *rb, uint8_t v)
+{
+  rb->buf[rb->tail++] = v;
+  if (rb->tail == rb->size)
+    rb->tail = 0;
+  if (rb->tail == rb->head)
+    rb->full = 1;
+  else
+    rb->full = 0;
+  rb->empty = 0;
+}
+
+static uint8_t
+rb_del (struct rb *rb)
+{
+  uint32_t v = rb->buf[rb->head++];
+
+  if (rb->head == rb->size)
+    rb->head = 0;
+  if (rb->head == rb->tail)
+    rb->empty = 1;
+  rb->full = 0;
+
+  return v;
+}
+
+/*
+ * Application: consumer
+ * Hardware:    generator
+ */
+static int
+rb_ll_put (struct rb *rb, uint8_t v)
+{
+  int r;
+
+  chopstx_mutex_lock (&rb->m);
+  if (rb->full && !rb->empty)
+    r = -1;
+  else
+    {
+      r = 0;
+      rb_add (rb, v);
+      chopstx_cond_signal (&rb->data_available);
+    }
+  chopstx_mutex_unlock (&rb->m);
+  return r;
+}
+
+/*
+ * Application: generator
+ * Hardware:    consumer
+ */
+static int
+rb_ll_get (struct rb *rb)
+{
+  int r;
+
+  chopstx_mutex_lock (&rb->m);
+  if (rb->empty)
+    {
+      if (!rb->full)
+	rb->full = 1;
+      r = -1;
+    }
+  else
+    r = rb_del (rb);
+  chopstx_cond_signal (&rb->space_available);
+  chopstx_mutex_unlock (&rb->m);
+  return r;
+}
+
+static void
+rb_ll_flush (struct rb *rb)
+{
+  chopstx_mutex_lock (&rb->m);
+  while (!rb->empty)
+    rb_del (rb);
+  chopstx_cond_signal (&rb->space_available);
+  chopstx_mutex_unlock (&rb->m);
+}
+
+/*
+ * Application: consumer
+ * Hardware:    generator
+ */
+static int
+rb_read (struct rb *rb, uint8_t *buf, uint16_t buflen)
+{
+  int i = 0;
+
+  chopstx_mutex_lock (&rb->m);
+  while (rb->empty)
+    chopstx_cond_wait (&rb->data_available, &rb->m);
+
+  while (i < buflen)
+    {
+      buf[i++] = rb_del (rb);
+      if (rb->empty)
+	break;
+    }
+  chopstx_cond_signal (&rb->space_available);
+  chopstx_mutex_unlock (&rb->m);
+
+  return i;
+}
+
+/*
+ * Application: generator
+ * Hardware:    consumer
+ */
+static void
+rb_write (struct rb *rb, uint8_t *buf, uint16_t buflen)
+{
+  int i = 0;
+
+  chopstx_mutex_lock (&rb->m);
+
+  do
+    {
+      while (rb->full && !rb->empty)
+	chopstx_cond_wait (&rb->space_available, &rb->m);
+
+      while (i < buflen)
+	{
+	  rb_add (rb, buf[i++]);
+	  if (rb->full)
+	    {
+	      chopstx_cond_signal (&rb->data_available);
+	      break;
+	    }
+	}
+    }
+  while (i < buflen);
+
+  if (i)
+    chopstx_cond_signal (&rb->data_available);
+  chopstx_mutex_unlock (&rb->m);
+}
+
+static int
+rb_empty_check (void *arg)
+{
+  struct rb *rb = arg;
+  return rb->empty == 0;
+}
+
+/* Can be used two ways:
+ *
+ *   When the ring buffer is rb_a2h:
+ *     Hardware-side polling if data is available from application.
+ *
+ *   When the ring buffer is rb_h2a:
+ *     Application-side polling if data is available from hardware.
+ */
+static void
+rb_get_prepare_poll (struct rb *rb, chopstx_poll_cond_t *poll_desc)
+{
+  poll_desc->type  = CHOPSTX_POLL_COND;
+  poll_desc->ready = 0;
+  poll_desc->cond  = &rb->data_available;
+  poll_desc->mutex = &rb->m;
+  poll_desc->check = rb_empty_check;
+  poll_desc->arg   = rb;
+}
+
+const struct usart_stat *
+usart_stat (uint8_t dev_no)
+{
+  if (dev_no < USART_DEVNO_START || dev_no > USART_DEVNO_END)
+    return NULL;
+  return usart_array[dev_no - USART_DEVNO_START].stat;
+}
+
+static struct USART *
+get_usart_dev (uint8_t dev_no)
+{
+  if (dev_no < USART_DEVNO_START || dev_no > USART_DEVNO_END)
+    return NULL;
+  return usart_array[dev_no - USART_DEVNO_START].USART;
+}
+
+static struct rb *
+get_usart_rb_h2a (uint8_t dev_no)
+{
+  if (dev_no < USART_DEVNO_START || dev_no > USART_DEVNO_END)
+    return NULL;
+  return usart_array[dev_no - USART_DEVNO_START].rb_h2a;
+}
+
+static struct rb *
+get_usart_rb_a2h (uint8_t dev_no)
+{
+  if (dev_no < USART_DEVNO_START || dev_no > USART_DEVNO_END)
+    return NULL;
+  return usart_array[dev_no - USART_DEVNO_START].rb_a2h;
+}
+
+static struct chx_intr *
+get_usart_intr (uint8_t dev_no)
+{
+  if (dev_no < USART_DEVNO_START || dev_no > USART_DEVNO_END)
+    return NULL;
+  return usart_array[dev_no - USART_DEVNO_START].intr;
+}
+
+void
+usart_init (uint16_t prio, uintptr_t stack_addr, size_t stack_size,
+	    int (*cb) (uint8_t dev_no, uint16_t notify_bits))
+{
+  usart_init0 (cb);
+  chopstx_create (prio, stack_addr, stack_size, usart_main, NULL);
+}
+
+static int (*ss_notify_callback) (uint8_t dev_no, uint16_t notify_bits);
+
+static struct chx_poll_head *usart_poll[NUM_USART*2];
+
+static void *
+usart_main (void *arg)
+{
+  int i;
+
+  (void)arg;
+
+  for (i = 0; i < NUM_USART; i++)
+    if (usart_array[i].tx_ready)
+      {
+	*usart_array[i].tx_ready = 1;
+	rb_init (usart_array[i].rb_a2h, usart_array[i].buf_a2h, BUF_A2H_SIZE);
+	rb_init (usart_array[i].rb_h2a, usart_array[i].buf_h2a, BUF_H2A_SIZE);
+	rb_get_prepare_poll (usart_array[i].rb_a2h, usart_array[i].app_write_event);
+      }
+
+  while (1)
+    {
+      int n = 0;
+
+      for (i = 0; i < NUM_USART; i++)
+	if (usart_array[i].tx_ready)
+	  {
+	    usart_poll[n++] = (struct chx_poll_head *)usart_array[i].intr;
+	    if (*usart_array[i].tx_ready)
+	      usart_poll[n++] = (struct chx_poll_head *)usart_array[i].app_write_event;
+	    else
+	      usart_array[i].app_write_event->ready = 0;
+	  }
+
+      chopstx_poll (NULL, n, usart_poll);
+
+      for (i = 0; i < NUM_USART; i++)
+	if (usart_array[i].tx_ready)
+	  {
+	    int tx_done = 0;
+
+	    if (usart_array[i].intr->ready)
+	      {
+		tx_done = handle_intr (usart_array[i].USART,
+				       usart_array[i].rb_h2a, usart_array[i].stat);
+		*usart_array[i].tx_ready |= tx_done;
+		chopstx_intr_done (usart_array[i].intr);
+	      }
+
+	    if (tx_done || (*usart_array[i].tx_ready
+			    && usart_array[i].app_write_event->ready))
+	      *usart_array[i].tx_ready = handle_tx (usart_array[i].USART,
+						    usart_array[i].rb_a2h, usart_array[i].stat);
+	  }
+    }
+
+  return NULL;
+}
+
+int
+usart_read (uint8_t dev_no, char *buf, uint16_t buflen)
+{
+  struct rb *rb = get_usart_rb_h2a (dev_no);
+
+  if (rb == NULL)
+    return -1;
+
+  if (buf == NULL && buflen == 0)
+    {
+      rb_ll_flush (rb);
+      return 0;
+    }
+  else
+    return rb_read (rb, (uint8_t *)buf, buflen);
+}
+
+void
+usart_read_prepare_poll (uint8_t dev_no, chopstx_poll_cond_t *poll_desc)
+{
+  struct rb *rb = get_usart_rb_h2a (dev_no);
+
+  if (rb == NULL)
+    return;
+
+  rb_get_prepare_poll (rb, poll_desc);
+}
+
+int
+usart_read_ext (uint8_t dev_no, char *buf, uint16_t buflen, uint32_t *timeout_p)
+{
+  chopstx_poll_cond_t poll_desc;
+  struct chx_poll_head *ph[] = { (struct chx_poll_head *)&poll_desc };
+  int r;
+  struct rb *rb = get_usart_rb_h2a (dev_no);
+
+  if (rb == NULL)
+    return -1;
+
+  rb_get_prepare_poll (rb, &poll_desc);
+  r = chopstx_poll (timeout_p, 1, ph);
+  if (r == 0)
+    return 0;
+  else
+    return rb_read (rb, (uint8_t *)buf, buflen);
+}
+
+static void
+usart_wait_write_completion (struct rb *rb)
+{
+  chopstx_mutex_lock (&rb->m);
+  while (!(rb->empty && rb->full))
+    chopstx_cond_wait (&rb->space_available, &rb->m);
+  chopstx_mutex_unlock (&rb->m);
+}
+
+int
+usart_write (uint8_t dev_no, char *buf, uint16_t buflen)
+{
+  struct rb *rb = get_usart_rb_a2h (dev_no);
+
+  if (rb == NULL)
+    return -1;
+
+  if (buf == NULL && buflen == 0)
+    rb_ll_flush (rb);
+  else
+    {
+      struct USART *USARTx = get_usart_dev (dev_no);
+      int smartcard_mode = ((USARTx->CR3 & USART_CR3_SCEN) != 0);
+
+      if (smartcard_mode)
+	usart_config_recv_enable (USARTx, 0);
+
+      rb_write (rb, (uint8_t *)buf, buflen);
+
+      if (smartcard_mode)
+	{
+	  usart_wait_write_completion (rb);
+	  usart_config_recv_enable (USARTx, 1);
+	}
+    }
+
+  return 0;
+}
+
+
+int
+usart_config_baud (uint8_t dev_no, uint8_t baud_spec)
+{
+  struct USART *USARTx = get_usart_dev (dev_no);
+  uint32_t save_bits;
+  int i;
+
+  for (i = 0; i < NUM_BAUD; i++)
+    if (brr_table[i].baud_spec == baud_spec)
+      break;
+
+  if (i >= NUM_BAUD)
+    return -1;
+
+  save_bits = USARTx->CR1 & (USART_CR1_TE | USART_CR1_RE);
+  USARTx->CR1 &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_UE);
+  USARTx->BRR = brr_table[i].brr_value;
+  USARTx->CR1 |= (save_bits | USART_CR1_UE);
+  return 0;
+}
+
+
+void
+usart_config_clken (uint8_t dev_no, int on)
+{
+  struct USART *USARTx = get_usart_dev (dev_no);
+
+  if (on)
+    USARTx->CR2 |= (1 << 11);
+  else
+    USARTx->CR2 &= ~(1 << 11);
+}

contrib/usart-stm32f103.c

@@ -0,0 +1,561 @@
+/*
+ * usart-stm32.c - USART driver for STM32F103 (USART2 and USART3)
+ *
+ * Copyright (C) 2017, 2019  g10 Code GmbH
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * recipients of GNU GPL by a written offer.
+ *
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <mcu/stm32.h>
+#include <contrib/usart.h>
+
+/* Hardware registers */
+struct USART {
+  volatile uint32_t SR;
+  volatile uint32_t DR;
+  volatile uint32_t BRR;
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t CR3;
+  volatile uint32_t GTPR;
+};
+
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define USART2 ((struct USART *)USART2_BASE)
+#define USART3 ((struct USART *)USART3_BASE)
+
+#define USART_SR_CTS	(1 << 9)
+#define USART_SR_LBD	(1 << 8)
+#define USART_SR_TXE	(1 << 7)
+#define USART_SR_TC	(1 << 6)
+#define USART_SR_RXNE	(1 << 5)
+#define USART_SR_IDLE	(1 << 4)
+#define USART_SR_ORE	(1 << 3)
+#define USART_SR_NE	(1 << 2)
+#define USART_SR_FE	(1 << 1)
+#define USART_SR_PE	(1 << 0)
+
+
+#define USART_CR1_UE		(1 << 13)
+#define USART_CR1_M		(1 << 12)
+#define USART_CR1_WAKE		(1 << 11)
+#define USART_CR1_PCE		(1 << 10)
+#define USART_CR1_PS		(1 <<  9)
+#define USART_CR1_PEIE		(1 <<  8)
+#define USART_CR1_TXEIE		(1 <<  7)
+#define USART_CR1_TCIE		(1 <<  6)
+#define USART_CR1_RXNEIE	(1 <<  5)
+#define USART_CR1_IDLEIE	(1 <<  4)
+#define USART_CR1_TE		(1 <<  3)
+#define USART_CR1_RE		(1 <<  2)
+#define USART_CR1_RWU		(1 <<  1)
+#define USART_CR1_SBK		(1 <<  0)
+
+#define USART_CR3_CTSE		(1 <<  9)
+#define USART_CR3_RTSE		(1 <<  8)
+#define USART_CR3_SCEN		(1 <<  5)
+#define USART_CR3_NACK		(1 <<  4)
+
+
+static struct usart_stat usart2_stat;
+static struct usart_stat usart3_stat;
+
+static struct chx_intr usart2_intr;
+static struct chx_intr usart3_intr;
+
+#define BUF_A2H_SIZE 256
+#define BUF_H2A_SIZE 512
+static uint8_t buf_usart2_rb_a2h[BUF_A2H_SIZE];
+static uint8_t buf_usart2_rb_h2a[BUF_H2A_SIZE];
+static uint8_t buf_usart3_rb_a2h[BUF_A2H_SIZE];
+static uint8_t buf_usart3_rb_h2a[BUF_H2A_SIZE];
+
+static struct rb usart2_rb_a2h;
+static struct rb usart2_rb_h2a;
+static struct rb usart3_rb_a2h;
+static struct rb usart3_rb_h2a;
+
+static chopstx_poll_cond_t usart2_app_write_event;
+static chopstx_poll_cond_t usart3_app_write_event;
+
+/* Global variables so that it can be easier to debug.  */
+static int usart2_tx_ready;
+static int usart3_tx_ready;
+
+#define INTR_REQ_USART2 38
+#define INTR_REQ_USART3 39
+
+#define USART_DEVNO_START 2
+#define USART_DEVNO_END 3
+
+struct usart {
+  struct USART *USART;
+  struct chx_intr *intr;
+  uint8_t irq_num;
+  struct usart_stat *stat;
+  struct rb *rb_a2h;
+  struct rb *rb_h2a;
+  uint8_t *buf_a2h;
+  uint8_t *buf_h2a;
+  chopstx_poll_cond_t *app_write_event;
+  int *tx_ready;
+};
+
+
+static const struct usart usart_array[] =
+  {
+   { USART2, &usart2_intr, INTR_REQ_USART2,
+     &usart2_stat, &usart2_rb_a2h, &usart2_rb_h2a, buf_usart2_rb_a2h,
+     buf_usart2_rb_h2a, &usart2_app_write_event, &usart2_tx_ready },
+   { USART3, &usart3_intr, INTR_REQ_USART3,
+     &usart3_stat, &usart3_rb_a2h, &usart3_rb_h2a, buf_usart3_rb_a2h,
+     buf_usart3_rb_h2a, &usart3_app_write_event, &usart3_tx_ready },
+  };
+#define NUM_USART ((int)(sizeof (usart_array) / sizeof (struct usart)))
+
+static int handle_intr (struct USART *USARTx, struct rb *rb2a, struct usart_stat *stat);
+static int handle_tx (struct USART *USARTx, struct rb *rb2h, struct usart_stat *stat);
+static void usart_config_recv_enable (struct USART *USARTx, int on);
+
+struct brr_setting {
+  uint8_t baud_spec;
+  uint32_t brr_value;
+};
+#define NUM_BAUD (int)(sizeof (brr_table) / sizeof (struct brr_setting))
+
+/* We assume 36MHz f_PCLK */
+static const struct brr_setting brr_table[] = {
+  { B600,    (3750 << 4)},
+  { B1200,   (1875 << 4)},
+  { B2400,   ( 937 << 4)|8},
+  { B9600,   ( 234 << 4)|6},
+  { B19200,  ( 117 << 4)|3},
+  { B57600,  (  39 << 4)|1},
+  { B115200, (  19 << 4)|8},
+  { B230400, (   9 << 4)|12},
+  { B460800, (   4 << 4)|14},
+  { B921600, (   2 << 4)|7},
+  { BSCARD1,  ( 232 << 4)|8},	/*   9677 */
+  { BSCARD2,  ( 116 << 4)|4},	/*  19354 */
+  { BSCARD4,  (  58 << 4)|2},	/*  38709 */
+  { BSCARD8,  (  29 << 4)|1},	/*  77419 */
+  { BSCARD12, (  19 << 4)|6},	/* 116129 */
+  { BSCARD16, (  14 << 4)|9},	/* 154506 */
+  { BSCARD20, (  11 << 4)|10},	/* 193548 */
+};
+
+#include "usart-common.c"
+
+static void
+usart_config_recv_enable (struct USART *USARTx, int on)
+{
+  if (on)
+    USARTx->CR1 |= USART_CR1_RE;
+  else
+    USARTx->CR1 &= ~USART_CR1_RE;
+}
+
+
+int
+usart_config (uint8_t dev_no, uint32_t config_bits)
+{
+  struct USART *USARTx = get_usart_dev (dev_no);
+  uint8_t baud_spec = (config_bits & MASK_BAUD);
+  int i;
+  uint32_t cr1_config = (USART_CR1_UE | USART_CR1_RXNEIE | USART_CR1_TE);
+				/* TXEIE/TCIE will be enabled when
+				   putting char */
+				/* No CTSIE, PEIE, IDLEIE, LBDIE */
+  if (USARTx == NULL)
+    return -1;
+
+  /* Disable USART before configure.  */
+  USARTx->CR1 &= ~USART_CR1_UE;
+
+  if (((config_bits & MASK_CS) == CS7 && (config_bits & PARENB))
+      || ((config_bits & MASK_CS) == CS8 && (config_bits & PARENB) == 0))
+    cr1_config &= ~USART_CR1_M;
+  else if ((config_bits & MASK_CS) == CS8)
+    cr1_config |=  USART_CR1_M;
+  else
+    return -1;
+
+  if ((config_bits & PARENB) == 0)
+    cr1_config &= ~(USART_CR1_PCE | USART_CR1_PEIE);
+  else
+    cr1_config |=  (USART_CR1_PCE | USART_CR1_PEIE);
+
+  if ((config_bits & PARODD) == 0)
+    cr1_config &= ~USART_CR1_PS;
+  else
+    cr1_config |=  USART_CR1_PS;
+
+  if ((config_bits & MASK_STOP) == STOP0B5)
+    USARTx->CR2 = (0x1 << 12);
+  else if ((config_bits & MASK_STOP) == STOP1B)
+    USARTx->CR2 = (0x0 << 12);
+  else if ((config_bits & MASK_STOP) == STOP1B5)
+    USARTx->CR2 = (0x3 << 12);
+  else /* if ((config_bits & MASK_STOP) == STOP2B) */
+    USARTx->CR2 = (0x2 << 12);
+
+  for (i = 0; i < NUM_BAUD; i++)
+    if (brr_table[i].baud_spec == baud_spec)
+      break;
+
+  if (i >= NUM_BAUD)
+    return -1;
+
+  USARTx->BRR = brr_table[i].brr_value;
+
+  if ((config_bits & MASK_FLOW))
+    USARTx->CR3 = USART_CR3_CTSE | USART_CR3_RTSE;
+  else
+    USARTx->CR3 = 0;
+
+  if (!(config_bits & MASK_MODE))
+    cr1_config |= USART_CR1_RE;
+
+  USARTx->CR1 = cr1_config;
+
+  /* SCEN (smartcard enable) should be set _after_ CR1.  */
+  if ((config_bits & MASK_MODE))
+    {
+      if ((config_bits & MASK_MODE) == MODE_SMARTCARD)
+	{
+	  USARTx->GTPR = (1 << 8) | 5;
+	  USARTx->CR3 |= (USART_CR3_SCEN | USART_CR3_NACK);
+	}
+      else if ((config_bits & MASK_MODE) == MODE_IRDA)
+	USARTx->CR3 |= (1 << 1);
+      else if ((config_bits & MASK_MODE) == MODE_IRDA_LP)
+	USARTx->CR3 |= (1 << 2) | (1 << 1);
+    }
+
+  return 0;
+}
+
+
+void
+usart_init0 (int (*cb) (uint8_t dev_no, uint16_t notify_bits))
+{
+  int i;
+
+  ss_notify_callback = cb;
+
+  for (i = 0; i < NUM_USART; i++)
+    {
+      if (usart_array[i].stat)
+	usart_array[i].stat->dev_no = i + USART_DEVNO_START;
+      chopstx_claim_irq (usart_array[i].intr, usart_array[i].irq_num);
+    }
+
+  /* Enable USART2 and USART3 clocks, and strobe reset.  */
+  RCC->APB1ENR |= ((1 << 18) | (1 << 17));
+  RCC->APB1RSTR = ((1 << 18) | (1 << 17));
+  RCC->APB1RSTR = 0;
+}
+
+#define UART_STATE_BITMAP_RX_CARRIER (1 << 0)
+#define UART_STATE_BITMAP_TX_CARRIER (1 << 1)
+#define UART_STATE_BITMAP_BREAK      (1 << 2)
+#define UART_STATE_BITMAP_RINGSIGNAL (1 << 3)
+#define UART_STATE_BITMAP_FRAMING    (1 << 4)
+#define UART_STATE_BITMAP_PARITY     (1 << 5)
+#define UART_STATE_BITMAP_OVERRUN    (1 << 6)
+
+static int
+handle_intr (struct USART *USARTx, struct rb *rb2a, struct usart_stat *stat)
+{
+  int tx_ready = 0;
+  uint32_t r = USARTx->SR;
+  int notify_bits = 0;
+  int smartcard_mode = ((USARTx->CR3 & USART_CR3_SCEN) != 0);
+
+  if (smartcard_mode)
+    {
+      if ((r & USART_SR_TC))
+	{
+	  tx_ready = 1;
+	  USARTx->CR1 &= ~USART_CR1_TCIE;
+	}
+    }
+  else
+    {
+      if ((r & USART_SR_TXE))
+	{
+	  tx_ready = 1;
+	  USARTx->CR1 &= ~USART_CR1_TXEIE;
+	}
+    }
+
+  if ((r & USART_SR_RXNE))
+    {
+      uint32_t data = USARTx->DR;
+
+      /* DR register should be accessed even if data is not used.
+       * Its read-access has side effect of clearing error flags.
+       */
+      asm volatile ("" : : "r" (data) : "memory");
+
+      if ((r & USART_SR_NE))
+	stat->err_rx_noise++;
+      else if ((r & USART_SR_FE))
+	{
+	  /* NOTE: Noway to distinguish framing error and break  */
+
+	  stat->rx_break++;
+	  notify_bits |= UART_STATE_BITMAP_BREAK;
+	}
+      else if ((r & USART_SR_PE))
+	{
+	  stat->err_rx_parity++;
+	  notify_bits |= UART_STATE_BITMAP_PARITY;
+	}
+      else
+	{
+	  if ((r & USART_SR_ORE))
+	    {
+	      stat->err_rx_overrun++;
+	      notify_bits |= UART_STATE_BITMAP_OVERRUN;
+	    }
+
+	  /* XXX: if CS is 7-bit, mask it, or else parity bit in upper layer */
+	  if (rb_ll_put (rb2a, (data & 0xff)) < 0)
+	    stat->err_rx_overflow++;
+	  else
+	    stat->rx++;
+	}
+    }
+  else if ((r & USART_SR_ORE))
+    {				/* Clear ORE */
+      uint32_t data = USARTx->DR;
+      asm volatile ("" : : "r" (data) : "memory");
+      stat->err_rx_overrun++;
+      notify_bits |= UART_STATE_BITMAP_OVERRUN;
+    }
+
+  if (notify_bits)
+    {
+      if (ss_notify_callback
+	  && (*ss_notify_callback) (stat->dev_no, notify_bits))
+	stat->err_notify_overflow++;
+    }
+
+  return tx_ready;
+}
+
+static int
+handle_tx (struct USART *USARTx, struct rb *rb2h, struct usart_stat *stat)
+{
+  int tx_ready = 1;
+  int c = rb_ll_get (rb2h);
+
+  if (c >= 0)
+    {
+      uint32_t r;
+      int smartcard_mode = ((USARTx->CR3 & USART_CR3_SCEN) != 0);
+
+      USARTx->DR = (c & 0xff);
+      stat->tx++;
+      r = USARTx->SR;
+      if (smartcard_mode)
+	{
+	  if ((r & USART_SR_TC) == 0)
+	    {
+	      tx_ready = 0;
+	      USARTx->CR1 |= USART_CR1_TCIE;
+	    }
+	}
+      else
+	{
+	  if ((r & USART_SR_TXE) == 0)
+	    {
+	      tx_ready = 0;
+	      USARTx->CR1 |= USART_CR1_TXEIE;
+	    }
+	}
+    }
+
+  return tx_ready;
+}
+
+int
+usart_send_break (uint8_t dev_no)
+{
+  struct USART *USARTx = get_usart_dev (dev_no);
+  if (USARTx == NULL)
+    return -1;
+
+  if ((USARTx->CR1 & 0x01))
+    return 1;	/* Busy sending break, which was requested before.  */
+
+  USARTx->CR1 |= 0x01;
+  return 0;
+}
+
+int
+usart_block_sendrecv (uint8_t dev_no, const char *s_buf, uint16_t s_buflen,
+		      char *r_buf, uint16_t r_buflen,
+		      uint32_t *timeout_block_p, uint32_t timeout_char)
+{
+  uint32_t timeout;
+  uint8_t *p;
+  int len;
+  uint32_t r;
+  uint32_t data;
+  struct USART *USARTx = get_usart_dev (dev_no);
+  int smartcard_mode = ((USARTx->CR3 & USART_CR3_SCEN) != 0);
+  struct chx_intr *usartx_intr = get_usart_intr (dev_no);
+  struct chx_poll_head *ph[1];
+
+  if (usartx_intr == NULL)
+    return -1;
+
+  ph[0] = (struct chx_poll_head *)usartx_intr;
+
+  p = (uint8_t *)s_buf;
+  if (p)
+    {
+      if (smartcard_mode)
+	usart_config_recv_enable (USARTx, 0);
+
+      USARTx->CR1 |= USART_CR1_TXEIE;
+
+      /* Sending part */
+      while (1)
+	{
+	  chopstx_poll (NULL, 1, ph);
+
+	  r = USARTx->SR;
+
+	  /* Here, ignore recv error(s).  */
+	  if ((r & USART_SR_RXNE) || (r & USART_SR_ORE))
+	    {
+	      data = USARTx->DR;
+	      asm volatile ("" : : "r" (data) : "memory");
+	    }
+
+	  if ((r & USART_SR_TXE))
+	    {
+	      if (s_buflen == 0)
+		break;
+	      else
+		{
+		  /* Keep TXEIE bit */
+		  USARTx->DR = *p++;
+		  s_buflen--;
+		}
+	    }
+
+	  chopstx_intr_done (usartx_intr);
+	}
+
+      USARTx->CR1 &= ~USART_CR1_TXEIE;
+      if (smartcard_mode)
+	{
+	  if (timeout_block_p && (*timeout_block_p))
+	    do
+	      r = USARTx->SR;
+	    while (((r & USART_SR_TC) == 0));
+
+	  usart_config_recv_enable (USARTx, 1);
+
+	  if (timeout_block_p && *timeout_block_p == 0)
+	    {
+	      /* Ignoring the echo back.  */
+	      do
+		r = USARTx->SR;
+	      while (((r & USART_SR_TC) == 0));
+
+	      if ((r & USART_SR_RXNE))
+		{
+		  data = USARTx->DR;
+		  asm volatile ("" : : "r" (data) : "memory");
+		}
+
+	      *timeout_block_p = timeout_char;
+	    }
+	}
+
+      chopstx_intr_done (usartx_intr);
+    }
+
+  if (r_buf == NULL)
+    return 0;
+
+  if (!p)
+    if (smartcard_mode)
+      usart_config_recv_enable (USARTx, 1);
+
+  /* Receiving part */
+  r = chopstx_poll (timeout_block_p, 1, ph);
+  if (r == 0)
+    return 0;
+
+  p = (uint8_t *)r_buf;
+  len = 0;
+
+  while (1)
+    {
+      r = USARTx->SR;
+
+      data = USARTx->DR;
+      asm volatile ("" : : "r" (data) : "memory");
+
+      if ((r & USART_SR_RXNE))
+	{
+	  if ((r & USART_SR_NE) || (r & USART_SR_FE) || (r & USART_SR_PE))
+	    /* ignore error, for now.  XXX: ss_notify */
+	    ;
+	  else
+	    {
+	      *p++ = (data & 0xff);
+	      len++;
+	      r_buflen--;
+	      if (r_buflen == 0)
+		{
+		  chopstx_intr_done (usartx_intr);
+		  break;
+		}
+	    }
+	}
+      else if ((r & USART_SR_ORE))
+	{
+	  data = USARTx->DR;
+	  asm volatile ("" : : "r" (data) : "memory");
+	}
+
+      chopstx_intr_done (usartx_intr);
+      timeout = timeout_char;
+      r = chopstx_poll (&timeout, 1, ph);
+      if (r == 0)
+	break;
+    }
+
+  return len;
+}

contrib/usart-stm32l4.c

@@ -0,0 +1,559 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <mcu/stm32l.h>
+#include <contrib/usart.h>
+
+
+#define RCC_APB1_1_USART2     (1 << 17)
+#define RCC_APB2_USART1       (1 << 14)
+
+/* Hardware registers */
+struct USART {
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t CR3;
+  volatile uint32_t BRR;
+  volatile uint32_t GTPR;
+  volatile uint32_t RTOR;
+  volatile uint32_t RQR;
+  volatile uint32_t ISR;
+  volatile uint32_t ICR;
+  volatile uint32_t RDR;
+  volatile uint32_t TDR;
+};
+
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define USART1 ((struct USART *)USART1_BASE)
+
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART2 ((struct USART *)USART2_BASE)
+
+#define USART_ISR_CTS	(1 << 10)
+#define USART_ISR_LBDF	(1 << 8)
+#define USART_ISR_TXE	(1 << 7)
+#define USART_ISR_TC	(1 << 6)
+#define USART_ISR_RXNE	(1 << 5)
+#define USART_ISR_IDLE	(1 << 4)
+#define USART_ISR_ORE	(1 << 3)
+#define USART_ISR_NE	(1 << 2)
+#define USART_ISR_FE	(1 << 1)
+#define USART_ISR_PE	(1 << 0)
+
+#define USART_CR1_M1		(1 << 28)
+#define USART_CR1_M0		(1 << 12)
+#define USART_CR1_WAKE		(1 << 11)
+#define USART_CR1_PCE		(1 << 10)
+#define USART_CR1_PS		(1 <<  9)
+#define USART_CR1_PEIE		(1 <<  8)
+#define USART_CR1_TXEIE		(1 <<  7)
+#define USART_CR1_TCIE		(1 <<  6)
+#define USART_CR1_RXNEIE	(1 <<  5)
+#define USART_CR1_IDLEIE	(1 <<  4)
+#define USART_CR1_TE		(1 <<  3)
+#define USART_CR1_RE		(1 <<  2)
+#define USART_CR1_UESM		(1 <<  1)
+#define USART_CR1_UE		(1 <<  0)
+
+#define USART_CR3_CTSE		(1 <<  9)
+#define USART_CR3_RTSE		(1 <<  8)
+#define USART_CR3_SCEN		(1 <<  5)
+#define USART_CR3_NACK		(1 <<  4)
+
+static struct usart_stat usart2_stat;
+
+static struct chx_intr usart1_intr;
+static struct chx_intr usart2_intr;
+
+#define BUF_A2H_SIZE 256
+#define BUF_H2A_SIZE 512
+static uint8_t buf_usart2_rb_a2h[BUF_A2H_SIZE];
+static uint8_t buf_usart2_rb_h2a[BUF_H2A_SIZE];
+
+static struct rb usart2_rb_a2h;
+static struct rb usart2_rb_h2a;
+
+static chopstx_poll_cond_t usart2_app_write_event;
+
+/* Global variables so that it can be easier to debug.  */
+static int usart2_tx_ready;
+
+#define INTR_REQ_USART1 37
+#define INTR_REQ_USART2 38
+
+#define USART_DEVNO_START 1
+#define USART_DEVNO_END   2
+
+struct usart {
+  struct USART *USART;
+  struct chx_intr *intr;
+  uint8_t irq_num;
+  struct usart_stat *stat;
+  struct rb *rb_a2h;
+  struct rb *rb_h2a;
+  uint8_t *buf_a2h;
+  uint8_t *buf_h2a;
+  chopstx_poll_cond_t *app_write_event;
+  int *tx_ready;
+};
+
+
+static const struct usart usart_array[] =
+  {
+   { USART1, &usart1_intr, INTR_REQ_USART1,
+     NULL, NULL, NULL, NULL,
+     NULL, NULL, NULL,
+   },
+   { USART2, &usart2_intr, INTR_REQ_USART2,
+     &usart2_stat, &usart2_rb_a2h, &usart2_rb_h2a, buf_usart2_rb_a2h,
+     buf_usart2_rb_h2a, &usart2_app_write_event, &usart2_tx_ready,
+   },
+  };
+#define NUM_USART ((int)(sizeof (usart_array) / sizeof (struct usart)))
+
+static int handle_intr (struct USART *USARTx, struct rb *rb2a, struct usart_stat *stat);
+static int handle_tx (struct USART *USARTx, struct rb *rb2h, struct usart_stat *stat);
+static void usart_config_recv_enable (struct USART *USARTx, int on);
+
+struct brr_setting {
+  uint8_t baud_spec;
+  uint32_t brr_value;
+};
+#define NUM_BAUD (int)(sizeof (brr_table) / sizeof (struct brr_setting))
+
+/* We assume 40MHz f_CK */
+static const struct brr_setting brr_table[] = {
+  { B600,    66667 },
+  { B1200,   33333 },
+  { B2400,   16667 },
+  { B9600,    4167 },
+  { B19200,   2083 },
+  { B57600,    694 },
+  { B115200,   347 },
+  { B230400,   174 },
+  { B460800,    87 },
+  { B921600,    43 },
+  { BSCARD1,  3720 },
+  { BSCARD2,  1860 },
+  { BSCARD4,   930 },
+  { BSCARD8,   465 },
+  { BSCARD12,  310 },
+  { BSCARD16,  233 },
+  { BSCARD20,  186 },
+};
+
+#include "usart-common.c"
+
+static void
+usart_config_recv_enable (struct USART *USARTx, int on)
+{
+  if (on)
+    {
+      USARTx->CR1 |= USART_CR1_RE;
+      /* Wait for REACK bit.  */
+      while ((USARTx->ISR & (1 << 22)) == 0)
+	;
+    }
+  else
+    USARTx->CR1 &= ~USART_CR1_RE;
+}
+
+int
+usart_config (uint8_t dev_no, uint32_t config_bits)
+{
+  struct USART *USARTx = get_usart_dev (dev_no);
+  uint8_t baud_spec = (config_bits & MASK_BAUD);
+  int i;
+  uint32_t cr1_config = (USART_CR1_UE | USART_CR1_RXNEIE | USART_CR1_TE);
+				/* TXEIE/TCIE will be enabled when
+				   putting char */
+				/* No CTSIE, PEIE, IDLEIE, LBDIE */
+  if (USARTx == NULL)
+    return -1;
+
+  /* Disable USART before configure.  */
+  USARTx->CR1 &= ~USART_CR1_UE;
+
+  if ((config_bits & MASK_CS) == CS7 && !(config_bits & PARENB))
+    cr1_config |=  USART_CR1_M1;
+  else if (((config_bits & MASK_CS) == CS7 && (config_bits & PARENB))
+      || ((config_bits & MASK_CS) == CS8 && (config_bits & PARENB) == 0))
+    ;
+  else if ((config_bits & MASK_CS) == CS8)
+    cr1_config |=  USART_CR1_M0;
+  else
+    return -1;
+
+  if ((config_bits & PARENB))
+    cr1_config |=  (USART_CR1_PCE | USART_CR1_PEIE);
+
+  if ((config_bits & PARODD))
+    cr1_config |=  USART_CR1_PS;
+
+  if ((config_bits & MASK_STOP) == STOP0B5)
+    USARTx->CR2 = (0x1 << 12);
+  else if ((config_bits & MASK_STOP) == STOP1B)
+    USARTx->CR2 = (0x0 << 12);
+  else if ((config_bits & MASK_STOP) == STOP1B5)
+    USARTx->CR2 = (0x3 << 12);
+  else /* if ((config_bits & MASK_STOP) == STOP2B) */
+    USARTx->CR2 = (0x2 << 12);
+
+  for (i = 0; i < NUM_BAUD; i++)
+    if (brr_table[i].baud_spec == baud_spec)
+      break;
+
+  if (i >= NUM_BAUD)
+    return -1;
+
+  USARTx->BRR = brr_table[i].brr_value;
+
+  if ((config_bits & MASK_FLOW))
+    USARTx->CR3 = USART_CR3_CTSE | USART_CR3_RTSE;
+  else
+    USARTx->CR3 = 0;
+
+  if ((config_bits & MASK_MODE))
+    {
+      if ((config_bits & MASK_MODE) == MODE_SMARTCARD)
+	{
+	  USARTx->GTPR = (1 << 8) | 5;
+	  USARTx->CR3 |= (USART_CR3_SCEN | USART_CR3_NACK);
+	}
+      else if ((config_bits & MASK_MODE) == MODE_IRDA)
+	USARTx->CR3 |= (1 << 1);
+      else if ((config_bits & MASK_MODE) == MODE_IRDA_LP)
+	USARTx->CR3 |= (1 << 2) | (1 << 1);
+    }
+  else
+    cr1_config |= USART_CR1_RE;
+
+  USARTx->CR1 = cr1_config;
+
+  /* Wait for TEACK bit.  */
+  while ((USARTx->ISR & (1 << 21)) == 0)
+    ;
+
+  return 0;
+}
+
+
+void
+usart_init0 (int (*cb) (uint8_t dev_no, uint16_t notify_bits))
+{
+  int i;
+
+  ss_notify_callback = cb;
+
+  for (i = 0; i < NUM_USART; i++)
+    {
+      if (usart_array[i].stat)
+	usart_array[i].stat->dev_no = i + USART_DEVNO_START;
+      chopstx_claim_irq (usart_array[i].intr, usart_array[i].irq_num);
+    }
+
+  /* Enable USART1 clock, and strobe reset.  */
+  RCC->APB2ENR |= RCC_APB2_USART1;
+  RCC->APB2RSTR = RCC_APB2_USART1;
+  RCC->APB2RSTR = 0;
+
+  /* Enable USART2 clock, and strobe reset.  */
+  RCC->APB1ENR1 |= RCC_APB1_1_USART2;
+  RCC->APB1RSTR1 = RCC_APB1_1_USART2;
+  RCC->APB1RSTR1 = 0;
+}
+
+#define UART_STATE_BITMAP_RX_CARRIER (1 << 0)
+#define UART_STATE_BITMAP_TX_CARRIER (1 << 1)
+#define UART_STATE_BITMAP_BREAK      (1 << 2)
+#define UART_STATE_BITMAP_RINGSIGNAL (1 << 3)
+#define UART_STATE_BITMAP_FRAMING    (1 << 4)
+#define UART_STATE_BITMAP_PARITY     (1 << 5)
+#define UART_STATE_BITMAP_OVERRUN    (1 << 6)
+
+static int
+handle_intr (struct USART *USARTx, struct rb *rb2a, struct usart_stat *stat)
+{
+  int tx_ready = 0;
+  uint32_t r = USARTx->ISR;
+  int notify_bits = 0;
+  int smartcard_mode = ((USARTx->CR3 & USART_CR3_SCEN) != 0);
+
+  if (smartcard_mode)
+    {
+      if ((r & USART_ISR_TC))
+	{
+	  tx_ready = 1;
+	  USARTx->CR1 &= ~USART_CR1_TCIE;
+	}
+    }
+  else
+    {
+      if ((r & USART_ISR_TXE))
+	{
+	  tx_ready = 1;
+	  USARTx->CR1 &= ~USART_CR1_TXEIE;
+	}
+    }
+
+  if ((r & USART_ISR_RXNE))
+    {
+      uint32_t data = USARTx->RDR;
+
+      /* RDR register should be accessed even if data is not used.  */
+      asm volatile ("" : : "r" (data) : "memory");
+
+      if ((r & USART_ISR_NE))
+	{
+	  USARTx->ICR |= (1 << 2);
+	  stat->err_rx_noise++;
+	}
+      else if ((r & USART_ISR_FE))
+	{
+	  /* NOTE: Noway to distinguish framing error and break  */
+
+	  USARTx->ICR |= (1 << 1);
+	  stat->rx_break++;
+	  notify_bits |= UART_STATE_BITMAP_BREAK;
+	}
+      else if ((r & USART_ISR_PE))
+	{
+	  USARTx->ICR |= (1 << 0);
+	  stat->err_rx_parity++;
+	  notify_bits |= UART_STATE_BITMAP_PARITY;
+	}
+      else
+	{
+	  if ((r & USART_ISR_ORE))
+	    {
+	      USARTx->ICR |= (1 << 3);
+	      stat->err_rx_overrun++;
+	      notify_bits |= UART_STATE_BITMAP_OVERRUN;
+	    }
+
+	  /* XXX: if CS is 7-bit, mask it, or else parity bit in upper layer */
+	  if (rb_ll_put (rb2a, (data & 0xff)) < 0)
+	    stat->err_rx_overflow++;
+	  else
+	    stat->rx++;
+	}
+    }
+  else if ((r & USART_ISR_ORE))
+    {				/* Clear ORE */
+      USARTx->ICR |= (1 << 3);
+      stat->err_rx_overrun++;
+      notify_bits |= UART_STATE_BITMAP_OVERRUN;
+    }
+
+  if (notify_bits)
+    {
+      if (ss_notify_callback
+	  && (*ss_notify_callback) (stat->dev_no, notify_bits))
+	stat->err_notify_overflow++;
+    }
+
+  return tx_ready;
+}
+
+static int
+handle_tx (struct USART *USARTx, struct rb *rb2h, struct usart_stat *stat)
+{
+  int tx_ready = 1;
+  int c = rb_ll_get (rb2h);
+
+  if (c >= 0)
+    {
+      uint32_t r;
+      int smartcard_mode = ((USARTx->CR3 & USART_CR3_SCEN) != 0);
+
+      USARTx->TDR = (c & 0xff);
+      stat->tx++;
+      r = USARTx->ISR;
+      if (smartcard_mode)
+	{
+	  if ((r & USART_ISR_TC) == 0)
+	    {
+	      tx_ready = 0;
+	      USARTx->CR1 |= USART_CR1_TCIE;
+	    }
+	}
+      else
+	{
+	  if ((r & USART_ISR_TXE) == 0)
+	    {
+	      tx_ready = 0;
+	      USARTx->CR1 |= USART_CR1_TXEIE;
+	    }
+	}
+    }
+
+  return tx_ready;
+}
+
+int
+usart_send_break (uint8_t dev_no)
+{
+  struct USART *USARTx = get_usart_dev (dev_no);
+  if (USARTx == NULL)
+    return -1;
+
+  if ((USARTx->ISR & (1 << 18)))
+    return 1;	/* Busy sending break, which was requested before.  */
+
+  /* ??? Should we check TX is empty? */
+
+  USARTx->RQR |= 0x02;
+  return 0;
+}
+
+int
+usart_block_sendrecv (uint8_t dev_no, const char *s_buf, uint16_t s_buflen,
+		      char *r_buf, uint16_t r_buflen,
+		      uint32_t *timeout_block_p, uint32_t timeout_char)
+{
+  uint32_t timeout;
+  uint8_t *p;
+  int len;
+  uint32_t r;
+  uint32_t data;
+  struct USART *USARTx = get_usart_dev (dev_no);
+  int smartcard_mode = ((USARTx->CR3 & USART_CR3_SCEN) != 0);
+  struct chx_intr *usartx_intr = get_usart_intr (dev_no);
+  struct chx_poll_head *ph[1];
+
+  if (usartx_intr == NULL)
+    return -1;
+
+  ph[0] = (struct chx_poll_head *)usartx_intr;
+
+  p = (uint8_t *)s_buf;
+  if (p)
+    {
+      if (smartcard_mode)
+	usart_config_recv_enable (USARTx, 0);
+
+      USARTx->CR1 |= USART_CR1_TXEIE;
+
+      /* Sending part */
+      while (1)
+	{
+	  chopstx_poll (NULL, 1, ph);
+
+	  r = USARTx->ISR;
+
+	  /* Here, ignore recv error(s).  */
+	  if ((r & USART_ISR_RXNE))
+	    {
+	      data = USARTx->RDR;
+	      asm volatile ("" : : "r" (data) : "memory");
+
+	      USARTx->ICR |= ((1 << 2) | (1 << 1) | (1 << 0));
+	    }
+	  else if ((r & USART_ISR_ORE))
+	    {
+	      USARTx->ICR |= (1 << 3);
+	    }
+
+	  if ((r & USART_ISR_TXE))
+	    {
+	      if (s_buflen == 0)
+		break;
+	      else
+		{
+		  /* Keep TXEIE bit */
+		  USARTx->TDR = *p++;
+		  s_buflen--;
+		}
+	    }
+
+	  chopstx_intr_done (usartx_intr);
+	}
+
+      USARTx->CR1 &= ~USART_CR1_TXEIE;
+      if (smartcard_mode)
+	{
+	  if (timeout_block_p && (*timeout_block_p))
+	    do
+	      r = USARTx->ISR;
+	    while (((r & USART_ISR_TC) == 0));
+
+	  usart_config_recv_enable (USARTx, 1);
+
+	  if (timeout_block_p && *timeout_block_p == 0)
+	    {
+	      /* Ignoring the echo back.  */
+	      do
+		r = USARTx->ISR;
+	      while (((r & USART_ISR_TC) == 0));
+
+	      if ((r & USART_ISR_RXNE))
+		{
+		  data = USARTx->RDR;
+		  asm volatile ("" : : "r" (data) : "memory");
+		}
+
+	      *timeout_block_p = timeout_char;
+	    }
+	}
+
+      chopstx_intr_done (usartx_intr);
+    }
+
+  if (r_buf == NULL)
+    return 0;
+
+  if (!p)
+    if (smartcard_mode)
+      usart_config_recv_enable (USARTx, 1);
+
+  /* Receiving part */
+  r = chopstx_poll (timeout_block_p, 1, ph);
+  if (r == 0)
+    return 0;
+
+  p = (uint8_t *)r_buf;
+  len = 0;
+
+  while (1)
+    {
+      r = USARTx->ISR;
+
+      data = USARTx->RDR;
+      asm volatile ("" : : "r" (data) : "memory");
+
+      if ((r & USART_ISR_RXNE))
+	{
+	  if ((r & USART_ISR_NE) || (r & USART_ISR_FE) || (r & USART_ISR_PE))
+	    {
+	      /* ignore error, for now.  XXX: ss_notify */
+	      /* Clear the error flag(s) */
+	      USARTx->ICR |= ((1 << 2) | (1 << 1) | (1 << 0));
+	    }
+	  else
+	    {
+	      *p++ = (data & 0xff);
+	      len++;
+	      r_buflen--;
+	      if (r_buflen == 0)
+		{
+		  chopstx_intr_done (usartx_intr);
+		  break;
+		}
+	    }
+	}
+      else if ((r & USART_ISR_ORE))
+	{
+	  /* ignore error, for now.  XXX: ss_notify */
+	  /* Clear the error flag */
+	  USARTx->ICR |= (1 << 3);
+	}
+
+      chopstx_intr_done (usartx_intr);
+      timeout = timeout_char;
+      r = chopstx_poll (&timeout, 1, ph);
+      if (r == 0)
+	break;
+    }
+
+  return len;
+}

contrib/usart.h

@@ -0,0 +1,90 @@
+#define B0       0 /* POSIX to hang up */
+
+/* POSIX supports B75 to B300 */
+#define B600        16
+#define B1200       17
+#define B2400       19
+#define B9600       21
+#define B19200      22
+#define B57600      24
+#define B115200     25
+#define B230400     26
+#define B460800     27
+#define B921600     28
+#define BSCARD1     57
+#define BSCARD2     58
+#define BSCARD4     59
+#define BSCARD8     60
+#define BSCARD12    61
+#define BSCARD16    62
+#define BSCARD20    63
+#define MASK_BAUD 0x3f
+
+/* POSIX supports 5, 6.  USB suppots 16 */
+#define CS7       (2 << 6)
+#define CS8       (3 << 6)
+#define MASK_CS   (0x7 << 6)
+
+#define STOP0B5	  (0 << 9) /* USART Hardware only */
+#define STOP1B	  (1 << 9) /* USB, POSIX  */
+#define STOP1B5	  (2 << 9) /* USB         */
+#define STOP2B	  (3 << 9) /* USB, POSIX  */
+#define MASK_STOP (0x3 << 9)
+
+#define PARENB    (1 << 11)
+#define PARODD    (2 << 11)
+#define MASK_PAR  (0x7 << 11)
+/* USB  0: none, 1: odd, 2: even, 3: mark, 4: space */
+
+#define CRTSCTS   (1 << 14)
+#define MASK_FLOW (0x1 << 14)
+
+/*
+BAUD_BITS 6
+CS_BITS   3
+STOP_BITS 2
+PAR_BITS  3
+*/
+/* USB: SET_CONTROL_LINE_STATE
+   DTR RTS */
+/* USB: SERIAL_STATE
+   DSR DCD RI */
+
+/* non-POSIX, non-USB-CDC configs */
+#define MODE_SMARTCARD (1 << 30)
+#define MODE_IRDA      (2UL << 30)
+#define MODE_IRDA_LP   (3UL << 30)
+#define MASK_MODE      (0x3UL << 30)
+/* 0: standard, 1: smartcard, 2: IrDA, 3: IrDA-LP */
+
+struct usart_stat {
+  uint8_t dev_no;
+
+  uint32_t tx;
+  uint32_t rx;
+  uint32_t rx_break;
+  uint32_t err_notify_overflow;
+  uint32_t err_rx_overflow;	/* software side */
+  uint32_t err_rx_overrun;	/* hardware side */
+  uint32_t err_rx_noise;
+  uint32_t err_rx_parity;
+};
+
+
+void usart_init (uint16_t prio, uintptr_t stack_addr, size_t stack_size,
+		 int (*ss_notify_callback) (uint8_t dev_no, uint16_t notify_bits));
+int usart_config (uint8_t dev_no, uint32_t config_bits);
+int usart_read (uint8_t dev_no, char *buf, uint16_t buflen);
+int usart_write (uint8_t dev_no, char *buf, uint16_t buflen);
+const struct usart_stat *usart_stat (uint8_t dev_no);
+int usart_send_break (uint8_t dev_no);
+void usart_config_clken (uint8_t dev_no, int on);
+int usart_config_baud (uint8_t dev_no, uint8_t baud_spec);
+
+void usart_read_prepare_poll (uint8_t dev_no, chopstx_poll_cond_t *poll_desc);
+int usart_read_ext (uint8_t dev_no, char *buf, uint16_t buflen, uint32_t *timeout_p);
+
+void usart_init0 (int (*cb) (uint8_t dev_no, uint16_t notify_bits));
+int usart_block_sendrecv (uint8_t dev_no, const char *s_buf, uint16_t s_buflen,
+			  char *r_buf, uint16_t r_buflen,
+			  uint32_t *timeout_block_p, uint32_t timeout_char);

doc/chopstx-api.texi

@@ -107,6 +107,14 @@ Claim interrupt @var{intr} with @var{irq_num}
 Wait for the interrupt @var{intr} to be occured.
 @end deftypefun
 
+@subheading chopstx_intr_done
+@anchor{chopstx_intr_done}
+@deftypefun {void} {chopstx_intr_done} (chopstx_intr_t * @var{intr})
+@var{intr}: Pointer to INTR structure
+
+Finish for the interrupt @var{intr} occurred.
+@end deftypefun
+
 @subheading chopstx_cleanup_push
 @anchor{chopstx_cleanup_push}
 @deftypefun {void} {chopstx_cleanup_push} (struct chx_cleanup * @var{clp})
@@ -176,8 +184,9 @@ Returns old state which is 0 when it was enabled.
 
 @subheading chopstx_poll
 @anchor{chopstx_poll}
-@deftypefun {int} {chopstx_poll} (uint32_t * @var{usec_p}, int @var{n}, struct chx_poll_head * [] @var{pd_array})
+@deftypefun {int} {chopstx_poll} (uint32_t * @var{usec_p}, int @var{n}, struct chx_poll_head *const [] @var{pd_array})
-@var{usec_p}: Pointer to usec for timeout.  Forever if NULL.
+@var{usec_p}: Pointer to usec for timeout.  Forever if NULL.  It is
+updated on return
 
 @var{n}: Number of poll descriptors
 
@@ -201,3 +210,23 @@ which starts its execution with priority of CHX_PRIO_MAIN_INIT, and
 let it change its priority after initialization of other threads.
 @end deftypefun
 
+@subheading chx_sleep_mode
+@anchor{chx_sleep_mode}
+@deftypefun {extern void} {chx_sleep_mode} (int @var{enable_sleep})
+@var{enable_sleep}: Enable sleep on idle or not
+
+If @var{enable_sleep} is > 0, allow sleep for the idle thread.
+
+Behavior of @var{enable_sleep} >= 1 depends on MCU.
+
+For STM32F0, 1 for Sleep (CPU clock OFF only), 2 for Stop (Wakeup
+by EXTI, voltage regulator on), 3 for Stop (Wakeup by EXTI, voltage
+regulator low-power), 4 for Standby (Wakeup by RESET, voltage
+regulator off).
+
+For STM32F103, 1 for normal sleep, and 2 for sleep with lower 8MHz
+clock.
+
+Return previous value of @var{enable_sleep}.
+@end deftypefun
+

doc/chopstx.texi

@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
 @c %**start of header
 @setfilename chopstx.info
-@set VERSION 1.5
+@set VERSION 1.16
 @settitle Chopstx Reference Manual
 @c Unify some of the indices.
 @syncodeindex tp fn
@@ -11,7 +11,7 @@
 This manual is for Chopstx (version @value{VERSION}).
 
 @noindent
-Copyright @copyright{} 2013, 2015, 2016 Flying Stone Technology @*
+Copyright @copyright{} 2013, 2015, 2016, 2017, 2018, 2019 Flying Stone Technology @*
 
 @quotation
 Permission is granted to copy, distribute and/or modify this document
@@ -59,7 +59,12 @@ section entitled ``Copying''.
 
 @menu
 * Introduction::                 What is Chopstx.
+* Threads and only Threads::     Threads and only Threads.
+* Poll or Pole::
+* Use of sleep mode::            Use it carefully.
+* Compile-time macro::           Macro to be defined.
 * API::                          API.
+* Memorandom::                   Memorandom for the implementation.
 
 Appendix
 
@@ -83,22 +88,182 @@ Indexes
 @node Introduction
 @chapter Introduction
 
-Chopstx is an RT thread library for ARM Cortex-M0, Cortex-M0plus and
+Chopstx is an RT thread library for ARM Cortex-M0, Cortex-M0plus,
-Cortex-M3.  Specifically, it is used for STM32F030, MKL27Z and
+Cortex-M3, Cortex-M4 with no FPU or DSP, and GNU/Linux emulation.
-STM32F103.
+Specifically, it is used for STM32F030, MKL27Z, STM32F103, GD32F103,
+STM32L432 and as a command on GNU/Linux.
 
 While most RTOSes come with many features, drivers, and stacks,
-Chopstx just offers a RT thread library.
+Chopstx just offers an RT thread library.
 
 With Chopstx, interrupt handling is also done by a thread.  This
 enables coherent code for ease of maintenance.
 
+While threads are important, we don't need more threads than
+necessary.  Chopstx provides a feature of poll, so that we can
+handle multiple events by a single thread.
+
+
+@node Threads and only Threads
+@chapter Threads and only Threads
+
+Chopstx doesn't use the feature of (prioritized) nested vector
+interrupt mechanism at all.  All interrupts are equally handled by a
+single entry of chx_handle_intr which just wakes up a corresponding
+thread.  This is the feature of Chopstx.
+
+Nested vector interrupt machanism would be useful for interrupt-driven
+programming style for specific application targets, or, some other
+programing style like the one with spl of Unix.  Some engineers
+(especially, hardware side) still seem to believe that it is a good
+feature to have.  But from the view point of programming and
+maintenance of software, this is one of the most difficult part with
+little benefit, if any.
+
+With traditional interrupt handling, a demarcation of what should be
+done by interrupt handler, bottom half, and thead is crucial for
+applications' performance.  And because the demarcation should be done
+at an early stage of an application development, it has a tendency,
+many parts are getting demanding higher priority.  Amount of code for
+higher priority interrupt hander is getting bigger and bigger, while
+losing performance.
+
+On the other hand, ``Threads (and only Threads)'' programming style
+gives us best flexibility and it can make an application more
+predictable, deterministic and easy to maintain.
+
+There are some applications, like square wave generator, which are not
+suited to this programming style; Another programming style can
+support more performance (frequency).  In general, such an example is
+best suited by hardware (not software).
+
+
+@node Poll or Pole
+@chapter Poll or Pole
+Chopstx provides the @code{chopstx_poll} function to wait on multiple events.
+
+Using @code{chopstx_poll}, we can write an application by event-driven
+programming style, with minimum number of threads, avoiding
+complicated dependency between threads.
+
+
+@node Use of sleep mode
+@chapter Use of sleep mode
+
+Calling the chopstx_conf_idle function (> 0) to allow the idle thread
+going to sleep.  MCU will be in sleep mode when no threads are
+running.  By setting relevant bits of system registers, MCU will be
+able to be into stop or stand-by mode, which is MCU dependent.
+
+If you use this sleep feature, please consider and implement your
+program carefully.  Enabling sleep, it may result a bricked board; A
+board with no RESET pin cannot be debugged by JTAG/SWD.
+
+
+@node Compile-time macro
+@chapter Compile-time macro
+
+Compiling Chopstx, a macro MHZ should be supplied.
+
+For example, when using the makefile rule of chopstx/rules.mk, please
+define the make variable DEFS with -DMHZ=72 before inclusion of the rule file.
+
+@subheading MHZ
+@anchor{MHZ}
+@defmac {MHZ}
+Running CPU clock in MHz.  Used for chopstx_usec_wait.
+@end defmac
+
 
 @node API
 @chapter API
 
 @include chopstx-api.texi
 
+@node Memorandom
+@chapter Memorandom for the implementation
+
+@menu
+* Honourable poverty::          Wabi and Sabi.
+* Better interrupt handling::
+* Static and deterministic when possible::
+@end menu
+
+@node Honourable poverty
+@section Honourable poverty
+
+Chopstx is an effort against many features.  It encourages doing
+harder decision earlier (because of less features).
+
+Along with Moore's law, MCU implementations and their software are
+getting more complex.  It's been getting more flexibile, versatile,
+and powerful.
+
+Here is a question: the bigger is the better?
+
+Historically, it used to be ``Yes, and it's even cheaper!''.  And, for
+a while, this trend continues.
+
+However, in my opinion, it has been arrived to the point where
+complexity matters.  Now, it's more difficult to manage the
+complexity.
+
+With full of resources, it became possible deferring difficult
+hardware or lower-level decisions to upper layer, by supporting both
+ways, when we have a choice.  It used to be considered a good
+practice.
+
+But, eventually, as a system, it may result many knobs, full of
+options, which might be too difficult to manage.
+
+In this situation, against existing practice, Chopstx is a challenge
+to handle all food by only two wooden sticks.  It's not fork and exec
+nor forks and knives.
+
+In Japan, it is common among families, to have private chopsticks for
+each individual at home.  It's like: these chopsticks are father's,
+these chopsticks are mother's... son's and daughter's.
+
+I hope Chopstx is the one for you.
+
+
+@node Better interrupt handling
+@section Better interrupt handling
+
+In Chopstx, all interrupt handling is done by a single routine named
+chx_handle_intr.  It uses linear list search to find a thread which
+handles the interrupt.  In the fixed vector_table, we see many of
+chx_handle_intr entries.
+
+Obviously, this is suboptimal.  It kills the hardware effort to
+decrease interrupt latency.
+
+I is certainly possible to support configurable vector table and/or
+better dispatch.
+
+The reason why I keep this badness is that I believe that when
+interrupt latency matters (to the level of supporting larger vector
+table, despite only few cycles elimination), something is going wrong.
+You should have better solution or work around, instead of eliminating
+few cycles in an interrupt handler.
+
+When I have an opportunity to design MCU, I don't support larger
+interrupt vector table.
+
+
+@node Static and deterministic when possible
+@section Static and deterministic when possible
+
+When an application enables features dynamically, it may invite
+non-deterministic bugs.  Typical example: the order of driver
+initialization matters, because of hidden dependency in a hardware
+implementation.  To cover all the cases, tests needed can become huge.
+
+A simple practice like following is good when it's enough: doing all
+initialization at start, then running threads to work.
+
+If possible, it's better to avoid supporting fine grain power control
+and/or dynamic clock frequency change.
 
 @c ********************************************
 

entry.c

@@ -1,7 +1,7 @@
 /*
  * entry.c - Entry routine when reset and interrupt vectors.
  *
- * Copyright (C) 2013, 2014, 2015, 2016, 2017
+ * Copyright (C) 2013, 2014, 2015, 2016, 2017, 2019
  *               Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -23,7 +23,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 
@@ -54,12 +54,16 @@ main (int argc, const char *argv[])
  * Avoid medium density specific code and prepare for high density
  * device, too.
  */
-#undef STM32F10X_MD
+#if !defined(MCU_STM32L4)
+#define STM32F10X_HD
+#endif
 #else
 #if defined (MCU_KINETIS_L)
 #include "mcu/clk_gpio_init-mkl27z.c"
+#elif defined (MCU_STM32L4)
+#include "mcu/clk_gpio_init-stm32l.c"
 #else
-#include "mcu/clk_gpio_init-stm32.c"
+#include "mcu/clk_gpio_init-stm32f.c"
 #endif
 #endif
 
@@ -71,7 +75,7 @@ main (int argc, const char *argv[])
 #endif
 
 extern uint8_t __main_stack_end__;
-#if defined(__ARM_ARCH_7M__)
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
 extern void svc (void);
 #endif
 extern void preempt (void);
@@ -167,7 +171,7 @@ entry (void)
 		"bl	chx_systick_init\n\t"
 		"bl	gpio_init\n\t"
 		/* Enable interrupts.  */
-#if defined(__ARM_ARCH_7M__)
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
 		"mov	r0, #0\n\t"
 		"msr	BASEPRI, r0\n\t"
 #endif
@@ -197,7 +201,7 @@ handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
   none, none, none,		/* reserved */
 #if defined(__ARM_ARCH_6M__)
   none,				/* SVCall */
-#elif defined(__ARM_ARCH_7M__)
+#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
   svc,				/* SVCall */
 #endif  
   none,				/* Debug */
@@ -205,23 +209,23 @@ handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
   preempt,			/* PendSV */
   chx_timer_expired,		/* SysTick */
   /* 0x40 */
-  chx_handle_intr /* WWDG */,     chx_handle_intr /* PVD */,
+  chx_handle_intr /* WWDG */,      chx_handle_intr /* PVD */,
-  chx_handle_intr /* TAMPER */,   chx_handle_intr /* RTC */,
+  chx_handle_intr /* TAMPER */,    chx_handle_intr /* RTC */,
-  chx_handle_intr /* FLASH */,    chx_handle_intr /* RCC */,
+  chx_handle_intr /* FLASH */,     chx_handle_intr /* RCC */,
-  chx_handle_intr /* EXTI0 */,    chx_handle_intr /* EXTI1 */,
+  chx_handle_intr /* EXTI0 */,     chx_handle_intr /* EXTI1 */,
   /* 0x60 */
-  chx_handle_intr /* EXTI2 */,    chx_handle_intr /* EXTI3 */,
+  chx_handle_intr /* EXTI2 */,     chx_handle_intr /* EXTI3 */,
-  chx_handle_intr /* EXTI4 */,    chx_handle_intr /* DMA1 CH1 */,
+  chx_handle_intr /* EXTI4 */,     chx_handle_intr /* DMA1 CH1 */,
-  chx_handle_intr /* DMA1 CH2 */, chx_handle_intr /* DMA1 CH3 */,
+  chx_handle_intr /* DMA1 CH2 */,  chx_handle_intr /* DMA1 CH3 */,
-  chx_handle_intr /* DMA1 CH4 */, chx_handle_intr /* DMA1 CH5 */,
+  chx_handle_intr /* DMA1 CH4 */,  chx_handle_intr /* DMA1 CH5 */,
   /* 0x80 */
-  chx_handle_intr /* DMA1 CH6 */, chx_handle_intr /* DMA1 CH7 */,
+  chx_handle_intr /* DMA1 CH6 */,  chx_handle_intr /* DMA1 CH7 */,
-  chx_handle_intr /* ADC1_2 */,   chx_handle_intr /* USB HP */,
+  chx_handle_intr /* ADC1_2 */,    chx_handle_intr /* USB HP */,
   /* 0x90 */
-  chx_handle_intr /* USB LP */,   chx_handle_intr /* CAN */,
+  chx_handle_intr /* USB LP */,    chx_handle_intr /* CAN RX1 */,
-  /* ... and more.  EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
+  chx_handle_intr /* CAN SCE */,   chx_handle_intr /* EXT9_5 */,
-  chx_handle_intr,                chx_handle_intr,
+  /* 0xa0 */
-  /* 0xA0 */
+  /* ... and more.  TIMx, I2C, SPI, USART... */
   chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
   chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
   /* 0xc0 */
@@ -229,15 +233,29 @@ handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
   /* STM32F0 doesn't have more.  */
   chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
   chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  /* 0xe0 */
+  chx_handle_intr /* EXT15_10 */,  chx_handle_intr /* RTCAlarm */,
+  chx_handle_intr /* USBWakeup */, chx_handle_intr,
 #endif
-#if !defined(STM32F10X_MD)
+#if defined(STM32F10X_HD)
-  /* High-density chips have more; RTCAlarm, USBWakeup, ... , DMA2_Channel4_5 */
+  /* High-density chips have more; ... DMA2_Channel4_5 */
   chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
   chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
   chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
   chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+#elif defined(MCU_STM32L4)
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
 #endif
 };
 #endif

eventflag.c

@@ -1,7 +1,7 @@
 /*
  * eventflag.c - Eventflag
  *
- * Copyright (C) 2013, 2016  Flying Stone Technology
+ * Copyright (C) 2013, 2016, 2018  Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -22,7 +22,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 
@@ -36,17 +36,29 @@ void
 eventflag_init (struct eventflag *ev)
 {
   ev->flags = 0;
+  ev->mask = ~0;
   chopstx_cond_init (&ev->cond);
   chopstx_mutex_init (&ev->mutex);
 }
 
 
+void
+eventflag_set_mask (struct eventflag *ev, eventmask_t m)
+{
+  chopstx_mutex_lock (&ev->mutex);
+  ev->mask = m;
+  if ((ev->flags & ev->mask))
+    chopstx_cond_signal (&ev->cond);
+  chopstx_mutex_unlock (&ev->mutex);
+}
+
+
 static int
 eventflag_check (void *arg)
 {
   struct eventflag *ev = arg;
 
-  return ev->flags != 0;
+  return (ev->flags & ev->mask) != 0;
 }
 
 
@@ -62,6 +74,9 @@ eventflag_prepare_poll (struct eventflag *ev, chopstx_poll_cond_t *poll_desc)
 }
 
 
+/* When multiple events are marked, event with lower bit has precedence.
+   Because __builtin_ffs returns the least significant 1-bit.  */
+
 eventmask_t
 eventflag_get (struct eventflag *ev)
 {
@@ -69,7 +84,7 @@ eventflag_get (struct eventflag *ev)
   eventmask_t m;
 
   chopstx_mutex_lock (&ev->mutex);
-  n = __builtin_ffs (ev->flags);
+  n = __builtin_ffs ((ev->flags & ev->mask));
   if (n)
     {
       m = (1 << (n - 1));
@@ -90,10 +105,10 @@ eventflag_wait (struct eventflag *ev)
   eventmask_t m;
 
   chopstx_mutex_lock (&ev->mutex);
-  if (!ev->flags)
+  while (!(ev->flags & ev->mask))
     chopstx_cond_wait (&ev->cond, &ev->mutex);
 
-  n = __builtin_ffs (ev->flags);
+  n = __builtin_ffs ((ev->flags & ev->mask));
   if (n) /* Always n > 0 when waked up, but make sure no bad things.  */
     {
       m = (1 << (n - 1));
@@ -124,6 +139,7 @@ eventflag_signal (struct eventflag *ev, eventmask_t m)
 {
   chopstx_mutex_lock (&ev->mutex);
   ev->flags |= m;
-  chopstx_cond_signal (&ev->cond);
+  if ((ev->flags & ev->mask))
+    chopstx_cond_signal (&ev->cond);
   chopstx_mutex_unlock (&ev->mutex);
 }

eventflag.h

@@ -2,11 +2,13 @@ typedef uint32_t eventmask_t;
 
 struct eventflag {
   eventmask_t flags;
+  eventmask_t mask;
   chopstx_mutex_t mutex;
   chopstx_cond_t cond;
 };
 
 void eventflag_init (struct eventflag *ev);
+void eventflag_set_mask (struct eventflag *ev, eventmask_t m);
 eventmask_t eventflag_wait (struct eventflag *ev);
 eventmask_t eventflag_wait_timeout (struct eventflag *ev, uint32_t usec);
 void eventflag_signal (struct eventflag *ev, eventmask_t m);

example-cdc-gnu-linux/usb-cdc.c

@@ -244,7 +244,7 @@ usb_device_reset (struct usb_dev *dev)
   tty0.flag_connected = 0;
   tty0.flag_send_ready = 1;
   tty0.flag_input_avail = 0;
-  tty0.device_state = ATTACHED;
+  tty0.device_state = USB_DEVICE_STATE_ATTACHED;
   memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
   chopstx_mutex_unlock (&tty0.mtx);
 }
@@ -414,7 +414,7 @@ usb_set_configuration (struct usb_dev *dev)
       for (i = 0; i < NUM_INTERFACES; i++)
 	vcom_setup_endpoints_for_interface (dev, i, 0);
       chopstx_mutex_lock (&tty0.mtx);
-      tty0.device_state = CONFIGURED;
+      tty0.device_state = USB_DEVICE_STATE_CONFIGURED;
       chopstx_cond_signal (&tty0.cnd);
       chopstx_mutex_unlock (&tty0.mtx);
     }
@@ -427,7 +427,7 @@ usb_set_configuration (struct usb_dev *dev)
       for (i = 0; i < NUM_INTERFACES; i++)
 	vcom_setup_endpoints_for_interface (dev, i, 1);
       chopstx_mutex_lock (&tty0.mtx);
-      tty0.device_state = ADDRESSED;
+      tty0.device_state = USB_DEVICE_STATE_ADDRESSED;
       chopstx_cond_signal (&tty0.cnd);
       chopstx_mutex_unlock (&tty0.mtx);
     }
@@ -629,8 +629,6 @@ usb_rx_ready (uint8_t ep_num, uint16_t len)
 
 static void *tty_main (void *arg);
 
-#include <signal.h>
-#define INTR_REQ_USB SIGUSR1
 #define PRIO_TTY      4
 
 static char __process3_stack_base__[4096];
@@ -647,7 +645,7 @@ tty_open (void)
   tty0.flag_connected = 0;
   tty0.flag_send_ready = 1;
   tty0.flag_input_avail = 0;
-  tty0.device_state = UNCONNECTED;
+  tty0.device_state = USB_DEVICE_STATE_UNCONNECTED;
   memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
 
   chopstx_create (PRIO_TTY, STACK_ADDR_TTY, STACK_SIZE_TTY, tty_main, &tty0);
@@ -662,31 +660,8 @@ tty_main (void *arg)
   struct usb_dev dev;
   int e;
 
-#if defined(OLDER_SYS_H)
-  /*
-   * Historically (before sys < 3.0), NVIC priority setting for USB
-   * interrupt was done in usb_lld_sys_init.  Thus this code.
-   *
-   * When USB interrupt occurs between usb_lld_init (which assumes
-   * ISR) and chopstx_claim_irq (which clears pending interrupt),
-   * invocation of usb_lld_event_handler won't occur.
-   *
-   * Calling usb_lld_event_handler is no harm even if there were no
-   * interrupts, thus, we call it unconditionally here, just in case
-   * if there is a request.
-   *
-   * We can't call usb_lld_init after chopstx_claim_irq, as
-   * usb_lld_init does its own setting for NVIC.  Calling
-   * chopstx_claim_irq after usb_lld_init overrides that.
-   *
-   */
-  usb_lld_init (&dev, VCOM_FEATURE_BUS_POWERED);
-  chopstx_claim_irq (&usb_intr, INTR_REQ_USB);
-  goto event_handle;
-#else
   chopstx_claim_irq (&usb_intr, INTR_REQ_USB);
   usb_lld_init (&dev, VCOM_FEATURE_BUS_POWERED);
-#endif
 
   while (1)
     {
@@ -694,9 +669,7 @@ tty_main (void *arg)
       if (usb_intr.ready)
 	{
 	  uint8_t ep_num;
-#if defined(OLDER_SYS_H)
+
-	event_handle:
-#endif
 	  /*
 	   * When interrupt is detected, call usb_lld_event_handler.
 	   * The event may be one of following:
@@ -710,6 +683,7 @@ tty_main (void *arg)
 	   *        
 	   */
 	  e = usb_lld_event_handler (&dev);
+	  chopstx_intr_done (&usb_intr);
 	  ep_num = USB_EVENT_ENDP (e);
 
 	  if (ep_num != 0)
@@ -734,7 +708,7 @@ tty_main (void *arg)
 		 * OK.
 		 */
 		chopstx_mutex_lock (&tty0.mtx);
-		tty0.device_state = ADDRESSED;
+		tty0.device_state = USB_DEVICE_STATE_ADDRESSED;
 		chopstx_cond_signal (&tty0.cnd);
 		chopstx_mutex_unlock (&tty0.mtx);
 		continue;
@@ -790,7 +764,7 @@ tty_main (void *arg)
 	}
 
       chopstx_mutex_lock (&t->mtx);
-      if (t->device_state == CONFIGURED && t->flag_connected
+      if (t->device_state == USB_DEVICE_STATE_CONFIGURED && t->flag_connected
 	  && t->flag_send_ready)
 	{
 	  uint8_t line[32];
@@ -814,7 +788,7 @@ void
 tty_wait_configured (struct tty *t)
 {
   chopstx_mutex_lock (&t->mtx);
-  while (t->device_state != CONFIGURED)
+  while (t->device_state != USB_DEVICE_STATE_CONFIGURED)
     chopstx_cond_wait (&t->cnd, &t->mtx);
   chopstx_mutex_unlock (&t->mtx);
 }

example-cdc/Makefile

@@ -3,13 +3,14 @@
 PROJECT = sample
 
 CHOPSTX = ..
-LDSCRIPT= sample.ld
+LDSCRIPT= sample.ld.m4
 CSRC = sample.c usb-cdc.c
 
-CHIP=stm32f103
+CHIP=stm32l4
 
 USE_SYS = yes
 USE_USB = yes
+ENABLE_OUTPUT_HEX=yes
 
 ###################################
 CROSS = arm-none-eabi-
@@ -17,9 +18,9 @@ CC   = $(CROSS)gcc
 LD   = $(CROSS)gcc
 OBJCOPY   = $(CROSS)objcopy
 
-MCU   = cortex-m3
+MCU   = cortex-m4
 CWARN = -Wall -Wextra -Wstrict-prototypes
-DEFS  = -DUSE_SYS3 -DFREE_STANDING
+DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=80
 OPT   = -O3 -Os -g
 LIBS  =
 

example-cdc/board.h

@@ -1 +1 @@
-../board/board-fst-01.h
+../board/board-st-nucleo-l432.h

example-cdc/sample.ld.m4

@@ -0,0 +1,107 @@
+/*
+ * ST32L4 memory setup.
+ */
+MEMORY
+{
+    flash  : org = 0x08000000, len = 256k
+    ram : org = 0x20000000, len = 48k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN(16);
+	_sys = .;
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .stacks (NOLOAD) :
+    {
+        *(.main_stack)
+        *(.process_stack.0)
+        *(.process_stack.1)
+        *(.process_stack.2)
+        *(.process_stack.3)
+        . = ALIGN(8);
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;

example-cdc/usb-cdc.c

@@ -2,6 +2,7 @@
 #include <stdlib.h>
 #include <chopstx.h>
 #include <string.h>
+#include "board.h"
 #include "usb_lld.h"
 #include "tty.h"
 
@@ -248,7 +249,7 @@ usb_device_reset (struct usb_dev *dev)
   tty0.flag_connected = 0;
   tty0.flag_send_ready = 1;
   tty0.flag_input_avail = 0;
-  tty0.device_state = ATTACHED;
+  tty0.device_state = USB_DEVICE_STATE_ATTACHED;
   memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
   chopstx_mutex_unlock (&tty0.mtx);
 }
@@ -417,7 +418,7 @@ usb_set_configuration (struct usb_dev *dev)
       for (i = 0; i < NUM_INTERFACES; i++)
 	vcom_setup_endpoints_for_interface (i, 0);
       chopstx_mutex_lock (&tty0.mtx);
-      tty0.device_state = CONFIGURED;
+      tty0.device_state = USB_DEVICE_STATE_CONFIGURED;
       chopstx_cond_signal (&tty0.cnd);
       chopstx_mutex_unlock (&tty0.mtx);
     }
@@ -430,7 +431,7 @@ usb_set_configuration (struct usb_dev *dev)
       for (i = 0; i < NUM_INTERFACES; i++)
 	vcom_setup_endpoints_for_interface (i, 1);
       chopstx_mutex_lock (&tty0.mtx);
-      tty0.device_state = ADDRESSED;
+      tty0.device_state = USB_DEVICE_STATE_ADDRESSED;
       chopstx_cond_signal (&tty0.cnd);
       chopstx_mutex_unlock (&tty0.mtx);
     }
@@ -639,7 +640,6 @@ usb_rx_ready (uint8_t ep_num, uint16_t len)
 
 static void *tty_main (void *arg);
 
-#define INTR_REQ_USB 20
 #define PRIO_TTY      4
 
 #define STACK_PROCESS_3
@@ -657,7 +657,7 @@ tty_open (void)
   tty0.flag_connected = 0;
   tty0.flag_send_ready = 1;
   tty0.flag_input_avail = 0;
-  tty0.device_state = UNCONNECTED;
+  tty0.device_state = USB_DEVICE_STATE_UNCONNECTED;
   memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
 
   chopstx_create (PRIO_TTY, STACK_ADDR_TTY, STACK_SIZE_TTY, tty_main, &tty0);
@@ -672,31 +672,8 @@ tty_main (void *arg)
   struct usb_dev dev;
   int e;
 
-#if defined(OLDER_SYS_H)
-  /*
-   * Historically (before sys < 3.0), NVIC priority setting for USB
-   * interrupt was done in usb_lld_sys_init.  Thus this code.
-   *
-   * When USB interrupt occurs between usb_lld_init (which assumes
-   * ISR) and chopstx_claim_irq (which clears pending interrupt),
-   * invocation of usb_lld_event_handler won't occur.
-   *
-   * Calling usb_lld_event_handler is no harm even if there were no
-   * interrupts, thus, we call it unconditionally here, just in case
-   * if there is a request.
-   *
-   * We can't call usb_lld_init after chopstx_claim_irq, as
-   * usb_lld_init does its own setting for NVIC.  Calling
-   * chopstx_claim_irq after usb_lld_init overrides that.
-   *
-   */
-  usb_lld_init (&dev, VCOM_FEATURE_BUS_POWERED);
-  chopstx_claim_irq (&usb_intr, INTR_REQ_USB);
-  goto event_handle;
-#else
   chopstx_claim_irq (&usb_intr, INTR_REQ_USB);
   usb_lld_init (&dev, VCOM_FEATURE_BUS_POWERED);
-#endif
 
   while (1)
     {
@@ -704,9 +681,7 @@ tty_main (void *arg)
       if (usb_intr.ready)
 	{
 	  uint8_t ep_num;
-#if defined(OLDER_SYS_H)
+
-	event_handle:
-#endif
 	  /*
 	   * When interrupt is detected, call usb_lld_event_handler.
 	   * The event may be one of following:
@@ -720,6 +695,7 @@ tty_main (void *arg)
 	   *        
 	   */
 	  e = usb_lld_event_handler (&dev);
+	  chopstx_intr_done (&usb_intr);
 	  ep_num = USB_EVENT_ENDP (e);
 
 	  if (ep_num != 0)
@@ -744,7 +720,7 @@ tty_main (void *arg)
 		 * OK.
 		 */
 		chopstx_mutex_lock (&tty0.mtx);
-		tty0.device_state = ADDRESSED;
+		tty0.device_state = USB_DEVICE_STATE_ADDRESSED;
 		chopstx_cond_signal (&tty0.cnd);
 		chopstx_mutex_unlock (&tty0.mtx);
 		continue;
@@ -800,7 +776,7 @@ tty_main (void *arg)
 	}
 
       chopstx_mutex_lock (&t->mtx);
-      if (t->device_state == CONFIGURED && t->flag_connected
+      if (t->device_state == USB_DEVICE_STATE_CONFIGURED && t->flag_connected
 	  && t->flag_send_ready)
 	{
 	  uint8_t line[32];
@@ -824,7 +800,7 @@ void
 tty_wait_configured (struct tty *t)
 {
   chopstx_mutex_lock (&t->mtx);
-  while (t->device_state != CONFIGURED)
+  while (t->device_state != USB_DEVICE_STATE_CONFIGURED)
     chopstx_cond_wait (&t->cnd, &t->mtx);
   chopstx_mutex_unlock (&t->mtx);
 }

example-fraucheky/Makefile

@@ -9,7 +9,7 @@ LDSCRIPT=
 
 CSRC = main.c
 CHIP=gnu-linux
-USE_SYS =
+USE_SYS = yes
 USE_USB = yes
 EMULATION=yes
 # USE_ADC = yes

example-fraucheky/main.c

@@ -11,13 +11,14 @@
 
 static chopstx_mutex_t usb_mtx;
 static chopstx_cond_t usb_cnd;
-static uint32_t bDeviceState = UNCONNECTED; /* USB device status */
+static uint32_t bDeviceState = USB_DEVICE_STATE_UNCONNECTED;
 
 extern void EP6_IN_Callback (uint16_t len);
 extern void EP6_OUT_Callback (uint16_t len);
 
 #define MSC_MASS_STORAGE_RESET_COMMAND 0xFF
 extern int fraucheky_enabled (void);
+extern void fraucheky_init (void);
 extern void fraucheky_main (void);
 
 extern void fraucheky_setup_endpoints_for_interface (struct usb_dev *dev, int stop);
@@ -41,13 +42,9 @@ usb_device_reset (struct usb_dev *dev)
   /* Initialize Endpoint 0.  */
   usb_lld_setup_endp (dev, ENDP0, 1, 1);
 
-  /* Stop the interface */
-  for (i = 0; i < NUM_INTERFACES; i++)
-    setup_endpoints_for_interface (dev, i, 1);
-
   /* Notify upper layer.  */
   chopstx_mutex_lock (&usb_mtx);
-  bDeviceState = ATTACHED;
+  bDeviceState = USB_DEVICE_STATE_ATTACHED;
   chopstx_cond_signal (&usb_cnd);
   chopstx_mutex_unlock (&usb_mtx);
 }
@@ -95,7 +92,7 @@ usb_set_configuration (struct usb_dev *dev)
       for (i = 0; i < NUM_INTERFACES; i++)
 	setup_endpoints_for_interface (dev, i, 0);
       chopstx_mutex_lock (&usb_mtx);
-      bDeviceState = CONFIGURED;
+      bDeviceState = USB_DEVICE_STATE_CONFIGURED;
       chopstx_mutex_unlock (&usb_mtx);
     }
   else if (current_conf != dev->dev_req.value)
@@ -107,7 +104,7 @@ usb_set_configuration (struct usb_dev *dev)
       for (i = 0; i < NUM_INTERFACES; i++)
 	setup_endpoints_for_interface (dev, i, 1);
       chopstx_mutex_lock (&usb_mtx);
-      bDeviceState = ADDRESSED;
+      bDeviceState = USB_DEVICE_STATE_ADDRESSED;
       chopstx_cond_signal (&usb_cnd);
       chopstx_mutex_unlock (&usb_mtx);
     }
@@ -164,7 +161,6 @@ static void usb_tx_done (uint8_t ep_num, uint16_t len);
 static void usb_rx_ready (uint8_t ep_num, uint16_t len);
 
 
-#define INTR_REQ_USB SIGUSR1
 #define PRIO_USB 3
 
 static void *
@@ -177,7 +173,6 @@ usb_main (void *arg)
   (void)arg;
   chopstx_claim_irq (&interrupt, INTR_REQ_USB);
   usb_lld_init (&dev, FEATURE_BUS_POWERED);
-  goto event_handle;	/* For old SYS < 3.0 */
 
   while (1)
     {
@@ -187,8 +182,8 @@ usb_main (void *arg)
 	{
 	  uint8_t ep_num;
 
-	event_handle:
 	  e = usb_lld_event_handler (&dev);
+	  chopstx_intr_done (&interrupt);
 	  ep_num = USB_EVENT_ENDP (e);
 
 	  if (ep_num != 0)
@@ -207,7 +202,7 @@ usb_main (void *arg)
 
 	      case USB_EVENT_DEVICE_ADDRESSED:
 		chopstx_mutex_lock (&usb_mtx);
-		bDeviceState = ADDRESSED;
+		bDeviceState = USB_DEVICE_STATE_ADDRESSED;
 		chopstx_cond_signal (&usb_cnd);
 		chopstx_mutex_unlock (&usb_mtx);
 		continue;
@@ -305,16 +300,17 @@ main (int argc, char **argv)
   chopstx_mutex_init (&usb_mtx);
   chopstx_cond_init (&usb_cnd);
 
-  bDeviceState = UNCONNECTED;
+  bDeviceState = USB_DEVICE_STATE_UNCONNECTED;
   usb_thd = chopstx_create (PRIO_USB, STACK_ADDR_USB, STACK_SIZE_USB,
 			    usb_main, NULL);
-  while (bDeviceState != CONFIGURED)
+  fraucheky_init ();
+  while (bDeviceState != USB_DEVICE_STATE_CONFIGURED)
     chopstx_usec_wait (250*1000);
   fraucheky_main ();
   chopstx_cancel (usb_thd);
   chopstx_join (usb_thd, NULL);
   usb_lld_shutdown ();
-  bDeviceState = UNCONNECTED;
+  bDeviceState = USB_DEVICE_STATE_UNCONNECTED;
 
   return 0;
 }

example-fs-bb48/touch.c

@@ -74,6 +74,7 @@ touch_get (void)
   TPM1->SC = 0;
   TPM1->CNT = 0xffff;	   /* Writing causes reset of the counter.  */
 
+  chopstx_intr_done (&tpm1_intr);
   return v;
 }
 

example-fs-bb48/usb-cdc.c

@@ -245,7 +245,7 @@ usb_device_reset (struct usb_dev *dev)
   tty0.flag_connected = 0;
   tty0.flag_send_ready = 1;
   tty0.flag_input_avail = 0;
-  tty0.device_state = ATTACHED;
+  tty0.device_state = USB_DEVICE_STATE_ATTACHED;
   memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
   chopstx_mutex_unlock (&tty0.mtx);
 }
@@ -409,7 +409,7 @@ usb_set_configuration (struct usb_dev *dev)
       for (i = 0; i < NUM_INTERFACES; i++)
 	vcom_setup_endpoints_for_interface (dev, i, 0);
       chopstx_mutex_lock (&tty0.mtx);
-      tty0.device_state = CONFIGURED;
+      tty0.device_state = USB_DEVICE_STATE_CONFIGURED;
       chopstx_cond_signal (&tty0.cnd);
       chopstx_mutex_unlock (&tty0.mtx);
     }
@@ -422,7 +422,7 @@ usb_set_configuration (struct usb_dev *dev)
       for (i = 0; i < NUM_INTERFACES; i++)
 	vcom_setup_endpoints_for_interface (dev, i, 1);
       chopstx_mutex_lock (&tty0.mtx);
-      tty0.device_state = ADDRESSED;
+      tty0.device_state = USB_DEVICE_STATE_ADDRESSED;
       chopstx_cond_signal (&tty0.cnd);
       chopstx_mutex_unlock (&tty0.mtx);
     }
@@ -626,7 +626,6 @@ usb_rx_ready (uint8_t ep_num, uint16_t len)
 
 static void *tty_main (void *arg);
 
-#define INTR_REQ_USB 24
 #define PRIO_TTY      4
 
 extern uint8_t __process3_stack_base__[], __process3_stack_size__[];
@@ -643,7 +642,7 @@ tty_open (void)
   tty0.flag_connected = 0;
   tty0.flag_send_ready = 1;
   tty0.flag_input_avail = 0;
-  tty0.device_state = UNCONNECTED;
+  tty0.device_state = USB_DEVICE_STATE_UNCONNECTED;
   memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
 
   chopstx_create (PRIO_TTY, STACK_ADDR_TTY, STACK_SIZE_TTY, tty_main, &tty0);
@@ -658,31 +657,8 @@ tty_main (void *arg)
   struct usb_dev dev;
   int e;
 
-#if defined(OLDER_SYS_H)
-  /*
-   * Historically (before sys < 3.0), NVIC priority setting for USB
-   * interrupt was done in usb_lld_sys_init.  Thus this code.
-   *
-   * When USB interrupt occurs between usb_lld_init (which assumes
-   * ISR) and chopstx_claim_irq (which clears pending interrupt),
-   * invocation of usb_lld_event_handler won't occur.
-   *
-   * Calling usb_lld_event_handler is no harm even if there were no
-   * interrupts, thus, we call it unconditionally here, just in case
-   * if there is a request.
-   *
-   * We can't call usb_lld_init after chopstx_claim_irq, as
-   * usb_lld_init does its own setting for NVIC.  Calling
-   * chopstx_claim_irq after usb_lld_init overrides that.
-   *
-   */
-  usb_lld_init (&dev, VCOM_FEATURE_BUS_POWERED);
-  chopstx_claim_irq (&usb_intr, INTR_REQ_USB);
-  goto event_handle;
-#else
   chopstx_claim_irq (&usb_intr, INTR_REQ_USB);
   usb_lld_init (&dev, VCOM_FEATURE_BUS_POWERED);
-#endif
 
   while (1)
     {
@@ -693,9 +669,7 @@ tty_main (void *arg)
       if (usb_intr.ready)
 	{
 	  uint8_t ep_num;
-#if defined(OLDER_SYS_H)
+
-	event_handle:
-#endif
 	  /*
 	   * When interrupt is detected, call usb_lld_event_handler.
 	   * The event may be one of following:
@@ -709,6 +683,7 @@ tty_main (void *arg)
 	   *        
 	   */
 	  e = usb_lld_event_handler (&dev);
+	  chopstx_intr_done (&usb_intr);
 	  ep_num = USB_EVENT_ENDP (e);
 
 	  if (ep_num != 0)
@@ -733,7 +708,7 @@ tty_main (void *arg)
 		 * OK.
 		 */
 		chopstx_mutex_lock (&tty0.mtx);
-		tty0.device_state = ADDRESSED;
+		tty0.device_state = USB_DEVICE_STATE_ADDRESSED;
 		chopstx_cond_signal (&tty0.cnd);
 		chopstx_mutex_unlock (&tty0.mtx);
 		continue;
@@ -789,7 +764,7 @@ tty_main (void *arg)
 	}
 
       chopstx_mutex_lock (&t->mtx);
-      if (t->device_state == CONFIGURED && t->flag_connected
+      if (t->device_state == USB_DEVICE_STATE_CONFIGURED && t->flag_connected
 	  && t->flag_send_ready)
 	{
 	  uint8_t line[32];
@@ -813,7 +788,7 @@ void
 tty_wait_configured (struct tty *t)
 {
   chopstx_mutex_lock (&t->mtx);
-  while (t->device_state != CONFIGURED)
+  while (t->device_state != USB_DEVICE_STATE_CONFIGURED)
     chopstx_cond_wait (&t->cnd, &t->mtx);
   chopstx_mutex_unlock (&t->mtx);
 }

example-fsm-55/Makefile

@@ -7,6 +7,8 @@ LDSCRIPT= hacker-emblem.ld
 
 CSRC = reset.c hh.c
 
+CHIP=stm32f0
+
 # Hacker Emblem and "Happy Hacking!" demonstration
 # CSRC = reset.c hh.c
 
@@ -25,7 +27,7 @@ OBJCOPY   = $(CROSS)objcopy
 MCU   = cortex-m0 # -save-temps
 CWARN = -Wall -Wextra -Wstrict-prototypes
 DEFS  = -DMAKE_ENTRY_PUBLIC \
-        -DFREE_STANDING -DMHZ=48 -DUSE_WFI_FOR_IDLE
+        -DFREE_STANDING -DMHZ=48
 OPT   = -O3 -Os -g
 LIBS  =
 

example-fsm-55/debian-logo.c

@@ -7,7 +7,7 @@
 static uint8_t main_finished;
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
 #define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
@@ -163,17 +163,19 @@ button (void *arg)
   return NULL;
 }
 
+#define STACK_MAIN
+#define STACK_PROCESS_1
+#define STACK_PROCESS_2
+#include "stack-def.h"
+
 #define PRIO_LED 3
 #define PRIO_BUTTON 2
 
-extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+#define STACK_ADDR_LED ((uint32_t)process1_base)
-extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
+#define STACK_SIZE_LED (sizeof process1_base)
 
-#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
+#define STACK_ADDR_BUTTON ((uint32_t)process2_base)
-#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
+#define STACK_SIZE_BUTTON (sizeof process2_base)
-
-#define STACK_ADDR_BUTTON ((uint32_t)__process2_stack_base__)
-#define STACK_SIZE_BUTTON ((uint32_t)__process2_stack_size__)
 
 #define DATA55(x0,x1,x2,x3,x4) (x0<<20)|(x1<<15)|(x2<<10)|(x3<< 5)|(x4<< 0)
 #define SIZE55(img) (sizeof (img) / sizeof (uint32_t))
@@ -365,8 +367,6 @@ text_display (uint8_t kind)
 }
 
 
-static void setup_scr_sleepdeep (void);
-
 int
 main (int argc, const char *argv[])
 {
@@ -378,6 +378,8 @@ main (int argc, const char *argv[])
   (void)argc;
   (void)argv;
 
+  chopstx_conf_idle (1);
+
   chopstx_mutex_init (&mtx);
   chopstx_cond_init (&cnd0);
   chopstx_cond_init (&cnd1);
@@ -418,56 +420,6 @@ main (int argc, const char *argv[])
   chopstx_join (button_thd, NULL);
   chopstx_join (led_thd, NULL);
 
-  setup_scr_sleepdeep ();
+  chopstx_conf_idle (4);
-  for (;;)
-    asm volatile ("wfi" : : : "memory");
-
   return 0;
 }
-
-struct SCB
-{
-  volatile uint32_t CPUID;
-  volatile uint32_t ICSR;
-  volatile uint32_t VTOR;
-  volatile uint32_t AIRCR;
-  volatile uint32_t SCR;
-  volatile uint32_t CCR;
-  volatile uint8_t  SHP[12];
-  volatile uint32_t SHCSR;
-  volatile uint32_t CFSR;
-  volatile uint32_t HFSR;
-  volatile uint32_t DFSR;
-  volatile uint32_t MMFAR;
-  volatile uint32_t BFAR;
-  volatile uint32_t AFSR;
-  volatile uint32_t PFR[2];
-  volatile uint32_t DFR;
-  volatile uint32_t ADR;
-  volatile uint32_t MMFR[4];
-  volatile uint32_t ISAR[5];
-};
-
-#define SCS_BASE	(0xE000E000)
-#define SCB_BASE	(SCS_BASE +  0x0D00)
-static struct SCB *const SCB = ((struct SCB *)SCB_BASE);
-
-#define SCB_SCR_SLEEPDEEP (1 << 2)
-
-struct PWR
-{
-  volatile uint32_t CR;
-  volatile uint32_t CSR;
-};
-#define PWR_CR_PDDS 0x0002
-#define PWR_CR_CWUF 0x0004
-
-#define PWR_BASE	(APBPERIPH_BASE + 0x00007000)
-#define PWR		((struct PWR *) PWR_BASE)
-
-static void setup_scr_sleepdeep (void)
-{
-  PWR->CR |= PWR_CR_CWUF;
-  PWR->CR |= PWR_CR_PDDS;
-  SCB->SCR |= SCB_SCR_SLEEPDEEP;
-}

example-fsm-55/hacker-emblem.ld

@@ -1,12 +1,6 @@
 /*
  * ST32F0 memory setup.
  */
-__main_stack_size__     = 0x0100;  /* Idle+Exception handlers */
-__process0_stack_size__  = 0x0100; /* Main program            */
-__process1_stack_size__  = 0x0100; /* first thread program    */
-__process2_stack_size__  = 0x0100; /* second thread program   */
-__process3_stack_size__  = 0x0100; /* third thread program    */
-
 MEMORY
 {
     flash  : org = 0x08000000, len = 16k
@@ -61,34 +55,15 @@ SECTIONS
     _etext = .;
     _textdata = _etext;
 
-    .process_stack :
+    .stacks (NOLOAD) :
     {
         . = ALIGN(8);
-        __process3_stack_base__ = .;
+        *(.main_stack)
-        . += __process3_stack_size__;
+        *(.process_stack.0)
+        *(.process_stack.1)
+        *(.process_stack.2)
+        *(.process_stack.3)
         . = ALIGN(8);
-        __process3_stack_end__ = .;
-        __process2_stack_base__ = .;
-        . += __process2_stack_size__;
-        . = ALIGN(8);
-        __process2_stack_end__ = .;
-        __process1_stack_base__ = .;
-        . += __process1_stack_size__;
-        . = ALIGN(8);
-        __process1_stack_end__ = .;
-        __process0_stack_base__ = .;
-        . += __process0_stack_size__;
-        . = ALIGN(8);
-        __process0_stack_end__ = .;
-    } > ram
-
-    .main_stack :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
     } > ram
 
     .data :

example-fsm-55/hh.c

@@ -7,7 +7,7 @@
 static uint8_t main_finished;
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
 #define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
@@ -166,14 +166,16 @@ button (void *arg)
 #define PRIO_LED 3
 #define PRIO_BUTTON 2
 
-extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+#define STACK_MAIN
-extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
+#define STACK_PROCESS_1
+#define STACK_PROCESS_2
+#include "stack-def.h"
 
-#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
+#define STACK_ADDR_LED ((uint32_t)process1_base)
-#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
+#define STACK_SIZE_LED (sizeof process1_base)
 
-#define STACK_ADDR_BUTTON ((uint32_t)__process2_stack_base__)
+#define STACK_ADDR_BUTTON ((uint32_t)process2_base)
-#define STACK_SIZE_BUTTON ((uint32_t)__process2_stack_size__)
+#define STACK_SIZE_BUTTON (sizeof process2_base)
 
 #define DATA55(x0,x1,x2,x3,x4) (x0<<20)|(x1<<15)|(x2<<10)|(x3<< 5)|(x4<< 0)
 #define SIZE55(img) (sizeof (img) / sizeof (uint32_t))
@@ -355,8 +357,6 @@ text_display (uint8_t kind)
 }
 
 
-static void setup_scr_sleepdeep (void);
-
 int
 main (int argc, const char *argv[])
 {
@@ -366,6 +366,8 @@ main (int argc, const char *argv[])
   (void)argc;
   (void)argv;
 
+  chopstx_conf_idle (1);
+
   chopstx_mutex_init (&mtx);
   chopstx_cond_init (&cnd0);
   chopstx_cond_init (&cnd1);
@@ -406,56 +408,6 @@ main (int argc, const char *argv[])
   chopstx_join (button_thd, NULL);
   chopstx_join (led_thd, NULL);
 
-  setup_scr_sleepdeep ();
+  chopstx_conf_idle (4);
-  for (;;)
-    asm volatile ("wfi" : : : "memory");
-
   return 0;
 }
-
-struct SCB
-{
-  volatile uint32_t CPUID;
-  volatile uint32_t ICSR;
-  volatile uint32_t VTOR;
-  volatile uint32_t AIRCR;
-  volatile uint32_t SCR;
-  volatile uint32_t CCR;
-  volatile uint8_t  SHP[12];
-  volatile uint32_t SHCSR;
-  volatile uint32_t CFSR;
-  volatile uint32_t HFSR;
-  volatile uint32_t DFSR;
-  volatile uint32_t MMFAR;
-  volatile uint32_t BFAR;
-  volatile uint32_t AFSR;
-  volatile uint32_t PFR[2];
-  volatile uint32_t DFR;
-  volatile uint32_t ADR;
-  volatile uint32_t MMFR[4];
-  volatile uint32_t ISAR[5];
-};
-
-#define SCS_BASE	(0xE000E000)
-#define SCB_BASE	(SCS_BASE +  0x0D00)
-static struct SCB *const SCB = ((struct SCB *)SCB_BASE);
-
-#define SCB_SCR_SLEEPDEEP (1 << 2)
-
-struct PWR
-{
-  volatile uint32_t CR;
-  volatile uint32_t CSR;
-};
-#define PWR_CR_PDDS 0x0002
-#define PWR_CR_CWUF 0x0004
-
-#define PWR_BASE	(APBPERIPH_BASE + 0x00007000)
-#define PWR		((struct PWR *) PWR_BASE)
-
-static void setup_scr_sleepdeep (void)
-{
-  PWR->CR |= PWR_CR_CWUF;
-  PWR->CR |= PWR_CR_PDDS;
-  SCB->SCR |= SCB_SCR_SLEEPDEEP;
-}

example-fsm-55/hiroshi-ayumi.c

@@ -6,7 +6,7 @@
 #include "board.h"
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
 #define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
@@ -86,12 +86,16 @@ led_enable_column (uint8_t col)
 }
 
 
+#define STACK_MAIN
+#define STACK_PROCESS_1
+#define STACK_PROCESS_2
+#define STACK_PROCESS_3
+#include "stack-def.h"
+
 #define PRIO_LED 3
 
-extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+#define STACK_ADDR_LED ((uint32_t)process1_base)
-
+#define STACK_SIZE_LED (sizeof process1_base)
-#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
-#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
 
 static void *
 led (void *arg)
@@ -119,10 +123,9 @@ led (void *arg)
 
 
 #define PRIO_SPK 4
-extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
 
-#define STACK_ADDR_SPK ((uint32_t)__process2_stack_base__)
+#define STACK_ADDR_SPK ((uint32_t)process2_base)
-#define STACK_SIZE_SPK ((uint32_t)__process2_stack_size__)
+#define STACK_SIZE_SPK (sizeof process2_base)
 
 static chopstx_mutex_t spk_mtx;
 static chopstx_cond_t spk_cnd;
@@ -193,10 +196,9 @@ spk (void *arg)
 
 
 #define PRIO_MUSIC 2
-extern uint8_t __process3_stack_base__[], __process3_stack_size__[];
 
-#define STACK_ADDR_MUSIC ((uint32_t)__process3_stack_base__)
+#define STACK_ADDR_MUSIC ((uint32_t)process3_base)
-#define STACK_SIZE_MUSIC ((uint32_t)__process3_stack_size__)
+#define STACK_SIZE_MUSIC (sizeof process3_base)
 
 #define C 0
 #define D 1

example-fsm-55/stack-def.h

@@ -0,0 +1,54 @@
+#define MAIN_SIZE 0x0080 /* Idle+Exception handlers  */
+#define SIZE_0 0x0100 /* Main program             */
+#define SIZE_1 0x0100 /* first thread program     */
+#define SIZE_2 0x0100 /* second thread program    */ 
+#define SIZE_3 0x0100 /* third thread program     */ 
+
+#if defined(STACK_MAIN)
+/*
+ * The terminology of "main" is confusing in ARM architecture.
+ * Here, "main_base" is for exception handlers.
+ */
+/* Idle+Exception handlers */
+char __main_stack_end__[0] __attribute__ ((section(".main_stack")));
+char main_base[MAIN_SIZE] __attribute__ ((section(".main_stack")));
+
+/* Main program            */
+char __process0_stack_end__[0] __attribute__ ((section(".process_stack.0")));
+char process0_base[SIZE_0] __attribute__ ((section(".process_stack.0")));
+#endif
+
+/* First thread program    */
+#if defined(STACK_PROCESS_1)
+char process1_base[SIZE_1] __attribute__ ((section(".process_stack.1"))); 
+#endif
+
+/* Second thread program   */
+#if defined(STACK_PROCESS_2)
+char process2_base[SIZE_2] __attribute__ ((section(".process_stack.2")));
+#endif
+
+/* Third thread program    */
+#if defined(STACK_PROCESS_3)
+char process3_base[SIZE_3] __attribute__ ((section(".process_stack.3")));
+#endif
+
+/* Fourth thread program    */
+#if defined(STACK_PROCESS_4)
+char process4_base[SIZE_4] __attribute__ ((section(".process_stack.4")));
+#endif
+
+/* Fifth thread program    */
+#if defined(STACK_PROCESS_5)
+char process5_base[SIZE_5] __attribute__ ((section(".process_stack.5")));
+#endif
+
+/* Sixth thread program    */
+#if defined(STACK_PROCESS_6)
+char process6_base[SIZE_6] __attribute__ ((section(".process_stack.6")));
+#endif
+
+/* Seventh thread program    */
+#if defined(STACK_PROCESS_7)
+char process7_base[SIZE_7] __attribute__ ((section(".process_stack.7")));
+#endif

example-led/Makefile

@@ -2,15 +2,20 @@
 
 PROJECT = sample
 
-### Currently, it's for STM32F0 Discovery.
+### Currently, it is for STM32 Nucleo L432
+### 
 ### Please change lines started with '###' for Cortex-M3 board.
+###
+### Please change lines started with '###' for Cortex-M0+ board
+### (STM32F0 Discovery).
 
 CHOPSTX = ..
-LDSCRIPT= sample.ld
+LDSCRIPT= sample.ld.m4
+### LDSCRIPT= sample.ld
 ### LDSCRIPT= sample.ld.m3
 CSRC = sample.c
 
-CHIP=stm32f0
+CHIP=stm32l4
 USE_SYS = yes
 
 ###################################
@@ -20,9 +25,10 @@ LD   = $(CROSS)gcc
 OBJCOPY   = $(CROSS)objcopy
 
 ### MCU   = cortex-m3
-MCU   = cortex-m0
+### MCU   = cortex-m0
+MCU   = cortex-m4
 CWARN = -Wall -Wextra -Wstrict-prototypes
-DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=48
+DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=80
 ### DEFS  = -DFREE_STANDING -DUSE_SYS3 -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
 OPT   = -O3 -Os -g
 LIBS  =

example-led/board.h

@@ -1 +1 @@
-../board/board-stm32f0-discovery.h
+../board/board-st-nucleo-l432.h

example-led/sample.c

@@ -1,6 +1,8 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <chopstx.h>
+
+#include "board.h"
 #include "sys.h" /* for set_led */
 
 static chopstx_mutex_t mtx;
@@ -72,14 +74,17 @@ blk (void *arg)
 #define PRIO_BLK 2
 #endif
 
-extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+#define STACK_MAIN
-extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
+#define STACK_PROCESS_1
+#define STACK_PROCESS_2
+#include "stack-def.h"
 
-#define STACK_ADDR_PWM ((uint32_t)__process1_stack_base__)
-#define STACK_SIZE_PWM ((uint32_t)__process1_stack_size__)
 
-#define STACK_ADDR_BLK ((uint32_t)__process2_stack_base__)
+#define STACK_ADDR_PWM ((uint32_t)process1_base)
-#define STACK_SIZE_BLK ((uint32_t)__process2_stack_size__)
+#define STACK_SIZE_PWM (sizeof process1_base)
+
+#define STACK_ADDR_BLK ((uint32_t)process2_base)
+#define STACK_SIZE_BLK (sizeof process2_base)
 
 
 int

example-led/sample.ld

@@ -1,12 +1,6 @@
 /*
  * ST32F0 memory setup.
  */
-__main_stack_size__      = 0x0100; /* Idle+Exception handlers */
-__process0_stack_size__  = 0x0100; /* Main program            */
-__process1_stack_size__  = 0x0100; /* first thread program    */
-__process2_stack_size__  = 0x0100; /* second thread program   */
-__process3_stack_size__  = 0x0100; /* third thread program    */
-
 MEMORY
 {
     flash0 : org = 0x08000000, len = 4k
@@ -87,34 +81,15 @@ SECTIONS
 	KEEP(*(.bss.startup.*))
     } > ram
 
-    .process_stack :
+    .stacks (NOLOAD) :
     {
         . = ALIGN(8);
-        __process3_stack_base__ = .;
+        *(.main_stack)
-        . += __process3_stack_size__;
+        *(.process_stack.0)
+        *(.process_stack.1)
+        *(.process_stack.2)
+        *(.process_stack.3)
         . = ALIGN(8);
-        __process3_stack_end__ = .;
-        __process2_stack_base__ = .;
-        . += __process2_stack_size__;
-        . = ALIGN(8);
-        __process2_stack_end__ = .;
-        __process1_stack_base__ = .;
-        . += __process1_stack_size__;
-        . = ALIGN(8);
-        __process1_stack_end__ = .;
-        __process0_stack_base__ = .;
-        . += __process0_stack_size__;
-        . = ALIGN(8);
-        __process0_stack_end__ = .;
-    } > ram
-
-    .main_stack :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
     } > ram
 
     .data :

example-led/sample.ld.m3

@@ -1,12 +1,6 @@
 /*
  * ST32F103 memory setup.
  */
-__main_stack_size__      = 0x0100; /* Idle+Exception handlers */
-__process0_stack_size__  = 0x0100; /* Main program            */
-__process1_stack_size__  = 0x0100; /* first thread program    */
-__process2_stack_size__  = 0x0100; /* second thread program   */
-__process3_stack_size__  = 0x0100; /* third thread program    */
-
 MEMORY
 {
     flash0 : org = 0x08000000, len = 4k
@@ -78,34 +72,14 @@ SECTIONS
     _etext = .;
     _textdata = _etext;
 
-    .process_stack :
+    .stacks (NOLOAD) :
     {
+        *(.main_stack)
+        *(.process_stack.0)
+        *(.process_stack.1)
+        *(.process_stack.2)
+        *(.process_stack.3)
         . = ALIGN(8);
-        __process3_stack_base__ = .;
-        . += __process3_stack_size__;
-        . = ALIGN(8);
-        __process3_stack_end__ = .;
-        __process2_stack_base__ = .;
-        . += __process2_stack_size__;
-        . = ALIGN(8);
-        __process2_stack_end__ = .;
-        __process1_stack_base__ = .;
-        . += __process1_stack_size__;
-        . = ALIGN(8);
-        __process1_stack_end__ = .;
-        __process0_stack_base__ = .;
-        . += __process0_stack_size__;
-        . = ALIGN(8);
-        __process0_stack_end__ = .;
-    } > ram
-
-    .main_stack :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
     } > ram
 
     .data :

example-led/sample.ld.m4

@@ -0,0 +1,107 @@
+/*
+ * ST32L4 memory setup.
+ */
+MEMORY
+{
+    flash  : org = 0x08000000, len = 256k
+    ram : org = 0x20000000, len = 48k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN(16);
+	_sys = .;
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .stacks (NOLOAD) :
+    {
+        *(.main_stack)
+        *(.process_stack.0)
+        *(.process_stack.1)
+        *(.process_stack.2)
+        *(.process_stack.3)
+        . = ALIGN(8);
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;

example-led/stack-def.h

@@ -0,0 +1,53 @@
+#define MAIN_SIZE 0x0080 /* Idle+Exception handlers  */
+#define SIZE_0 0x0100 /* Main program             */
+#define SIZE_1 0x0100 /* first thread program     */
+#define SIZE_2 0x0100 /* second thread program    */ 
+
+#if defined(STACK_MAIN)
+/*
+ * The terminology of "main" is confusing in ARM architecture.
+ * Here, "main_base" is for exception handlers.
+ */
+/* Idle+Exception handlers */
+char __main_stack_end__[0] __attribute__ ((section(".main_stack")));
+char main_base[MAIN_SIZE] __attribute__ ((section(".main_stack")));
+
+/* Main program            */
+char __process0_stack_end__[0] __attribute__ ((section(".process_stack.0")));
+char process0_base[SIZE_0] __attribute__ ((section(".process_stack.0")));
+#endif
+
+/* First thread program    */
+#if defined(STACK_PROCESS_1)
+char process1_base[SIZE_1] __attribute__ ((section(".process_stack.1"))); 
+#endif
+
+/* Second thread program   */
+#if defined(STACK_PROCESS_2)
+char process2_base[SIZE_2] __attribute__ ((section(".process_stack.2")));
+#endif
+
+/* Third thread program    */
+#if defined(STACK_PROCESS_3)
+char process3_base[SIZE_3] __attribute__ ((section(".process_stack.3")));
+#endif
+
+/* Fourth thread program    */
+#if defined(STACK_PROCESS_4)
+char process4_base[SIZE_4] __attribute__ ((section(".process_stack.4")));
+#endif
+
+/* Fifth thread program    */
+#if defined(STACK_PROCESS_5)
+char process5_base[SIZE_5] __attribute__ ((section(".process_stack.5")));
+#endif
+
+/* Sixth thread program    */
+#if defined(STACK_PROCESS_6)
+char process6_base[SIZE_6] __attribute__ ((section(".process_stack.6")));
+#endif
+
+/* Seventh thread program    */
+#if defined(STACK_PROCESS_7)
+char process7_base[SIZE_7] __attribute__ ((section(".process_stack.7")));
+#endif

example-primer2/lcd.c

@@ -6,7 +6,7 @@
 #include "board.h"
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 
 struct GPIO {

example-primer2/primer2-switches.c

@@ -4,7 +4,7 @@
 #include "board.h"
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 
 struct GPIO {

example-primer2/primer2-ts.c

@@ -107,6 +107,10 @@ void adc3_conversion (uint32_t *result)
   /* Stop conversion.  */
   ADC3->CR2 &= ~ADC_CR2_JSWSTART;
 
+#if USE_ADC3_INTR
+  chopstx_intr_done (&adc3_intr);
+#endif
+
   return;
 }
 

example-usart/Makefile

@@ -0,0 +1,47 @@
+# Makefile for example application of Chopstx
+
+PROJECT = sample
+
+### Currently, it is for STM32 Nucleo L432
+### 
+### Please change lines started with '###' for Cortex-M3 board.
+###
+### Please change lines started with '###' for Cortex-M0+ board
+### (STM32F0 Discovery).
+
+CHOPSTX = ..
+LDSCRIPT= sample.ld.m4
+### LDSCRIPT= sample.ld
+### LDSCRIPT= sample.ld.m3
+CSRC = sample.c
+
+CHIP=stm32l4
+USE_SYS = yes
+USE_USART = yes
+
+###################################
+CROSS = arm-none-eabi-
+CC   = $(CROSS)gcc
+LD   = $(CROSS)gcc
+OBJCOPY   = $(CROSS)objcopy
+
+### MCU   = cortex-m3
+### MCU   = cortex-m0
+MCU   = cortex-m4
+CWARN = -Wall -Wextra -Wstrict-prototypes
+DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=80
+### DEFS  = -DFREE_STANDING -DUSE_SYS3 -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
+OPT   = -O3 -Os -g
+LIBS  =
+
+####################
+include ../rules.mk
+
+board.h:
+	@echo Please make a symbolic link \'board.h\' to a file in ../board;
+	@exit 1
+
+sys.c: board.h
+
+distclean: clean
+	rm -f board.h

example-usart/board.h

@@ -0,0 +1 @@
+../board/board-st-nucleo-l432.h

example-usart/sample.c

@@ -0,0 +1,156 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+
+#include "board.h"
+#include "sys.h" /* for set_led */
+#include <contrib/usart.h>
+
+static chopstx_mutex_t mtx;
+static chopstx_cond_t cnd0;
+static chopstx_cond_t cnd1;
+
+static uint8_t u, v;
+static uint8_t m;		/* 0..100 */
+
+static void
+wait_for (uint32_t usec)
+{
+#if defined(BUSY_LOOP)
+  uint32_t count = usec * 6;
+  uint32_t i;
+
+  for (i = 0; i < count; i++)
+    asm volatile ("" : : "r" (i) : "memory");
+#else
+  chopstx_usec_wait (usec);
+#endif
+}
+
+static void *
+pwm (void *arg)
+{
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd0, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (1)
+    {
+      set_led (u&v);
+      wait_for (m);
+      set_led (0);
+      wait_for (100-m);
+    }
+
+  return NULL;
+}
+
+static void *
+blk (void *arg)
+{
+  (void)arg;
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_wait (&cnd1, &mtx);
+  chopstx_mutex_unlock (&mtx);
+
+  while (1)
+    {
+      v = 0;
+      wait_for (200*1000);
+      v = 1;
+      wait_for (200*1000);
+    }
+
+  return NULL;
+}
+
+#if defined(BUSY_LOOP)
+#define PRIO_PWM (CHOPSTX_SCHED_RR|1)
+#define PRIO_BLK (CHOPSTX_SCHED_RR|1)
+#else
+#define PRIO_PWM 3
+#define PRIO_BLK 2
+#endif
+
+#define STACK_MAIN
+#define STACK_PROCESS_1
+#define STACK_PROCESS_2
+#define STACK_PROCESS_3
+#include "stack-def.h"
+
+
+#define STACK_ADDR_PWM ((uint32_t)process1_base)
+#define STACK_SIZE_PWM (sizeof process1_base)
+
+#define STACK_ADDR_BLK ((uint32_t)process2_base)
+#define STACK_SIZE_BLK (sizeof process2_base)
+
+#define PRIO_USART     4
+#define STACK_ADDR_USART ((uint32_t)process3_base)
+#define STACK_SIZE_USART (sizeof process3_base)
+
+static int
+ss_notify (uint8_t dev_no, uint16_t state_bits)
+{
+  (void)dev_no;
+  (void)state_bits;
+  return 0;
+}
+
+int
+main (int argc, const char *argv[])
+{
+  chopstx_poll_cond_t poll_desc;
+  uint32_t timeout;
+  struct chx_poll_head *ph[1];
+
+  (void)argc;
+  (void)argv;
+
+  chopstx_mutex_init (&mtx);
+  chopstx_cond_init (&cnd0);
+  chopstx_cond_init (&cnd1);
+
+  m = 10;
+
+  chopstx_create (PRIO_PWM, STACK_ADDR_PWM, STACK_SIZE_PWM, pwm, NULL);
+  chopstx_create (PRIO_BLK, STACK_ADDR_BLK, STACK_SIZE_BLK, blk, NULL);
+
+  chopstx_usec_wait (200*1000);
+
+  chopstx_mutex_lock (&mtx);
+  chopstx_cond_signal (&cnd0);
+  chopstx_cond_signal (&cnd1);
+  chopstx_mutex_unlock (&mtx);
+
+  usart_init (PRIO_USART, STACK_ADDR_USART, STACK_SIZE_USART, ss_notify);
+  usart_config (2, B115200 | CS8 | STOP1B);
+
+  usart_read_prepare_poll (2, &poll_desc);
+  ph[0] = (struct chx_poll_head *)&poll_desc;
+
+  timeout = 200*1000*6;
+  while (1)
+    {
+      chopstx_poll (&timeout, 1, ph);
+      if (timeout == 0)
+	{
+	  usart_write (2, "Hello\r\n", 7);
+	  u ^= 1;
+	  timeout = 200*1000*6;
+	}
+      else
+	{
+	  char buf[256];
+	  int r;
+	  r = usart_read (2, buf, 256);
+	  if (r)
+	    usart_write (2, buf, r);
+	}
+    }
+
+  return 0;
+}

example-usart/sample.ld

@@ -0,0 +1,126 @@
+/*
+ * ST32F0 memory setup.
+ */
+MEMORY
+{
+    flash0 : org = 0x08000000, len = 4k
+    flash  : org = 0x08000000+0x1000, len = 60k
+    ram : org = 0x20000000, len = 20k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    .sys : ALIGN(4) SUBALIGN(4)
+    {
+	_sys = .;
+	KEEP(*(.vectors))
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+/*
+	*(.sys.0)
+	*(.sys.1)
+	*(.sys.2)
+*/
+    } > flash0 =0xffffffff
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN (16);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .vectors_in_ram :
+    {
+        . = ALIGN(8);
+        __vector_ram_addr__ = .;
+	KEEP(*(.bss.startup.*))
+    } > ram
+
+    .stacks (NOLOAD) :
+    {
+        . = ALIGN(8);
+        *(.main_stack)
+        *(.process_stack.0)
+        *(.process_stack.1)
+        *(.process_stack.2)
+        *(.process_stack.3)
+        . = ALIGN(8);
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;

example-usart/sample.ld.m3

@@ -0,0 +1,116 @@
+/*
+ * ST32F103 memory setup.
+ */
+MEMORY
+{
+    flash0 : org = 0x08000000, len = 4k
+    flash  : org = 0x08000000+0x1000, len = 60k
+    ram : org = 0x20000000, len = 20k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    .sys : ALIGN(4) SUBALIGN(4)
+    {
+	_sys = .;
+	KEEP(*(.vectors))
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+	*(.sys.0)
+	*(.sys.1)
+	*(.sys.2)
+    } > flash0
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN (16);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .stacks (NOLOAD) :
+    {
+        *(.main_stack)
+        *(.process_stack.0)
+        *(.process_stack.1)
+        *(.process_stack.2)
+        *(.process_stack.3)
+        . = ALIGN(8);
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;

example-usart/sample.ld.m4

@@ -0,0 +1,107 @@
+/*
+ * ST32L4 memory setup.
+ */
+MEMORY
+{
+    flash  : org = 0x08000000, len = 256k
+    ram : org = 0x20000000, len = 48k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN(16);
+	_sys = .;
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .stacks (NOLOAD) :
+    {
+        *(.main_stack)
+        *(.process_stack.0)
+        *(.process_stack.1)
+        *(.process_stack.2)
+        *(.process_stack.3)
+        . = ALIGN(8);
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;

example-usart/stack-def.h

@@ -0,0 +1,54 @@
+#define MAIN_SIZE 0x0080 /* Idle+Exception handlers  */
+#define SIZE_0 0x0300 /* Main program             */
+#define SIZE_1 0x0100 /* first thread program     */
+#define SIZE_2 0x0100 /* second thread program    */ 
+#define SIZE_3 0x0200 /* third thread program    */ 
+
+#if defined(STACK_MAIN)
+/*
+ * The terminology of "main" is confusing in ARM architecture.
+ * Here, "main_base" is for exception handlers.
+ */
+/* Idle+Exception handlers */
+char __main_stack_end__[0] __attribute__ ((section(".main_stack")));
+char main_base[MAIN_SIZE] __attribute__ ((section(".main_stack")));
+
+/* Main program            */
+char __process0_stack_end__[0] __attribute__ ((section(".process_stack.0")));
+char process0_base[SIZE_0] __attribute__ ((section(".process_stack.0")));
+#endif
+
+/* First thread program    */
+#if defined(STACK_PROCESS_1)
+char process1_base[SIZE_1] __attribute__ ((section(".process_stack.1"))); 
+#endif
+
+/* Second thread program   */
+#if defined(STACK_PROCESS_2)
+char process2_base[SIZE_2] __attribute__ ((section(".process_stack.2")));
+#endif
+
+/* Third thread program    */
+#if defined(STACK_PROCESS_3)
+char process3_base[SIZE_3] __attribute__ ((section(".process_stack.3")));
+#endif
+
+/* Fourth thread program    */
+#if defined(STACK_PROCESS_4)
+char process4_base[SIZE_4] __attribute__ ((section(".process_stack.4")));
+#endif
+
+/* Fifth thread program    */
+#if defined(STACK_PROCESS_5)
+char process5_base[SIZE_5] __attribute__ ((section(".process_stack.5")));
+#endif
+
+/* Sixth thread program    */
+#if defined(STACK_PROCESS_6)
+char process6_base[SIZE_6] __attribute__ ((section(".process_stack.6")));
+#endif
+
+/* Seventh thread program    */
+#if defined(STACK_PROCESS_7)
+char process7_base[SIZE_7] __attribute__ ((section(".process_stack.7")));
+#endif

example-usb-serial/Makefile

@@ -0,0 +1,37 @@
+# Makefile for example application of Chopstx
+
+PROJECT = sample
+
+CHOPSTX = ..
+LDSCRIPT= sample.ld
+CSRC = sample.c usb-cdc.c
+
+CHIP=stm32f103
+
+USE_SYS = yes
+USE_USB = yes
+USE_USART = yes
+
+###################################
+CROSS = arm-none-eabi-
+CC   = $(CROSS)gcc
+LD   = $(CROSS)gcc
+OBJCOPY   = $(CROSS)objcopy
+
+MCU   = cortex-m3
+CWARN = -Wall -Wextra -Wstrict-prototypes
+DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=72
+OPT   = -O3 -Os -g
+LIBS  =
+
+####################
+include ../rules.mk
+
+board.h:
+	@echo Please make a symbolic link \'board.h\' to a file in ../board;
+	@exit 1
+
+sys.c: board.h
+
+distclean: clean
+	rm -f board.h

example-usb-serial/README

@@ -0,0 +1,29 @@
+This is an application example using ST Nucleo F103 board.
+
+SB62 and SB63 should be soldered to connect PA2 and PA3 to CN10
+connector.
+
+ST-Link/V2's TX and RX are disconnected (by removing SB13 and SB14).
+
+Smartcard can be connected, by using USART3_TX for I/O and USART3_CK
+for CLK, PB6 for Vcc, PB8 for Vpp, and PB9 for RST.
+
+
+NOTE:
+
+Using the USB CDC-ACM for serial communication is a kind of wrong,
+because it's designed for modem; In the protocol, we have no way to
+control the CTSRTS signal.
+
+TIOCGICOUNT
+
+
+TODO:
+* Use of DMA for serial communication
+* RS-232 support: GPIO with DTR (out), DCD (in), DSR (in), RI (in)
+* serial config setting of CTSRTS?
+  By vendor specific control?
+* stats report control
+  By vendor specific control?
+* Half-duplex support
+* Support of other communication mode: IrDA, etc.

example-usb-serial/board.h

@@ -0,0 +1 @@
+../board/board-st-nucleo-f103.h

example-usb-serial/cdc.h

@@ -0,0 +1,17 @@
+#define BUFSIZE 64
+
+struct cdc;
+
+void
+cdc_init (uint16_t prio, uintptr_t stack_addr, size_t stack_size,
+	  void (*sendbrk_callback) (uint8_t dev_no, uint16_t duration),
+	  void (*config_callback) (uint8_t dev_no,
+				   uint32_t bitrate, uint8_t format,
+				   uint8_t paritytype, uint8_t databits));
+void cdc_wait_configured (void);
+
+struct cdc *cdc_open (uint8_t num);
+void cdc_wait_connection (struct cdc *);
+int cdc_send (struct cdc *s, const char *buf, int count);
+int cdc_recv (struct cdc *s, char *buf, uint32_t *timeout);
+int cdc_ss_notify (struct cdc *s, uint16_t state_bits);

example-usb-serial/sample.c

@@ -0,0 +1,260 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <chopstx.h>
+#include <contrib/usart.h>
+
+#include <usb_lld.h>
+#include "cdc.h"
+
+/* For set_led */
+#include "board.h"
+#include "sys.h"
+
+static void *
+blk (void *arg)
+{
+  (void)arg;
+
+  while (1)
+    {
+      set_led (0);
+      chopstx_usec_wait (200*1000);
+      set_led (1);
+      chopstx_usec_wait (200*1000);
+    }
+
+  return NULL;
+}
+
+#define PRIO_USART     4
+#define PRIO_CDC2USART 3
+#define PRIO_USART2CDC 3
+#define PRIO_CDC       2
+
+#define STACK_MAIN
+#define STACK_PROCESS_1
+#define STACK_PROCESS_2
+#define STACK_PROCESS_3
+#define STACK_PROCESS_4
+#define STACK_PROCESS_5
+#define STACK_PROCESS_6
+#include "stack-def.h"
+#define STACK_ADDR_CDC ((uintptr_t)process1_base)
+#define STACK_SIZE_CDC (sizeof process1_base)
+
+#define STACK_ADDR_USART ((uint32_t)process2_base)
+#define STACK_SIZE_USART (sizeof process2_base)
+
+#define STACK_ADDR_CDC2USART0 ((uint32_t)process3_base)
+#define STACK_SIZE_CDC2USART0 (sizeof process3_base)
+
+#define STACK_ADDR_USART2CDC0 ((uint32_t)process4_base)
+#define STACK_SIZE_USART2CDC0 (sizeof process4_base)
+
+#define STACK_ADDR_CDC2USART1 ((uint32_t)process5_base)
+#define STACK_SIZE_CDC2USART1 (sizeof process5_base)
+
+#define STACK_ADDR_USART2CDC1 ((uint32_t)process6_base)
+#define STACK_SIZE_USART2CDC1 (sizeof process6_base)
+
+
+struct cdc_usart {
+  uint8_t dev_no;
+  struct cdc *cdc;
+};
+
+static void *
+usart_to_cdc_loop (void *arg)
+{
+  struct cdc_usart *cdc_usart = arg;
+
+  while (1)
+    {
+      char s[BUFSIZE];
+
+      cdc_wait_connection (cdc_usart->cdc);
+
+      /* Flush USART buffers */
+      usart_read (cdc_usart->dev_no, NULL, 0);
+      usart_write (cdc_usart->dev_no, NULL, 0);
+
+      chopstx_usec_wait (100*1000);
+
+      while (1)
+	{
+	  int size = usart_read (cdc_usart->dev_no, s, BUFSIZE);
+
+	  if (size > 0)
+	    {
+	      if (cdc_send (cdc_usart->cdc, s, size) < 0)
+		break;
+	    }
+	}
+    }
+
+  return NULL;
+}
+
+static void *
+cdc_to_usart_loop (void *arg)
+{
+  struct cdc_usart *cdc_usart = arg;
+
+  while (1)
+    {
+      char s[BUFSIZE];
+
+      cdc_wait_connection (cdc_usart->cdc);
+
+      /* Flush USART buffers */
+      usart_read (cdc_usart->dev_no, NULL, 0);
+      usart_write (cdc_usart->dev_no, NULL, 0);
+
+      chopstx_usec_wait (50*1000);
+
+      /* Send ZLP at the beginning.  */
+      cdc_send (cdc_usart->cdc, s, 0);
+
+      while (1)
+	{
+	  int size;
+	  uint32_t usec = 3000000;	/* 3.0 seconds */
+
+	  size = cdc_recv (cdc_usart->cdc, s, &usec);
+	  if (size < 0)
+	    break;
+
+	  if (size)
+	    usart_write (cdc_usart->dev_no, s, size);
+	}
+    }
+
+  return NULL;
+}
+
+static struct cdc_usart cdc_usart0;
+static struct cdc_usart cdc_usart1;
+
+static int
+ss_notify (uint8_t dev_no, uint16_t state_bits)
+{
+  struct cdc *s;
+
+  if (dev_no == cdc_usart0.dev_no)
+    s = cdc_usart0.cdc;
+  else if (dev_no == cdc_usart1.dev_no)
+    s = cdc_usart1.cdc;
+  else
+    return -1;
+
+  return cdc_ss_notify (s, state_bits);
+}
+
+static void
+send_break (uint8_t dev_no, uint16_t duration)
+{
+  (void)duration; 		/* Not supported by USART.  */
+  usart_send_break (dev_no);
+}
+
+static void
+setup_usart_config (uint8_t dev_no, uint32_t bitrate, uint8_t format,
+		    uint8_t paritytype, uint8_t databits)
+{
+  /* Check supported config(s) */
+  uint32_t config_bits;
+
+  if (bitrate == 9600)
+    config_bits = B9600;
+  else if (bitrate == 19200)
+    config_bits = B19200;
+  else if (bitrate == 57600)
+    config_bits = B57600;
+  else if (bitrate == 115200)
+    config_bits = B115200;
+  else
+    {
+      bitrate = 115200;
+      config_bits = B115200;
+    }
+
+  if (format == 0)
+    config_bits |= STOP1B;
+  else if (format == 1)
+    config_bits |= STOP1B5;
+  else if (format == 2)
+    config_bits |= STOP2B;
+  else
+    {
+      format = 0;
+      config_bits |= STOP1B;
+    }
+
+  if (paritytype == 0)
+    config_bits |= 0;
+  else if (paritytype == 1)
+    config_bits |= (PARENB | PARODD);
+  else if (paritytype == 2)
+    config_bits |= PARENB;
+  else
+    {
+      paritytype = 0;
+      config_bits |= 0;
+    }
+
+  if (databits == 7)
+    config_bits |= CS7;
+  else if (databits == 7)
+    config_bits |= CS8;
+  else
+    {
+      databits = 8;
+      config_bits |= CS8;
+    }
+
+  if (databits == 7 && paritytype == 0)
+    {
+      databits = 8;
+      config_bits &= ~MASK_CS;
+      config_bits |= CS8;
+    }
+
+  usart_config (dev_no, config_bits);
+}
+
+
+int
+main (int argc, const char *argv[])
+{
+  (void)argc;
+  (void)argv;
+
+  chopstx_usec_wait (200*1000);
+
+  cdc_init (PRIO_CDC, STACK_ADDR_CDC, STACK_SIZE_CDC,
+	    send_break, setup_usart_config);
+  cdc_wait_configured ();
+
+  usart_init (PRIO_USART, STACK_ADDR_USART, STACK_SIZE_USART, ss_notify);
+
+  usart_config (2, B115200 | CS8 | STOP1B);
+  usart_config (3, B115200 | CS8 | STOP1B);
+
+  cdc_usart0.cdc = cdc_open (0);
+  cdc_usart0.dev_no = 2;
+  cdc_usart1.cdc = cdc_open (1);
+  cdc_usart1.dev_no = 3;
+
+  chopstx_create (PRIO_USART2CDC, STACK_ADDR_USART2CDC0,
+		  STACK_SIZE_USART2CDC0, usart_to_cdc_loop, &cdc_usart0);
+  chopstx_create (PRIO_USART2CDC, STACK_ADDR_USART2CDC1,
+		  STACK_SIZE_USART2CDC1, usart_to_cdc_loop, &cdc_usart1);
+  chopstx_create (PRIO_CDC2USART, STACK_ADDR_CDC2USART0,
+		  STACK_SIZE_CDC2USART0, cdc_to_usart_loop, &cdc_usart0);
+  chopstx_create (PRIO_CDC2USART, STACK_ADDR_CDC2USART1,
+		  STACK_SIZE_CDC2USART1, cdc_to_usart_loop, &cdc_usart1);
+
+  blk (NULL);
+  return 0;
+}

example-usb-serial/sample.ld

@@ -0,0 +1,127 @@
+/*
+ * ST32F103 memory setup.
+ */
+
+MEMORY
+{
+    flash0 : org = 0x08000000, len = 4k
+    flash  : org = 0x08000000+0x1000, len = 60k
+    ram : org = 0x20000000, len = 20k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    .sys : ALIGN(4) SUBALIGN(4)
+    {
+	_sys = .;
+	KEEP(*(.vectors))
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+	*(.sys.0)
+	*(.sys.1)
+	*(.sys.2)
+    } > flash0
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN (16);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .process_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        *(.process_stack.6)
+        *(.process_stack.5)
+        *(.process_stack.4)
+        *(.process_stack.3)
+        *(.process_stack.2)
+        *(.process_stack.1)
+        *(.process_stack.0)
+        . = ALIGN(8);
+    } > ram
+
+    .main_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        *(.main_stack)
+        . = ALIGN(8);
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;

example-usb-serial/stack-def.h

@@ -0,0 +1,39 @@
+#if defined(STACK_MAIN)
+/* Idle+Exception handlers */
+char __main_stack_end__[0] __attribute__ ((section(".main_stack")));
+char main_base[0x0080] __attribute__ ((section(".main_stack")));
+
+/* Main program            */
+char __process0_stack_end__[0] __attribute__ ((section(".process_stack.0")));
+char process0_base[0x0400] __attribute__ ((section(".process_stack.0")));
+#endif
+
+/* First thread program    */
+#if defined(STACK_PROCESS_1)
+char process1_base[0x0200] __attribute__ ((section(".process_stack.1"))); 
+#endif
+
+/* Second thread program   */
+#if defined(STACK_PROCESS_2)
+char process2_base[0x0200] __attribute__ ((section(".process_stack.2")));
+#endif
+
+/* Third thread program    */
+#if defined(STACK_PROCESS_3)
+char process3_base[0x0200] __attribute__ ((section(".process_stack.3")));
+#endif
+
+/* Fourth thread program    */
+#if defined(STACK_PROCESS_4)
+char process4_base[0x0200] __attribute__ ((section(".process_stack.4")));
+#endif
+
+/* Fifth thread program    */
+#if defined(STACK_PROCESS_5)
+char process5_base[0x0200] __attribute__ ((section(".process_stack.5")));
+#endif
+
+/* Sixth thread program    */
+#if defined(STACK_PROCESS_6)
+char process6_base[0x0200] __attribute__ ((section(".process_stack.6")));
+#endif

mcu/ABOUT-SYS

@@ -1,8 +1,7 @@
 Consideration about SYS and the first pages of flash ROM
 ========================================================
 
-Now, I'm developing something like SYS for Kinetis L MCU, so, I write
+This document was written when I was porting Chopstx to Kinetis L.
-this document.
 
 * Compatibility
 
@@ -10,7 +9,8 @@ this document.
   SYS 2.0: Added clock_init, gpio_init 
   SYS 2.1: Added sys_board_id, sys_board_name 
   SYS 3.0: Don't setup NVIC priority by usb_lld_sys_init
-
+  SYS 4.0: For USB, only do usb_cable_config.  Enabling/disabling the
+           USB module is the role of USB driver.
 
 * Macro definition by DEFS in Makefile
 
@@ -131,23 +131,24 @@ and here is the list of all.
 
     nvic_system_reset
 
-The routines of clock_init and gpio_init are here because of some
+The routines of clock_init and gpio_init exist in SYS, because of some
-historical reasons.  (We could design a system with no such exported
+historical reasons; Without such exported routines, we could design a
-routines: by defining: those things done internally after reset and
+system having an assumption: important clock and gpio initialization
-before calling the application.)
+is done internally after reset, so that an application can just work.
 
 Those are exported as entries of SYS, and it is the responsibility of
 the application which do initialize clock and GPIO, calling those
 routines.
 
-USB routines are needed because of hardware practice of STM32F103.
+USB routines are needed because of hardware practice of STM32F103. (It
-With STM32F103, each board has different way for handling the pull up
+can support low speed device.  It can support self powered USB
-of USB D+ and how the device asks re-enumeration to host PC.  In my
+system.)  With STM32F103 (for allowing low speed device and self
-opinion, if it's defined as full speed device and it's OK for us not
+powered system), each board has different way for handling the pull up
-to use high impedance (but asserting to LOW, instead) of D+ to ask
+of USB D+ and how the device asks re-enumeration to host PC.
-re-enumeration, we can just pull up D+ always.  And we wouldn't need
-such routines in SYS.
 
+For bus-powered system and full speed device, we can just pull up D+
+always.  Still, support of high impedance state of D+ line would be
+ideal when asking re-enumeration, asserting to LOW works.
 
 
 About SYS on Kinetis L

mcu/ABOUT-USB

@@ -0,0 +1,32 @@
+USB driver in Chopstx
+
+Full speed device is assumed.  Bus powered system is assumed.
+API-wise, self powered system is not supported (yet) by this USB driver.
+
+The driver can be used without Chopstx.  An example can be find in
+Gnuk (gnuk/regnual).
+
+The USB driver was originally written for STM32F103, which USB
+hardware design is considered not mature.  Modern USB hardware design
+allows crystal-less design, and/or comes with internal 5V->3V3
+regulator, D+-line pull-up support, and VBUS detection.  STM32F103 has
+nothing.
+
+To support self powered system, we need to define a hardware interface
+for a board detecting VBUS voltage.  Only after detecting VBUS power,
+we can enable USB driver (D+/D- lines).  For self powered system,
+driving D+/D- lines by fixed pull-up resistor violates the USB
+specification.
+
+With STM32F103, there is a common hardware practice having a
+gate/transistor for pull-up D+ line.  If it also supports detecting
+VBUS, self powerd system can be supported with the gate/transistor.
+
+Such a gate/transistor can be also used for the board to ask
+re-enumeration of USB device.  Asking re-enumeration, it is enough to
+have SE0 (Single-Ended Zero) state.  
+
+The USB driver doesn't touch such a gate/transistor.  By gpio_init,
+the D+-line should be asserted, USB D+ and D- lines should be drived
+to 0 (SE0).  When the USB module is enabled, it goes into J and K
+state (from SE0 state).

mcu/chx-gnu-linux.c

@@ -0,0 +1,5 @@
+void
+chx_sleep_mode (int enable_sleep)
+{
+  (void)enable_sleep;
+}

mcu/chx-mkl27z.c

@@ -0,0 +1,23 @@
+extern int chx_allow_sleep;
+
+void
+chx_sleep_mode (int enable_sleep)
+{
+  (void)enable_sleep;
+}
+
+void __attribute__((naked))
+chx_idle (void)
+{
+  int sleep_enabled;
+
+  for (;;)
+    {
+      asm ("ldr	%0, %1" : "=r" (sleep_enabled): "m" (chx_allow_sleep));
+      if (sleep_enabled)
+	{
+	  asm volatile ("wfi" : : : "memory");
+	  /* NOTE: it never comes here.  Don't add lines after this.  */
+	}
+    }
+}

mcu/chx-stm32f0.c

@@ -0,0 +1,42 @@
+#include <stdint.h>
+#include <mcu/cortex-m.h>
+#define MCU_STM32F0
+#include <mcu/stm32.h>
+
+extern int chx_allow_sleep;
+
+void
+chx_sleep_mode (int how)
+{
+  PWR->CR |= PWR_CR_CWUF;
+  PWR->CR &= ~(PWR_CR_PDDS|PWR_CR_LPDS);
+
+  if (how == 0 || how == 1 /* Sleep only (not deepsleep) */)
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP;
+  else
+    {			   /* Deepsleep */
+      /* how == 2: deepsleep but regulator ON */
+      if (how == 3)
+	PWR->CR |= PWR_CR_LPDS;	/* regulator low-power mode */
+      else if (how == 4)
+	PWR->CR |= PWR_CR_PDDS;	/* Power down: All OFF     */
+
+      SCB->SCR |= SCB_SCR_SLEEPDEEP;
+    }
+}
+
+void __attribute__((naked))
+chx_idle (void)
+{
+  int sleep_enabled;
+
+  for (;;)
+    {
+      asm ("ldr	%0, %1" : "=r" (sleep_enabled): "m" (chx_allow_sleep));
+      if (sleep_enabled)
+	{
+	  asm volatile ("wfi" : : : "memory");
+	  /* NOTE: it never comes here.  Don't add lines after this.  */
+	}
+    }
+}

mcu/chx-stm32f103.c

@@ -0,0 +1,92 @@
+#include <stdint.h>
+#include <mcu/stm32f103.h>
+#include "board.h"
+
+extern int chx_allow_sleep;
+
+#define STM32_PLLSRC		STM32_PLLSRC_HSE
+#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
+#ifndef STM32_ADCPRE
+#define STM32_ADCPRE		STM32_ADCPRE_DIV6
+#endif
+#ifndef STM32_USBPRE
+#define STM32_USBPRE		STM32_USBPRE_DIV1P5
+#endif
+
+static void
+configure_clock (int high)
+{
+  uint32_t cfg_sw;
+  uint32_t cfg;
+
+  if (high)
+    {
+      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE
+	| STM32_PLLMUL | STM32_PLLXTPRE	| STM32_PLLSRC
+	| STM32_ADCPRE | STM32_PPRE2_DIV1
+	| STM32_PPRE1_DIV2 | STM32_HPRE_DIV1;
+
+      cfg_sw = RCC_CFGR_SW_PLL;
+    }
+  else
+    {
+      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE
+	| STM32_PLLMUL | STM32_PLLXTPRE	| STM32_PLLSRC
+	| STM32_ADCPRE_DIV8 | STM32_PPRE2_DIV16
+	| STM32_PPRE1_DIV16 | STM32_HPRE_DIV8;
+
+      cfg_sw = RCC_CFGR_SW_HSI;
+    }
+
+  RCC->CFGR = cfg | cfg_sw;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (cfg_sw << 2))
+    ;
+}
+
+/*
+ * When HOW=0 or HOW=1, SYSCLK is PLL (72MHz).
+ * When HOW=2, SYSCLK will be 1MHz with HSI (8MHz) on sleep.
+ *
+ * With lower clock, it can achieve lower power consumption.
+ *
+ * Implementation note: Deepsleep is only useful with RTC, Watch Dog,
+ * or WKUP pin.  We can't use deepsleep for USB, it never wakes up.
+ *
+ */
+void
+chx_sleep_mode (int how)
+{
+  if (how == 0 || how == 1)
+    configure_clock (1);
+
+  /* how == 2: Defer setting to 8MHz clock to the idle function */
+}
+
+void __attribute__((naked))
+chx_idle (void)
+{
+  int sleep_enabled;
+
+  for (;;)
+    {
+      asm ("ldr	%0, %1" : "=r" (sleep_enabled): "m" (chx_allow_sleep));
+      if (sleep_enabled)
+	{
+	  asm volatile ("cpsid	i" : : : "memory");
+	  if (sleep_enabled == 1)
+	    {
+	      /* Allow JTAG/SWD access on sleep.  */
+	      DBGMCU->CR |= DBG_SLEEP;
+	    }
+	  else if (sleep_enabled == 2)
+	    {
+	      DBGMCU->CR &= ~DBG_SLEEP; /* Disable HCLK on sleep */
+	      configure_clock (0);
+	    }
+	  asm volatile ("cpsie	i" : : : "memory");
+
+	  asm volatile ("wfi" : : : "memory");
+	  /* NOTE: it never comes here.  Don't add lines after this.  */
+	}
+    }
+}

mcu/chx-stm32l4.c

@@ -0,0 +1,29 @@
+#include <stdint.h>
+#include <mcu/cortex-m.h>
+#include <mcu/stm32l.h>
+
+extern int chx_allow_sleep;
+
+void
+chx_sleep_mode (int how)
+{
+  /*TBD*/
+  (void)how;
+}
+
+void __attribute__((naked))
+chx_idle (void)
+{
+  /*TBD*/
+  int sleep_enabled;
+
+  for (;;)
+    {
+      asm ("ldr	%0, %1" : "=r" (sleep_enabled): "m" (chx_allow_sleep));
+      if (sleep_enabled)
+	{
+	  asm volatile ("wfi" : : : "memory");
+	  /* NOTE: it never comes here.  Don't add lines after this.  */
+	}
+    }
+}

mcu/clk_gpio_init-mkl27z.c

@@ -22,7 +22,7 @@
  * As additional permission under GNU GPL version 3 section 7, you may
  * distribute non-source form of the Program without the copy of the
  * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
+ * recipients of GNU GPL by a written offer.
  *
  */
 

mcu/clk_gpio_init-stm32.c

@@ -1,368 +0,0 @@
-/*
- * clk_gpio_init-stm32.c - Clock and GPIO initialization for STM32.
- *
- * Copyright (C) 2015  Flying Stone Technology
- * Author: NIIBE Yutaka <gniibe@fsij.org>
- *
- * This file is a part of Chopstx, a thread library for embedded.
- *
- * Chopstx is free software: you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * Chopstx is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- * As additional permission under GNU GPL version 3 section 7, you may
- * distribute non-source form of the Program without the copy of the
- * GNU GPL normally required by section 4, provided you inform the
- * receipents of GNU GPL by a written offer.
- *
- */
-
-#define STM32_SW_HSI		(0 << 0)
-#define STM32_SW_PLL		(2 << 0)
-#define STM32_PLLSRC_HSI	(0 << 16)
-#define STM32_PLLSRC_HSE	(1 << 16)
-
-#define STM32_PLLXTPRE_DIV1	(0 << 17)
-#define STM32_PLLXTPRE_DIV2	(1 << 17)
-
-#define STM32_HPRE_DIV1		(0 << 4)
-
-#define STM32_PPRE1_DIV1	(0 << 8)
-#define STM32_PPRE1_DIV2	(4 << 8)
-
-#define STM32_PPRE2_DIV1        (0 << 11)
-#define STM32_PPRE2_DIV2	(4 << 11)
-
-#define STM32_ADCPRE_DIV4	(1 << 14)
-#define STM32_ADCPRE_DIV6       (2 << 14)
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)
-
-#define STM32_MCO_NOCLOCK	(0 << 24)
-
-#if defined(MCU_STM32F0)
-#define STM32_PPRE1		STM32_PPRE1_DIV1
-#define STM32_PLLSRC		STM32_PLLSRC_HSI
-#define STM32_FLASHBITS		0x00000011
-#define STM32_PLLCLKIN		(STM32_HSICLK / 2)
-#else
-#define STM32_PPRE1		STM32_PPRE1_DIV2
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_FLASHBITS		0x00000012
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
-#endif
-
-#define STM32_SW		STM32_SW_PLL
-#define STM32_HPRE		STM32_HPRE_DIV1
-#define STM32_PPRE2		STM32_PPRE2_DIV1
-#define STM32_ADCPRE		STM32_ADCPRE_DIV6
-#define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
-
-#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK		STM32_PLLCLKOUT
-#define STM32_HCLK		(STM32_SYSCLK / 1)
-
-
-#define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-#if defined(MCU_STM32F0)
-  volatile uint32_t AHBRSTR;
-  volatile uint32_t CFGR2;
-  volatile uint32_t CFGR3;
-  volatile uint32_t CR2;
-#endif
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = (struct RCC *)RCC_BASE;
-
-#define RCC_APB1ENR_USBEN	0x00800000
-#define RCC_APB1RSTR_USBRST	0x00800000
-
-#define RCC_CR_HSION		0x00000001
-#define RCC_CR_HSIRDY		0x00000002
-#define RCC_CR_HSITRIM		0x000000F8
-#define RCC_CR_HSEON		0x00010000
-#define RCC_CR_HSERDY		0x00020000
-#define RCC_CR_PLLON		0x01000000
-#define RCC_CR_PLLRDY		0x02000000
-
-#define RCC_CFGR_SWS		0x0000000C
-#define RCC_CFGR_SWS_HSI	0x00000000
-
-#define RCC_AHBENR_CRCEN        0x0040
-
-#if defined(MCU_STM32F0)
-#define RCC_AHBRSTR_IOPARST	0x00020000
-#define RCC_AHBRSTR_IOPBRST	0x00040000
-#define RCC_AHBRSTR_IOPCRST	0x00080000
-#define RCC_AHBRSTR_IOPDRST	0x00100000
-#define RCC_AHBRSTR_IOPFRST	0x00400000
-
-#define RCC_AHBENR_IOPAEN	0x00020000
-#define RCC_AHBENR_IOPBEN	0x00040000
-#define RCC_AHBENR_IOPCEN	0x00080000
-#define RCC_AHBENR_IOPDEN	0x00100000
-#define RCC_AHBENR_IOPFEN	0x00400000
-
-#define RCC_APB2RSTR_SYSCFGRST	0x00000001
-#define RCC_APB2ENR_SYSCFGEN	0x00000001
-#else
-#define RCC_APB2RSTR_AFIORST	0x00000001
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-#define RCC_APB2RSTR_IOPERST	0x00000040
-#define RCC_APB2RSTR_IOPFRST	0x00000080
-#define RCC_APB2RSTR_IOPGRST	0x00000100
-
-#define RCC_APB2ENR_AFIOEN	0x00000001
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-#define RCC_APB2ENR_IOPEEN	0x00000040
-#define RCC_APB2ENR_IOPFEN	0x00000080
-#define RCC_APB2ENR_IOPGEN	0x00000100
-#endif
-
-#if defined(MCU_STM32F0)
-struct SYSCFG {
-  volatile uint32_t CFGR1;
-  uint32_t dummy0;
-  volatile uint32_t EXTICR[4];
-  volatile uint32_t CFGR2;
-};
-#define SYSCFG_CFGR1_MEM_MODE 0x03
-
-#define SYSCFG_BASE	(APBPERIPH_BASE + 0x00010000)
-static struct SYSCFG *const SYSCFG = (struct SYSCFG *)SYSCFG_BASE;
-#endif
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;
-
-static void __attribute__((used))
-clock_init (void)
-{
-  /* HSI setup */
-  RCC->CR |= RCC_CR_HSION;
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;
-  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
-  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
-  RCC->CFGR = 0;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;
-
-#if !defined(MCU_STM32F0)
-  /* HSE setup */
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;
-#endif
-
-  /* PLL setup */
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-
-  /* Clock settings */
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
-    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /*
-   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
-   */
-
-  /* Flash setup */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* CRC */
-  RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
-  /* Switching on the configured clock source. */
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-
-#if defined(MCU_STM32F0)
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-  RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
-  RCC->APB2RSTR = 0;
-
-# if defined(STM32F0_USE_VECTOR_ON_RAM)
-  /* Use vectors on RAM */
-  SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
-# endif
-#endif
-}
-
-
-#if defined(MCU_STM32F0)
-struct GPIO {
-  volatile uint32_t MODER;
-  volatile uint16_t OTYPER;
-  uint16_t dummy0;
-  volatile uint32_t OSPEEDR;
-  volatile uint32_t PUPDR;
-  volatile uint16_t IDR;
-  uint16_t dummy1;
-  volatile uint16_t ODR;
-  uint16_t dummy2;
-  volatile uint16_t BSRR;
-  uint16_t dummy3;
-  volatile uint32_t LCKR;
-  volatile uint32_t AFR[2];
-  volatile uint16_t BRR;
-  uint16_t dummy4;
-};
-
-#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
-#define GPIOF		((struct GPIO *) GPIOF_BASE)
-#else
-struct AFIO
-{
-  volatile uint32_t EVCR;
-  volatile uint32_t MAPR;
-  volatile uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  volatile uint32_t MAPR2;
-};
-
-#define AFIO_BASE 0x40010000
-static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE;
-
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
-#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE     0x02000000
-
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-#endif
-
-static struct GPIO *const GPIO_LED = (struct GPIO *)GPIO_LED_BASE;
-#ifdef GPIO_USB_BASE
-static struct GPIO *const GPIO_USB = (struct GPIO *)GPIO_USB_BASE;
-#endif
-#ifdef GPIO_OTHER_BASE
-static struct GPIO *const GPIO_OTHER = (struct GPIO *)GPIO_OTHER_BASE;
-#endif
-
-static void __attribute__((used))
-gpio_init (void)
-{
-  /* Enable GPIO clock. */
-#if defined(MCU_STM32F0)
-  RCC->AHBENR |= RCC_ENR_IOP_EN;
-  RCC->AHBRSTR = RCC_RSTR_IOP_RST;
-  RCC->AHBRSTR = 0;
-#else
-  RCC->APB2ENR |= RCC_ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
-  RCC->APB2RSTR = 0;
-#endif
-
-#if defined(MCU_STM32F0)
-  GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
-  GPIO_LED->OTYPER  = VAL_GPIO_LED_OTYPER;
-  GPIO_LED->MODER   = VAL_GPIO_LED_MODER;
-  GPIO_LED->PUPDR   = VAL_GPIO_LED_PUPDR;
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
-  GPIO_OTHER->OTYPER  = VAL_GPIO_OTHER_OTYPER;
-  GPIO_OTHER->MODER   = VAL_GPIO_OTHER_MODER;
-  GPIO_OTHER->PUPDR   = VAL_GPIO_OTHER_PUPDR;
-#endif
-#else
-#ifdef AFIO_MAPR_SOMETHING
-  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
-#endif
-
-  /* LED is mandatory.  If it's on an independent port, we configure it.  */
-  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
-  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
-  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-
-  /* If there is USB enabler pin and it's independent, we configure it.  */
-#if defined(GPIO_USB_BASE) && GPIO_USB_BASE != GPIO_LED_BASE
-  GPIO_USB->ODR = VAL_GPIO_USB_ODR;
-  GPIO_USB->CRH = VAL_GPIO_USB_CRH;
-  GPIO_USB->CRL = VAL_GPIO_USB_CRL;
-#endif
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
-  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
-  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
-#endif
-#endif
-}

mcu/clk_gpio_init-stm32f.c

@@ -0,0 +1,176 @@
+/*
+ * clk_gpio_init-stm32.c - Clock and GPIO initialization for STM32.
+ *
+ * Copyright (C) 2015, 2018  Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * recipients of GNU GPL by a written offer.
+ *
+ */
+
+#if defined(MCU_STM32F0)
+#include <mcu/stm32.h>
+#else
+#include <mcu/stm32f103.h>
+#endif
+
+#if defined(MCU_STM32F0)
+#define STM32_PPRE1		STM32_PPRE1_DIV1
+#define STM32_PLLSRC		STM32_PLLSRC_HSI
+#define STM32_FLASHBITS		0x00000011
+#define STM32_PLLCLKIN		(STM32_HSICLK / 2)
+#else
+#define STM32_PPRE1		STM32_PPRE1_DIV2
+#define STM32_PLLSRC		STM32_PLLSRC_HSE
+#define STM32_FLASHBITS		0x00000012
+#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
+#endif
+
+#define STM32_SW		STM32_SW_PLL
+#define STM32_HPRE		STM32_HPRE_DIV1
+#define STM32_PPRE2		STM32_PPRE2_DIV1
+#ifndef STM32_ADCPRE
+#define STM32_ADCPRE		STM32_ADCPRE_DIV6
+#endif
+#define STM32_MCOSEL		STM32_MCO_NOCLOCK
+#ifndef STM32_USBPRE
+#define STM32_USBPRE		STM32_USBPRE_DIV1P5
+#endif
+
+#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
+#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+#define STM32_SYSCLK		STM32_PLLCLKOUT
+#define STM32_HCLK		(STM32_SYSCLK / 1)
+
+
+static void __attribute__((used))
+clock_init (void)
+{
+  /* HSI setup */
+  RCC->CR |= RCC_CR_HSION;
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;
+  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
+  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
+  RCC->CFGR = 0;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;
+
+#if !defined(MCU_STM32F0)
+  /* HSE setup */
+  RCC->CR |= RCC_CR_HSEON;
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;
+#endif
+
+  /* PLL setup */
+  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;
+
+  /* Clock settings */
+  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
+    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+  /*
+   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
+   */
+
+  /* Flash setup */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* Switching on the configured clock source. */
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;
+
+#if defined(MCU_STM32F0)
+  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+  RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
+  RCC->APB2RSTR = 0;
+
+# if defined(STM32F0_USE_VECTOR_ON_RAM)
+  /* Use vectors on RAM */
+  SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
+# endif
+#endif
+}
+
+
+static struct GPIO *const GPIO_LED = (struct GPIO *)GPIO_LED_BASE;
+#ifdef GPIO_USB_BASE
+static struct GPIO *const GPIO_USB = (struct GPIO *)GPIO_USB_BASE;
+#endif
+#ifdef GPIO_OTHER_BASE
+static struct GPIO *const GPIO_OTHER = (struct GPIO *)GPIO_OTHER_BASE;
+#endif
+
+static void __attribute__((used))
+gpio_init (void)
+{
+  /* Enable GPIO clock. */
+#if defined(MCU_STM32F0)
+  RCC->AHBENR |= RCC_ENR_IOP_EN;
+  RCC->AHBRSTR = RCC_RSTR_IOP_RST;
+  RCC->AHBRSTR = 0;
+#else
+  RCC->APB2ENR |= RCC_ENR_IOP_EN;
+  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
+  RCC->APB2RSTR = 0;
+#endif
+
+#if defined(MCU_STM32F0)
+  GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
+  GPIO_LED->OTYPER  = VAL_GPIO_LED_OTYPER;
+  GPIO_LED->MODER   = VAL_GPIO_LED_MODER;
+  GPIO_LED->PUPDR   = VAL_GPIO_LED_PUPDR;
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
+  GPIO_OTHER->OTYPER  = VAL_GPIO_OTHER_OTYPER;
+  GPIO_OTHER->MODER   = VAL_GPIO_OTHER_MODER;
+  GPIO_OTHER->PUPDR   = VAL_GPIO_OTHER_PUPDR;
+#endif
+#else
+#ifdef AFIO_MAPR_SOMETHING
+  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
+#endif
+
+  /* LED is mandatory.  We configure it always.  */
+  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
+  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
+  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
+
+  /* If there is USB enabler pin and it's independent, we configure it.  */
+#if defined(GPIO_USB_BASE) && GPIO_USB_BASE != GPIO_LED_BASE
+  GPIO_USB->ODR = VAL_GPIO_USB_ODR;
+  GPIO_USB->CRH = VAL_GPIO_USB_CRH;
+  GPIO_USB->CRL = VAL_GPIO_USB_CRL;
+#endif
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
+  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
+  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
+#endif
+#endif
+}

mcu/clk_gpio_init-stm32l.c

@@ -0,0 +1,115 @@
+/*
+ * clk_gpio_init-stm32l.c - Clock and GPIO initialization for STM32L.
+ *
+ * Copyright (C) 2019  Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * recipients of GNU GPL by a written offer.
+ *
+ */
+
+#include <mcu/stm32l.h>
+
+#define STM32_FLASHBITS		0x00000704
+
+void
+clock_init (void)
+{
+  /* MSI: 4MHz (keep the default value) */
+
+  /* PLL input: MSI at 4MHz, VCO: 160 MHz, output 80MHz */
+  RCC->PLLCFGR = ((1 << 24) | (40 << 8)) | 0x01;
+
+  /* Enable PLL */
+  RCC->CR |= (1 << 24);
+  while (!(RCC->CR & (1 << 25)))
+    ;
+
+  /* Flash setup: four wait states at 80MHz */
+  FLASH->ACR = STM32_FLASHBITS;
+  while ((FLASH->ACR & 0x07) != (STM32_FLASHBITS & 0x07))
+    ;
+
+  /* Configure bus clocks: AHB: 80MHz, APB1: 40MHz, APB2: 40MHz */
+  RCC->CFGR = ((0x04 << 11) | (0x04 << 8));
+
+  /* Switch SYSCLOCK using PLL */
+  RCC->CFGR |= 0x03;
+  while ((RCC->CFGR & 0x0C) != 0x0C)
+    ;
+
+  /* Peripheral clock selection */
+  RCC->CCIPR = ( (0x00 << 26) |	 /* HSI48 for USB   */
+		 (0x00 <<  2) |  /* PCLK for USART2 */
+		 (0x00 <<  0) ); /* PCLK for USART1 */
+
+  /* Enable PWR clock */
+  RCC->APB1ENR1 |= (1 << 28);
+  RCC->APB1RSTR1 = (1 << 28);
+  RCC->APB1RSTR1 = 0;
+
+  /* Enable HSI48 clock */
+  RCC->CRRCR |= 1;
+  while ((RCC->CRRCR & 0x02) == 0)
+    ;
+}
+
+static struct GPIO *const GPIO_LED = (struct GPIO *)GPIO_LED_BASE;
+#ifdef GPIO_USB_BASE
+static struct GPIO *const GPIO_USB = (struct GPIO *)GPIO_USB_BASE;
+#endif
+#ifdef GPIO_OTHER_BASE
+static struct GPIO *const GPIO_OTHER = (struct GPIO *)GPIO_OTHER_BASE;
+#endif
+
+void
+gpio_init (void)
+{
+  /* Enable GPIO clock. */
+  RCC->AHB2ENR |= RCC_AHB2_GPIO;
+  /* Delay (more than two clocks) is needed.  */
+  while ((RCC->AHB2ENR & RCC_AHB2_GPIO) == 0)
+    ;
+
+  RCC->AHB2RSTR = RCC_AHB2_GPIO;
+  RCC->AHB2RSTR = 0;
+
+  /* Delay (more than two clocks) is needed.  */
+  while (RCC->AHB2RSTR != 0)
+    ;
+
+  /* LED is mandatory.  We configure it always.  */
+  GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
+  GPIO_LED->OTYPER  = VAL_GPIO_LED_OTYPER;
+  GPIO_LED->MODER   = VAL_GPIO_LED_MODER;
+  GPIO_LED->PUPDR   = VAL_GPIO_LED_PUPDR;
+  GPIO_LED->AFRL    = VAL_GPIO_LED_AFRL;
+  GPIO_LED->AFRH    = VAL_GPIO_LED_AFRH;
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
+  GPIO_OTHER->OTYPER  = VAL_GPIO_OTHER_OTYPER;
+  GPIO_OTHER->MODER   = VAL_GPIO_OTHER_MODER;
+  GPIO_OTHER->PUPDR   = VAL_GPIO_OTHER_PUPDR;
+  GPIO_OTHER->AFRL    = VAL_GPIO_OTHER_AFRL;
+  GPIO_OTHER->AFRH    = VAL_GPIO_OTHER_AFRH;
+#endif
+}

mcu/cortex-m.h

@@ -0,0 +1,29 @@
+/* System Control Block */
+struct SCB
+{
+  volatile uint32_t CPUID;
+  volatile uint32_t ICSR;
+  volatile uint32_t VTOR;
+  volatile uint32_t AIRCR;
+  volatile uint32_t SCR;
+  volatile uint32_t CCR;
+  volatile uint8_t  SHP[12];
+  volatile uint32_t SHCSR;
+  volatile uint32_t CFSR;
+  volatile uint32_t HFSR;
+  volatile uint32_t DFSR;
+  volatile uint32_t MMAR;
+  volatile uint32_t BFAR;
+  volatile uint32_t AFSR;
+  volatile uint32_t PFR[2];
+  volatile uint32_t DFR;
+  volatile uint32_t AFR;
+  volatile uint32_t MMFR[4];
+  volatile uint32_t ISAR[5];
+};
+
+#define SCS_BASE 0xE000E000
+#define SCB_BASE (SCS_BASE + 0x0D00)
+static struct SCB *const SCB = (struct SCB *)SCB_BASE;
+#define SCB_SCR_SLEEPDEEP (1 << 2)
+#define SCB_AIRCR_SYSRESETREQ 0x04

mcu/stm32.h

@@ -0,0 +1,224 @@
+#define PERIPH_BASE	0x40000000
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
+
+struct RCC {
+  volatile uint32_t CR;
+  volatile uint32_t CFGR;
+  volatile uint32_t CIR;
+  volatile uint32_t APB2RSTR;
+  volatile uint32_t APB1RSTR;
+  volatile uint32_t AHBENR;
+  volatile uint32_t APB2ENR;
+  volatile uint32_t APB1ENR;
+  volatile uint32_t BDCR;
+  volatile uint32_t CSR;
+#if defined(MCU_STM32F0)
+  volatile uint32_t AHBRSTR;
+  volatile uint32_t CFGR2;
+  volatile uint32_t CFGR3;
+  volatile uint32_t CR2;
+#endif
+};
+
+#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
+static struct RCC *const RCC = (struct RCC *)RCC_BASE;
+
+#define RCC_APB1ENR_USBEN	0x00800000
+#define RCC_APB1RSTR_USBRST	0x00800000
+
+#define RCC_CR_HSION		0x00000001
+#define RCC_CR_HSIRDY		0x00000002
+#define RCC_CR_HSITRIM		0x000000F8
+#define RCC_CR_HSEON		0x00010000
+#define RCC_CR_HSERDY		0x00020000
+#define RCC_CR_PLLON		0x01000000
+#define RCC_CR_PLLRDY		0x02000000
+
+#define RCC_CFGR_SWS		0x0000000C
+#define RCC_CFGR_SWS_HSI	0x00000000
+#define RCC_CFGR_SW_HSI		(0 << 0)
+#define RCC_CFGR_SW_HSE		(1 << 0)
+#define RCC_CFGR_SW_PLL		(2 << 0)
+#define RCC_CFGR_SW_MASK	(3 << 0)
+
+#define RCC_AHBENR_DMA1EN       0x00000001
+#define RCC_AHBENR_CRCEN        0x00000040
+
+#if defined(MCU_STM32F0)
+#define RCC_AHBRSTR_IOPARST	0x00020000
+#define RCC_AHBRSTR_IOPBRST	0x00040000
+#define RCC_AHBRSTR_IOPCRST	0x00080000
+#define RCC_AHBRSTR_IOPDRST	0x00100000
+#define RCC_AHBRSTR_IOPFRST	0x00400000
+
+#define RCC_AHBENR_IOPAEN	0x00020000
+#define RCC_AHBENR_IOPBEN	0x00040000
+#define RCC_AHBENR_IOPCEN	0x00080000
+#define RCC_AHBENR_IOPDEN	0x00100000
+#define RCC_AHBENR_IOPFEN	0x00400000
+
+#define RCC_APB2RSTR_SYSCFGRST	0x00000001
+#define RCC_APB2ENR_SYSCFGEN	0x00000001
+#else
+#define RCC_APB2ENR_ADC1EN      0x00000200
+#define RCC_APB2ENR_ADC2EN      0x00000400
+#define RCC_APB2ENR_TIM1EN      0x00000800
+#define RCC_APB1ENR_TIM2EN      0x00000001
+#define RCC_APB1ENR_TIM3EN      0x00000002
+#define RCC_APB1ENR_TIM4EN      0x00000004
+
+#define RCC_APB2RSTR_ADC1RST    0x00000200
+#define RCC_APB2RSTR_ADC2RST    0x00000400
+#define RCC_APB2RSTR_TIM1RST    0x00000800
+#define RCC_APB1RSTR_TIM2RST    0x00000001
+#define RCC_APB1RSTR_TIM3RST    0x00000002
+#define RCC_APB1RSTR_TIM4RST    0x00000004
+
+#define RCC_APB2RSTR_AFIORST	0x00000001
+#define RCC_APB2RSTR_IOPARST	0x00000004
+#define RCC_APB2RSTR_IOPBRST	0x00000008
+#define RCC_APB2RSTR_IOPCRST	0x00000010
+#define RCC_APB2RSTR_IOPDRST	0x00000020
+#define RCC_APB2RSTR_IOPERST	0x00000040
+#define RCC_APB2RSTR_IOPFRST	0x00000080
+#define RCC_APB2RSTR_IOPGRST	0x00000100
+
+#define RCC_APB2ENR_AFIOEN	0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+#define RCC_APB2ENR_IOPEEN	0x00000040
+#define RCC_APB2ENR_IOPFEN	0x00000080
+#define RCC_APB2ENR_IOPGEN	0x00000100
+#endif
+
+
+/* Clock setting values.
+ * Due to historical reason, it has the prefix of STM32_.
+ */
+#define STM32_SW_HSI		(0 << 0)
+#define STM32_SW_HSE		(1 << 0)
+#define STM32_SW_PLL		(2 << 0)
+
+#define STM32_PLLSRC_HSI	(0 << 16)
+#define STM32_PLLSRC_HSE	(1 << 16)
+
+#define STM32_PLLXTPRE_DIV1	(0 << 17)
+#define STM32_PLLXTPRE_DIV2	(1 << 17)
+
+#define STM32_HPRE_DIV1		(0 << 4)
+#define STM32_HPRE_DIV8		(10 << 4)
+#define STM32_HPRE_DIV16	(11 << 4)
+
+#define STM32_PPRE1_DIV1	(0 << 8)
+#define STM32_PPRE1_DIV2	(4 << 8)
+#define STM32_PPRE1_DIV16	(7 << 8)
+
+#define STM32_PPRE2_DIV1        (0 << 11)
+#define STM32_PPRE2_DIV2	(4 << 11)
+#define STM32_PPRE2_DIV16	(7 << 11)
+
+#define STM32_ADCPRE_DIV4	(1 << 14)
+#define STM32_ADCPRE_DIV6       (2 << 14)
+#define STM32_ADCPRE_DIV8	(3 << 14)
+
+#define STM32_USBPRE_DIV1P5     (0 << 22)
+#define STM32_USBPRE_DIV2       (3 << 22) /* Not for STM32, but GD32F103 */
+
+#define STM32_MCO_NOCLOCK	(0 << 24)
+
+struct PWR
+{
+  volatile uint32_t CR;
+  volatile uint32_t CSR;
+};
+static struct PWR *const PWR = ((struct PWR *)0x40007000);
+#define PWR_CR_LPDS 0x0001	/* Low-power deepsleep  */
+#define PWR_CR_PDDS 0x0002	/* Power down deepsleep */
+#define PWR_CR_CWUF 0x0004	/* Clear wakeup flag    */
+
+
+#if defined(MCU_STM32F0)
+struct GPIO {
+  volatile uint32_t MODER;
+  volatile uint16_t OTYPER;
+  uint16_t dummy0;
+  volatile uint32_t OSPEEDR;
+  volatile uint32_t PUPDR;
+  volatile uint16_t IDR;
+  uint16_t dummy1;
+  volatile uint16_t ODR;
+  uint16_t dummy2;
+  volatile uint16_t BSRR;
+  uint16_t dummy3;
+  volatile uint32_t LCKR;
+  volatile uint32_t AFR[2];
+  volatile uint16_t BRR;
+  uint16_t dummy4;
+};
+
+#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
+#define GPIOF		((struct GPIO *) GPIOF_BASE)
+#else
+struct GPIO {
+  volatile uint32_t CRL;
+  volatile uint32_t CRH;
+  volatile uint32_t IDR;
+  volatile uint32_t ODR;
+  volatile uint32_t BSRR;
+  volatile uint32_t BRR;
+  volatile uint32_t LCKR;
+};
+
+#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
+#define GPIOE		((struct GPIO *) GPIOE_BASE)
+#endif
+
+
+#if defined(MCU_STM32F0)
+struct SYSCFG {
+  volatile uint32_t CFGR1;
+  uint32_t dummy0;
+  volatile uint32_t EXTICR[4];
+  volatile uint32_t CFGR2;
+};
+#define SYSCFG_CFGR1_MEM_MODE 0x03
+
+#define SYSCFG_BASE	(APB1PERIPH_BASE + 0x00010000)
+static struct SYSCFG *const SYSCFG = (struct SYSCFG *)SYSCFG_BASE;
+#endif
+
+struct FLASH {
+  volatile uint32_t ACR;
+  volatile uint32_t KEYR;
+  volatile uint32_t OPTKEYR;
+  volatile uint32_t SR;
+  volatile uint32_t CR;
+  volatile uint32_t AR;
+  volatile uint32_t RESERVED;
+  volatile uint32_t OBR;
+  volatile uint32_t WRPR;
+};
+
+#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
+static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;

mcu/stm32f103.h

@@ -1,40 +1,5 @@
-#define PERIPH_BASE	0x40000000
+#include <mcu/stm32.h>
-#define APB1PERIPH_BASE PERIPH_BASE
+#include <mcu/cortex-m.h>
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = (struct RCC *)RCC_BASE;
-
-#define RCC_AHBENR_DMA1EN       0x00000001
-#define RCC_AHBENR_CRCEN        0x00000040
-
-#define RCC_APB2ENR_ADC1EN      0x00000200
-#define RCC_APB2ENR_ADC2EN      0x00000400
-#define RCC_APB2ENR_TIM1EN      0x00000800
-#define RCC_APB1ENR_TIM2EN      0x00000001
-#define RCC_APB1ENR_TIM3EN      0x00000002
-#define RCC_APB1ENR_TIM4EN      0x00000004
-
-#define RCC_APB2RSTR_ADC1RST    0x00000200
-#define RCC_APB2RSTR_ADC2RST    0x00000400
-#define RCC_APB2RSTR_TIM1RST    0x00000800
-#define RCC_APB1RSTR_TIM2RST    0x00000001
-#define RCC_APB1RSTR_TIM3RST    0x00000002
-#define RCC_APB1RSTR_TIM4RST    0x00000004
 
 #define  CRC_CR_RESET                        0x00000001
 
@@ -182,36 +147,6 @@ static struct DMA *const DMA1 = (struct DMA *)DMA1_BASE;
 static struct DMA_Channel *const DMA1_Channel1 =
   (struct DMA_Channel *)DMA1_Channel1_BASE;
 
-/* System Control Block */
-struct SCB
-{
-  volatile uint32_t CPUID;
-  volatile uint32_t ICSR;
-  volatile uint32_t VTOR;
-  volatile uint32_t AIRCR;
-  volatile uint32_t SCR;
-  volatile uint32_t CCR;
-  volatile uint8_t  SHP[12];
-  volatile uint32_t SHCSR;
-  volatile uint32_t CFSR;
-  volatile uint32_t HFSR;
-  volatile uint32_t DFSR;
-  volatile uint32_t MMFAR;
-  volatile uint32_t BFAR;
-  volatile uint32_t AFSR;
-  volatile uint32_t PFR[2];
-  volatile uint32_t DFR;
-  volatile uint32_t ADR;
-  volatile uint32_t MMFR[4];
-  volatile uint32_t ISAR[5];
-  uint32_t RESERVED0[5];
-  volatile uint32_t CPACR;
-};
-
-#define SCS_BASE 0xE000E000
-#define SCB_BASE (SCS_BASE + 0x0D00)
-static struct SCB *const SCB = (struct SCB *)SCB_BASE;
-
 /* Timer */
 struct TIM
 {
@@ -639,6 +574,8 @@ static struct EXTI *const EXTI = (struct EXTI *)EXTI_BASE;
 #define EXTI0_IRQ    6
 #define EXTI1_IRQ    7
 #define EXTI2_IRQ    8
+#define EXTI3_IRQ    9
+#define EXTI4_IRQ   10
 #define EXTI9_5_IRQ 23
 #define TIM2_IRQ    28
 #define TIM3_IRQ    29
@@ -698,3 +635,13 @@ static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE;
 
 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
 #define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE     0x02000000
+
+
+struct DBGMCU {
+  volatile uint32_t CR;
+};
+
+#define DBGMCU_BASE	0xE0042004
+#define DBG_SLEEP	1
+static struct DBGMCU *const DBGMCU = (struct DBGMCU *)DBGMCU_BASE;

mcu/stm32l.h

@@ -0,0 +1,197 @@
+#define PERIPH_BASE	0x40000000
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+#define AHB1PERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
+
+struct RCC {
+  volatile uint32_t CR;
+  volatile uint32_t ICSCR;
+  volatile uint32_t CFGR;
+  volatile uint32_t PLLCFGR;
+
+  volatile uint32_t PLLSAI1CFGR;
+  volatile uint32_t RESERVED0;
+  volatile uint32_t CIER;
+  volatile uint32_t CIFR;
+
+  volatile uint32_t CICR;
+  volatile uint32_t RESERVED1;
+  volatile uint32_t AHB1RSTR;
+  volatile uint32_t AHB2RSTR;
+
+  volatile uint32_t AHB3RSTR;
+  volatile uint32_t RESERVED2;
+  volatile uint32_t APB1RSTR1;
+  volatile uint32_t APB1RSTR2;
+
+  volatile uint32_t APB2RSTR;
+  volatile uint32_t RESERVED3;
+  volatile uint32_t AHB1ENR;
+  volatile uint32_t AHB2ENR;
+
+  volatile uint32_t AHB3ENR;
+  volatile uint32_t RESERVED4;
+  volatile uint32_t APB1ENR1;
+  volatile uint32_t APB1ENR2;
+
+  volatile uint32_t APB2ENR;
+  volatile uint32_t RESERVED5;
+  volatile uint32_t AHB1SMENR;
+  volatile uint32_t AHB2SMENR;
+
+  volatile uint32_t AHB3SMENR;
+  volatile uint32_t RESERVED6;
+  volatile uint32_t APB1SMENR1;
+  volatile uint32_t APB1SMENR2;
+
+  volatile uint32_t APB2SMENR;
+  volatile uint32_t RESERVED7;
+  volatile uint32_t CCIPR;
+  volatile uint32_t RESERVED8;
+
+  volatile uint32_t BDCR;
+  volatile uint32_t CSR;
+  volatile uint32_t CRRCR;
+  volatile uint32_t CCIPR2;
+};
+
+#define RCC_BASE		(AHB1PERIPH_BASE + 0x1000)
+static struct RCC *const RCC = (struct RCC *)RCC_BASE;
+
+#define RCC_AHB2_GPIOA       0x00000001
+#define RCC_AHB2_GPIOB       0x00000002
+#define RCC_AHB2_GPIOC       0x00000004
+#define RCC_AHB2_GPIOD       0x00000008
+#define RCC_AHB2_GPIOE       0x00000010
+#define RCC_AHB2_GPIOH       0x00000080
+
+#define RCC_APB1_1_USB         (1 << 26)
+#define RCC_APB1_1_CRS         (1 << 24)
+
+
+struct PWR
+{
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t CR3;
+  volatile uint32_t CR4;
+  volatile uint32_t SR1;
+  volatile uint32_t SR2;
+  volatile uint32_t SCR;
+  volatile uint32_t PUCRA;
+  volatile uint32_t PDCRA;
+  volatile uint32_t PUCRB;
+  volatile uint32_t PDCRB;
+  volatile uint32_t PUCRC;
+  volatile uint32_t PDCRC;
+  volatile uint32_t PUCRD;
+  volatile uint32_t PDCRD;
+  volatile uint32_t PUCRE;
+  volatile uint32_t PDCRE;
+  volatile uint32_t PUCRH;
+  volatile uint32_t PDCRH;
+};
+static struct PWR *const PWR = ((struct PWR *)0x40007000);
+
+struct GPIO {
+  volatile uint32_t MODER;
+  volatile uint32_t OTYPER;
+  volatile uint32_t OSPEEDR;
+  volatile uint32_t PUPDR;
+  volatile uint32_t IDR;
+  volatile uint32_t ODR;
+  volatile uint32_t BSRR;
+  volatile uint32_t LCKR;
+  volatile uint32_t AFRL;
+  volatile uint32_t AFRH;
+  volatile uint32_t BRR;
+};
+
+#define GPIOA_BASE	(AHB2PERIPH_BASE)
+static struct GPIO *const GPIOA	= (struct GPIO *)GPIOA_BASE;
+#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
+static struct GPIO *const GPIOB	= (struct GPIO *)GPIOB_BASE;
+
+
+struct FLASH {
+  volatile uint32_t ACR;
+  volatile uint32_t PDKEYR;
+  volatile uint32_t KEYR;
+  volatile uint32_t OPTKEYR;
+  volatile uint32_t SR;
+  volatile uint32_t CR;
+  volatile uint32_t ECCR;
+  volatile uint32_t RESERVED;
+  volatile uint32_t OPTR;
+  volatile uint32_t PCROP1SR;
+  volatile uint32_t PCROP1ER;
+  volatile uint32_t WRP1AR;
+  volatile uint32_t WRP1BR;
+};
+
+#define FLASH_R_BASE	(AHB1PERIPH_BASE + 0x2000)
+static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;
+
+struct USB_STM32L4 {
+  volatile uint16_t LPMCSR;
+  volatile uint16_t reserved0;
+  volatile uint16_t BCDR;
+  volatile uint16_t reserved1;
+};
+
+#define USB_STM32L4_BASE  (0x40006854UL)
+static struct USB_STM32L4 *const USB_STM32L4 = (struct USB_STM32L4 *)USB_STM32L4_BASE;
+
+struct SYSCFG {
+  volatile uint32_t MEMRMP;
+  volatile uint32_t CFGR1;
+  volatile uint32_t EXTICR[4];
+  volatile uint32_t SCSR;
+  volatile uint32_t CFGR2;
+  volatile uint32_t SWPR;
+  volatile uint32_t SKR;
+};
+
+#define SYSCFG_BASE  (APB2PERIPH_BASE+0UL)
+static struct SYSCFG *const SYSCFG = (struct SYSCFG *)SYSCFG_BASE;
+
+#define EXTI0_IRQ    6
+#define SYSCFG_EXTICR1_EXTI0_PA 0
+
+struct EXTI {
+  union {
+    volatile uint32_t IMR1;
+    volatile uint32_t IMR;
+  };
+  union {
+    volatile uint32_t EMR1;
+    volatile uint32_t EMR;
+  };
+  union {
+    volatile uint32_t RTSR1;
+    volatile uint32_t RTSR;
+  };
+  union {
+    volatile uint32_t FTSR1;
+    volatile uint32_t FTSR;
+  };
+  union {
+    volatile uint32_t SWIER1;
+    volatile uint32_t SWIER;
+  };
+  union {
+    volatile uint32_t PR1;
+    volatile uint32_t PR;
+  };
+  volatile uint32_t reserved;
+  volatile uint32_t IMR2;
+  volatile uint32_t EMR2;
+  volatile uint32_t RTSR2;
+  volatile uint32_t FTSR2;
+  volatile uint32_t SWIER2;
+  volatile uint32_t PR2;
+};
+
+#define EXTI_BASE (APB2PERIPH_BASE+0x0400)
+static struct EXTI *const EXTI = (struct EXTI *)EXTI_BASE;

mcu/sys-gnu-linux.c

@@ -16,8 +16,8 @@
 const uint8_t sys_version[8] = {
   3*2+2,	     /* bLength */
   0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
-  /* sys version: "3.0" */
+  /* sys version: "4.0" */
-  '3', 0, '.', 0, '0', 0,
+  '4', 0, '.', 0, '0', 0,
 };
 
 #if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)