Add mcu/*stm32l4.

mcu/chx-stm32l4.c

@@ -0,0 +1,29 @@
+#include <stdint.h>
+#include <mcu/cortex-m.h>
+#include <mcu/stm32l.h>
+
+extern int chx_allow_sleep;
+
+void
+chx_sleep_mode (int how)
+{
+  /*TBD*/
+  (void)how;
+}
+
+void __attribute__((naked))
+chx_idle (void)
+{
+  /*TBD*/
+  int sleep_enabled;
+
+  for (;;)
+    {
+      asm ("ldr	%0, %1" : "=r" (sleep_enabled): "m" (chx_allow_sleep));
+      if (sleep_enabled)
+	{
+	  asm volatile ("wfi" : : : "memory");
+	  /* NOTE: it never comes here.  Don't add lines after this.  */
+	}
+    }
+}

mcu/clk_gpio_init-stm32l.c

@@ -30,7 +30,7 @@
 
 #define STM32_FLASHBITS		0x00000704
 
-static void __attribute__((used))
+void
 clock_init (void)
 {
   /* MSI: 4MHz (keep the default value) */
@@ -65,12 +65,12 @@ static struct GPIO *const GPIO_USB = (struct GPIO *)GPIO_USB_BASE;
 static struct GPIO *const GPIO_OTHER = (struct GPIO *)GPIO_OTHER_BASE;
 #endif
 
-static void __attribute__((used))
+void
 gpio_init (void)
 {
   /* Enable GPIO clock. */
-  RCC->AHB2ENR |= RCC_IOP;
-  RCC->AHB2RSTR = RCC_IOP;
+  RCC->AHB2ENR |= RCC_PHR_GPIO;
+  RCC->AHB2RSTR = RCC_PHR_GPIO;
   RCC->AHB2RSTR = 0;
 
   /* Delay (more than two clocks) is needed.  */

mcu/stm32l.h

@@ -11,44 +11,44 @@ struct RCC {
   volatile uint32_t PLLCFGR;
 
   volatile uint32_t PLLSAI1CFGR;
-  volatile uint32_t RESERVED;
+  volatile uint32_t RESERVED0;
   volatile uint32_t CIER;
   volatile uint32_t CIFR;
 
   volatile uint32_t CICR;
-  volatile uint32_t RESERVED;
+  volatile uint32_t RESERVED1;
   volatile uint32_t AHB1RSTR;
   volatile uint32_t AHB2RSTR;
 
   volatile uint32_t AHB3RSTR;
-  volatile uint32_t RESERVED;
+  volatile uint32_t RESERVED2;
   volatile uint32_t APB1RSTR1;
   volatile uint32_t APB1RSTR2;
 
   volatile uint32_t APB2RSTR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t AHB1ENRR;
-  volatile uint32_t AHB2ENRR;
+  volatile uint32_t RESERVED3;
+  volatile uint32_t AHB1ENR;
+  volatile uint32_t AHB2ENR;
 
-  volatile uint32_t AHB3ENRR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t APB1ENRR1;
-  volatile uint32_t APB1ENRR2;
+  volatile uint32_t AHB3ENR;
+  volatile uint32_t RESERVED4;
+  volatile uint32_t APB1ENR1;
+  volatile uint32_t APB1ENR2;
 
-  volatile uint32_t APB2ENRR;
-  volatile uint32_t RESERVED;
+  volatile uint32_t APB2ENR;
+  volatile uint32_t RESERVED5;
   volatile uint32_t AHB1SMENR;
   volatile uint32_t AHB2SMENR;
 
   volatile uint32_t AHB3SMENR;
-  volatile uint32_t RESERVED;
+  volatile uint32_t RESERVED6;
   volatile uint32_t APB1SMENR1;
   volatile uint32_t APB1SMENR2;
 
   volatile uint32_t APB2SMENR;
-  volatile uint32_t RESERVED;
+  volatile uint32_t RESERVED7;
   volatile uint32_t CCIPR;
-  volatile uint32_t RESERVED;
+  volatile uint32_t RESERVED8;
 
   volatile uint32_t BDCR;
   volatile uint32_t CSR;
@@ -66,6 +66,9 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE;
 #define RCC_PHR_GPIOE       0x00000010
 #define RCC_PHR_GPIOH       0x00000080
 
+#define RCC_PHR_USB         (1 << 26)
+#define RCC_PHR_CRS         (1 << 24)
+
 
 struct PWR
 {

mcu/sys-stm32l4.c

@@ -0,0 +1,157 @@
+/*
+ * sys-stm32l432.c - system routines for STM32L432.
+ *
+ * Copyright (C) 2019  Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * Copying and distribution of this file, with or without modification,
+ * are permitted in any medium without royalty provided the copyright
+ * notice and this notice are preserved.  This file is offered as-is,
+ * without any warranty.
+ *
+ * We put some system routines (which is useful for any program) here.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <mcu/cortex-m.h>
+#include "board.h"
+
+#include "mcu/clk_gpio_init-stm32l.c"
+
+void
+set_led (int on)
+{
+#if defined(GPIO_LED_CLEAR_TO_EMIT)
+  if (on)
+    GPIO_LED->BRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
+  else
+    GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
+#else
+  if (on)
+    GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT);
+  else
+    GPIO_LED->BRR = (1 << GPIO_LED_SET_TO_EMIT);
+#endif
+}
+
+static void wait (int count)
+{
+  int i;
+
+  for (i = 0; i < count; i++)
+    asm volatile ("" : : "r" (i) : "memory");
+}
+
+
+void
+usb_lld_sys_shutdown (void)
+{
+  RCC->APB1ENR1 &= ~(RCC_PHR_USB | RCC_PHR_CRS);
+  RCC->APB1RSTR1 |= (RCC_PHR_USB | RCC_PHR_CRS);
+}
+
+void
+usb_lld_sys_init (void)
+{
+  /* XXX: should configure CRS (clock recovery system) and HSI48 clock */
+
+  if ((RCC->APB1ENR1 & RCC_PHR_USB) && (RCC->APB1RSTR1 & RCC_PHR_USB) == 0)
+    /* Make sure the device is disconnected, even after core reset.  */
+    {
+      usb_lld_sys_shutdown ();
+      /* Disconnect requires SE0 (>= 2.5uS).  */
+      wait (5*MHZ);
+    }
+
+  RCC->APB1ENR1 |= (RCC_PHR_USB | RCC_PHR_CRS);
+  RCC->APB1RSTR1 = (RCC_PHR_USB | RCC_PHR_CRS);
+  RCC->APB1RSTR1 = 0;
+}
+
+/* Not yet implemented, API should be reconsidered */
+
+void
+flash_unlock (void)
+{
+}
+
+
+#define intr_disable()  asm volatile ("cpsid   i" : : : "memory")
+#define intr_enable()  asm volatile ("cpsie   i" : : : "memory")
+
+
+int
+flash_wait_for_last_operation (uint32_t timeout)
+{
+  (void)timeout;
+  return 0;
+}
+
+int
+flash_program_halfword (uintptr_t addr, uint16_t data)
+{
+  (void)addr;
+  (void)data;
+  return 0;
+}
+
+int
+flash_erase_page (uintptr_t addr)
+{
+  (void)addr;
+  return 0;
+}
+
+int
+flash_check_blank (const uint8_t *p_start, size_t size)
+{
+  (void)p_start;
+  (void)size;
+  return 1;
+}
+
+
+int
+flash_write (uintptr_t dst_addr, const uint8_t *src, size_t len)
+{
+  (void)dst_addr;
+  (void)src;
+  (void)len;
+  return 1;
+}
+
+int
+flash_protect (void)
+{
+  return 0;
+}
+
+void __attribute__((naked))
+flash_erase_all_and_exec (void (*entry)(void))
+{
+  (void)entry;
+}
+
+void
+nvic_system_reset (void)
+{
+  SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SCB_AIRCR_SYSRESETREQ);
+  asm volatile ("dsb");
+  for (;;);
+}
+
+const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
+  3*2+2,	     /* bLength */
+  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
+  /* sys version: "3.0" */
+  '3', 0, '.', 0, '0', 0,
+};
+
+#if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)
+const uint32_t __attribute__((section(".sys.board_id")))
+sys_board_id = BOARD_ID;
+
+const uint8_t __attribute__((section(".sys.board_name")))
+sys_board_name[] = BOARD_NAME;
+#endif

mcu/sys-stm32l4.h

@@ -0,0 +1,33 @@
+#define BOARD_ID_ST_NUCLEO_L432    0x3a8d5116
+
+extern const uint8_t sys_version[8];
+#if defined(USE_SYS3) || defined(USE_SYS_BOARD_ID)
+extern const uint32_t sys_board_id;
+extern const uint8_t sys_board_name[];
+# define SYS_BOARD_ID sys_board_id
+#else
+# define SYS_BOARD_ID BOARD_ID
+#endif
+
+/* XXX: unique_device_id */
+
+void set_led (int on);
+
+uintptr_t flash_init (const char *f_name);
+void flash_unlock (void);
+int flash_program_halfword (uintptr_t addr, uint16_t data);
+int flash_erase_page (uintptr_t addr);
+int flash_check_blank (const uint8_t *p_start, size_t size);
+int flash_write (uintptr_t dst_addr, const uint8_t *src, size_t len);
+int flash_protect (void);
+void __attribute__((noreturn))
+flash_erase_all_and_exec (void (*entry)(void));
+
+void usb_lld_sys_init (void);
+void usb_lld_sys_shutdown (void);
+
+void __attribute__((noreturn))
+nvic_system_reset (void);
+
+void clock_init (void);
+void gpio_init (void);

sys.h

@@ -4,6 +4,8 @@
 #include "mcu/sys-mkl27z.h"
 #elif defined(MCU_STM32F0)
 #include "mcu/sys-stm32f0.h"
+#elif defined(MCU_STM32L4)
+#include "mcu/sys-stm32l4.h"
 #else
 #include "mcu/sys-stm32f103.h"
 #endif