142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
#define PERIPH_BASE 0x40000000
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#define APB1PERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
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struct RCC {
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volatile uint32_t CR;
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volatile uint32_t ICSCR;
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volatile uint32_t CFGR;
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volatile uint32_t PLLCFGR;
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volatile uint32_t PLLSAI1CFGR;
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volatile uint32_t RESERVED0;
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volatile uint32_t CIER;
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volatile uint32_t CIFR;
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volatile uint32_t CICR;
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volatile uint32_t RESERVED1;
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volatile uint32_t AHB1RSTR;
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volatile uint32_t AHB2RSTR;
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volatile uint32_t AHB3RSTR;
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volatile uint32_t RESERVED2;
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volatile uint32_t APB1RSTR1;
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volatile uint32_t APB1RSTR2;
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volatile uint32_t APB2RSTR;
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volatile uint32_t RESERVED3;
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volatile uint32_t AHB1ENR;
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volatile uint32_t AHB2ENR;
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volatile uint32_t AHB3ENR;
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volatile uint32_t RESERVED4;
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volatile uint32_t APB1ENR1;
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volatile uint32_t APB1ENR2;
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volatile uint32_t APB2ENR;
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volatile uint32_t RESERVED5;
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volatile uint32_t AHB1SMENR;
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volatile uint32_t AHB2SMENR;
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volatile uint32_t AHB3SMENR;
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volatile uint32_t RESERVED6;
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volatile uint32_t APB1SMENR1;
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volatile uint32_t APB1SMENR2;
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volatile uint32_t APB2SMENR;
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volatile uint32_t RESERVED7;
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volatile uint32_t CCIPR;
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volatile uint32_t RESERVED8;
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volatile uint32_t BDCR;
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volatile uint32_t CSR;
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volatile uint32_t CRRCR;
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volatile uint32_t CCIPR2;
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};
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#define RCC_BASE (AHB1PERIPH_BASE + 0x1000)
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static struct RCC *const RCC = (struct RCC *)RCC_BASE;
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#define RCC_PHR_GPIOA 0x00000001
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#define RCC_PHR_GPIOB 0x00000002
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#define RCC_PHR_GPIOC 0x00000004
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#define RCC_PHR_GPIOD 0x00000008
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#define RCC_PHR_GPIOE 0x00000010
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#define RCC_PHR_GPIOH 0x00000080
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#define RCC_PHR_USB (1 << 26)
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#define RCC_PHR_CRS (1 << 24)
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struct PWR
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{
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t CR3;
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volatile uint32_t CR4;
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volatile uint32_t SR1;
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volatile uint32_t SR2;
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volatile uint32_t SCR;
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volatile uint32_t PUCRA;
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volatile uint32_t PDCRA;
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volatile uint32_t PUCRB;
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volatile uint32_t PDCRB;
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volatile uint32_t PUCRC;
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volatile uint32_t PDCRC;
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volatile uint32_t PUCRD;
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volatile uint32_t PDCRD;
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volatile uint32_t PUCRE;
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volatile uint32_t PDCRE;
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volatile uint32_t PUCRH;
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volatile uint32_t PDCRH;
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};
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static struct PWR *const PWR = ((struct PWR *)0x40007000);
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struct GPIO {
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volatile uint32_t MODER;
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volatile uint32_t OTYPER;
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volatile uint32_t OSPEEDR;
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volatile uint32_t PUPDR;
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volatile uint32_t IDR;
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volatile uint32_t ODR;
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volatile uint32_t BSRR;
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volatile uint32_t LCKR;
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volatile uint32_t AFRL;
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volatile uint32_t AFRH;
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volatile uint32_t BRR;
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};
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#define GPIOA_BASE (AHB2PERIPH_BASE)
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#define GPIOA ((struct GPIO *) GPIOA_BASE)
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#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
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#define GPIOB ((struct GPIO *) GPIOB_BASE)
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#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
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#define GPIOC ((struct GPIO *) GPIOC_BASE)
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#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
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#define GPIOD ((struct GPIO *) GPIOD_BASE)
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#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
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#define GPIOE ((struct GPIO *) GPIOE_BASE)
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#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00)
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#define GPIOH ((struct GPIO *) GPIOH_BASE)
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struct FLASH {
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volatile uint32_t ACR;
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volatile uint32_t PDKEYR;
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volatile uint32_t KEYR;
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volatile uint32_t OPTKEYR;
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volatile uint32_t SR;
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volatile uint32_t CR;
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volatile uint32_t ECCR;
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volatile uint32_t RESERVED;
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volatile uint32_t OPTR;
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volatile uint32_t PCROP1SR;
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volatile uint32_t PCROP1ER;
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volatile uint32_t WRP1AR;
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volatile uint32_t WRP1BR;
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};
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#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000)
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static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;
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