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fix for newer GNU Toolchain

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NIIBE Yutaka
2013-03-14 13:24:35 +09:00
parent ca46cc465c
commit 4abcddef93
2 changed files with 9 additions and 3 deletions
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6
ChangeLog
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@@ -1,3 +1,9 @@
2013-03-13 Niibe Yutaka <gniibe@fsij.org>
* ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c (__STREXB)
(__STREXH, __STREXW): Specify R2 to avoid %0 and %2 will be same
register. This is for newer binutils (>= 2.22).
2013-03-12 Niibe Yutaka <gniibe@fsij.org>
* tool/stlinkv2.py (stlinkv2.exit_from_debug_swd)

6
ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c
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@@ -731,7 +731,7 @@ uint32_t __LDREXW(uint32_t *addr)
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
register uint32_t result asm ("r2");
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
@@ -748,7 +748,7 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr)
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
register uint32_t result asm ("r2");
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
@@ -765,7 +765,7 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr)
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
register uint32_t result asm ("r2");
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);