From 4abcddef93c196d5752e3e8cd347c7715c9b3cd2 Mon Sep 17 00:00:00 2001 From: NIIBE Yutaka Date: Thu, 14 Mar 2013 13:24:35 +0900 Subject: [PATCH] fix for newer GNU Toolchain --- ChangeLog | 6 ++++++ ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c | 6 +++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/ChangeLog b/ChangeLog index 9a26cbc..6f8e527 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2013-03-13 Niibe Yutaka + + * ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c (__STREXB) + (__STREXH, __STREXW): Specify R2 to avoid %0 and %2 will be same + register. This is for newer binutils (>= 2.22). + 2013-03-12 Niibe Yutaka * tool/stlinkv2.py (stlinkv2.exit_from_debug_swd) diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c index fcff0d1..dc4cc02 100644 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c +++ b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c @@ -731,7 +731,7 @@ uint32_t __LDREXW(uint32_t *addr) */ uint32_t __STREXB(uint8_t value, uint8_t *addr) { - uint32_t result=0; + register uint32_t result asm ("r2"); __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); @@ -748,7 +748,7 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr) */ uint32_t __STREXH(uint16_t value, uint16_t *addr) { - uint32_t result=0; + register uint32_t result asm ("r2"); __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result); @@ -765,7 +765,7 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr) */ uint32_t __STREXW(uint32_t value, uint32_t *addr) { - uint32_t result=0; + register uint32_t result asm ("r2"); __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); return(result);