Version 1.10.

.gitlab-ci.yml

@@ -0,0 +1,15 @@
+image: debian:stable
+
+before_script:
+  - apt-get update && apt-get -y install texi2html
+
+pages:
+  stage: deploy
+  script:
+  - mkdir -p html && (cd html && texi2html ../doc/chopstx.texi)
+  - mv html/ public
+  artifacts:
+    paths:
+    - public
+  only:
+    - master

AUTHORS

@@ -19,7 +19,7 @@ Kenji Rikitake:
 
 Kiwamu Okabe:
     Wrote an OpenOCD scirpt:
-        example-fsm-55/stlink-v2.cfg
+	example-fsm-55/stlink-v2.cfg
 
 Mateusz Zalega:
     Added Nitrokey-Start support.
@@ -28,7 +28,7 @@ Mateusz Zalega:
 NIIBE Yutaka:
     Wrote the library:
 	chopstx.c, entry.c, eventflag.c,
-        chopstx.h, eventflag.h
+	chopstx.h, eventflag.h
     Wrote the drivers mcu/*:
     	clk_gpio_init-mkl27z.c, clk_gpio_init-stm32.c,
 	sys-stm32f103.c, sys-stm32f030.c, sys-mkl27z.c,
@@ -36,9 +36,10 @@ NIIBE Yutaka:
     Drew the logo:
 	chopstx.svg, chopstx.png
     Wrote examples:
-        example-led, example-cdc, example-fsm-55, example-fs-bb48
+	example-led, example-cdc, example-fsm-55, example-fs-bb48,
+	example-usb-serial
     Wrote board/*:
-        board-fst-01.h, board-fst-01-00.h,
+	board-fst-01.h, board-fst-01-00.h,
 	board-olimex-stm32-h103.h, board-stm8s-discovery.h
 	board-cq-starm.h, board-stbee-mini.h, board-stbee.h,
 
@@ -47,7 +48,8 @@ NIIBE Yutaka:
 	board-fs-bb48.h
 
     Under contract of g10 Code GmbH, wrote:
-        mcu/usb-usbip.c
+	mcu/usb-usbip.c
+	contrib/usart-stm32f103.c
 
 Paul Fertser:
     Added Blue Pill support.

ChangeLog

@@ -1,3 +1,125 @@
+2018-09-29  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.10.
+	* doc/chopstx.texi (VERSION): 1.10.
+
+2018-09-27  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/ackbtn-stm32f103.c: New.
+	* rules.mk [USE_ACKBTN] (CSRC): Add ack-button support.
+
+2018-09-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+	Fix for chopstx_intr_done.  No spurious interrupts.
+	* contrib/adc-mkl27z.c (adc_wait_completion): Fix.
+	* contrib/adc-stm32f103.c (adc_wait_completion): Likewise.
+	* contrib/usart-stm32f103.c (usart_main): Likewise.
+	* example-cdc-gnu-linux/usb-cdc.c (tty_main): Likewise.
+	* example-cdc/usb-cdc.c (tty_main): Likewise.
+	* example-fraucheky/main.c (usb_main): Likewise.
+	* example-fs-bb48/touch.c (touch_get): Likewise.
+	* example-fs-bb48/usb-cdc.c (tty_main): Likewise.
+	* example-primer2/primer2-ts.c (adc3_conversion): Likewise.
+	* example-usb-serial/usb-cdc.c (cdc_main): Likewise.
+
+2018-09-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.h (chopstx_intr_done): New function.
+	* chopstx.c (chopstx_intr_done): New function.
+	(chopstx_poll): Don't call chx_clr_intr.
+	Ensure data memory barrier for interrupt handling.
+
+	* chopstx-cortex-m.c (chx_dmb): New static function.
+	* chopstx-gnu-linux.c (chx_dmb): Ditto.
+
+2018-09-21  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/stm32.h (struct GPIO, struct FLASH): Moved from...
+	* mcu/clk_gpio_init-stm32.c: ... here.
+	(AFIO_MAPR_SWJ_CFG_JTAGDISABLE): Move to ...
+	* mcu/stm32f103.h: ... here.
+	* mcu/sys-stm32f103.c: Don't include "mcu/cortex-m.h".
+
+	* board/board-fst-01sz.h: New.
+	* mcu/sys-stm32f103.h (BOARD_ID_FST_01SZ): New.
+	* contrib/adc-stm32f103.c (get_adc_config): Add BOARD_ID_FST_01SZ.
+
+2018-08-20  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/usb-stm32f103.c (usb_lld_ctrl_send): Fix for ZLP.
+	* mcu/usb-usbip.c (usb_lld_ctrl_send): Likewise.
+	* mcu/usb-mkl27z.c (usb_lld_ctrl_send): Likewise.
+
+2018-05-09  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.9.
+	* doc/chopstx.texi (VERSION): 1.9.
+
+2018-05-08  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-blue-pill.h (GPIO_USB_SET_TO_ENABLE): Remove.
+
+	* doc/chopstx.texi (Compile-time macro): New chapter.
+
+	* mcu/sys-stm32f103.c (usb_lld_sys_init): Use MHZ.
+	(flash_protect): Fix for GD32F103.
+
+2018-04-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-blue-pill-g.h: New.  Define STM32_ADCPRE and
+	STM32_USBPRE for 96MHz clock.
+	* mcu/stm32.h (STM32_USBPRE_DIV2): New for GD32F103.
+	* mcu/clk_gpio_init-stm32.c: Allow constants, which are defined by
+	board.h	(STM32_ADCPRE and STM32_USBPRE).
+	* mcu/chx-stm32f103.c: Use STM32_ADCPRE and STM32_USBPRE.
+
+	* mcu/usb-stm32f103.c (usb_lld_init): BTABLE setting at
+	initialization.
+	(usb_lld_reset): Not at each reset.
+
+	* contrib/adc-stm32f103.c [MCU_STM32F1_GD32F1]: Use continuous
+	sampling with no DELIBARATELY_DO_IT_WRONG_START_STOP.
+	(adc_init): Wait after ADC_CR2_ADON.
+	(adc_start): Likewise.  Enabling by ADC_CR2_ADON after all other
+	registers configuration.
+
+2018-01-19  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.8.
+	* doc/chopstx.texi (VERSION): 1.8.
+
+2018-01-18  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/stm32f103.h: Include stm32.h and cortex-m.h.
+
+2018-01-09  Anthony Romano <romanoanthony061@gmail.com>
+
+	* contrib/adc-stm32f103.c: Support IN8 config.
+
+2017-12-19  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.7.
+	* doc/chopstx.texi (VERSION): 1.7.
+
+2017-12-18  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* contrib/usart-stm32f103.c: New.
+	* example-usb-serial: New example.
+
+2017-12-16  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chx_timer_expired): Bug fix of wake up.
+	(chx_mutex_unlock): Avoid non-deterministic thing.
+
+2017-12-14  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-st-nucleo-f103.h: Update.
+
+	* mcu/sys-stm32f103.h (BOARD_ID_FST_01G): New.
+
+	* contrib/adc-stm32f103.c (get_adc_config): Add a case for
+	BOARD_ID_FST_01G and BOARD_ID_ST_NUCLEO_F103.
+
 2017-11-24  NIIBE Yutaka  <gniibe@fsij.org>
 
 	* VERSION: 1.6.

NEWS

@@ -1,6 +1,68 @@
 NEWS - Noteworthy changes
 
 
+* Major changes in Chopstx 1.10
+
+  Released 2018-09-29
+
+** Function chopstx_intr_wait is not deprecated, now.
+Once, it was said that it's deprecated, but it's active again
+to match the new function of chopstx_intr_done.
+
+** API change: chopstx_poll, chopstx_intr_wait, chopstx_intr_done
+To avoid spurious interrupt, we introduce new function
+chopstx_intr_done, which should be called after interrupt handling.
+
+** New driver: Acknowledge button for FST-01SZ
+The use case is waiting user's acknowledge.  We use EXTI interrupt
+feature of STM32.
+
+
+* Major changes in Chopstx 1.9
+
+  Released 2018-05-09
+
+** GD32F103 support
+GD32F103 is an alternative implementation of STM32F103 by Giga Device,
+which can run at 96MHz.
+
+** Minor USB driver fix for STM32F103/GD32F103
+BTABLE setting should be done at initialization, not at USB RESET.
+
+** Minor SYS driver fix for GD32F103
+flash_protect should check FLASH_CR_OPTWRE.
+
+** Minor ADC driver change for GD32F103
+ADC on GD32F103 is another implementation and its behavior is somewhat
+different.  It requires waits after enabling.  So, we use continuous
+sampling, instead of start and stop for each sample.  Still, we
+observe enough noise (> 4.7 bit/byte) for each ADC sampling.
+
+
+* Major changes in Chopstx 1.8
+
+  Released 2018-01-19
+
+** Minor driver API fix
+In version 1.6, part of mcu/stm32f103.h was moved into mcu/cortex-m.h
+and mcu/stm32.h.  Now, mcu/stm32f103.h automatically includes
+mcu/cortex-m.h and mcu/stm32.h, so that it doesn't break existing
+applications.
+
+
+* Major changes in Chopstx 1.7
+
+  Released 2017-12-19
+
+** Fix: timer wakeup
+Timer expiration had a bug.  When it is waken up, the wake up doesn't
+handle as a timer expiration when there are multiple threads on same
+timing of expire.  It confuses as if it were forced wakeup.
+
+** New driver: USART for STM32.
+USART driver for STM32 is added.
+
+
 * Major changes in Chopstx 1.6
 
   Released 2017-11-24

README

@@ -1,14 +1,14 @@
 Chopstx - Threads and only Threads
-							 Version 1.6
-							  2017-11-24
+							Version 1.10
+							  2018-09-29
 							Niibe Yutaka
 					     Flying Stone Technology
 
 What's Chopstx?
 ===============
 
-Chopstx is an RT thread library for STM32F103 (ARM Cortex-M3),
-STM32F030 (ARM Cortex-M0), MKL27Z (ARM Cortex-M0plus), and
+Chopstx is an RT thread library for STM32F103 and GD32F103 (ARM
+Cortex-M3), STM32F030 (ARM Cortex-M0), MKL27Z (ARM Cortex-M0plus), and
 emulation on GNU/Linux.
 
 While most RTOSes come with many features, drivers, and protocol
@@ -17,12 +17,17 @@ stacks, Chopstx just offers a simple RT thread library.
 With Chopstx, interrupt handling is also done by a thread.  This
 enables coherent code for ease of maintenance.
 
+While threads are important, we don't need more threads than
+necessary.  Chopstx provides a feature of poll, so that we can
+minimize use of threads.
+
+
 Note that this library is _not_ related to the hand game:
 
     https://en.wikipedia.org/wiki/Chopsticks_(hand_game)
 
 Thanks to Yao Wei and Enrico Zini for giving me an opportunity
-visiting the wiki page above.
+visiting the wiki page above, when my children were playing the game.
 
 
 License
@@ -44,6 +49,8 @@ CDC-ACM demo by:
    $ ln -sf ../board/board-olimex-stm32-h103.h board.h
    $ make
 
+If you want to try GD32F103, Add -DMHZ=96 to DEFS in Makefile.
+
 For a specific board named FSM-55, an example of LED matrix dynamic
 driver is provided.  See the directory: example-fsm-55.
 

VERSION

@@ -1 +1 @@
-release/1.6
+release/1.10

board/board-blue-pill-g.h

@@ -0,0 +1,42 @@
+#define BOARD_NAME "Blue Pill GD32F103"
+/* http://wiki.stm32duino.com/index.php?title=Blue_Pill */
+/* echo -n "Blue Pill GD32F103" | shasum -a 256 | sed -e 's/^.*\(........\)  -$/\1/' */
+#define BOARD_ID    0xed415594
+
+#define MCU_STM32F1_GD32F1 1
+#define STM32_USBPRE                    STM32_USBPRE_DIV2
+#define STM32_ADCPRE                    STM32_ADCPRE_DIV8
+
+#define MCU_STM32F1 1
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              12
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOC_BASE
+#define GPIO_LED_CLEAR_TO_EMIT          13
+#define GPIO_USB_BASE   GPIOA_BASE
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ *
+ * Port C setup.
+ * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ * PCx  - input with pull-up
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFE7FF
+#define VAL_GPIO_USB_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x88811888      /* PA15...PA8 */
+
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x88388888      /* PC15...PC8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPCRST)

board/board-blue-pill.h

@@ -13,13 +13,14 @@
 #define GPIO_LED_BASE   GPIOC_BASE
 #define GPIO_LED_CLEAR_TO_EMIT          13
 #define GPIO_USB_BASE   GPIOA_BASE
-#define GPIO_USB_SET_TO_ENABLE          12
 #undef  GPIO_OTHER_BASE
 
 /*
  * Port A setup.
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ *
+ * Port C setup.
  * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF)
  * ------------------------ Default
  * PAx  - input with pull-up

board/board-fst-01.h

@@ -71,6 +71,7 @@
  * Those will be removed soon, once such an driver will be improved
  * in new style.
  */
+#if defined(PINPAD_CIR_SUPPORT)
 /* For pin-cir settings of Gnuk */
 #define TIMx                  TIM2
 #define INTR_REQ_TIM          TIM2_IRQ
@@ -83,3 +84,4 @@
 #define ENABLE_RCC_APB1
 #define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM2EN
 #define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM2RST
+#endif

board/board-fst-01g.h

@@ -71,7 +71,7 @@
  * Those will be removed soon, once such an driver will be improved
  * in new style.
  */
-/* For pin-cir settings of Gnuk */
+#if defined(PINPAD_CIR_SUPPORT)
 #define TIMx                  TIM2
 #define INTR_REQ_TIM          TIM2_IRQ
 #define AFIO_EXTICR_INDEX     0
@@ -83,3 +83,4 @@
 #define ENABLE_RCC_APB1
 #define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM2EN
 #define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM2RST
+#endif

board/board-fst-01sz.h

@@ -0,0 +1,43 @@
+#define BOARD_NAME "FST-01SZ"
+#define BOARD_ID    0x7e6fb084
+/* echo -n "FST-01SZ" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
+
+#define MCU_STM32F1_GD32F1 1
+#define STM32_USBPRE                    STM32_USBPRE_DIV2
+#define STM32_ADCPRE                    STM32_ADCPRE_DIV8
+
+#define MCU_STM32F1 1
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              8
+#define STM32_HSECLK                    12000000
+
+#define GPIO_LED_BASE   GPIOA_BASE
+#define GPIO_LED_SET_TO_EMIT            8
+#define GPIO_USB_BASE   GPIOA_BASE
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up: AN0 for NeuG
+ * PA1  - input with pull-up: AN1 for NeuG
+ * PA3  - input with pull-up: Hall effect sensor output
+ * PA8  - Push pull output 10MHz 0 default (LED 1:ON 0:OFF)
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up.
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFE6FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88811881      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
+
+/*
+ * Board specific information other than clock and GPIO initial
+ * setting should not be in board-*.h, but each driver should include
+ * such specific information by itself.
+ */

board/board-olimex-stm32-h103.h

@@ -31,11 +31,3 @@
 
 #define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPCEN
 #define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPCRST
-
-/* NeuG settings for ADC2.  */
-#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \
-                              | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5)
-#define NEUG_ADC_SETTING2_SMPR2 0
-#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)   \
-                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11)
-#define NEUG_ADC_SETTING2_NUM_CHANNELS 2

board/board-st-nucleo-f103.h

@@ -26,21 +26,40 @@
 #define GPIO_LED_BASE   GPIOA_BASE
 #define GPIO_LED_SET_TO_EMIT            5
 #undef  GPIO_USB_BASE		/* No external DISCONNECT/RENUM circuit.  */
-#undef  GPIO_OTHER_BASE
+#define GPIO_OTHER_BASE GPIOB_BASE
 
 /*
  * Port A setup.
- * PA0  - input with pull-up.  AN0
- * PA1  - input with pull-up.  AN1
- * PA5  - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * PA0  - Input with pull-up                       USART2-CTS
+ * PA1  - Alternate function push pull output 2MHz USART2-RTS
+ * PA2  - Alternate function push pull output 2MHz USART2-TX
+ * PA3  - Input with pull-up                       USART2-RX
+ * PA4  - Alternate function push pull output 2MHz USART2-CK
+ * PA5  - Push pull output 2MHz (LED 1:ON 0:OFF)
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
  * ------------------------ Default
  * PAx  - input with pull-up
  */
 #define VAL_GPIO_LED_ODR            0xFFFFE7FF
-#define VAL_GPIO_LED_CRL            0x88388888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRL            0x882A8AA8      /*  PA7...PA0 */
 #define VAL_GPIO_LED_CRH            0x88811888      /* PA15...PA8 */
 
-#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
-#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
+/*
+ * Port B setup.
+ * PB0  - input with pull-up: AN8 for NeuG
+ * PB1  - input with pull-up: AN9 for NeuG
+ * PB10 - Alternate function push pull output 2MHz USART3-TX
+ * PB11 - Input with pull-up                       USART3-RX
+ * PB12 - Alternate function push pull output 2MHz USART3-CK
+ * PB13 - Input with pull-up                       USART3-CTS
+ * PB14 - Alternate function push pull output 2MHz USART3-RTS
+ * ------------------------ Default
+ * PBx  - input with pull-up.
+ */
+#define VAL_GPIO_OTHER_ODR          0xFFFFFFFF
+#define VAL_GPIO_OTHER_CRL          0x88888888      /*  PB7...PB0 */
+#define VAL_GPIO_OTHER_CRH          0x8A8A8A88      /* PB15...PB8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)

board/board-stm8s-discovery.h

@@ -44,7 +44,7 @@
 #define VAL_GPIO_OTHER_CRH 0x88888888      /* PB15...PB8 */
 
 
-/* For pin-cir settings of Gnuk */
+#if defined(PINPAD_CIR_SUPPORT)
 #define TIMx                  TIM3
 #define INTR_REQ_TIM          TIM3_IRQ
 #define AFIO_EXTICR_INDEX     1
@@ -58,3 +58,4 @@
 #define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM3RST
 #define AFIO_MAPR_SOMETHING   AFIO_MAPR_TIM3_REMAP_PARTIALREMAP
                               /* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */
+#endif

chopstx-cortex-m.c

@@ -2,7 +2,7 @@
  * chopstx-cortex-m.c - Threads and only threads: Arch specific code
  *                      for Cortex-M0/M3
  *
- * Copyright (C) 2013, 2014, 2015, 2016, 2017
+ * Copyright (C) 2013, 2014, 2015, 2016, 2017, 2018
  *               Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -28,6 +28,13 @@
  *
  */
 
+/* Data Memory Barrier.  */
+static void
+chx_dmb (void)
+{
+  asm volatile ("dmb"  : : : "memory");
+}
+
 /* Saved registers on the stack.  */
 struct chx_stack_regs {
   uint32_t reg[8];	       /* r0, r1, r2, r3, r12, lr, pc, xpsr */
@@ -287,7 +294,7 @@ chx_request_preemption (uint16_t prio)
  *
  * Returns:
  *          1 on wakeup by others.
- *          0 on normal wakeup.
+ *          0 on normal wakeup (timer expiration, lock aquirement).
  *         -1 on cancellation.
  */
 static uintptr_t __attribute__ ((naked, noinline))

chopstx-gnu-linux.c

@@ -2,7 +2,7 @@
  * chopstx-gnu-linux.c - Threads and only threads: Arch specific code
  *                       for GNU/Linux emulation
  *
- * Copyright (C) 2017 Flying Stone Technology
+ * Copyright (C) 2017, 2018 Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -32,6 +32,13 @@
 #include <signal.h>
 #include <sys/time.h>
 
+/* Data Memory Barrier.  */
+static void
+chx_dmb (void)
+{
+}
+
+
 static sigset_t ss_cur;
 
 static void

chopstx.c

@@ -1,7 +1,7 @@
 /*
  * chopstx.c - Threads and only threads.
  *
- * Copyright (C) 2013, 2014, 2015, 2016, 2017
+ * Copyright (C) 2013, 2014, 2015, 2016, 2017, 2018
  *               Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -403,6 +403,7 @@ chx_timer_expired (void)
 	       tp = tp_next)
 	    {
 	      next_tick = tp->v;
+	      tp->v = (uintptr_t)0;
 	      tp_next = (struct chx_thread *)tp->next;
 	      ll_dequeue ((struct chx_pq *)tp);
 	      chx_ready_enqueue (tp);
@@ -575,6 +576,7 @@ chx_mutex_unlock (chopstx_mutex_t *mutex)
       uint16_t newprio = running->prio_orig;
       chopstx_mutex_t *m;
 
+      tp->v = (uintptr_t)0;
       chx_ready_enqueue (tp);
 
       /* Examine mutexes we hold, and determine new priority for running.  */
@@ -1032,6 +1034,23 @@ chopstx_intr_wait (chopstx_intr_t *intr)
 }
 
 
+/**
+ * chopstx_intr_done - Finish an IRQ handling
+ * @intr: Pointer to INTR structure
+ *
+ * Finish for the interrupt @intr occurred.
+ *
+ */
+void
+chopstx_intr_done (chopstx_intr_t *intr)
+{
+  chx_dmb ();
+
+  if (intr->ready)
+    chx_clr_intr (intr->irq_num);
+}
+
+
 /**
  * chopstx_cleanup_push - Register a clean-up
  * @clp: Pointer to clean-up structure
@@ -1330,6 +1349,7 @@ chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *const pd_array[])
   struct chx_poll_head *pd;
   int r = 0;
 
+  chx_dmb ();
   chopstx_testcancel ();
 
   for (i = 0; i < n; i++)
@@ -1382,6 +1402,7 @@ chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *const pd_array[])
       while (r == 0);
     }
 
+  chx_dmb ();
   for (i = 0; i < n; i++)
     {
       pd = pd_array[i];
@@ -1402,9 +1423,7 @@ chopstx_poll (uint32_t *usec_p, int n, struct chx_poll_head *const pd_array[])
 	{
 	  struct chx_intr *intr = (struct chx_intr *)pd;
 
-	  if (intr->ready)
-	    chx_clr_intr (intr->irq_num);
-	  else
+	  if (intr->ready == 0)
 	    {
 	      chx_spin_lock (&q_intr.lock);
 	      ll_dequeue ((struct chx_pq *)&px[i]);

chopstx.h

@@ -155,7 +155,8 @@ typedef struct chx_intr chopstx_intr_t;
 
 void chopstx_claim_irq (chopstx_intr_t *intr, uint8_t irq_num);
 
-void chopstx_intr_wait (chopstx_intr_t *intr); /* DEPRECATED */
+void chopstx_intr_wait (chopstx_intr_t *intr);
+void chopstx_intr_done (chopstx_intr_t *intr);
 
 
 int chopstx_poll (uint32_t *usec_p, int n,

contrib/ackbtn-stm32f103.c

@@ -0,0 +1,88 @@
+/*
+ * ackbtn-stm32f103.c - Acknowledge button support for STM32F103
+ *
+ * Copyright (C) 2018  g10 Code GmbH
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <chopstx.h>
+#include <mcu/stm32f103.h>
+
+#include "board.h"
+#include "sys.h"
+
+static uint32_t pin_config;
+
+void
+ackbtn_init (chopstx_intr_t *intr)
+{
+  uint8_t irq_num;
+  uint32_t afio_exticr_index;
+  uint32_t afio_exticr_extiX_pY;
+  int rising_edge;
+
+  switch (SYS_BOARD_ID)
+    {
+    case BOARD_ID_FST_01SZ:
+    default:
+      /* PA3 is connected to a hall sensor DRV5032FA */
+      afio_exticr_index = 0;
+      afio_exticr_extiX_pY = AFIO_EXTICR1_EXTI3_PA;
+      irq_num = EXTI3_IRQ;
+      pin_config = 0x0008; /* EXTI_PR_PR3 == EXTI_IMR_MR3 == EXTI_RTSR_TR3 */
+      rising_edge = 1;
+      break;
+    }
+
+  chopstx_claim_irq (intr, irq_num);
+
+  /* Configure EXTI line */
+  if (afio_exticr_extiX_pY)
+    AFIO->EXTICR[afio_exticr_index] |= afio_exticr_extiX_pY;
+
+  /* Interrupt is masked, now */
+  EXTI->IMR &= ~pin_config;
+
+  /* Configure which edge is detected */
+  if (rising_edge)
+    EXTI->RTSR |= pin_config;
+  else
+    EXTI->FTSR |= pin_config;
+}
+
+void
+ackbtn_enable (void)
+{
+  EXTI->PR |= pin_config;	/* Clear pending interrupt */
+  EXTI->IMR |= pin_config;	/* Enable interrupt clearing the mask */
+}
+
+void
+ackbtn_disable (void)
+{
+  EXTI->IMR &= ~pin_config;	/* Disable interrupt having the mask */
+  EXTI->PR |= pin_config;	/* Clear pending interrupt */
+}

contrib/ackbtn.h

@@ -0,0 +1,3 @@
+void ackbtn_init (chopstx_intr_t *intr);
+void ackbtn_enable (void);
+void ackbtn_disable (void);

contrib/adc-mkl27z.c

@@ -295,19 +295,20 @@ adc_stop (void)
 int
 adc_wait_completion (void)
 {
-  struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&adc_intr };
   int i;
 
   while (1)
     {
       /* Wait DMA completion */
-      chopstx_poll (NULL, 1, pd_array);
+      chopstx_intr_wait (&adc_intr);
 
       DMA0->DSR_BCR = (1 << 24);
       DMA1->DSR_BCR = (1 << 24);
 
       adc_stop_conversion ();
 
+      chopstx_intr_done (&adc_intr);
+
       for (i = 0; i < adc.count; i++)
 	*adc.p++ = (uint8_t)adc.buf[i];
 

contrib/adc-stm32f103.c

@@ -3,7 +3,7 @@
  *                   In this ADC driver, there are NeuG specific parts.
  *                   You need to modify to use this as generic ADC driver.
  *
- * Copyright (C) 2011, 2012, 2013, 2015, 2016
+ * Copyright (C) 2011, 2012, 2013, 2015, 2016, 2017, 2018
  *               Free Software Initiative of Japan
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -32,9 +32,10 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <chopstx.h>
-#include <mcu/stm32.h>
 #include <mcu/stm32f103.h>
 #include "adc.h"
+#include "board.h"
+#include "sys.h"
 
 #define STM32_ADC_ADC1_DMA_PRIORITY         2
 
@@ -47,6 +48,7 @@
 #define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)
 #define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)
 #define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)
+#define ADC_SMPR2_SMP_AN8(n)    ((n) << 24)
 #define ADC_SMPR2_SMP_AN9(n)    ((n) << 27)
 
 #define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
@@ -61,6 +63,7 @@
 #define ADC_CHANNEL_IN0         0
 #define ADC_CHANNEL_IN1         1
 #define ADC_CHANNEL_IN2         2
+#define ADC_CHANNEL_IN8         8
 #define ADC_CHANNEL_IN9         9
 #define ADC_CHANNEL_IN10        10
 #define ADC_CHANNEL_IN11        11
@@ -68,7 +71,9 @@
 #define ADC_CHANNEL_VREFINT     17
 
 #define DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
+#ifndef MCU_STM32F1_GD32F1
 #define DELIBARATELY_DO_IT_WRONG_START_STOP
+#endif
 
 #ifdef DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
 #define ADC_SAMPLE_VREF ADC_SAMPLE_1P5
@@ -113,6 +118,8 @@ adc_init (void)
 
   ADC1->CR1 = 0;
   ADC1->CR2 = ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
+
   ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
   while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
     ;
@@ -123,6 +130,8 @@ adc_init (void)
 
   ADC2->CR1 = 0;
   ADC2->CR2 = ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
+
   ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
   while ((ADC2->CR2 & ADC_CR2_RSTCAL) != 0)
     ;
@@ -136,15 +145,13 @@ adc_init (void)
   return 0;
 }
 
-#include "board.h"
-#include "sys.h"
-
 static void
 get_adc_config (uint32_t config[4])
 {
   config[2] = ADC_SQR1_NUM_CH(2);
   switch (SYS_BOARD_ID)
     {
+    case BOARD_ID_FST_01G:
     case BOARD_ID_FST_01:
       config[0] = 0;
       config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
@@ -170,14 +177,22 @@ get_adc_config (uint32_t config[4])
 		| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2);
       break;
 
+    case BOARD_ID_ST_NUCLEO_F103:
+      config[0] = 0;
+      config[1] = ADC_SMPR2_SMP_AN8(ADC_SAMPLE_1P5)
+		| ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5);
+      config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN8)
+		| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9);
+      break;
+
     case BOARD_ID_CQ_STARM:
     case BOARD_ID_FST_01_00:
     case BOARD_ID_MAPLE_MINI:
     case BOARD_ID_STM32_PRIMER2:
     case BOARD_ID_STM8S_DISCOVERY:
     case BOARD_ID_ST_DONGLE:
-    case BOARD_ID_ST_NUCLEO_F103:
     case BOARD_ID_NITROKEY_START:
+    case BOARD_ID_FST_01SZ:
     default:
       config[0] = 0;
       config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
@@ -203,24 +218,26 @@ adc_start (void)
 
   RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
 
-  ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
-	       | ADC_CR1_SCAN);
-  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
-	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
   ADC1->SMPR1 = NEUG_ADC_SETTING1_SMPR1;
   ADC1->SMPR2 = NEUG_ADC_SETTING1_SMPR2;
   ADC1->SQR1 = ADC_SQR1_NUM_CH(NEUG_ADC_SETTING1_NUM_CHANNELS);
   ADC1->SQR2 = 0;
   ADC1->SQR3 = NEUG_ADC_SETTING1_SQR3;
-
-  ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+  ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
 	       | ADC_CR1_SCAN);
-  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+  chopstx_usec_wait (1000);
+
   ADC2->SMPR1 = config[0];
   ADC2->SMPR2 = config[1];
   ADC2->SQR1 = config[2];
   ADC2->SQR2 = 0;
   ADC2->SQR3 = config[3];
+  ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+	       | ADC_CR1_SCAN);
+  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
 
 #ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
   /*
@@ -299,11 +316,10 @@ int
 adc_wait_completion (void)
 {
   uint32_t flags;
-  struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&adc_intr };
 
   while (1)
     {
-      chopstx_poll (NULL, 1, pd_array);
+      chopstx_intr_wait (&adc_intr);
       flags = DMA1->ISR & STM32_DMA_ISR_MASK; /* Channel 1 interrupt cause.  */
       /*
        * Clear interrupt cause of channel 1.
@@ -312,6 +328,7 @@ adc_wait_completion (void)
        * and TEIF.
        */
       DMA1->IFCR = (flags & ~1);
+      chopstx_intr_done (&adc_intr);
 
       if ((flags & STM32_DMA_ISR_TEIF) != 0)  /* DMA errors  */
 	{

contrib/usart-stm32f103.c

@@ -0,0 +1,630 @@
+/*
+ * usart-stm32.c - USART driver for STM32F103 (USART2 and USART3)
+ *
+ * Copyright (C) 2017  g10 Code GmbH
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <chopstx.h>
+#include <mcu/stm32.h>
+#include <contrib/usart.h>
+
+struct USART {
+  volatile uint32_t SR;
+  volatile uint32_t DR;
+  volatile uint32_t BRR;
+  volatile uint32_t CR1;
+  volatile uint32_t CR2;
+  volatile uint32_t CR3;
+  volatile uint32_t GTPR;
+};
+
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+static struct USART *const USART2 = (struct USART *)USART2_BASE;
+static struct USART *const USART3 = (struct USART *)USART3_BASE;
+
+#define USART_SR_CTS	(1 << 9)
+#define USART_SR_LBD	(1 << 8)
+#define USART_SR_TXE	(1 << 7)
+#define USART_SR_TC	(1 << 6)
+#define USART_SR_RXNE	(1 << 5)
+#define USART_SR_IDLE	(1 << 4)
+#define USART_SR_ORE	(1 << 3)
+#define USART_SR_NE	(1 << 2)
+#define USART_SR_FE	(1 << 1)
+#define USART_SR_PE	(1 << 0)
+
+
+#define USART_CR1_UE		(1 << 13)
+#define USART_CR1_M		(1 << 12)
+#define USART_CR1_WAKE		(1 << 11)
+#define USART_CR1_PCE		(1 << 10)
+#define USART_CR1_PS		(1 <<  9)
+#define USART_CR1_PEIE		(1 <<  8)
+#define USART_CR1_TXEIE		(1 <<  7)
+#define USART_CR1_TCIE		(1 <<  6)
+#define USART_CR1_RXNEIE	(1 <<  5)
+#define USART_CR1_IDLEIE	(1 <<  4)
+#define USART_CR1_TE		(1 <<  3)
+#define USART_CR1_RE		(1 <<  2)
+#define USART_CR1_RWU		(1 <<  1)
+#define USART_CR1_SBK		(1 <<  0)
+
+
+static struct USART *
+get_usart_dev (uint8_t dev_no)
+{
+  if (dev_no == 2)
+    return USART2;
+  else if (dev_no == 3)
+    return USART3;
+
+  return NULL;
+}
+
+/* We assume 36MHz f_PCLK */
+struct brr_setting {
+  uint8_t baud_spec;
+  uint16_t brr_value;
+};
+#define NUM_BAUD (int)(sizeof (brr_table) / sizeof (struct brr_setting))
+
+static const struct brr_setting brr_table[] = {
+  { B600,    (3750 << 4)},
+  { B1200,   (1875 << 4)},
+  { B2400,   ( 937 << 4)|8},
+  { B9600,   ( 234 << 4)|6},
+  { B19200,  ( 117 << 4)|3},
+  { B57600,  (  39 << 4)|1},
+  { B115200, (  19 << 4)|8},
+  { B230400, (   9 << 4)|12},
+  { B460800, (   4 << 4)|14},
+  { B921600, (   2 << 4)|7},
+};
+
+static void *usart_main (void *arg);
+
+static struct usart_stat usart2_stat;
+static struct usart_stat usart3_stat;
+
+int
+usart_config (uint8_t dev_no, uint32_t config_bits)
+{
+  struct USART *USARTx = get_usart_dev (dev_no);
+  uint8_t baud_spec = (config_bits & MASK_BAUD);
+  int i;
+  uint32_t cr1_config = (USART_CR1_UE | USART_CR1_RXNEIE
+			 | USART_CR1_TE | USART_CR1_RE);
+				/* TXEIE will be enabled when putting char */
+				/* No CTSIE, PEIE, TCIE, IDLEIE, LBDIE */
+  if (USARTx == NULL)
+    return -1;
+
+  /* Disable USART before configure.  */
+  USARTx->CR1 &= ~USART_CR1_UE;
+
+  if (((config_bits & MASK_CS) == CS7 && (config_bits & PARENB))
+      || ((config_bits & MASK_CS) == CS8 && (config_bits & PARENB) == 0))
+    cr1_config &= ~USART_CR1_M;
+  else if ((config_bits & MASK_CS) == CS8)
+    cr1_config |=  USART_CR1_M;
+  else
+    return -1;
+
+  if ((config_bits & PARENB) == 0)
+    cr1_config &= ~USART_CR1_PCE;
+  else
+    cr1_config |=  USART_CR1_PCE;
+
+  if ((config_bits & PARODD) == 0)
+    cr1_config &= ~USART_CR1_PS;
+  else
+    cr1_config |=  USART_CR1_PS;
+
+  if ((config_bits & MASK_STOP) == STOP0B5)
+    USARTx->CR2 = (0x1 << 12);
+  else if ((config_bits & MASK_STOP) == STOP1B)
+    USARTx->CR2 = (0x0 << 12);
+  else if ((config_bits & MASK_STOP) == STOP1B5)
+    USARTx->CR2 = (0x3 << 12);
+  else /* if ((config_bits & MASK_STOP) == STOP2B) */
+    USARTx->CR2 = (0x2 << 12);
+
+  for (i = 0; i < NUM_BAUD; i++)
+    if (brr_table[i].baud_spec == baud_spec)
+      break;
+
+  if (i >= NUM_BAUD)
+    return -1;
+
+  USARTx->BRR = brr_table[i].brr_value;
+
+  if ((config_bits & MASK_FLOW))
+    USARTx->CR3 = (1 << 9) | (1 << 8);
+  else
+    USARTx->CR3 = 0;
+
+  USARTx->CR1 = cr1_config;
+  return 0;
+}
+
+static int (*ss_notify_callback) (uint8_t dev_no, uint16_t notify_bits);
+
+void
+usart_init (uint16_t prio, uintptr_t stack_addr, size_t stack_size,
+	    int (*cb) (uint8_t dev_no, uint16_t notify_bits))
+{
+  ss_notify_callback = cb;
+  usart2_stat.dev_no = 2;
+  usart3_stat.dev_no = 3;
+
+  /* Enable USART2 and USART3 clocks, and strobe reset.  */
+  RCC->APB1ENR |= ((1 << 18) | (1 << 17));
+  RCC->APB1RSTR = ((1 << 18) | (1 << 17));
+  RCC->APB1RSTR = 0;
+
+  usart_config (2, B115200 | CS8 | STOP1B);
+  usart_config (3, B115200 | CS8 | STOP1B);
+  chopstx_create (prio, stack_addr, stack_size, usart_main, NULL);
+}
+
+/*
+ * Ring buffer
+ */
+#define MAX_RB_BUF 1024
+
+struct rb {
+  uint8_t *buf;
+  chopstx_mutex_t m;
+  chopstx_cond_t data_available;
+  chopstx_cond_t space_available;
+  uint32_t head  :10;
+  uint32_t tail  :10;
+  uint32_t size  :10;
+  uint32_t full  : 1;
+  uint32_t empty : 1;
+};
+
+/*
+ * Note: size = 1024 can still work, regardless of the limit of 10-bit.
+ */
+static void
+rb_init (struct rb *rb, uint8_t *p, uint16_t size)
+{
+  rb->buf = p;
+  rb->size = size;
+  chopstx_mutex_init (&rb->m);
+  chopstx_cond_init (&rb->data_available);
+  chopstx_cond_init (&rb->space_available);
+  rb->head = rb->tail = 0;
+  rb->full = 0;
+  rb->empty = 1;
+}
+
+static void
+rb_add (struct rb *rb, uint8_t v)
+{
+  rb->buf[rb->tail++] = v;
+  if (rb->tail == rb->size)
+    rb->tail = 0;
+  if (rb->tail == rb->head)
+    rb->full = 1;
+  rb->empty = 0;
+}
+
+static uint8_t
+rb_del (struct rb *rb)
+{
+  uint32_t v = rb->buf[rb->head++];
+
+  if (rb->head == rb->size)
+    rb->head = 0;
+  if (rb->head == rb->tail)
+    rb->empty = 1;
+  rb->full = 0;
+
+  return v;
+}
+
+/*
+ * Application: consumer
+ * Hardware:    generator
+ */
+static int
+rb_ll_put (struct rb *rb, uint8_t v)
+{
+  int r;
+
+  chopstx_mutex_lock (&rb->m);
+  if (rb->full)
+    r = -1;
+  else
+    {
+      r = 0;
+      rb_add (rb, v);
+      chopstx_cond_signal (&rb->data_available);
+    }
+  chopstx_mutex_unlock (&rb->m);
+  return r;
+}
+
+/*
+ * Application: generator
+ * Hardware:    consumer
+ */
+static int
+rb_ll_get (struct rb *rb)
+{
+  int r;
+
+  chopstx_mutex_lock (&rb->m);
+  if (rb->empty)
+    r = -1;
+  else
+    {
+      r = rb_del (rb);
+      chopstx_cond_signal (&rb->space_available);
+    }
+  chopstx_mutex_unlock (&rb->m);
+  return r;
+}
+
+static void
+rb_ll_flush (struct rb *rb)
+{
+  chopstx_mutex_lock (&rb->m);
+  while (!rb->empty)
+    rb_del (rb);
+  chopstx_cond_signal (&rb->space_available);
+  chopstx_mutex_unlock (&rb->m);
+}
+
+/*
+ * Application: consumer
+ * Hardware:    generator
+ */
+static int
+rb_read (struct rb *rb, uint8_t *buf, uint16_t buflen)
+{
+  int i = 0;
+
+  chopstx_mutex_lock (&rb->m);
+  while (rb->empty)
+    chopstx_cond_wait (&rb->data_available, &rb->m);
+
+  while (i < buflen)
+    {
+      buf[i++] = rb_del (rb);
+      if (rb->empty)
+	break;
+    }
+  chopstx_cond_signal (&rb->space_available);
+  chopstx_mutex_unlock (&rb->m);
+
+  return i;
+}
+
+/*
+ * Application: generator
+ * Hardware:    consumer
+ */
+static void
+rb_write (struct rb *rb, uint8_t *buf, uint16_t buflen)
+{
+  int i = 0;
+
+  chopstx_mutex_lock (&rb->m);
+
+  do
+    {
+      while (rb->full)
+	chopstx_cond_wait (&rb->space_available, &rb->m);
+
+      while (i < buflen)
+	{
+	  rb_add (rb, buf[i++]);
+	  if (rb->full)
+	    {
+	      chopstx_cond_signal (&rb->data_available);
+	      break;
+	    }
+	}
+    }
+  while (i < buflen);
+
+  if (i)
+    chopstx_cond_signal (&rb->data_available);
+  chopstx_mutex_unlock (&rb->m);
+}
+
+static int
+rb_empty_check (void *arg)
+{
+  struct rb *rb = arg;
+  return rb->empty == 0;
+}
+
+static void
+rb_get_prepare_poll (struct rb *rb, chopstx_poll_cond_t *poll_desc)
+{
+  poll_desc->type  = CHOPSTX_POLL_COND;
+  poll_desc->ready = 0;
+  poll_desc->cond  = &rb->data_available;
+  poll_desc->mutex = &rb->m;
+  poll_desc->check = rb_empty_check;
+  poll_desc->arg   = rb;
+}
+
+#define INTR_REQ_USART2 38
+#define INTR_REQ_USART3 39
+
+static uint8_t buf_usart2_rb_a2h[256];
+static uint8_t buf_usart2_rb_h2a[512];
+static uint8_t buf_usart3_rb_a2h[256];
+static uint8_t buf_usart3_rb_h2a[512];
+
+static struct chx_intr usart2_intr;
+static struct chx_intr usart3_intr;
+
+static struct rb usart2_rb_a2h;
+static struct rb usart2_rb_h2a;
+static struct rb usart3_rb_a2h;
+static struct rb usart3_rb_h2a;
+
+static chopstx_poll_cond_t usart2_app_write_event;
+static chopstx_poll_cond_t usart3_app_write_event;
+
+static struct chx_poll_head *usart_poll[4];
+
+/* Global variables so that it can be easier to debug.  */
+static int usart2_tx_ready;
+static int usart3_tx_ready;
+
+#define UART_STATE_BITMAP_RX_CARRIER (1 << 0)
+#define UART_STATE_BITMAP_TX_CARRIER (1 << 1)
+#define UART_STATE_BITMAP_BREAK      (1 << 2)
+#define UART_STATE_BITMAP_RINGSIGNAL (1 << 3)
+#define UART_STATE_BITMAP_FRAMING    (1 << 4)
+#define UART_STATE_BITMAP_PARITY     (1 << 5)
+#define UART_STATE_BITMAP_OVERRUN    (1 << 6)
+
+static int
+handle_intr (struct USART *USARTx, struct rb *rb2a, struct usart_stat *stat)
+{
+  int tx_ready = 0;
+  uint32_t r = USARTx->SR;
+  int notify_bits = 0;
+
+  if ((r & USART_SR_TXE))
+    {
+      tx_ready = 1;
+      USARTx->CR1 &= ~USART_CR1_TXEIE;
+    }
+
+  if ((r & USART_SR_RXNE))
+    {
+      uint32_t data = USARTx->DR;
+
+      /* DR register should be accessed even if data is not used.
+       * Its read-access has side effect of clearing error flags.
+       */
+      asm volatile ("" : : "r" (data) : "memory");
+
+      if ((r & USART_SR_NE))
+	stat->err_rx_noise++;
+      else if ((r & USART_SR_FE))
+	{
+	  /* NOTE: Noway to distinguish framing error and break  */
+
+	  stat->rx_break++;
+	  notify_bits |= UART_STATE_BITMAP_BREAK;
+	}
+      else if ((r & USART_SR_PE))
+	{
+	  stat->err_rx_parity++;
+	  notify_bits |= UART_STATE_BITMAP_PARITY;
+	}
+      else
+	{
+	  if ((r & USART_SR_ORE))
+	    {
+	      stat->err_rx_overrun++;
+	      notify_bits |= UART_STATE_BITMAP_OVERRUN;
+	    }
+
+	  /* XXX: if CS is 7-bit, mask it, or else parity bit in upper layer */
+	  if (rb_ll_put (rb2a, (data & 0xff)) < 0)
+	    stat->err_rx_overflow++;
+	  else
+	    stat->rx++;
+	}
+    }
+  else if ((r & USART_SR_ORE))
+    {				/* Clear ORE */
+      uint32_t data = USARTx->DR;
+      asm volatile ("" : : "r" (data) : "memory");
+      stat->err_rx_overrun++;
+      notify_bits |= UART_STATE_BITMAP_OVERRUN;
+    }
+
+  if (notify_bits)
+    {
+      if ((*ss_notify_callback) (stat->dev_no, notify_bits))
+	stat->err_notify_overflow++;
+    }
+
+  return tx_ready;
+}
+
+static int
+handle_tx_ready (struct USART *USARTx, struct rb *rb2h,
+		 struct usart_stat *stat)
+{
+  int tx_ready = 1;
+  int c = rb_ll_get (rb2h);
+
+  if (c >= 0)
+    {
+      uint32_t r;
+
+      USARTx->DR = (c & 0xff);
+      stat->tx++;
+      r = USARTx->SR;
+      if ((r & USART_SR_TXE) == 0)
+	{
+	  tx_ready = 0;
+	  USARTx->CR1 |= USART_CR1_TXEIE;
+	}
+    }
+
+  return tx_ready;
+}
+
+static void *
+usart_main (void *arg)
+{
+  (void)arg;
+
+  usart2_tx_ready = 1;
+  usart3_tx_ready = 1;
+
+  chopstx_claim_irq (&usart2_intr, INTR_REQ_USART2);
+  chopstx_claim_irq (&usart3_intr, INTR_REQ_USART3);
+
+  rb_init (&usart2_rb_a2h, buf_usart2_rb_a2h, sizeof buf_usart2_rb_a2h);
+  rb_init (&usart2_rb_h2a, buf_usart2_rb_h2a, sizeof buf_usart2_rb_h2a);
+  rb_init (&usart3_rb_a2h, buf_usart3_rb_a2h, sizeof buf_usart3_rb_a2h);
+  rb_init (&usart3_rb_h2a, buf_usart3_rb_h2a, sizeof buf_usart3_rb_h2a);
+
+  rb_get_prepare_poll (&usart2_rb_a2h, &usart2_app_write_event);
+  rb_get_prepare_poll (&usart3_rb_a2h, &usart3_app_write_event);
+
+  while (1)
+    {
+      int n = 0;
+
+      usart_poll[n++] = (struct chx_poll_head *)&usart2_intr;
+      usart_poll[n++] = (struct chx_poll_head *)&usart3_intr;
+      if (usart2_tx_ready)
+	usart_poll[n++] = (struct chx_poll_head *)&usart2_app_write_event;
+      else
+	usart2_app_write_event.ready = 0;
+      if (usart3_tx_ready)
+	usart_poll[n++] = (struct chx_poll_head *)&usart3_app_write_event;
+      else
+	usart3_app_write_event.ready = 0;
+
+      chopstx_poll (NULL, n, usart_poll);
+
+      if (usart2_intr.ready)
+	{
+	  usart2_tx_ready = handle_intr (USART2, &usart2_rb_h2a, &usart2_stat);
+	  chopstx_intr_done (&usart2_intr);
+	}
+
+      if (usart3_intr.ready)
+	{
+	  usart3_tx_ready = handle_intr (USART3, &usart3_rb_h2a, &usart3_stat);
+	  chopstx_intr_done (&usart3_intr);
+	}
+
+      if (usart2_tx_ready && usart2_app_write_event.ready)
+	usart2_tx_ready = handle_tx_ready (USART2,
+					   &usart2_rb_a2h, &usart2_stat);
+
+      if (usart3_tx_ready && usart3_app_write_event.ready)
+	usart3_tx_ready = handle_tx_ready (USART3,
+					   &usart3_rb_a2h, &usart3_stat);
+    }
+
+  return NULL;
+}
+
+int
+usart_read (uint8_t dev_no, char *buf, uint16_t buflen)
+{
+  struct rb *rb;
+
+  if (dev_no == 2)
+    rb = &usart2_rb_h2a;
+  else if (dev_no == 3)
+    rb = &usart3_rb_h2a;
+  else
+    return -1;
+
+  if (buf == NULL && buflen == 0)
+    {
+      rb_ll_flush (rb);
+      return 0;
+    }
+  else
+    return rb_read (rb, (uint8_t *)buf, buflen);
+}
+
+int
+usart_write (uint8_t dev_no, char *buf, uint16_t buflen)
+{
+  struct rb *rb;
+
+  if (dev_no == 2)
+    rb = &usart2_rb_a2h;
+  else if (dev_no == 3)
+    rb = &usart3_rb_a2h;
+  else
+    return -1;
+
+  if (buf == NULL && buflen == 0)
+    rb_ll_flush (rb);
+  else
+    rb_write (rb, (uint8_t *)buf, buflen);
+  return 0;
+}
+
+const struct usart_stat *
+usart_stat (uint8_t dev_no)
+{
+  if (dev_no == 2)
+    return &usart2_stat;
+  else if (dev_no == 3)
+    return &usart3_stat;
+  else
+    return NULL;
+}
+
+int
+usart_send_break (uint8_t dev_no)
+{
+  struct USART *USARTx = get_usart_dev (dev_no);
+  if (USARTx == NULL)
+    return -1;
+
+  if ((USARTx->CR1 & 0x01))
+    return 1;	/* Busy sending break, which was requested before.  */
+
+  USARTx->CR1 |= 0x01;
+  return 0;
+}

contrib/usart.h

@@ -0,0 +1,66 @@
+#define B0       0 /* POSIX to hang up */
+
+/* POSIX supports B75 to B300 */
+#define B600        16
+#define B1200       17
+#define B2400       19
+#define B9600       21
+#define B19200      22
+#define B57600      24
+#define B115200     25
+#define B230400     26
+#define B460800     27
+#define B921600     28
+#define MASK_BAUD 0x3f
+
+/* POSIX supports 5, 6.  USB suppots 16 */
+#define CS7       (2 << 6)
+#define CS8       (3 << 6)
+#define MASK_CS   (0x7 << 6)
+
+#define STOP0B5	  (0 << 9) /* USART Hardware only */
+#define STOP1B	  (1 << 9) /* USB, POSIX  */
+#define STOP1B5	  (2 << 9) /* USB         */
+#define STOP2B	  (3 << 9) /* USB, POSIX  */
+#define MASK_STOP (0x3 << 9)
+
+#define PARENB    (1 << 11)
+#define PARODD    (2 << 11)
+#define MASK_PAR  (0x7 << 11)
+/* USB  0: none, 1: odd, 2: even, 3: mark, 4: space */
+
+#define CRTSCTS   (1 << 14)
+#define MASK_FLOW (0x1 << 14)
+
+/*
+BAUD_BITS 6
+CS_BITS   3
+STOP_BITS 2
+PAR_BITS  3
+*/
+/* USB: SET_CONTROL_LINE_STATE
+   DTR RTS */
+/* USB: SERIAL_STATE
+   DSR DCD RI */
+
+struct usart_stat {
+  uint8_t dev_no;
+
+  uint32_t tx;
+  uint32_t rx;
+  uint32_t rx_break;
+  uint32_t err_notify_overflow;
+  uint32_t err_rx_overflow;	/* software side */
+  uint32_t err_rx_overrun;	/* hardware side */
+  uint32_t err_rx_noise;
+  uint32_t err_rx_parity;
+};
+
+
+void usart_init (uint16_t prio, uintptr_t stack_addr, size_t stack_size,
+		 int (*ss_notify_callback) (uint8_t dev_no, uint16_t notify_bits));
+int usart_config (uint8_t dev_no, uint32_t config_bits);
+int usart_read (uint8_t dev_no, char *buf, uint16_t buflen);
+int usart_write (uint8_t dev_no, char *buf, uint16_t buflen);
+const struct usart_stat *usart_stat (uint8_t dev_no);
+int usart_send_break (uint8_t dev_no);

doc/chopstx-api.texi

@@ -107,6 +107,14 @@ Claim interrupt @var{intr} with @var{irq_num}
 Wait for the interrupt @var{intr} to be occured.
 @end deftypefun
 
+@subheading chopstx_intr_done
+@anchor{chopstx_intr_done}
+@deftypefun {void} {chopstx_intr_done} (chopstx_intr_t * @var{intr})
+@var{intr}: Pointer to INTR structure
+
+Finish for the interrupt @var{intr} occurred.
+@end deftypefun
+
 @subheading chopstx_cleanup_push
 @anchor{chopstx_cleanup_push}
 @deftypefun {void} {chopstx_cleanup_push} (struct chx_cleanup * @var{clp})

doc/chopstx.texi

@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
 @c %**start of header
 @setfilename chopstx.info
-@set VERSION 1.6
+@set VERSION 1.10
 @settitle Chopstx Reference Manual
 @c Unify some of the indices.
 @syncodeindex tp fn
@@ -11,7 +11,7 @@
 This manual is for Chopstx (version @value{VERSION}).
 
 @noindent
-Copyright @copyright{} 2013, 2015, 2016, 2017 Flying Stone Technology @*
+Copyright @copyright{} 2013, 2015, 2016, 2017, 2018 Flying Stone Technology @*
 
 @quotation
 Permission is granted to copy, distribute and/or modify this document
@@ -60,7 +60,9 @@ section entitled ``Copying''.
 @menu
 * Introduction::                 What is Chopstx.
 * Threads and only Threads::     Threads and only Threads.
-* Note: Use of sleep mode::      Use it carefully.
+* Poll or Pole::                 Poll or Pole.
+* Note (Use of sleep mode)::     Use it carefully.
+* Compile-time macro::           Macro to be defined.
 * API::                          API.
 
 Appendix
@@ -87,14 +89,19 @@ Indexes
 
 Chopstx is an RT thread library for ARM Cortex-M0, Cortex-M0plus,
 Cortex-M3 and GNU/Linux emulation.  Specifically, it is used for
-STM32F030, MKL27Z, STM32F103 and as a command on GNU/Linux.
+STM32F030, MKL27Z, STM32F103, GD32F103 and as a command on GNU/Linux.
 
 While most RTOSes come with many features, drivers, and stacks,
-Chopstx just offers a RT thread library.
+Chopstx just offers an RT thread library.
 
 With Chopstx, interrupt handling is also done by a thread.  This
 enables coherent code for ease of maintenance.
 
+While threads are important, we don't need more threads than
+necessary.  Chopstx provides a feature of poll, so that we can
+minimize use of threads.
+
+
 @node Threads and only Threads
 @chapter Threads and only Threads
 
@@ -129,8 +136,17 @@ support more performance (frequency).  In general, such an example is
 best suited by hardware (not software).
 
 
-@node Note: Use of sleep mode
-@chapter Note: Use of sleep mode
+@node Poll or Pole
+@chapter Poll or Pole
+Chopstx provides the @code{chopstx_poll} function to wait on multiple events.
+
+Using @code{chopstx_poll}, we can write an application by event-driven
+programming style, with minimum number of threads, avoiding
+complicated dependency between threads.
+
+
+@node Note (Use of sleep mode)
+@chapter Note (Use of sleep mode)
 
 Calling the chopstx_conf_idle function (> 0) to allow the idle thread
 going to sleep.  MCU will be in sleep mode when no threads are
@@ -142,6 +158,21 @@ program carefully.  Enabling sleep, it may result a bricked board; A
 board with no RESET pin cannot be debugged by JTAG/SWD.
 
 
+@node Compile-time macro
+@chapter Compile-time macro
+
+Compiling Chopstx, a macro MHZ should be supplied.
+
+For example, when using the makefile rule of chopstx/rules.mk, please
+define the make variable DEFS with -DMHZ=72 before inclusion of the rule file.
+
+@subheading MHZ
+@anchor{MHZ}
+@defmac {MHZ}
+Running CPU clock in MHz.  Used for chopstx_usec_wait.
+@end defmac
+
+
 @node API
 @chapter API
 

example-cdc-gnu-linux/usb-cdc.c

@@ -708,6 +708,7 @@ tty_main (void *arg)
 	   *        
 	   */
 	  e = usb_lld_event_handler (&dev);
+	  chopstx_intr_done (&usb_intr);
 	  ep_num = USB_EVENT_ENDP (e);
 
 	  if (ep_num != 0)

example-cdc/Makefile

@@ -10,6 +10,7 @@ CHIP=stm32f103
 
 USE_SYS = yes
 USE_USB = yes
+ENABLE_OUTPUT_HEX=yes
 
 ###################################
 CROSS = arm-none-eabi-
@@ -19,7 +20,7 @@ OBJCOPY   = $(CROSS)objcopy
 
 MCU   = cortex-m3
 CWARN = -Wall -Wextra -Wstrict-prototypes
-DEFS  = -DUSE_SYS3 -DFREE_STANDING
+DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=72
 OPT   = -O3 -Os -g
 LIBS  =
 

example-cdc/usb-cdc.c

@@ -719,6 +719,7 @@ tty_main (void *arg)
 	   *        
 	   */
 	  e = usb_lld_event_handler (&dev);
+	  chopstx_intr_done (&usb_intr);
 	  ep_num = USB_EVENT_ENDP (e);
 
 	  if (ep_num != 0)

example-fraucheky/main.c

@@ -18,6 +18,7 @@ extern void EP6_OUT_Callback (uint16_t len);
 
 #define MSC_MASS_STORAGE_RESET_COMMAND 0xFF
 extern int fraucheky_enabled (void);
+extern void fraucheky_init (void);
 extern void fraucheky_main (void);
 
 extern void fraucheky_setup_endpoints_for_interface (struct usb_dev *dev, int stop);
@@ -41,10 +42,6 @@ usb_device_reset (struct usb_dev *dev)
   /* Initialize Endpoint 0.  */
   usb_lld_setup_endp (dev, ENDP0, 1, 1);
 
-  /* Stop the interface */
-  for (i = 0; i < NUM_INTERFACES; i++)
-    setup_endpoints_for_interface (dev, i, 1);
-
   /* Notify upper layer.  */
   chopstx_mutex_lock (&usb_mtx);
   bDeviceState = USB_DEVICE_STATE_ATTACHED;
@@ -188,6 +185,7 @@ usb_main (void *arg)
 
 	event_handle:
 	  e = usb_lld_event_handler (&dev);
+	  chopstx_intr_done (&interrupt);
 	  ep_num = USB_EVENT_ENDP (e);
 
 	  if (ep_num != 0)
@@ -307,6 +305,7 @@ main (int argc, char **argv)
   bDeviceState = USB_DEVICE_STATE_UNCONNECTED;
   usb_thd = chopstx_create (PRIO_USB, STACK_ADDR_USB, STACK_SIZE_USB,
 			    usb_main, NULL);
+  fraucheky_init ();
   while (bDeviceState != USB_DEVICE_STATE_CONFIGURED)
     chopstx_usec_wait (250*1000);
   fraucheky_main ();

example-fs-bb48/touch.c

@@ -74,6 +74,7 @@ touch_get (void)
   TPM1->SC = 0;
   TPM1->CNT = 0xffff;	   /* Writing causes reset of the counter.  */
 
+  chopstx_intr_done (&tpm1_intr);
   return v;
 }
 

example-fs-bb48/usb-cdc.c

@@ -708,6 +708,7 @@ tty_main (void *arg)
 	   *        
 	   */
 	  e = usb_lld_event_handler (&dev);
+	  chopstx_intr_done (&usb_intr);
 	  ep_num = USB_EVENT_ENDP (e);
 
 	  if (ep_num != 0)

example-fsm-55/debian-logo.c

@@ -7,7 +7,7 @@
 static uint8_t main_finished;
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
 #define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)

example-fsm-55/hh.c

@@ -7,7 +7,7 @@
 static uint8_t main_finished;
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
 #define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)

example-fsm-55/hiroshi-ayumi.c

@@ -6,7 +6,7 @@
 #include "board.h"
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
 #define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)

example-primer2/lcd.c

@@ -6,7 +6,7 @@
 #include "board.h"
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 
 struct GPIO {

example-primer2/primer2-switches.c

@@ -4,7 +4,7 @@
 #include "board.h"
 
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
+#define APB1PERIPH_BASE  PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 
 struct GPIO {

example-primer2/primer2-ts.c

@@ -107,6 +107,10 @@ void adc3_conversion (uint32_t *result)
   /* Stop conversion.  */
   ADC3->CR2 &= ~ADC_CR2_JSWSTART;
 
+#if USE_ADC3_INTR
+  chopstx_intr_done (&adc3_intr);
+#endif
+
   return;
 }
 

example-usb-serial/Makefile

@@ -0,0 +1,37 @@
+# Makefile for example application of Chopstx
+
+PROJECT = sample
+
+CHOPSTX = ..
+LDSCRIPT= sample.ld
+CSRC = sample.c usb-cdc.c
+
+CHIP=stm32f103
+
+USE_SYS = yes
+USE_USB = yes
+USE_USART = yes
+
+###################################
+CROSS = arm-none-eabi-
+CC   = $(CROSS)gcc
+LD   = $(CROSS)gcc
+OBJCOPY   = $(CROSS)objcopy
+
+MCU   = cortex-m3
+CWARN = -Wall -Wextra -Wstrict-prototypes
+DEFS  = -DUSE_SYS3 -DFREE_STANDING -DMHZ=72
+OPT   = -O3 -Os -g
+LIBS  =
+
+####################
+include ../rules.mk
+
+board.h:
+	@echo Please make a symbolic link \'board.h\' to a file in ../board;
+	@exit 1
+
+sys.c: board.h
+
+distclean: clean
+	rm -f board.h

example-usb-serial/README

@@ -0,0 +1,22 @@
+This is an application example using ST Nucleo F103 board.
+
+SB62 and SB63 should be soldered.
+ST-Link/V2 is disconnected (SB13 and SB14).
+
+NOTE:
+
+Using the USB CDC-ACM for serial communication is a kind of wrong,
+because it's designed for modem;  No way to control CTSRTS. 
+
+TIOCGICOUNT
+
+
+TODO:
+* Use of DMA for serial communication
+* RS-232 support: GPIO with DTR (out), DCD (in), DSR (in), RI (in)
+* serial config setting of CTSRTS?
+  By vendor specific control?
+* stats report control
+  By vendor specific control?
+* Half-duplex support
+* Support of other communication mode: smartcard, IrDA, etc.

example-usb-serial/board.h

@@ -0,0 +1 @@
+../board/board-st-nucleo-f103.h

example-usb-serial/cdc.h

@@ -0,0 +1,17 @@
+#define BUFSIZE 64
+
+struct cdc;
+
+void
+cdc_init (uint16_t prio, uintptr_t stack_addr, size_t stack_size,
+	  void (*sendbrk_callback) (uint8_t dev_no, uint16_t duration),
+	  void (*config_callback) (uint8_t dev_no,
+				   uint32_t bitrate, uint8_t format,
+				   uint8_t paritytype, uint8_t databits));
+void cdc_wait_configured (void);
+
+struct cdc *cdc_open (uint8_t num);
+void cdc_wait_connection (struct cdc *);
+int cdc_send (struct cdc *s, const char *buf, int count);
+int cdc_recv (struct cdc *s, char *buf, uint32_t *timeout);
+int cdc_ss_notify (struct cdc *s, uint16_t state_bits);

example-usb-serial/sample.c

@@ -0,0 +1,257 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <chopstx.h>
+#include <contrib/usart.h>
+
+#include <usb_lld.h>
+#include "cdc.h"
+
+/* For set_led */
+#include "board.h"
+#include "sys.h"
+
+static void *
+blk (void *arg)
+{
+  (void)arg;
+
+  while (1)
+    {
+      set_led (0);
+      chopstx_usec_wait (200*1000);
+      set_led (1);
+      chopstx_usec_wait (200*1000);
+    }
+
+  return NULL;
+}
+
+#define PRIO_USART     4
+#define PRIO_CDC2USART 3
+#define PRIO_USART2CDC 3
+#define PRIO_CDC       2
+
+#define STACK_MAIN
+#define STACK_PROCESS_1
+#define STACK_PROCESS_2
+#define STACK_PROCESS_3
+#define STACK_PROCESS_4
+#define STACK_PROCESS_5
+#define STACK_PROCESS_6
+#include "stack-def.h"
+#define STACK_ADDR_CDC ((uintptr_t)process1_base)
+#define STACK_SIZE_CDC (sizeof process1_base)
+
+#define STACK_ADDR_USART ((uint32_t)process2_base)
+#define STACK_SIZE_USART (sizeof process2_base)
+
+#define STACK_ADDR_CDC2USART0 ((uint32_t)process3_base)
+#define STACK_SIZE_CDC2USART0 (sizeof process3_base)
+
+#define STACK_ADDR_USART2CDC0 ((uint32_t)process4_base)
+#define STACK_SIZE_USART2CDC0 (sizeof process4_base)
+
+#define STACK_ADDR_CDC2USART1 ((uint32_t)process5_base)
+#define STACK_SIZE_CDC2USART1 (sizeof process5_base)
+
+#define STACK_ADDR_USART2CDC1 ((uint32_t)process6_base)
+#define STACK_SIZE_USART2CDC1 (sizeof process6_base)
+
+
+struct cdc_usart {
+  uint8_t dev_no;
+  struct cdc *cdc;
+};
+
+static void *
+usart_to_cdc_loop (void *arg)
+{
+  struct cdc_usart *cdc_usart = arg;
+
+  while (1)
+    {
+      char s[BUFSIZE];
+
+      cdc_wait_connection (cdc_usart->cdc);
+
+      /* Flush USART buffers */
+      usart_read (cdc_usart->dev_no, NULL, 0);
+      usart_write (cdc_usart->dev_no, NULL, 0);
+
+      chopstx_usec_wait (100*1000);
+
+      while (1)
+	{
+	  int size = usart_read (cdc_usart->dev_no, s, BUFSIZE);
+
+	  if (size > 0)
+	    {
+	      if (cdc_send (cdc_usart->cdc, s, size) < 0)
+		break;
+	    }
+	}
+    }
+
+  return NULL;
+}
+
+static void *
+cdc_to_usart_loop (void *arg)
+{
+  struct cdc_usart *cdc_usart = arg;
+
+  while (1)
+    {
+      char s[BUFSIZE];
+
+      cdc_wait_connection (cdc_usart->cdc);
+
+      /* Flush USART buffers */
+      usart_read (cdc_usart->dev_no, NULL, 0);
+      usart_write (cdc_usart->dev_no, NULL, 0);
+
+      chopstx_usec_wait (50*1000);
+
+      /* Send ZLP at the beginning.  */
+      cdc_send (cdc_usart->cdc, s, 0);
+
+      while (1)
+	{
+	  int size;
+	  uint32_t usec = 3000000;	/* 3.0 seconds */
+
+	  size = cdc_recv (cdc_usart->cdc, s, &usec);
+	  if (size < 0)
+	    break;
+
+	  if (size)
+	    usart_write (cdc_usart->dev_no, s, size);
+	}
+    }
+
+  return NULL;
+}
+
+static struct cdc_usart cdc_usart0;
+static struct cdc_usart cdc_usart1;
+
+static int
+ss_notify (uint8_t dev_no, uint16_t state_bits)
+{
+  struct cdc *s;
+
+  if (dev_no == cdc_usart0.dev_no)
+    s = cdc_usart0.cdc;
+  else if (dev_no == cdc_usart1.dev_no)
+    s = cdc_usart1.cdc;
+  else
+    return -1;
+
+  return cdc_ss_notify (s, state_bits);
+}
+
+static void
+send_break (uint8_t dev_no, uint16_t duration)
+{
+  (void)duration; 		/* Not supported by USART.  */
+  usart_send_break (dev_no);
+}
+
+static void
+setup_usart_config (uint8_t dev_no, uint32_t bitrate, uint8_t format,
+		    uint8_t paritytype, uint8_t databits)
+{
+  /* Check supported config(s) */
+  uint32_t config_bits;
+
+  if (bitrate == 9600)
+    config_bits = B9600;
+  else if (bitrate == 19200)
+    config_bits = B19200;
+  else if (bitrate == 57600)
+    config_bits = B57600;
+  else if (bitrate == 115200)
+    config_bits = B115200;
+  else
+    {
+      bitrate = 115200;
+      config_bits = B115200;
+    }
+
+  if (format == 0)
+    config_bits |= STOP1B;
+  else if (format == 1)
+    config_bits |= STOP1B5;
+  else if (format == 2)
+    config_bits |= STOP2B;
+  else
+    {
+      format = 0;
+      config_bits |= STOP1B;
+    }
+
+  if (paritytype == 0)
+    config_bits |= 0;
+  else if (paritytype == 1)
+    config_bits |= (PARENB | PARODD);
+  else if (paritytype == 2)
+    config_bits |= PARENB;
+  else
+    {
+      paritytype = 0;
+      config_bits |= 0;
+    }
+
+  if (databits == 7)
+    config_bits |= CS7;
+  else if (databits == 7)
+    config_bits |= CS8;
+  else
+    {
+      databits = 8;
+      config_bits |= CS8;
+    }
+
+  if (databits == 7 && paritytype == 0)
+    {
+      databits = 8;
+      config_bits &= ~MASK_CS;
+      config_bits |= CS8;
+    }
+
+  usart_config (dev_no, config_bits);
+}
+
+
+int
+main (int argc, const char *argv[])
+{
+  (void)argc;
+  (void)argv;
+
+  chopstx_usec_wait (200*1000);
+
+  cdc_init (PRIO_CDC, STACK_ADDR_CDC, STACK_SIZE_CDC,
+	    send_break, setup_usart_config);
+  cdc_wait_configured ();
+
+  usart_init (PRIO_USART, STACK_ADDR_USART, STACK_SIZE_USART, ss_notify);
+
+  cdc_usart0.cdc = cdc_open (0);
+  cdc_usart0.dev_no = 2;
+  cdc_usart1.cdc = cdc_open (1);
+  cdc_usart1.dev_no = 3;
+
+  chopstx_create (PRIO_USART2CDC, STACK_ADDR_USART2CDC0,
+		  STACK_SIZE_USART2CDC0, usart_to_cdc_loop, &cdc_usart0);
+  chopstx_create (PRIO_USART2CDC, STACK_ADDR_USART2CDC1,
+		  STACK_SIZE_USART2CDC1, usart_to_cdc_loop, &cdc_usart1);
+  chopstx_create (PRIO_CDC2USART, STACK_ADDR_CDC2USART0,
+		  STACK_SIZE_CDC2USART0, cdc_to_usart_loop, &cdc_usart0);
+  chopstx_create (PRIO_CDC2USART, STACK_ADDR_CDC2USART1,
+		  STACK_SIZE_CDC2USART1, cdc_to_usart_loop, &cdc_usart1);
+
+  blk (NULL);
+  return 0;
+}

example-usb-serial/sample.ld

@@ -0,0 +1,127 @@
+/*
+ * ST32F103 memory setup.
+ */
+
+MEMORY
+{
+    flash0 : org = 0x08000000, len = 4k
+    flash  : org = 0x08000000+0x1000, len = 60k
+    ram : org = 0x20000000, len = 20k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    .sys : ALIGN(4) SUBALIGN(4)
+    {
+	_sys = .;
+	KEEP(*(.vectors))
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys-*.o(.text)
+	build/sys-*.o(.text.*)
+	build/sys-*.o(.rodata)
+	build/sys-*.o(.rodata.*)
+	. = ALIGN(1024);
+	*(.sys.0)
+	*(.sys.1)
+	*(.sys.2)
+    } > flash0
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN (16);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .process_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        *(.process_stack.6)
+        *(.process_stack.5)
+        *(.process_stack.4)
+        *(.process_stack.3)
+        *(.process_stack.2)
+        *(.process_stack.1)
+        *(.process_stack.0)
+        . = ALIGN(8);
+    } > ram
+
+    .main_stack (NOLOAD) :
+    {
+        . = ALIGN(8);
+        *(.main_stack)
+        . = ALIGN(8);
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;

example-usb-serial/stack-def.h

@@ -0,0 +1,39 @@
+#if defined(STACK_MAIN)
+/* Idle+Exception handlers */
+char __main_stack_end__[0] __attribute__ ((section(".main_stack")));
+char main_base[0x0080] __attribute__ ((section(".main_stack")));
+
+/* Main program            */
+char __process0_stack_end__[0] __attribute__ ((section(".process_stack.0")));
+char process0_base[0x0400] __attribute__ ((section(".process_stack.0")));
+#endif
+
+/* First thread program    */
+#if defined(STACK_PROCESS_1)
+char process1_base[0x0200] __attribute__ ((section(".process_stack.1"))); 
+#endif
+
+/* Second thread program   */
+#if defined(STACK_PROCESS_2)
+char process2_base[0x0200] __attribute__ ((section(".process_stack.2")));
+#endif
+
+/* Third thread program    */
+#if defined(STACK_PROCESS_3)
+char process3_base[0x0200] __attribute__ ((section(".process_stack.3")));
+#endif
+
+/* Fourth thread program    */
+#if defined(STACK_PROCESS_4)
+char process4_base[0x0200] __attribute__ ((section(".process_stack.4")));
+#endif
+
+/* Fifth thread program    */
+#if defined(STACK_PROCESS_5)
+char process5_base[0x0200] __attribute__ ((section(".process_stack.5")));
+#endif
+
+/* Sixth thread program    */
+#if defined(STACK_PROCESS_6)
+char process6_base[0x0200] __attribute__ ((section(".process_stack.6")));
+#endif

mcu/chx-stm32f103.c

@@ -1,5 +1,4 @@
 #include <stdint.h>
-#include <mcu/stm32.h>
 #include <mcu/stm32f103.h>
 #include "board.h"
 
@@ -7,7 +6,12 @@ extern int chx_allow_sleep;
 
 #define STM32_PLLSRC		STM32_PLLSRC_HSE
 #define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-
+#ifndef STM32_ADCPRE
+#define STM32_ADCPRE		STM32_ADCPRE_DIV6
+#endif
+#ifndef STM32_USBPRE
+#define STM32_USBPRE		STM32_USBPRE_DIV1P5
+#endif
 
 static void
 configure_clock (int high)
@@ -17,16 +21,16 @@ configure_clock (int high)
 
   if (high)
     {
-      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE_DIV1P5
+      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE
 	| STM32_PLLMUL | STM32_PLLXTPRE	| STM32_PLLSRC
-	| STM32_ADCPRE_DIV6 | STM32_PPRE2_DIV1
+	| STM32_ADCPRE | STM32_PPRE2_DIV1
 	| STM32_PPRE1_DIV2 | STM32_HPRE_DIV1;
 
       cfg_sw = RCC_CFGR_SW_PLL;
     }
   else
     {
-      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE_DIV1P5
+      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE
 	| STM32_PLLMUL | STM32_PLLXTPRE	| STM32_PLLSRC
 	| STM32_ADCPRE_DIV8 | STM32_PPRE2_DIV16
 	| STM32_PPRE1_DIV16 | STM32_HPRE_DIV8;

mcu/clk_gpio_init-stm32.c

@@ -1,7 +1,7 @@
 /*
  * clk_gpio_init-stm32.c - Clock and GPIO initialization for STM32.
  *
- * Copyright (C) 2015  Flying Stone Technology
+ * Copyright (C) 2015, 2018  Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -26,7 +26,11 @@
  *
  */
 
+#if defined(MCU_STM32F0)
 #include <mcu/stm32.h>
+#else
+#include <mcu/stm32f103.h>
+#endif
 
 #if defined(MCU_STM32F0)
 #define STM32_PPRE1		STM32_PPRE1_DIV1
@@ -43,9 +47,13 @@
 #define STM32_SW		STM32_SW_PLL
 #define STM32_HPRE		STM32_HPRE_DIV1
 #define STM32_PPRE2		STM32_PPRE2_DIV1
+#ifndef STM32_ADCPRE
 #define STM32_ADCPRE		STM32_ADCPRE_DIV6
+#endif
 #define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
+#ifndef STM32_USBPRE
+#define STM32_USBPRE		STM32_USBPRE_DIV1P5
+#endif
 
 #define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
 #define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
@@ -53,34 +61,6 @@
 #define STM32_HCLK		(STM32_SYSCLK / 1)
 
 
-#if defined(MCU_STM32F0)
-struct SYSCFG {
-  volatile uint32_t CFGR1;
-  uint32_t dummy0;
-  volatile uint32_t EXTICR[4];
-  volatile uint32_t CFGR2;
-};
-#define SYSCFG_CFGR1_MEM_MODE 0x03
-
-#define SYSCFG_BASE	(APBPERIPH_BASE + 0x00010000)
-static struct SYSCFG *const SYSCFG = (struct SYSCFG *)SYSCFG_BASE;
-#endif
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;
-
 static void __attribute__((used))
 clock_init (void)
 {
@@ -136,75 +116,6 @@ clock_init (void)
 }
 
 
-#if defined(MCU_STM32F0)
-struct GPIO {
-  volatile uint32_t MODER;
-  volatile uint16_t OTYPER;
-  uint16_t dummy0;
-  volatile uint32_t OSPEEDR;
-  volatile uint32_t PUPDR;
-  volatile uint16_t IDR;
-  uint16_t dummy1;
-  volatile uint16_t ODR;
-  uint16_t dummy2;
-  volatile uint16_t BSRR;
-  uint16_t dummy3;
-  volatile uint32_t LCKR;
-  volatile uint32_t AFR[2];
-  volatile uint16_t BRR;
-  uint16_t dummy4;
-};
-
-#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
-#define GPIOF		((struct GPIO *) GPIOF_BASE)
-#else
-struct AFIO
-{
-  volatile uint32_t EVCR;
-  volatile uint32_t MAPR;
-  volatile uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  volatile uint32_t MAPR2;
-};
-
-#define AFIO_BASE 0x40010000
-static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE;
-
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
-#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE     0x02000000
-
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-#endif
-
 static struct GPIO *const GPIO_LED = (struct GPIO *)GPIO_LED_BASE;
 #ifdef GPIO_USB_BASE
 static struct GPIO *const GPIO_USB = (struct GPIO *)GPIO_USB_BASE;
@@ -244,7 +155,7 @@ gpio_init (void)
   AFIO->MAPR |= AFIO_MAPR_SOMETHING;
 #endif
 
-  /* LED is mandatory.  If it's on an independent port, we configure it.  */
+  /* LED is mandatory.  We configure it always.  */
   GPIO_LED->ODR = VAL_GPIO_LED_ODR;
   GPIO_LED->CRH = VAL_GPIO_LED_CRH;
   GPIO_LED->CRL = VAL_GPIO_LED_CRL;

mcu/stm32.h

@@ -1,5 +1,5 @@
 #define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE  PERIPH_BASE
+#define APB1PERIPH_BASE PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
 #define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
@@ -127,6 +127,7 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE;
 #define STM32_ADCPRE_DIV8	(3 << 14)
 
 #define STM32_USBPRE_DIV1P5     (0 << 22)
+#define STM32_USBPRE_DIV2       (3 << 22) /* Not for STM32, but GD32F103 */
 
 #define STM32_MCO_NOCLOCK	(0 << 24)
 
@@ -139,3 +140,85 @@ static struct PWR *const PWR = ((struct PWR *)0x40007000);
 #define PWR_CR_LPDS 0x0001	/* Low-power deepsleep  */
 #define PWR_CR_PDDS 0x0002	/* Power down deepsleep */
 #define PWR_CR_CWUF 0x0004	/* Clear wakeup flag    */
+
+
+#if defined(MCU_STM32F0)
+struct GPIO {
+  volatile uint32_t MODER;
+  volatile uint16_t OTYPER;
+  uint16_t dummy0;
+  volatile uint32_t OSPEEDR;
+  volatile uint32_t PUPDR;
+  volatile uint16_t IDR;
+  uint16_t dummy1;
+  volatile uint16_t ODR;
+  uint16_t dummy2;
+  volatile uint16_t BSRR;
+  uint16_t dummy3;
+  volatile uint32_t LCKR;
+  volatile uint32_t AFR[2];
+  volatile uint16_t BRR;
+  uint16_t dummy4;
+};
+
+#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
+#define GPIOF		((struct GPIO *) GPIOF_BASE)
+#else
+struct GPIO {
+  volatile uint32_t CRL;
+  volatile uint32_t CRH;
+  volatile uint32_t IDR;
+  volatile uint32_t ODR;
+  volatile uint32_t BSRR;
+  volatile uint32_t BRR;
+  volatile uint32_t LCKR;
+};
+
+#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
+#define GPIOE		((struct GPIO *) GPIOE_BASE)
+#endif
+
+
+#if defined(MCU_STM32F0)
+struct SYSCFG {
+  volatile uint32_t CFGR1;
+  uint32_t dummy0;
+  volatile uint32_t EXTICR[4];
+  volatile uint32_t CFGR2;
+};
+#define SYSCFG_CFGR1_MEM_MODE 0x03
+
+#define SYSCFG_BASE	(APB1PERIPH_BASE + 0x00010000)
+static struct SYSCFG *const SYSCFG = (struct SYSCFG *)SYSCFG_BASE;
+#endif
+
+struct FLASH {
+  volatile uint32_t ACR;
+  volatile uint32_t KEYR;
+  volatile uint32_t OPTKEYR;
+  volatile uint32_t SR;
+  volatile uint32_t CR;
+  volatile uint32_t AR;
+  volatile uint32_t RESERVED;
+  volatile uint32_t OBR;
+  volatile uint32_t WRPR;
+};
+
+#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
+static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;

mcu/stm32f103.h

@@ -1,3 +1,6 @@
+#include <mcu/stm32.h>
+#include <mcu/cortex-m.h>
+
 #define  CRC_CR_RESET                        0x00000001
 
 struct CRC {
@@ -571,6 +574,8 @@ static struct EXTI *const EXTI = (struct EXTI *)EXTI_BASE;
 #define EXTI0_IRQ    6
 #define EXTI1_IRQ    7
 #define EXTI2_IRQ    8
+#define EXTI3_IRQ    9
+#define EXTI4_IRQ   10
 #define EXTI9_5_IRQ 23
 #define TIM2_IRQ    28
 #define TIM3_IRQ    29
@@ -630,6 +635,7 @@ static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE;
 
 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
 #define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE     0x02000000
 
 
 struct DBGMCU {

mcu/sys-stm32f103.c

@@ -1,7 +1,7 @@
 /*
  * sys-stm32f103.c - system routines for the initial page for STM32F103.
  *
- * Copyright (C) 2013, 2014, 2015, 2016, 2017
+ * Copyright (C) 2013, 2014, 2015, 2016, 2017, 2018
  *               Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -18,7 +18,6 @@
 #include <stdlib.h>
 #include "board.h"
 
-#include "mcu/cortex-m.h"
 #include "mcu/clk_gpio_init-stm32.c"
 
 
@@ -82,7 +81,7 @@ usb_lld_sys_init (void)
     {
       usb_lld_sys_shutdown ();
       /* Disconnect requires SE0 (>= 2.5uS).  */
-      wait (300);
+      wait (5*MHZ);
     }
 
   usb_cable_config (1);
@@ -256,6 +255,9 @@ flash_protect (void)
       FLASH->OPTKEYR = FLASH_KEY1;
       FLASH->OPTKEYR = FLASH_KEY2;
 
+      while (!(FLASH->CR & FLASH_CR_OPTWRE))
+	;
+
       FLASH->CR |= FLASH_CR_OPTER;
       FLASH->CR |= FLASH_CR_STRT;
 

mcu/sys-stm32f103.h

@@ -1,6 +1,8 @@
 #define BOARD_ID_CQ_STARM          0xc5480875
 #define BOARD_ID_FST_01_00         0x613870a9
 #define BOARD_ID_FST_01            0x696886af
+#define BOARD_ID_FST_01G           0x8801277f
+#define BOARD_ID_FST_01SZ          0x7e6fb084
 #define BOARD_ID_MAPLE_MINI        0x7a445272
 #define BOARD_ID_OLIMEX_STM32_H103 0xf92bb594
 #define BOARD_ID_STBEE_MINI        0x1f341961

mcu/usb-mkl27z.c

@@ -950,11 +950,11 @@ usb_lld_ctrl_send (struct usb_dev *dev, const void *buf, size_t buflen)
   data_p->len = buflen;
 
   /* Restrict the data length to be the one host asks for */
-  if (data_p->len > len_asked)
+  if (data_p->len >= len_asked)
     data_p->len = len_asked;
-
-  data_p->require_zlp = (data_p->len != 0
-			 && (data_p->len % USB_MAX_PACKET_SIZE) == 0);
+  /* ZLP is only required when host doesn't expect the end of packets.  */
+  else if (data_p->len != 0 && (data_p->len % USB_MAX_PACKET_SIZE) == 0)
+    data_p->require_zlp = 1;
 
   if (data_p->len < USB_MAX_PACKET_SIZE)
     {

mcu/usb-stm32f103.c

@@ -339,6 +339,9 @@ void usb_lld_init (struct usb_dev *dev, uint8_t feature)
 
   /* Clear Interrupt Status Register, and enable interrupt for USB */
   st103_set_istr (0);
+
+  st103_set_btable ();
+
   st103_set_cntr (CNTR_CTRM | CNTR_OVRM | CNTR_ERRM
 		  | CNTR_WKUPM | CNTR_SUSPM | CNTR_RESETM);
 
@@ -906,7 +909,6 @@ void usb_lld_reset (struct usb_dev *dev, uint8_t feature)
 {
   usb_lld_set_configuration (dev, 0);
   dev->feature = feature;
-  st103_set_btable ();
   st103_set_daddr (0);
 }
 
@@ -1103,10 +1105,10 @@ usb_lld_ctrl_send (struct usb_dev *dev, const void *buf, size_t buflen)
   data_p->len = buflen;
 
   /* Restrict the data length to be the one host asks for */
-  if (data_p->len > len_asked)
+  if (data_p->len >= len_asked)
     data_p->len = len_asked;
-
-  if (data_p->len != 0 && (data_p->len % USB_MAX_PACKET_SIZE) == 0)
+  /* ZLP is only required when host doesn't expect the end of packets.  */
+  else if (data_p->len != 0 && (data_p->len % USB_MAX_PACKET_SIZE) == 0)
     data_p->require_zlp = 1;
 
   if (data_p->len < USB_MAX_PACKET_SIZE)

mcu/usb-usbip.c

@@ -2169,10 +2169,10 @@ usb_lld_ctrl_send (struct usb_dev *dev, const void *buf, size_t buflen)
   data_p->len = buflen;
 
   /* Restrict the data length to be the one host asks for */
-  if (data_p->len > len_asked)
+  if (data_p->len >= len_asked)
     data_p->len = len_asked;
-
-  if (data_p->len != 0 && (data_p->len % USB_MAX_PACKET_SIZE) == 0)
+  /* ZLP is only required when host doesn't expect the end of packets.  */
+  else if (data_p->len != 0 && (data_p->len % USB_MAX_PACKET_SIZE) == 0)
     data_p->require_zlp = 1;
 
   if (data_p->len < USB_MAX_PACKET_SIZE)

rules.mk

@@ -25,6 +25,12 @@ endif
 ifneq ($(USE_ADC),)
 CSRC += $(CHOPSTX)/contrib/adc-$(CHIP).c
 endif
+ifneq ($(USE_USART),)
+CSRC += $(CHOPSTX)/contrib/usart-$(CHIP).c
+endif
+ifneq ($(USE_ACKBTN),)
+CSRC += $(CHOPSTX)/contrib/ackbtn-$(CHIP).c
+endif
 
 INCDIR += $(CHOPSTX)