update chopstx
This commit is contained in:
NIIBE Yutaka
@@ -1,5 +1,9 @@
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2015-06-30 Niibe Yutaka <gniibe@fsij.org>
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* chopstx: Update.
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* src/sys.c: Update from chopstx/example-cdc/sys.c.
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* src/main.c (device_initialize_once): Apply change of NeuG.
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2015-06-03 Niibe Yutaka <gniibe@fsij.org>
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2
chopstx
2
chopstx
Submodule chopstx updated: fc26cf0889...43bd3bcefd
229
src/sys.c
229
src/sys.c
@@ -1,7 +1,7 @@
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/*
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* sys.c - system routines for the initial page for STM32F103.
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*
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* Copyright (C) 2013, 2014 Flying Stone Technology
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* Copyright (C) 2013, 2014, 2015 Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* Copying and distribution of this file, with or without modification,
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@@ -17,53 +17,13 @@
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#include <stdlib.h>
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#include "board.h"
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#include "clk_gpio_init.c"
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#define CORTEX_PRIORITY_BITS 4
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#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
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#define USB_LP_CAN1_RX0_IRQn 20
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#define STM32_USB_IRQ_PRIORITY 11
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#define STM32_SW_HSI (0 << 0)
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#define STM32_SW_PLL (2 << 0)
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#define STM32_PLLSRC_HSI (0 << 16)
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#define STM32_PLLSRC_HSE (1 << 16)
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#define STM32_PLLXTPRE_DIV1 (0 << 17)
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#define STM32_PLLXTPRE_DIV2 (1 << 17)
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#define STM32_HPRE_DIV1 (0 << 4)
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#define STM32_PPRE1_DIV1 (0 << 8)
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#define STM32_PPRE1_DIV2 (4 << 8)
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#define STM32_PPRE2_DIV1 (0 << 11)
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#define STM32_PPRE2_DIV2 (4 << 11)
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#define STM32_ADCPRE_DIV4 (1 << 14)
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#define STM32_ADCPRE_DIV6 (2 << 14)
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#define STM32_USBPRE_DIV1P5 (0 << 22)
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#define STM32_MCO_NOCLOCK (0 << 24)
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_FLASHBITS 0x00000012
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#define STM32_SW STM32_SW_PLL
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_ADCPRE STM32_ADCPRE_DIV6
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#define STM32_MCOSEL STM32_MCO_NOCLOCK
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#define STM32_USBPRE STM32_USBPRE_DIV1P5
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#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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#define STM32_SYSCLK STM32_PLLCLKOUT
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#define STM32_HCLK (STM32_SYSCLK / 1)
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struct NVIC {
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uint32_t ISER[8];
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uint32_t unused1[24];
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@@ -93,191 +53,6 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
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NVIC_ISER (n) = 1 << (n & 0x1F);
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}
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#define PERIPH_BASE 0x40000000
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#define APBPERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
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struct RCC {
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volatile uint32_t CR;
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volatile uint32_t CFGR;
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volatile uint32_t CIR;
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volatile uint32_t APB2RSTR;
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volatile uint32_t APB1RSTR;
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volatile uint32_t AHBENR;
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volatile uint32_t APB2ENR;
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volatile uint32_t APB1ENR;
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volatile uint32_t BDCR;
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volatile uint32_t CSR;
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};
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#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
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#define RCC_APB1ENR_USBEN 0x00800000
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#define RCC_APB1RSTR_USBRST 0x00800000
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#define RCC_CR_HSION 0x00000001
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#define RCC_CR_HSIRDY 0x00000002
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#define RCC_CR_HSITRIM 0x000000F8
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#define RCC_CR_HSEON 0x00010000
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#define RCC_CR_HSERDY 0x00020000
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#define RCC_CR_PLLON 0x01000000
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#define RCC_CR_PLLRDY 0x02000000
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#define RCC_CFGR_SWS 0x0000000C
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#define RCC_CFGR_SWS_HSI 0x00000000
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#define RCC_AHBENR_CRCEN 0x0040
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#define RCC_APB2RSTR_AFIORST 0x00000001
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#define RCC_APB2RSTR_IOPARST 0x00000004
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#define RCC_APB2RSTR_IOPBRST 0x00000008
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#define RCC_APB2RSTR_IOPCRST 0x00000010
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#define RCC_APB2RSTR_IOPDRST 0x00000020
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#define RCC_APB2ENR_AFIOEN 0x00000001
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#define RCC_APB2ENR_IOPAEN 0x00000004
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#define RCC_APB2ENR_IOPBEN 0x00000008
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#define RCC_APB2ENR_IOPCEN 0x00000010
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#define RCC_APB2ENR_IOPDEN 0x00000020
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struct FLASH {
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volatile uint32_t ACR;
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volatile uint32_t KEYR;
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volatile uint32_t OPTKEYR;
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volatile uint32_t SR;
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volatile uint32_t CR;
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volatile uint32_t AR;
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volatile uint32_t RESERVED;
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volatile uint32_t OBR;
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volatile uint32_t WRPR;
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};
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#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
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static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
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static void
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clock_init (void)
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{
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/* HSI setup */
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY))
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;
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/* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
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RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
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RCC->CFGR = 0;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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;
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/* HSE setup */
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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;
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/* PLL setup */
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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/* Clock settings */
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RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
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| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/*
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* We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
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*/
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/* Flash setup */
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FLASH->ACR = STM32_FLASHBITS;
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/* CRC */
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RCC->AHBENR |= RCC_AHBENR_CRCEN;
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/* Switching on the configured clock source. */
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RCC->CFGR |= STM32_SW;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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}
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struct AFIO
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{
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volatile uint32_t EVCR;
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volatile uint32_t MAPR;
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volatile uint32_t EXTICR[4];
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uint32_t RESERVED0;
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volatile uint32_t MAPR2;
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};
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#define AFIO_BASE 0x40010000
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static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
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#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
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#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
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struct GPIO {
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volatile uint32_t CRL;
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volatile uint32_t CRH;
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volatile uint32_t IDR;
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volatile uint32_t ODR;
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volatile uint32_t BSRR;
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volatile uint32_t BRR;
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volatile uint32_t LCKR;
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};
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#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
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#define GPIOA ((struct GPIO *) GPIOA_BASE)
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#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
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#define GPIOB ((struct GPIO *) GPIOB_BASE)
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#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
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#define GPIOC ((struct GPIO *) GPIOC_BASE)
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#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
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#define GPIOD ((struct GPIO *) GPIOD_BASE)
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#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
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#define GPIOE ((struct GPIO *) GPIOE_BASE)
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static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
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#ifdef GPIO_USB_BASE
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static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
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#endif
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#ifdef GPIO_OTHER_BASE
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static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
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#endif
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static void
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gpio_init (void)
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{
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/* Enable GPIO clock. */
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RCC->APB2ENR |= RCC_ENR_IOP_EN;
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RCC->APB2RSTR = RCC_RSTR_IOP_RST;
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RCC->APB2RSTR = 0;
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#ifdef AFIO_MAPR_SOMETHING
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AFIO->MAPR |= AFIO_MAPR_SOMETHING;
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#endif
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GPIO_USB->ODR = VAL_GPIO_ODR;
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GPIO_USB->CRH = VAL_GPIO_CRH;
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GPIO_USB->CRL = VAL_GPIO_CRL;
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#if GPIO_USB_BASE != GPIO_LED_BASE
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GPIO_LED->ODR = VAL_GPIO_LED_ODR;
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GPIO_LED->CRH = VAL_GPIO_LED_CRH;
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GPIO_LED->CRL = VAL_GPIO_LED_CRL;
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#endif
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#ifdef GPIO_OTHER_BASE
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GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
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GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
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GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
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#endif
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}
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static void
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usb_cable_config (int enable)
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{
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