Imported ChibiOS/RT 2.0.6.
This commit is contained in:
NIIBE Yutaka
433
ChibiOS_2.0.6/os/hal/platforms/STM32/serial_lld.c
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433
ChibiOS_2.0.6/os/hal/platforms/STM32/serial_lld.c
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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---
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes ChibiOS/RT, without being obliged to provide
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the source code for any proprietary components. See the file exception.txt
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for full details of how and when the exception can be applied.
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*/
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/**
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* @file STM32/serial_lld.c
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* @brief STM32 low level serial driver code.
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*
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* @addtogroup STM32_SERIAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief USART1 serial driver identifier.*/
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#if USE_STM32_USART1 || defined(__DOXYGEN__)
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SerialDriver SD1;
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#endif
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/** @brief USART2 serial driver identifier.*/
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#if USE_STM32_USART2 || defined(__DOXYGEN__)
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SerialDriver SD2;
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#endif
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/** @brief USART3 serial driver identifier.*/
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#if USE_STM32_USART3 || defined(__DOXYGEN__)
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SerialDriver SD3;
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#endif
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#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)
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/** @brief UART4 serial driver identifier.*/
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#if USE_STM32_UART4 || defined(__DOXYGEN__)
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SerialDriver SD4;
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#endif
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/** @brief UART5 serial driver identifier.*/
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#if USE_STM32_UART5 || defined(__DOXYGEN__)
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SerialDriver SD5;
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#endif
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/** @brief Driver default configuration.*/
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static const SerialConfig default_config =
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{
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SERIAL_DEFAULT_BITRATE,
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0,
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USART_CR2_STOP1_BITS | USART_CR2_LINEN,
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0
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief USART initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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* @param[in] config the architecture-dependent serial driver configuration
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*/
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static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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USART_TypeDef *u = sdp->usart;
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/*
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* Baud rate setting.
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*/
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if (sdp->usart == USART1)
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u->BRR = STM32_PCLK2 / config->sc_speed;
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else
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u->BRR = STM32_PCLK1 / config->sc_speed;
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/*
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* Note that some bits are enforced.
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*/
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u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
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USART_CR1_RXNEIE | USART_CR1_TE |
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USART_CR1_RE;
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u->CR2 = config->sc_cr2 | USART_CR2_LBDIE;
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u->CR3 = config->sc_cr3 | USART_CR3_EIE;
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(void)u->SR; /* SR reset step 1.*/
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(void)u->DR; /* SR reset step 2.*/
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}
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/**
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* @brief USART de-initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] u pointer to an USART I/O block
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*/
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static void usart_deinit(USART_TypeDef *u) {
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u->CR1 = 0;
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u->CR2 = 0;
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u->CR3 = 0;
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}
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/**
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* @brief Error handling routine.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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* @param[in] sr USART SR register value
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*/
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static void set_error(SerialDriver *sdp, uint16_t sr) {
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sdflags_t sts = 0;
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if (sr & USART_SR_ORE)
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sts |= SD_OVERRUN_ERROR;
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if (sr & USART_SR_PE)
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sts |= SD_PARITY_ERROR;
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if (sr & USART_SR_FE)
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sts |= SD_FRAMING_ERROR;
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if (sr & USART_SR_NE)
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sts |= SD_NOISE_ERROR;
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if (sr & USART_SR_LBD)
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sts |= SD_BREAK_DETECTED;
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chSysLockFromIsr();
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sdAddFlagsI(sdp, sts);
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chSysUnlockFromIsr();
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}
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/**
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* @brief Common IRQ handler.
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*
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* @param[in] sdp communication channel associated to the USART
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*/
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static void serve_interrupt(SerialDriver *sdp) {
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USART_TypeDef *u = sdp->usart;
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uint16_t cr1 = u->CR1;
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uint16_t sr = u->SR; /* SR reset step 1.*/
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uint16_t dr = u->DR; /* SR reset step 2.*/
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if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE |
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USART_SR_FE | USART_SR_PE)) {
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set_error(sdp, sr);
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u->SR = 0; /* Clears the LBD bit in the SR.*/
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}
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if (sr & USART_SR_RXNE) {
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chSysLockFromIsr();
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sdIncomingDataI(sdp, (uint8_t)dr);
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chSysUnlockFromIsr();
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}
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if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) {
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msg_t b;
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chSysLockFromIsr();
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b = chOQGetI(&sdp->oqueue);
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if (b < Q_OK) {
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chEvtBroadcastI(&sdp->oevent);
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u->CR1 = cr1 & ~USART_CR1_TXEIE;
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}
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else
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u->DR = b;
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chSysUnlockFromIsr();
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}
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}
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#if USE_STM32_USART1 || defined(__DOXYGEN__)
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static void notify1(void) {
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USART1->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if USE_STM32_USART2 || defined(__DOXYGEN__)
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static void notify2(void) {
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USART2->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if USE_STM32_USART3 || defined(__DOXYGEN__)
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static void notify3(void) {
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USART3->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)
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#if USE_STM32_UART4 || defined(__DOXYGEN__)
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static void notify4(void) {
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UART4->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if USE_STM32_UART5 || defined(__DOXYGEN__)
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static void notify5(void) {
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UART5->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#endif
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if USE_STM32_USART1 || defined(__DOXYGEN__)
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CH_IRQ_HANDLER(VectorD4) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&SD1);
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CH_IRQ_EPILOGUE();
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}
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#endif
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#if USE_STM32_USART2 || defined(__DOXYGEN__)
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CH_IRQ_HANDLER(VectorD8) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&SD2);
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CH_IRQ_EPILOGUE();
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}
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#endif
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#if USE_STM32_USART3 || defined(__DOXYGEN__)
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CH_IRQ_HANDLER(VectorDC) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&SD3);
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CH_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)
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#if USE_STM32_UART4 || defined(__DOXYGEN__)
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CH_IRQ_HANDLER(Vector110) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&SD4);
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CH_IRQ_EPILOGUE();
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}
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#endif
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#if USE_STM32_UART5 || defined(__DOXYGEN__)
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CH_IRQ_HANDLER(Vector114) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&SD5);
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CH_IRQ_EPILOGUE();
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}
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#endif
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level serial driver initialization.
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*/
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void sd_lld_init(void) {
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#if USE_STM32_USART1
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sdObjectInit(&SD1, NULL, notify1);
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SD1.usart = USART1;
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#endif
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#if USE_STM32_USART2
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sdObjectInit(&SD2, NULL, notify2);
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SD2.usart = USART2;
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#endif
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#if USE_STM32_USART3
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sdObjectInit(&SD3, NULL, notify3);
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SD3.usart = USART3;
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#endif
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#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
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#if USE_STM32_UART4
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sdObjectInit(&SD4, NULL, notify4);
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SD4.usart = UART4;
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#endif
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#if USE_STM32_UART5
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sdObjectInit(&SD5, NULL, notify5);
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SD5.usart = UART5;
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#endif
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#endif
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}
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/**
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* @brief Low level serial driver configuration and (re)start.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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* @param[in] config the architecture-dependent serial driver configuration.
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* If this parameter is set to @p NULL then a default
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* configuration is used.
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*/
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void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
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if (config == NULL)
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config = &default_config;
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if (sdp->state == SD_STOP) {
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#if USE_STM32_USART1
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if (&SD1 == sdp) {
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RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
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NVICEnableVector(USART1_IRQn,
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CORTEX_PRIORITY_MASK(STM32_USART1_PRIORITY));
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}
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#endif
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#if USE_STM32_USART2
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if (&SD2 == sdp) {
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RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
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NVICEnableVector(USART2_IRQn,
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CORTEX_PRIORITY_MASK(STM32_USART2_PRIORITY));
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}
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#endif
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#if USE_STM32_USART3
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if (&SD3 == sdp) {
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RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
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NVICEnableVector(USART3_IRQn,
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CORTEX_PRIORITY_MASK(STM32_USART3_PRIORITY));
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}
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#endif
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#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
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#if USE_STM32_UART4
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if (&SD4 == sdp) {
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RCC->APB1ENR |= RCC_APB1ENR_UART4EN;
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NVICEnableVector(UART4_IRQn,
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CORTEX_PRIORITY_MASK(STM32_UART4_PRIORITY));
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}
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#endif
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#if USE_STM32_UART5
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if (&SD5 == sdp) {
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RCC->APB1ENR |= RCC_APB1ENR_UART5EN;
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NVICEnableVector(UART5_IRQn,
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CORTEX_PRIORITY_MASK(STM32_UART5_PRIORITY));
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}
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#endif
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#endif
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}
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usart_init(sdp, config);
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}
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/**
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* @brief Low level serial driver stop.
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* @details De-initializes the USART, stops the associated clock, resets the
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* interrupt vector.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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*/
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void sd_lld_stop(SerialDriver *sdp) {
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if (sdp->state == SD_READY) {
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usart_deinit(sdp->usart);
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#if USE_STM32_USART1
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if (&SD1 == sdp) {
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RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN;
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NVICDisableVector(USART1_IRQn);
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return;
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}
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#endif
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#if USE_STM32_USART2
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if (&SD2 == sdp) {
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RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;
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NVICDisableVector(USART2_IRQn);
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return;
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}
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#endif
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#if USE_STM32_USART3
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if (&SD3 == sdp) {
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RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN;
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NVICDisableVector(USART3_IRQn);
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return;
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}
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#endif
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#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
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#if USE_STM32_UART4
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if (&SD4 == sdp) {
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RCC->APB1ENR &= ~RCC_APB1ENR_UART4EN;
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NVICDisableVector(UART4_IRQn);
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return;
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}
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#endif
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#if USE_STM32_UART5
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if (&SD5 == sdp) {
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RCC->APB1ENR &= ~RCC_APB1ENR_UART5EN;
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NVICDisableVector(UART5_IRQn);
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return;
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}
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#endif
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#endif
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}
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}
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#endif /* CH_HAL_USE_SERIAL */
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/** @} */
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