208 lines
4.6 KiB
C
208 lines
4.6 KiB
C
/*
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* spi-st.c - SPI driver for STM32F103/GD32F103/GD32VF103
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*
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* Copyright (C) 2019 Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* This file is a part of Chopstx, a thread library for embedded.
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*
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* Chopstx is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Chopstx is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* As additional permission under GNU GPL version 3 section 7, you may
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* distribute non-source form of the Program without the copy of the
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* GNU GPL normally required by section 4, provided you inform the
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* recipients of GNU GPL by a written offer.
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*
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <chopstx.h>
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#include <mcu/stm32.h>
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#ifndef SPI_USE_INTERRUPT
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#define SPI_BUSY_WAIT 1
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#endif
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/* Hardware registers */
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struct SPI {
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t SR;
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volatile uint32_t DR;
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volatile uint32_t CRCPR;
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volatile uint32_t RXCRCR;
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volatile uint32_t TXCRCR;
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};
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/* It is named SPI0 in GD32VF103, while it's "SPI1" in RM0008 of STM32F103 */
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#define SPI0_BASE (APB2PERIPH_BASE + 0x3000)
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#define SPI0 ((struct SPI *)SPI0_BASE)
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#define INTR_REQ_SPI0 54 /* For GD32VF103 */
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static struct SPI *SPIx = SPI0;
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#ifndef SPI_BUSY_WAIT
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static struct chx_intr spi_intr;
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#endif
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static int tx_ready;
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static int rx_done;
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/*
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* For now, it only support configuration of a specific use case:
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*
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* SPI0 of GD32VF103
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* Master mode
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* Hardware NSS pin not used
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* Two unidirectional lines, full duplex
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* CRC enabled
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* 8-bit data frame
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* MSBit first
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* Clock polarity: High==idle
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*
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* We need to consider what kind of configuration can be specified
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* by the API. Perhaps, it should return an error code when it is
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* not supported by the hardware.
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*/
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int
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spi_init (void)
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{
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uint32_t cr1_reg = 0;
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/* Enable SPI module */
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RCC->APB2ENR |= (1 << 12);
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RCC->APB2RSTR = (1 << 12);
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RCC->APB2RSTR = 0;
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/* Master mode */
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cr1_reg |= (1 << 2); /* In RM0008, it's called MSTR */
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/* No use of hardware NSS pin */
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cr1_reg |= (1 << 9); /* In RM0008, it's called SSM */
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cr1_reg |= (1 << 8); /* In RM0008, it's called SSI */
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/* Two unidirectional lines, full duplex: Bit15=0, Bit14=0, Bit10=0 */
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/* Bit11: data-frame-format: 8-bit 0 (16-bit (1<<11)) */
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/* But7: bit-order: MSB first 0, LSB first (1<<7) */
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/* Enable CRC */
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cr1_reg |= (1 << 13);
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cr1_reg |= (0x02 << 3); /* prescaler: fPCLK/8 */
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cr1_reg |= (1 << 1); /* clock polarity 1==idle */
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cr1_reg |= (1 << 0); /* second clock data capture edge */
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cr1_reg |= (1 << 6); /* SPI enable */
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SPIx->CR1 = cr1_reg;
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/* Don't touch CRCPR: Just use reset default value of 7 */
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/* Don't touch I2SCFGR, I2SPR */
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#ifndef SPI_BUSY_WAIT
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chopstx_claim_irq (&spi_intr, INTR_REQ_SPI0);
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/* Enable notification for Tx empty, Rx done, or Error */
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SPIx->CR2 = (1 << 7) | (1 << 6) | (1 << 5);
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#endif
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tx_ready = 0;
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rx_done = 0;
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return 0;
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}
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static void
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clear_crc_err (void)
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{
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SPIx->SR &= ~(1 << 4);
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}
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static void
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put_data (uint16_t data)
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{
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tx_ready = 0;
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rx_done = 0;
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SPIx->DR = (uint32_t)data;
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}
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static uint16_t
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get_data (void)
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{
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return ((uint16_t)SPIx->DR);
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}
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#define CHECK_TX 0
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#define CHECK_RX 1
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static void
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check_transmit (int for_what)
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{
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for (;;)
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{
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uint16_t status;
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if (for_what == CHECK_TX && tx_ready)
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return;
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if (for_what == CHECK_RX && rx_done)
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return;
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#ifndef SPI_BUSY_WAIT
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/* Wait an event */
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chopstx_intr_wait (&spi_intr);
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#endif
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status = SPIx->SR;
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if ((status & (1 << 0)))
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rx_done = 1;
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if ((status & (1 << 1)))
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tx_ready = 1;
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if ((status & (1 << 4)))
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{
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/*FIXME: stat crc_err_count++ */
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clear_crc_err ();
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}
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#if 0
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/*FIXME: stat err_count++ */
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if ((status & 0x00fc))
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{
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}
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#endif
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#ifndef SPI_BUSY_WAIT
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chopstx_intr_done (&spi_intr);
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#endif
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}
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}
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void
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spi_send (uint16_t data)
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{
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check_transmit (CHECK_TX);
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put_data (data);
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}
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uint16_t
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spi_recv (void)
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{
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check_transmit (CHECK_RX);
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return get_data ();
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}
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