Version 1.9.

.gitlab-ci.yml

@@ -0,0 +1,15 @@
+image: debian:stable
+
+before_script:
+  - apt-get update && apt-get -y install texi2html
+
+pages:
+  stage: deploy
+  script:
+  - mkdir -p html && (cd html && texi2html ../doc/chopstx.texi)
+  - mv html/ public
+  artifacts:
+    paths:
+    - public
+  only:
+    - master

ChangeLog

@@ -1,3 +1,36 @@
+2018-05-09  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.9.
+	* doc/chopstx.texi (VERSION): 1.9.
+
+2018-05-08  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-blue-pill.h (GPIO_USB_SET_TO_ENABLE): Remove.
+
+	* doc/chopstx.texi (Compile-time macro): New chapter.
+
+	* mcu/sys-stm32f103.c (usb_lld_sys_init): Use MHZ.
+	(flash_protect): Fix for GD32F103.
+
+2018-04-26  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* board/board-blue-pill-g.h: New.  Define STM32_ADCPRE and
+	STM32_USBPRE for 96MHz clock.
+	* mcu/stm32.h (STM32_USBPRE_DIV2): New for GD32F103.
+	* mcu/clk_gpio_init-stm32.c: Allow constants, which are defined by
+	board.h	(STM32_ADCPRE and STM32_USBPRE).
+	* mcu/chx-stm32f103.c: Use STM32_ADCPRE and STM32_USBPRE.
+
+	* mcu/usb-stm32f103.c (usb_lld_init): BTABLE setting at
+	initialization.
+	(usb_lld_reset): Not at each reset.
+
+	* contrib/adc-stm32f103.c [MCU_STM32F1_GD32F1]: Use continuous
+	sampling with no DELIBARATELY_DO_IT_WRONG_START_STOP.
+	(adc_init): Wait after ADC_CR2_ADON.
+	(adc_start): Likewise.  Enabling by ADC_CR2_ADON after all other
+	registers configuration.
+
 2018-01-19  NIIBE Yutaka  <gniibe@fsij.org>
 
 	* VERSION: 1.8.

NEWS

@@ -1,6 +1,27 @@
 NEWS - Noteworthy changes
 
 
+* Major changes in Chopstx 1.9
+
+  Released 2018-05-09
+
+** GD32F103 support
+GD32F103 is an alternative implementation of STM32F103 by Giga Device,
+which can run at 96MHz.
+
+** Minor USB driver fix for STM32F103/GD32F103
+BTABLE setting should be done at initialization, not at USB RESET.
+
+** Minor SYS driver fix for GD32F103
+flash_protect should check FLASH_CR_OPTWRE.
+
+** Minor ADC driver change for GD32F103
+ADC on GD32F103 is another implementation and its behavior is somewhat
+different.  It requires waits after enabling.  So, we use continuous
+sampling, instead of start and stop for each sample.  Still, we
+observe enough noise (> 4.7 bit/byte) for each ADC sampling.
+
+
 * Major changes in Chopstx 1.8
 
   Released 2018-01-19

README

@@ -1,14 +1,14 @@
 Chopstx - Threads and only Threads
-							 Version 1.8
-							  2018-01-19
+							 Version 1.9
+							  2018-05-09
 							Niibe Yutaka
 					     Flying Stone Technology
 
 What's Chopstx?
 ===============
 
-Chopstx is an RT thread library for STM32F103 (ARM Cortex-M3),
-STM32F030 (ARM Cortex-M0), MKL27Z (ARM Cortex-M0plus), and
+Chopstx is an RT thread library for STM32F103 and GD32F103 (ARM
+Cortex-M3), STM32F030 (ARM Cortex-M0), MKL27Z (ARM Cortex-M0plus), and
 emulation on GNU/Linux.
 
 While most RTOSes come with many features, drivers, and protocol
@@ -49,6 +49,8 @@ CDC-ACM demo by:
    $ ln -sf ../board/board-olimex-stm32-h103.h board.h
    $ make
 
+If you want to try GD32F103, Add -DMHZ=96 to DEFS in Makefile.
+
 For a specific board named FSM-55, an example of LED matrix dynamic
 driver is provided.  See the directory: example-fsm-55.
 

VERSION

@@ -1 +1 @@
-release/1.8
+release/1.9

board/board-blue-pill-g.h

@@ -0,0 +1,42 @@
+#define BOARD_NAME "Blue Pill GD32F103"
+/* http://wiki.stm32duino.com/index.php?title=Blue_Pill */
+/* echo -n "Blue Pill GD32F103" | shasum -a 256 | sed -e 's/^.*\(........\)  -$/\1/' */
+#define BOARD_ID    0xed415594
+
+#define MCU_STM32F1_GD32F1 1
+#define STM32_USBPRE                    STM32_USBPRE_DIV2
+#define STM32_ADCPRE                    STM32_ADCPRE_DIV8
+
+#define MCU_STM32F1 1
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              12
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOC_BASE
+#define GPIO_LED_CLEAR_TO_EMIT          13
+#define GPIO_USB_BASE   GPIOA_BASE
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ *
+ * Port C setup.
+ * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ * PCx  - input with pull-up
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFE7FF
+#define VAL_GPIO_USB_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x88811888      /* PA15...PA8 */
+
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x88388888      /* PC15...PC8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPCRST)

board/board-blue-pill.h

@@ -13,13 +13,14 @@
 #define GPIO_LED_BASE   GPIOC_BASE
 #define GPIO_LED_CLEAR_TO_EMIT          13
 #define GPIO_USB_BASE   GPIOA_BASE
-#define GPIO_USB_SET_TO_ENABLE          12
 #undef  GPIO_OTHER_BASE
 
 /*
  * Port A setup.
  * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
  * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ *
+ * Port C setup.
  * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF)
  * ------------------------ Default
  * PAx  - input with pull-up

contrib/adc-stm32f103.c

@@ -34,6 +34,8 @@
 #include <chopstx.h>
 #include <mcu/stm32f103.h>
 #include "adc.h"
+#include "board.h"
+#include "sys.h"
 
 #define STM32_ADC_ADC1_DMA_PRIORITY         2
 
@@ -69,7 +71,9 @@
 #define ADC_CHANNEL_VREFINT     17
 
 #define DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
+#ifndef MCU_STM32F1_GD32F1
 #define DELIBARATELY_DO_IT_WRONG_START_STOP
+#endif
 
 #ifdef DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
 #define ADC_SAMPLE_VREF ADC_SAMPLE_1P5
@@ -114,6 +118,8 @@ adc_init (void)
 
   ADC1->CR1 = 0;
   ADC1->CR2 = ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
+
   ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
   while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
     ;
@@ -124,6 +130,8 @@ adc_init (void)
 
   ADC2->CR1 = 0;
   ADC2->CR2 = ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
+
   ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
   while ((ADC2->CR2 & ADC_CR2_RSTCAL) != 0)
     ;
@@ -137,9 +145,6 @@ adc_init (void)
   return 0;
 }
 
-#include "board.h"
-#include "sys.h"
-
 static void
 get_adc_config (uint32_t config[4])
 {
@@ -212,24 +217,26 @@ adc_start (void)
 
   RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
 
-  ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
-	       | ADC_CR1_SCAN);
-  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
-	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
   ADC1->SMPR1 = NEUG_ADC_SETTING1_SMPR1;
   ADC1->SMPR2 = NEUG_ADC_SETTING1_SMPR2;
   ADC1->SQR1 = ADC_SQR1_NUM_CH(NEUG_ADC_SETTING1_NUM_CHANNELS);
   ADC1->SQR2 = 0;
   ADC1->SQR3 = NEUG_ADC_SETTING1_SQR3;
-
-  ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+  ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
 	       | ADC_CR1_SCAN);
-  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
+	       | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
+  chopstx_usec_wait (1000);
+
   ADC2->SMPR1 = config[0];
   ADC2->SMPR2 = config[1];
   ADC2->SQR1 = config[2];
   ADC2->SQR2 = 0;
   ADC2->SQR3 = config[3];
+  ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
+	       | ADC_CR1_SCAN);
+  ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
+  chopstx_usec_wait (1000);
 
 #ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
   /*

doc/chopstx.texi

@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
 @c %**start of header
 @setfilename chopstx.info
-@set VERSION 1.8
+@set VERSION 1.9
 @settitle Chopstx Reference Manual
 @c Unify some of the indices.
 @syncodeindex tp fn
@@ -11,7 +11,7 @@
 This manual is for Chopstx (version @value{VERSION}).
 
 @noindent
-Copyright @copyright{} 2013, 2015, 2016, 2017 Flying Stone Technology @*
+Copyright @copyright{} 2013, 2015, 2016, 2017, 2018 Flying Stone Technology @*
 
 @quotation
 Permission is granted to copy, distribute and/or modify this document
@@ -62,6 +62,7 @@ section entitled ``Copying''.
 * Threads and only Threads::     Threads and only Threads.
 * Poll or Pole::                 Poll or Pole.
 * Note (Use of sleep mode)::     Use it carefully.
+* Compile-time macro::           Macro to be defined.
 * API::                          API.
 
 Appendix
@@ -88,7 +89,7 @@ Indexes
 
 Chopstx is an RT thread library for ARM Cortex-M0, Cortex-M0plus,
 Cortex-M3 and GNU/Linux emulation.  Specifically, it is used for
-STM32F030, MKL27Z, STM32F103 and as a command on GNU/Linux.
+STM32F030, MKL27Z, STM32F103, GD32F103 and as a command on GNU/Linux.
 
 While most RTOSes come with many features, drivers, and stacks,
 Chopstx just offers an RT thread library.
@@ -157,6 +158,21 @@ program carefully.  Enabling sleep, it may result a bricked board; A
 board with no RESET pin cannot be debugged by JTAG/SWD.
 
 
+@node Compile-time macro
+@chapter Compile-time macro
+
+Compiling Chopstx, a macro MHZ should be supplied.
+
+For example, when using the makefile rule of chopstx/rules.mk, please
+define the make variable DEFS with -DMHZ=72 before inclusion of the rule file.
+
+@subheading MHZ
+@anchor{MHZ}
+@defmac {MHZ}
+Running CPU clock in MHz.  Used for chopstx_usec_wait.
+@end defmac
+
+
 @node API
 @chapter API
 

example-fraucheky/main.c

@@ -18,6 +18,7 @@ extern void EP6_OUT_Callback (uint16_t len);
 
 #define MSC_MASS_STORAGE_RESET_COMMAND 0xFF
 extern int fraucheky_enabled (void);
+extern void fraucheky_init (void);
 extern void fraucheky_main (void);
 
 extern void fraucheky_setup_endpoints_for_interface (struct usb_dev *dev, int stop);
@@ -41,10 +42,6 @@ usb_device_reset (struct usb_dev *dev)
   /* Initialize Endpoint 0.  */
   usb_lld_setup_endp (dev, ENDP0, 1, 1);
 
-  /* Stop the interface */
-  for (i = 0; i < NUM_INTERFACES; i++)
-    setup_endpoints_for_interface (dev, i, 1);
-
   /* Notify upper layer.  */
   chopstx_mutex_lock (&usb_mtx);
   bDeviceState = USB_DEVICE_STATE_ATTACHED;
@@ -307,6 +304,7 @@ main (int argc, char **argv)
   bDeviceState = USB_DEVICE_STATE_UNCONNECTED;
   usb_thd = chopstx_create (PRIO_USB, STACK_ADDR_USB, STACK_SIZE_USB,
 			    usb_main, NULL);
+  fraucheky_init ();
   while (bDeviceState != USB_DEVICE_STATE_CONFIGURED)
     chopstx_usec_wait (250*1000);
   fraucheky_main ();

mcu/chx-stm32f103.c

@@ -6,7 +6,12 @@ extern int chx_allow_sleep;
 
 #define STM32_PLLSRC		STM32_PLLSRC_HSE
 #define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-
+#ifndef STM32_ADCPRE
+#define STM32_ADCPRE		STM32_ADCPRE_DIV6
+#endif
+#ifndef STM32_USBPRE
+#define STM32_USBPRE		STM32_USBPRE_DIV1P5
+#endif
 
 static void
 configure_clock (int high)
@@ -16,16 +21,16 @@ configure_clock (int high)
 
   if (high)
     {
-      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE_DIV1P5
+      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE
 	| STM32_PLLMUL | STM32_PLLXTPRE	| STM32_PLLSRC
-	| STM32_ADCPRE_DIV6 | STM32_PPRE2_DIV1
+	| STM32_ADCPRE | STM32_PPRE2_DIV1
 	| STM32_PPRE1_DIV2 | STM32_HPRE_DIV1;
 
       cfg_sw = RCC_CFGR_SW_PLL;
     }
   else
     {
-      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE_DIV1P5
+      cfg = STM32_MCO_NOCLOCK | STM32_USBPRE
 	| STM32_PLLMUL | STM32_PLLXTPRE	| STM32_PLLSRC
 	| STM32_ADCPRE_DIV8 | STM32_PPRE2_DIV16
 	| STM32_PPRE1_DIV16 | STM32_HPRE_DIV8;

mcu/clk_gpio_init-stm32.c

@@ -43,9 +43,13 @@
 #define STM32_SW		STM32_SW_PLL
 #define STM32_HPRE		STM32_HPRE_DIV1
 #define STM32_PPRE2		STM32_PPRE2_DIV1
+#ifndef STM32_ADCPRE
 #define STM32_ADCPRE		STM32_ADCPRE_DIV6
+#endif
 #define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
+#ifndef STM32_USBPRE
+#define STM32_USBPRE		STM32_USBPRE_DIV1P5
+#endif
 
 #define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
 #define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)

mcu/stm32.h

@@ -127,6 +127,7 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE;
 #define STM32_ADCPRE_DIV8	(3 << 14)
 
 #define STM32_USBPRE_DIV1P5     (0 << 22)
+#define STM32_USBPRE_DIV2       (3 << 22) /* Not for STM32, but GD32F103 */
 
 #define STM32_MCO_NOCLOCK	(0 << 24)
 

mcu/sys-stm32f103.c

@@ -1,7 +1,7 @@
 /*
  * sys-stm32f103.c - system routines for the initial page for STM32F103.
  *
- * Copyright (C) 2013, 2014, 2015, 2016, 2017
+ * Copyright (C) 2013, 2014, 2015, 2016, 2017, 2018
  *               Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
@@ -82,7 +82,7 @@ usb_lld_sys_init (void)
     {
       usb_lld_sys_shutdown ();
       /* Disconnect requires SE0 (>= 2.5uS).  */
-      wait (300);
+      wait (5*MHZ);
     }
 
   usb_cable_config (1);
@@ -256,6 +256,9 @@ flash_protect (void)
       FLASH->OPTKEYR = FLASH_KEY1;
       FLASH->OPTKEYR = FLASH_KEY2;
 
+      while (!(FLASH->CR & FLASH_CR_OPTWRE))
+	;
+
       FLASH->CR |= FLASH_CR_OPTER;
       FLASH->CR |= FLASH_CR_STRT;
 

mcu/usb-stm32f103.c

@@ -339,6 +339,9 @@ void usb_lld_init (struct usb_dev *dev, uint8_t feature)
 
   /* Clear Interrupt Status Register, and enable interrupt for USB */
   st103_set_istr (0);
+
+  st103_set_btable ();
+
   st103_set_cntr (CNTR_CTRM | CNTR_OVRM | CNTR_ERRM
 		  | CNTR_WKUPM | CNTR_SUSPM | CNTR_RESETM);
 
@@ -906,7 +909,6 @@ void usb_lld_reset (struct usb_dev *dev, uint8_t feature)
 {
   usb_lld_set_configuration (dev, 0);
   dev->feature = feature;
-  st103_set_btable ();
   st103_set_daddr (0);
 }