Compare commits
24 Commits
release/0.
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release/0.
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1
.gitignore
vendored
1
.gitignore
vendored
@@ -1,4 +1,3 @@
|
||||
*/board.h
|
||||
*/build
|
||||
*/.dep
|
||||
doc/chopstx.info
|
||||
|
||||
32
AUTHORS
Normal file
32
AUTHORS
Normal file
@@ -0,0 +1,32 @@
|
||||
Aidan Thornton:
|
||||
Added Maple Mini support.
|
||||
board/board-maple-mini.h
|
||||
|
||||
Kaz Kojima:
|
||||
Added STM32 Primer2 support.
|
||||
board/board-stm32-primer2.h
|
||||
|
||||
Kenji Rikitake:
|
||||
Added ST Dongle support.
|
||||
board/board-st-dongle.h
|
||||
Added ST Nucleo F103 support.
|
||||
board/board-st-nucleo-f103.h
|
||||
|
||||
Kiwamu Okabe:
|
||||
Wrote an OpenOCD scirpt:
|
||||
example-fsm-55/stlink-v2.cfg
|
||||
|
||||
NIIBE Yutaka:
|
||||
Write the library:
|
||||
chopstx.c, eventflag.c, entry.c, clk_gpio_init.c
|
||||
chopstx.h, eventflag.h
|
||||
Draw the logo:
|
||||
chopstx.svg, chopstx.png
|
||||
Write examples:
|
||||
example-led, example-cdc, example-fsm-55
|
||||
Write board:
|
||||
board-fst-01.h, board-fst-01-00.h,
|
||||
board-olimex-stm32-h103.h, board-stm8s-discovery.h
|
||||
board-cq-starm.h, board-stbee-mini.h, board-stbee.h,
|
||||
|
||||
board-stm32f0-discovery.h, board-fsm-55.h
|
||||
87
ChangeLog
87
ChangeLog
@@ -1,7 +1,94 @@
|
||||
2015-07-31 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* VERSION: 0.08.
|
||||
* doc/chopstx.texi (VERSION): 0.08.
|
||||
|
||||
* example-fsm-55/Makefile (DEFS): Remove HAVE_SYS_H.
|
||||
Add MAKE_ENTRY_PUBLIC.
|
||||
* example-fsm-55/hacker-emblem.ld: Put vectors on ROM.
|
||||
* example-fsm-55/sys.c: No system services.
|
||||
* entry.c (entry): Can be public.
|
||||
* clk_gpio_init.c [MCU_STM32F0] (clock_init): Don't change CFGR1.
|
||||
|
||||
2015-07-30 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* board/board-st-nucleo-f103.h: New. Contributed by Kenji
|
||||
Rikitake.
|
||||
|
||||
2015-07-29 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* board/board-st-dongle.h: New. Contributed by Kenji Rikitake.
|
||||
|
||||
* board/board-*.h (FLASH_PAGE_SIZE): Remove.
|
||||
|
||||
2015-07-28 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* example-cdc/usb_stm32f103.c: Update from Gnuk.
|
||||
* example-cdc/usb_lld.h: Ditto.
|
||||
* example-cdc/usb-cdc.c: Follow the change.
|
||||
|
||||
2015-07-15 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* VERSION: 0.07.
|
||||
* doc/chopstx.texi (VERSION): 0.07.
|
||||
|
||||
2015-07-14 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* board/board-*.h (BOARD_ID): New.
|
||||
* example-cdc/sys.c (sys_board_id): New.
|
||||
* example-cdc/sample.ld (.sys.board_id): New.
|
||||
(__flash_start__, __flash_end__): Remove.
|
||||
* entry.c [HAVE_SYS_H] (vector_table): By undefining STM32F10X_MD,
|
||||
prepare for high density device even compiled for MD device.
|
||||
|
||||
2015-07-13 Kaz Kojima <kkojima@rr.iij4u.or.jp>
|
||||
|
||||
* board/board-stm32-primer2.h: Update.
|
||||
* entry.c (vector_table): Less or more.
|
||||
|
||||
2015-07-13 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* board/board-*.h (BOARD_NAME): New.
|
||||
(STM32F10X_MD): Define for medium-density devices.
|
||||
* example-led/sys.c, sample.ld: Update.
|
||||
* example-fsm-55/sys.c, hacker-emblem.ld: Update.
|
||||
* example-cdc/sys.c (sys_board_name): New.
|
||||
* example-cdc/sample.ld: Update.
|
||||
|
||||
2015-07-08 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* VERSION: 0.06.
|
||||
* doc/chopstx.texi (VERSION): 0.06.
|
||||
|
||||
2015-07-07 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* example-fsm-55/sys.c: Include clk_gpio_init.c.
|
||||
* board/board-stm32f0-discovery.h, board/board-fsm-55.h: Update.
|
||||
* clk_gpio_init.c (gpio_init): Use VAL_GPIO_LED_*.
|
||||
|
||||
2015-06-29 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* board/board-cq-starm.h: New for CQ STARM.
|
||||
|
||||
* clk_gpio_init.c (gpio_init): LED is mandatory, but USB enabler
|
||||
is optional.
|
||||
* board/*.h: Update.
|
||||
|
||||
2015-06-22 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
* clk_gpio_init.c: New, adding ports E/F/G.
|
||||
* entry.c: Include clk_gpio.init.c if not HAVE_SYS_H.
|
||||
* example-led/sys.c: Include clk_gpio_init.c.
|
||||
* example-cdc/sys.c: Ditto.
|
||||
|
||||
* board/board-stm32-primer2.h: New from Kaz Kojima.
|
||||
|
||||
2015-04-20 Niibe Yutaka <gniibe@fsij.org>
|
||||
|
||||
Merge cortex-m0-support branch.
|
||||
|
||||
* VERSION: 0.05.
|
||||
|
||||
* example-led/sys.c (gpio_init): Support MCU_STM32F0.
|
||||
(reset): Support __ARM_ARCH_6M__.
|
||||
* example-led/sample.ld: Change for Cortex-M0.
|
||||
|
||||
41
NEWS
41
NEWS
@@ -1,5 +1,46 @@
|
||||
NEWS - Noteworthy changes
|
||||
|
||||
|
||||
* Major changes in Chopstx 0.08
|
||||
|
||||
Released 2015-07-31
|
||||
|
||||
** New board support: ST Nucleo F103
|
||||
It is contributed by Kenji Rikitake.
|
||||
|
||||
** New board support: ST Dongle
|
||||
It is contributed by Kenji Rikitake.
|
||||
It's the ST-Link/V2-1 part of ST Nucleo F103.
|
||||
|
||||
|
||||
* Major changes in Chopstx 0.07
|
||||
|
||||
Released 2015-07-15
|
||||
|
||||
** New Board macro definitions
|
||||
Each board-*.h should have BOARD_ID and BOARD_NAME now.
|
||||
FLASH_PAGE_SIZE and NEUG_ADC_SETTING2_* are deprecated.
|
||||
|
||||
** New sys.c (2.1)
|
||||
Flash memory size is probed at runtime now. System
|
||||
service flash pages now include sys_board_id and sys_board_name.
|
||||
|
||||
|
||||
* Major changes in Chopstx 0.06
|
||||
|
||||
Released 2015-07-08
|
||||
|
||||
** New file: clk_gpio_init.c
|
||||
To avoid duplication of code, clock and GPIO initialization code
|
||||
is now in this file.
|
||||
|
||||
** New board support: STM32 Primer2
|
||||
It is contributed by Kaz Kojima.
|
||||
|
||||
** New board support: CQ STARM
|
||||
The old board which was "published" by CQ Publishing in 2008 is added.
|
||||
|
||||
|
||||
* Major changes in Chopstx 0.05
|
||||
|
||||
Released 2015-04-20, by NIIBE Yutaka
|
||||
|
||||
7
README
7
README
@@ -1,6 +1,6 @@
|
||||
Chopstx - Threads and only Threads
|
||||
Version 0.05
|
||||
2015-04-20
|
||||
Version 0.08
|
||||
2015-07-31
|
||||
Niibe Yutaka
|
||||
Flying Stone Technology
|
||||
|
||||
@@ -35,6 +35,9 @@ USB CDC-ACM function. You can build it like:
|
||||
$ ln -s ../board/board-olimex-stm32-h103.h board.h
|
||||
$ make
|
||||
|
||||
For a specific board named FSM-55, an example of LED matrix dynamic
|
||||
driver is provided. See the directory: example-fsm-55.
|
||||
|
||||
|
||||
Future Works
|
||||
============
|
||||
|
||||
46
board/board-cq-starm.h
Normal file
46
board/board-cq-starm.h
Normal file
@@ -0,0 +1,46 @@
|
||||
#define BOARD_NAME "CQ STARM"
|
||||
#define BOARD_ID 0xc5480875
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
#define GPIO_LED_BASE GPIOC_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 6
|
||||
#undef GPIO_USB_BASE /* No external DISCONNECT/RENUM circuit. */
|
||||
#define GPIO_OTHER_BASE GPIOA_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA0 - input with pull-up. AN0
|
||||
* PA1 - input with pull-up. AN1
|
||||
* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
|
||||
* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
|
||||
* ------------------------ Default
|
||||
* PAx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_OTHER_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_OTHER_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_OTHER_CRH 0x88811888 /* PA15...PA8 */
|
||||
|
||||
/*
|
||||
* Port C setup.
|
||||
* PC0 - Push Pull output 50MHz.
|
||||
* PC1 - Push Pull output 50MHz.
|
||||
* Everything input with pull-up except:
|
||||
* PC4 - Normal input (ADC_IN14 : VoutY of LIS344ALH).
|
||||
* PC5 - Normal input (ADC_IN15 : VoutZ of LIS344ALH).
|
||||
* PC6 - Push Pull output (LED).
|
||||
* (PC9 - SDCard CD)
|
||||
* (PC12 - SDCard CS)
|
||||
* PC14 - Normal input (XTAL).
|
||||
* PC15 - Normal input (XTAL).
|
||||
*/
|
||||
#define VAL_GPIO_LED_CRL 0x83448833 /* PC7...PC0 */
|
||||
#define VAL_GPIO_LED_CRH 0x44888888 /* PC15...PC8 */
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFFFFF
|
||||
|
||||
#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPCEN)
|
||||
#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPCRST)
|
||||
@@ -1,3 +1,6 @@
|
||||
#define BOARD_NAME "FSM-55"
|
||||
#define BOARD_ID 0x83433c76
|
||||
|
||||
/*
|
||||
* Running at 48MHz with HSI as clock source.
|
||||
*
|
||||
@@ -6,32 +9,30 @@
|
||||
/* __ARM_ARCH_6M__ */
|
||||
|
||||
|
||||
#define FLASH_PAGE_SIZE 1024
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HSICLK 8000000
|
||||
|
||||
#define GPIO_LED_SET_TO_EMIT 5
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 5
|
||||
#define GPIO_OTHER_BASE GPIOF_BASE /* USER BUTTON */
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA5 - ON (LED 1:ON 0:OFF)
|
||||
* PA4 - Pull DOWN
|
||||
*/
|
||||
#define VAL_GPIO_MODER 0x00145555 /* Output Pin0-7, Pin9 and Pin10 */
|
||||
#define VAL_GPIO_OTYPER 0x0000001f /* Open-drain for Pin0-4, Push-Pull*/
|
||||
#define VAL_GPIO_OSPEEDR 0x003cffff /* High speed */
|
||||
#define VAL_GPIO_PUPDR 0x00000000 /* No pull-up/pull-down */
|
||||
#define VAL_GPIO_LED_MODER 0x00145555 /* Output Pin0-7, Pin9 and Pin10 */
|
||||
#define VAL_GPIO_LED_OTYPER 0x0000001f /* Open-drain for Pin0-4, Push-Pull*/
|
||||
#define VAL_GPIO_LED_OSPEEDR 0x003cffff /* High speed */
|
||||
#define VAL_GPIO_LED_PUPDR 0x00000000 /* No pull-up/pull-down */
|
||||
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
|
||||
#define RCC_ENR_IOP_EN (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPFEN)
|
||||
#define RCC_RSTR_IOP_RST (RCC_AHBRSTR_IOPARST | RCC_AHBRSTR_IOPFRST)
|
||||
|
||||
/* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */
|
||||
|
||||
#define GPIO_OTHER_BASE GPIOF_BASE /* USER BUTTON */
|
||||
/*
|
||||
* Port F setup.
|
||||
* PF0 - USER Button
|
||||
|
||||
@@ -1,11 +1,17 @@
|
||||
#define FLASH_PAGE_SIZE 1024
|
||||
#define BOARD_NAME "FST-01-00"
|
||||
#define BOARD_ID 0x613870a9
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
#define GPIO_USB_SET_TO_ENABLE 10
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 8
|
||||
#define GPIO_USB_BASE GPIOA_BASE
|
||||
#define GPIO_USB_SET_TO_ENABLE 10
|
||||
#undef GPIO_OTHER_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
@@ -18,14 +24,9 @@
|
||||
* ------------------------ Default
|
||||
* PAx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_CRH 0x88811383 /* PA15...PA8 */
|
||||
|
||||
#define GPIO_USB_BASE GPIOA_BASE
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_LED_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_LED_CRH 0x88811383 /* PA15...PA8 */
|
||||
|
||||
#define RCC_ENR_IOP_EN RCC_APB2ENR_IOPAEN
|
||||
#define RCC_RSTR_IOP_RST RCC_APB2RSTR_IOPARST
|
||||
|
||||
/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */
|
||||
|
||||
@@ -1,24 +1,18 @@
|
||||
#define FLASH_PAGE_SIZE 1024
|
||||
#define BOARD_NAME "FST-01"
|
||||
#define BOARD_ID 0x696886af
|
||||
/* echo -n "FST-01" | sha256sum | sed -e 's/^.*\(........\) -$/\1/' */
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 6
|
||||
#define STM32_HSECLK 12000000
|
||||
|
||||
#define GPIO_USB_SET_TO_ENABLE 10
|
||||
#define GPIO_LED_BASE GPIOB_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 0
|
||||
|
||||
/* For pin-cir settings of Gnuk */
|
||||
#define TIMx TIM2
|
||||
#define INTR_REQ_TIM TIM2_IRQ
|
||||
#define AFIO_EXTICR_INDEX 0
|
||||
#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA
|
||||
#define EXTI_PR EXTI_PR_PR2
|
||||
#define EXTI_IMR EXTI_IMR_MR2
|
||||
#define EXTI_FTSR_TR EXTI_FTSR_TR2
|
||||
#define INTR_REQ_EXTI EXTI2_IRQ
|
||||
#define ENABLE_RCC_APB1
|
||||
#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM2EN
|
||||
#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM2RST
|
||||
#define GPIO_USB_BASE GPIOA_BASE
|
||||
#define GPIO_USB_SET_TO_ENABLE 10
|
||||
#undef GPIO_OTHER_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
@@ -40,9 +34,9 @@
|
||||
* PA14 - input with pull-up.
|
||||
* PA15 - input with pull-up.
|
||||
*/
|
||||
#define VAL_GPIO_ODR 0xFFFFE7FD
|
||||
#define VAL_GPIO_CRL 0xBBB38888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_CRH 0x88811388 /* PA15...PA8 */
|
||||
#define VAL_GPIO_USB_ODR 0xFFFFE7FD
|
||||
#define VAL_GPIO_USB_CRL 0xBBB38888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_USB_CRH 0x88811388 /* PA15...PA8 */
|
||||
|
||||
/*
|
||||
* Port B setup.
|
||||
@@ -55,16 +49,36 @@
|
||||
#define VAL_GPIO_LED_CRL 0x88888883 /* PA7...PA0 */
|
||||
#define VAL_GPIO_LED_CRH 0x88888888 /* PA15...PA8 */
|
||||
|
||||
#define GPIO_USB_BASE GPIOA_BASE
|
||||
#define GPIO_LED_BASE GPIOB_BASE
|
||||
|
||||
#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
|
||||
#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
|
||||
|
||||
/* NeuG settings for ADC2. */
|
||||
#define NEUG_ADC_SETTING2_SMPR1 0
|
||||
#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5) \
|
||||
| ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5)
|
||||
#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0) \
|
||||
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9)
|
||||
#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
|
||||
/*
|
||||
* Board specific information other than clock and GPIO initial
|
||||
* setting should not be in board-*.h, but each driver should include
|
||||
* information by itself.
|
||||
*
|
||||
* Please see NeuG's ADC driver how board specific handling is done.
|
||||
*
|
||||
* Given the situation of Chopstx's boards support, which is not that
|
||||
* huge, this works well. If scalability and flexibility will matter,
|
||||
* we will need something like device tree in which boot process can
|
||||
* pass information to application program.
|
||||
*
|
||||
* Following constants are here, because experimental CIR driver is
|
||||
* written before this design decision of Chopstx.
|
||||
*
|
||||
* Those will be removed soon, once such an driver will be improved
|
||||
* in new style.
|
||||
*/
|
||||
/* For pin-cir settings of Gnuk */
|
||||
#define TIMx TIM2
|
||||
#define INTR_REQ_TIM TIM2_IRQ
|
||||
#define AFIO_EXTICR_INDEX 0
|
||||
#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA
|
||||
#define EXTI_PR EXTI_PR_PR2
|
||||
#define EXTI_IMR EXTI_IMR_MR2
|
||||
#define EXTI_FTSR_TR EXTI_FTSR_TR2
|
||||
#define INTR_REQ_EXTI EXTI2_IRQ
|
||||
#define ENABLE_RCC_APB1
|
||||
#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM2EN
|
||||
#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM2RST
|
||||
|
||||
@@ -1,11 +1,30 @@
|
||||
#define FLASH_PAGE_SIZE 1024
|
||||
#define BOARD_NAME "Maple Mini"
|
||||
#define BOARD_ID 0x7a445272
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
#define GPIO_USB_CLEAR_TO_ENABLE 9
|
||||
#define GPIO_LED_BASE GPIOB_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 1
|
||||
#define GPIO_USB_BASE GPIOB_BASE
|
||||
#define GPIO_USB_CLEAR_TO_ENABLE 9
|
||||
#define GPIO_OTHER_BASE GPIOA_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA0 - input with pull-up. AN0
|
||||
* PA1 - input with pull-up. AN1
|
||||
* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
|
||||
* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
|
||||
* ------------------------ Default
|
||||
* PAx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_OTHER_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_OTHER_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_OTHER_CRH 0x88811888 /* PA15...PA8 */
|
||||
|
||||
/*
|
||||
* Port B setup.
|
||||
@@ -14,14 +33,9 @@
|
||||
* ------------------------ Default
|
||||
* PBx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_CRL 0x88888838 /* PB7...PB0 */
|
||||
#define VAL_GPIO_CRH 0x88888838 /* PB15...PB8 */
|
||||
|
||||
#define GPIO_USB_BASE GPIOB_BASE
|
||||
#define GPIO_LED_BASE GPIOB_BASE
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_LED_CRL 0x88888838 /* PB7...PB0 */
|
||||
#define VAL_GPIO_LED_CRH 0x88888838 /* PB15...PB8 */
|
||||
|
||||
#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
|
||||
#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
|
||||
|
||||
/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */
|
||||
|
||||
@@ -1,11 +1,17 @@
|
||||
#define FLASH_PAGE_SIZE 1024
|
||||
#define BOARD_NAME "Olimex STM32-H103"
|
||||
#define BOARD_ID 0xf92bb594
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
#define GPIO_USB_CLEAR_TO_ENABLE 11
|
||||
#define GPIO_LED_BASE GPIOC_BASE
|
||||
#define GPIO_LED_CLEAR_TO_EMIT 12
|
||||
#define GPIO_USB_BASE GPIOC_BASE
|
||||
#define GPIO_USB_CLEAR_TO_ENABLE 11
|
||||
#undef GPIO_OTHER_BASE
|
||||
|
||||
/*
|
||||
* Port C setup.
|
||||
@@ -18,12 +24,9 @@
|
||||
* ------------------------ Default
|
||||
* PCx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_CRL 0x44888888 /* PC7...PC0 */
|
||||
#define VAL_GPIO_CRH 0x88837888 /* PC15...PC8 */
|
||||
|
||||
#define GPIO_USB_BASE GPIOC_BASE
|
||||
#define GPIO_LED_BASE GPIOC_BASE
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_LED_CRL 0x44888888 /* PC7...PC0 */
|
||||
#define VAL_GPIO_LED_CRH 0x88837888 /* PC15...PC8 */
|
||||
|
||||
#define RCC_ENR_IOP_EN RCC_APB2ENR_IOPCEN
|
||||
#define RCC_RSTR_IOP_RST RCC_APB2RSTR_IOPCRST
|
||||
|
||||
33
board/board-st-dongle.h
Normal file
33
board/board-st-dongle.h
Normal file
@@ -0,0 +1,33 @@
|
||||
#define BOARD_NAME "ST Dongle"
|
||||
/* echo -n "ST Dongle" | shasum -a 256 | sed -e 's/^.*\(........\) -$/\1/' */
|
||||
#define BOARD_ID 0x2cd4e471
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 9
|
||||
#define GPIO_USB_BASE GPIOA_BASE
|
||||
#define GPIO_USB_SET_TO_ENABLE 15
|
||||
#undef GPIO_OTHER_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA0 - input with pull-up. AN0
|
||||
* PA1 - input with pull-up. AN1
|
||||
* PA9 - Push pull output 50MHz (LED 1:ON 0:OFF)
|
||||
* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
|
||||
* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
|
||||
* PA15 - Push pull output 50MHz (USB 1:ON 0:OFF)
|
||||
* ------------------------ Default
|
||||
* PAx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_LED_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_LED_CRH 0x38811838 /* PA15...PA8 */
|
||||
|
||||
#define RCC_ENR_IOP_EN RCC_APB2ENR_IOPAEN
|
||||
#define RCC_RSTR_IOP_RST RCC_APB2RSTR_IOPARST
|
||||
45
board/board-st-nucleo-f103.h
Normal file
45
board/board-st-nucleo-f103.h
Normal file
@@ -0,0 +1,45 @@
|
||||
#define BOARD_NAME "ST Nucleo F103"
|
||||
#define BOARD_ID 0x9b87c16d
|
||||
|
||||
/*
|
||||
* Please add X3 and USB cable to ST Nucleo F103.
|
||||
*
|
||||
* Solder X3 XTAL of 8MHz (and put C33 and C34 of 22pF).
|
||||
* Solder the bridges for R35 and R37, since it's 0 ohm.
|
||||
*
|
||||
* (Optional) Remove SB54 and SB55.
|
||||
*
|
||||
* At CN10, connect USB cable
|
||||
* Vbus RED --> 10 NC ----------> CN7 (6 E5V)
|
||||
* D+ GREEN --> 12 PA11 ---[1K5]--> CN6 (4 3V3)
|
||||
* D- WHITE --> 14 PA12
|
||||
* GND BLACK --> 20 GND
|
||||
*/
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 5
|
||||
#undef GPIO_USB_BASE /* No external DISCONNECT/RENUM circuit. */
|
||||
#undef GPIO_OTHER_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA0 - input with pull-up. AN0
|
||||
* PA1 - input with pull-up. AN1
|
||||
* PA5 - Push pull output 50MHz (LED 1:ON 0:OFF)
|
||||
* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
|
||||
* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
|
||||
* ------------------------ Default
|
||||
* PAx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_LED_CRL 0x88388888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_LED_CRH 0x88811888 /* PA15...PA8 */
|
||||
|
||||
#define RCC_ENR_IOP_EN RCC_APB2ENR_IOPAEN
|
||||
#define RCC_RSTR_IOP_RST RCC_APB2RSTR_IOPARST
|
||||
@@ -1,11 +1,16 @@
|
||||
#define FLASH_PAGE_SIZE 1024
|
||||
#define BOARD_NAME "STBee Mini"
|
||||
#define BOARD_ID 0x1f341961
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 6
|
||||
#define STM32_HSECLK 12000000
|
||||
|
||||
#define GPIO_USB_SET_TO_ENABLE 14
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
#define GPIO_LED_CLEAR_TO_EMIT 13
|
||||
#define GPIO_USB_BASE GPIOA_BASE
|
||||
#define GPIO_USB_SET_TO_ENABLE 14
|
||||
|
||||
#if defined(PINPAD_CIR_SUPPORT) || defined(PINPAD_DIAL_SUPPORT)
|
||||
#define HAVE_7SEGLED 1
|
||||
@@ -49,19 +54,20 @@
|
||||
* PA14 - Push pull output (USB ENABLE 0:DISABLE 1:ENABLE)
|
||||
* PA15 - Open Drain output (LED2 0:ON 1:OFF)
|
||||
*/
|
||||
#define VAL_GPIO_ODR 0xFFFFE77F
|
||||
#define VAL_GPIO_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_CRH 0x63611888 /* PA15...PA8 */
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFE77F
|
||||
#define VAL_GPIO_LED_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_LED_CRH 0x63611888 /* PA15...PA8 */
|
||||
|
||||
#define GPIO_OTHER_BASE GPIOB_BASE
|
||||
/*
|
||||
* Port B setup.
|
||||
* PB0 - Push pull output (LED 1:ON 0:OFF)
|
||||
* ------------------------ Default
|
||||
* PBx - input with pull-up.
|
||||
*/
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_LED_CRL 0x88888888 /* PB7...PB0 */
|
||||
#define VAL_GPIO_LED_CRH 0x66666666 /* PB15...PB8 */
|
||||
#define VAL_GPIO_OTHER_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_OTHER_CRL 0x88888888 /* PB7...PB0 */
|
||||
#define VAL_GPIO_OTHER_CRH 0x66666666 /* PB15...PB8 */
|
||||
|
||||
/* Port B setup. */
|
||||
#define GPIOB_CIR 0
|
||||
@@ -93,23 +99,15 @@
|
||||
* PA14 - Push pull output (USB ENABLE 0:DISABLE 1:ENABLE)
|
||||
* PA15 - Open Drain output (LED2 0:ON 1:OFF)
|
||||
*/
|
||||
#define VAL_GPIO_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_CRH 0x63611888 /* PA15...PA8 */
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_LED_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_LED_CRH 0x63611888 /* PA15...PA8 */
|
||||
|
||||
#undef GPIO_OTHER_BASE
|
||||
|
||||
#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN)
|
||||
#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_AFIORST)
|
||||
#endif
|
||||
|
||||
|
||||
#define GPIO_USB_BASE GPIOA_BASE
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
#define AFIO_MAPR_SOMETHING AFIO_MAPR_SWJ_CFG_DISABLE
|
||||
|
||||
/* NeuG settings for ADC2. */
|
||||
#define NEUG_ADC_SETTING2_SMPR1 0
|
||||
#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5) \
|
||||
| ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5)
|
||||
#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1) \
|
||||
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2)
|
||||
#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
|
||||
|
||||
@@ -1,11 +1,15 @@
|
||||
#define FLASH_PAGE_SIZE 2048
|
||||
#define BOARD_NAME "STBee"
|
||||
#define BOARD_ID 0x945c37e8
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 6
|
||||
#define STM32_HSECLK 12000000
|
||||
|
||||
#define GPIO_USB_CLEAR_TO_ENABLE 3
|
||||
#define GPIO_LED_BASE GPIOD_BASE
|
||||
#define GPIO_LED_CLEAR_TO_EMIT 4
|
||||
#define GPIO_USB_BASE GPIOD_BASE
|
||||
#define GPIO_USB_CLEAR_TO_ENABLE 3
|
||||
#define GPIO_OTHER_BASE GPIOA_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
@@ -25,18 +29,6 @@
|
||||
* PD3 - Push pull output (USB_DISC 1:USB-DISABLE 0:USB-ENABLE) 2MHz
|
||||
* PD4 - Open Drain output 2MHz (LED1).
|
||||
*/
|
||||
#define VAL_GPIO_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_CRL 0x88862888 /* PD7...PD0 */
|
||||
#define VAL_GPIO_CRH 0x88888888 /* PD15...PD8 */
|
||||
|
||||
#define GPIO_USB_BASE GPIOD_BASE
|
||||
#define GPIO_LED_BASE GPIOD_BASE
|
||||
#define GPIO_OTHER_BASE GPIOA_BASE
|
||||
|
||||
/* NeuG settings for ADC2. */
|
||||
#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \
|
||||
| ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5)
|
||||
#define NEUG_ADC_SETTING2_SMPR2 0
|
||||
#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) \
|
||||
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11)
|
||||
#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_LED_CRL 0x88862888 /* PD7...PD0 */
|
||||
#define VAL_GPIO_LED_CRH 0x88888888 /* PD15...PD8 */
|
||||
|
||||
56
board/board-stm32-primer2.h
Normal file
56
board/board-stm32-primer2.h
Normal file
@@ -0,0 +1,56 @@
|
||||
#define BOARD_NAME "STM32 Primer2"
|
||||
#define BOARD_ID 0x21e5798d
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 6
|
||||
#define STM32_HSECLK 12000000
|
||||
|
||||
#define GPIO_LED_BASE GPIOE_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 0
|
||||
#define GPIO_USB_BASE GPIOD_BASE
|
||||
#define GPIO_USB_CLEAR_TO_ENABLE 3
|
||||
#define GPIO_OTHER_BASE GPIOA_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA0 - input with pull-up. AN0
|
||||
* PA1 - input with pull-up. AN1
|
||||
* PA8 - Input with pull-down (PBUTTON).
|
||||
* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
|
||||
* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
|
||||
* ------------------------ Default
|
||||
* PAx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_OTHER_ODR 0xFFFFE6FF
|
||||
#define VAL_GPIO_OTHER_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_OTHER_CRH 0x88811888 /* PA15...PA8 */
|
||||
|
||||
/*
|
||||
* Port D setup.
|
||||
* PD3 - Push pull output 50MHz (USB 1:ON 0:OFF)
|
||||
* ------------------------ Default
|
||||
* PDx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_USB_ODR 0xFFFFFFFF
|
||||
#define VAL_GPIO_USB_CRL 0x88883888 /* PD7...PD0 */
|
||||
#define VAL_GPIO_USB_CRH 0x88888888 /* PD15...PD8 */
|
||||
|
||||
/*
|
||||
* Port E setup.
|
||||
* PE0 - Push pull output (LED 1:ON 0:OFF)
|
||||
* PE1 - Push pull output (LED 1:ON 0:OFF)
|
||||
* PE3 - Input with pull-down (JOYSTICK L).
|
||||
* PE4 - Input with pull-down (JOYSTICK R).
|
||||
* PE5 - Input with pull-down (JOYSTICK U).
|
||||
* PE6 - Input with pull-down (JOYSTICK D).
|
||||
* ------------------------ Default
|
||||
* PEx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFFF87
|
||||
#define VAL_GPIO_LED_CRL 0x88888833 /* PE7...PE0 */
|
||||
#define VAL_GPIO_LED_CRH 0x88888888 /* PE15...PE8 */
|
||||
|
||||
#define RCC_ENR_IOP_EN \
|
||||
(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_IOPEEN)
|
||||
#define RCC_RSTR_IOP_RST \
|
||||
(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPDRST | RCC_APB2RSTR_IOPERST)
|
||||
@@ -1,3 +1,6 @@
|
||||
#define BOARD_NAME "STM32F0 Discovery"
|
||||
#define BOARD_ID 0xde4b4bc1
|
||||
|
||||
/*
|
||||
* Running at 48MHz with HSI as clock source.
|
||||
*
|
||||
@@ -6,25 +9,24 @@
|
||||
/* __ARM_ARCH_6M__ */
|
||||
|
||||
|
||||
#define FLASH_PAGE_SIZE 1024
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HSICLK 8000000
|
||||
|
||||
#define GPIO_LED_SET_TO_EMIT 8
|
||||
#define GPIO_LED_BASE GPIOC_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 8
|
||||
#define GPIO_OTHER_BASE GPIOA_BASE /* USER BUTTON */
|
||||
|
||||
/*
|
||||
* Port C setup.
|
||||
* PC9 - LED3 (LED 1:ON 0:OFF)
|
||||
* PC8 - LED4 (LED 1:ON 0:OFF)
|
||||
*/
|
||||
#define VAL_GPIO_MODER 0x00050000 /* Output Pin9 and Pin8 */
|
||||
#define VAL_GPIO_OTYPER 0x00000000 /* Push-Pull */
|
||||
#define VAL_GPIO_OSPEEDR 0x000f0000 /* High speed: Pin9 and Pin8 */
|
||||
#define VAL_GPIO_PUPDR 0x00000000 /* No pull-up/pull-down */
|
||||
#define VAL_GPIO_LED_MODER 0x00050000 /* Output Pin9 and Pin8 */
|
||||
#define VAL_GPIO_LED_OTYPER 0x00000000 /* Push-Pull */
|
||||
#define VAL_GPIO_LED_OSPEEDR 0x000f0000 /* High speed: Pin9 and Pin8 */
|
||||
#define VAL_GPIO_LED_PUPDR 0x00000000 /* No pull-up/pull-down */
|
||||
|
||||
#define GPIO_LED_BASE GPIOC_BASE
|
||||
|
||||
#if 0
|
||||
#define RCC_ENR_IOP_EN (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPCEN)
|
||||
@@ -36,7 +38,6 @@
|
||||
|
||||
/* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */
|
||||
|
||||
#define GPIO_OTHER_BASE GPIOA_BASE /* USER BUTTON */
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA0 - USER Button
|
||||
|
||||
@@ -1,11 +1,47 @@
|
||||
#define FLASH_PAGE_SIZE 1024
|
||||
#define BOARD_NAME "STM8S Discovery"
|
||||
#define BOARD_ID 0x2f0976bb
|
||||
|
||||
#define STM32F10X_MD /* Medium-density device */
|
||||
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
#undef GPIO_USB_CLEAR_TO_ENABLE
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
#define GPIO_LED_SET_TO_EMIT 8
|
||||
#undef GPIO_USB_BASE /* No external DISCONNECT/RENUM circuit. */
|
||||
#define GPIO_OTHER_BASE GPIOB_BASE
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA0 - input with pull-up. AN0
|
||||
* PA1 - input with pull-up. AN1
|
||||
* PA8 - Push pull output 10MHz (LED 1:ON 0:OFF)
|
||||
* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
|
||||
* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
|
||||
* ------------------------ Default
|
||||
* PAx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_LED_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_LED_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_LED_CRH 0x88811881 /* PA15...PA8 */
|
||||
|
||||
#define RCC_ENR_IOP_EN \
|
||||
(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
|
||||
#define RCC_RSTR_IOP_RST \
|
||||
(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)
|
||||
|
||||
/*
|
||||
* Port B setup.
|
||||
* PB4 - (TIM3_CH1) input with pull-up
|
||||
* PB5 - (TIM3_CH2) input with pull-up, connected to CIR module
|
||||
* Everything input with pull-up except:
|
||||
* PB0 - (TIM3_CH3) input with pull-down
|
||||
*/
|
||||
#define VAL_GPIO_OTHER_ODR 0xFFFFFFFE
|
||||
#define VAL_GPIO_OTHER_CRL 0x88888888 /* PB7...PB0 */
|
||||
#define VAL_GPIO_OTHER_CRH 0x88888888 /* PB15...PB8 */
|
||||
|
||||
|
||||
/* For pin-cir settings of Gnuk */
|
||||
#define TIMx TIM3
|
||||
@@ -21,39 +57,3 @@
|
||||
#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM3RST
|
||||
#define AFIO_MAPR_SOMETHING AFIO_MAPR_TIM3_REMAP_PARTIALREMAP
|
||||
/* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* PA0 - input with pull-up. AN0
|
||||
* PA1 - input with pull-up. AN1
|
||||
* PA8 - Push pull output 10MHz (LED 1:ON 0:OFF)
|
||||
* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
|
||||
* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
|
||||
* ------------------------ Default
|
||||
* PAx - input with pull-up
|
||||
*/
|
||||
#define VAL_GPIO_ODR 0xFFFFE7FF
|
||||
#define VAL_GPIO_CRL 0x88888888 /* PA7...PA0 */
|
||||
#define VAL_GPIO_CRH 0x88811881 /* PA15...PA8 */
|
||||
|
||||
#define GPIO_USB_BASE GPIOA_BASE
|
||||
#define GPIO_LED_BASE GPIOA_BASE
|
||||
|
||||
#define RCC_ENR_IOP_EN \
|
||||
(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
|
||||
#define RCC_RSTR_IOP_RST \
|
||||
(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)
|
||||
|
||||
/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */
|
||||
|
||||
#define GPIO_OTHER_BASE GPIOB_BASE
|
||||
/*
|
||||
* Port B setup.
|
||||
* PB4 - (TIM3_CH1) input with pull-up
|
||||
* PB5 - (TIM3_CH2) input with pull-up, connected to CIR module
|
||||
* Everything input with pull-up except:
|
||||
* PB0 - (TIM3_CH3) input with pull-down
|
||||
*/
|
||||
#define VAL_GPIO_OTHER_ODR 0xFFFFFFFE
|
||||
#define VAL_GPIO_OTHER_CRL 0x88888888 /* PB7...PB0 */
|
||||
#define VAL_GPIO_OTHER_CRH 0x88888888 /* PB15...PB8 */
|
||||
|
||||
367
clk_gpio_init.c
Normal file
367
clk_gpio_init.c
Normal file
@@ -0,0 +1,367 @@
|
||||
/*
|
||||
* clk_gpio_init.c - Clock and GPIO initialization.
|
||||
*
|
||||
* Copyright (C) 2015 Flying Stone Technology
|
||||
* Author: NIIBE Yutaka <gniibe@fsij.org>
|
||||
*
|
||||
* This file is a part of Chopstx, a thread library for embedded.
|
||||
*
|
||||
* Chopstx is free software: you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* Chopstx is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* As additional permission under GNU GPL version 3 section 7, you may
|
||||
* distribute non-source form of the Program without the copy of the
|
||||
* GNU GPL normally required by section 4, provided you inform the
|
||||
* receipents of GNU GPL by a written offer.
|
||||
*
|
||||
*/
|
||||
|
||||
#define STM32_SW_HSI (0 << 0)
|
||||
#define STM32_SW_PLL (2 << 0)
|
||||
#define STM32_PLLSRC_HSI (0 << 16)
|
||||
#define STM32_PLLSRC_HSE (1 << 16)
|
||||
|
||||
#define STM32_PLLXTPRE_DIV1 (0 << 17)
|
||||
#define STM32_PLLXTPRE_DIV2 (1 << 17)
|
||||
|
||||
#define STM32_HPRE_DIV1 (0 << 4)
|
||||
|
||||
#define STM32_PPRE1_DIV1 (0 << 8)
|
||||
#define STM32_PPRE1_DIV2 (4 << 8)
|
||||
|
||||
#define STM32_PPRE2_DIV1 (0 << 11)
|
||||
#define STM32_PPRE2_DIV2 (4 << 11)
|
||||
|
||||
#define STM32_ADCPRE_DIV4 (1 << 14)
|
||||
#define STM32_ADCPRE_DIV6 (2 << 14)
|
||||
|
||||
#define STM32_USBPRE_DIV1P5 (0 << 22)
|
||||
|
||||
#define STM32_MCO_NOCLOCK (0 << 24)
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSI
|
||||
#define STM32_FLASHBITS 0x00000011
|
||||
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
|
||||
#else
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_FLASHBITS 0x00000012
|
||||
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
|
||||
#endif
|
||||
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV6
|
||||
#define STM32_MCOSEL STM32_MCO_NOCLOCK
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
|
||||
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
|
||||
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
||||
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||
|
||||
|
||||
#define PERIPH_BASE 0x40000000
|
||||
#define APBPERIPH_BASE PERIPH_BASE
|
||||
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
||||
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
|
||||
|
||||
struct RCC {
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t CFGR;
|
||||
volatile uint32_t CIR;
|
||||
volatile uint32_t APB2RSTR;
|
||||
volatile uint32_t APB1RSTR;
|
||||
volatile uint32_t AHBENR;
|
||||
volatile uint32_t APB2ENR;
|
||||
volatile uint32_t APB1ENR;
|
||||
volatile uint32_t BDCR;
|
||||
volatile uint32_t CSR;
|
||||
#if defined(MCU_STM32F0)
|
||||
volatile uint32_t AHBRSTR;
|
||||
volatile uint32_t CFGR2;
|
||||
volatile uint32_t CFGR3;
|
||||
volatile uint32_t CR2;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
|
||||
static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
|
||||
|
||||
#define RCC_APB1ENR_USBEN 0x00800000
|
||||
#define RCC_APB1RSTR_USBRST 0x00800000
|
||||
|
||||
#define RCC_CR_HSION 0x00000001
|
||||
#define RCC_CR_HSIRDY 0x00000002
|
||||
#define RCC_CR_HSITRIM 0x000000F8
|
||||
#define RCC_CR_HSEON 0x00010000
|
||||
#define RCC_CR_HSERDY 0x00020000
|
||||
#define RCC_CR_PLLON 0x01000000
|
||||
#define RCC_CR_PLLRDY 0x02000000
|
||||
|
||||
#define RCC_CFGR_SWS 0x0000000C
|
||||
#define RCC_CFGR_SWS_HSI 0x00000000
|
||||
|
||||
#define RCC_AHBENR_CRCEN 0x0040
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
#define RCC_AHBRSTR_IOPARST 0x00020000
|
||||
#define RCC_AHBRSTR_IOPBRST 0x00040000
|
||||
#define RCC_AHBRSTR_IOPCRST 0x00080000
|
||||
#define RCC_AHBRSTR_IOPDRST 0x00100000
|
||||
#define RCC_AHBRSTR_IOPFRST 0x00400000
|
||||
|
||||
#define RCC_AHBENR_IOPAEN 0x00020000
|
||||
#define RCC_AHBENR_IOPBEN 0x00040000
|
||||
#define RCC_AHBENR_IOPCEN 0x00080000
|
||||
#define RCC_AHBENR_IOPDEN 0x00100000
|
||||
#define RCC_AHBENR_IOPFEN 0x00400000
|
||||
|
||||
#define RCC_APB2RSTR_SYSCFGRST 0x00000001
|
||||
#define RCC_APB2ENR_SYSCFGEN 0x00000001
|
||||
#else
|
||||
#define RCC_APB2RSTR_AFIORST 0x00000001
|
||||
#define RCC_APB2RSTR_IOPARST 0x00000004
|
||||
#define RCC_APB2RSTR_IOPBRST 0x00000008
|
||||
#define RCC_APB2RSTR_IOPCRST 0x00000010
|
||||
#define RCC_APB2RSTR_IOPDRST 0x00000020
|
||||
#define RCC_APB2RSTR_IOPERST 0x00000040
|
||||
#define RCC_APB2RSTR_IOPFRST 0x00000080
|
||||
#define RCC_APB2RSTR_IOPGRST 0x00000100
|
||||
|
||||
#define RCC_APB2ENR_AFIOEN 0x00000001
|
||||
#define RCC_APB2ENR_IOPAEN 0x00000004
|
||||
#define RCC_APB2ENR_IOPBEN 0x00000008
|
||||
#define RCC_APB2ENR_IOPCEN 0x00000010
|
||||
#define RCC_APB2ENR_IOPDEN 0x00000020
|
||||
#define RCC_APB2ENR_IOPEEN 0x00000040
|
||||
#define RCC_APB2ENR_IOPFEN 0x00000080
|
||||
#define RCC_APB2ENR_IOPGEN 0x00000100
|
||||
#endif
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
struct SYSCFG {
|
||||
volatile uint32_t CFGR1;
|
||||
uint32_t dummy0;
|
||||
volatile uint32_t EXTICR[4];
|
||||
volatile uint32_t CFGR2;
|
||||
};
|
||||
#define SYSCFG_CFGR1_MEM_MODE 0x03
|
||||
|
||||
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
|
||||
static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
|
||||
#endif
|
||||
|
||||
struct FLASH {
|
||||
volatile uint32_t ACR;
|
||||
volatile uint32_t KEYR;
|
||||
volatile uint32_t OPTKEYR;
|
||||
volatile uint32_t SR;
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t AR;
|
||||
volatile uint32_t RESERVED;
|
||||
volatile uint32_t OBR;
|
||||
volatile uint32_t WRPR;
|
||||
};
|
||||
|
||||
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
|
||||
static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
|
||||
|
||||
static void __attribute__((used))
|
||||
clock_init (void)
|
||||
{
|
||||
/* HSI setup */
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY))
|
||||
;
|
||||
/* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
|
||||
RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
|
||||
RCC->CFGR = 0;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
|
||||
;
|
||||
|
||||
#if !defined(MCU_STM32F0)
|
||||
/* HSE setup */
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY))
|
||||
;
|
||||
#endif
|
||||
|
||||
/* PLL setup */
|
||||
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
;
|
||||
|
||||
/* Clock settings */
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
|
||||
| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
|
||||
/*
|
||||
* We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
|
||||
*/
|
||||
|
||||
/* Flash setup */
|
||||
FLASH->ACR = STM32_FLASHBITS;
|
||||
|
||||
/* CRC */
|
||||
RCC->AHBENR |= RCC_AHBENR_CRCEN;
|
||||
|
||||
/* Switching on the configured clock source. */
|
||||
RCC->CFGR |= STM32_SW;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
;
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
|
||||
RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
|
||||
RCC->APB2RSTR = 0;
|
||||
|
||||
# if defined(HAVE_SYS_H)
|
||||
/* Use vectors on RAM */
|
||||
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
|
||||
# endif
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
struct GPIO {
|
||||
volatile uint32_t MODER;
|
||||
volatile uint16_t OTYPER;
|
||||
uint16_t dummy0;
|
||||
volatile uint32_t OSPEEDR;
|
||||
volatile uint32_t PUPDR;
|
||||
volatile uint16_t IDR;
|
||||
uint16_t dummy1;
|
||||
volatile uint16_t ODR;
|
||||
uint16_t dummy2;
|
||||
volatile uint16_t BSRR;
|
||||
uint16_t dummy3;
|
||||
volatile uint32_t LCKR;
|
||||
volatile uint32_t AFR[2];
|
||||
volatile uint16_t BRR;
|
||||
uint16_t dummy4;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOF ((struct GPIO *) GPIOF_BASE)
|
||||
#else
|
||||
struct AFIO
|
||||
{
|
||||
volatile uint32_t EVCR;
|
||||
volatile uint32_t MAPR;
|
||||
volatile uint32_t EXTICR[4];
|
||||
uint32_t RESERVED0;
|
||||
volatile uint32_t MAPR2;
|
||||
};
|
||||
|
||||
#define AFIO_BASE 0x40010000
|
||||
static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
|
||||
|
||||
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
|
||||
#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
|
||||
|
||||
|
||||
struct GPIO {
|
||||
volatile uint32_t CRL;
|
||||
volatile uint32_t CRH;
|
||||
volatile uint32_t IDR;
|
||||
volatile uint32_t ODR;
|
||||
volatile uint32_t BSRR;
|
||||
volatile uint32_t BRR;
|
||||
volatile uint32_t LCKR;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
|
||||
#define GPIOE ((struct GPIO *) GPIOE_BASE)
|
||||
#endif
|
||||
|
||||
static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
|
||||
#ifdef GPIO_USB_BASE
|
||||
static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
|
||||
#endif
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
|
||||
#endif
|
||||
|
||||
static void __attribute__((used))
|
||||
gpio_init (void)
|
||||
{
|
||||
/* Enable GPIO clock. */
|
||||
#if defined(MCU_STM32F0)
|
||||
RCC->AHBENR |= RCC_ENR_IOP_EN;
|
||||
RCC->AHBRSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->AHBRSTR = 0;
|
||||
#else
|
||||
RCC->APB2ENR |= RCC_ENR_IOP_EN;
|
||||
RCC->APB2RSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->APB2RSTR = 0;
|
||||
#endif
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
|
||||
GPIO_LED->OTYPER = VAL_GPIO_LED_OTYPER;
|
||||
GPIO_LED->MODER = VAL_GPIO_LED_MODER;
|
||||
GPIO_LED->PUPDR = VAL_GPIO_LED_PUPDR;
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
|
||||
GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
|
||||
GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
|
||||
GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
|
||||
#endif
|
||||
#else
|
||||
#ifdef AFIO_MAPR_SOMETHING
|
||||
AFIO->MAPR |= AFIO_MAPR_SOMETHING;
|
||||
#endif
|
||||
|
||||
/* LED is mandatory. If it's on an independent port, we configure it. */
|
||||
GPIO_LED->ODR = VAL_GPIO_LED_ODR;
|
||||
GPIO_LED->CRH = VAL_GPIO_LED_CRH;
|
||||
GPIO_LED->CRL = VAL_GPIO_LED_CRL;
|
||||
|
||||
/* If there is USB enabler pin and it's independent, we configure it. */
|
||||
#if defined(GPIO_USB_BASE) && GPIO_USB_BASE != GPIO_LED_BASE
|
||||
GPIO_USB->ODR = VAL_GPIO_USB_ODR;
|
||||
GPIO_USB->CRH = VAL_GPIO_USB_CRH;
|
||||
GPIO_USB->CRL = VAL_GPIO_USB_CRL;
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
|
||||
GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
|
||||
GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
@@ -7,6 +7,16 @@ When it detects a coding error, this function will be called to
|
||||
stop further execution of code. It never returns.
|
||||
@end deftypefun
|
||||
|
||||
@subheading chopstx_main_init
|
||||
@anchor{chopstx_main_init}
|
||||
@deftypefun {void} {chopstx_main_init} (chopstx_prio_t @var{prio})
|
||||
@var{prio}: priority
|
||||
|
||||
Initialize main thread with @var{prio}.
|
||||
The thread main is created with priority CHX_PRIO_MAIN_INIT,
|
||||
and it runs with that priority until this routine will is called.
|
||||
@end deftypefun
|
||||
|
||||
@subheading chopstx_create
|
||||
@anchor{chopstx_create}
|
||||
@deftypefun {chopstx_t} {chopstx_create} (uint32_t @var{flags_and_prio}, uint32_t @var{stack_addr}, size_t @var{stack_size}, voidfunc @var{thread_entry}, void * @var{arg})
|
||||
@@ -28,8 +38,8 @@ Create a thread.
|
||||
@deftypefun {void} {chopstx_usec_wait_var} (uint32_t * @var{var})
|
||||
@var{var}: Pointer to usec
|
||||
|
||||
Sleep for micro second specified by @var{var}.
|
||||
Another thread can clear @var{var} on condition (to avoid this thread going into sleep).
|
||||
Sleep for micro seconds, specified by @var{var}.
|
||||
Another thread can clear @var{var} to stop the caller going into sleep.
|
||||
@end deftypefun
|
||||
|
||||
@subheading chopstx_usec_wait
|
||||
@@ -95,7 +105,7 @@ Wake up a thread waiting on @var{cond}.
|
||||
@deftypefun {void} {chopstx_cond_broadcast} (chopstx_cond_t * @var{cond})
|
||||
@var{cond}: Condition Variable
|
||||
|
||||
Wake up all thread winting on @var{cond}.
|
||||
Wake up all threads waiting on @var{cond}.
|
||||
@end deftypefun
|
||||
|
||||
@subheading chopstx_claim_irq
|
||||
@@ -167,7 +177,7 @@ Waits for the thread of @var{thd} to terminate.
|
||||
@deftypefun {void} {chopstx_wakeup_usec_wait} (chopstx_t @var{thd})
|
||||
@var{thd}: Thread to be awakened
|
||||
|
||||
Canceling the timer, wakup the sleeping thread for it.
|
||||
Canceling the timer, wake up the sleeping thread.
|
||||
No return value.
|
||||
@end deftypefun
|
||||
|
||||
@@ -176,7 +186,7 @@ No return value.
|
||||
@deftypefun {void} {chopstx_cancel} (chopstx_t @var{thd})
|
||||
@var{thd}: Thread to be canceled
|
||||
|
||||
This function requests a cancellation th the thread @var{thd}.
|
||||
This function requests a cancellation of a thread @var{thd}.
|
||||
No return value.
|
||||
@end deftypefun
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
\input texinfo @c -*-texinfo-*-
|
||||
@c %**start of header
|
||||
@setfilename chopstx.info
|
||||
@set VERSION 0.04
|
||||
@set VERSION 0.08
|
||||
@settitle Chopstx Reference Manual
|
||||
@c Unify some of the indices.
|
||||
@syncodeindex tp fn
|
||||
|
||||
357
entry.c
357
entry.c
@@ -34,341 +34,19 @@
|
||||
#define INLINE __attribute__ ((used))
|
||||
#include "sys.h"
|
||||
#include "board.h"
|
||||
#undef STM32F10X_MD /* Prepare for high density device, too. */
|
||||
#else
|
||||
#include "board.h"
|
||||
#include "clk_gpio_init.c"
|
||||
#endif
|
||||
|
||||
#define STM32_SW_HSI (0 << 0)
|
||||
#define STM32_SW_PLL (2 << 0)
|
||||
#define STM32_PLLSRC_HSI (0 << 16)
|
||||
#define STM32_PLLSRC_HSE (1 << 16)
|
||||
|
||||
#define STM32_PLLXTPRE_DIV1 (0 << 17)
|
||||
#define STM32_PLLXTPRE_DIV2 (1 << 17)
|
||||
|
||||
#define STM32_HPRE_DIV1 (0 << 4)
|
||||
|
||||
#define STM32_PPRE1_DIV1 (0 << 8)
|
||||
#define STM32_PPRE1_DIV2 (4 << 8)
|
||||
|
||||
#define STM32_PPRE2_DIV1 (0 << 11)
|
||||
#define STM32_PPRE2_DIV2 (4 << 11)
|
||||
|
||||
#define STM32_ADCPRE_DIV4 (1 << 14)
|
||||
#define STM32_ADCPRE_DIV6 (2 << 14)
|
||||
|
||||
#define STM32_USBPRE_DIV1P5 (0 << 22)
|
||||
|
||||
#define STM32_MCO_NOCLOCK (0 << 24)
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSI
|
||||
#define STM32_FLASHBITS 0x00000011
|
||||
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
|
||||
#ifdef MAKE_ENTRY_PUBLIC
|
||||
#define STATIC_ENTRY
|
||||
#else
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_FLASHBITS 0x00000012
|
||||
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
|
||||
#define STATIC_ENTRY static
|
||||
#endif
|
||||
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV6
|
||||
#define STM32_MCOSEL STM32_MCO_NOCLOCK
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
|
||||
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
|
||||
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
||||
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||
|
||||
|
||||
#define PERIPH_BASE 0x40000000
|
||||
#define APBPERIPH_BASE PERIPH_BASE
|
||||
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
||||
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
|
||||
|
||||
struct RCC {
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t CFGR;
|
||||
volatile uint32_t CIR;
|
||||
volatile uint32_t APB2RSTR;
|
||||
volatile uint32_t APB1RSTR;
|
||||
volatile uint32_t AHBENR;
|
||||
volatile uint32_t APB2ENR;
|
||||
volatile uint32_t APB1ENR;
|
||||
volatile uint32_t BDCR;
|
||||
volatile uint32_t CSR;
|
||||
#if defined(MCU_STM32F0)
|
||||
volatile uint32_t AHBRSTR;
|
||||
volatile uint32_t CFGR2;
|
||||
volatile uint32_t CFGR3;
|
||||
volatile uint32_t CR2;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
|
||||
static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
|
||||
|
||||
#define RCC_APB1ENR_USBEN 0x00800000
|
||||
#define RCC_APB1RSTR_USBRST 0x00800000
|
||||
|
||||
#define RCC_CR_HSION 0x00000001
|
||||
#define RCC_CR_HSIRDY 0x00000002
|
||||
#define RCC_CR_HSITRIM 0x000000F8
|
||||
#define RCC_CR_HSEON 0x00010000
|
||||
#define RCC_CR_HSERDY 0x00020000
|
||||
#define RCC_CR_PLLON 0x01000000
|
||||
#define RCC_CR_PLLRDY 0x02000000
|
||||
|
||||
#define RCC_CFGR_SWS 0x0000000C
|
||||
#define RCC_CFGR_SWS_HSI 0x00000000
|
||||
|
||||
#define RCC_AHBENR_CRCEN 0x0040
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
#define RCC_AHBRSTR_IOPARST 0x00020000
|
||||
#define RCC_AHBRSTR_IOPBRST 0x00040000
|
||||
#define RCC_AHBRSTR_IOPCRST 0x00080000
|
||||
#define RCC_AHBRSTR_IOPDRST 0x00100000
|
||||
#define RCC_AHBRSTR_IOPFRST 0x00400000
|
||||
|
||||
#define RCC_AHBENR_IOPAEN 0x00020000
|
||||
#define RCC_AHBENR_IOPBEN 0x00040000
|
||||
#define RCC_AHBENR_IOPCEN 0x00080000
|
||||
#define RCC_AHBENR_IOPDEN 0x00100000
|
||||
#define RCC_AHBENR_IOPFEN 0x00400000
|
||||
|
||||
#define RCC_APB2RSTR_SYSCFGRST 0x00000001
|
||||
#define RCC_APB2ENR_SYSCFGEN 0x00000001
|
||||
#else
|
||||
#define RCC_APB2RSTR_AFIORST 0x00000001
|
||||
#define RCC_APB2RSTR_IOPARST 0x00000004
|
||||
#define RCC_APB2RSTR_IOPBRST 0x00000008
|
||||
#define RCC_APB2RSTR_IOPCRST 0x00000010
|
||||
#define RCC_APB2RSTR_IOPDRST 0x00000020
|
||||
|
||||
#define RCC_APB2ENR_AFIOEN 0x00000001
|
||||
#define RCC_APB2ENR_IOPAEN 0x00000004
|
||||
#define RCC_APB2ENR_IOPBEN 0x00000008
|
||||
#define RCC_APB2ENR_IOPCEN 0x00000010
|
||||
#define RCC_APB2ENR_IOPDEN 0x00000020
|
||||
#endif
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
struct SYSCFG {
|
||||
volatile uint32_t CFGR1;
|
||||
uint32_t dummy0;
|
||||
volatile uint32_t EXTICR[4];
|
||||
volatile uint32_t CFGR2;
|
||||
};
|
||||
#define SYSCFG_CFGR1_MEM_MODE 0x03
|
||||
|
||||
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
|
||||
static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
|
||||
#endif
|
||||
|
||||
struct FLASH {
|
||||
volatile uint32_t ACR;
|
||||
volatile uint32_t KEYR;
|
||||
volatile uint32_t OPTKEYR;
|
||||
volatile uint32_t SR;
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t AR;
|
||||
volatile uint32_t RESERVED;
|
||||
volatile uint32_t OBR;
|
||||
volatile uint32_t WRPR;
|
||||
};
|
||||
|
||||
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
|
||||
static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
|
||||
|
||||
static void __attribute__((used))
|
||||
clock_init (void)
|
||||
{
|
||||
/* HSI setup */
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY))
|
||||
;
|
||||
/* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
|
||||
RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
|
||||
RCC->CFGR = 0;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
|
||||
;
|
||||
|
||||
#if !defined(MCU_STM32F0)
|
||||
/* HSE setup */
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY))
|
||||
;
|
||||
#endif
|
||||
|
||||
/* PLL setup */
|
||||
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
;
|
||||
|
||||
/* Clock settings */
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
|
||||
| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
|
||||
/*
|
||||
* We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
|
||||
*/
|
||||
|
||||
/* Flash setup */
|
||||
FLASH->ACR = STM32_FLASHBITS;
|
||||
|
||||
/* CRC */
|
||||
RCC->AHBENR |= RCC_AHBENR_CRCEN;
|
||||
|
||||
/* Switching on the configured clock source. */
|
||||
RCC->CFGR |= STM32_SW;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
;
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
|
||||
RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
|
||||
RCC->APB2RSTR = 0;
|
||||
|
||||
/* Use vectors on RAM */
|
||||
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
struct GPIO {
|
||||
volatile uint32_t MODER;
|
||||
volatile uint16_t OTYPER;
|
||||
uint16_t dummy0;
|
||||
volatile uint32_t OSPEEDR;
|
||||
volatile uint32_t PUPDR;
|
||||
volatile uint16_t IDR;
|
||||
uint16_t dummy1;
|
||||
volatile uint16_t ODR;
|
||||
uint16_t dummy2;
|
||||
volatile uint16_t BSRR;
|
||||
uint16_t dummy3;
|
||||
volatile uint32_t LCKR;
|
||||
volatile uint32_t AFR[2];
|
||||
volatile uint16_t BRR;
|
||||
uint16_t dummy4;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOF ((struct GPIO *) GPIOF_BASE)
|
||||
#else
|
||||
struct AFIO
|
||||
{
|
||||
volatile uint32_t EVCR;
|
||||
volatile uint32_t MAPR;
|
||||
volatile uint32_t EXTICR[4];
|
||||
uint32_t RESERVED0;
|
||||
volatile uint32_t MAPR2;
|
||||
};
|
||||
|
||||
#define AFIO_BASE 0x40010000
|
||||
static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
|
||||
|
||||
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
|
||||
#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
|
||||
|
||||
|
||||
struct GPIO {
|
||||
volatile uint32_t CRL;
|
||||
volatile uint32_t CRH;
|
||||
volatile uint32_t IDR;
|
||||
volatile uint32_t ODR;
|
||||
volatile uint32_t BSRR;
|
||||
volatile uint32_t BRR;
|
||||
volatile uint32_t LCKR;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
|
||||
#define GPIOE ((struct GPIO *) GPIOE_BASE)
|
||||
#endif
|
||||
|
||||
static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
|
||||
#ifdef GPIO_USB_BASE
|
||||
static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
|
||||
#endif
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
|
||||
#endif
|
||||
|
||||
static void __attribute__((used))
|
||||
gpio_init (void)
|
||||
{
|
||||
/* Enable GPIO clock. */
|
||||
#if defined(MCU_STM32F0)
|
||||
RCC->AHBENR |= RCC_ENR_IOP_EN;
|
||||
RCC->AHBRSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->AHBRSTR = 0;
|
||||
#else
|
||||
RCC->APB2ENR |= RCC_ENR_IOP_EN;
|
||||
RCC->APB2RSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->APB2RSTR = 0;
|
||||
#endif
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
|
||||
GPIO_LED->OTYPER = VAL_GPIO_OTYPER;
|
||||
GPIO_LED->MODER = VAL_GPIO_MODER;
|
||||
GPIO_LED->PUPDR = VAL_GPIO_PUPDR;
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
|
||||
GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
|
||||
GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
|
||||
GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
|
||||
#endif
|
||||
#else
|
||||
#ifdef AFIO_MAPR_SOMETHING
|
||||
AFIO->MAPR |= AFIO_MAPR_SOMETHING;
|
||||
#endif
|
||||
|
||||
GPIO_USB->ODR = VAL_GPIO_ODR;
|
||||
GPIO_USB->CRH = VAL_GPIO_CRH;
|
||||
GPIO_USB->CRL = VAL_GPIO_CRL;
|
||||
|
||||
#if GPIO_USB_BASE != GPIO_LED_BASE
|
||||
GPIO_LED->ODR = VAL_GPIO_LED_ODR;
|
||||
GPIO_LED->CRH = VAL_GPIO_LED_CRH;
|
||||
GPIO_LED->CRL = VAL_GPIO_LED_CRL;
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
|
||||
GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
|
||||
GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
extern uint8_t __main_stack_end__;
|
||||
extern void svc (void);
|
||||
extern void preempt (void);
|
||||
@@ -426,7 +104,7 @@ uint32_t vectors_in_ram[48];
|
||||
/*
|
||||
* This routine only changes PSP and not MSP.
|
||||
*/
|
||||
static __attribute__ ((naked,section(".text.startup.0")))
|
||||
STATIC_ENTRY __attribute__ ((naked,section(".text.startup.0")))
|
||||
void entry (void)
|
||||
{
|
||||
asm volatile ("bl clock_init\n\t"
|
||||
@@ -521,12 +199,25 @@ handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
|
||||
chx_handle_intr /* DMA1 CH6 */, chx_handle_intr /* DMA1 CH7 */,
|
||||
chx_handle_intr /* ADC1_2 */, chx_handle_intr /* USB HP */,
|
||||
/* 0x90 */
|
||||
chx_handle_intr, /* USB LP */
|
||||
/* ... and more. CAN, EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
|
||||
chx_handle_intr /* USB LP */, chx_handle_intr /* CAN */,
|
||||
/* ... and more. EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
|
||||
chx_handle_intr, chx_handle_intr,
|
||||
/* 0xA0 */
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
/* 0xc0 */
|
||||
#if !defined(__ARM_ARCH_6M__)
|
||||
/* STM32F0 doesn't have more. */
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
#endif
|
||||
#if !defined(STM32F10X_MD)
|
||||
/* High-density chips have more; RTCAlarm, USBWakeup, ... , DMA2_Channel4_5 */
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
#endif
|
||||
};
|
||||
|
||||
1
example-cdc/board.h
Symbolic link
1
example-cdc/board.h
Symbolic link
@@ -0,0 +1 @@
|
||||
../board/board-fst-01.h
|
||||
@@ -14,9 +14,6 @@ MEMORY
|
||||
ram : org = 0x20000000, len = 20k
|
||||
}
|
||||
|
||||
__flash_start__ = 0x08001000;
|
||||
__flash_end__ = 0x08020000;
|
||||
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_size__ = 20k;
|
||||
__ram_end__ = __ram_start__ + __ram_size__;
|
||||
@@ -25,15 +22,17 @@ SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
|
||||
.sys : ALIGN(16) SUBALIGN(16)
|
||||
.sys : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
_sys = .;
|
||||
KEEP(*(.vectors))
|
||||
_sys = .;
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(16);
|
||||
*(.sys.version)
|
||||
KEEP(*(.sys.version))
|
||||
KEEP(*(.sys.board_id))
|
||||
KEEP(*(.sys.board_name))
|
||||
build/sys.o(.text)
|
||||
build/sys.o(.text.*)
|
||||
build/sys.o(.rodata)
|
||||
build/sys.o(.rodata)
|
||||
build/sys.o(.rodata.*)
|
||||
. = ALIGN(1024);
|
||||
*(.sys.0)
|
||||
@@ -59,6 +58,7 @@ SECTIONS
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
. = ALIGN(8);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* sys.c - system routines for the initial page for STM32F103.
|
||||
*
|
||||
* Copyright (C) 2013, 2014 Flying Stone Technology
|
||||
* Copyright (C) 2013, 2014, 2015 Flying Stone Technology
|
||||
* Author: NIIBE Yutaka <gniibe@fsij.org>
|
||||
*
|
||||
* Copying and distribution of this file, with or without modification,
|
||||
@@ -17,53 +17,13 @@
|
||||
#include <stdlib.h>
|
||||
#include "board.h"
|
||||
|
||||
#include "clk_gpio_init.c"
|
||||
|
||||
#define CORTEX_PRIORITY_BITS 4
|
||||
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
|
||||
#define USB_LP_CAN1_RX0_IRQn 20
|
||||
#define STM32_USB_IRQ_PRIORITY 11
|
||||
|
||||
|
||||
#define STM32_SW_HSI (0 << 0)
|
||||
#define STM32_SW_PLL (2 << 0)
|
||||
#define STM32_PLLSRC_HSI (0 << 16)
|
||||
#define STM32_PLLSRC_HSE (1 << 16)
|
||||
|
||||
#define STM32_PLLXTPRE_DIV1 (0 << 17)
|
||||
#define STM32_PLLXTPRE_DIV2 (1 << 17)
|
||||
|
||||
#define STM32_HPRE_DIV1 (0 << 4)
|
||||
|
||||
#define STM32_PPRE1_DIV1 (0 << 8)
|
||||
#define STM32_PPRE1_DIV2 (4 << 8)
|
||||
|
||||
#define STM32_PPRE2_DIV1 (0 << 11)
|
||||
#define STM32_PPRE2_DIV2 (4 << 11)
|
||||
|
||||
#define STM32_ADCPRE_DIV4 (1 << 14)
|
||||
#define STM32_ADCPRE_DIV6 (2 << 14)
|
||||
|
||||
#define STM32_USBPRE_DIV1P5 (0 << 22)
|
||||
|
||||
#define STM32_MCO_NOCLOCK (0 << 24)
|
||||
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_FLASHBITS 0x00000012
|
||||
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
|
||||
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV6
|
||||
#define STM32_MCOSEL STM32_MCO_NOCLOCK
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
|
||||
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
|
||||
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
||||
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||
|
||||
struct NVIC {
|
||||
uint32_t ISER[8];
|
||||
uint32_t unused1[24];
|
||||
@@ -93,191 +53,6 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
|
||||
NVIC_ISER (n) = 1 << (n & 0x1F);
|
||||
}
|
||||
|
||||
|
||||
#define PERIPH_BASE 0x40000000
|
||||
#define APBPERIPH_BASE PERIPH_BASE
|
||||
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
||||
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
|
||||
|
||||
struct RCC {
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t CFGR;
|
||||
volatile uint32_t CIR;
|
||||
volatile uint32_t APB2RSTR;
|
||||
volatile uint32_t APB1RSTR;
|
||||
volatile uint32_t AHBENR;
|
||||
volatile uint32_t APB2ENR;
|
||||
volatile uint32_t APB1ENR;
|
||||
volatile uint32_t BDCR;
|
||||
volatile uint32_t CSR;
|
||||
};
|
||||
|
||||
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
|
||||
static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
|
||||
|
||||
#define RCC_APB1ENR_USBEN 0x00800000
|
||||
#define RCC_APB1RSTR_USBRST 0x00800000
|
||||
|
||||
#define RCC_CR_HSION 0x00000001
|
||||
#define RCC_CR_HSIRDY 0x00000002
|
||||
#define RCC_CR_HSITRIM 0x000000F8
|
||||
#define RCC_CR_HSEON 0x00010000
|
||||
#define RCC_CR_HSERDY 0x00020000
|
||||
#define RCC_CR_PLLON 0x01000000
|
||||
#define RCC_CR_PLLRDY 0x02000000
|
||||
|
||||
#define RCC_CFGR_SWS 0x0000000C
|
||||
#define RCC_CFGR_SWS_HSI 0x00000000
|
||||
|
||||
#define RCC_AHBENR_CRCEN 0x0040
|
||||
|
||||
#define RCC_APB2RSTR_AFIORST 0x00000001
|
||||
#define RCC_APB2RSTR_IOPARST 0x00000004
|
||||
#define RCC_APB2RSTR_IOPBRST 0x00000008
|
||||
#define RCC_APB2RSTR_IOPCRST 0x00000010
|
||||
#define RCC_APB2RSTR_IOPDRST 0x00000020
|
||||
|
||||
#define RCC_APB2ENR_AFIOEN 0x00000001
|
||||
#define RCC_APB2ENR_IOPAEN 0x00000004
|
||||
#define RCC_APB2ENR_IOPBEN 0x00000008
|
||||
#define RCC_APB2ENR_IOPCEN 0x00000010
|
||||
#define RCC_APB2ENR_IOPDEN 0x00000020
|
||||
|
||||
struct FLASH {
|
||||
volatile uint32_t ACR;
|
||||
volatile uint32_t KEYR;
|
||||
volatile uint32_t OPTKEYR;
|
||||
volatile uint32_t SR;
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t AR;
|
||||
volatile uint32_t RESERVED;
|
||||
volatile uint32_t OBR;
|
||||
volatile uint32_t WRPR;
|
||||
};
|
||||
|
||||
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
|
||||
static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
|
||||
|
||||
static void
|
||||
clock_init (void)
|
||||
{
|
||||
/* HSI setup */
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY))
|
||||
;
|
||||
/* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
|
||||
RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
|
||||
RCC->CFGR = 0;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
|
||||
;
|
||||
|
||||
/* HSE setup */
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY))
|
||||
;
|
||||
|
||||
/* PLL setup */
|
||||
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
;
|
||||
|
||||
/* Clock settings */
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
|
||||
| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
|
||||
/*
|
||||
* We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
|
||||
*/
|
||||
|
||||
/* Flash setup */
|
||||
FLASH->ACR = STM32_FLASHBITS;
|
||||
|
||||
/* CRC */
|
||||
RCC->AHBENR |= RCC_AHBENR_CRCEN;
|
||||
|
||||
/* Switching on the configured clock source. */
|
||||
RCC->CFGR |= STM32_SW;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
struct AFIO
|
||||
{
|
||||
volatile uint32_t EVCR;
|
||||
volatile uint32_t MAPR;
|
||||
volatile uint32_t EXTICR[4];
|
||||
uint32_t RESERVED0;
|
||||
volatile uint32_t MAPR2;
|
||||
};
|
||||
|
||||
#define AFIO_BASE 0x40010000
|
||||
static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
|
||||
|
||||
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
|
||||
#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
|
||||
|
||||
|
||||
struct GPIO {
|
||||
volatile uint32_t CRL;
|
||||
volatile uint32_t CRH;
|
||||
volatile uint32_t IDR;
|
||||
volatile uint32_t ODR;
|
||||
volatile uint32_t BSRR;
|
||||
volatile uint32_t BRR;
|
||||
volatile uint32_t LCKR;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
|
||||
#define GPIOE ((struct GPIO *) GPIOE_BASE)
|
||||
|
||||
static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
|
||||
#ifdef GPIO_USB_BASE
|
||||
static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
|
||||
#endif
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
|
||||
#endif
|
||||
|
||||
static void
|
||||
gpio_init (void)
|
||||
{
|
||||
/* Enable GPIO clock. */
|
||||
RCC->APB2ENR |= RCC_ENR_IOP_EN;
|
||||
RCC->APB2RSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->APB2RSTR = 0;
|
||||
|
||||
#ifdef AFIO_MAPR_SOMETHING
|
||||
AFIO->MAPR |= AFIO_MAPR_SOMETHING;
|
||||
#endif
|
||||
|
||||
GPIO_USB->ODR = VAL_GPIO_ODR;
|
||||
GPIO_USB->CRH = VAL_GPIO_CRH;
|
||||
GPIO_USB->CRL = VAL_GPIO_CRL;
|
||||
|
||||
#if GPIO_USB_BASE != GPIO_LED_BASE
|
||||
GPIO_LED->ODR = VAL_GPIO_LED_ODR;
|
||||
GPIO_LED->CRH = VAL_GPIO_LED_CRH;
|
||||
GPIO_LED->CRL = VAL_GPIO_LED_CRL;
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
|
||||
GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
|
||||
GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
usb_cable_config (int enable)
|
||||
{
|
||||
@@ -468,16 +243,19 @@ flash_check_blank (const uint8_t *p_start, size_t size)
|
||||
return 1;
|
||||
}
|
||||
|
||||
extern uint8_t __flash_start__, __flash_end__;
|
||||
#define FLASH_START_ADDR 0x08000000 /* Fixed for all STM32F1. */
|
||||
#define FLASH_OFFSET 0x1000 /* First pages are not-writable. */
|
||||
#define FLASH_START (FLASH_START_ADDR+FLASH_OFFSET)
|
||||
#define CHIP_ID_REG ((uint32_t *)0xe0042000)
|
||||
#define FLASH_SIZE_REG ((uint16_t *)0x1ffff7e0)
|
||||
|
||||
static int
|
||||
flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
|
||||
{
|
||||
int status;
|
||||
uint32_t flash_start = (uint32_t)&__flash_start__;
|
||||
uint32_t flash_end = (uint32_t)&__flash_end__;
|
||||
uint32_t flash_end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
|
||||
|
||||
if (dst_addr < flash_start || dst_addr + len > flash_end)
|
||||
if (dst_addr < FLASH_START || dst_addr + len > flash_end)
|
||||
return 0;
|
||||
|
||||
while (len)
|
||||
@@ -530,17 +308,21 @@ flash_protect (void)
|
||||
static void __attribute__((naked))
|
||||
flash_erase_all_and_exec (void (*entry)(void))
|
||||
{
|
||||
uint32_t addr = (uint32_t)&__flash_start__;
|
||||
uint32_t end = (uint32_t)&__flash_end__;
|
||||
uint32_t addr = FLASH_START;
|
||||
uint32_t end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
|
||||
uint32_t page_size = 1024;
|
||||
int r;
|
||||
|
||||
if (((*CHIP_ID_REG) & 0xfff) == 0x0414)
|
||||
page_size = 2048;
|
||||
|
||||
while (addr < end)
|
||||
{
|
||||
r = flash_erase_page (addr);
|
||||
if (r != 0)
|
||||
break;
|
||||
|
||||
addr += FLASH_PAGE_SIZE;
|
||||
addr += page_size;
|
||||
}
|
||||
|
||||
if (addr >= end)
|
||||
@@ -640,7 +422,13 @@ handler vector[] __attribute__ ((section(".vectors"))) = {
|
||||
|
||||
const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
|
||||
3*2+2, /* bLength */
|
||||
0x03, /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
|
||||
/* sys version: "2.0" */
|
||||
'2', 0, '.', 0, '0', 0,
|
||||
0x03, /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
|
||||
/* sys version: "2.1" */
|
||||
'2', 0, '.', 0, '1', 0,
|
||||
};
|
||||
|
||||
const uint32_t __attribute__((section(".sys.board_id")))
|
||||
sys_board_id = BOARD_ID;
|
||||
|
||||
const uint8_t __attribute__((section(".sys.board_name")))
|
||||
sys_board_name[] = BOARD_NAME;
|
||||
|
||||
@@ -1,4 +1,18 @@
|
||||
#define BOARD_ID_CQ_STARM 0xc5480875
|
||||
#define BOARD_ID_FST_01_00 0x613870a9
|
||||
#define BOARD_ID_FST_01 0x696886af
|
||||
#define BOARD_ID_MAPLE_MINI 0x7a445272
|
||||
#define BOARD_ID_OLIMEX_STM32_H103 0xf92bb594
|
||||
#define BOARD_ID_STBEE_MINI 0x1f341961
|
||||
#define BOARD_ID_STBEE 0x945c37e8
|
||||
#define BOARD_ID_STM32_PRIMER2 0x21e5798d
|
||||
#define BOARD_ID_STM8S_DISCOVERY 0x2f0976bb
|
||||
#define BOARD_ID_ST_DONGLE 0x2cd4e471
|
||||
#define BOARD_ID_ST_NUCLEO_F103 0x9b87c16d
|
||||
|
||||
extern const uint8_t sys_version[8];
|
||||
extern const uint32_t sys_board_id;
|
||||
extern const uint8_t sys_board_name[];
|
||||
|
||||
typedef void (*handler)(void);
|
||||
extern handler vector[16];
|
||||
|
||||
@@ -36,7 +36,7 @@ static const uint8_t vcom_device_desc[18] = {
|
||||
};
|
||||
|
||||
/* Configuration Descriptor tree for a CDC.*/
|
||||
static const uint8_t vcom_configuration_desc[67] = {
|
||||
static const uint8_t vcom_config_desc[67] = {
|
||||
9,
|
||||
USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
|
||||
/* Configuration Descriptor.*/
|
||||
@@ -167,7 +167,7 @@ usb_cb_device_reset (void)
|
||||
usb_lld_set_configuration (0);
|
||||
|
||||
/* Current Feature initialization */
|
||||
usb_lld_set_feature (vcom_configuration_desc[7]);
|
||||
usb_lld_set_feature (vcom_config_desc[7]);
|
||||
|
||||
usb_lld_reset ();
|
||||
|
||||
@@ -177,14 +177,12 @@ usb_cb_device_reset (void)
|
||||
|
||||
|
||||
void
|
||||
usb_cb_ctrl_write_finish (uint8_t req, uint8_t req_no, uint16_t value,
|
||||
uint16_t index, uint16_t len)
|
||||
usb_cb_ctrl_write_finish (uint8_t req, uint8_t req_no, uint16_t value)
|
||||
{
|
||||
uint8_t type_rcp = req & (REQUEST_TYPE|RECIPIENT);
|
||||
|
||||
if (type_rcp == (CLASS_REQUEST | INTERFACE_RECIPIENT)
|
||||
&& index == 0 && USB_SETUP_SET (req) && len == 0
|
||||
&& req_no == USB_CDC_REQ_SET_CONTROL_LINE_STATE)
|
||||
&& USB_SETUP_SET (req) && req_no == USB_CDC_REQ_SET_CONTROL_LINE_STATE)
|
||||
{
|
||||
/* Open/close the connection. */
|
||||
chopstx_mutex_lock (&usb_mtx);
|
||||
@@ -211,22 +209,17 @@ static struct line_coding line_coding = {
|
||||
|
||||
|
||||
static int
|
||||
vcom_port_data_setup (uint8_t req, uint8_t req_no, uint16_t value, uint16_t len)
|
||||
vcom_port_data_setup (uint8_t req, uint8_t req_no, struct control_info *detail)
|
||||
{
|
||||
(void)value;
|
||||
if (USB_SETUP_GET (req))
|
||||
{
|
||||
if (req_no == USB_CDC_REQ_GET_LINE_CODING
|
||||
&& len == sizeof (line_coding))
|
||||
{
|
||||
usb_lld_set_data_to_send (&line_coding, sizeof (line_coding));
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
if (req_no == USB_CDC_REQ_GET_LINE_CODING)
|
||||
return usb_lld_reply_request (&line_coding, sizeof(line_coding), detail);
|
||||
}
|
||||
else /* USB_SETUP_SET (req) */
|
||||
{
|
||||
if (req_no == USB_CDC_REQ_SET_LINE_CODING
|
||||
&& len == sizeof (line_coding))
|
||||
&& detail->len == sizeof (line_coding))
|
||||
{
|
||||
usb_lld_set_data_to_recv (&line_coding, sizeof (line_coding));
|
||||
return USB_SUCCESS;
|
||||
@@ -239,38 +232,29 @@ vcom_port_data_setup (uint8_t req, uint8_t req_no, uint16_t value, uint16_t len)
|
||||
}
|
||||
|
||||
int
|
||||
usb_cb_setup (uint8_t req, uint8_t req_no,
|
||||
uint16_t value, uint16_t index, uint16_t len)
|
||||
usb_cb_setup (uint8_t req, uint8_t req_no, struct control_info *detail)
|
||||
{
|
||||
uint8_t type_rcp = req & (REQUEST_TYPE|RECIPIENT);
|
||||
|
||||
(void)len;
|
||||
if (type_rcp == (CLASS_REQUEST | INTERFACE_RECIPIENT))
|
||||
if (index == 0)
|
||||
return vcom_port_data_setup (req, req_no, value, len);
|
||||
if (type_rcp == (CLASS_REQUEST | INTERFACE_RECIPIENT) && detail->index == 0)
|
||||
return vcom_port_data_setup (req, req_no, detail);
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
int
|
||||
usb_cb_get_descriptor (uint8_t rcp, uint8_t desc_type, uint8_t desc_index,
|
||||
uint16_t index)
|
||||
struct control_info *detail)
|
||||
{
|
||||
(void)index;
|
||||
if (rcp != DEVICE_RECIPIENT)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (desc_type == DEVICE_DESCRIPTOR)
|
||||
{
|
||||
usb_lld_set_data_to_send (vcom_device_desc, sizeof (vcom_device_desc));
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
return usb_lld_reply_request (vcom_device_desc, sizeof (vcom_device_desc),
|
||||
detail);
|
||||
else if (desc_type == CONFIG_DESCRIPTOR)
|
||||
{
|
||||
usb_lld_set_data_to_send (vcom_configuration_desc,
|
||||
sizeof (vcom_configuration_desc));
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
return usb_lld_reply_request (vcom_config_desc, sizeof (vcom_config_desc),
|
||||
detail);
|
||||
else if (desc_type == STRING_DESCRIPTOR)
|
||||
{
|
||||
const uint8_t *str;
|
||||
@@ -298,8 +282,7 @@ usb_cb_get_descriptor (uint8_t rcp, uint8_t desc_type, uint8_t desc_index,
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
usb_lld_set_data_to_send (str, size);
|
||||
return USB_SUCCESS;
|
||||
return usb_lld_reply_request (str, size, detail);
|
||||
}
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
@@ -374,9 +357,11 @@ int usb_cb_handle_event (uint8_t event_type, uint16_t value)
|
||||
}
|
||||
|
||||
|
||||
int usb_cb_interface (uint8_t cmd, uint16_t interface, uint16_t alt)
|
||||
int usb_cb_interface (uint8_t cmd, struct control_info *detail)
|
||||
{
|
||||
static uint8_t zero = 0;
|
||||
const uint8_t zero = 0;
|
||||
uint16_t interface = detail->index;
|
||||
uint16_t alt = detail->value;
|
||||
|
||||
if (interface >= NUM_INTERFACES)
|
||||
return USB_UNSUPPORT;
|
||||
@@ -393,8 +378,7 @@ int usb_cb_interface (uint8_t cmd, uint16_t interface, uint16_t alt)
|
||||
}
|
||||
|
||||
case USB_GET_INTERFACE:
|
||||
usb_lld_set_data_to_send (&zero, 1);
|
||||
return USB_SUCCESS;
|
||||
return usb_lld_reply_request (&zero, 1, detail);
|
||||
|
||||
default:
|
||||
case USB_QUERY_INTERFACE:
|
||||
|
||||
@@ -55,15 +55,19 @@ enum
|
||||
USB_SUCCESS = 1,
|
||||
};
|
||||
|
||||
struct control_info {
|
||||
uint16_t value;
|
||||
uint16_t index;
|
||||
uint16_t len;
|
||||
};
|
||||
|
||||
void usb_cb_device_reset (void);
|
||||
void usb_cb_ctrl_write_finish (uint8_t req, uint8_t req_no,
|
||||
uint16_t value, uint16_t index, uint16_t len);
|
||||
int usb_cb_setup (uint8_t req, uint8_t req_no, uint16_t value,
|
||||
uint16_t index, uint16_t len);
|
||||
int usb_cb_setup (uint8_t req, uint8_t req_no, struct control_info *detail);
|
||||
int usb_cb_interface (uint8_t cmd, struct control_info *detail);
|
||||
int usb_cb_get_descriptor (uint8_t rcp, uint8_t desc_type, uint8_t desc_index,
|
||||
uint16_t index);
|
||||
struct control_info *detail);
|
||||
int usb_cb_handle_event (uint8_t event_type, uint16_t value);
|
||||
int usb_cb_interface (uint8_t cmd, uint16_t interface, uint16_t value);
|
||||
void usb_cb_ctrl_write_finish (uint8_t req, uint8_t req_no, uint16_t value);
|
||||
|
||||
enum {
|
||||
USB_EVENT_ADDRESS,
|
||||
@@ -89,51 +93,30 @@ enum DEVICE_STATE
|
||||
CONFIGURED
|
||||
};
|
||||
|
||||
void usb_lld_init (uint8_t feature);
|
||||
void usb_lld_to_pmabuf (const void *src, uint16_t addr, size_t n);
|
||||
void usb_lld_from_pmabuf (void *dst, uint16_t addr, size_t n);
|
||||
void usb_lld_stall_tx (int ep_num);
|
||||
void usb_lld_stall_rx (int ep_num);
|
||||
int usb_lld_tx_data_len (int ep_num);
|
||||
void usb_lld_txcpy (const void *src, int ep_num, int offset, size_t len);
|
||||
void usb_lld_tx_enable (int ep_num, size_t len);
|
||||
void usb_lld_write (uint8_t ep_num, const void *buf, size_t len);
|
||||
int usb_lld_reply_request (const void *buf, size_t buflen,
|
||||
struct control_info *ctrl);
|
||||
void usb_lld_rx_enable (int ep_num);
|
||||
int usb_lld_rx_data_len (int ep_num);
|
||||
void usb_lld_rxcpy (uint8_t *dst, int ep_num, int offset, size_t len);
|
||||
void usb_lld_reset (void);
|
||||
void usb_lld_setup_endpoint (int ep_num, int ep_type, int ep_kind,
|
||||
int ep_rx_addr, int ep_tx_addr,
|
||||
int ep_rx_memory_size);
|
||||
void usb_lld_set_configuration (uint8_t config);
|
||||
uint8_t usb_lld_current_configuration (void);
|
||||
void usb_lld_set_feature (uint8_t feature);
|
||||
void usb_lld_set_data_to_recv (const void *p, size_t len);
|
||||
|
||||
extern void usb_lld_init (uint8_t feature);
|
||||
void usb_lld_prepare_shutdown (void);
|
||||
void usb_lld_shutdown (void);
|
||||
|
||||
extern void usb_lld_to_pmabuf (const void *src, uint16_t addr, size_t n);
|
||||
|
||||
extern void usb_lld_from_pmabuf (void *dst, uint16_t addr, size_t n);
|
||||
|
||||
extern void usb_lld_stall_tx (int ep_num);
|
||||
|
||||
extern void usb_lld_stall_rx (int ep_num);
|
||||
|
||||
extern int usb_lld_tx_data_len (int ep_num);
|
||||
|
||||
extern void usb_lld_txcpy (const void *src, int ep_num, int offset, size_t len);
|
||||
|
||||
extern void usb_lld_tx_enable (int ep_num, size_t len);
|
||||
|
||||
extern void usb_lld_write (uint8_t ep_num, const void *buf, size_t len);
|
||||
|
||||
extern void usb_lld_rx_enable (int ep_num);
|
||||
|
||||
extern int usb_lld_rx_data_len (int ep_num);
|
||||
|
||||
extern void usb_lld_rxcpy (uint8_t *dst, int ep_num, int offset, size_t len);
|
||||
|
||||
extern void usb_lld_reset (void);
|
||||
|
||||
extern void usb_lld_setup_endpoint (int ep_num, int ep_type, int ep_kind,
|
||||
int ep_rx_addr, int ep_tx_addr,
|
||||
int ep_rx_memory_size);
|
||||
|
||||
extern void usb_lld_set_configuration (uint8_t config);
|
||||
|
||||
extern uint8_t usb_lld_current_configuration (void);
|
||||
|
||||
extern void usb_lld_set_feature (uint8_t feature);
|
||||
|
||||
extern void usb_lld_set_data_to_send (const void *p, size_t len);
|
||||
|
||||
extern inline void usb_lld_set_data_to_recv (void *p, size_t len)
|
||||
{
|
||||
usb_lld_set_data_to_send ((const void *)p, len);
|
||||
}
|
||||
|
||||
extern void usb_lld_prepare_shutdown (void);
|
||||
extern void usb_lld_shutdown (void);
|
||||
|
||||
extern void usb_interrupt_handler (void);
|
||||
void usb_interrupt_handler (void);
|
||||
|
||||
@@ -1,9 +1,6 @@
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
#include "sys.h"
|
||||
#include "usb_lld.h"
|
||||
|
||||
@@ -49,33 +46,27 @@ enum FEATURE_SELECTOR
|
||||
|
||||
struct DATA_INFO
|
||||
{
|
||||
uint16_t len;
|
||||
uint16_t offset;
|
||||
uint8_t *addr;
|
||||
uint16_t len;
|
||||
uint8_t require_zlp;
|
||||
};
|
||||
|
||||
struct CONTROL_INFO
|
||||
{
|
||||
uint8_t bmRequestType;
|
||||
uint8_t bRequest;
|
||||
uint16_t wValue;
|
||||
uint16_t wIndex;
|
||||
uint16_t wLength;
|
||||
};
|
||||
|
||||
struct DEVICE_INFO
|
||||
{
|
||||
uint8_t current_configuration;
|
||||
uint8_t current_feature;
|
||||
uint8_t state;
|
||||
/**/
|
||||
uint8_t bmRequestType;
|
||||
uint8_t bRequest;
|
||||
/**/
|
||||
uint16_t value;
|
||||
};
|
||||
|
||||
static struct CONTROL_INFO control_info;
|
||||
static struct DEVICE_INFO device_info;
|
||||
static struct DATA_INFO data_info;
|
||||
|
||||
static struct CONTROL_INFO *const ctrl_p = &control_info;
|
||||
static struct DEVICE_INFO *const dev_p = &device_info;
|
||||
static struct DATA_INFO *const data_p = &data_info;
|
||||
|
||||
@@ -412,16 +403,14 @@ static void handle_datastage_out (void)
|
||||
{
|
||||
if (data_p->addr && data_p->len)
|
||||
{
|
||||
uint8_t *buf;
|
||||
uint32_t len = st103_get_rx_count (ENDP0);
|
||||
|
||||
if (len > data_p->len)
|
||||
len = data_p->len;
|
||||
|
||||
buf = data_p->addr + data_p->offset;
|
||||
usb_lld_from_pmabuf (buf, st103_get_rx_addr (ENDP0), len);
|
||||
usb_lld_from_pmabuf (data_p->addr, st103_get_rx_addr (ENDP0), len);
|
||||
data_p->len -= len;
|
||||
data_p->offset += len;
|
||||
data_p->addr += len;
|
||||
}
|
||||
|
||||
if (data_p->len == 0)
|
||||
@@ -440,13 +429,12 @@ static void handle_datastage_out (void)
|
||||
static void handle_datastage_in (void)
|
||||
{
|
||||
uint32_t len = USB_MAX_PACKET_SIZE;;
|
||||
const uint8_t *buf;
|
||||
|
||||
if ((data_p->len == 0) && (dev_p->state == LAST_IN_DATA))
|
||||
{
|
||||
if (data_p->require_zlp == TRUE)
|
||||
if (data_p->require_zlp)
|
||||
{
|
||||
data_p->require_zlp = FALSE;
|
||||
data_p->require_zlp = 0;
|
||||
|
||||
/* No more data to send. Send empty packet */
|
||||
st103_set_tx_count (ENDP0, 0);
|
||||
@@ -467,40 +455,33 @@ static void handle_datastage_in (void)
|
||||
if (len > data_p->len)
|
||||
len = data_p->len;
|
||||
|
||||
buf = (const uint8_t *)data_p->addr + data_p->offset;
|
||||
usb_lld_to_pmabuf (buf, st103_get_tx_addr (ENDP0), len);
|
||||
usb_lld_to_pmabuf (data_p->addr, st103_get_tx_addr (ENDP0), len);
|
||||
data_p->len -= len;
|
||||
data_p->offset += len;
|
||||
data_p->addr += len;
|
||||
st103_set_tx_count (ENDP0, len);
|
||||
st103_ep_set_tx_status (ENDP0, EP_TX_VALID);
|
||||
}
|
||||
|
||||
typedef int (*HANDLER) (uint8_t req,
|
||||
uint16_t value, uint16_t index, uint16_t length);
|
||||
typedef int (*HANDLER) (uint8_t req, struct control_info *detail);
|
||||
|
||||
static int std_none (uint8_t req,
|
||||
uint16_t value, uint16_t index, uint16_t length)
|
||||
static int std_none (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
(void)req; (void)value; (void)index; (void)length;
|
||||
(void)req; (void)detail;
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
static int std_get_status (uint8_t req,
|
||||
uint16_t value, uint16_t index, uint16_t length)
|
||||
static int std_get_status (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
static uint16_t status_info;
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
uint16_t status_info = 0;
|
||||
|
||||
status_info = 0; /* Reset Status Information */
|
||||
data_p->addr = (uint8_t *)&status_info;
|
||||
|
||||
if (value != 0 || length != 2 || (index >> 8) != 0
|
||||
if (detail->value != 0 || detail->len != 2 || (detail->index >> 8) != 0
|
||||
|| (req & REQUEST_DIR) == 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (rcp == DEVICE_RECIPIENT)
|
||||
{
|
||||
if (index == 0)
|
||||
if (detail->index == 0)
|
||||
{
|
||||
/* Get Device Status */
|
||||
uint8_t feature = dev_p->current_feature;
|
||||
@@ -517,8 +498,7 @@ static int std_get_status (uint8_t req,
|
||||
else /* Self-powered */
|
||||
status_info &= ~1;
|
||||
|
||||
data_p->len = 2;
|
||||
return USB_SUCCESS;
|
||||
return usb_lld_reply_request (&status_info, 2, detail);
|
||||
}
|
||||
}
|
||||
else if (rcp == INTERFACE_RECIPIENT)
|
||||
@@ -528,22 +508,21 @@ static int std_get_status (uint8_t req,
|
||||
if (dev_p->current_configuration == 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
r = usb_cb_interface (USB_QUERY_INTERFACE, index, 0);
|
||||
r = usb_cb_interface (USB_QUERY_INTERFACE, detail);
|
||||
if (r != USB_SUCCESS)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
data_p->len = 2;
|
||||
return USB_SUCCESS;
|
||||
return usb_lld_reply_request (&status_info, 2, detail);
|
||||
}
|
||||
else if (rcp == ENDPOINT_RECIPIENT)
|
||||
{
|
||||
uint8_t endpoint = (index & 0x0f);
|
||||
uint8_t endpoint = (detail->index & 0x0f);
|
||||
uint16_t status;
|
||||
|
||||
if ((index & 0x70) || endpoint == ENDP0)
|
||||
if ((detail->index & 0x70) || endpoint == ENDP0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if ((index & 0x80))
|
||||
if ((detail->index & 0x80))
|
||||
{
|
||||
status = st103_ep_get_tx_status (endpoint);
|
||||
if (status == 0) /* Disabled */
|
||||
@@ -560,15 +539,13 @@ static int std_get_status (uint8_t req,
|
||||
status_info |= 1; /* OUT Endpoint stalled */
|
||||
}
|
||||
|
||||
data_p->len = 2;
|
||||
return USB_SUCCESS;
|
||||
return usb_lld_reply_request (&status_info, 2, detail);
|
||||
}
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
static int std_clear_feature (uint8_t req, uint16_t value,
|
||||
uint16_t index, uint16_t length)
|
||||
static int std_clear_feature (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
|
||||
@@ -577,10 +554,10 @@ static int std_clear_feature (uint8_t req, uint16_t value,
|
||||
|
||||
if (rcp == DEVICE_RECIPIENT)
|
||||
{
|
||||
if (length != 0 || index != 0)
|
||||
if (detail->len != 0 || detail->index != 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (value == DEVICE_REMOTE_WAKEUP)
|
||||
if (detail->value == DEVICE_REMOTE_WAKEUP)
|
||||
{
|
||||
dev_p->current_feature &= ~(1 << 5);
|
||||
return USB_SUCCESS;
|
||||
@@ -588,17 +565,17 @@ static int std_clear_feature (uint8_t req, uint16_t value,
|
||||
}
|
||||
else if (rcp == ENDPOINT_RECIPIENT)
|
||||
{
|
||||
uint8_t endpoint = (index & 0x0f);
|
||||
uint8_t endpoint = (detail->index & 0x0f);
|
||||
uint16_t status;
|
||||
|
||||
if (dev_p->current_configuration == 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (length != 0 || (index >> 8) != 0 || value != ENDPOINT_STALL
|
||||
|| endpoint == ENDP0)
|
||||
if (detail->len != 0 || (detail->index >> 8) != 0
|
||||
|| detail->value != ENDPOINT_STALL || endpoint == ENDP0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if ((index & 0x80))
|
||||
if ((detail->index & 0x80))
|
||||
status = st103_ep_get_tx_status (endpoint);
|
||||
else
|
||||
status = st103_ep_get_rx_status (endpoint);
|
||||
@@ -606,7 +583,7 @@ static int std_clear_feature (uint8_t req, uint16_t value,
|
||||
if (status == 0) /* Disabled */
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (index & 0x80) /* IN endpoint */
|
||||
if (detail->index & 0x80) /* IN endpoint */
|
||||
st103_ep_clear_dtog_tx (endpoint);
|
||||
else /* OUT endpoint */
|
||||
st103_ep_clear_dtog_rx (endpoint);
|
||||
@@ -618,8 +595,7 @@ static int std_clear_feature (uint8_t req, uint16_t value,
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
static int std_set_feature (uint8_t req, uint16_t value,
|
||||
uint16_t index, uint16_t length)
|
||||
static int std_set_feature (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
|
||||
@@ -628,10 +604,10 @@ static int std_set_feature (uint8_t req, uint16_t value,
|
||||
|
||||
if (rcp == DEVICE_RECIPIENT)
|
||||
{
|
||||
if (length != 0 || index != 0)
|
||||
if (detail->len != 0 || detail->index != 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (value == DEVICE_REMOTE_WAKEUP)
|
||||
if (detail->value == DEVICE_REMOTE_WAKEUP)
|
||||
{
|
||||
dev_p->current_feature |= 1 << 5;
|
||||
// event??
|
||||
@@ -640,16 +616,17 @@ static int std_set_feature (uint8_t req, uint16_t value,
|
||||
}
|
||||
else if (rcp == ENDPOINT_RECIPIENT)
|
||||
{
|
||||
uint8_t endpoint = (index & 0x0f);
|
||||
uint8_t endpoint = (detail->index & 0x0f);
|
||||
uint32_t status;
|
||||
|
||||
if (dev_p->current_configuration == 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (length != 0 || (index >> 8) != 0 || value != 0 || endpoint == ENDP0)
|
||||
if (detail->len != 0 || (detail->index >> 8) != 0
|
||||
|| detail->value != 0 || endpoint == ENDP0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if ((index & 0x80))
|
||||
if ((detail->index & 0x80))
|
||||
status = st103_ep_get_tx_status (endpoint);
|
||||
else
|
||||
status = st103_ep_get_rx_status (endpoint);
|
||||
@@ -657,7 +634,7 @@ static int std_set_feature (uint8_t req, uint16_t value,
|
||||
if (status == 0) /* Disabled */
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (index & 0x80)
|
||||
if (detail->index & 0x80)
|
||||
/* IN endpoint */
|
||||
st103_ep_set_tx_status (endpoint, EP_TX_STALL);
|
||||
else
|
||||
@@ -671,77 +648,59 @@ static int std_set_feature (uint8_t req, uint16_t value,
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
static int std_set_address (uint8_t req, uint16_t value,
|
||||
uint16_t index, uint16_t length)
|
||||
static int std_set_address (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
|
||||
if ((req & REQUEST_DIR) == 1)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (rcp == DEVICE_RECIPIENT)
|
||||
{
|
||||
if (length == 0 && value <= 127 && index == 0
|
||||
&& dev_p->current_configuration == 0)
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
if (rcp == DEVICE_RECIPIENT && detail->len == 0 && detail->value <= 127
|
||||
&& detail->index == 0 && dev_p->current_configuration == 0)
|
||||
return USB_SUCCESS;
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
static int std_get_descriptor (uint8_t req, uint16_t value,
|
||||
uint16_t index, uint16_t length)
|
||||
static int std_get_descriptor (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
|
||||
if ((req & REQUEST_DIR) == 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
(void)length;
|
||||
return usb_cb_get_descriptor (rcp, (value >> 8), (value & 0xff), index);
|
||||
return usb_cb_get_descriptor (rcp, (detail->value >> 8),
|
||||
(detail->value & 0xff), detail);
|
||||
}
|
||||
|
||||
static int std_get_configuration (uint8_t req, uint16_t value,
|
||||
uint16_t index, uint16_t length)
|
||||
static int std_get_configuration (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
|
||||
(void)detail;
|
||||
if ((req & REQUEST_DIR) == 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
(void)value; (void)index; (void)length;
|
||||
if (rcp == DEVICE_RECIPIENT)
|
||||
{
|
||||
data_p->addr = &dev_p->current_configuration;
|
||||
data_p->len = 1;
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
return usb_lld_reply_request (&dev_p->current_configuration, 1, detail);
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
static int std_set_configuration (uint8_t req, uint16_t value,
|
||||
uint16_t index, uint16_t length)
|
||||
static int std_set_configuration (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
|
||||
if ((req & REQUEST_DIR) == 1)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (rcp == DEVICE_RECIPIENT && index == 0 && length == 0)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = usb_cb_handle_event (USB_EVENT_CONFIG, value);
|
||||
if (r == USB_SUCCESS)
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
if (rcp == DEVICE_RECIPIENT && detail->index == 0 && detail->len == 0)
|
||||
return usb_cb_handle_event (USB_EVENT_CONFIG, detail->value);
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
static int std_get_interface (uint8_t req, uint16_t value,
|
||||
uint16_t index, uint16_t length)
|
||||
static int std_get_interface (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
|
||||
@@ -750,74 +709,61 @@ static int std_get_interface (uint8_t req, uint16_t value,
|
||||
|
||||
if (rcp == INTERFACE_RECIPIENT)
|
||||
{
|
||||
if (value != 0 || (index >> 8) != 0 || length != 1)
|
||||
if (detail->value != 0 || (detail->index >> 8) != 0 || detail->len != 1)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (dev_p->current_configuration == 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
return usb_cb_interface (USB_GET_INTERFACE, index, 0);
|
||||
return usb_cb_interface (USB_GET_INTERFACE, detail);
|
||||
}
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
static int std_set_interface (uint8_t req, uint16_t value,
|
||||
uint16_t index, uint16_t length)
|
||||
static int std_set_interface (uint8_t req, struct control_info *detail)
|
||||
{
|
||||
uint8_t rcp = req & RECIPIENT;
|
||||
|
||||
if ((req & REQUEST_DIR) == 1)
|
||||
if ((req & REQUEST_DIR) == 1 || rcp != INTERFACE_RECIPIENT
|
||||
|| detail->len != 0 || (detail->index >> 8) != 0
|
||||
|| (detail->value >> 8) != 0 || dev_p->current_configuration != 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (rcp == INTERFACE_RECIPIENT)
|
||||
{
|
||||
int r;
|
||||
|
||||
if (length != 0 || (index >> 8) != 0 || (value >> 8) != 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
if (dev_p->current_configuration != 0)
|
||||
return USB_UNSUPPORT;
|
||||
|
||||
r = usb_cb_interface (USB_SET_INTERFACE, index, value);
|
||||
if (r == USB_SUCCESS)
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
return usb_cb_interface (USB_SET_INTERFACE, detail);
|
||||
}
|
||||
|
||||
|
||||
static void handle_setup0 (void)
|
||||
{
|
||||
const uint16_t *pw;
|
||||
struct control_info ctrl;
|
||||
uint16_t w;
|
||||
uint8_t req;
|
||||
uint8_t req_no;
|
||||
int r = USB_UNSUPPORT;
|
||||
HANDLER handler;
|
||||
|
||||
pw = (uint16_t *)(PMA_ADDR + (uint8_t *)(st103_get_rx_addr (ENDP0) * 2));
|
||||
w = *pw++;
|
||||
|
||||
ctrl_p->bmRequestType = w & 0xff;
|
||||
ctrl_p->bRequest = req = w >> 8;
|
||||
dev_p->bmRequestType = w & 0xff;
|
||||
dev_p->bRequest = req_no = w >> 8;
|
||||
pw++;
|
||||
ctrl_p->wValue = *pw++;
|
||||
ctrl.value = *pw++;
|
||||
pw++;
|
||||
ctrl_p->wIndex = *pw++;
|
||||
ctrl.index = *pw++;
|
||||
pw++;
|
||||
ctrl_p->wLength = *pw;
|
||||
ctrl.len = *pw;
|
||||
|
||||
data_p->addr = NULL;
|
||||
data_p->len = 0;
|
||||
data_p->offset = 0;
|
||||
data_p->require_zlp = 0;
|
||||
|
||||
if ((ctrl_p->bmRequestType & REQUEST_TYPE) == STANDARD_REQUEST)
|
||||
if ((dev_p->bmRequestType & REQUEST_TYPE) == STANDARD_REQUEST)
|
||||
{
|
||||
if (req < TOTAL_REQUEST)
|
||||
if (req_no < TOTAL_REQUEST)
|
||||
{
|
||||
switch (req)
|
||||
switch (req_no)
|
||||
{
|
||||
case 0: handler = std_get_status; break;
|
||||
case 1: handler = std_clear_feature; break;
|
||||
@@ -831,44 +777,30 @@ static void handle_setup0 (void)
|
||||
default: handler = std_none; break;
|
||||
}
|
||||
|
||||
r = (*handler) (ctrl_p->bmRequestType,
|
||||
ctrl_p->wValue, ctrl_p->wIndex, ctrl_p->wLength);
|
||||
r = (*handler) (dev_p->bmRequestType, &ctrl);
|
||||
}
|
||||
}
|
||||
else
|
||||
r = usb_cb_setup (ctrl_p->bmRequestType, req,
|
||||
ctrl_p->wValue, ctrl_p->wIndex, ctrl_p->wLength);
|
||||
r = usb_cb_setup (dev_p->bmRequestType, req_no, &ctrl);
|
||||
|
||||
if (r != USB_SUCCESS)
|
||||
dev_p->state = STALLED;
|
||||
else
|
||||
{
|
||||
if (USB_SETUP_GET (ctrl_p->bmRequestType))
|
||||
if (USB_SETUP_SET (dev_p->bmRequestType))
|
||||
{
|
||||
uint32_t len = ctrl_p->wLength;
|
||||
|
||||
/* Restrict the data length to be the one host asks for */
|
||||
if (data_p->len > len)
|
||||
data_p->len = len;
|
||||
|
||||
if ((data_p->len % USB_MAX_PACKET_SIZE) == 0)
|
||||
data_p->require_zlp = TRUE;
|
||||
dev_p->value = ctrl.value;
|
||||
if (ctrl.len == 0)
|
||||
{
|
||||
dev_p->state = WAIT_STATUS_IN;
|
||||
st103_set_tx_count (ENDP0, 0);
|
||||
st103_ep_set_rxtx_status (ENDP0, EP_RX_STALL, EP_TX_VALID);
|
||||
}
|
||||
else
|
||||
data_p->require_zlp = FALSE;
|
||||
|
||||
dev_p->state = IN_DATA;
|
||||
handle_datastage_in ();
|
||||
}
|
||||
else if (ctrl_p->wLength == 0)
|
||||
{
|
||||
dev_p->state = WAIT_STATUS_IN;
|
||||
st103_set_tx_count (ENDP0, 0);
|
||||
st103_ep_set_rxtx_status (ENDP0, EP_RX_STALL, EP_TX_VALID);
|
||||
}
|
||||
else
|
||||
{
|
||||
dev_p->state = OUT_DATA;
|
||||
st103_ep_set_rx_status (ENDP0, EP_RX_VALID);
|
||||
{
|
||||
dev_p->state = OUT_DATA;
|
||||
st103_ep_set_rx_status (ENDP0, EP_RX_VALID);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -879,17 +811,16 @@ static void handle_in0 (void)
|
||||
handle_datastage_in ();
|
||||
else if (dev_p->state == WAIT_STATUS_IN)
|
||||
{
|
||||
if ((ctrl_p->bRequest == SET_ADDRESS) &&
|
||||
((ctrl_p->bmRequestType & (REQUEST_TYPE | RECIPIENT))
|
||||
if ((dev_p->bRequest == SET_ADDRESS) &&
|
||||
((dev_p->bmRequestType & (REQUEST_TYPE | RECIPIENT))
|
||||
== (STANDARD_REQUEST | DEVICE_RECIPIENT)))
|
||||
{
|
||||
st103_set_daddr (ctrl_p->wValue);
|
||||
usb_cb_handle_event (USB_EVENT_ADDRESS, ctrl_p->wValue);
|
||||
st103_set_daddr (dev_p->value);
|
||||
usb_cb_handle_event (USB_EVENT_ADDRESS, dev_p->value);
|
||||
}
|
||||
else
|
||||
usb_cb_ctrl_write_finish (ctrl_p->bmRequestType,
|
||||
ctrl_p->bRequest, ctrl_p->wValue,
|
||||
ctrl_p->wIndex, ctrl_p->wLength);
|
||||
usb_cb_ctrl_write_finish (dev_p->bmRequestType, dev_p->bRequest,
|
||||
dev_p->value);
|
||||
|
||||
dev_p->state = STALLED;
|
||||
}
|
||||
@@ -1111,7 +1042,7 @@ void usb_lld_set_feature (uint8_t feature)
|
||||
dev_p->current_feature = feature;
|
||||
}
|
||||
|
||||
void usb_lld_set_data_to_send (const void *p, size_t len)
|
||||
void usb_lld_set_data_to_recv (const void *p, size_t len)
|
||||
{
|
||||
data_p->addr = (uint8_t *)p;
|
||||
data_p->len = len;
|
||||
@@ -1189,3 +1120,49 @@ void usb_lld_from_pmabuf (void *dst, uint16_t addr, size_t n)
|
||||
*d = (w & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* BUF: Pointer to data memory. Data memory should not be allocated
|
||||
* on stack when BUFLEN > USB_MAX_PACKET_SIZE.
|
||||
*
|
||||
* BUFLEN: size of the data.
|
||||
*/
|
||||
int
|
||||
usb_lld_reply_request (const void *buf, size_t buflen, struct control_info *ctl)
|
||||
{
|
||||
uint32_t len_asked = ctl->len;
|
||||
uint32_t len;
|
||||
|
||||
data_p->addr = (void *)buf;
|
||||
data_p->len = buflen;
|
||||
|
||||
/* Restrict the data length to be the one host asks for */
|
||||
if (data_p->len > len_asked)
|
||||
data_p->len = len_asked;
|
||||
|
||||
if (data_p->len != 0 && (data_p->len % USB_MAX_PACKET_SIZE) == 0)
|
||||
data_p->require_zlp = 1;
|
||||
|
||||
if (data_p->len < USB_MAX_PACKET_SIZE)
|
||||
{
|
||||
len = data_p->len;
|
||||
dev_p->state = LAST_IN_DATA;
|
||||
}
|
||||
else
|
||||
{
|
||||
len = USB_MAX_PACKET_SIZE;
|
||||
dev_p->state = IN_DATA;
|
||||
}
|
||||
|
||||
if (len)
|
||||
{
|
||||
usb_lld_to_pmabuf (data_p->addr, st103_get_tx_addr (ENDP0), len);
|
||||
data_p->len -= len;
|
||||
data_p->addr += len;
|
||||
}
|
||||
|
||||
st103_set_tx_count (ENDP0, len);
|
||||
st103_ep_set_tx_status (ENDP0, EP_TX_VALID);
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
|
||||
@@ -14,7 +14,8 @@ OBJCOPY = $(CROSS)objcopy
|
||||
|
||||
MCU = cortex-m0 # -save-temps
|
||||
CWARN = -Wall -Wextra -Wstrict-prototypes
|
||||
DEFS = -DHAVE_SYS_H -DFREE_STANDING -DMHZ=48 -DUSE_WFI_FOR_IDLE
|
||||
DEFS = -DMAKE_ENTRY_PUBLIC \
|
||||
-DFREE_STANDING -DMHZ=48 -DUSE_WFI_FOR_IDLE
|
||||
OPT = -O3 -Os -g
|
||||
LIBS =
|
||||
|
||||
|
||||
12
example-fsm-55/README
Normal file
12
example-fsm-55/README
Normal file
@@ -0,0 +1,12 @@
|
||||
FSM-55 LED Matrix Display Board is a simple board to play 5x5 LED
|
||||
Display. Please see the product page:
|
||||
|
||||
http://www.seeedstudio.com/depot/FSM55-LED-Matrix-Display-p-2121.html
|
||||
|
||||
The file stlink-v2.cfg can be used for ST-Link/V2 with OpenOCD. You
|
||||
can flash by typing:
|
||||
|
||||
$ openocd -f ./stlink-v2.cfg -c "program build/hacker-emblem.elf"
|
||||
|
||||
Thanks to Kiwamu Okabe who kindly tested OpenOCD and wrote the
|
||||
configuration.
|
||||
1
example-fsm-55/board.h
Symbolic link
1
example-fsm-55/board.h
Symbolic link
@@ -0,0 +1 @@
|
||||
../board/board-fsm-55.h
|
||||
@@ -1 +1 @@
|
||||
debian-logo.c
|
||||
hh.c
|
||||
@@ -1,62 +1,32 @@
|
||||
/*
|
||||
* ST32F103 memory setup.
|
||||
* ST32F0 memory setup.
|
||||
*/
|
||||
__main_stack_size__ = 0x0100; /* Exception handlers */
|
||||
__process0_stack_size__ = 0x0100; /* Main program */
|
||||
__process0_stack_size__ = 0x0100; /* Main program */
|
||||
__process1_stack_size__ = 0x0100; /* first thread program */
|
||||
__process2_stack_size__ = 0x0100; /* second thread program */
|
||||
__process3_stack_size__ = 0x0100; /* third thread program */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/*
|
||||
flash0 : org = 0x08000000, len = 4k
|
||||
flash : org = 0x08000000+0x1000, len = 60k
|
||||
*/
|
||||
flash0 : org = 0x08000000, len = 1k
|
||||
flash : org = 0x08000000+0x0400, len = 60k
|
||||
ram : org = 0x20000000, len = 20k
|
||||
flash : org = 0x08000000, len = 16k
|
||||
ram : org = 0x20000000, len = 4k
|
||||
}
|
||||
|
||||
__flash_start__ = 0x08001000;
|
||||
__flash_end__ = 0x08020000;
|
||||
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_size__ = 20k;
|
||||
__ram_size__ = 4k;
|
||||
__ram_end__ = __ram_start__ + __ram_size__;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
|
||||
.sys : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
_sys = .;
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(16);
|
||||
*(.sys.version)
|
||||
build/sys.o(.text)
|
||||
build/sys.o(.text.*)
|
||||
build/sys.o(.rodata)
|
||||
build/sys.o(.rodata.*)
|
||||
. = ALIGN(1024);
|
||||
/*
|
||||
*(.sys.0)
|
||||
*(.sys.1)
|
||||
*(.sys.2)
|
||||
*/
|
||||
} > flash0
|
||||
|
||||
_text = .;
|
||||
|
||||
.startup : ALIGN(128) SUBALIGN(128)
|
||||
{
|
||||
KEEP(*(.startup.vectors))
|
||||
. = ALIGN (16);
|
||||
} > flash =0xffffffff
|
||||
|
||||
.text : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(16);
|
||||
*(.text.startup.*)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
@@ -65,8 +35,15 @@ SECTIONS
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
. = ALIGN(8);
|
||||
} > flash
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.startup.vectors)
|
||||
*(.bss.startup.0)
|
||||
}
|
||||
|
||||
.ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
|
||||
|
||||
.ARM.exidx : {
|
||||
@@ -84,28 +61,21 @@ SECTIONS
|
||||
_etext = .;
|
||||
_textdata = _etext;
|
||||
|
||||
.vectors_in_ram :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__vector_ram_addr__ = .;
|
||||
KEEP(*(.bss.startup.*))
|
||||
} > ram
|
||||
|
||||
.process_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__process3_stack_base__ = .;
|
||||
. += __process3_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack3_end__ = .;
|
||||
__process3_stack_end__ = .;
|
||||
__process2_stack_base__ = .;
|
||||
. += __process2_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack2_end__ = .;
|
||||
__process2_stack_end__ = .;
|
||||
__process1_stack_base__ = .;
|
||||
. += __process1_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack1_end__ = .;
|
||||
__process1_stack_end__ = .;
|
||||
__process0_stack_base__ = .;
|
||||
. += __process0_stack_size__;
|
||||
. = ALIGN(8);
|
||||
|
||||
11
example-fsm-55/stlink-v2.cfg
Normal file
11
example-fsm-55/stlink-v2.cfg
Normal file
@@ -0,0 +1,11 @@
|
||||
# Contributed by Kiwamu Okabe
|
||||
|
||||
source [find interface/stlink-v2.cfg]
|
||||
transport select hla_swd
|
||||
|
||||
# The STM32F030F4P6 is a *tightly* constrained chip; the work area size must be
|
||||
# similarly constrained.
|
||||
set WORKAREASIZE 0x1000
|
||||
source [find target/stm32f0x.cfg]
|
||||
|
||||
# use hardware reset, connect under reset
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* sys.c - system routines for the initial page for STM32F030 / STM32F103.
|
||||
* sys.c - No system routines, but only RESET handler for STM32F030.
|
||||
*
|
||||
* Copyright (C) 2013, 2014 Flying Stone Technology
|
||||
* Copyright (C) 2015 Flying Stone Technology
|
||||
* Author: NIIBE Yutaka <gniibe@fsij.org>
|
||||
*
|
||||
* Copying and distribution of this file, with or without modification,
|
||||
@@ -9,762 +9,110 @@
|
||||
* notice and this notice are preserved. This file is offered as-is,
|
||||
* without any warranty.
|
||||
*
|
||||
* When the flash ROM is protected, we cannot modify the initial page.
|
||||
* We put some system routines (which is useful for any program) here.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "board.h"
|
||||
|
||||
|
||||
#define CORTEX_PRIORITY_BITS 4
|
||||
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
|
||||
#define USB_LP_CAN1_RX0_IRQn 20
|
||||
#define STM32_USB_IRQ_PRIORITY 11
|
||||
|
||||
#define STM32_SW_HSI (0 << 0)
|
||||
#define STM32_SW_PLL (2 << 0)
|
||||
#define STM32_PLLSRC_HSI (0 << 16)
|
||||
#define STM32_PLLSRC_HSE (1 << 16)
|
||||
|
||||
#define STM32_PLLXTPRE_DIV1 (0 << 17)
|
||||
#define STM32_PLLXTPRE_DIV2 (1 << 17)
|
||||
|
||||
#define STM32_HPRE_DIV1 (0 << 4)
|
||||
|
||||
#define STM32_PPRE1_DIV1 (0 << 8)
|
||||
#define STM32_PPRE1_DIV2 (4 << 8)
|
||||
|
||||
#define STM32_PPRE2_DIV1 (0 << 11)
|
||||
#define STM32_PPRE2_DIV2 (4 << 11)
|
||||
|
||||
#define STM32_ADCPRE_DIV4 (1 << 14)
|
||||
#define STM32_ADCPRE_DIV6 (2 << 14)
|
||||
|
||||
#define STM32_USBPRE_DIV1P5 (0 << 22)
|
||||
|
||||
#define STM32_MCO_NOCLOCK (0 << 24)
|
||||
|
||||
#if MCU_STM32F0
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSI
|
||||
#define STM32_FLASHBITS 0x00000011
|
||||
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
|
||||
#else
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_FLASHBITS 0x00000012
|
||||
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
|
||||
#endif
|
||||
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV6
|
||||
#define STM32_MCOSEL STM32_MCO_NOCLOCK
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
|
||||
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
|
||||
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
||||
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||
|
||||
struct NVIC {
|
||||
uint32_t ISER[8];
|
||||
uint32_t unused1[24];
|
||||
uint32_t ICER[8];
|
||||
uint32_t unused2[24];
|
||||
uint32_t ISPR[8];
|
||||
uint32_t unused3[24];
|
||||
uint32_t ICPR[8];
|
||||
uint32_t unused4[24];
|
||||
uint32_t IABR[8];
|
||||
uint32_t unused5[56];
|
||||
uint32_t IPR[60];
|
||||
};
|
||||
|
||||
static struct NVIC *const NVICBase = ((struct NVIC *const)0xE000E100);
|
||||
#define NVIC_ISER(n) (NVICBase->ISER[n >> 5])
|
||||
#define NVIC_ICPR(n) (NVICBase->ICPR[n >> 5])
|
||||
#define NVIC_IPR(n) (NVICBase->IPR[n >> 2])
|
||||
|
||||
static void
|
||||
nvic_enable_vector (uint32_t n, uint32_t prio)
|
||||
{
|
||||
unsigned int sh = (n & 3) << 3;
|
||||
|
||||
NVIC_IPR (n) = (NVIC_IPR(n) & ~(0xFF << sh)) | (prio << sh);
|
||||
NVIC_ICPR (n) = 1 << (n & 0x1F);
|
||||
NVIC_ISER (n) = 1 << (n & 0x1F);
|
||||
}
|
||||
|
||||
|
||||
#define PERIPH_BASE 0x40000000
|
||||
#define APBPERIPH_BASE PERIPH_BASE
|
||||
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
||||
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
|
||||
|
||||
struct RCC {
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t CFGR;
|
||||
volatile uint32_t CIR;
|
||||
volatile uint32_t APB2RSTR;
|
||||
volatile uint32_t APB1RSTR;
|
||||
volatile uint32_t AHBENR;
|
||||
volatile uint32_t APB2ENR;
|
||||
volatile uint32_t APB1ENR;
|
||||
volatile uint32_t BDCR;
|
||||
volatile uint32_t CSR;
|
||||
#if MCU_STM32F0
|
||||
volatile uint32_t AHBRSTR;
|
||||
volatile uint32_t CFGR2;
|
||||
volatile uint32_t CFGR3;
|
||||
volatile uint32_t CR2;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
|
||||
static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
|
||||
|
||||
#define RCC_APB1ENR_USBEN 0x00800000
|
||||
#define RCC_APB1RSTR_USBRST 0x00800000
|
||||
|
||||
#define RCC_CR_HSION 0x00000001
|
||||
#define RCC_CR_HSIRDY 0x00000002
|
||||
#define RCC_CR_HSITRIM 0x000000F8
|
||||
#define RCC_CR_HSEON 0x00010000
|
||||
#define RCC_CR_HSERDY 0x00020000
|
||||
#define RCC_CR_PLLON 0x01000000
|
||||
#define RCC_CR_PLLRDY 0x02000000
|
||||
|
||||
#define RCC_CFGR_SWS 0x0000000C
|
||||
#define RCC_CFGR_SWS_HSI 0x00000000
|
||||
|
||||
#define RCC_AHBENR_CRCEN 0x0040
|
||||
|
||||
#if MCU_STM32F0
|
||||
#define RCC_AHBRSTR_IOPARST 0x00020000
|
||||
#define RCC_AHBRSTR_IOPBRST 0x00040000
|
||||
#define RCC_AHBRSTR_IOPCRST 0x00080000
|
||||
#define RCC_AHBRSTR_IOPDRST 0x00100000
|
||||
#define RCC_AHBRSTR_IOPFRST 0x00400000
|
||||
|
||||
#define RCC_AHBENR_IOPAEN 0x00020000
|
||||
#define RCC_AHBENR_IOPBEN 0x00040000
|
||||
#define RCC_AHBENR_IOPCEN 0x00080000
|
||||
#define RCC_AHBENR_IOPDEN 0x00100000
|
||||
#define RCC_AHBENR_IOPFEN 0x00400000
|
||||
|
||||
#define RCC_APB2RSTR_SYSCFGRST 0x00000001
|
||||
#define RCC_APB2ENR_SYSCFGEN 0x00000001
|
||||
#else
|
||||
#define RCC_APB2RSTR_AFIORST 0x00000001
|
||||
#define RCC_APB2RSTR_IOPARST 0x00000004
|
||||
#define RCC_APB2RSTR_IOPBRST 0x00000008
|
||||
#define RCC_APB2RSTR_IOPCRST 0x00000010
|
||||
#define RCC_APB2RSTR_IOPDRST 0x00000020
|
||||
|
||||
#define RCC_APB2ENR_AFIOEN 0x00000001
|
||||
#define RCC_APB2ENR_IOPAEN 0x00000004
|
||||
#define RCC_APB2ENR_IOPBEN 0x00000008
|
||||
#define RCC_APB2ENR_IOPCEN 0x00000010
|
||||
#define RCC_APB2ENR_IOPDEN 0x00000020
|
||||
#endif
|
||||
|
||||
#if MCU_STM32F0
|
||||
struct SYSCFG {
|
||||
volatile uint32_t CFGR1;
|
||||
uint32_t dummy0;
|
||||
volatile uint32_t EXTICR[4];
|
||||
volatile uint32_t CFGR2;
|
||||
};
|
||||
#define SYSCFG_CFGR1_MEM_MODE 0x03
|
||||
|
||||
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
|
||||
static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
|
||||
#endif
|
||||
|
||||
struct FLASH {
|
||||
volatile uint32_t ACR;
|
||||
volatile uint32_t KEYR;
|
||||
volatile uint32_t OPTKEYR;
|
||||
volatile uint32_t SR;
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t AR;
|
||||
volatile uint32_t RESERVED;
|
||||
volatile uint32_t OBR;
|
||||
volatile uint32_t WRPR;
|
||||
};
|
||||
|
||||
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
|
||||
static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
|
||||
|
||||
static void
|
||||
clock_init (void)
|
||||
{
|
||||
/* HSI setup */
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY))
|
||||
;
|
||||
/* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
|
||||
RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
|
||||
RCC->CFGR = 0;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
|
||||
;
|
||||
|
||||
#if !MCU_STM32F0
|
||||
/* HSE setup */
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY))
|
||||
;
|
||||
#endif
|
||||
|
||||
/* PLL setup */
|
||||
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
;
|
||||
|
||||
/* Clock settings */
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
|
||||
| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
|
||||
/* Switching on the configured clock source. */
|
||||
RCC->CFGR |= STM32_SW;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
;
|
||||
|
||||
/*
|
||||
* We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
|
||||
*/
|
||||
|
||||
/* Flash setup */
|
||||
FLASH->ACR = STM32_FLASHBITS;
|
||||
|
||||
/* CRC */
|
||||
RCC->AHBENR |= RCC_AHBENR_CRCEN;
|
||||
|
||||
#if MCU_STM32F0
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
|
||||
RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
|
||||
RCC->APB2RSTR = 0;
|
||||
|
||||
/* Use vectors on RAM */
|
||||
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if MCU_STM32F0
|
||||
struct GPIO {
|
||||
volatile uint32_t MODER;
|
||||
volatile uint16_t OTYPER;
|
||||
uint16_t dummy0;
|
||||
volatile uint32_t OSPEEDR;
|
||||
volatile uint32_t PUPDR;
|
||||
volatile uint16_t IDR;
|
||||
uint16_t dummy1;
|
||||
volatile uint16_t ODR;
|
||||
uint16_t dummy2;
|
||||
volatile uint16_t BSRR;
|
||||
uint16_t dummy3;
|
||||
volatile uint32_t LCKR;
|
||||
volatile uint32_t AFR[2];
|
||||
volatile uint16_t BRR;
|
||||
uint16_t dummy4;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOF ((struct GPIO *) GPIOF_BASE)
|
||||
#else
|
||||
struct AFIO
|
||||
{
|
||||
volatile uint32_t EVCR;
|
||||
volatile uint32_t MAPR;
|
||||
volatile uint32_t EXTICR[4];
|
||||
uint32_t RESERVED0;
|
||||
volatile uint32_t MAPR2;
|
||||
};
|
||||
|
||||
#define AFIO_BASE 0x40010000
|
||||
static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
|
||||
|
||||
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
|
||||
#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
|
||||
|
||||
struct GPIO {
|
||||
volatile uint32_t CRL;
|
||||
volatile uint32_t CRH;
|
||||
volatile uint32_t IDR;
|
||||
volatile uint32_t ODR;
|
||||
volatile uint32_t BSRR;
|
||||
volatile uint32_t BRR;
|
||||
volatile uint32_t LCKR;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
|
||||
#define GPIOE ((struct GPIO *) GPIOE_BASE)
|
||||
#endif
|
||||
|
||||
static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
|
||||
#ifdef GPIO_USB_BASE
|
||||
static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
|
||||
#endif
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
|
||||
#endif
|
||||
|
||||
static void
|
||||
gpio_init (void)
|
||||
{
|
||||
/* Enable GPIO clock. */
|
||||
#if MCU_STM32F0
|
||||
RCC->AHBENR |= RCC_ENR_IOP_EN;
|
||||
RCC->AHBRSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->AHBRSTR = 0;
|
||||
#else
|
||||
RCC->APB2ENR |= RCC_ENR_IOP_EN;
|
||||
RCC->APB2RSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->APB2RSTR = 0;
|
||||
#endif
|
||||
|
||||
#if MCU_STM32F0
|
||||
GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
|
||||
GPIO_LED->OTYPER = VAL_GPIO_OTYPER;
|
||||
GPIO_LED->MODER = VAL_GPIO_MODER;
|
||||
GPIO_LED->PUPDR = VAL_GPIO_PUPDR;
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
|
||||
GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
|
||||
GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
|
||||
GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
|
||||
#endif
|
||||
#else
|
||||
#ifdef AFIO_MAPR_SOMETHING
|
||||
AFIO->MAPR |= AFIO_MAPR_SOMETHING;
|
||||
#endif
|
||||
|
||||
GPIO_USB->ODR = VAL_GPIO_ODR;
|
||||
GPIO_USB->CRH = VAL_GPIO_CRH;
|
||||
GPIO_USB->CRL = VAL_GPIO_CRL;
|
||||
|
||||
#if GPIO_USB_BASE != GPIO_LED_BASE
|
||||
GPIO_LED->ODR = VAL_GPIO_LED_ODR;
|
||||
GPIO_LED->CRH = VAL_GPIO_LED_CRH;
|
||||
GPIO_LED->CRL = VAL_GPIO_LED_CRL;
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
|
||||
GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
|
||||
GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
usb_cable_config (int enable)
|
||||
{
|
||||
#if defined(GPIO_USB_SET_TO_ENABLE)
|
||||
if (enable)
|
||||
GPIO_USB->BSRR = (1 << GPIO_USB_SET_TO_ENABLE);
|
||||
else
|
||||
GPIO_USB->BRR = (1 << GPIO_USB_SET_TO_ENABLE);
|
||||
#elif defined(GPIO_USB_CLEAR_TO_ENABLE)
|
||||
if (enable)
|
||||
GPIO_USB->BRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
|
||||
else
|
||||
GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
|
||||
#else
|
||||
(void)enable;
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
set_led (int on)
|
||||
{
|
||||
#if defined(GPIO_LED_CLEAR_TO_EMIT)
|
||||
if (on)
|
||||
GPIO_LED->BRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
|
||||
else
|
||||
GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
|
||||
#else
|
||||
if (on)
|
||||
GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT);
|
||||
else
|
||||
GPIO_LED->BRR = (1 << GPIO_LED_SET_TO_EMIT);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void wait (int count)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
asm volatile ("" : : "r" (i) : "memory");
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
usb_lld_sys_shutdown (void)
|
||||
{
|
||||
RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
|
||||
RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
|
||||
usb_cable_config (0);
|
||||
}
|
||||
|
||||
static void
|
||||
usb_lld_sys_init (void)
|
||||
{
|
||||
if ((RCC->APB1ENR & RCC_APB1ENR_USBEN)
|
||||
&& (RCC->APB1RSTR & RCC_APB1RSTR_USBRST) == 0)
|
||||
/* Make sure the device is disconnected, even after core reset. */
|
||||
{
|
||||
usb_lld_sys_shutdown ();
|
||||
/* Disconnect requires SE0 (>= 2.5uS). */
|
||||
wait (300);
|
||||
}
|
||||
|
||||
usb_cable_config (1);
|
||||
RCC->APB1ENR |= RCC_APB1ENR_USBEN;
|
||||
nvic_enable_vector (USB_LP_CAN1_RX0_IRQn,
|
||||
CORTEX_PRIORITY_MASK (STM32_USB_IRQ_PRIORITY));
|
||||
/*
|
||||
* Note that we also have other IRQ(s):
|
||||
* USB_HP_CAN1_TX_IRQn (for double-buffered or isochronous)
|
||||
* USBWakeUp_IRQn (suspend/resume)
|
||||
*/
|
||||
RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
|
||||
RCC->APB1RSTR = 0;
|
||||
}
|
||||
|
||||
#define FLASH_KEY1 0x45670123UL
|
||||
#define FLASH_KEY2 0xCDEF89ABUL
|
||||
|
||||
enum flash_status
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_PG,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
};
|
||||
|
||||
static void __attribute__ ((used))
|
||||
flash_unlock (void)
|
||||
{
|
||||
FLASH->KEYR = FLASH_KEY1;
|
||||
FLASH->KEYR = FLASH_KEY2;
|
||||
}
|
||||
|
||||
|
||||
#define intr_disable() asm volatile ("cpsid i" : : : "memory")
|
||||
#define intr_enable() asm volatile ("cpsie i" : : : "memory")
|
||||
|
||||
#define FLASH_SR_BSY 0x01
|
||||
#define FLASH_SR_PGERR 0x04
|
||||
#define FLASH_SR_WRPRTERR 0x10
|
||||
#define FLASH_SR_EOP 0x20
|
||||
|
||||
#define FLASH_CR_PG 0x0001
|
||||
#define FLASH_CR_PER 0x0002
|
||||
#define FLASH_CR_MER 0x0004
|
||||
#define FLASH_CR_OPTPG 0x0010
|
||||
#define FLASH_CR_OPTER 0x0020
|
||||
#define FLASH_CR_STRT 0x0040
|
||||
#define FLASH_CR_LOCK 0x0080
|
||||
#define FLASH_CR_OPTWRE 0x0200
|
||||
#define FLASH_CR_ERRIE 0x0400
|
||||
#define FLASH_CR_EOPIE 0x1000
|
||||
|
||||
static int
|
||||
flash_wait_for_last_operation (uint32_t timeout)
|
||||
{
|
||||
int status;
|
||||
|
||||
do
|
||||
{
|
||||
status = FLASH->SR;
|
||||
if (--timeout == 0)
|
||||
break;
|
||||
}
|
||||
while ((status & FLASH_SR_BSY) != 0);
|
||||
|
||||
return status & (FLASH_SR_BSY|FLASH_SR_PGERR|FLASH_SR_WRPRTERR);
|
||||
}
|
||||
|
||||
#define FLASH_PROGRAM_TIMEOUT 0x00010000
|
||||
#define FLASH_ERASE_TIMEOUT 0x01000000
|
||||
|
||||
static int
|
||||
flash_program_halfword (uint32_t addr, uint16_t data)
|
||||
{
|
||||
int status;
|
||||
|
||||
status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
|
||||
|
||||
intr_disable ();
|
||||
if (status == 0)
|
||||
{
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(volatile uint16_t *)addr = data;
|
||||
|
||||
status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
|
||||
FLASH->CR &= ~FLASH_CR_PG;
|
||||
}
|
||||
intr_enable ();
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int
|
||||
flash_erase_page (uint32_t addr)
|
||||
{
|
||||
int status;
|
||||
|
||||
status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
|
||||
|
||||
intr_disable ();
|
||||
if (status == 0)
|
||||
{
|
||||
FLASH->CR |= FLASH_CR_PER;
|
||||
FLASH->AR = addr;
|
||||
FLASH->CR |= FLASH_CR_STRT;
|
||||
|
||||
status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
|
||||
FLASH->CR &= ~FLASH_CR_PER;
|
||||
}
|
||||
intr_enable ();
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int
|
||||
flash_check_blank (const uint8_t *p_start, size_t size)
|
||||
{
|
||||
const uint8_t *p;
|
||||
|
||||
for (p = p_start; p < p_start + size; p++)
|
||||
if (*p != 0xff)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
extern uint8_t __flash_start__, __flash_end__;
|
||||
|
||||
static int
|
||||
flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
|
||||
{
|
||||
int status;
|
||||
uint32_t flash_start = (uint32_t)&__flash_start__;
|
||||
uint32_t flash_end = (uint32_t)&__flash_end__;
|
||||
|
||||
if (dst_addr < flash_start || dst_addr + len > flash_end)
|
||||
return 0;
|
||||
|
||||
while (len)
|
||||
{
|
||||
uint16_t hw = *src++;
|
||||
|
||||
hw |= (*src++ << 8);
|
||||
status = flash_program_halfword (dst_addr, hw);
|
||||
if (status != 0)
|
||||
return 0; /* error return */
|
||||
|
||||
dst_addr += 2;
|
||||
len -= 2;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#define OPTION_BYTES_ADDR 0x1ffff800
|
||||
|
||||
static int
|
||||
flash_protect (void)
|
||||
{
|
||||
int status;
|
||||
uint32_t option_bytes_value;
|
||||
|
||||
status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
|
||||
|
||||
intr_disable ();
|
||||
if (status == 0)
|
||||
{
|
||||
FLASH->OPTKEYR = FLASH_KEY1;
|
||||
FLASH->OPTKEYR = FLASH_KEY2;
|
||||
|
||||
FLASH->CR |= FLASH_CR_OPTER;
|
||||
FLASH->CR |= FLASH_CR_STRT;
|
||||
|
||||
status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
|
||||
FLASH->CR &= ~FLASH_CR_OPTER;
|
||||
}
|
||||
intr_enable ();
|
||||
|
||||
if (status != 0)
|
||||
return 0;
|
||||
|
||||
option_bytes_value = *(uint32_t *)OPTION_BYTES_ADDR;
|
||||
return (option_bytes_value & 0xff) == 0xff ? 1 : 0;
|
||||
}
|
||||
|
||||
static void __attribute__((naked))
|
||||
flash_erase_all_and_exec (void (*entry)(void))
|
||||
{
|
||||
uint32_t addr = (uint32_t)&__flash_start__;
|
||||
uint32_t end = (uint32_t)&__flash_end__;
|
||||
int r;
|
||||
|
||||
while (addr < end)
|
||||
{
|
||||
r = flash_erase_page (addr);
|
||||
if (r != 0)
|
||||
break;
|
||||
|
||||
addr += FLASH_PAGE_SIZE;
|
||||
}
|
||||
|
||||
if (addr >= end)
|
||||
(*entry) ();
|
||||
|
||||
for (;;);
|
||||
}
|
||||
|
||||
struct SCB
|
||||
{
|
||||
volatile uint32_t CPUID;
|
||||
volatile uint32_t ICSR;
|
||||
volatile uint32_t VTOR;
|
||||
volatile uint32_t AIRCR;
|
||||
volatile uint32_t SCR;
|
||||
volatile uint32_t CCR;
|
||||
volatile uint8_t SHP[12];
|
||||
volatile uint32_t SHCSR;
|
||||
volatile uint32_t CFSR;
|
||||
volatile uint32_t HFSR;
|
||||
volatile uint32_t DFSR;
|
||||
volatile uint32_t MMFAR;
|
||||
volatile uint32_t BFAR;
|
||||
volatile uint32_t AFSR;
|
||||
volatile uint32_t PFR[2];
|
||||
volatile uint32_t DFR;
|
||||
volatile uint32_t ADR;
|
||||
volatile uint32_t MMFR[4];
|
||||
volatile uint32_t ISAR[5];
|
||||
};
|
||||
|
||||
#define SCS_BASE (0xE000E000)
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00)
|
||||
static struct SCB *const SCB = ((struct SCB *const) SCB_BASE);
|
||||
|
||||
#define SYSRESETREQ 0x04
|
||||
static void
|
||||
nvic_system_reset (void)
|
||||
{
|
||||
SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
|
||||
asm volatile ("dsb");
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static void __attribute__ ((naked))
|
||||
reset (void)
|
||||
{
|
||||
/*
|
||||
* This code may not be at start of flash ROM, because of DFU.
|
||||
* So, we take the address from PC.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__
|
||||
asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
|
||||
"ldr r0, 1f\n\t" /* r0 = RAM start */
|
||||
"mov r1, pc\n\t" /* r1 = (PC + 0x0400) & ~0x03ff */
|
||||
"mov r2, #0x04\n\t"
|
||||
"lsl r2, #8\n\t"
|
||||
"add r1, r1, r2\n\t"
|
||||
"sub r2, r2, #1\n\t"
|
||||
"bic r1, r1, r2\n\t"
|
||||
"mov r2, #188\n"
|
||||
"2:\n\t" /* Copy vectors. It will be enabled later by clock_init. */
|
||||
"ldr r3, [r1, r2]\n\t"
|
||||
"str r3, [r0, r2]\n\t"
|
||||
"sub r2, #4\n\t"
|
||||
"bcs 2b\n\t"
|
||||
"msr MSP, r3\n\t" /* Main (exception handler) stack. */
|
||||
"ldr r0, [r1, #4]\n\t" /* Reset handler. */
|
||||
"bx r0\n\t"
|
||||
".align 2\n"
|
||||
"1: .word 0x20000000"
|
||||
"mov r0, pc\n\t" /* r0 = PC & ~0x0fff */
|
||||
"mov r1, #0x10\n\t"
|
||||
"lsl r1, #8\n\t"
|
||||
"sub r1, r1, #1\n\t"
|
||||
"bic r0, r0, r1\n\t"
|
||||
"ldr r2, [r0]\n\t"
|
||||
"msr MSP, r2\n\t" /* Main (exception handler) stack. */
|
||||
"b entry\n\t"
|
||||
: /* no output */ : /* no input */ : "memory");
|
||||
#else
|
||||
extern const unsigned long *FT0, *FT1, *FT2;
|
||||
asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
|
||||
"ldr r0, 1f\n\t" /* r0 = SCR */
|
||||
"mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */
|
||||
"mov r2, #0x1000\n\t"
|
||||
"add r1, r1, r2\n\t"
|
||||
"sub r2, r2, #1\n\t"
|
||||
"bic r1, r1, r2\n\t"
|
||||
"str r1, [r0, #8]\n\t" /* Set SCR->VCR */
|
||||
"ldr r0, [r1], #4\n\t"
|
||||
"msr MSP, r0\n\t" /* Main (exception handler) stack. */
|
||||
"ldr r0, [r1]\n\t" /* Reset handler. */
|
||||
"bx r0\n\t"
|
||||
".align 2\n"
|
||||
"1: .word 0xe000ed00"
|
||||
: /* no output */ : /* no input */ : "memory");
|
||||
/* Artificial entry to refer FT0, FT1, and FT2. */
|
||||
asm volatile (""
|
||||
: : "r" (FT0), "r" (FT1), "r" (FT2));
|
||||
#endif
|
||||
/* Never reach here. */
|
||||
}
|
||||
|
||||
extern uint8_t __main_stack_end__;
|
||||
extern void svc (void);
|
||||
extern void preempt (void);
|
||||
extern void chx_timer_expired (void);
|
||||
extern void chx_handle_intr (void);
|
||||
|
||||
static void nmi (void)
|
||||
{
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static void __attribute__ ((naked))
|
||||
hard_fault (void)
|
||||
{
|
||||
register uint32_t primask;
|
||||
|
||||
asm ("mrs %0, PRIMASK" : "=r" (primask));
|
||||
|
||||
if (primask)
|
||||
asm volatile ("b svc");
|
||||
else
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static void mem_manage (void)
|
||||
{
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static void bus_fault (void)
|
||||
{
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static void usage_fault (void)
|
||||
{
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static void none (void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
typedef void (*handler)(void);
|
||||
extern uint8_t __ram_end__;
|
||||
extern uint8_t __main_stack_end__;
|
||||
|
||||
handler vector[] __attribute__ ((section(".vectors"))) = {
|
||||
(handler)&__ram_end__,
|
||||
(handler)&__main_stack_end__,
|
||||
reset,
|
||||
(handler)set_led,
|
||||
flash_unlock,
|
||||
(handler)flash_program_halfword,
|
||||
(handler)flash_erase_page,
|
||||
(handler)flash_check_blank,
|
||||
(handler)flash_write,
|
||||
(handler)flash_protect,
|
||||
(handler)flash_erase_all_and_exec,
|
||||
usb_lld_sys_init,
|
||||
usb_lld_sys_shutdown,
|
||||
nvic_system_reset,
|
||||
clock_init,
|
||||
gpio_init,
|
||||
NULL,
|
||||
};
|
||||
|
||||
const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
|
||||
3*2+2, /* bLength */
|
||||
0x03, /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
|
||||
/* sys version: "2.0" */
|
||||
'2', 0, '.', 0, '0', 0,
|
||||
nmi, /* nmi */
|
||||
hard_fault, /* hard fault */
|
||||
/* 0x10 */
|
||||
mem_manage, /* mem manage */
|
||||
bus_fault, /* bus fault */
|
||||
usage_fault, /* usage fault */
|
||||
none,
|
||||
/* 0x20 */
|
||||
none, none, none, /* reserved */
|
||||
svc, /* SVCall */
|
||||
none, /* Debug */
|
||||
none, /* reserved */
|
||||
preempt, /* PendSV */
|
||||
chx_timer_expired, /* SysTick */
|
||||
/* 0x40 */
|
||||
chx_handle_intr /* WWDG */, chx_handle_intr /* PVD */,
|
||||
chx_handle_intr /* TAMPER */, chx_handle_intr /* RTC */,
|
||||
chx_handle_intr /* FLASH */, chx_handle_intr /* RCC */,
|
||||
chx_handle_intr /* EXTI0 */, chx_handle_intr /* EXTI1 */,
|
||||
/* 0x60 */
|
||||
chx_handle_intr /* EXTI2 */, chx_handle_intr /* EXTI3 */,
|
||||
chx_handle_intr /* EXTI4 */, chx_handle_intr /* DMA1 CH1 */,
|
||||
chx_handle_intr /* DMA1 CH2 */, chx_handle_intr /* DMA1 CH3 */,
|
||||
chx_handle_intr /* DMA1 CH4 */, chx_handle_intr /* DMA1 CH5 */,
|
||||
/* 0x80 */
|
||||
chx_handle_intr /* DMA1 CH6 */, chx_handle_intr /* DMA1 CH7 */,
|
||||
chx_handle_intr /* ADC1_2 */, chx_handle_intr /* USB HP */,
|
||||
/* 0x90 */
|
||||
chx_handle_intr /* USB LP */, chx_handle_intr /* CAN */,
|
||||
/* ... and more. EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
|
||||
chx_handle_intr, chx_handle_intr,
|
||||
/* 0xA0 */
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
chx_handle_intr, chx_handle_intr, chx_handle_intr, chx_handle_intr,
|
||||
/* 0xc0 */
|
||||
};
|
||||
|
||||
@@ -1,115 +0,0 @@
|
||||
extern const uint8_t sys_version[8];
|
||||
|
||||
typedef void (*handler)(void);
|
||||
extern handler vector[16];
|
||||
|
||||
static inline const uint8_t *
|
||||
unique_device_id (void)
|
||||
{
|
||||
/* STM32F103 has 96-bit unique device identifier */
|
||||
const uint8_t *addr = (const uint8_t *)0x1ffff7e8;
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static inline void
|
||||
set_led (int on)
|
||||
{
|
||||
void (*func) (int) = (void (*)(int))vector[2];
|
||||
|
||||
return (*func) (on);
|
||||
}
|
||||
|
||||
static inline void
|
||||
flash_unlock (void)
|
||||
{
|
||||
(*vector[3]) ();
|
||||
}
|
||||
|
||||
static inline int
|
||||
flash_program_halfword (uint32_t addr, uint16_t data)
|
||||
{
|
||||
int (*func) (uint32_t, uint16_t) = (int (*)(uint32_t, uint16_t))vector[4];
|
||||
|
||||
return (*func) (addr, data);
|
||||
}
|
||||
|
||||
static inline int
|
||||
flash_erase_page (uint32_t addr)
|
||||
{
|
||||
int (*func) (uint32_t) = (int (*)(uint32_t))vector[5];
|
||||
|
||||
return (*func) (addr);
|
||||
}
|
||||
|
||||
static inline int
|
||||
flash_check_blank (const uint8_t *p_start, size_t size)
|
||||
{
|
||||
int (*func) (const uint8_t *, int) = (int (*)(const uint8_t *, int))vector[6];
|
||||
|
||||
return (*func) (p_start, size);
|
||||
}
|
||||
|
||||
static inline int
|
||||
flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
|
||||
{
|
||||
int (*func) (uint32_t, const uint8_t *, size_t)
|
||||
= (int (*)(uint32_t, const uint8_t *, size_t))vector[7];
|
||||
|
||||
return (*func) (dst_addr, src, len);
|
||||
}
|
||||
|
||||
static inline int
|
||||
flash_protect (void)
|
||||
{
|
||||
int (*func) (void) = (int (*)(void))vector[8];
|
||||
|
||||
return (*func) ();
|
||||
}
|
||||
|
||||
static inline void __attribute__((noreturn))
|
||||
flash_erase_all_and_exec (void (*entry)(void))
|
||||
{
|
||||
void (*func) (void (*)(void)) = (void (*)(void (*)(void)))vector[9];
|
||||
|
||||
(*func) (entry);
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static inline void
|
||||
usb_lld_sys_init (void)
|
||||
{
|
||||
(*vector[10]) ();
|
||||
}
|
||||
|
||||
static inline void
|
||||
usb_lld_sys_shutdown (void)
|
||||
{
|
||||
(*vector[11]) ();
|
||||
}
|
||||
|
||||
static inline void
|
||||
nvic_system_reset (void)
|
||||
{
|
||||
(*vector[12]) ();
|
||||
}
|
||||
|
||||
/*
|
||||
* Users can override INLINE by 'attribute((used))' to have an
|
||||
* implementation defined.
|
||||
*/
|
||||
#if !defined(INLINE)
|
||||
#define INLINE __inline__
|
||||
#endif
|
||||
|
||||
static INLINE void
|
||||
clock_init (void)
|
||||
{
|
||||
(*vector[13]) ();
|
||||
}
|
||||
|
||||
static INLINE void
|
||||
gpio_init (void)
|
||||
{
|
||||
(*vector[14]) ();
|
||||
}
|
||||
@@ -2,9 +2,14 @@
|
||||
|
||||
PROJECT = sample
|
||||
|
||||
### Currently, it's for STM32F0 Discovery.
|
||||
### Please change lines started with '###' for Cortex-M3 board.
|
||||
|
||||
CHOPSTX = ..
|
||||
LDSCRIPT= sample.ld
|
||||
CSRC = sys.c aes-constant-ft.c sample.c
|
||||
### LDSCRIPT= sample.ld.m3
|
||||
CSRC = sys.c sample.c
|
||||
### CSRC = sys.c aes-constant-ft.c sample.c
|
||||
|
||||
###################################
|
||||
CROSS = arm-none-eabi-
|
||||
@@ -12,11 +17,11 @@ CC = $(CROSS)gcc
|
||||
LD = $(CROSS)gcc
|
||||
OBJCOPY = $(CROSS)objcopy
|
||||
|
||||
# MCU = cortex-m3
|
||||
### MCU = cortex-m3
|
||||
MCU = cortex-m0
|
||||
CWARN = -Wall -Wextra -Wstrict-prototypes
|
||||
DEFS = -DHAVE_SYS_H -DFREE_STANDING -DMHZ=48
|
||||
# DEFS = -DFREE_STANDING -DHAVE_SYS_H -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
|
||||
### DEFS = -DFREE_STANDING -DHAVE_SYS_H -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
|
||||
OPT = -O3 -Os -g
|
||||
LIBS =
|
||||
|
||||
|
||||
1
example-led/board.h
Symbolic link
1
example-led/board.h
Symbolic link
@@ -0,0 +1 @@
|
||||
../board/board-stm32f0-discovery.h
|
||||
@@ -1,26 +1,19 @@
|
||||
/*
|
||||
* ST32F103 memory setup.
|
||||
* ST32F0 memory setup.
|
||||
*/
|
||||
__main_stack_size__ = 0x0100; /* Exception handlers */
|
||||
__process0_stack_size__ = 0x0100; /* Main program */
|
||||
__process0_stack_size__ = 0x0100; /* Main program */
|
||||
__process1_stack_size__ = 0x0100; /* first thread program */
|
||||
__process2_stack_size__ = 0x0100; /* second thread program */
|
||||
__process3_stack_size__ = 0x0100; /* third thread program */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/*
|
||||
flash0 : org = 0x08000000, len = 4k
|
||||
flash : org = 0x08000000+0x1000, len = 60k
|
||||
*/
|
||||
flash0 : org = 0x08000000, len = 1k
|
||||
flash : org = 0x08000000+0x0400, len = 60k
|
||||
ram : org = 0x20000000, len = 20k
|
||||
}
|
||||
|
||||
__flash_start__ = 0x08001000;
|
||||
__flash_end__ = 0x08020000;
|
||||
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_size__ = 20k;
|
||||
__ram_end__ = __ram_start__ + __ram_size__;
|
||||
@@ -29,15 +22,17 @@ SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
|
||||
.sys : ALIGN(16) SUBALIGN(16)
|
||||
.sys : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
_sys = .;
|
||||
KEEP(*(.vectors))
|
||||
_sys = .;
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(16);
|
||||
*(.sys.version)
|
||||
KEEP(*(.sys.version))
|
||||
KEEP(*(.sys.board_id))
|
||||
KEEP(*(.sys.board_name))
|
||||
build/sys.o(.text)
|
||||
build/sys.o(.text.*)
|
||||
build/sys.o(.rodata)
|
||||
build/sys.o(.rodata)
|
||||
build/sys.o(.rodata.*)
|
||||
. = ALIGN(1024);
|
||||
/*
|
||||
@@ -45,7 +40,7 @@ SECTIONS
|
||||
*(.sys.1)
|
||||
*(.sys.2)
|
||||
*/
|
||||
} > flash0
|
||||
} > flash0 =0xffffffff
|
||||
|
||||
_text = .;
|
||||
|
||||
@@ -65,6 +60,7 @@ SECTIONS
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
. = ALIGN(8);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
|
||||
@@ -88,7 +84,7 @@ SECTIONS
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__vector_ram_addr__ = .;
|
||||
KEEP(*(.data.startup.*))
|
||||
KEEP(*(.bss.startup.*))
|
||||
} > ram
|
||||
|
||||
.process_stack :
|
||||
@@ -97,15 +93,15 @@ SECTIONS
|
||||
__process3_stack_base__ = .;
|
||||
. += __process3_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack3_end__ = .;
|
||||
__process3_stack_end__ = .;
|
||||
__process2_stack_base__ = .;
|
||||
. += __process2_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack2_end__ = .;
|
||||
__process2_stack_end__ = .;
|
||||
__process1_stack_base__ = .;
|
||||
. += __process1_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process_stack1_end__ = .;
|
||||
__process1_stack_end__ = .;
|
||||
__process0_stack_base__ = .;
|
||||
. += __process0_stack_size__;
|
||||
. = ALIGN(8);
|
||||
|
||||
142
example-led/sample.ld.m3
Normal file
142
example-led/sample.ld.m3
Normal file
@@ -0,0 +1,142 @@
|
||||
/*
|
||||
* ST32F103 memory setup.
|
||||
*/
|
||||
__main_stack_size__ = 0x0100; /* Exception handlers */
|
||||
__process0_stack_size__ = 0x0100; /* Main program */
|
||||
__process1_stack_size__ = 0x0100; /* first thread program */
|
||||
__process2_stack_size__ = 0x0100; /* second thread program */
|
||||
__process3_stack_size__ = 0x0100; /* third thread program */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash0 : org = 0x08000000, len = 4k
|
||||
flash : org = 0x08000000+0x1000, len = 60k
|
||||
ram : org = 0x20000000, len = 20k
|
||||
}
|
||||
|
||||
__ram_start__ = ORIGIN(ram);
|
||||
__ram_size__ = 20k;
|
||||
__ram_end__ = __ram_start__ + __ram_size__;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
|
||||
.sys : ALIGN(4) SUBALIGN(4)
|
||||
{
|
||||
_sys = .;
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(16);
|
||||
KEEP(*(.sys.version))
|
||||
KEEP(*(.sys.board_id))
|
||||
KEEP(*(.sys.board_name))
|
||||
build/sys.o(.text)
|
||||
build/sys.o(.text.*)
|
||||
build/sys.o(.rodata)
|
||||
build/sys.o(.rodata.*)
|
||||
. = ALIGN(1024);
|
||||
*(.sys.0)
|
||||
*(.sys.1)
|
||||
*(.sys.2)
|
||||
} > flash0
|
||||
|
||||
_text = .;
|
||||
|
||||
.startup : ALIGN(128) SUBALIGN(128)
|
||||
{
|
||||
KEEP(*(.startup.vectors))
|
||||
. = ALIGN (16);
|
||||
} > flash =0xffffffff
|
||||
|
||||
.text : ALIGN(16) SUBALIGN(16)
|
||||
{
|
||||
*(.text.startup.*)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.gcc*)
|
||||
. = ALIGN(8);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
|
||||
|
||||
.ARM.exidx : {
|
||||
PROVIDE(__exidx_start = .);
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
PROVIDE(__exidx_end = .);
|
||||
} > flash
|
||||
|
||||
.eh_frame_hdr : {*(.eh_frame_hdr)} > flash
|
||||
|
||||
.eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
|
||||
|
||||
.textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
|
||||
|
||||
_etext = .;
|
||||
_textdata = _etext;
|
||||
|
||||
.process_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__process3_stack_base__ = .;
|
||||
. += __process3_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process3_stack_end__ = .;
|
||||
__process2_stack_base__ = .;
|
||||
. += __process2_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process2_stack_end__ = .;
|
||||
__process1_stack_base__ = .;
|
||||
. += __process1_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process1_stack_end__ = .;
|
||||
__process0_stack_base__ = .;
|
||||
. += __process0_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__process0_stack_end__ = .;
|
||||
} > ram
|
||||
|
||||
.main_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__main_stack_base__ = .;
|
||||
. += __main_stack_size__;
|
||||
. = ALIGN(8);
|
||||
__main_stack_end__ = .;
|
||||
} > ram
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data = .);
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
*(.data.*)
|
||||
. = ALIGN(4);
|
||||
*(.ramtext)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_edata = .);
|
||||
} > ram AT > flash
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_bss_start = .);
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
*(.bss.*)
|
||||
. = ALIGN(4);
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_bss_end = .);
|
||||
} > ram
|
||||
|
||||
PROVIDE(end = .);
|
||||
_end = .;
|
||||
}
|
||||
|
||||
__heap_base__ = _end;
|
||||
__heap_end__ = __ram_end__;
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* sys.c - system routines for the initial page for STM32F030 / STM32F103.
|
||||
*
|
||||
* Copyright (C) 2013, 2014 Flying Stone Technology
|
||||
* Copyright (C) 2013, 2014, 2015 Flying Stone Technology
|
||||
* Author: NIIBE Yutaka <gniibe@fsij.org>
|
||||
*
|
||||
* Copying and distribution of this file, with or without modification,
|
||||
@@ -17,60 +17,13 @@
|
||||
#include <stdlib.h>
|
||||
#include "board.h"
|
||||
|
||||
#include "clk_gpio_init.c"
|
||||
|
||||
#define CORTEX_PRIORITY_BITS 4
|
||||
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
|
||||
#define USB_LP_CAN1_RX0_IRQn 20
|
||||
#define STM32_USB_IRQ_PRIORITY 11
|
||||
|
||||
|
||||
#define STM32_SW_HSI (0 << 0)
|
||||
#define STM32_SW_PLL (2 << 0)
|
||||
#define STM32_PLLSRC_HSI (0 << 16)
|
||||
#define STM32_PLLSRC_HSE (1 << 16)
|
||||
|
||||
#define STM32_PLLXTPRE_DIV1 (0 << 17)
|
||||
#define STM32_PLLXTPRE_DIV2 (1 << 17)
|
||||
|
||||
#define STM32_HPRE_DIV1 (0 << 4)
|
||||
|
||||
#define STM32_PPRE1_DIV1 (0 << 8)
|
||||
#define STM32_PPRE1_DIV2 (4 << 8)
|
||||
|
||||
#define STM32_PPRE2_DIV1 (0 << 11)
|
||||
#define STM32_PPRE2_DIV2 (4 << 11)
|
||||
|
||||
#define STM32_ADCPRE_DIV4 (1 << 14)
|
||||
#define STM32_ADCPRE_DIV6 (2 << 14)
|
||||
|
||||
#define STM32_USBPRE_DIV1P5 (0 << 22)
|
||||
|
||||
#define STM32_MCO_NOCLOCK (0 << 24)
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSI
|
||||
#define STM32_FLASHBITS 0x00000011
|
||||
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
|
||||
#else
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_FLASHBITS 0x00000012
|
||||
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
|
||||
#endif
|
||||
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV6
|
||||
#define STM32_MCOSEL STM32_MCO_NOCLOCK
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
|
||||
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
|
||||
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
||||
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||
|
||||
struct NVIC {
|
||||
uint32_t ISER[8];
|
||||
uint32_t unused1[24];
|
||||
@@ -100,289 +53,6 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
|
||||
NVIC_ISER (n) = 1 << (n & 0x1F);
|
||||
}
|
||||
|
||||
|
||||
#define PERIPH_BASE 0x40000000
|
||||
#define APBPERIPH_BASE PERIPH_BASE
|
||||
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
||||
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
|
||||
|
||||
struct RCC {
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t CFGR;
|
||||
volatile uint32_t CIR;
|
||||
volatile uint32_t APB2RSTR;
|
||||
volatile uint32_t APB1RSTR;
|
||||
volatile uint32_t AHBENR;
|
||||
volatile uint32_t APB2ENR;
|
||||
volatile uint32_t APB1ENR;
|
||||
volatile uint32_t BDCR;
|
||||
volatile uint32_t CSR;
|
||||
#if defined(MCU_STM32F0)
|
||||
volatile uint32_t AHBRSTR;
|
||||
volatile uint32_t CFGR2;
|
||||
volatile uint32_t CFGR3;
|
||||
volatile uint32_t CR2;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
|
||||
static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
|
||||
|
||||
#define RCC_APB1ENR_USBEN 0x00800000
|
||||
#define RCC_APB1RSTR_USBRST 0x00800000
|
||||
|
||||
#define RCC_CR_HSION 0x00000001
|
||||
#define RCC_CR_HSIRDY 0x00000002
|
||||
#define RCC_CR_HSITRIM 0x000000F8
|
||||
#define RCC_CR_HSEON 0x00010000
|
||||
#define RCC_CR_HSERDY 0x00020000
|
||||
#define RCC_CR_PLLON 0x01000000
|
||||
#define RCC_CR_PLLRDY 0x02000000
|
||||
|
||||
#define RCC_CFGR_SWS 0x0000000C
|
||||
#define RCC_CFGR_SWS_HSI 0x00000000
|
||||
|
||||
#define RCC_AHBENR_CRCEN 0x0040
|
||||
|
||||
#if MCU_STM32F0
|
||||
#define RCC_AHBRSTR_IOPARST 0x00020000
|
||||
#define RCC_AHBRSTR_IOPBRST 0x00040000
|
||||
#define RCC_AHBRSTR_IOPCRST 0x00080000
|
||||
#define RCC_AHBRSTR_IOPDRST 0x00100000
|
||||
#define RCC_AHBRSTR_IOPFRST 0x00400000
|
||||
|
||||
#define RCC_AHBENR_IOPAEN 0x00020000
|
||||
#define RCC_AHBENR_IOPBEN 0x00040000
|
||||
#define RCC_AHBENR_IOPCEN 0x00080000
|
||||
#define RCC_AHBENR_IOPDEN 0x00100000
|
||||
#define RCC_AHBENR_IOPFEN 0x00400000
|
||||
|
||||
#define RCC_APB2RSTR_SYSCFGRST 0x00000001
|
||||
#define RCC_APB2ENR_SYSCFGEN 0x00000001
|
||||
#else
|
||||
#define RCC_APB2RSTR_AFIORST 0x00000001
|
||||
#define RCC_APB2RSTR_IOPARST 0x00000004
|
||||
#define RCC_APB2RSTR_IOPBRST 0x00000008
|
||||
#define RCC_APB2RSTR_IOPCRST 0x00000010
|
||||
#define RCC_APB2RSTR_IOPDRST 0x00000020
|
||||
|
||||
#define RCC_APB2ENR_AFIOEN 0x00000001
|
||||
#define RCC_APB2ENR_IOPAEN 0x00000004
|
||||
#define RCC_APB2ENR_IOPBEN 0x00000008
|
||||
#define RCC_APB2ENR_IOPCEN 0x00000010
|
||||
#define RCC_APB2ENR_IOPDEN 0x00000020
|
||||
#endif
|
||||
|
||||
#if MCU_STM32F0
|
||||
struct SYSCFG {
|
||||
volatile uint32_t CFGR1;
|
||||
uint32_t dummy0;
|
||||
volatile uint32_t EXTICR[4];
|
||||
volatile uint32_t CFGR2;
|
||||
};
|
||||
#define SYSCFG_CFGR1_MEM_MODE 0x03
|
||||
|
||||
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
|
||||
static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
|
||||
#endif
|
||||
|
||||
struct FLASH {
|
||||
volatile uint32_t ACR;
|
||||
volatile uint32_t KEYR;
|
||||
volatile uint32_t OPTKEYR;
|
||||
volatile uint32_t SR;
|
||||
volatile uint32_t CR;
|
||||
volatile uint32_t AR;
|
||||
volatile uint32_t RESERVED;
|
||||
volatile uint32_t OBR;
|
||||
volatile uint32_t WRPR;
|
||||
};
|
||||
|
||||
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
|
||||
static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
|
||||
|
||||
static void
|
||||
clock_init (void)
|
||||
{
|
||||
/* HSI setup */
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY))
|
||||
;
|
||||
/* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
|
||||
RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
|
||||
RCC->CFGR = 0;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
|
||||
;
|
||||
|
||||
#if !defined(MCU_STM32F0)
|
||||
/* HSE setup */
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY))
|
||||
;
|
||||
#endif
|
||||
|
||||
/* PLL setup */
|
||||
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
;
|
||||
|
||||
/* Clock settings */
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
|
||||
| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
|
||||
/*
|
||||
* We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
|
||||
*/
|
||||
|
||||
/* Flash setup */
|
||||
FLASH->ACR = STM32_FLASHBITS;
|
||||
|
||||
/* CRC */
|
||||
RCC->AHBENR |= RCC_AHBENR_CRCEN;
|
||||
|
||||
/* Switching on the configured clock source. */
|
||||
RCC->CFGR |= STM32_SW;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
;
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
|
||||
RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
|
||||
RCC->APB2RSTR = 0;
|
||||
|
||||
/* Use vectors on RAM */
|
||||
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if defined(MCU_STM32F0)
|
||||
struct GPIO {
|
||||
volatile uint32_t MODER;
|
||||
volatile uint16_t OTYPER;
|
||||
uint16_t dummy0;
|
||||
volatile uint32_t OSPEEDR;
|
||||
volatile uint32_t PUPDR;
|
||||
volatile uint16_t IDR;
|
||||
uint16_t dummy1;
|
||||
volatile uint16_t ODR;
|
||||
uint16_t dummy2;
|
||||
volatile uint16_t BSRR;
|
||||
uint16_t dummy3;
|
||||
volatile uint32_t LCKR;
|
||||
volatile uint32_t AFR[2];
|
||||
volatile uint16_t BRR;
|
||||
uint16_t dummy4;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOF ((struct GPIO *) GPIOF_BASE)
|
||||
#else
|
||||
struct AFIO
|
||||
{
|
||||
volatile uint32_t EVCR;
|
||||
volatile uint32_t MAPR;
|
||||
volatile uint32_t EXTICR[4];
|
||||
uint32_t RESERVED0;
|
||||
volatile uint32_t MAPR2;
|
||||
};
|
||||
|
||||
#define AFIO_BASE 0x40010000
|
||||
static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
|
||||
|
||||
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
|
||||
#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
|
||||
|
||||
|
||||
struct GPIO {
|
||||
volatile uint32_t CRL;
|
||||
volatile uint32_t CRH;
|
||||
volatile uint32_t IDR;
|
||||
volatile uint32_t ODR;
|
||||
volatile uint32_t BSRR;
|
||||
volatile uint32_t BRR;
|
||||
volatile uint32_t LCKR;
|
||||
};
|
||||
|
||||
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOA ((struct GPIO *) GPIOA_BASE)
|
||||
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOB ((struct GPIO *) GPIOB_BASE)
|
||||
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
||||
#define GPIOC ((struct GPIO *) GPIOC_BASE)
|
||||
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOD ((struct GPIO *) GPIOD_BASE)
|
||||
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
|
||||
#define GPIOE ((struct GPIO *) GPIOE_BASE)
|
||||
#endif
|
||||
|
||||
static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
|
||||
#ifdef GPIO_USB_BASE
|
||||
static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
|
||||
#endif
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
|
||||
#endif
|
||||
|
||||
static void
|
||||
gpio_init (void)
|
||||
{
|
||||
/* Enable GPIO clock. */
|
||||
#if defined(MCU_STM32F0)
|
||||
RCC->AHBENR |= RCC_ENR_IOP_EN;
|
||||
RCC->AHBRSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->AHBRSTR = 0;
|
||||
#else
|
||||
RCC->APB2ENR |= RCC_ENR_IOP_EN;
|
||||
RCC->APB2RSTR = RCC_RSTR_IOP_RST;
|
||||
RCC->APB2RSTR = 0;
|
||||
#endif
|
||||
|
||||
#if MCU_STM32F0
|
||||
GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
|
||||
GPIO_LED->OTYPER = VAL_GPIO_OTYPER;
|
||||
GPIO_LED->MODER = VAL_GPIO_MODER;
|
||||
GPIO_LED->PUPDR = VAL_GPIO_PUPDR;
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
|
||||
GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
|
||||
GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
|
||||
GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
|
||||
#endif
|
||||
#else
|
||||
#ifdef AFIO_MAPR_SOMETHING
|
||||
AFIO->MAPR |= AFIO_MAPR_SOMETHING;
|
||||
#endif
|
||||
|
||||
GPIO_USB->ODR = VAL_GPIO_ODR;
|
||||
GPIO_USB->CRH = VAL_GPIO_CRH;
|
||||
GPIO_USB->CRL = VAL_GPIO_CRL;
|
||||
|
||||
#if GPIO_USB_BASE != GPIO_LED_BASE
|
||||
GPIO_LED->ODR = VAL_GPIO_LED_ODR;
|
||||
GPIO_LED->CRH = VAL_GPIO_LED_CRH;
|
||||
GPIO_LED->CRL = VAL_GPIO_LED_CRL;
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_OTHER_BASE
|
||||
GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
|
||||
GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
|
||||
GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
usb_cable_config (int enable)
|
||||
{
|
||||
@@ -573,16 +243,25 @@ flash_check_blank (const uint8_t *p_start, size_t size)
|
||||
return 1;
|
||||
}
|
||||
|
||||
extern uint8_t __flash_start__, __flash_end__;
|
||||
#define FLASH_START_ADDR 0x08000000 /* Fixed for all STM32F0/F1. */
|
||||
#define FLASH_OFFSET 0x1000 /* First pages are not-writable
|
||||
when protected. */
|
||||
#if defined(__ARM_ARCH_6M__)
|
||||
#define FLASH_SIZE_REG ((uint16_t *)0x1ffff7cc)
|
||||
#define CHIP_ID_REG ((uint32_t *)0x40015800)
|
||||
#else
|
||||
#define FLASH_SIZE_REG ((uint16_t *)0x1ffff7e0)
|
||||
#define CHIP_ID_REG ((uint32_t *)0xe0042000)
|
||||
#endif
|
||||
#define FLASH_START (FLASH_START_ADDR+FLASH_OFFSET)
|
||||
|
||||
static int
|
||||
flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
|
||||
{
|
||||
int status;
|
||||
uint32_t flash_start = (uint32_t)&__flash_start__;
|
||||
uint32_t flash_end = (uint32_t)&__flash_end__;
|
||||
uint32_t flash_end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
|
||||
|
||||
if (dst_addr < flash_start || dst_addr + len > flash_end)
|
||||
if (dst_addr < FLASH_START || dst_addr + len > flash_end)
|
||||
return 0;
|
||||
|
||||
while (len)
|
||||
@@ -635,17 +314,21 @@ flash_protect (void)
|
||||
static void __attribute__((naked))
|
||||
flash_erase_all_and_exec (void (*entry)(void))
|
||||
{
|
||||
uint32_t addr = (uint32_t)&__flash_start__;
|
||||
uint32_t end = (uint32_t)&__flash_end__;
|
||||
uint32_t addr = FLASH_START;
|
||||
uint32_t end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
|
||||
uint32_t page_size = 1024;
|
||||
int r;
|
||||
|
||||
if (((*CHIP_ID_REG) & 0xfff) == 0x0414)
|
||||
page_size = 2048;
|
||||
|
||||
while (addr < end)
|
||||
{
|
||||
r = flash_erase_page (addr);
|
||||
if (r != 0)
|
||||
break;
|
||||
|
||||
addr += FLASH_PAGE_SIZE;
|
||||
addr += page_size;
|
||||
}
|
||||
|
||||
if (addr >= end)
|
||||
@@ -693,8 +376,6 @@ nvic_system_reset (void)
|
||||
static void __attribute__ ((naked))
|
||||
reset (void)
|
||||
{
|
||||
extern const unsigned long *FT0, *FT1, *FT2;
|
||||
|
||||
/*
|
||||
* This code may not be at the start of flash ROM, because of DFU.
|
||||
* So, we take the address from PC.
|
||||
@@ -702,8 +383,8 @@ reset (void)
|
||||
#if defined(__ARM_ARCH_6M__)
|
||||
asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
|
||||
"ldr r0, 1f\n\t" /* r0 = RAM start */
|
||||
"mov r1, pc\n\t" /* r1 = (PC + 0x0400) & ~0x03ff */
|
||||
"mov r2, #0x04\n\t"
|
||||
"mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */
|
||||
"mov r2, #0x10\n\t"
|
||||
"lsl r2, #8\n\t"
|
||||
"add r1, r1, r2\n\t"
|
||||
"sub r2, r2, #1\n\t"
|
||||
@@ -721,6 +402,7 @@ reset (void)
|
||||
"1: .word 0x20000000"
|
||||
: /* no output */ : /* no input */ : "memory");
|
||||
#else
|
||||
extern const unsigned long *FT0, *FT1, *FT2;
|
||||
asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
|
||||
"ldr r0, 1f\n\t" /* r0 = SCR */
|
||||
"mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */
|
||||
@@ -736,12 +418,11 @@ reset (void)
|
||||
".align 2\n"
|
||||
"1: .word 0xe000ed00"
|
||||
: /* no output */ : /* no input */ : "memory");
|
||||
#endif
|
||||
|
||||
/* Never reach here. */
|
||||
/* Artificial entry to refer FT0, FT1, and FT2. */
|
||||
asm volatile (""
|
||||
: : "r" (FT0), "r" (FT1), "r" (FT2));
|
||||
#endif
|
||||
/* Never reach here. */
|
||||
}
|
||||
|
||||
typedef void (*handler)(void);
|
||||
@@ -768,7 +449,13 @@ handler vector[] __attribute__ ((section(".vectors"))) = {
|
||||
|
||||
const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
|
||||
3*2+2, /* bLength */
|
||||
0x03, /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
|
||||
/* sys version: "2.0" */
|
||||
'2', 0, '.', 0, '0', 0,
|
||||
0x03, /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
|
||||
/* sys version: "2.1" */
|
||||
'2', 0, '.', 0, '1', 0,
|
||||
};
|
||||
|
||||
const uint32_t __attribute__((section(".sys.board_id")))
|
||||
sys_board_id = BOARD_ID;
|
||||
|
||||
const uint8_t __attribute__((section(".sys.board_name")))
|
||||
sys_board_name[] = BOARD_NAME;
|
||||
|
||||
@@ -1,4 +1,23 @@
|
||||
#if defined(__ARM_ARCH_6M__)
|
||||
#define BOARD_ID_STM32F0_DISCOVERY 0xde4b4bc1
|
||||
#define BOARD_ID_FSM_55 0x83433c76
|
||||
#else
|
||||
#define BOARD_ID_CQ_STARM 0xc5480875
|
||||
#define BOARD_ID_FST_01_00 0x613870a9
|
||||
#define BOARD_ID_FST_01 0x696886af
|
||||
#define BOARD_ID_MAPLE_MINI 0x7a445272
|
||||
#define BOARD_ID_OLIMEX_STM32_H103 0xf92bb594
|
||||
#define BOARD_ID_STBEE_MINI 0x1f341961
|
||||
#define BOARD_ID_STBEE 0x945c37e8
|
||||
#define BOARD_ID_STM32_PRIMER2 0x21e5798d
|
||||
#define BOARD_ID_STM8S_DISCOVERY 0x2f0976bb
|
||||
#define BOARD_ID_ST_DONGLE 0x2cd4e471
|
||||
#define BOARD_ID_ST_NUCLEO_F103 0x9b87c16d
|
||||
#endif
|
||||
|
||||
extern const uint8_t sys_version[8];
|
||||
extern const uint32_t sys_board_id;
|
||||
extern const uint8_t sys_board_name[];
|
||||
|
||||
typedef void (*handler)(void);
|
||||
extern handler vector[16];
|
||||
|
||||
Reference in New Issue
Block a user