Version 0.07

Update example CDC
Update example for FSM-55
2015-07-15 12:09:07 +09:00 · 2015-07-15 12:04:45 +09:00 · 2015-07-15 12:03:49 +09:00 · 2015-07-15 12:01:53 +09:00 · 2015-07-15 11:48:36 +09:00 · 2015-07-15 09:51:24 +09:00
36 changed files with 1021 additions and 1968 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,3 @@
-*/board.h
 */build
 */.dep
 doc/chopstx.info
--- a/22
+++ b/22
@@ -0,0 +1,22 @@
+Aidan Thornton:
+    Added Maple Mini support.
+	board/board-maple-mini.h
+
+Kaz Kojima:
+    Added STM32 Primer2 support.
+	board/board-stm32-primer2.h
+
+NIIBE Yutaka:
+    Write the library:
+	chopstx.c, eventflag.c, entry.c, clk_gpio_init.c
+        chopstx.h, eventflag.h
+    Draw the logo:
+	chopstx.svg, chopstx.png
+    Write examples:
+        example-led, example-cdc, example-fsm-55
+    Write board:
+        board-fst-01.h, board-fst-01-00.h,
+	board-olimex-stm32-h103.h, board-stm8s-discovery.h
+	board-cq-starm.h, board-stbee-mini.h, board-stbee.h,
+
+	board-stm32f0-discovery.h, board-fsm-55.h
--- a/58
+++ b/58
@@ -1,7 +1,65 @@
+2015-07-15  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.07.
+	* doc/chopstx.texi (VERSION): 0.07.
+
+2015-07-14  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-*.h (BOARD_ID): New.
+	* example-cdc/sys.c (sys_board_id): New.
+	* example-cdc/sample.ld (.sys.board_id): New.
+	(__flash_start__, __flash_end__): Remove.
+	* entry.c [HAVE_SYS_H] (vector_table): By undefining STM32F10X_MD,
+	prepare for high density device even compiled for MD device.
+
+2015-07-13  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* board/board-stm32-primer2.h: Update.
+	* entry.c (vector_table): Less or more.
+
+2015-07-13  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-*.h (BOARD_NAME): New.
+	(STM32F10X_MD): Define for medium-density devices.
+	* example-led/sys.c, sample.ld: Update.
+	* example-fsm-55/sys.c, hacker-emblem.ld: Update.
+	* example-cdc/sys.c (sys_board_name): New.
+	* example-cdc/sample.ld: Update.
+
+2015-07-08  Niibe Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 0.06.
+	* doc/chopstx.texi (VERSION): 0.06.
+
+2015-07-07  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-fsm-55/sys.c: Include clk_gpio_init.c.
+	* board/board-stm32f0-discovery.h, board/board-fsm-55.h: Update.
+	* clk_gpio_init.c (gpio_init): Use VAL_GPIO_LED_*.
+
+2015-06-29  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-cq-starm.h: New for CQ STARM.
+
+	* clk_gpio_init.c (gpio_init): LED is mandatory, but USB enabler
+	is optional.
+	* board/*.h: Update.
+
+2015-06-22  Niibe Yutaka  <gniibe@fsij.org>
+
+	* clk_gpio_init.c: New, adding ports E/F/G.
+	* entry.c: Include clk_gpio.init.c if not HAVE_SYS_H.
+	* example-led/sys.c: Include clk_gpio_init.c.
+	* example-cdc/sys.c: Ditto.
+
+	* board/board-stm32-primer2.h: New from Kaz Kojima.
+
 2015-04-20  Niibe Yutaka  <gniibe@fsij.org>

 	Merge cortex-m0-support branch.

+	* VERSION: 0.05.
+
 	* example-led/sys.c (gpio_init): Support MCU_STM32F0.
 	(reset): Support __ARM_ARCH_6M__.
 	* example-led/sample.ld: Change for Cortex-M0.
--- a/29
+++ b/29
@@ -1,5 +1,34 @@
 NEWS - Noteworthy changes

+
+* Major changes in Chopstx 0.07
+
+  Released 2015-07-15
+
+** New Board macro definitions
+Each board-*.h should have BOARD_ID and BOARD_NAME now.
+FLASH_PAGE_SIZE and NEUG_ADC_SETTING2_* are deprecated.
+
+** New sys.c (2.1)
+Flash memory size is probed at runtime now.  System
+service flash pages now include sys_board_id and sys_board_name.
+
+
+* Major changes in Chopstx 0.06
+
+  Released 2015-07-08
+
+** New file: clk_gpio_init.c
+To avoid duplication of code, clock and GPIO initialization code
+is now in this file.
+
+** New board support: STM32 Primer2
+It is contributed by Kaz Kojima.
+
+** New board support: CQ STARM
+The old board which was "published" by CQ Publishing in 2008 is added.
+
+
 * Major changes in Chopstx 0.05

  Released 2015-04-20, by NIIBE Yutaka
--- a/7
+++ b/7
@@ -1,6 +1,6 @@
 Chopstx - Threads and only Threads
-							Version 0.05
-							  2015-04-20
+							Version 0.07
+							  2015-07-15
 							Niibe Yutaka
 					     Flying Stone Technology

@@ -35,6 +35,9 @@ USB CDC-ACM function.  You can build it like:
   $ ln -s ../board/board-olimex-stm32-h103.h board.h
   $ make

+For a specific board named FSM-55, an example of LED matrix dynamic
+driver is provided.  See the directory: example-fsm-55.
+

 Future Works
 ============
--- a/2
+++ b/2
@@ -1 +1 @@
-release/0.05
+release/0.07
--- a/board/board-cq-starm.h
+++ b/board/board-cq-starm.h
@@ -0,0 +1,48 @@
+#define BOARD_NAME "CQ STARM"
+#define BOARD_ID    0xc5480875
+
+#define FLASH_PAGE_SIZE 1024
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOC_BASE
+#define GPIO_LED_SET_TO_EMIT            6
+#undef  GPIO_USB_BASE
+#undef  GPIO_USB_CLEAR_TO_ENABLE
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up.  AN0
+ * PA1  - input with pull-up.  AN1
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ */
+#define VAL_GPIO_OTHER_ODR            0xFFFFE7FF
+#define VAL_GPIO_OTHER_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_OTHER_CRH            0x88811888      /* PA15...PA8 */
+
+/*
+ * Port C setup.
+ * PC0  - Push Pull output 50MHz.
+ * PC1  - Push Pull output 50MHz.
+ * Everything input with pull-up except:
+ * PC4  - Normal input      (ADC_IN14 : VoutY of LIS344ALH).
+ * PC5  - Normal input      (ADC_IN15 : VoutZ of LIS344ALH).
+ * PC6  - Push Pull output (LED).
+ * (PC9  - SDCard CD)
+ * (PC12 - SDCard CS)
+ * PC14 - Normal input (XTAL).
+ * PC15 - Normal input (XTAL).
+ */
+#define VAL_GPIO_LED_CRL            0x83448833      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x44888888      /* PC15...PC8 */
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPCEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPCRST)
--- a/board/board-fsm-55.h
+++ b/board/board-fsm-55.h
@@ -1,3 +1,6 @@
+#define BOARD_NAME "FSM-55"
+#define BOARD_ID    0x83433c76
+
 /*
 * Running at 48MHz with HSI as clock source.
 * 
@@ -12,26 +15,26 @@
 #define STM32_PLLMUL_VALUE              12
 #define STM32_HSICLK                    8000000

+#define GPIO_LED_BASE           GPIOA_BASE
 #define GPIO_LED_SET_TO_EMIT    5
+#define GPIO_OTHER_BASE         GPIOF_BASE /* USER BUTTON */

 /*
 * Port A setup.
 * PA5  - ON (LED 1:ON 0:OFF)
 * PA4  - Pull DOWN
 */
-#define VAL_GPIO_MODER   0x00145555 /* Output Pin0-7, Pin9 and Pin10 */
-#define VAL_GPIO_OTYPER  0x0000001f /* Open-drain for Pin0-4, Push-Pull*/
-#define VAL_GPIO_OSPEEDR 0x003cffff /* High speed */
-#define VAL_GPIO_PUPDR   0x00000000 /* No pull-up/pull-down */
+#define VAL_GPIO_LED_MODER   0x00145555 /* Output Pin0-7, Pin9 and Pin10 */
+#define VAL_GPIO_LED_OTYPER  0x0000001f /* Open-drain for Pin0-4, Push-Pull*/
+#define VAL_GPIO_LED_OSPEEDR 0x003cffff /* High speed */
+#define VAL_GPIO_LED_PUPDR   0x00000000 /* No pull-up/pull-down */

-#define GPIO_LED_BASE   GPIOA_BASE

 #define RCC_ENR_IOP_EN   (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPFEN)
 #define RCC_RSTR_IOP_RST (RCC_AHBRSTR_IOPARST | RCC_AHBRSTR_IOPFRST)

 /* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */

-#define GPIO_OTHER_BASE GPIOF_BASE /* USER BUTTON */
 /*
 * Port F setup.
 * PF0  - USER Button
--- a/board/board-fst-01-00.h
+++ b/board/board-fst-01-00.h
@@ -1,11 +1,18 @@
+#define BOARD_NAME "FST-01-00"
+#define BOARD_ID    0x613870a9
+
 #define FLASH_PAGE_SIZE 1024
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              9
 #define STM32_HSECLK                    8000000

-#define GPIO_USB_SET_TO_ENABLE          10
+#define GPIO_LED_BASE   GPIOA_BASE
 #define GPIO_LED_SET_TO_EMIT            8
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          10
+#undef  GPIO_OTHER_BASE

 /*
 * Port A setup.
@@ -18,14 +25,9 @@
 * ------------------------ Default
 * PAx  - input with pull-up
 */
-#define VAL_GPIO_ODR            0xFFFFE7FF
-#define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
-#define VAL_GPIO_CRH            0x88811383      /* PA15...PA8 */
-
-#define GPIO_USB_BASE   GPIOA_BASE
-#define GPIO_LED_BASE   GPIOA_BASE
+#define VAL_GPIO_LED_ODR            0xFFFFE7FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88811383      /* PA15...PA8 */

 #define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
 #define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
-
-/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */
--- a/board/board-fst-01.h
+++ b/board/board-fst-01.h
@@ -1,11 +1,19 @@
+#define BOARD_NAME "FST-01"
+#define BOARD_ID    0x696886af
+/* echo -n "FST-01" | sha256sum | sed -e 's/^.*\(........\)  -$/\1/' */
+
 #define FLASH_PAGE_SIZE 1024
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              6
 #define STM32_HSECLK                    12000000

-#define GPIO_USB_SET_TO_ENABLE          10
+#define GPIO_LED_BASE   GPIOB_BASE
 #define GPIO_LED_SET_TO_EMIT            0
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          10
+#undef  GPIO_OTHER_BASE

 /* For pin-cir settings of Gnuk */
 #define TIMx                  TIM2
@@ -40,9 +48,9 @@
 * PA14 - input with pull-up.
 * PA15 - input with pull-up.
 */
-#define VAL_GPIO_ODR            0xFFFFE7FD
-#define VAL_GPIO_CRL            0xBBB38888      /*  PA7...PA0 */
-#define VAL_GPIO_CRH            0x88811388      /* PA15...PA8 */
+#define VAL_GPIO_USB_ODR            0xFFFFE7FD
+#define VAL_GPIO_USB_CRL            0xBBB38888      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x88811388      /* PA15...PA8 */

 /*
 * Port B setup.
@@ -55,16 +63,5 @@
 #define VAL_GPIO_LED_CRL            0x88888883      /*  PA7...PA0 */
 #define VAL_GPIO_LED_CRH            0x88888888      /* PA15...PA8 */

-#define GPIO_USB_BASE   GPIOA_BASE
-#define GPIO_LED_BASE   GPIOB_BASE
-
 #define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
 #define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
-
-/* NeuG settings for ADC2.  */
-#define NEUG_ADC_SETTING2_SMPR1 0
-#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)    \
-                              | ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5)
-#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)      \
-                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9)
-#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
--- a/board/board-maple-mini.h
+++ b/board/board-maple-mini.h
@@ -1,11 +1,31 @@
+#define BOARD_NAME "Maple Mini"
+#define BOARD_ID    0x7a445272
+
 #define FLASH_PAGE_SIZE 1024
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              9
 #define STM32_HSECLK                    8000000

-#define GPIO_USB_CLEAR_TO_ENABLE        9
+#define GPIO_LED_BASE   GPIOB_BASE
 #define GPIO_LED_SET_TO_EMIT            1
+#define GPIO_USB_BASE   GPIOB_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE        9
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up.  AN0
+ * PA1  - input with pull-up.  AN1
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ */
+#define VAL_GPIO_OTHER_ODR            0xFFFFE7FF
+#define VAL_GPIO_OTHER_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_OTHER_CRH            0x88811888      /* PA15...PA8 */

 /*
 * Port B setup.
@@ -14,14 +34,9 @@
 * ------------------------ Default
 * PBx  - input with pull-up
 */
-#define VAL_GPIO_ODR            0xFFFFFFFF
-#define VAL_GPIO_CRL            0x88888838      /*  PB7...PB0 */
-#define VAL_GPIO_CRH            0x88888838      /* PB15...PB8 */
-
-#define GPIO_USB_BASE   GPIOB_BASE
-#define GPIO_LED_BASE   GPIOB_BASE
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888838      /*  PB7...PB0 */
+#define VAL_GPIO_LED_CRH            0x88888838      /* PB15...PB8 */

 #define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
 #define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
-
-/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */
--- a/board/board-olimex-stm32-h103.h
+++ b/board/board-olimex-stm32-h103.h
@@ -1,11 +1,18 @@
+#define BOARD_NAME "Olimex STM32-H103"
+#define BOARD_ID    0xf92bb594
+
 #define FLASH_PAGE_SIZE 1024
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              9
 #define STM32_HSECLK                    8000000

-#define GPIO_USB_CLEAR_TO_ENABLE        11
+#define GPIO_LED_BASE   GPIOC_BASE
 #define GPIO_LED_CLEAR_TO_EMIT          12
+#define GPIO_USB_BASE   GPIOC_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE        11
+#undef  GPIO_OTHER_BASE

 /*
 * Port C setup.
@@ -18,12 +25,9 @@
 * ------------------------ Default
 * PCx  - input with pull-up
 */
-#define VAL_GPIO_ODR            0xFFFFFFFF
-#define VAL_GPIO_CRL            0x44888888      /*  PC7...PC0 */
-#define VAL_GPIO_CRH            0x88837888      /* PC15...PC8 */
-
-#define GPIO_USB_BASE   GPIOC_BASE
-#define GPIO_LED_BASE   GPIOC_BASE
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x44888888      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x88837888      /* PC15...PC8 */

 #define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPCEN
 #define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPCRST
--- a/board/board-stbee-mini.h
+++ b/board/board-stbee-mini.h
@@ -1,11 +1,17 @@
+#define BOARD_NAME "STBee Mini"
+#define BOARD_ID    0x1f341961
+
 #define FLASH_PAGE_SIZE 1024
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              6
 #define STM32_HSECLK                    12000000

-#define GPIO_USB_SET_TO_ENABLE          14
+#define GPIO_LED_BASE           GPIOA_BASE
 #define GPIO_LED_CLEAR_TO_EMIT          13
+#define GPIO_USB_BASE           GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          14

 #if defined(PINPAD_CIR_SUPPORT) || defined(PINPAD_DIAL_SUPPORT)
 #define HAVE_7SEGLED	1
@@ -49,19 +55,20 @@
 * PA14 - Push pull output  (USB ENABLE 0:DISABLE 1:ENABLE)
 * PA15 - Open Drain output (LED2 0:ON 1:OFF)
 */
-#define VAL_GPIO_ODR            0xFFFFE77F
-#define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
-#define VAL_GPIO_CRH            0x63611888      /* PA15...PA8 */
+#define VAL_GPIO_LED_ODR            0xFFFFE77F
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x63611888      /* PA15...PA8 */

+#define GPIO_OTHER_BASE          GPIOB_BASE
 /*
 * Port B setup.
 * PB0  - Push pull output   (LED 1:ON 0:OFF)
 * ------------------------ Default
 * PBx  - input with pull-up.
 */
-#define VAL_GPIO_LED_ODR            0xFFFFFFFF
-#define VAL_GPIO_LED_CRL            0x88888888      /*  PB7...PB0 */
-#define VAL_GPIO_LED_CRH            0x66666666      /* PB15...PB8 */
+#define VAL_GPIO_OTHER_ODR            0xFFFFFFFF
+#define VAL_GPIO_OTHER_CRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIO_OTHER_CRH            0x66666666      /* PB15...PB8 */

 /* Port B setup. */
 #define GPIOB_CIR               0
@@ -93,23 +100,15 @@
 * PA14 - Push pull output  (USB ENABLE 0:DISABLE 1:ENABLE)
 * PA15 - Open Drain output (LED2 0:ON 1:OFF)
 */
-#define VAL_GPIO_ODR            0xFFFFE7FF
-#define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
-#define VAL_GPIO_CRH            0x63611888      /* PA15...PA8 */
+#define VAL_GPIO_LED_ODR            0xFFFFE7FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x63611888      /* PA15...PA8 */
+
+#undef  GPIO_OTHER_BASE

 #define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN)
 #define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_AFIORST)
 #endif


-#define GPIO_USB_BASE           GPIOA_BASE
-#define GPIO_LED_BASE           GPIOA_BASE
 #define AFIO_MAPR_SOMETHING     AFIO_MAPR_SWJ_CFG_DISABLE
-
-/* NeuG settings for ADC2.  */
-#define NEUG_ADC_SETTING2_SMPR1 0
-#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5)    \
-                              | ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5)
-#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1)      \
-                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2)
-#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
--- a/board/board-stbee.h
+++ b/board/board-stbee.h
@@ -1,11 +1,17 @@
+#define BOARD_NAME "STBee"
+#define BOARD_ID    0x945c37e8
+
 #define FLASH_PAGE_SIZE 2048

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              6
 #define STM32_HSECLK                    12000000

-#define GPIO_USB_CLEAR_TO_ENABLE        3
+#define GPIO_LED_BASE   GPIOD_BASE
 #define GPIO_LED_CLEAR_TO_EMIT          4
+#define GPIO_USB_BASE   GPIOD_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE        3
+#define GPIO_OTHER_BASE GPIOA_BASE

 /*
 * Port A setup.
@@ -25,18 +31,6 @@
 * PD3  - Push pull output  (USB_DISC 1:USB-DISABLE 0:USB-ENABLE) 2MHz
 * PD4  - Open Drain output 2MHz (LED1).
 */
-#define VAL_GPIO_ODR            0xFFFFFFFF
-#define VAL_GPIO_CRL            0x88862888      /*  PD7...PD0 */
-#define VAL_GPIO_CRH            0x88888888      /* PD15...PD8 */
-
-#define GPIO_USB_BASE   GPIOD_BASE
-#define GPIO_LED_BASE   GPIOD_BASE
-#define GPIO_OTHER_BASE GPIOA_BASE
-
-/* NeuG settings for ADC2.  */
-#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \
-                              | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5)
-#define NEUG_ADC_SETTING2_SMPR2 0
-#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)   \
-                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11)
-#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88862888      /*  PD7...PD0 */
+#define VAL_GPIO_LED_CRH            0x88888888      /* PD15...PD8 */
--- a/board/board-stm32-primer2.h
+++ b/board/board-stm32-primer2.h
@@ -0,0 +1,58 @@
+#define BOARD_NAME "STM32 Primer2"
+#define BOARD_ID    0x21e5798d
+
+#define FLASH_PAGE_SIZE 2048
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
+
+#define GPIO_LED_BASE   GPIOE_BASE
+#define GPIO_LED_SET_TO_EMIT            0
+#define GPIO_USB_BASE   GPIOD_BASE
+#define GPIO_USB_CLEAR_TO_ENABLE        3
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/*
+ * Port A setup.
+ * PA0  - input with pull-up.  AN0
+ * PA1  - input with pull-up.  AN1
+ * PA8  - Input with pull-down (PBUTTON).
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) 
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ */
+#define VAL_GPIO_OTHER_ODR            0xFFFFE6FF
+#define VAL_GPIO_OTHER_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_OTHER_CRH            0x88811888      /* PA15...PA8 */
+
+/*
+ * Port D setup.
+ * PD3  - Push pull output 50MHz (USB 1:ON 0:OFF)
+ * ------------------------ Default
+ * PDx  - input with pull-up
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFFFFF
+#define VAL_GPIO_USB_CRL            0x88883888      /*  PD7...PD0 */
+#define VAL_GPIO_USB_CRH            0x88888888      /* PD15...PD8 */
+
+/*
+ * Port E setup.
+ * PE0  - Push pull output   (LED 1:ON 0:OFF)
+ * PE1  - Push pull output   (LED 1:ON 0:OFF)
+ * PE3  - Input with pull-down (JOYSTICK L).
+ * PE4  - Input with pull-down (JOYSTICK R).
+ * PE5  - Input with pull-down (JOYSTICK U).
+ * PE6  - Input with pull-down (JOYSTICK D).
+ * ------------------------ Default
+ * PEx  - input with pull-up
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFFF87
+#define VAL_GPIO_LED_CRL            0x88888833      /*  PE7...PE0 */
+#define VAL_GPIO_LED_CRH            0x88888888      /* PE15...PE8 */
+
+#define RCC_ENR_IOP_EN \
+	(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_IOPEEN)
+#define RCC_RSTR_IOP_RST \
+	(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPDRST | RCC_APB2RSTR_IOPERST)
--- a/board/board-stm32f0-discovery.h
+++ b/board/board-stm32f0-discovery.h
@@ -1,3 +1,6 @@
+#define BOARD_NAME "STM32F0 Discovery"
+#define BOARD_ID    0xde4b4bc1
+
 /*
 * Running at 48MHz with HSI as clock source.
 * 
@@ -12,19 +15,20 @@
 #define STM32_PLLMUL_VALUE              12
 #define STM32_HSICLK                    8000000

+#define GPIO_LED_BASE           GPIOC_BASE
 #define GPIO_LED_SET_TO_EMIT    8
+#define GPIO_OTHER_BASE         GPIOA_BASE /* USER BUTTON */

 /*
 * Port C setup.
 * PC9  - LED3 (LED 1:ON 0:OFF)
 * PC8  - LED4 (LED 1:ON 0:OFF)
 */
-#define VAL_GPIO_MODER   0x00050000 /* Output Pin9 and Pin8 */
-#define VAL_GPIO_OTYPER  0x00000000 /* Push-Pull */
-#define VAL_GPIO_OSPEEDR 0x000f0000 /* High speed: Pin9 and Pin8 */
-#define VAL_GPIO_PUPDR   0x00000000 /* No pull-up/pull-down */
+#define VAL_GPIO_LED_MODER   0x00050000 /* Output Pin9 and Pin8 */
+#define VAL_GPIO_LED_OTYPER  0x00000000 /* Push-Pull */
+#define VAL_GPIO_LED_OSPEEDR 0x000f0000 /* High speed: Pin9 and Pin8 */
+#define VAL_GPIO_LED_PUPDR   0x00000000 /* No pull-up/pull-down */

-#define GPIO_LED_BASE   GPIOC_BASE

 #if 0
 #define RCC_ENR_IOP_EN   (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPCEN)
@@ -36,7 +40,6 @@

 /* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */

-#define GPIO_OTHER_BASE GPIOA_BASE /* USER BUTTON */
 /*
 * Port A setup.
 * PA0  - USER Button
--- a/board/board-stm8s-discovery.h
+++ b/board/board-stm8s-discovery.h
@@ -1,11 +1,18 @@
+#define BOARD_NAME "STM8S Discovery"
+#define BOARD_ID    0x2f0976bb
+
 #define FLASH_PAGE_SIZE 1024
+#define STM32F10X_MD		/* Medium-density device */

 #define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
 #define STM32_PLLMUL_VALUE              9
 #define STM32_HSECLK                    8000000

-#undef  GPIO_USB_CLEAR_TO_ENABLE
+#define GPIO_LED_BASE   GPIOA_BASE
 #define GPIO_LED_SET_TO_EMIT            8
+#undef  GPIO_USB_BASE
+#undef  GPIO_USB_CLEAR_TO_ENABLE
+#define GPIO_OTHER_BASE GPIOB_BASE

 /* For pin-cir settings of Gnuk */
 #define TIMx                  TIM3
@@ -32,21 +39,15 @@
 * ------------------------ Default
 * PAx  - input with pull-up
 */
-#define VAL_GPIO_ODR            0xFFFFE7FF
-#define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
-#define VAL_GPIO_CRH            0x88811881      /* PA15...PA8 */
-
-#define GPIO_USB_BASE   GPIOA_BASE
-#define GPIO_LED_BASE   GPIOA_BASE
+#define VAL_GPIO_LED_ODR            0xFFFFE7FF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_LED_CRH            0x88811881      /* PA15...PA8 */

 #define RCC_ENR_IOP_EN   \
  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
 #define RCC_RSTR_IOP_RST \
  (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)

-/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */
-
-#define GPIO_OTHER_BASE GPIOB_BASE
 /*
 * Port B setup.
 * PB4  - (TIM3_CH1) input with pull-up
--- a/clk_gpio_init.c
+++ b/clk_gpio_init.c
@@ -0,0 +1,365 @@
+/*
+ * clk_gpio_init.c - Clock and GPIO initialization.
+ *
+ * Copyright (C) 2015  Flying Stone Technology
+ * Author: NIIBE Yutaka <gniibe@fsij.org>
+ *
+ * This file is a part of Chopstx, a thread library for embedded.
+ *
+ * Chopstx is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chopstx is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As additional permission under GNU GPL version 3 section 7, you may
+ * distribute non-source form of the Program without the copy of the
+ * GNU GPL normally required by section 4, provided you inform the
+ * receipents of GNU GPL by a written offer.
+ *
+ */
+
+#define STM32_SW_HSI		(0 << 0)
+#define STM32_SW_PLL		(2 << 0)
+#define STM32_PLLSRC_HSI	(0 << 16)
+#define STM32_PLLSRC_HSE	(1 << 16)
+
+#define STM32_PLLXTPRE_DIV1	(0 << 17)
+#define STM32_PLLXTPRE_DIV2	(1 << 17)
+
+#define STM32_HPRE_DIV1		(0 << 4)
+
+#define STM32_PPRE1_DIV1	(0 << 8)
+#define STM32_PPRE1_DIV2	(4 << 8)
+
+#define STM32_PPRE2_DIV1        (0 << 11)
+#define STM32_PPRE2_DIV2	(4 << 11)
+
+#define STM32_ADCPRE_DIV4	(1 << 14)
+#define STM32_ADCPRE_DIV6       (2 << 14)
+
+#define STM32_USBPRE_DIV1P5     (0 << 22)
+
+#define STM32_MCO_NOCLOCK	(0 << 24)
+
+#if defined(MCU_STM32F0)
+#define STM32_PPRE1		STM32_PPRE1_DIV1
+#define STM32_PLLSRC		STM32_PLLSRC_HSI
+#define STM32_FLASHBITS		0x00000011
+#define STM32_PLLCLKIN		(STM32_HSICLK / 2)
+#else
+#define STM32_PPRE1		STM32_PPRE1_DIV2
+#define STM32_PLLSRC		STM32_PLLSRC_HSE
+#define STM32_FLASHBITS		0x00000012
+#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
+#endif
+
+#define STM32_SW		STM32_SW_PLL
+#define STM32_HPRE		STM32_HPRE_DIV1
+#define STM32_PPRE2		STM32_PPRE2_DIV1
+#define STM32_ADCPRE		STM32_ADCPRE_DIV6
+#define STM32_MCOSEL		STM32_MCO_NOCLOCK
+#define STM32_USBPRE            STM32_USBPRE_DIV1P5
+
+#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
+#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+#define STM32_SYSCLK		STM32_PLLCLKOUT
+#define STM32_HCLK		(STM32_SYSCLK / 1)
+
+
+#define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
+#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
+
+struct RCC {
+  volatile uint32_t CR;
+  volatile uint32_t CFGR;
+  volatile uint32_t CIR;
+  volatile uint32_t APB2RSTR;
+  volatile uint32_t APB1RSTR;
+  volatile uint32_t AHBENR;
+  volatile uint32_t APB2ENR;
+  volatile uint32_t APB1ENR;
+  volatile uint32_t BDCR;
+  volatile uint32_t CSR;
+#if defined(MCU_STM32F0)
+  volatile uint32_t AHBRSTR;
+  volatile uint32_t CFGR2;
+  volatile uint32_t CFGR3;
+  volatile uint32_t CR2;
+#endif
+};
+
+#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
+static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
+
+#define RCC_APB1ENR_USBEN	0x00800000
+#define RCC_APB1RSTR_USBRST	0x00800000
+
+#define RCC_CR_HSION		0x00000001
+#define RCC_CR_HSIRDY		0x00000002
+#define RCC_CR_HSITRIM		0x000000F8
+#define RCC_CR_HSEON		0x00010000
+#define RCC_CR_HSERDY		0x00020000
+#define RCC_CR_PLLON		0x01000000
+#define RCC_CR_PLLRDY		0x02000000
+
+#define RCC_CFGR_SWS		0x0000000C
+#define RCC_CFGR_SWS_HSI	0x00000000
+
+#define RCC_AHBENR_CRCEN        0x0040
+
+#if defined(MCU_STM32F0)
+#define RCC_AHBRSTR_IOPARST	0x00020000
+#define RCC_AHBRSTR_IOPBRST	0x00040000
+#define RCC_AHBRSTR_IOPCRST	0x00080000
+#define RCC_AHBRSTR_IOPDRST	0x00100000
+#define RCC_AHBRSTR_IOPFRST	0x00400000
+
+#define RCC_AHBENR_IOPAEN	0x00020000
+#define RCC_AHBENR_IOPBEN	0x00040000
+#define RCC_AHBENR_IOPCEN	0x00080000
+#define RCC_AHBENR_IOPDEN	0x00100000
+#define RCC_AHBENR_IOPFEN	0x00400000
+
+#define RCC_APB2RSTR_SYSCFGRST	0x00000001
+#define RCC_APB2ENR_SYSCFGEN	0x00000001
+#else
+#define RCC_APB2RSTR_AFIORST	0x00000001
+#define RCC_APB2RSTR_IOPARST	0x00000004
+#define RCC_APB2RSTR_IOPBRST	0x00000008
+#define RCC_APB2RSTR_IOPCRST	0x00000010
+#define RCC_APB2RSTR_IOPDRST	0x00000020
+#define RCC_APB2RSTR_IOPERST	0x00000040
+#define RCC_APB2RSTR_IOPFRST	0x00000080
+#define RCC_APB2RSTR_IOPGRST	0x00000100
+
+#define RCC_APB2ENR_AFIOEN	0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+#define RCC_APB2ENR_IOPEEN	0x00000040
+#define RCC_APB2ENR_IOPFEN	0x00000080
+#define RCC_APB2ENR_IOPGEN	0x00000100
+#endif
+
+#if defined(MCU_STM32F0)
+struct SYSCFG {
+  volatile uint32_t CFGR1;
+  uint32_t dummy0;
+  volatile uint32_t EXTICR[4];
+  volatile uint32_t CFGR2;
+};
+#define SYSCFG_CFGR1_MEM_MODE 0x03
+
+#define SYSCFG_BASE	(APBPERIPH_BASE + 0x00010000)
+static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
+#endif
+
+struct FLASH {
+  volatile uint32_t ACR;
+  volatile uint32_t KEYR;
+  volatile uint32_t OPTKEYR;
+  volatile uint32_t SR;
+  volatile uint32_t CR;
+  volatile uint32_t AR;
+  volatile uint32_t RESERVED;
+  volatile uint32_t OBR;
+  volatile uint32_t WRPR;
+};
+
+#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
+static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
+
+static void __attribute__((used))
+clock_init (void)
+{
+  /* HSI setup */
+  RCC->CR |= RCC_CR_HSION;
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;
+  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
+  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
+  RCC->CFGR = 0;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;
+
+#if !defined(MCU_STM32F0)
+  /* HSE setup */
+  RCC->CR |= RCC_CR_HSEON;
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;
+#endif
+
+  /* PLL setup */
+  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;
+
+  /* Clock settings */
+  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
+    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+  /*
+   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
+   */
+
+  /* Flash setup */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* CRC */
+  RCC->AHBENR |= RCC_AHBENR_CRCEN;
+
+  /* Switching on the configured clock source. */
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;
+
+#if defined(MCU_STM32F0)
+  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+  RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
+  RCC->APB2RSTR = 0;
+  
+  /* Use vectors on RAM */
+  SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
+#endif
+}
+
+
+#if defined(MCU_STM32F0)
+struct GPIO {
+  volatile uint32_t MODER;
+  volatile uint16_t OTYPER;
+  uint16_t dummy0;
+  volatile uint32_t OSPEEDR;
+  volatile uint32_t PUPDR;
+  volatile uint16_t IDR;
+  uint16_t dummy1;
+  volatile uint16_t ODR;
+  uint16_t dummy2;
+  volatile uint16_t BSRR;
+  uint16_t dummy3;
+  volatile uint32_t LCKR;
+  volatile uint32_t AFR[2];
+  volatile uint16_t BRR;
+  uint16_t dummy4;
+};
+
+#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
+#define GPIOF		((struct GPIO *) GPIOF_BASE)
+#else
+struct AFIO
+{
+  volatile uint32_t EVCR;
+  volatile uint32_t MAPR;
+  volatile uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  volatile uint32_t MAPR2;
+};
+
+#define AFIO_BASE 0x40010000
+static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
+
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
+
+
+struct GPIO {
+  volatile uint32_t CRL;
+  volatile uint32_t CRH;
+  volatile uint32_t IDR;
+  volatile uint32_t ODR;
+  volatile uint32_t BSRR;
+  volatile uint32_t BRR;
+  volatile uint32_t LCKR;
+};
+
+#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
+#define GPIOA		((struct GPIO *) GPIOA_BASE)
+#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
+#define GPIOB		((struct GPIO *) GPIOB_BASE)
+#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
+#define GPIOC		((struct GPIO *) GPIOC_BASE)
+#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
+#define GPIOD		((struct GPIO *) GPIOD_BASE)
+#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
+#define GPIOE		((struct GPIO *) GPIOE_BASE)
+#endif
+
+static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
+#ifdef GPIO_USB_BASE
+static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
+#endif
+#ifdef GPIO_OTHER_BASE
+static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
+#endif
+
+static void __attribute__((used))
+gpio_init (void)
+{
+  /* Enable GPIO clock. */
+#if defined(MCU_STM32F0)
+  RCC->AHBENR |= RCC_ENR_IOP_EN;
+  RCC->AHBRSTR = RCC_RSTR_IOP_RST;
+  RCC->AHBRSTR = 0;
+#else
+  RCC->APB2ENR |= RCC_ENR_IOP_EN;
+  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
+  RCC->APB2RSTR = 0;
+#endif
+
+#if defined(MCU_STM32F0)
+  GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
+  GPIO_LED->OTYPER  = VAL_GPIO_LED_OTYPER;
+  GPIO_LED->MODER   = VAL_GPIO_LED_MODER;
+  GPIO_LED->PUPDR   = VAL_GPIO_LED_PUPDR;
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
+  GPIO_OTHER->OTYPER  = VAL_GPIO_OTHER_OTYPER;
+  GPIO_OTHER->MODER   = VAL_GPIO_OTHER_MODER;
+  GPIO_OTHER->PUPDR   = VAL_GPIO_OTHER_PUPDR;
+#endif
+#else
+#ifdef AFIO_MAPR_SOMETHING
+  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
+#endif
+
+  /* LED is mandatory.  If it's on an independent port, we configure it.  */
+  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
+  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
+  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
+
+  /* If there is USB enabler pin and it's independent, we configure it.  */
+#if defined(GPIO_USB_BASE) && GPIO_USB_BASE != GPIO_LED_BASE
+  GPIO_USB->ODR = VAL_GPIO_USB_ODR;
+  GPIO_USB->CRH = VAL_GPIO_USB_CRH;
+  GPIO_USB->CRL = VAL_GPIO_USB_CRL;
+#endif
+
+#ifdef GPIO_OTHER_BASE
+  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
+  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
+  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
+#endif
+#endif
+}
--- a/doc/chopstx-api.texi
+++ b/doc/chopstx-api.texi
@@ -7,6 +7,16 @@ When it detects a coding error, this function will be called to
 stop further execution of code.  It never returns.
@end deftypefun

+@subheading chopstx_main_init
+@anchor{chopstx_main_init}
+@deftypefun {void} {chopstx_main_init} (chopstx_prio_t @var{prio})
+@var{prio}: priority
+
+Initialize main thread with @var{prio}.
+The thread main is created with priority CHX_PRIO_MAIN_INIT,
+and it runs with that priority until this routine will is called.
+@end deftypefun
+
@subheading chopstx_create
@anchor{chopstx_create}
@deftypefun {chopstx_t} {chopstx_create} (uint32_t @var{flags_and_prio}, uint32_t @var{stack_addr}, size_t @var{stack_size}, voidfunc @var{thread_entry}, void * @var{arg})
@@ -28,8 +38,8 @@ Create a thread.
@deftypefun {void} {chopstx_usec_wait_var} (uint32_t * @var{var})
@var{var}: Pointer to usec

-Sleep for micro second specified by @var{var}.
-Another thread can clear @var{var} on condition (to avoid this thread going into sleep).
+Sleep for micro seconds, specified by @var{var}.
+Another thread can clear @var{var} to stop the caller going into sleep.
@end deftypefun

@subheading chopstx_usec_wait
@@ -95,7 +105,7 @@ Wake up a thread waiting on @var{cond}.
@deftypefun {void} {chopstx_cond_broadcast} (chopstx_cond_t * @var{cond})
@var{cond}: Condition Variable

-Wake up all thread winting on @var{cond}.
+Wake up all threads waiting on @var{cond}.
@end deftypefun

@subheading chopstx_claim_irq
@@ -167,7 +177,7 @@ Waits for the thread of @var{thd} to terminate.
@deftypefun {void} {chopstx_wakeup_usec_wait} (chopstx_t @var{thd})
@var{thd}: Thread to be awakened

-Canceling the timer, wakup the sleeping thread for it.
+Canceling the timer, wake up the sleeping thread.
 No return value.
@end deftypefun

@@ -176,7 +186,7 @@ No return value.
@deftypefun {void} {chopstx_cancel} (chopstx_t @var{thd})
@var{thd}: Thread to be canceled

-This function requests a cancellation th the thread @var{thd}.
+This function requests a cancellation of a thread @var{thd}.
 No return value.
@end deftypefun

--- a/doc/chopstx.texi
+++ b/doc/chopstx.texi
@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
@c %**start of header
@setfilename chopstx.info
-@set VERSION 0.04
+@set VERSION 0.07
@settitle Chopstx Reference Manual
@c Unify some of the indices.
@syncodeindex tp fn
--- a/entry.c
+++ b/entry.c
@@ -34,338 +34,10 @@
 #define INLINE __attribute__ ((used))
 #include "sys.h"
 #include "board.h"
+#undef STM32F10X_MD		/* Prepare for high density device, too.  */
 #else
 #include "board.h"
-
-#define STM32_SW_HSI		(0 << 0)
-#define STM32_SW_PLL		(2 << 0)
-#define STM32_PLLSRC_HSI	(0 << 16)
-#define STM32_PLLSRC_HSE	(1 << 16)
-
-#define STM32_PLLXTPRE_DIV1	(0 << 17)
-#define STM32_PLLXTPRE_DIV2	(1 << 17)
-
-#define STM32_HPRE_DIV1		(0 << 4)
-
-#define STM32_PPRE1_DIV1	(0 << 8)
-#define STM32_PPRE1_DIV2	(4 << 8)
-
-#define STM32_PPRE2_DIV1        (0 << 11)
-#define STM32_PPRE2_DIV2	(4 << 11)
-
-#define STM32_ADCPRE_DIV4	(1 << 14)
-#define STM32_ADCPRE_DIV6       (2 << 14)
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)
-
-#define STM32_MCO_NOCLOCK	(0 << 24)
-
-#if defined(MCU_STM32F0)
-#define STM32_PPRE1		STM32_PPRE1_DIV1
-#define STM32_PLLSRC		STM32_PLLSRC_HSI
-#define STM32_FLASHBITS		0x00000011
-#define STM32_PLLCLKIN		(STM32_HSICLK / 2)
-#else
-#define STM32_PPRE1		STM32_PPRE1_DIV2
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_FLASHBITS		0x00000012
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
-#endif
-
-#define STM32_SW		STM32_SW_PLL
-#define STM32_HPRE		STM32_HPRE_DIV1
-#define STM32_PPRE2		STM32_PPRE2_DIV1
-#define STM32_ADCPRE		STM32_ADCPRE_DIV6
-#define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
-
-#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK		STM32_PLLCLKOUT
-#define STM32_HCLK		(STM32_SYSCLK / 1)
-
-
-#define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-#if defined(MCU_STM32F0)
-  volatile uint32_t AHBRSTR;
-  volatile uint32_t CFGR2;
-  volatile uint32_t CFGR3;
-  volatile uint32_t CR2;
-#endif
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN	0x00800000
-#define RCC_APB1RSTR_USBRST	0x00800000
-
-#define RCC_CR_HSION		0x00000001
-#define RCC_CR_HSIRDY		0x00000002
-#define RCC_CR_HSITRIM		0x000000F8
-#define RCC_CR_HSEON		0x00010000
-#define RCC_CR_HSERDY		0x00020000
-#define RCC_CR_PLLON		0x01000000
-#define RCC_CR_PLLRDY		0x02000000
-
-#define RCC_CFGR_SWS		0x0000000C
-#define RCC_CFGR_SWS_HSI	0x00000000
-
-#define RCC_AHBENR_CRCEN        0x0040
-
-#if defined(MCU_STM32F0)
-#define RCC_AHBRSTR_IOPARST	0x00020000
-#define RCC_AHBRSTR_IOPBRST	0x00040000
-#define RCC_AHBRSTR_IOPCRST	0x00080000
-#define RCC_AHBRSTR_IOPDRST	0x00100000
-#define RCC_AHBRSTR_IOPFRST	0x00400000
-
-#define RCC_AHBENR_IOPAEN	0x00020000
-#define RCC_AHBENR_IOPBEN	0x00040000
-#define RCC_AHBENR_IOPCEN	0x00080000
-#define RCC_AHBENR_IOPDEN	0x00100000
-#define RCC_AHBENR_IOPFEN	0x00400000
-
-#define RCC_APB2RSTR_SYSCFGRST	0x00000001
-#define RCC_APB2ENR_SYSCFGEN	0x00000001
-#else
-#define RCC_APB2RSTR_AFIORST	0x00000001
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-#define RCC_APB2ENR_AFIOEN	0x00000001
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-#endif
-
-#if defined(MCU_STM32F0)
-struct SYSCFG {
-  volatile uint32_t CFGR1;
-  uint32_t dummy0;
-  volatile uint32_t EXTICR[4];
-  volatile uint32_t CFGR2;
-};
-#define SYSCFG_CFGR1_MEM_MODE 0x03
-
-#define SYSCFG_BASE	(APBPERIPH_BASE + 0x00010000)
-static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
-#endif
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void __attribute__((used))
-clock_init (void)
-{
-  /* HSI setup */
-  RCC->CR |= RCC_CR_HSION;
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;
-  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
-  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
-  RCC->CFGR = 0;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;
-
-#if !defined(MCU_STM32F0)
-  /* HSE setup */
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;
-#endif
-
-  /* PLL setup */
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-
-  /* Clock settings */
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
-    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /*
-   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
-   */
-
-  /* Flash setup */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* CRC */
-  RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
-  /* Switching on the configured clock source. */
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-
-#if defined(MCU_STM32F0)
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-  RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
-  RCC->APB2RSTR = 0;
-  
-  /* Use vectors on RAM */
-  SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
-#endif
-}
-
-
-#if defined(MCU_STM32F0)
-struct GPIO {
-  volatile uint32_t MODER;
-  volatile uint16_t OTYPER;
-  uint16_t dummy0;
-  volatile uint32_t OSPEEDR;
-  volatile uint32_t PUPDR;
-  volatile uint16_t IDR;
-  uint16_t dummy1;
-  volatile uint16_t ODR;
-  uint16_t dummy2;
-  volatile uint16_t BSRR;
-  uint16_t dummy3;
-  volatile uint32_t LCKR;
-  volatile uint32_t AFR[2];
-  volatile uint16_t BRR;
-  uint16_t dummy4;
-};
-
-#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
-#define GPIOF		((struct GPIO *) GPIOF_BASE)
-#else
-struct AFIO
-{
-  volatile uint32_t EVCR;
-  volatile uint32_t MAPR;
-  volatile uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  volatile uint32_t MAPR2;
-};
-
-#define AFIO_BASE 0x40010000
-static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
-
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
-#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
-
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-#endif
-
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-#ifdef GPIO_USB_BASE
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-#endif
-#ifdef GPIO_OTHER_BASE
-static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
-#endif
-
-static void __attribute__((used))
-gpio_init (void)
-{
-  /* Enable GPIO clock. */
-#if defined(MCU_STM32F0)
-  RCC->AHBENR |= RCC_ENR_IOP_EN;
-  RCC->AHBRSTR = RCC_RSTR_IOP_RST;
-  RCC->AHBRSTR = 0;
-#else
-  RCC->APB2ENR |= RCC_ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
-  RCC->APB2RSTR = 0;
-#endif
-
-#if defined(MCU_STM32F0)
-  GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
-  GPIO_LED->OTYPER  = VAL_GPIO_OTYPER;
-  GPIO_LED->MODER   = VAL_GPIO_MODER;
-  GPIO_LED->PUPDR   = VAL_GPIO_PUPDR;
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
-  GPIO_OTHER->OTYPER  = VAL_GPIO_OTHER_OTYPER;
-  GPIO_OTHER->MODER   = VAL_GPIO_OTHER_MODER;
-  GPIO_OTHER->PUPDR   = VAL_GPIO_OTHER_PUPDR;
-#endif
-#else
-#ifdef AFIO_MAPR_SOMETHING
-  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
-#endif
-
-  GPIO_USB->ODR = VAL_GPIO_ODR;
-  GPIO_USB->CRH = VAL_GPIO_CRH;
-  GPIO_USB->CRL = VAL_GPIO_CRL;
-
-#if GPIO_USB_BASE != GPIO_LED_BASE
-  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
-  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
-  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-#endif
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
-  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
-  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
-#endif
-#endif
-}
+#include "clk_gpio_init.c"
 #endif


@@ -521,12 +193,25 @@ handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
  chx_handle_intr /* DMA1 CH6 */, chx_handle_intr /* DMA1 CH7 */,
  chx_handle_intr /* ADC1_2 */,   chx_handle_intr /* USB HP */,
  /* 0x90 */
-  chx_handle_intr,		/* USB LP */
-  /* ... and more.  CAN, EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
-  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr /* USB LP */,   chx_handle_intr /* CAN */, 
+  /* ... and more.  EXT9_5, TIMx, I2C, SPI, USART, EXT15_10 */
  chx_handle_intr,                chx_handle_intr,
+  /* 0xA0 */
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  /* 0xc0 */
+#if !defined(__ARM_ARCH_6M__)
+  /* STM32F0 doesn't have more.  */
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+#endif
+#if !defined(STM32F10X_MD)
+  /* High-density chips have more; RTCAlarm, USBWakeup, ... , DMA2_Channel4_5 */
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+  chx_handle_intr,  chx_handle_intr,  chx_handle_intr,
+#endif
 };
--- a/example-cdc/board.h
+++ b/example-cdc/board.h
@@ -0,0 +1 @@
+../board/board-fst-01.h
--- a/example-cdc/sample.ld
+++ b/example-cdc/sample.ld
@@ -14,9 +14,6 @@ MEMORY
    ram : org = 0x20000000, len = 20k
 }

-__flash_start__ = 0x08001000;
-__flash_end__   = 0x08020000;
-
 __ram_start__           = ORIGIN(ram);
 __ram_size__            = 20k;
 __ram_end__             = __ram_start__ + __ram_size__;
@@ -25,12 +22,14 @@ SECTIONS
 {
    . = 0;

-    .sys : ALIGN(16) SUBALIGN(16)
+    .sys : ALIGN(4) SUBALIGN(4)
    {
 	_sys = .;
 	KEEP(*(.vectors))
 	. = ALIGN(16);
-	*(.sys.version)
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
 	build/sys.o(.text)
 	build/sys.o(.text.*)
 	build/sys.o(.rodata)
@@ -59,6 +58,7 @@ SECTIONS
        *(.glue_7t)
        *(.glue_7)
        *(.gcc*)
+	. = ALIGN(8);
    } > flash

    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
--- a/example-cdc/sys.c
+++ b/example-cdc/sys.c
@@ -1,7 +1,7 @@
 /*
 * sys.c - system routines for the initial page for STM32F103.
 *
- * Copyright (C) 2013, 2014 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015 Flying Stone Technology
 * Author: NIIBE Yutaka <gniibe@fsij.org>
 *
 * Copying and distribution of this file, with or without modification,
@@ -17,53 +17,13 @@
 #include <stdlib.h>
 #include "board.h"

+#include "clk_gpio_init.c"

 #define CORTEX_PRIORITY_BITS    4
 #define CORTEX_PRIORITY_MASK(n)  ((n) << (8 - CORTEX_PRIORITY_BITS))
 #define USB_LP_CAN1_RX0_IRQn	 20
 #define STM32_USB_IRQ_PRIORITY   11

-
-#define STM32_SW_HSI		(0 << 0)
-#define STM32_SW_PLL		(2 << 0)
-#define STM32_PLLSRC_HSI	(0 << 16)
-#define STM32_PLLSRC_HSE	(1 << 16)
-
-#define STM32_PLLXTPRE_DIV1	(0 << 17)
-#define STM32_PLLXTPRE_DIV2	(1 << 17)
-
-#define STM32_HPRE_DIV1		(0 << 4)
-
-#define STM32_PPRE1_DIV1	(0 << 8)
-#define STM32_PPRE1_DIV2	(4 << 8)
-
-#define STM32_PPRE2_DIV1        (0 << 11)
-#define STM32_PPRE2_DIV2	(4 << 11)
-
-#define STM32_ADCPRE_DIV4	(1 << 14)
-#define STM32_ADCPRE_DIV6       (2 << 14)
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)
-
-#define STM32_MCO_NOCLOCK	(0 << 24)
-
-#define STM32_PPRE1		STM32_PPRE1_DIV2
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_FLASHBITS		0x00000012
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
-
-#define STM32_SW		STM32_SW_PLL
-#define STM32_HPRE		STM32_HPRE_DIV1
-#define STM32_PPRE2		STM32_PPRE2_DIV1
-#define STM32_ADCPRE		STM32_ADCPRE_DIV6
-#define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
-
-#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK		STM32_PLLCLKOUT
-#define STM32_HCLK		(STM32_SYSCLK / 1)
-
 struct NVIC {
  uint32_t ISER[8];
  uint32_t unused1[24];
@@ -93,191 +53,6 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
  NVIC_ISER (n) = 1 << (n & 0x1F);
 }

-
-#define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN	0x00800000
-#define RCC_APB1RSTR_USBRST	0x00800000
-
-#define RCC_CR_HSION		0x00000001
-#define RCC_CR_HSIRDY		0x00000002
-#define RCC_CR_HSITRIM		0x000000F8
-#define RCC_CR_HSEON		0x00010000
-#define RCC_CR_HSERDY		0x00020000
-#define RCC_CR_PLLON		0x01000000
-#define RCC_CR_PLLRDY		0x02000000
-
-#define RCC_CFGR_SWS		0x0000000C
-#define RCC_CFGR_SWS_HSI	0x00000000
-
-#define RCC_AHBENR_CRCEN        0x0040
-
-#define RCC_APB2RSTR_AFIORST	0x00000001
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-#define RCC_APB2ENR_AFIOEN	0x00000001
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void
-clock_init (void)
-{
-  /* HSI setup */
-  RCC->CR |= RCC_CR_HSION;
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;
-  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
-  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
-  RCC->CFGR = 0;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;
-
-  /* HSE setup */
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;
-
-  /* PLL setup */
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-
-  /* Clock settings */
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
-    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /*
-   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
-   */
-
-  /* Flash setup */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* CRC */
-  RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
-  /* Switching on the configured clock source. */
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-}
-
-
-struct AFIO
-{
-  volatile uint32_t EVCR;
-  volatile uint32_t MAPR;
-  volatile uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  volatile uint32_t MAPR2;
-};
-
-#define AFIO_BASE 0x40010000
-static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
-
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
-#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
-
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-#ifdef GPIO_USB_BASE
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-#endif
-#ifdef GPIO_OTHER_BASE
-static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
-#endif
-
-static void
-gpio_init (void)
-{
-  /* Enable GPIO clock. */
-  RCC->APB2ENR |= RCC_ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
-  RCC->APB2RSTR = 0;
-
-#ifdef AFIO_MAPR_SOMETHING
-  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
-#endif
-
-  GPIO_USB->ODR = VAL_GPIO_ODR;
-  GPIO_USB->CRH = VAL_GPIO_CRH;
-  GPIO_USB->CRL = VAL_GPIO_CRL;
-
-#if GPIO_USB_BASE != GPIO_LED_BASE
-  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
-  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
-  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-#endif
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
-  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
-  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
-#endif
-}
-
 static void
 usb_cable_config (int enable)
 {
@@ -468,16 +243,19 @@ flash_check_blank (const uint8_t *p_start, size_t size)
  return 1;
 }

-extern uint8_t __flash_start__, __flash_end__;
+#define FLASH_START_ADDR 0x08000000 /* Fixed for all STM32F1.  */
+#define FLASH_OFFSET     0x1000     /* First pages are not-writable.  */
+#define FLASH_START      (FLASH_START_ADDR+FLASH_OFFSET)
+#define CHIP_ID_REG      ((uint32_t *)0xe0042000)
+#define FLASH_SIZE_REG   ((uint16_t *)0x1ffff7e0)

 static int
 flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
 {
  int status;
-  uint32_t flash_start = (uint32_t)&__flash_start__;
-  uint32_t flash_end = (uint32_t)&__flash_end__;
+  uint32_t flash_end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;

-  if (dst_addr < flash_start || dst_addr + len > flash_end)
+  if (dst_addr < FLASH_START || dst_addr + len > flash_end)
    return 0;

  while (len)
@@ -530,17 +308,21 @@ flash_protect (void)
 static void __attribute__((naked))
 flash_erase_all_and_exec (void (*entry)(void))
 {
-  uint32_t addr = (uint32_t)&__flash_start__;
-  uint32_t end = (uint32_t)&__flash_end__;
+  uint32_t addr = FLASH_START;
+  uint32_t end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
+  uint32_t page_size = 1024;
  int r;

+  if (((*CHIP_ID_REG) & 0xfff) == 0x0414)
+    page_size = 2048;
+
  while (addr < end)
    {
      r = flash_erase_page (addr);
      if (r != 0)
 	break;

-      addr += FLASH_PAGE_SIZE;
+      addr += page_size;
    }

  if (addr >= end)
@@ -640,7 +422,13 @@ handler vector[] __attribute__ ((section(".vectors"))) = {

 const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
  3*2+2,	     /* bLength */
-  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
-  /* sys version: "2.0" */
-  '2', 0, '.', 0, '0', 0,
+  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
+  /* sys version: "2.1" */
+  '2', 0, '.', 0, '1', 0,
 };
+
+const uint32_t __attribute__((section(".sys.board_id")))
+sys_board_id = BOARD_ID;
+
+const uint8_t __attribute__((section(".sys.board_name")))
+sys_board_name[] = BOARD_NAME;
--- a/example-cdc/sys.h
+++ b/example-cdc/sys.h
@@ -1,4 +1,16 @@
+#define BOARD_ID_CQ_STARM          0xc5480875
+#define BOARD_ID_FST_01_00         0x613870a9
+#define BOARD_ID_FST_01            0x696886af
+#define BOARD_ID_MAPLE_MINI        0x7a445272
+#define BOARD_ID_OLIMEX_STM32_H103 0xf92bb594
+#define BOARD_ID_STBEE_MINI        0x1f341961
+#define BOARD_ID_STBEE             0x945c37e8
+#define BOARD_ID_STM32_PRIMER2     0x21e5798d
+#define BOARD_ID_STM8S_DISCOVERY   0x2f0976bb
+
 extern const uint8_t sys_version[8];
+extern const uint32_t sys_board_id;
+extern const uint8_t sys_board_name[];

 typedef void (*handler)(void);
 extern handler vector[16];
--- a/example-fsm-55/board.h
+++ b/example-fsm-55/board.h
@@ -0,0 +1 @@
+../board/board-fsm-55.h
--- a/example-fsm-55/hacker-emblem.c
+++ b/example-fsm-55/hacker-emblem.c
@@ -1 +1 @@
-debian-logo.c
+hh.c
--- a/example-fsm-55/hacker-emblem.ld
+++ b/example-fsm-55/hacker-emblem.ld
@@ -1,5 +1,5 @@
 /*
- * ST32F103 memory setup.
+ * ST32F0 memory setup.
 */
 __main_stack_size__     = 0x0100;  /* Exception handlers     */
 __process0_stack_size__  = 0x0100; /* Main program           */
@@ -9,18 +9,11 @@ __process3_stack_size__  = 0x0100; /* third thread program */

 MEMORY
 {
-/*
    flash0 : org = 0x08000000, len = 4k
    flash  : org = 0x08000000+0x1000, len = 60k
-*/
-    flash0 : org = 0x08000000, len = 1k
-    flash  : org = 0x08000000+0x0400, len = 60k
    ram : org = 0x20000000, len = 20k
 }

-__flash_start__ = 0x08001000;
-__flash_end__   = 0x08020000;
-
 __ram_start__           = ORIGIN(ram);
 __ram_size__            = 20k;
 __ram_end__             = __ram_start__ + __ram_size__;
@@ -29,23 +22,20 @@ SECTIONS
 {
    . = 0;

-    .sys : ALIGN(16) SUBALIGN(16)
+    .sys : ALIGN(4) SUBALIGN(4)
    {
 	_sys = .;
 	KEEP(*(.vectors))
 	. = ALIGN(16);
-	*(.sys.version)
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
 	build/sys.o(.text)
 	build/sys.o(.text.*)
 	build/sys.o(.rodata)
 	build/sys.o(.rodata.*)
 	. = ALIGN(1024);
-/*
-	*(.sys.0)
-	*(.sys.1)
-	*(.sys.2)
-*/
-    } > flash0
+    } > flash0 =0xffffffff

    _text = .;

@@ -65,6 +55,7 @@ SECTIONS
        *(.glue_7t)
        *(.glue_7)
        *(.gcc*)
+	. = ALIGN(8);
    } > flash

    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
@@ -97,15 +88,15 @@ SECTIONS
        __process3_stack_base__ = .;
        . += __process3_stack_size__;
        . = ALIGN(8);
-        __process_stack3_end__ = .;
+        __process3_stack_end__ = .;
        __process2_stack_base__ = .;
        . += __process2_stack_size__;
        . = ALIGN(8);
-        __process_stack2_end__ = .;
+        __process2_stack_end__ = .;
        __process1_stack_base__ = .;
        . += __process1_stack_size__;
        . = ALIGN(8);
-        __process_stack1_end__ = .;
+        __process1_stack_end__ = .;
        __process0_stack_base__ = .;
        . += __process0_stack_size__;
        . = ALIGN(8);
--- a/example-fsm-55/sys.c
+++ b/example-fsm-55/sys.c
@@ -1,7 +1,7 @@
 /*
 * sys.c - system routines for the initial page for STM32F030 / STM32F103.
 *
- * Copyright (C) 2013, 2014 Flying Stone Technology
+ * Copyright (C) 2013, 2014, 2015 Flying Stone Technology
 * Author: NIIBE Yutaka <gniibe@fsij.org>
 *
 * Copying and distribution of this file, with or without modification,
@@ -17,59 +17,13 @@
 #include <stdlib.h>
 #include "board.h"

+#include "clk_gpio_init.c"

 #define CORTEX_PRIORITY_BITS    4
 #define CORTEX_PRIORITY_MASK(n)  ((n) << (8 - CORTEX_PRIORITY_BITS))
 #define USB_LP_CAN1_RX0_IRQn	 20
 #define STM32_USB_IRQ_PRIORITY   11

-#define STM32_SW_HSI		(0 << 0)
-#define STM32_SW_PLL		(2 << 0)
-#define STM32_PLLSRC_HSI	(0 << 16)
-#define STM32_PLLSRC_HSE	(1 << 16)
-
-#define STM32_PLLXTPRE_DIV1	(0 << 17)
-#define STM32_PLLXTPRE_DIV2	(1 << 17)
-
-#define STM32_HPRE_DIV1		(0 << 4)
-
-#define STM32_PPRE1_DIV1	(0 << 8)
-#define STM32_PPRE1_DIV2	(4 << 8)
-
-#define STM32_PPRE2_DIV1        (0 << 11)
-#define STM32_PPRE2_DIV2	(4 << 11)
-
-#define STM32_ADCPRE_DIV4	(1 << 14)
-#define STM32_ADCPRE_DIV6       (2 << 14)
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)
-
-#define STM32_MCO_NOCLOCK	(0 << 24)
-
-#if MCU_STM32F0
-#define STM32_PPRE1		STM32_PPRE1_DIV1
-#define STM32_PLLSRC		STM32_PLLSRC_HSI
-#define STM32_FLASHBITS		0x00000011
-#define STM32_PLLCLKIN		(STM32_HSICLK / 2)
-#else
-#define STM32_PPRE1		STM32_PPRE1_DIV2
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_FLASHBITS		0x00000012
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
-#endif
-
-#define STM32_SW		STM32_SW_PLL
-#define STM32_HPRE		STM32_HPRE_DIV1
-#define STM32_PPRE2		STM32_PPRE2_DIV1
-#define STM32_ADCPRE		STM32_ADCPRE_DIV6
-#define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
-
-#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK		STM32_PLLCLKOUT
-#define STM32_HCLK		(STM32_SYSCLK / 1)
-
 struct NVIC {
  uint32_t ISER[8];
  uint32_t unused1[24];
@@ -99,288 +53,6 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
  NVIC_ISER (n) = 1 << (n & 0x1F);
 }

-
-#define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-#if MCU_STM32F0
-  volatile uint32_t AHBRSTR;
-  volatile uint32_t CFGR2;
-  volatile uint32_t CFGR3;
-  volatile uint32_t CR2;
-#endif
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN	0x00800000
-#define RCC_APB1RSTR_USBRST	0x00800000
-
-#define RCC_CR_HSION		0x00000001
-#define RCC_CR_HSIRDY		0x00000002
-#define RCC_CR_HSITRIM		0x000000F8
-#define RCC_CR_HSEON		0x00010000
-#define RCC_CR_HSERDY		0x00020000
-#define RCC_CR_PLLON		0x01000000
-#define RCC_CR_PLLRDY		0x02000000
-
-#define RCC_CFGR_SWS		0x0000000C
-#define RCC_CFGR_SWS_HSI	0x00000000
-
-#define RCC_AHBENR_CRCEN        0x0040
-
-#if MCU_STM32F0
-#define RCC_AHBRSTR_IOPARST	0x00020000
-#define RCC_AHBRSTR_IOPBRST	0x00040000
-#define RCC_AHBRSTR_IOPCRST	0x00080000
-#define RCC_AHBRSTR_IOPDRST	0x00100000
-#define RCC_AHBRSTR_IOPFRST	0x00400000
-
-#define RCC_AHBENR_IOPAEN	0x00020000
-#define RCC_AHBENR_IOPBEN	0x00040000
-#define RCC_AHBENR_IOPCEN	0x00080000
-#define RCC_AHBENR_IOPDEN	0x00100000
-#define RCC_AHBENR_IOPFEN	0x00400000
-
-#define RCC_APB2RSTR_SYSCFGRST	0x00000001
-#define RCC_APB2ENR_SYSCFGEN	0x00000001
-#else
-#define RCC_APB2RSTR_AFIORST	0x00000001
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-#define RCC_APB2ENR_AFIOEN	0x00000001
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-#endif
-
-#if MCU_STM32F0
-struct SYSCFG {
-  volatile uint32_t CFGR1;
-  uint32_t dummy0;
-  volatile uint32_t EXTICR[4];
-  volatile uint32_t CFGR2;
-};
-#define SYSCFG_CFGR1_MEM_MODE 0x03
-
-#define SYSCFG_BASE	(APBPERIPH_BASE + 0x00010000)
-static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
-#endif
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void
-clock_init (void)
-{
-  /* HSI setup */
-  RCC->CR |= RCC_CR_HSION;
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;
-  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
-  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
-  RCC->CFGR = 0;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;
-
-#if !MCU_STM32F0
-  /* HSE setup */
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;
-#endif
-
-  /* PLL setup */
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-
-  /* Clock settings */
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
-    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /* Switching on the configured clock source. */
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-
-  /*
-   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
-   */
-
-  /* Flash setup */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* CRC */
-  RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
-#if MCU_STM32F0
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-  RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
-  RCC->APB2RSTR = 0;
-  
-  /* Use vectors on RAM */
-  SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
-#endif
-}
-
-
-#if MCU_STM32F0
-struct GPIO {
-  volatile uint32_t MODER;
-  volatile uint16_t OTYPER;
-  uint16_t dummy0;
-  volatile uint32_t OSPEEDR;
-  volatile uint32_t PUPDR;
-  volatile uint16_t IDR;
-  uint16_t dummy1;
-  volatile uint16_t ODR;
-  uint16_t dummy2;
-  volatile uint16_t BSRR;
-  uint16_t dummy3;
-  volatile uint32_t LCKR;
-  volatile uint32_t AFR[2];
-  volatile uint16_t BRR;
-  uint16_t dummy4;
-};
-
-#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
-#define GPIOF		((struct GPIO *) GPIOF_BASE)
-#else
-struct AFIO
-{
-  volatile uint32_t EVCR;
-  volatile uint32_t MAPR;
-  volatile uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  volatile uint32_t MAPR2;
-};
-
-#define AFIO_BASE 0x40010000
-static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
-
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
-#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-#endif
-
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-#ifdef GPIO_USB_BASE
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-#endif
-#ifdef GPIO_OTHER_BASE
-static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
-#endif
-
-static void
-gpio_init (void)
-{
-  /* Enable GPIO clock. */
-#if MCU_STM32F0
-  RCC->AHBENR |= RCC_ENR_IOP_EN;
-  RCC->AHBRSTR = RCC_RSTR_IOP_RST;
-  RCC->AHBRSTR = 0;
-#else
-  RCC->APB2ENR |= RCC_ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
-  RCC->APB2RSTR = 0;
-#endif
-
-#if MCU_STM32F0
-  GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
-  GPIO_LED->OTYPER  = VAL_GPIO_OTYPER;
-  GPIO_LED->MODER   = VAL_GPIO_MODER;
-  GPIO_LED->PUPDR   = VAL_GPIO_PUPDR;
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
-  GPIO_OTHER->OTYPER  = VAL_GPIO_OTHER_OTYPER;
-  GPIO_OTHER->MODER   = VAL_GPIO_OTHER_MODER;
-  GPIO_OTHER->PUPDR   = VAL_GPIO_OTHER_PUPDR;
-#endif
-#else
-#ifdef AFIO_MAPR_SOMETHING
-  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
-#endif
-
-  GPIO_USB->ODR = VAL_GPIO_ODR;
-  GPIO_USB->CRH = VAL_GPIO_CRH;
-  GPIO_USB->CRL = VAL_GPIO_CRL;
-
-#if GPIO_USB_BASE != GPIO_LED_BASE
-  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
-  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
-  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-#endif
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
-  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
-  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
-#endif
-#endif
-}
-
 static void
 usb_cable_config (int enable)
 {
@@ -571,16 +243,25 @@ flash_check_blank (const uint8_t *p_start, size_t size)
  return 1;
 }

-extern uint8_t __flash_start__, __flash_end__;
+#define FLASH_START_ADDR 0x08000000 /* Fixed for all STM32F0/F1.  */
+#define FLASH_OFFSET     0x1000     /* First pages are not-writable
+				       when protected.  */
+#if defined(__ARM_ARCH_6M__)
+#define FLASH_SIZE_REG   ((uint16_t *)0x1ffff7cc)
+#define CHIP_ID_REG      ((uint32_t *)0x40015800)
+#else
+#define FLASH_SIZE_REG   ((uint16_t *)0x1ffff7e0)
+#define CHIP_ID_REG      ((uint32_t *)0xe0042000)
+#endif
+#define FLASH_START      (FLASH_START_ADDR+FLASH_OFFSET)

 static int
 flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
 {
  int status;
-  uint32_t flash_start = (uint32_t)&__flash_start__;
-  uint32_t flash_end = (uint32_t)&__flash_end__;
+  uint32_t flash_end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;

-  if (dst_addr < flash_start || dst_addr + len > flash_end)
+  if (dst_addr < FLASH_START || dst_addr + len > flash_end)
    return 0;

  while (len)
@@ -633,17 +314,21 @@ flash_protect (void)
 static void __attribute__((naked))
 flash_erase_all_and_exec (void (*entry)(void))
 {
-  uint32_t addr = (uint32_t)&__flash_start__;
-  uint32_t end = (uint32_t)&__flash_end__;
+  uint32_t addr = FLASH_START;
+  uint32_t end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
+  uint32_t page_size = 1024;
  int r;

+  if (((*CHIP_ID_REG) & 0xfff) == 0x0414)
+    page_size = 2048;
+
  while (addr < end)
    {
      r = flash_erase_page (addr);
      if (r != 0)
 	break;

-      addr += FLASH_PAGE_SIZE;
+      addr += page_size;
    }

  if (addr >= end)
@@ -692,14 +377,14 @@ static void __attribute__ ((naked))
 reset (void)
 {
  /*
-   * This code may not be at start of flash ROM, because of DFU.
+   * This code may not be at the start of flash ROM, because of DFU.
   * So, we take the address from PC.
   */
-#if __ARM_ARCH_6M__
+#if defined(__ARM_ARCH_6M__)
  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
 		"ldr	r0, 1f\n\t"     /* r0 = RAM start */
-		"mov	r1, pc\n\t"	/* r1 = (PC + 0x0400) & ~0x03ff */
-		"mov	r2, #0x04\n\t"
+		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
+		"mov	r2, #0x10\n\t"
 		"lsl	r2, #8\n\t"
 		"add	r1, r1, r2\n\t"
 		"sub	r2, r2, #1\n\t"
@@ -764,7 +449,13 @@ handler vector[] __attribute__ ((section(".vectors"))) = {

 const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
  3*2+2,	     /* bLength */
-  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
-  /* sys version: "2.0" */
-  '2', 0, '.', 0, '0', 0,
+  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
+  /* sys version: "2.1" */
+  '2', 0, '.', 0, '1', 0,
 };
+
+const uint32_t __attribute__((section(".sys.board_id")))
+sys_board_id = BOARD_ID;
+
+const uint8_t __attribute__((section(".sys.board_name")))
+sys_board_name[] = BOARD_NAME;
--- a/example-fsm-55/sys.h
+++ b/example-fsm-55/sys.h
@@ -1,4 +1,21 @@
+#if defined(__ARM_ARCH_6M__)
+#define BOARD_ID_STM32F0_DISCOVERY 0xde4b4bc1
+#define BOARD_ID_FSM_55            0x83433c76
+#else
+#define BOARD_ID_CQ_STARM          0xc5480875
+#define BOARD_ID_FST_01_00         0x613870a9
+#define BOARD_ID_FST_01            0x696886af
+#define BOARD_ID_MAPLE_MINI        0x7a445272
+#define BOARD_ID_OLIMEX_STM32_H103 0xf92bb594
+#define BOARD_ID_STBEE_MINI        0x1f341961
+#define BOARD_ID_STBEE             0x945c37e8
+#define BOARD_ID_STM32_PRIMER2     0x21e5798d
+#define BOARD_ID_STM8S_DISCOVERY   0x2f0976bb
+#endif
+
 extern const uint8_t sys_version[8];
+extern const uint32_t sys_board_id;
+extern const uint8_t sys_board_name[];

 typedef void (*handler)(void);
 extern handler vector[16];
--- a/example-led/Makefile
+++ b/example-led/Makefile
@@ -2,9 +2,14 @@

 PROJECT = sample

+### Currently, it's for STM32F0 Discovery.
+### Please change lines started with '###' for Cortex-M3 board.
+
 CHOPSTX = ..
 LDSCRIPT= sample.ld
-CSRC = sys.c aes-constant-ft.c sample.c
+### LDSCRIPT= sample.ld.m3
+CSRC = sys.c sample.c
+### CSRC = sys.c aes-constant-ft.c sample.c

 ###################################
 CROSS = arm-none-eabi-
@@ -12,11 +17,11 @@ CC   = $(CROSS)gcc
 LD   = $(CROSS)gcc
 OBJCOPY   = $(CROSS)objcopy

-# MCU   = cortex-m3
+### MCU   = cortex-m3
 MCU   = cortex-m0
 CWARN = -Wall -Wextra -Wstrict-prototypes
 DEFS  = -DHAVE_SYS_H -DFREE_STANDING -DMHZ=48
-# DEFS  = -DFREE_STANDING -DHAVE_SYS_H -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
+### DEFS  = -DFREE_STANDING -DHAVE_SYS_H -DBUSY_LOOP -DCHX_FLAGS_MAIN=CHOPSTX_SCHED_RR
 OPT   = -O3 -Os -g
 LIBS  =

--- a/example-led/board.h
+++ b/example-led/board.h
@@ -0,0 +1 @@
+../board/board-stm32f0-discovery.h
--- a/example-led/sample.ld
+++ b/example-led/sample.ld
@@ -1,5 +1,5 @@
 /*
- * ST32F103 memory setup.
+ * ST32F0 memory setup.
 */
 __main_stack_size__     = 0x0100;  /* Exception handlers     */
 __process0_stack_size__  = 0x0100; /* Main program           */
@@ -9,18 +9,11 @@ __process3_stack_size__  = 0x0100; /* third thread program */

 MEMORY
 {
-/*
    flash0 : org = 0x08000000, len = 4k
    flash  : org = 0x08000000+0x1000, len = 60k
-*/
-    flash0 : org = 0x08000000, len = 1k
-    flash  : org = 0x08000000+0x0400, len = 60k
    ram : org = 0x20000000, len = 20k
 }

-__flash_start__ = 0x08001000;
-__flash_end__   = 0x08020000;
-
 __ram_start__           = ORIGIN(ram);
 __ram_size__            = 20k;
 __ram_end__             = __ram_start__ + __ram_size__;
@@ -29,12 +22,14 @@ SECTIONS
 {
    . = 0;

-    .sys : ALIGN(16) SUBALIGN(16)
+    .sys : ALIGN(4) SUBALIGN(4)
    {
 	_sys = .;
 	KEEP(*(.vectors))
 	. = ALIGN(16);
-	*(.sys.version)
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
 	build/sys.o(.text)
 	build/sys.o(.text.*)
 	build/sys.o(.rodata)
@@ -45,7 +40,7 @@ SECTIONS
 	*(.sys.1)
 	*(.sys.2)
 */
-    } > flash0
+    } > flash0 =0xffffffff

    _text = .;

@@ -65,6 +60,7 @@ SECTIONS
        *(.glue_7t)
        *(.glue_7)
        *(.gcc*)
+	. = ALIGN(8);
    } > flash

    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
@@ -88,7 +84,7 @@ SECTIONS
    {
        . = ALIGN(8);
        __vector_ram_addr__ = .;
-	KEEP(*(.data.startup.*))
+	KEEP(*(.bss.startup.*))
    } > ram

    .process_stack :
@@ -97,15 +93,15 @@ SECTIONS
        __process3_stack_base__ = .;
        . += __process3_stack_size__;
        . = ALIGN(8);
-        __process_stack3_end__ = .;
+        __process3_stack_end__ = .;
        __process2_stack_base__ = .;
        . += __process2_stack_size__;
        . = ALIGN(8);
-        __process_stack2_end__ = .;
+        __process2_stack_end__ = .;
        __process1_stack_base__ = .;
        . += __process1_stack_size__;
        . = ALIGN(8);
-        __process_stack1_end__ = .;
+        __process1_stack_end__ = .;
        __process0_stack_base__ = .;
        . += __process0_stack_size__;
        . = ALIGN(8);
--- a/example-led/sample.ld.m3
+++ b/example-led/sample.ld.m3
@@ -0,0 +1,142 @@
+/*
+ * ST32F103 memory setup.
+ */
+__main_stack_size__     = 0x0100;  /* Exception handlers     */
+__process0_stack_size__  = 0x0100; /* Main program           */
+__process1_stack_size__  = 0x0100; /* first thread program */
+__process2_stack_size__  = 0x0100; /* second thread program */
+__process3_stack_size__  = 0x0100; /* third thread program */
+
+MEMORY
+{
+    flash0 : org = 0x08000000, len = 4k
+    flash  : org = 0x08000000+0x1000, len = 60k
+    ram : org = 0x20000000, len = 20k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = 20k;
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+    . = 0;
+
+    .sys : ALIGN(4) SUBALIGN(4)
+    {
+	_sys = .;
+	KEEP(*(.vectors))
+	. = ALIGN(16);
+	KEEP(*(.sys.version))
+	KEEP(*(.sys.board_id))
+	KEEP(*(.sys.board_name))
+	build/sys.o(.text)
+	build/sys.o(.text.*)
+	build/sys.o(.rodata)
+	build/sys.o(.rodata.*)
+	. = ALIGN(1024);
+	*(.sys.0)
+	*(.sys.1)
+	*(.sys.2)
+    } > flash0
+
+    _text = .;
+
+    .startup : ALIGN(128) SUBALIGN(128)
+    {
+        KEEP(*(.startup.vectors))
+        . = ALIGN (16);
+    } > flash =0xffffffff
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+	. = ALIGN(8);
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash
+
+    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash
+
+    _etext = .;
+    _textdata = _etext;
+
+    .process_stack :
+    {
+        . = ALIGN(8);
+        __process3_stack_base__ = .;
+        . += __process3_stack_size__;
+        . = ALIGN(8);
+        __process3_stack_end__ = .;
+        __process2_stack_base__ = .;
+        . += __process2_stack_size__;
+        . = ALIGN(8);
+        __process2_stack_end__ = .;
+        __process1_stack_base__ = .;
+        . += __process1_stack_size__;
+        . = ALIGN(8);
+        __process1_stack_end__ = .;
+        __process0_stack_base__ = .;
+        . += __process0_stack_size__;
+        . = ALIGN(8);
+        __process0_stack_end__ = .;
+    } > ram
+
+    .main_stack :
+    {
+        . = ALIGN(8);
+        __main_stack_base__ = .;
+        . += __main_stack_size__;
+        . = ALIGN(8);
+        __main_stack_end__ = .;
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram
+
+    PROVIDE(end = .);
+    _end            = .;
+}
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;
--- a/example-led/sys.c
+++ b/example-led/sys.c
@@ -1,774 +0,0 @@
-/*
- * sys.c - system routines for the initial page for STM32F030 / STM32F103.
- *
- * Copyright (C) 2013, 2014 Flying Stone Technology
- * Author: NIIBE Yutaka <gniibe@fsij.org>
- *
- * Copying and distribution of this file, with or without modification,
- * are permitted in any medium without royalty provided the copyright
- * notice and this notice are preserved.  This file is offered as-is,
- * without any warranty.
- *
- * When the flash ROM is protected, we cannot modify the initial page.
- * We put some system routines (which is useful for any program) here.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include "board.h"
-
-
-#define CORTEX_PRIORITY_BITS    4
-#define CORTEX_PRIORITY_MASK(n)  ((n) << (8 - CORTEX_PRIORITY_BITS))
-#define USB_LP_CAN1_RX0_IRQn	 20
-#define STM32_USB_IRQ_PRIORITY   11
-
-
-#define STM32_SW_HSI		(0 << 0)
-#define STM32_SW_PLL		(2 << 0)
-#define STM32_PLLSRC_HSI	(0 << 16)
-#define STM32_PLLSRC_HSE	(1 << 16)
-
-#define STM32_PLLXTPRE_DIV1	(0 << 17)
-#define STM32_PLLXTPRE_DIV2	(1 << 17)
-
-#define STM32_HPRE_DIV1		(0 << 4)
-
-#define STM32_PPRE1_DIV1	(0 << 8)
-#define STM32_PPRE1_DIV2	(4 << 8)
-
-#define STM32_PPRE2_DIV1        (0 << 11)
-#define STM32_PPRE2_DIV2	(4 << 11)
-
-#define STM32_ADCPRE_DIV4	(1 << 14)
-#define STM32_ADCPRE_DIV6       (2 << 14)
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)
-
-#define STM32_MCO_NOCLOCK	(0 << 24)
-
-#if defined(MCU_STM32F0)
-#define STM32_PPRE1		STM32_PPRE1_DIV1
-#define STM32_PLLSRC		STM32_PLLSRC_HSI
-#define STM32_FLASHBITS		0x00000011
-#define STM32_PLLCLKIN		(STM32_HSICLK / 2)
-#else
-#define STM32_PPRE1		STM32_PPRE1_DIV2
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_FLASHBITS		0x00000012
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
-#endif
-
-#define STM32_SW		STM32_SW_PLL
-#define STM32_HPRE		STM32_HPRE_DIV1
-#define STM32_PPRE2		STM32_PPRE2_DIV1
-#define STM32_ADCPRE		STM32_ADCPRE_DIV6
-#define STM32_MCOSEL		STM32_MCO_NOCLOCK
-#define STM32_USBPRE            STM32_USBPRE_DIV1P5
-
-#define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
-#define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-#define STM32_SYSCLK		STM32_PLLCLKOUT
-#define STM32_HCLK		(STM32_SYSCLK / 1)
-
-struct NVIC {
-  uint32_t ISER[8];
-  uint32_t unused1[24];
-  uint32_t ICER[8];
-  uint32_t unused2[24];
-  uint32_t ISPR[8];
-  uint32_t unused3[24];
-  uint32_t ICPR[8];
-  uint32_t unused4[24];
-  uint32_t IABR[8];
-  uint32_t unused5[56];
-  uint32_t IPR[60];
-};
-
-static struct NVIC *const NVICBase = ((struct NVIC *const)0xE000E100);
-#define NVIC_ISER(n)	(NVICBase->ISER[n >> 5])
-#define NVIC_ICPR(n)	(NVICBase->ICPR[n >> 5])
-#define NVIC_IPR(n)	(NVICBase->IPR[n >> 2])
-
-static void
-nvic_enable_vector (uint32_t n, uint32_t prio)
-{
-  unsigned int sh = (n & 3) << 3;
-
-  NVIC_IPR (n) = (NVIC_IPR(n) & ~(0xFF << sh)) | (prio << sh);
-  NVIC_ICPR (n) = 1 << (n & 0x1F);
-  NVIC_ISER (n) = 1 << (n & 0x1F);
-}
-
-
-#define PERIPH_BASE	0x40000000
-#define APBPERIPH_BASE   PERIPH_BASE
-#define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
-#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
-
-struct RCC {
-  volatile uint32_t CR;
-  volatile uint32_t CFGR;
-  volatile uint32_t CIR;
-  volatile uint32_t APB2RSTR;
-  volatile uint32_t APB1RSTR;
-  volatile uint32_t AHBENR;
-  volatile uint32_t APB2ENR;
-  volatile uint32_t APB1ENR;
-  volatile uint32_t BDCR;
-  volatile uint32_t CSR;
-#if defined(MCU_STM32F0)
-  volatile uint32_t AHBRSTR;
-  volatile uint32_t CFGR2;
-  volatile uint32_t CFGR3;
-  volatile uint32_t CR2;
-#endif
-};
-
-#define RCC_BASE		(AHBPERIPH_BASE + 0x1000)
-static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
-
-#define RCC_APB1ENR_USBEN	0x00800000
-#define RCC_APB1RSTR_USBRST	0x00800000
-
-#define RCC_CR_HSION		0x00000001
-#define RCC_CR_HSIRDY		0x00000002
-#define RCC_CR_HSITRIM		0x000000F8
-#define RCC_CR_HSEON		0x00010000
-#define RCC_CR_HSERDY		0x00020000
-#define RCC_CR_PLLON		0x01000000
-#define RCC_CR_PLLRDY		0x02000000
-
-#define RCC_CFGR_SWS		0x0000000C
-#define RCC_CFGR_SWS_HSI	0x00000000
-
-#define RCC_AHBENR_CRCEN        0x0040
-
-#if MCU_STM32F0
-#define RCC_AHBRSTR_IOPARST	0x00020000
-#define RCC_AHBRSTR_IOPBRST	0x00040000
-#define RCC_AHBRSTR_IOPCRST	0x00080000
-#define RCC_AHBRSTR_IOPDRST	0x00100000
-#define RCC_AHBRSTR_IOPFRST	0x00400000
-
-#define RCC_AHBENR_IOPAEN	0x00020000
-#define RCC_AHBENR_IOPBEN	0x00040000
-#define RCC_AHBENR_IOPCEN	0x00080000
-#define RCC_AHBENR_IOPDEN	0x00100000
-#define RCC_AHBENR_IOPFEN	0x00400000
-
-#define RCC_APB2RSTR_SYSCFGRST	0x00000001
-#define RCC_APB2ENR_SYSCFGEN	0x00000001
-#else
-#define RCC_APB2RSTR_AFIORST	0x00000001
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-#define RCC_APB2ENR_AFIOEN	0x00000001
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-#endif
-
-#if MCU_STM32F0
-struct SYSCFG {
-  volatile uint32_t CFGR1;
-  uint32_t dummy0;
-  volatile uint32_t EXTICR[4];
-  volatile uint32_t CFGR2;
-};
-#define SYSCFG_CFGR1_MEM_MODE 0x03
-
-#define SYSCFG_BASE	(APBPERIPH_BASE + 0x00010000)
-static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
-#endif
-
-struct FLASH {
-  volatile uint32_t ACR;
-  volatile uint32_t KEYR;
-  volatile uint32_t OPTKEYR;
-  volatile uint32_t SR;
-  volatile uint32_t CR;
-  volatile uint32_t AR;
-  volatile uint32_t RESERVED;
-  volatile uint32_t OBR;
-  volatile uint32_t WRPR;
-};
-
-#define FLASH_R_BASE	(AHBPERIPH_BASE + 0x2000)
-static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
-
-static void
-clock_init (void)
-{
-  /* HSI setup */
-  RCC->CR |= RCC_CR_HSION;
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;
-  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
-  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
-  RCC->CFGR = 0;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;
-
-#if !defined(MCU_STM32F0)
-  /* HSE setup */
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;
-#endif
-
-  /* PLL setup */
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-
-  /* Clock settings */
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
-    | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /*
-   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
-   */
-
-  /* Flash setup */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* CRC */
-  RCC->AHBENR |= RCC_AHBENR_CRCEN;
-
-  /* Switching on the configured clock source. */
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-
-#if defined(MCU_STM32F0)
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-  RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
-  RCC->APB2RSTR = 0;
-  
-  /* Use vectors on RAM */
-  SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
-#endif
-}
-
-
-#if defined(MCU_STM32F0)
-struct GPIO {
-  volatile uint32_t MODER;
-  volatile uint16_t OTYPER;
-  uint16_t dummy0;
-  volatile uint32_t OSPEEDR;
-  volatile uint32_t PUPDR;
-  volatile uint16_t IDR;
-  uint16_t dummy1;
-  volatile uint16_t ODR;
-  uint16_t dummy2;
-  volatile uint16_t BSRR;
-  uint16_t dummy3;
-  volatile uint32_t LCKR;
-  volatile uint32_t AFR[2];
-  volatile uint16_t BRR;
-  uint16_t dummy4;
-};
-
-#define GPIOA_BASE	(AHB2PERIPH_BASE + 0x0000)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(AHB2PERIPH_BASE + 0x0400)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(AHB2PERIPH_BASE + 0x0800)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(AHB2PERIPH_BASE + 0x0C00)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOF_BASE	(AHB2PERIPH_BASE + 0x1400)
-#define GPIOF		((struct GPIO *) GPIOF_BASE)
-#else
-struct AFIO
-{
-  volatile uint32_t EVCR;
-  volatile uint32_t MAPR;
-  volatile uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  volatile uint32_t MAPR2;
-};
-
-#define AFIO_BASE 0x40010000
-static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
-
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
-#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
-
-
-struct GPIO {
-  volatile uint32_t CRL;
-  volatile uint32_t CRH;
-  volatile uint32_t IDR;
-  volatile uint32_t ODR;
-  volatile uint32_t BSRR;
-  volatile uint32_t BRR;
-  volatile uint32_t LCKR;
-};
-
-#define GPIOA_BASE	(APB2PERIPH_BASE + 0x0800)
-#define GPIOA		((struct GPIO *) GPIOA_BASE)
-#define GPIOB_BASE	(APB2PERIPH_BASE + 0x0C00)
-#define GPIOB		((struct GPIO *) GPIOB_BASE)
-#define GPIOC_BASE	(APB2PERIPH_BASE + 0x1000)
-#define GPIOC		((struct GPIO *) GPIOC_BASE)
-#define GPIOD_BASE	(APB2PERIPH_BASE + 0x1400)
-#define GPIOD		((struct GPIO *) GPIOD_BASE)
-#define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
-#define GPIOE		((struct GPIO *) GPIOE_BASE)
-#endif
-
-static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
-#ifdef GPIO_USB_BASE
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
-#endif
-#ifdef GPIO_OTHER_BASE
-static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
-#endif
-
-static void
-gpio_init (void)
-{
-  /* Enable GPIO clock. */
-#if defined(MCU_STM32F0)
-  RCC->AHBENR |= RCC_ENR_IOP_EN;
-  RCC->AHBRSTR = RCC_RSTR_IOP_RST;
-  RCC->AHBRSTR = 0;
-#else
-  RCC->APB2ENR |= RCC_ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
-  RCC->APB2RSTR = 0;
-#endif
-
-#if MCU_STM32F0
-  GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
-  GPIO_LED->OTYPER  = VAL_GPIO_OTYPER;
-  GPIO_LED->MODER   = VAL_GPIO_MODER;
-  GPIO_LED->PUPDR   = VAL_GPIO_PUPDR;
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
-  GPIO_OTHER->OTYPER  = VAL_GPIO_OTHER_OTYPER;
-  GPIO_OTHER->MODER   = VAL_GPIO_OTHER_MODER;
-  GPIO_OTHER->PUPDR   = VAL_GPIO_OTHER_PUPDR;
-#endif
-#else
-#ifdef AFIO_MAPR_SOMETHING
-  AFIO->MAPR |= AFIO_MAPR_SOMETHING;
-#endif
-
-  GPIO_USB->ODR = VAL_GPIO_ODR;
-  GPIO_USB->CRH = VAL_GPIO_CRH;
-  GPIO_USB->CRL = VAL_GPIO_CRL;
-
-#if GPIO_USB_BASE != GPIO_LED_BASE
-  GPIO_LED->ODR = VAL_GPIO_LED_ODR;
-  GPIO_LED->CRH = VAL_GPIO_LED_CRH;
-  GPIO_LED->CRL = VAL_GPIO_LED_CRL;
-#endif
-
-#ifdef GPIO_OTHER_BASE
-  GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
-  GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
-  GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
-#endif
-#endif
-}
-
-static void
-usb_cable_config (int enable)
-{
-#if defined(GPIO_USB_SET_TO_ENABLE)
-  if (enable)
-    GPIO_USB->BSRR = (1 << GPIO_USB_SET_TO_ENABLE);
-  else
-    GPIO_USB->BRR = (1 << GPIO_USB_SET_TO_ENABLE);
-#elif defined(GPIO_USB_CLEAR_TO_ENABLE)
-  if (enable)
-    GPIO_USB->BRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
-  else
-    GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
-#else
-  (void)enable;
-#endif
-}
-
-void
-set_led (int on)
-{
-#if defined(GPIO_LED_CLEAR_TO_EMIT)
-  if (on)
-    GPIO_LED->BRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
-  else
-    GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
-#else
-  if (on)
-    GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT);
-  else
-    GPIO_LED->BRR = (1 << GPIO_LED_SET_TO_EMIT);
-#endif
-}
-
-static void wait (int count)
-{
-  int i;
-
-  for (i = 0; i < count; i++)
-    asm volatile ("" : : "r" (i) : "memory");
-}
-
-
-static void
-usb_lld_sys_shutdown (void)
-{
-  RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
-  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
-  usb_cable_config (0);
-}
-
-static void
-usb_lld_sys_init (void)
-{
-  if ((RCC->APB1ENR & RCC_APB1ENR_USBEN)
-      && (RCC->APB1RSTR & RCC_APB1RSTR_USBRST) == 0)
-    /* Make sure the device is disconnected, even after core reset.  */
-    {
-      usb_lld_sys_shutdown ();
-      /* Disconnect requires SE0 (>= 2.5uS).  */
-      wait (300);
-    }
-
-  usb_cable_config (1);
-  RCC->APB1ENR |= RCC_APB1ENR_USBEN;
-  nvic_enable_vector (USB_LP_CAN1_RX0_IRQn,
-		      CORTEX_PRIORITY_MASK (STM32_USB_IRQ_PRIORITY));
-  /*
-   * Note that we also have other IRQ(s):
-   * 	USB_HP_CAN1_TX_IRQn (for double-buffered or isochronous)
-   * 	USBWakeUp_IRQn (suspend/resume)
-   */
-  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
-  RCC->APB1RSTR = 0;
-}
-
-#define FLASH_KEY1               0x45670123UL
-#define FLASH_KEY2               0xCDEF89ABUL
-
-enum flash_status
-{
-  FLASH_BUSY = 1,
-  FLASH_ERROR_PG,
-  FLASH_ERROR_WRP,
-  FLASH_COMPLETE,
-  FLASH_TIMEOUT
-};
-
-static void __attribute__ ((used))
-flash_unlock (void)
-{
-  FLASH->KEYR = FLASH_KEY1;
-  FLASH->KEYR = FLASH_KEY2;
-}
-
-
-#define intr_disable()  asm volatile ("cpsid   i" : : : "memory")
-#define intr_enable()  asm volatile ("cpsie   i" : : : "memory")
-
-#define FLASH_SR_BSY		0x01
-#define FLASH_SR_PGERR		0x04
-#define FLASH_SR_WRPRTERR	0x10
-#define FLASH_SR_EOP		0x20
-
-#define FLASH_CR_PG	0x0001
-#define FLASH_CR_PER	0x0002
-#define FLASH_CR_MER	0x0004
-#define FLASH_CR_OPTPG	0x0010
-#define FLASH_CR_OPTER	0x0020
-#define FLASH_CR_STRT	0x0040
-#define FLASH_CR_LOCK	0x0080
-#define FLASH_CR_OPTWRE	0x0200
-#define FLASH_CR_ERRIE	0x0400
-#define FLASH_CR_EOPIE	0x1000
-
-static int
-flash_wait_for_last_operation (uint32_t timeout)
-{
-  int status;
-
-  do
-    {
-      status = FLASH->SR;
-      if (--timeout == 0)
-	break;
-    }
-  while ((status & FLASH_SR_BSY) != 0);
-
-  return status & (FLASH_SR_BSY|FLASH_SR_PGERR|FLASH_SR_WRPRTERR);
-}
-
-#define FLASH_PROGRAM_TIMEOUT 0x00010000
-#define FLASH_ERASE_TIMEOUT   0x01000000
-
-static int
-flash_program_halfword (uint32_t addr, uint16_t data)
-{
-  int status;
-
-  status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
-
-  intr_disable ();
-  if (status == 0)
-    {
-      FLASH->CR |= FLASH_CR_PG;
-
-      *(volatile uint16_t *)addr = data;
-
-      status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
-      FLASH->CR &= ~FLASH_CR_PG;
-    }
-  intr_enable ();
-
-  return status;
-}
-
-static int
-flash_erase_page (uint32_t addr)
-{
-  int status;
-
-  status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
-
-  intr_disable ();
-  if (status == 0)
-    {
-      FLASH->CR |= FLASH_CR_PER;
-      FLASH->AR = addr;
-      FLASH->CR |= FLASH_CR_STRT;
-
-      status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
-      FLASH->CR &= ~FLASH_CR_PER;
-    }
-  intr_enable ();
-
-  return status;
-}
-
-static int
-flash_check_blank (const uint8_t *p_start, size_t size)
-{
-  const uint8_t *p;
-
-  for (p = p_start; p < p_start + size; p++)
-    if (*p != 0xff)
-      return 0;
-
-  return 1;
-}
-
-extern uint8_t __flash_start__, __flash_end__;
-
-static int
-flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
-{
-  int status;
-  uint32_t flash_start = (uint32_t)&__flash_start__;
-  uint32_t flash_end = (uint32_t)&__flash_end__;
-
-  if (dst_addr < flash_start || dst_addr + len > flash_end)
-    return 0;
-
-  while (len)
-    {
-      uint16_t hw = *src++;
-
-      hw |= (*src++ << 8);
-      status = flash_program_halfword (dst_addr, hw);
-      if (status != 0)
-	return 0;		/* error return */
-
-      dst_addr += 2;
-      len -= 2;
-    }
-
-  return 1;
-}
-
-#define OPTION_BYTES_ADDR 0x1ffff800
-
-static int
-flash_protect (void)
-{
-  int status;
-  uint32_t option_bytes_value;
-
-  status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
-
-  intr_disable ();
-  if (status == 0)
-    {
-      FLASH->OPTKEYR = FLASH_KEY1;
-      FLASH->OPTKEYR = FLASH_KEY2;
-
-      FLASH->CR |= FLASH_CR_OPTER;
-      FLASH->CR |= FLASH_CR_STRT;
-
-      status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
-      FLASH->CR &= ~FLASH_CR_OPTER;
-    }
-  intr_enable ();
-
-  if (status != 0)
-    return 0;
-
-  option_bytes_value = *(uint32_t *)OPTION_BYTES_ADDR;
-  return (option_bytes_value & 0xff) == 0xff ? 1 : 0;
-}
-
-static void __attribute__((naked))
-flash_erase_all_and_exec (void (*entry)(void))
-{
-  uint32_t addr = (uint32_t)&__flash_start__;
-  uint32_t end = (uint32_t)&__flash_end__;
-  int r;
-
-  while (addr < end)
-    {
-      r = flash_erase_page (addr);
-      if (r != 0)
-	break;
-
-      addr += FLASH_PAGE_SIZE;
-    }
-
-  if (addr >= end)
-    (*entry) ();
-
-  for (;;);
-}
-
-struct SCB
-{
-  volatile uint32_t CPUID;
-  volatile uint32_t ICSR;
-  volatile uint32_t VTOR;
-  volatile uint32_t AIRCR;
-  volatile uint32_t SCR;
-  volatile uint32_t CCR;
-  volatile uint8_t  SHP[12];
-  volatile uint32_t SHCSR;
-  volatile uint32_t CFSR;
-  volatile uint32_t HFSR;
-  volatile uint32_t DFSR;
-  volatile uint32_t MMFAR;
-  volatile uint32_t BFAR;
-  volatile uint32_t AFSR;
-  volatile uint32_t PFR[2];
-  volatile uint32_t DFR;
-  volatile uint32_t ADR;
-  volatile uint32_t MMFR[4];
-  volatile uint32_t ISAR[5];
-};
-
-#define SCS_BASE	(0xE000E000)
-#define SCB_BASE	(SCS_BASE +  0x0D00)
-static struct SCB *const SCB = ((struct SCB *const) SCB_BASE);
-
-#define SYSRESETREQ 0x04
-static void
-nvic_system_reset (void)
-{
-  SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
-  asm volatile ("dsb");
-  for (;;);
-}
-
-static void __attribute__ ((naked))
-reset (void)
-{
-  extern const unsigned long *FT0, *FT1, *FT2;
-
-  /*
-   * This code may not be at the start of flash ROM, because of DFU.
-   * So, we take the address from PC.
-   */
-#if defined(__ARM_ARCH_6M__)
-  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
-		"ldr	r0, 1f\n\t"     /* r0 = RAM start */
-		"mov	r1, pc\n\t"	/* r1 = (PC + 0x0400) & ~0x03ff */
-		"mov	r2, #0x04\n\t"
-		"lsl	r2, #8\n\t"
-		"add	r1, r1, r2\n\t"
-		"sub	r2, r2, #1\n\t"
-		"bic	r1, r1, r2\n\t"
-		"mov	r2, #188\n"
-	"2:\n\t" /* Copy vectors.  It will be enabled later by clock_init.  */
-		"ldr	r3, [r1, r2]\n\t"
-		"str	r3, [r0, r2]\n\t"
-		"sub	r2, #4\n\t"
-		"bcs	2b\n\t"
-		"msr	MSP, r3\n\t"	/* Main (exception handler) stack. */
-		"ldr	r0, [r1, #4]\n\t" /* Reset handler.                */
-		"bx	r0\n\t"
-		".align	2\n"
-	"1:	.word	0x20000000"
-		: /* no output */ : /* no input */ : "memory");
-#else
-  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
-		"ldr	r0, 1f\n\t"     /* r0 = SCR */
-		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
-		"mov	r2, #0x1000\n\t"
-		"add	r1, r1, r2\n\t"
-		"sub	r2, r2, #1\n\t"
-		"bic	r1, r1, r2\n\t"
-		"str	r1, [r0, #8]\n\t"	/* Set SCR->VCR */
-		"ldr	r0, [r1], #4\n\t"
-		"msr	MSP, r0\n\t"	/* Main (exception handler) stack. */
-		"ldr	r0, [r1]\n\t"	/* Reset handler.                  */
-		"bx	r0\n\t"
-		".align	2\n"
-	"1:	.word	0xe000ed00"
-		: /* no output */ : /* no input */ : "memory");
-#endif
-
-  /* Never reach here. */
-  /* Artificial entry to refer FT0, FT1, and FT2.  */
-  asm volatile (""
-		: : "r" (FT0), "r" (FT1), "r" (FT2));
-}
-
-typedef void (*handler)(void);
-extern uint8_t __ram_end__;
-
-handler vector[] __attribute__ ((section(".vectors"))) = {
-  (handler)&__ram_end__,
-  reset,
-  (handler)set_led,
-  flash_unlock,
-  (handler)flash_program_halfword,
-  (handler)flash_erase_page,
-  (handler)flash_check_blank,
-  (handler)flash_write,
-  (handler)flash_protect,
-  (handler)flash_erase_all_and_exec,
-  usb_lld_sys_init,
-  usb_lld_sys_shutdown,
-  nvic_system_reset,
-  clock_init,
-  gpio_init,
-  NULL,
-};
-
-const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
-  3*2+2,	     /* bLength */
-  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE*/
-  /* sys version: "2.0" */
-  '2', 0, '.', 0, '0', 0,
-};
--- a/example-led/sys.c
+++ b/example-led/sys.c
@@ -0,0 +1 @@
+../example-fsm-55/sys.c
--- a/example-led/sys.h
+++ b/example-led/sys.h
@@ -1,115 +0,0 @@
-extern const uint8_t sys_version[8];
-
-typedef void (*handler)(void);
-extern handler vector[16];
-
-static inline const uint8_t *
-unique_device_id (void)
-{
-  /* STM32F103 has 96-bit unique device identifier */
-  const uint8_t *addr = (const uint8_t *)0x1ffff7e8;
-
-  return addr;
-}
-
-static inline void
-set_led (int on)
-{
-  void (*func) (int) = (void (*)(int))vector[2];
-
-  return (*func) (on);
-}
-
-static inline void
-flash_unlock (void)
-{
-  (*vector[3]) ();
-}
-
-static inline int
-flash_program_halfword (uint32_t addr, uint16_t data)
-{
-  int (*func) (uint32_t, uint16_t) = (int (*)(uint32_t, uint16_t))vector[4];
-
-  return (*func) (addr, data);
-}
-
-static inline int
-flash_erase_page (uint32_t addr)
-{
-  int (*func) (uint32_t) = (int (*)(uint32_t))vector[5];
-
-  return (*func) (addr);
-}
-
-static inline int
-flash_check_blank (const uint8_t *p_start, size_t size)
-{
-  int (*func) (const uint8_t *, int) = (int (*)(const uint8_t *, int))vector[6];
-
-  return (*func) (p_start, size);
-}
-
-static inline int
-flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
-{
-  int (*func) (uint32_t, const uint8_t *, size_t)
-    = (int (*)(uint32_t, const uint8_t *, size_t))vector[7];
-
-  return (*func) (dst_addr, src, len);
-}
-
-static inline int
-flash_protect (void)
-{
-  int (*func) (void) = (int (*)(void))vector[8];
-
-  return (*func) ();
-}
-
-static inline void __attribute__((noreturn))
-flash_erase_all_and_exec (void (*entry)(void))
-{
-  void (*func) (void (*)(void)) = (void (*)(void (*)(void)))vector[9];
-
-  (*func) (entry);
-  for (;;);
-}
-
-static inline void
-usb_lld_sys_init (void)
-{
-  (*vector[10]) ();
-}
-
-static inline void
-usb_lld_sys_shutdown (void)
-{
-  (*vector[11]) ();
-}
-
-static inline void
-nvic_system_reset (void)
-{
-  (*vector[12]) ();
-}
-
-/*
- * Users can override INLINE by 'attribute((used))' to have an
- * implementation defined.
- */
-#if !defined(INLINE)
-#define INLINE __inline__
-#endif
-
-static INLINE void
-clock_init (void)
-{
-  (*vector[13]) ();
-}
-
-static INLINE void
-gpio_init (void)
-{
-  (*vector[14]) ();
-}
--- a/example-led/sys.h
+++ b/example-led/sys.h
@@ -0,0 +1 @@
+../example-fsm-55/sys.h
Author	SHA1	Message	Date
NIIBE Yutaka	bdaae5661d	Version 0.07	2015-07-15 12:09:07 +09:00
NIIBE Yutaka	2de0e2c405	Update example CDC	2015-07-15 12:04:45 +09:00
NIIBE Yutaka	d19570954e	Update example for FSM-55	2015-07-15 12:03:49 +09:00
NIIBE Yutaka	44b4bf640f	Update example for LED blink	2015-07-15 12:01:53 +09:00
NIIBE Yutaka	9898639165	Update Cortex-M0 boards	2015-07-15 11:48:36 +09:00
NIIBE Yutaka	cd61ff5653	share sys with example-fsm-55	2015-07-15 09:51:24 +09:00
NIIBE Yutaka	27f42c8522	ADC settings are consolidated into the driver	2015-07-14 21:31:18 +09:00
NIIBE Yutaka	a48ffaef47	fix sys.c	2015-07-14 21:26:10 +09:00
NIIBE Yutaka	27f71ff5c0	New sys.c	2015-07-14 16:10:07 +09:00
NIIBE Yutaka	3ba8234cec	sys_board and stm32 primer2	2015-07-13 16:45:32 +09:00
NIIBE Yutaka	2bb0e0de5d	Version 0.06	2015-07-08 08:38:18 +09:00
NIIBE Yutaka	4dc10d6b18	Update for FSM-55	2015-07-07 12:31:15 +09:00
NIIBE Yutaka	43bd3bcefd	fix STBee Mini	2015-06-30 10:47:07 +09:00
NIIBE Yutaka	6d13bd3770	fix clk_gpio_init	2015-06-30 10:20:11 +09:00
NIIBE Yutaka	6665723154	Add support for CQ STARM.	2015-06-29 15:59:30 +09:00
NIIBE Yutaka	97b4471cee	Make it clear LED is mandatory.	2015-06-29 15:58:21 +09:00
NIIBE Yutaka	15ae2d8b32	cleanup entry.c	2015-06-29 13:48:30 +09:00
NIIBE Yutaka	48273b3cb6	Clean up clock/gpio code	2015-06-22 17:34:17 +09:00
NIIBE Yutaka	b298648079	Kaz Kojima add STM32 Primer2 support	2015-06-22 16:18:44 +09:00