Factor out mcu/cortex-m.h.
This commit is contained in:
@@ -1,5 +1,8 @@
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2017-11-17 NIIBE Yutaka <gniibe@fsij.org>
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* mcu/cortex-m.h: New.
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* mcu/sys-stm32f0.c, mcu/sys-stm32f103.c: Use mcu/cortex-m.h.
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* chopstx.c (chopstx_conf_idle): Call chx_sleep_mode before
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changing chx_allow_sleep.
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29
mcu/cortex-m.h
Normal file
29
mcu/cortex-m.h
Normal file
@@ -0,0 +1,29 @@
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/* System Control Block */
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struct SCB
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{
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volatile uint32_t CPUID;
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volatile uint32_t ICSR;
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volatile uint32_t VTOR;
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volatile uint32_t AIRCR;
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volatile uint32_t SCR;
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volatile uint32_t CCR;
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volatile uint8_t SHP[12];
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volatile uint32_t SHCSR;
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volatile uint32_t CFSR;
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volatile uint32_t HFSR;
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volatile uint32_t DFSR;
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volatile uint32_t MMAR;
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volatile uint32_t BFAR;
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volatile uint32_t AFSR;
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volatile uint32_t PFR[2];
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volatile uint32_t DFR;
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volatile uint32_t AFR;
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volatile uint32_t MMFR[4];
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volatile uint32_t ISAR[5];
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};
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#define SCS_BASE 0xE000E000
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#define SCB_BASE (SCS_BASE + 0x0D00)
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static struct SCB *const SCB = (struct SCB *)SCB_BASE;
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#define SCB_SCR_SLEEPDEEP (1 << 2)
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#define SCB_AIRCR_SYSRESETREQ 0x04
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@@ -1,7 +1,8 @@
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/*
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* sys.c - system routines for the initial page for STM32F030 / STM32F103.
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* sys-stm32f0.c - system routines for the initial page for STM32F030.
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*
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* Copyright (C) 2013, 2014, 2015, 2016 Flying Stone Technology
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* Copyright (C) 2013, 2014, 2015, 2016, 2017
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* Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* Copying and distribution of this file, with or without modification,
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@@ -18,6 +19,7 @@
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#include "board.h"
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#define STM32F0_USE_VECTOR_ON_RAM
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#include "mcu/cortex-m.h"
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#include "mcu/clk_gpio_init-stm32.c"
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@@ -298,38 +300,11 @@ flash_erase_all_and_exec (void (*entry)(void))
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for (;;);
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}
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struct SCB
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{
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volatile uint32_t CPUID;
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volatile uint32_t ICSR;
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volatile uint32_t VTOR;
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volatile uint32_t AIRCR;
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volatile uint32_t SCR;
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volatile uint32_t CCR;
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volatile uint8_t SHP[12];
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volatile uint32_t SHCSR;
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volatile uint32_t CFSR;
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volatile uint32_t HFSR;
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volatile uint32_t DFSR;
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volatile uint32_t MMFAR;
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volatile uint32_t BFAR;
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volatile uint32_t AFSR;
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volatile uint32_t PFR[2];
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volatile uint32_t DFR;
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volatile uint32_t ADR;
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volatile uint32_t MMFR[4];
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volatile uint32_t ISAR[5];
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};
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#define SCS_BASE (0xE000E000)
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#define SCB_BASE (SCS_BASE + 0x0D00)
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static struct SCB *const SCB = (struct SCB *)SCB_BASE;
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#define SYSRESETREQ 0x04
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static void
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nvic_system_reset (void)
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{
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SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
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SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SCB_AIRCR_SYSRESETREQ);
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asm volatile ("dsb");
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for (;;);
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}
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@@ -1,7 +1,8 @@
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/*
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* sys.c - system routines for the initial page for STM32F103.
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* sys-stm32f103.c - system routines for the initial page for STM32F103.
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*
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* Copyright (C) 2013, 2014, 2015, 2016 Flying Stone Technology
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* Copyright (C) 2013, 2014, 2015, 2016, 2017
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* Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* Copying and distribution of this file, with or without modification,
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@@ -17,6 +18,7 @@
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#include <stdlib.h>
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#include "board.h"
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#include "mcu/cortex-m.h"
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#include "mcu/clk_gpio_init-stm32.c"
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@@ -299,38 +301,10 @@ flash_erase_all_and_exec (void (*entry)(void))
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for (;;);
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}
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struct SCB
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{
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volatile uint32_t CPUID;
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volatile uint32_t ICSR;
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volatile uint32_t VTOR;
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volatile uint32_t AIRCR;
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volatile uint32_t SCR;
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volatile uint32_t CCR;
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volatile uint8_t SHP[12];
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volatile uint32_t SHCSR;
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volatile uint32_t CFSR;
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volatile uint32_t HFSR;
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volatile uint32_t DFSR;
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volatile uint32_t MMFAR;
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volatile uint32_t BFAR;
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volatile uint32_t AFSR;
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volatile uint32_t PFR[2];
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volatile uint32_t DFR;
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volatile uint32_t ADR;
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volatile uint32_t MMFR[4];
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volatile uint32_t ISAR[5];
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};
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#define SCS_BASE (0xE000E000)
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#define SCB_BASE (SCS_BASE + 0x0D00)
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static struct SCB *const SCB = (struct SCB *)SCB_BASE;
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#define SYSRESETREQ 0x04
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static void
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nvic_system_reset (void)
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{
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SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
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SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SCB_AIRCR_SYSRESETREQ);
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asm volatile ("dsb");
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for (;;);
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}
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