From b72154f47bc2a5ad1ee22b90bf040881362f0417 Mon Sep 17 00:00:00 2001 From: NIIBE Yutaka Date: Fri, 17 Nov 2017 11:34:28 +0900 Subject: [PATCH] Factor out mcu/cortex-m.h. --- ChangeLog | 3 +++ mcu/cortex-m.h | 29 +++++++++++++++++++++++++++++ mcu/sys-stm32f0.c | 35 +++++------------------------------ mcu/sys-stm32f103.c | 36 +++++------------------------------- 4 files changed, 42 insertions(+), 61 deletions(-) create mode 100644 mcu/cortex-m.h diff --git a/ChangeLog b/ChangeLog index 5508b30..a70ffab 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,8 @@ 2017-11-17 NIIBE Yutaka + * mcu/cortex-m.h: New. + * mcu/sys-stm32f0.c, mcu/sys-stm32f103.c: Use mcu/cortex-m.h. + * chopstx.c (chopstx_conf_idle): Call chx_sleep_mode before changing chx_allow_sleep. diff --git a/mcu/cortex-m.h b/mcu/cortex-m.h new file mode 100644 index 0000000..dbae9c6 --- /dev/null +++ b/mcu/cortex-m.h @@ -0,0 +1,29 @@ +/* System Control Block */ +struct SCB +{ + volatile uint32_t CPUID; + volatile uint32_t ICSR; + volatile uint32_t VTOR; + volatile uint32_t AIRCR; + volatile uint32_t SCR; + volatile uint32_t CCR; + volatile uint8_t SHP[12]; + volatile uint32_t SHCSR; + volatile uint32_t CFSR; + volatile uint32_t HFSR; + volatile uint32_t DFSR; + volatile uint32_t MMAR; + volatile uint32_t BFAR; + volatile uint32_t AFSR; + volatile uint32_t PFR[2]; + volatile uint32_t DFR; + volatile uint32_t AFR; + volatile uint32_t MMFR[4]; + volatile uint32_t ISAR[5]; +}; + +#define SCS_BASE 0xE000E000 +#define SCB_BASE (SCS_BASE + 0x0D00) +static struct SCB *const SCB = (struct SCB *)SCB_BASE; +#define SCB_SCR_SLEEPDEEP (1 << 2) +#define SCB_AIRCR_SYSRESETREQ 0x04 diff --git a/mcu/sys-stm32f0.c b/mcu/sys-stm32f0.c index f7db06c..d773c3c 100644 --- a/mcu/sys-stm32f0.c +++ b/mcu/sys-stm32f0.c @@ -1,7 +1,8 @@ /* - * sys.c - system routines for the initial page for STM32F030 / STM32F103. + * sys-stm32f0.c - system routines for the initial page for STM32F030. * - * Copyright (C) 2013, 2014, 2015, 2016 Flying Stone Technology + * Copyright (C) 2013, 2014, 2015, 2016, 2017 + * Flying Stone Technology * Author: NIIBE Yutaka * * Copying and distribution of this file, with or without modification, @@ -18,6 +19,7 @@ #include "board.h" #define STM32F0_USE_VECTOR_ON_RAM +#include "mcu/cortex-m.h" #include "mcu/clk_gpio_init-stm32.c" @@ -298,38 +300,11 @@ flash_erase_all_and_exec (void (*entry)(void)) for (;;); } -struct SCB -{ - volatile uint32_t CPUID; - volatile uint32_t ICSR; - volatile uint32_t VTOR; - volatile uint32_t AIRCR; - volatile uint32_t SCR; - volatile uint32_t CCR; - volatile uint8_t SHP[12]; - volatile uint32_t SHCSR; - volatile uint32_t CFSR; - volatile uint32_t HFSR; - volatile uint32_t DFSR; - volatile uint32_t MMFAR; - volatile uint32_t BFAR; - volatile uint32_t AFSR; - volatile uint32_t PFR[2]; - volatile uint32_t DFR; - volatile uint32_t ADR; - volatile uint32_t MMFR[4]; - volatile uint32_t ISAR[5]; -}; -#define SCS_BASE (0xE000E000) -#define SCB_BASE (SCS_BASE + 0x0D00) -static struct SCB *const SCB = (struct SCB *)SCB_BASE; - -#define SYSRESETREQ 0x04 static void nvic_system_reset (void) { - SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ); + SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SCB_AIRCR_SYSRESETREQ); asm volatile ("dsb"); for (;;); } diff --git a/mcu/sys-stm32f103.c b/mcu/sys-stm32f103.c index f391fa6..62084a6 100644 --- a/mcu/sys-stm32f103.c +++ b/mcu/sys-stm32f103.c @@ -1,7 +1,8 @@ /* - * sys.c - system routines for the initial page for STM32F103. + * sys-stm32f103.c - system routines for the initial page for STM32F103. * - * Copyright (C) 2013, 2014, 2015, 2016 Flying Stone Technology + * Copyright (C) 2013, 2014, 2015, 2016, 2017 + * Flying Stone Technology * Author: NIIBE Yutaka * * Copying and distribution of this file, with or without modification, @@ -17,6 +18,7 @@ #include #include "board.h" +#include "mcu/cortex-m.h" #include "mcu/clk_gpio_init-stm32.c" @@ -299,38 +301,10 @@ flash_erase_all_and_exec (void (*entry)(void)) for (;;); } -struct SCB -{ - volatile uint32_t CPUID; - volatile uint32_t ICSR; - volatile uint32_t VTOR; - volatile uint32_t AIRCR; - volatile uint32_t SCR; - volatile uint32_t CCR; - volatile uint8_t SHP[12]; - volatile uint32_t SHCSR; - volatile uint32_t CFSR; - volatile uint32_t HFSR; - volatile uint32_t DFSR; - volatile uint32_t MMFAR; - volatile uint32_t BFAR; - volatile uint32_t AFSR; - volatile uint32_t PFR[2]; - volatile uint32_t DFR; - volatile uint32_t ADR; - volatile uint32_t MMFR[4]; - volatile uint32_t ISAR[5]; -}; - -#define SCS_BASE (0xE000E000) -#define SCB_BASE (SCS_BASE + 0x0D00) -static struct SCB *const SCB = (struct SCB *)SCB_BASE; - -#define SYSRESETREQ 0x04 static void nvic_system_reset (void) { - SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ); + SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SCB_AIRCR_SYSRESETREQ); asm volatile ("dsb"); for (;;); }