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Factor out mcu/cortex-m.h.

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This commit is contained in:
NIIBE Yutaka
2017-11-17 11:34:28 +09:00
parent 378201a1c7
commit b72154f47b
4 changed files with 42 additions and 61 deletions
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3
ChangeLog
View File

@@ -1,5 +1,8 @@
2017-11-17 NIIBE Yutaka <gniibe@fsij.org> 2017-11-17 NIIBE Yutaka <gniibe@fsij.org>
* mcu/cortex-m.h: New.
* mcu/sys-stm32f0.c, mcu/sys-stm32f103.c: Use mcu/cortex-m.h.
* chopstx.c (chopstx_conf_idle): Call chx_sleep_mode before * chopstx.c (chopstx_conf_idle): Call chx_sleep_mode before
changing chx_allow_sleep. changing chx_allow_sleep.

29
mcu/cortex-m.h Normal file
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@@ -0,0 +1,29 @@
/* System Control Block */
struct SCB
{
volatile uint32_t CPUID;
volatile uint32_t ICSR;
volatile uint32_t VTOR;
volatile uint32_t AIRCR;
volatile uint32_t SCR;
volatile uint32_t CCR;
volatile uint8_t SHP[12];
volatile uint32_t SHCSR;
volatile uint32_t CFSR;
volatile uint32_t HFSR;
volatile uint32_t DFSR;
volatile uint32_t MMAR;
volatile uint32_t BFAR;
volatile uint32_t AFSR;
volatile uint32_t PFR[2];
volatile uint32_t DFR;
volatile uint32_t AFR;
volatile uint32_t MMFR[4];
volatile uint32_t ISAR[5];
};
#define SCS_BASE 0xE000E000
#define SCB_BASE (SCS_BASE + 0x0D00)
static struct SCB *const SCB = (struct SCB *)SCB_BASE;
#define SCB_SCR_SLEEPDEEP (1 << 2)
#define SCB_AIRCR_SYSRESETREQ 0x04

35
mcu/sys-stm32f0.c
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@@ -1,7 +1,8 @@
/* /*
* sys.c - system routines for the initial page for STM32F030 / STM32F103. * sys-stm32f0.c - system routines for the initial page for STM32F030.
* *
* Copyright (C) 2013, 2014, 2015, 2016 Flying Stone Technology * Copyright (C) 2013, 2014, 2015, 2016, 2017
* Flying Stone Technology
* Author: NIIBE Yutaka <gniibe@fsij.org> * Author: NIIBE Yutaka <gniibe@fsij.org>
* *
* Copying and distribution of this file, with or without modification, * Copying and distribution of this file, with or without modification,
@@ -18,6 +19,7 @@
#include "board.h" #include "board.h"
#define STM32F0_USE_VECTOR_ON_RAM #define STM32F0_USE_VECTOR_ON_RAM
#include "mcu/cortex-m.h"
#include "mcu/clk_gpio_init-stm32.c" #include "mcu/clk_gpio_init-stm32.c"
@@ -298,38 +300,11 @@ flash_erase_all_and_exec (void (*entry)(void))
for (;;); for (;;);
} }
struct SCB
{
volatile uint32_t CPUID;
volatile uint32_t ICSR;
volatile uint32_t VTOR;
volatile uint32_t AIRCR;
volatile uint32_t SCR;
volatile uint32_t CCR;
volatile uint8_t SHP[12];
volatile uint32_t SHCSR;
volatile uint32_t CFSR;
volatile uint32_t HFSR;
volatile uint32_t DFSR;
volatile uint32_t MMFAR;
volatile uint32_t BFAR;
volatile uint32_t AFSR;
volatile uint32_t PFR[2];
volatile uint32_t DFR;
volatile uint32_t ADR;
volatile uint32_t MMFR[4];
volatile uint32_t ISAR[5];
};
#define SCS_BASE (0xE000E000)
#define SCB_BASE (SCS_BASE + 0x0D00)
static struct SCB *const SCB = (struct SCB *)SCB_BASE;
#define SYSRESETREQ 0x04
static void static void
nvic_system_reset (void) nvic_system_reset (void)
{ {
SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ); SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SCB_AIRCR_SYSRESETREQ);
asm volatile ("dsb"); asm volatile ("dsb");
for (;;); for (;;);
} }

36
mcu/sys-stm32f103.c
View File

@@ -1,7 +1,8 @@
/* /*
* sys.c - system routines for the initial page for STM32F103. * sys-stm32f103.c - system routines for the initial page for STM32F103.
* *
* Copyright (C) 2013, 2014, 2015, 2016 Flying Stone Technology * Copyright (C) 2013, 2014, 2015, 2016, 2017
* Flying Stone Technology
* Author: NIIBE Yutaka <gniibe@fsij.org> * Author: NIIBE Yutaka <gniibe@fsij.org>
* *
* Copying and distribution of this file, with or without modification, * Copying and distribution of this file, with or without modification,
@@ -17,6 +18,7 @@
#include <stdlib.h> #include <stdlib.h>
#include "board.h" #include "board.h"
#include "mcu/cortex-m.h"
#include "mcu/clk_gpio_init-stm32.c" #include "mcu/clk_gpio_init-stm32.c"
@@ -299,38 +301,10 @@ flash_erase_all_and_exec (void (*entry)(void))
for (;;); for (;;);
} }
struct SCB
{
volatile uint32_t CPUID;
volatile uint32_t ICSR;
volatile uint32_t VTOR;
volatile uint32_t AIRCR;
volatile uint32_t SCR;
volatile uint32_t CCR;
volatile uint8_t SHP[12];
volatile uint32_t SHCSR;
volatile uint32_t CFSR;
volatile uint32_t HFSR;
volatile uint32_t DFSR;
volatile uint32_t MMFAR;
volatile uint32_t BFAR;
volatile uint32_t AFSR;
volatile uint32_t PFR[2];
volatile uint32_t DFR;
volatile uint32_t ADR;
volatile uint32_t MMFR[4];
volatile uint32_t ISAR[5];
};
#define SCS_BASE (0xE000E000)
#define SCB_BASE (SCS_BASE + 0x0D00)
static struct SCB *const SCB = (struct SCB *)SCB_BASE;
#define SYSRESETREQ 0x04
static void static void
nvic_system_reset (void) nvic_system_reset (void)
{ {
SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ); SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SCB_AIRCR_SYSRESETREQ);
asm volatile ("dsb"); asm volatile ("dsb");
for (;;); for (;;);
} }