Start experiment with STM32L432.
This commit is contained in:
NIIBE Yutaka
61
board/board-st-nucleo-l432.h
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61
board/board-st-nucleo-l432.h
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#define BOARD_NAME "ST Nucleo L432"
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#define BOARD_ID 0x3a8d5116
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/*
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* Please add USB cable to ST Nucleo L432.
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*
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* At CN4, connect USB cable, only when ST Link is not connected
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* Vbus RED --> 4
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*
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* At CN3, connect USB cable
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* D- GREEN --> 13 PA11
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* D+ WHITE --> 5 PA12
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* GND BLACK --> 4 GND
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*/
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#define MCU_STM32L4 1
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#define RCC_HSICLK 48000000
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#define GPIO_LED_BASE GPIOB_BASE
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#define GPIO_LED_SET_TO_EMIT 3
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#undef GPIO_USB_BASE /* No external DISCONNECT/RENUM circuit. */
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#define GPIO_OTHER_BASE GPIOB_BASE
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/*
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* Port A setup.
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* PA0 - Input with pull-up USART2-CTS
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* PA1 - Alternate function push pull output 2MHz USART2-RTS
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* PA2 - Alternate function push pull output 2MHz USART2-TX
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* PA3 - Input with pull-up USART2-RX
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* PA4 - Alternate function push pull output 2MHz USART2-CK
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* PA5 - Push pull output 2MHz (LED 1:ON 0:OFF)
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* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
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* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
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* ------------------------ Default
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* PAx - input with pull-up
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*/
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#define VAL_GPIO_LED_ODR 0xFFFFE7FF
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/*
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* Port B setup.
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* PB0 - input with pull-up: AN8 for NeuG
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* PB1 - input with pull-up: AN9 for NeuG
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* ---
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* ---
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* PB4 - Input with pull-up: Card insertion detect: 0 when detected
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* ---
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* PB6 - Output push pull 2MHz: Vcc for card: default 0
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* ---
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* PB8 - Output push pull 2MHz: Vpp for card: default 0
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* PB9 - Output push pull 2MHz: RST for card: default 0
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* PB10 - Alternate function open-drain output 50MHz USART3-TX
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* PB11 - Input with pull-up USART3-RX
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* PB12 - Alternate function push pull output 50MHz USART3-CK
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* PB13 - Input with pull-up USART3-CTS
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* PB14 - Alternate function push pull output 50MHz USART3-RTS
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* ---
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* ------------------------ Default
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* PBx - input with pull-up.
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*/
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#define VAL_GPIO_OTHER_ODR 0xFFFFFCBF
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51
mcu/clk_gpio_init-stm32l.c
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51
mcu/clk_gpio_init-stm32l.c
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/*
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* clk_gpio_init-stm32l.c - Clock and GPIO initialization for STM32L.
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*
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* Copyright (C) 2019 Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* This file is a part of Chopstx, a thread library for embedded.
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*
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* Chopstx is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Chopstx is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* As additional permission under GNU GPL version 3 section 7, you may
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* distribute non-source form of the Program without the copy of the
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* GNU GPL normally required by section 4, provided you inform the
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* recipients of GNU GPL by a written offer.
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*
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*/
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#include <mcu/stm32l.h>
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static void __attribute__((used))
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clock_init (void)
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{
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}
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static struct GPIO *const GPIO_LED = (struct GPIO *)GPIO_LED_BASE;
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#ifdef GPIO_USB_BASE
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static struct GPIO *const GPIO_USB = (struct GPIO *)GPIO_USB_BASE;
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#endif
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#ifdef GPIO_OTHER_BASE
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static struct GPIO *const GPIO_OTHER = (struct GPIO *)GPIO_OTHER_BASE;
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#endif
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static void __attribute__((used))
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gpio_init (void)
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{
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/* Enable GPIO clock. */
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/* LED is mandatory. We configure it always. */
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GPIO_LED->ODR = VAL_GPIO_LED_ODR;
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}
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130
mcu/stm32l.h
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130
mcu/stm32l.h
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#define PERIPH_BASE 0x40000000
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#define APB1PERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
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struct RCC {
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volatile uint32_t CR;
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volatile uint32_t ICSCR;
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volatile uint32_t CFGR;
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volatile uint32_t PLLCFGR;
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volatile uint32_t PLLSAI1CFGR;
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volatile uint32_t RESERVED;
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volatile uint32_t CIER;
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volatile uint32_t CIFR;
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volatile uint32_t CICR;
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volatile uint32_t RESERVED;
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volatile uint32_t AHB1RSTR;
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volatile uint32_t AHB2RSTR;
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volatile uint32_t AHB3RSTR;
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volatile uint32_t RESERVED;
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volatile uint32_t APB1RSTR1;
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volatile uint32_t APB1RSTR2;
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volatile uint32_t APB2RSTR;
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volatile uint32_t RESERVED;
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volatile uint32_t AHB1ENRR;
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volatile uint32_t AHB2ENRR;
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volatile uint32_t AHB3ENRR;
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volatile uint32_t RESERVED;
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volatile uint32_t APB1ENRR1;
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volatile uint32_t APB1ENRR2;
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volatile uint32_t APB2ENRR;
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volatile uint32_t RESERVED;
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volatile uint32_t AHB1SMENR;
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volatile uint32_t AHB2SMENR;
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volatile uint32_t AHB3SMENR;
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volatile uint32_t RESERVED;
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volatile uint32_t APB1SMENR1;
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volatile uint32_t APB1SMENR2;
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volatile uint32_t APB2SMENR;
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volatile uint32_t RESERVED;
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volatile uint32_t CCIPR;
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volatile uint32_t RESERVED;
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volatile uint32_t BDCR;
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volatile uint32_t CSR;
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volatile uint32_t CRRCR;
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volatile uint32_t CCIPR2;
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};
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#define RCC_BASE (AHB1PERIPH_BASE + 0x1000)
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static struct RCC *const RCC = (struct RCC *)RCC_BASE;
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struct PWR
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{
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t CR3;
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volatile uint32_t CR4;
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volatile uint32_t SR1;
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volatile uint32_t SR2;
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volatile uint32_t SCR;
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volatile uint32_t PUCRA;
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volatile uint32_t PDCRA;
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volatile uint32_t PUCRB;
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volatile uint32_t PDCRB;
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volatile uint32_t PUCRC;
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volatile uint32_t PDCRC;
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volatile uint32_t PUCRD;
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volatile uint32_t PDCRD;
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volatile uint32_t PUCRE;
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volatile uint32_t PDCRE;
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volatile uint32_t PUCRH;
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volatile uint32_t PDCRH;
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};
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static struct PWR *const PWR = ((struct PWR *)0x40007000);
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struct GPIO {
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volatile uint32_t MODER;
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volatile uint32_t OTYPER;
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volatile uint32_t OSPEEDR;
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volatile uint32_t PUPDR;
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volatile uint32_t IDR;
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volatile uint32_t ODR;
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volatile uint32_t BSRR;
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volatile uint32_t LCKR;
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volatile uint32_t AFRL;
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volatile uint32_t AFRH;
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volatile uint32_t BRR;
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};
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#define GPIOA_BASE (AHB2PERIPH_BASE)
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#define GPIOA ((struct GPIO *) GPIOA_BASE)
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#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
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#define GPIOB ((struct GPIO *) GPIOB_BASE)
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#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
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#define GPIOC ((struct GPIO *) GPIOC_BASE)
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#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
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#define GPIOD ((struct GPIO *) GPIOD_BASE)
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#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
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#define GPIOE ((struct GPIO *) GPIOE_BASE)
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#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00)
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#define GPIOH ((struct GPIO *) GPIOH_BASE)
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struct FLASH {
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volatile uint32_t ACR;
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volatile uint32_t PDKEYR;
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volatile uint32_t KEYR;
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volatile uint32_t OPTKEYR;
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volatile uint32_t SR;
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volatile uint32_t CR;
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volatile uint32_t ECCR;
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volatile uint32_t RESERVED;
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volatile uint32_t OPTR;
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volatile uint32_t PCROP1SR;
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volatile uint32_t PCROP1ER;
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volatile uint32_t WRP1AR;
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volatile uint32_t WRP1BR;
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};
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#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000)
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static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;
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