From 69a796087625c4c997e26b8750d51c4c92d83ab3 Mon Sep 17 00:00:00 2001 From: NIIBE Yutaka Date: Wed, 10 Apr 2019 12:39:07 +0900 Subject: [PATCH] Start experiment with STM32L432. --- board/board-st-nucleo-l432.h | 61 ++++++++++++++++ mcu/clk_gpio_init-stm32l.c | 51 ++++++++++++++ mcu/stm32l.h | 130 +++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 board/board-st-nucleo-l432.h create mode 100644 mcu/clk_gpio_init-stm32l.c create mode 100644 mcu/stm32l.h diff --git a/board/board-st-nucleo-l432.h b/board/board-st-nucleo-l432.h new file mode 100644 index 0000000..dad5947 --- /dev/null +++ b/board/board-st-nucleo-l432.h @@ -0,0 +1,61 @@ +#define BOARD_NAME "ST Nucleo L432" +#define BOARD_ID 0x3a8d5116 + +/* + * Please add USB cable to ST Nucleo L432. + * + * At CN4, connect USB cable, only when ST Link is not connected + * Vbus RED --> 4 + * + * At CN3, connect USB cable + * D- GREEN --> 13 PA11 + * D+ WHITE --> 5 PA12 + * GND BLACK --> 4 GND + */ + +#define MCU_STM32L4 1 + +#define RCC_HSICLK 48000000 + +#define GPIO_LED_BASE GPIOB_BASE +#define GPIO_LED_SET_TO_EMIT 3 +#undef GPIO_USB_BASE /* No external DISCONNECT/RENUM circuit. */ +#define GPIO_OTHER_BASE GPIOB_BASE + +/* + * Port A setup. + * PA0 - Input with pull-up USART2-CTS + * PA1 - Alternate function push pull output 2MHz USART2-RTS + * PA2 - Alternate function push pull output 2MHz USART2-TX + * PA3 - Input with pull-up USART2-RX + * PA4 - Alternate function push pull output 2MHz USART2-CK + * PA5 - Push pull output 2MHz (LED 1:ON 0:OFF) + * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) + * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP) + * ------------------------ Default + * PAx - input with pull-up + */ +#define VAL_GPIO_LED_ODR 0xFFFFE7FF + +/* + * Port B setup. + * PB0 - input with pull-up: AN8 for NeuG + * PB1 - input with pull-up: AN9 for NeuG + * --- + * --- + * PB4 - Input with pull-up: Card insertion detect: 0 when detected + * --- + * PB6 - Output push pull 2MHz: Vcc for card: default 0 + * --- + * PB8 - Output push pull 2MHz: Vpp for card: default 0 + * PB9 - Output push pull 2MHz: RST for card: default 0 + * PB10 - Alternate function open-drain output 50MHz USART3-TX + * PB11 - Input with pull-up USART3-RX + * PB12 - Alternate function push pull output 50MHz USART3-CK + * PB13 - Input with pull-up USART3-CTS + * PB14 - Alternate function push pull output 50MHz USART3-RTS + * --- + * ------------------------ Default + * PBx - input with pull-up. + */ +#define VAL_GPIO_OTHER_ODR 0xFFFFFCBF diff --git a/mcu/clk_gpio_init-stm32l.c b/mcu/clk_gpio_init-stm32l.c new file mode 100644 index 0000000..600149e --- /dev/null +++ b/mcu/clk_gpio_init-stm32l.c @@ -0,0 +1,51 @@ +/* + * clk_gpio_init-stm32l.c - Clock and GPIO initialization for STM32L. + * + * Copyright (C) 2019 Flying Stone Technology + * Author: NIIBE Yutaka + * + * This file is a part of Chopstx, a thread library for embedded. + * + * Chopstx is free software: you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Chopstx is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * As additional permission under GNU GPL version 3 section 7, you may + * distribute non-source form of the Program without the copy of the + * GNU GPL normally required by section 4, provided you inform the + * recipients of GNU GPL by a written offer. + * + */ + +#include + +static void __attribute__((used)) +clock_init (void) +{ +} + +static struct GPIO *const GPIO_LED = (struct GPIO *)GPIO_LED_BASE; +#ifdef GPIO_USB_BASE +static struct GPIO *const GPIO_USB = (struct GPIO *)GPIO_USB_BASE; +#endif +#ifdef GPIO_OTHER_BASE +static struct GPIO *const GPIO_OTHER = (struct GPIO *)GPIO_OTHER_BASE; +#endif + +static void __attribute__((used)) +gpio_init (void) +{ + /* Enable GPIO clock. */ + + /* LED is mandatory. We configure it always. */ + GPIO_LED->ODR = VAL_GPIO_LED_ODR; +} diff --git a/mcu/stm32l.h b/mcu/stm32l.h new file mode 100644 index 0000000..ece30d9 --- /dev/null +++ b/mcu/stm32l.h @@ -0,0 +1,130 @@ +#define PERIPH_BASE 0x40000000 +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) + +struct RCC { + volatile uint32_t CR; + volatile uint32_t ICSCR; + volatile uint32_t CFGR; + volatile uint32_t PLLCFGR; + + volatile uint32_t PLLSAI1CFGR; + volatile uint32_t RESERVED; + volatile uint32_t CIER; + volatile uint32_t CIFR; + + volatile uint32_t CICR; + volatile uint32_t RESERVED; + volatile uint32_t AHB1RSTR; + volatile uint32_t AHB2RSTR; + + volatile uint32_t AHB3RSTR; + volatile uint32_t RESERVED; + volatile uint32_t APB1RSTR1; + volatile uint32_t APB1RSTR2; + + volatile uint32_t APB2RSTR; + volatile uint32_t RESERVED; + volatile uint32_t AHB1ENRR; + volatile uint32_t AHB2ENRR; + + volatile uint32_t AHB3ENRR; + volatile uint32_t RESERVED; + volatile uint32_t APB1ENRR1; + volatile uint32_t APB1ENRR2; + + volatile uint32_t APB2ENRR; + volatile uint32_t RESERVED; + volatile uint32_t AHB1SMENR; + volatile uint32_t AHB2SMENR; + + volatile uint32_t AHB3SMENR; + volatile uint32_t RESERVED; + volatile uint32_t APB1SMENR1; + volatile uint32_t APB1SMENR2; + + volatile uint32_t APB2SMENR; + volatile uint32_t RESERVED; + volatile uint32_t CCIPR; + volatile uint32_t RESERVED; + + volatile uint32_t BDCR; + volatile uint32_t CSR; + volatile uint32_t CRRCR; + volatile uint32_t CCIPR2; +}; + +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000) +static struct RCC *const RCC = (struct RCC *)RCC_BASE; + +struct PWR +{ + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t CR3; + volatile uint32_t CR4; + volatile uint32_t SR1; + volatile uint32_t SR2; + volatile uint32_t SCR; + volatile uint32_t PUCRA; + volatile uint32_t PDCRA; + volatile uint32_t PUCRB; + volatile uint32_t PDCRB; + volatile uint32_t PUCRC; + volatile uint32_t PDCRC; + volatile uint32_t PUCRD; + volatile uint32_t PDCRD; + volatile uint32_t PUCRE; + volatile uint32_t PDCRE; + volatile uint32_t PUCRH; + volatile uint32_t PDCRH; +}; +static struct PWR *const PWR = ((struct PWR *)0x40007000); + +struct GPIO { + volatile uint32_t MODER; + volatile uint32_t OTYPER; + volatile uint32_t OSPEEDR; + volatile uint32_t PUPDR; + volatile uint32_t IDR; + volatile uint32_t ODR; + volatile uint32_t BSRR; + volatile uint32_t LCKR; + volatile uint32_t AFRL; + volatile uint32_t AFRH; + volatile uint32_t BRR; +}; + +#define GPIOA_BASE (AHB2PERIPH_BASE) +#define GPIOA ((struct GPIO *) GPIOA_BASE) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400) +#define GPIOB ((struct GPIO *) GPIOB_BASE) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800) +#define GPIOC ((struct GPIO *) GPIOC_BASE) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00) +#define GPIOD ((struct GPIO *) GPIOD_BASE) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000) +#define GPIOE ((struct GPIO *) GPIOE_BASE) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00) +#define GPIOH ((struct GPIO *) GPIOH_BASE) + +struct FLASH { + volatile uint32_t ACR; + volatile uint32_t PDKEYR; + volatile uint32_t KEYR; + volatile uint32_t OPTKEYR; + volatile uint32_t SR; + volatile uint32_t CR; + volatile uint32_t ECCR; + volatile uint32_t RESERVED; + volatile uint32_t OPTR; + volatile uint32_t PCROP1SR; + volatile uint32_t PCROP1ER; + volatile uint32_t WRP1AR; + volatile uint32_t WRP1BR; +}; + +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000) +static struct FLASH *const FLASH = (struct FLASH *)FLASH_R_BASE;