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More clean up.

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This commit is contained in:
NIIBE Yutaka
2017-11-17 14:55:59 +09:00
parent a362f32cdd
commit 14cb38e56f
3 changed files with 36 additions and 24 deletions
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5
ChangeLog
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@@ -1,6 +1,9 @@
2017-11-17 NIIBE Yutaka <gniibe@fsij.org> 2017-11-17 NIIBE Yutaka <gniibe@fsij.org>
* mcu/stm32f103.h (RCC), clk_gpio_init-stm32.c (RCC): Move to... * mcu/clk_gpio_init-stm32.c (STM32_*): Move to...
* mcu/stm32.h (STM32_*): ... this header file.
* mcu/stm32f103.h, mcu/clk_gpio_init-stm32.c (RCC): Move to...
* mcu/stm32.h (RCC): ... this header file. * mcu/stm32.h (RCC): ... this header file.
* example-fsm-55: Update for new sleep API. * example-fsm-55: Update for new sleep API.

23
mcu/clk_gpio_init-stm32.c
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@@ -28,29 +28,6 @@
#include <mcu/stm32.h> #include <mcu/stm32.h>
#define STM32_SW_HSI (0 << 0)
#define STM32_SW_PLL (2 << 0)
#define STM32_PLLSRC_HSI (0 << 16)
#define STM32_PLLSRC_HSE (1 << 16)
#define STM32_PLLXTPRE_DIV1 (0 << 17)
#define STM32_PLLXTPRE_DIV2 (1 << 17)
#define STM32_HPRE_DIV1 (0 << 4)
#define STM32_PPRE1_DIV1 (0 << 8)
#define STM32_PPRE1_DIV2 (4 << 8)
#define STM32_PPRE2_DIV1 (0 << 11)
#define STM32_PPRE2_DIV2 (4 << 11)
#define STM32_ADCPRE_DIV4 (1 << 14)
#define STM32_ADCPRE_DIV6 (2 << 14)
#define STM32_USBPRE_DIV1P5 (0 << 22)
#define STM32_MCO_NOCLOCK (0 << 24)
#if defined(MCU_STM32F0) #if defined(MCU_STM32F0)
#define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PLLSRC STM32_PLLSRC_HSI #define STM32_PLLSRC STM32_PLLSRC_HSI

32
mcu/stm32.h
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@@ -97,6 +97,38 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE;
#define RCC_CFGR_SW_MASK (3 << 0) #define RCC_CFGR_SW_MASK (3 << 0)
#define RCC_CFGR_SWS 0x0000000C #define RCC_CFGR_SWS 0x0000000C
/* Clock setting values.
* Due to historical reason, it has the prefix of STM32_.
*/
#define STM32_SW_HSI (0 << 0)
#define STM32_SW_HSE (1 << 0)
#define STM32_SW_PLL (2 << 0)
#define STM32_PLLSRC_HSI (0 << 16)
#define STM32_PLLSRC_HSE (1 << 16)
#define STM32_PLLXTPRE_DIV1 (0 << 17)
#define STM32_PLLXTPRE_DIV2 (1 << 17)
#define STM32_HPRE_DIV1 (0 << 4)
#define STM32_HPRE_DIV8 (10 << 4)
#define STM32_HPRE_DIV16 (11 << 4)
#define STM32_PPRE1_DIV1 (0 << 8)
#define STM32_PPRE1_DIV2 (4 << 8)
#define STM32_PPRE1_DIV16 (7 << 8)
#define STM32_PPRE2_DIV1 (0 << 11)
#define STM32_PPRE2_DIV2 (4 << 11)
#define STM32_PPRE2_DIV16 (7 << 11)
#define STM32_ADCPRE_DIV4 (1 << 14)
#define STM32_ADCPRE_DIV6 (2 << 14)
#define STM32_ADCPRE_DIV8 (3 << 14)
#define STM32_USBPRE_DIV1P5 (0 << 22)
#define STM32_MCO_NOCLOCK (0 << 24)
struct PWR struct PWR
{ {