142 lines
4.0 KiB
C
142 lines
4.0 KiB
C
#define PERIPH_BASE 0x40000000
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#define APBPERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
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struct RCC {
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volatile uint32_t CR;
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volatile uint32_t CFGR;
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volatile uint32_t CIR;
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volatile uint32_t APB2RSTR;
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volatile uint32_t APB1RSTR;
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volatile uint32_t AHBENR;
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volatile uint32_t APB2ENR;
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volatile uint32_t APB1ENR;
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volatile uint32_t BDCR;
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volatile uint32_t CSR;
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#if defined(MCU_STM32F0)
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volatile uint32_t AHBRSTR;
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volatile uint32_t CFGR2;
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volatile uint32_t CFGR3;
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volatile uint32_t CR2;
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#endif
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};
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#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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static struct RCC *const RCC = (struct RCC *)RCC_BASE;
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#define RCC_APB1ENR_USBEN 0x00800000
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#define RCC_APB1RSTR_USBRST 0x00800000
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#define RCC_CR_HSION 0x00000001
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#define RCC_CR_HSIRDY 0x00000002
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#define RCC_CR_HSITRIM 0x000000F8
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#define RCC_CR_HSEON 0x00010000
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#define RCC_CR_HSERDY 0x00020000
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#define RCC_CR_PLLON 0x01000000
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#define RCC_CR_PLLRDY 0x02000000
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#define RCC_CFGR_SWS 0x0000000C
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#define RCC_CFGR_SWS_HSI 0x00000000
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#define RCC_AHBENR_DMA1EN 0x00000001
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#define RCC_AHBENR_CRCEN 0x00000040
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#if defined(MCU_STM32F0)
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#define RCC_AHBRSTR_IOPARST 0x00020000
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#define RCC_AHBRSTR_IOPBRST 0x00040000
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#define RCC_AHBRSTR_IOPCRST 0x00080000
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#define RCC_AHBRSTR_IOPDRST 0x00100000
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#define RCC_AHBRSTR_IOPFRST 0x00400000
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#define RCC_AHBENR_IOPAEN 0x00020000
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#define RCC_AHBENR_IOPBEN 0x00040000
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#define RCC_AHBENR_IOPCEN 0x00080000
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#define RCC_AHBENR_IOPDEN 0x00100000
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#define RCC_AHBENR_IOPFEN 0x00400000
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#define RCC_APB2RSTR_SYSCFGRST 0x00000001
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#define RCC_APB2ENR_SYSCFGEN 0x00000001
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#else
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#define RCC_APB2ENR_ADC1EN 0x00000200
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#define RCC_APB2ENR_ADC2EN 0x00000400
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#define RCC_APB2ENR_TIM1EN 0x00000800
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#define RCC_APB1ENR_TIM2EN 0x00000001
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#define RCC_APB1ENR_TIM3EN 0x00000002
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#define RCC_APB1ENR_TIM4EN 0x00000004
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#define RCC_APB2RSTR_ADC1RST 0x00000200
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#define RCC_APB2RSTR_ADC2RST 0x00000400
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#define RCC_APB2RSTR_TIM1RST 0x00000800
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#define RCC_APB1RSTR_TIM2RST 0x00000001
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#define RCC_APB1RSTR_TIM3RST 0x00000002
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#define RCC_APB1RSTR_TIM4RST 0x00000004
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#define RCC_APB2RSTR_AFIORST 0x00000001
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#define RCC_APB2RSTR_IOPARST 0x00000004
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#define RCC_APB2RSTR_IOPBRST 0x00000008
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#define RCC_APB2RSTR_IOPCRST 0x00000010
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#define RCC_APB2RSTR_IOPDRST 0x00000020
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#define RCC_APB2RSTR_IOPERST 0x00000040
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#define RCC_APB2RSTR_IOPFRST 0x00000080
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#define RCC_APB2RSTR_IOPGRST 0x00000100
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#define RCC_APB2ENR_AFIOEN 0x00000001
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#define RCC_APB2ENR_IOPAEN 0x00000004
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#define RCC_APB2ENR_IOPBEN 0x00000008
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#define RCC_APB2ENR_IOPCEN 0x00000010
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#define RCC_APB2ENR_IOPDEN 0x00000020
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#define RCC_APB2ENR_IOPEEN 0x00000040
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#define RCC_APB2ENR_IOPFEN 0x00000080
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#define RCC_APB2ENR_IOPGEN 0x00000100
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#endif
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#define RCC_CFGR_SW_HCI (0 << 0)
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#define RCC_CFGR_SW_PLL (2 << 0)
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#define RCC_CFGR_SW_MASK (3 << 0)
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#define RCC_CFGR_SWS 0x0000000C
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/* Clock setting values.
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* Due to historical reason, it has the prefix of STM32_.
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*/
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#define STM32_SW_HSI (0 << 0)
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#define STM32_SW_HSE (1 << 0)
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#define STM32_SW_PLL (2 << 0)
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#define STM32_PLLSRC_HSI (0 << 16)
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#define STM32_PLLSRC_HSE (1 << 16)
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#define STM32_PLLXTPRE_DIV1 (0 << 17)
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#define STM32_PLLXTPRE_DIV2 (1 << 17)
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#define STM32_HPRE_DIV1 (0 << 4)
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#define STM32_HPRE_DIV8 (10 << 4)
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#define STM32_HPRE_DIV16 (11 << 4)
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#define STM32_PPRE1_DIV1 (0 << 8)
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#define STM32_PPRE1_DIV2 (4 << 8)
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#define STM32_PPRE1_DIV16 (7 << 8)
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#define STM32_PPRE2_DIV1 (0 << 11)
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#define STM32_PPRE2_DIV2 (4 << 11)
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#define STM32_PPRE2_DIV16 (7 << 11)
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#define STM32_ADCPRE_DIV4 (1 << 14)
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#define STM32_ADCPRE_DIV6 (2 << 14)
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#define STM32_ADCPRE_DIV8 (3 << 14)
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#define STM32_USBPRE_DIV1P5 (0 << 22)
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#define STM32_MCO_NOCLOCK (0 << 24)
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struct PWR
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{
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volatile uint32_t CR;
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volatile uint32_t CSR;
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};
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static struct PWR *const PWR = ((struct PWR *)0x40007000);
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#define PWR_CR_LPDS 0x0001 /* Low-power deepsleep */
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#define PWR_CR_PDDS 0x0002 /* Power down deepsleep */
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#define PWR_CR_CWUF 0x0004 /* Clear wakeup flag */
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