PowerPC [Ports]

Collaboration diagram for PowerPC:

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Description

PowerPC port details. This section describes how the ChibiOS/RT features are implemented on this architecture.

Mapping of the System States in the PowerPC port

The ChibiOS/RT logical System States are mapped as follow in the PowerPC port:

• Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated.
• Normal. This is the state the system has after executing chSysInit(). Interrupts are enabled.
• Suspended. Interrupts are disabled.
• Disabled. Interrupts are disabled. This state is equivalent to the Suspended state because there are no fast interrupts in this architecture.
• Sleep. This state is entered with the execution of the specific instruction wait.
• S-Locked. Interrupts are disabled.
• I-Locked. This state is equivalent to the SRI state, the chSysLockI() and chSysUnlockI() APIs do nothing (still use them in order to formally change state because this may change).
• Serving Regular Interrupt. Normal interrupt service code.
• Serving Fast Interrupt. Not present in this architecture.
• Serving Non-Maskable Interrupt. The PowerPC has several non maskable interrupt sources that can be associated to this state.
• Halted. Implemented as an infinite loop with interrupts disabled.

The PowerPC port notes

The PowerPC port is organized as follow:

• The main() function is invoked in privileged mode.
• Each thread has a private stack with extra storage for interrupts servicing.
• The Book-E Decrementer Timer, mapped on IVOR10, is used for system tick.
• Interrupt nesting is not currently supported.

Modules
	Configuration Options
	PowerPC Configuration Options.
	Core Port Implementation
	PowerPC specific port code, structures and macros.
	Startup Support
	PPC startup code support.
	SPC563 Drivers
	Device drivers included in the SPC563 support.