diff --git a/ChangeLog b/ChangeLog index cf99f94..b3367b1 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,7 @@ +2013-02-19 Niibe Yutaka + + * ChibiOS_2.0.8: Remove. + 2013-02-18 Niibe Yutaka Changes for new ChibiOS/RT. diff --git a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.c b/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.c deleted file mode 100644 index 52fdac9..0000000 --- a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - lpc111x_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * Extra, board-specific, initializations. - * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG - * you must comment that line first. - */ - LPC_IOCON->PIO0_7 = 0xC0; /* Disables pull-up on LED2 output. */ - LPC_IOCON->JTAG_nTRST_PIO1_2 = 0xC1; /* Disables pull-up on LED3B output - and makes it GPIO1_2. */ - LPC_IOCON->PIO1_9 = 0xC0; /* Disables pull-up on LED3R output.*/ - LPC_IOCON->PIO1_10 = 0xC0; /* Disables pull-up on LED3G output.*/ - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.h b/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.h deleted file mode 100644 index 1b725e7..0000000 --- a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter - * board. - */ - -/* - * Board identifiers. - */ -#define BOARD_EA_BB_LPC1114 -#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1114" - -/* - * Board frequencies. - */ -#define SYSOSCCLK 12000000 - -/* - * GPIO 0 initial setup. - * Bit7 - LPCxpresso LED, initially output at low level. - */ -#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_LED2) -#define VAL_GPIO0DATA 0x00000000 - -/* - * GPIO 1 initial setup. - */ -#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_LED3B) | \ - PAL_PORT_BIT(GPIO1_LED3R) | \ - PAL_PORT_BIT(GPIO1_LED3G) -#define VAL_GPIO1DATA 0x00000000 - -/* - * GPIO 2 initial setup. - */ -#define VAL_GPIO2DIR 0x00000000 -#define VAL_GPIO2DATA 0x00000000 - -/* - * GPIO 3 initial setup. - */ -#define VAL_GPIO3DIR 0x00000000 -#define VAL_GPIO3DATA 0x00000000 - -/* - * Pin definitions. - */ -#define GPIO0_SW3 1 -#define GPIO0_LED2 7 - -#define GPIO1_LED3B 2 -#define GPIO1_SW4 4 -#define GPIO1_LED3R 9 -#define GPIO1_LED3G 10 - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.mk b/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.mk deleted file mode 100644 index 377aea0..0000000 --- a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1114/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1114/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1114 diff --git a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.c b/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.c deleted file mode 100644 index a680095..0000000 --- a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - LPC13xx_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * Extra, board-specific, initializations. - * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG - * you must comment that line first. - */ - LPC_IOCON->PIO0_7 = 0xC0; /* Disables pull-up on LED2 output. */ - LPC_IOCON->JTAG_nTRST_PIO1_2 = 0xC1; /* Disables pull-up on LED3B output - and makes it GPIO1_2. */ - LPC_IOCON->PIO1_9 = 0xC0; /* Disables pull-up on LED3R output.*/ - LPC_IOCON->PIO1_10 = 0xC0; /* Disables pull-up on LED3G output.*/ - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.h b/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.h deleted file mode 100644 index 0e596e6..0000000 --- a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for Embedded Artists LPCXpresso Base Board with LPC1343 daughter - * board. - */ - -/* - * Board identifiers. - */ -#define BOARD_EA_BB_LPC1343 -#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1343" - -/* - * Board frequencies. - */ -#define SYSOSCCLK 12000000 - -/* - * GPIO 0 initial setup. - * Bit7 - LPCxpresso LED, initially output at low level. - */ -#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_LED2) -#define VAL_GPIO0DATA 0x00000000 - -/* - * GPIO 1 initial setup. - */ -#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_LED3B) | \ - PAL_PORT_BIT(GPIO1_LED3R) | \ - PAL_PORT_BIT(GPIO1_LED3G) -#define VAL_GPIO1DATA 0x00000000 - -/* - * GPIO 2 initial setup. - */ -#define VAL_GPIO2DIR 0x00000000 -#define VAL_GPIO2DATA 0x00000000 - -/* - * GPIO 3 initial setup. - */ -#define VAL_GPIO3DIR 0x00000000 -#define VAL_GPIO3DATA 0x00000000 - -/* - * Pin definitions. - */ -#define GPIO0_SW3 1 -#define GPIO0_LED2 7 - -#define GPIO1_LED3B 2 -#define GPIO1_SW4 4 -#define GPIO1_LED3R 9 -#define GPIO1_LED3G 10 - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.mk b/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.mk deleted file mode 100644 index 22fb23e..0000000 --- a/ChibiOS_2.0.8/boards/EA_LPCXPRESSO_BB_1343/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1343/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1343 diff --git a/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.c b/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.c deleted file mode 100644 index 5887dc7..0000000 --- a/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - spc563_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * Various initialization (temporary code). - */ - SIU.PCR[GPIO_LED1].R = 0x0300; /* OBE | IBE. */ - SIU.PCR[GPIO_LED2].R = 0x0300; /* OBE | IBE. */ - SIU.PCR[GPIO_LED3].R = 0x0300; /* OBE | IBE. */ - SIU.PCR[GPIO_LED4].R = 0x0300; /* OBE | IBE. */ - SIU.PCR[GPIO_BUTTON1].R = 0x0100; /* IBE. */ - SIU.PCR[GPIO_BUTTON2].R = 0x0100; /* IBE. */ - SIU.PCR[GPIO_BUTTON3].R = 0x0100; /* IBE. */ - SIU.PCR[GPIO_BUTTON4].R = 0x0100; /* IBE. */ - SIU.PCR[GPIO_SCI_A_TX].R = 0x0500; /* Primary | IBE. */ - SIU.PCR[GPIO_SCI_A_RX].R = 0x0500; /* Primary | IBE. */ - - /* - * HAL initialization. - */ - halInit(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.h b/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.h deleted file mode 100644 index 26490c7..0000000 --- a/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for a generic SPC563 proto board. - */ - -/* - * Board identifiers. - */ -#define BOARD_GENERIC_SPC563 -#define BOARD_NAME "Generic SPC563" - -/* - * Board frequencies. - */ -#if !defined(EXTCLK) -#define EXTCLK 8000000 -#endif - -/* - * I/O definitions. - */ -#define GPIO_SCI_A_TX 89 -#define GPIO_SCI_A_RX 90 - -#define GPIO_BUTTON1 179 -#define GPIO_BUTTON2 181 -#define GPIO_BUTTON3 183 -#define GPIO_BUTTON4 187 - -#define GPIO_LED1 188 -#define GPIO_LED2 189 -#define GPIO_LED3 190 -#define GPIO_LED4 191 - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit0(void); - void hwinit1(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.mk b/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.mk deleted file mode 100644 index 3925456..0000000 --- a/ChibiOS_2.0.8/boards/GENERIC_SPC563/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/GENERIC_SPC563/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/GENERIC_SPC563 diff --git a/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.c b/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.c deleted file mode 100644 index 3a1f690..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -CH_IRQ_HANDLER(TIMER0_COMP_vect) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/* - * Board initialization code. - */ -void hwinit(void) { - - /* - * I/O ports setup. - */ - DDRA = VAL_DDRA; - PORTA = VAL_PORTA; - DDRB = VAL_DDRB; - PORTB = VAL_PORTB; - DDRC = VAL_DDRC; - PORTC = VAL_PORTC; - DDRD = VAL_DDRD; - PORTD = VAL_PORTD; - DDRE = VAL_DDRE; - PORTE = VAL_PORTE; - DDRF = VAL_DDRF; - PORTF = VAL_PORTF; - DDRG = VAL_DDRG; - PORTG = VAL_PORTG; - - /* - * External interrupts setup, all disabled initially. - */ - EICRA = 0x00; - EICRB = 0x00; - EIMSK = 0x00; - - /* - * Enables Idle mode for SLEEP instruction. - */ - SMCR = (1 << SE); - - /* - * Timer 0 setup. - */ - TCCR0A = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ - (0 << COM0A1) | (0 << COM0A0) | /* OC0A disabled. */ - (0 << CS02) | (1 << CS01) | (1 << CS00); /* CLK/64 clock. */ - OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; - TCNT0 = 0; /* Reset counter. */ - TIFR0 = (1 << OCF0A); /* Reset pending. */ - TIMSK0 = (1 << OCIE0A); /* IRQ on compare. */ - - /* - * HAL initialization. - */ - halInit(); -} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.h b/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.h deleted file mode 100644 index 4f49030..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the Olimex AVR-CAN proto board. - */ - -/* - * Board identifier. - */ -#define BOARD_OLIMEX_AVR_CAN -#define BOARD_NAME "Olimex AVR-CAN" - -/* - * All inputs with pullups. - */ -#define VAL_DDRA 0x00 -#define VAL_PORTA 0xFF - -/* - * All inputs with pullups. - */ -#define VAL_DDRB 0x00 -#define VAL_PORTB 0xFF - -/* - * All inputs with pullups. - */ -#define VAL_DDRC 0x00 -#define VAL_PORTC 0xFF - -/* PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 - * IN IN OUT IN OUT IN IN IN - * DDRD 0 0 1 0 1 0 0 0 - * PU HiZ VAL PU VAL HiZ HiZ HiZ - * PORTD 1 0 ?1 1 1 0 0 0 - */ -#define VAL_DDRD 0x28 -#define VAL_PORTD 0xB8 - -/* PE7 PE6 BUT LED PE3 PE2 PE1 PE0 - * IN IN IN OUT IN IN OUT IN - * DDRE 0 0 0 1 0 0 1 0 - * PU PU HiZ VAL PU PU VAL HiZ - * PORTE 1 1 0 1 1 1 1 0 - */ -#define VAL_DDRE 0x12 -#define VAL_PORTE 0xDE - -/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 - * x x x x IN IN IN IN - * DDRF 0 0 0 0 0 0 0 0 - * x x x x PU PU PU PU - * PORTF 0 0 0 0 1 1 1 1 - * - */ -#define VAL_DDRF 0x00 -#define VAL_PORTF 0x0F - -/* x x x x x PG2 PG1 PG0 - * x x x x x IN IN IN - * DDRG 0 0 0 0 0 0 0 0 - * x x x x x PU PU PU - * PORTG 0 0 0 0 0 1 1 1 - * - */ -#define VAL_DDRG 0x00 -#define VAL_PORTG 0x07 - -#define PORTE_LED (1 << 4) -#define PORTE_BUTTON (1 << 5) - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.mk b/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.mk deleted file mode 100644 index 3abf0f6..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_AVR_CAN/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/OLIMEX_AVR_CAN/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/OLIMEX_AVR_CAN diff --git a/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.c b/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.c deleted file mode 100644 index f967f72..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -CH_IRQ_HANDLER(TIMER0_COMP_vect) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/* - * Board initialization code. - */ -void hwinit(void) { - - /* - * I/O ports setup. - */ - DDRA = VAL_DDRA; - PORTA = VAL_PORTA; - DDRB = VAL_DDRB; - PORTB = VAL_PORTB; - DDRC = VAL_DDRC; - PORTC = VAL_PORTC; - DDRD = VAL_DDRD; - PORTD = VAL_PORTD; - DDRE = VAL_DDRE; - PORTE = VAL_PORTE; - DDRF = VAL_DDRF; - PORTF = VAL_PORTF; - DDRG = VAL_DDRG; - PORTG = VAL_PORTG; - - /* - * External interrupts setup, all disabled initially. - */ - EICRA = 0x00; - EICRB = 0x00; - EIMSK = 0x00; - - /* - * Enables Idle mode for SLEEP instruction. - */ - MCUCR = (1 << SE); - - /* - * Timer 0 setup. - */ - TCCR0 = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ - (0 << COM01) | (0 << COM00) | /* OC0A disabled. */ - (1 << CS02) | (0 << CS01) | (0 << CS00); /* CLK/64 clock. */ - OCR0 = F_CPU / 64 / CH_FREQUENCY - 1; - TCNT0 = 0; /* Reset counter. */ - TIFR = (1 << OCF0); /* Reset pending. */ - TIMSK = (1 << OCIE0); /* IRQ on compare. */ - - /* - * HAL initialization. - */ - halInit(); -} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.h b/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.h deleted file mode 100644 index 8e35a76..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the Olimex AVR-MT-128 proto board. - */ - -/* - * Board identifier. - */ -#define BOARD_OLIMEX_AVR_MT_128 -#define BOARD_NAME "Olimex AVR-MT-128" - -/* PA7 RLY DS B5 B4 B3 B2 B1 - * IN OUT IN IN IN IN IN IN - * DDRA 0 1 0 0 0 0 0 0 - * PU VAL HiZ HiZ HiZ HiZ HiZ HiZ - * PORTA 1 0 0 0 0 0 0 0 - */ -#define VAL_DDRA 0x40 -#define VAL_PORTA 0x80 - -/* - * All inputs with pullups. - */ -#define VAL_DDRB 0x00 -#define VAL_PORTB 0xFF - -/* D7 D6 D5 D4 PC3 E R/W RS - * OUT OUT OUT OUT IN OUT OUT OUT - * DDRC 1 1 1 1 0 1 1 1 - * PU PU PU PU PU VAL VAL VAL - * PORTC 0 0 0 0 1 0 0 0 - */ -#define VAL_DDRC 0xF7 -#define VAL_PORTC 0x08 - -/* PD7 PD6 PD5 PD4 TXD RXD PD1 PD0 - * IN IN IN IN OUT IN IN IN - * DDRD 0 0 0 0 1 0 0 0 - * PU PU PU PU VAL HiZ PU PU - * PORTD 1 1 1 1 1 0 1 1 - */ -#define VAL_DDRD 0x08 -#define VAL_PORTD 0xFB - -/* PE7 PE6 BZ2 BZ2 PE3 PE2 PE1 PE0 - * IN IN OUT OUT IN IN OUT IN - * DDRE 0 0 1 1 0 0 1 0 - * PU PU VAL VAL PU PU VAL PU - * PORTE 1 1 1 1 1 1 1 1 - */ -#define VAL_DDRE 0x32 -#define VAL_PORTE 0xFF - -/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 - * x x x x IN IN IN IN - * DDRF 0 0 0 0 0 0 0 0 - * x x x x PU PU PU PU - * PORTF 0 0 0 0 1 1 1 1 - * - */ -#define VAL_DDRF 0x00 -#define VAL_PORTF 0x0F - -/* x x x x x PG2 PG1 PG0 - * x x x x x IN IN IN - * DDRG 0 0 0 0 0 0 0 0 - * x x x x x PU PU PU - * PORTG 0 0 0 0 0 1 1 1 - * - */ -#define VAL_DDRG 0x00 -#define VAL_PORTG 0x07 - -#define PORTA_BUTTON1 (1 << 0) -#define PORTA_BUTTON2 (1 << 1) -#define PORTA_BUTTON3 (1 << 2) -#define PORTA_BUTTON4 (1 << 3) -#define PORTA_BUTTON5 (1 << 4) -#define PORTA_DALLAS (1 << 5) -#define PORTA_RELAY (1 << 6) - -#define PORTC_44780_RS (1 << 0) -#define PORTC_44780_RW (1 << 1) -#define PORTC_44780_E (1 << 2) -#define PORTC_44780_D4 (1 << 4) -#define PORTC_44780_D5 (1 << 5) -#define PORTC_44780_D6 (1 << 6) -#define PORTC_44780_D7 (1 << 7) -#define PORTC_44780_DATA (PORTC_44780_D4 | PORTC_44780_D5 | \ - PORTC_44780_D6 | PORTC_44780_D7) - -#define PORTE_BUZZ1 (1 << 4) -#define PORTE_BUZZ2 (1 << 5) - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.mk b/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.mk deleted file mode 100644 index 71b16ae..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_AVR_MT_128/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/OLIMEX_AVR_MT_128/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/OLIMEX_AVR_MT_128 diff --git a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.c b/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.c deleted file mode 100644 index e25467f..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -#define VAL_TC0_PRESCALER 0 - -/* - * Timer 0 IRQ handling here. - */ -static CH_IRQ_HANDLER(T0IrqHandler) { - - CH_IRQ_PROLOGUE(); - T0IR = 1; /* Clear interrupt on match MR0. */ - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - VICVectAddr = 0; - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - lpc214x_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * System Timer initialization, 1ms intervals. - */ - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); - VICIntEnable = INTMASK(SOURCE_Timer0); - TC *timer = T0Base; - timer->TC_PR = VAL_TC0_PRESCALER; - timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); - timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ - timer->TC_TCR = 2; /* Reset counter and prescaler. */ - timer->TC_TCR = 1; /* Timer enabled. */ - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.h b/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.h deleted file mode 100644 index c089c55..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the Olimex LPC-P2148 proto board. - */ - -/* - * Board identifier. - */ -#define BOARD_OLIMEX_LPC_P2148 -#define BOARD_NAME "Olimex LPC-P2148" - -/* - * The following values are implementation dependent. You may change them in - * order to match your HW. - */ -#define FOSC 12000000 -#define CCLK 48000000 -#define PCLK 12000000 - -/* - * Pins configuration for Olimex LPC-P2148. - * - * PINSEL0 - * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD - * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 - * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 - * FIO0DIR (15...0) - * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- - * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - * - * PINSEL1 - * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 - * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 - * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 - * FIO0DIR (31...16) - * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN - * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 - * - * FIO1DIR (31...16) - * -- -- -- -- -- IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT - * 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 - */ -#define VAL_PINSEL0 0x00055555 -#define VAL_PINSEL1 0x100840A8 -#define VAL_PINSEL2 0x00000004 /* Do not modify */ -#define VAL_FIO0DIR 0xB0703C00 -#define VAL_FIO1DIR 0x01FF0000 -#define VAL_FIO0PIN 0xFFFFFFFF -#define VAL_FIO1PIN 0xFFFFFFFF - -#define PA_LED1 10 -#define PA_LED2 11 -#define PA_BUZZ1 12 -#define PA_BUZZ2 13 -#define PA_BSL 14 -#define PA_BUTTON1 15 -#define PA_BUTTON2 16 -#define PA_SSEL1 20 -#define PA_LEDUSB 31 - -#define PB_WP1 24 -#define PB_CP1 25 - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.mk b/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.mk deleted file mode 100644 index ceb075f..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/board.mk +++ /dev/null @@ -1,8 +0,0 @@ -# Board directory path -BOARDPATH = ${CHIBIOS}/boards/OLIMEX_LPC_P2148/ - -# List of all the mandatory board related files. -BOARDSRC = ${BOARDPATH}/board.c - -# Required include directories -BOARDINC = ${BOARDPATH} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/buzzer.c b/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/buzzer.c deleted file mode 100644 index 92d8310..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/buzzer.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * Buzzer driver for Olimex LPC-P2148. - * Uses the timer 1 for wave generation and a Virtual Timer for the sound - * duration. - * The driver also generates an event when the sound is done and the buzzer - * goes silent. - */ - -#include "ch.h" -#include "hal.h" - -#include "buzzer.h" - -EventSource BuzzerSilentEventSource; - -#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1) -#define StopCounter(t) ((t)->TC_EMR = 0, (t)->TC_TCR = 2) - -/** - * @brief Buzzer driver initialization. - */ -void buzzInit(void) { - - chEvtInit(&BuzzerSilentEventSource); - - /* - * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions. - * Enables Timer1 clock. - */ - PINSEL0 &= 0xF0FFFFFF; - PINSEL0 |= 0x0A000000; - PCONP = (PCONP & PCALL) | PCTIM1; - - /* - * Timer setup. - */ - TC *tc = T1Base; - StopCounter(tc); - tc->TC_CTCR = 0; /* Clock source is PCLK. */ - tc->TC_PR = 0; /* Prescaler disabled. */ - tc->TC_MCR = 2; /* Clear TC on match MR0. */ -} - -/** - * @brief Stops the sound. - * - * @param[in] p pointer to the timer - */ -static void stop(void *p) { - - StopCounter((TC *)p); - chEvtBroadcastI(&BuzzerSilentEventSource); -} - -/** - * @brief Plays a tone asynchronously. - * - * @param[in] freq approximated tone frequency - * @param[in] duration tone duration in systicks - */ -void buzzPlay(uint32_t freq, systime_t duration) { - static VirtualTimer bvt; - TC *tc = T1Base; - - chSysLock(); - - if (chVTIsArmedI(&bvt)) { /* If a sound is already being */ - chVTResetI(&bvt); /* played then aborts it. */ - StopCounter(tc); - } - - tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); - StartCounter(tc); - chVTSetI(&bvt, duration, stop, tc); - - chSysUnlock(); -} - -/** - * @brief Plays a tone. - * - * @param[in] freq approximated tone frequency - * @param[in] duration tone duration in systicks - */ -void buzzPlayWait(uint32_t freq, systime_t duration) { - TC *tc = T1Base; - - StopCounter(tc); - tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); - StartCounter(tc); - chThdSleep(duration); - StopCounter(tc); -} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/buzzer.h b/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/buzzer.h deleted file mode 100644 index ec2a3b6..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_LPC_P2148/buzzer.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BUZZER_H_ -#define _BUZZER_H_ - -#ifdef __cplusplus -extern "C" { -#endif - void buzzInit(void); - void buzzPlay(uint32_t freq, systime_t duration); - void buzzPlayWait(uint32_t freq, systime_t duration); -#ifdef __cplusplus -} -#endif - -extern EventSource BuzzerSilentEventSource; - -#endif /* _BUZZER_H_ */ diff --git a/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.c b/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.c deleted file mode 100644 index 7a60ea8..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include - -#include "ch.h" -#include "hal.h" - -CH_IRQ_HANDLER(TIMERA0_VECTOR) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. - */ -void hwinit(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * Timer 0 setup, uses SMCLK as source. - */ - TACCR0 = SMCLK / 4 / CH_FREQUENCY - 1;/* Counter limit. */ - TACTL = TACLR; /* Clean start. */ - TACTL = TASSEL_2 | ID_2 | MC_1; /* Src=SMCLK, ID=4, cmp=TACCR0. */ - TACCTL0 = CCIE; /* Interrupt on compare. */ -} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.h b/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.h deleted file mode 100644 index 8489dff..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the Olimex MSP430-P1611 proto board. - */ - -/* - * Board identifier. - */ -#define BOARD_OLIMEX_MSP430_P1611 -#define BOARD_NAME "Olimex MSP430-P1611" - -/* - * Clock constants. - */ -#define LFXT1CLK 32768 -#define XT2CLK 8000000 -#define DCOCLK 750000 - -/* - * Pin definitions for the Olimex MSP430-P1611 board. - */ -#define P3_O_TXD0 4 -#define P3_O_TXD0_MASK (1 << P3_O_TXD0) -#define P3_I_RXD0 5 -#define P3_I_RXD0_MASK (1 << P3_I_RXD0) -#define P6_O_LED 0 -#define P6_O_LED_MASK (1 << P6_O_LED) -#define P6_I_BUTTON 1 -#define P6_I_BUTTON_MASK (1 << P6_I_BUTTON) - -/* - * Initial I/O ports settings. - */ -#define VAL_P1OUT 0x00 -#define VAL_P1DIR 0xFF - -#define VAL_P2OUT 0x00 -#define VAL_P2DIR 0xFF - -#define VAL_P3OUT P3_O_TXD0_MASK -#define VAL_P3DIR ~P3_I_RXD0_MASK - -#define VAL_P4OUT 0x00 -#define VAL_P4DIR 0xFF - -#define VAL_P5OUT 0x00 -#define VAL_P5DIR 0xFF - -#define VAL_P6OUT P6_O_LED_MASK -#define VAL_P6DIR ~P6_I_BUTTON_MASK - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.mk b/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.mk deleted file mode 100644 index 420f176..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_MSP430_P1611/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/OLIMEX_MSP430_P1611/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/OLIMEX_MSP430_P1611 diff --git a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.c b/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.c deleted file mode 100644 index 047e7e7..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -/* - * SYS IRQ handling here. - */ -static CH_IRQ_HANDLER(SYSIrqHandler) { - - CH_IRQ_PROLOGUE(); - - if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { - (void) AT91C_BASE_PITC->PITC_PIVR; - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - } - -#if USE_SAM7_DBGU_UART - if (AT91C_BASE_DBGU->DBGU_CSR & - (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE | AT91C_US_RXBRK)) { - sd_lld_serve_interrupt(&SD3); - } -#endif - AT91C_BASE_AIC->AIC_EOICR = 0; - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - /* Watchdog disabled.*/ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - at91sam7_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * LCD pins setup. - */ - palClearPad(IOPORT2, PIOB_LCD_BL); - palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); - - palSetPad(IOPORT1, PIOA_LCD_RESET); - palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); - - /* - * Joystick and buttons setup. - */ - palSetGroupMode(IOPORT1, - PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | - PIOA_B4_MASK | PIOA_B5_MASK, - PAL_MODE_INPUT); - palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); - - /* - * MMC/SD slot setup. - */ - palSetGroupMode(IOPORT2, - PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, - PAL_MODE_INPUT); - - /* - * PIT Initialization. - */ - AIC_ConfigureIT(AT91C_ID_SYS, - AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), - SYSIrqHandler); - AIC_EnableIT(AT91C_ID_SYS); - AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; - AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - - /* - * RTS/CTS pins enabled for USART0 only. - */ - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; - AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.h b/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.h deleted file mode 100644 index d4a7b1e..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the Olimex SAM7-EX256 development board. - */ - -/* - * Board identifier. - */ -#define BOARD_OLIMEX_SAM7_EX256 -#define BOARD_NAME "Olimex SAM7-EX256" - -/* - * Select your platform by modifying the following line. - */ -#if !defined(SAM7_PLATFORM) -#define SAM7_PLATFORM SAM7X256 -#endif - -#include "at91sam7.h" - -#define CLK 18432000 -#define MCK 48054857 - -/* - * Initial I/O setup. - */ -#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOA_OSR 0x00000000 /* Direction. */ -#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ - -#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOB_OSR 0x00000000 /* Direction. */ -#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ - -/* - * I/O definitions. - */ -#define PIOA_LCD_RESET 2 -#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) -#define PIOA_B1 7 -#define PIOA_B1_MASK (1 << PIOA_B1) -#define PIOA_B2 8 -#define PIOA_B2_MASK (1 << PIOA_B2) -#define PIOA_B3 9 -#define PIOA_B3_MASK (1 << PIOA_B3) -#define PIOA_B4 14 -#define PIOA_B4_MASK (1 << PIOA_B4) -#define PIOA_B5 15 -#define PIOA_B5_MASK (1 << PIOA_B5) -#define PIOA_USB_PUP 25 -#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) -#define PIOA_USB_PR 26 -#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) - -#define PIOB_PHY_PD 18 -#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) -#define PIOB_AUDIO_OUT 19 -#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) -#define PIOB_LCD_BL 20 -#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) -#define PIOB_MMC_WP 22 -#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) -#define PIOB_MMC_CP 23 -#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) -#define PIOB_SW1 24 -#define PIOB_SW1_MASK (1 << PIOB_SW1) -#define PIOB_SW2 25 -#define PIOB_SW2_MASK (1 << PIOB_SW2) -#define PIOB_PHY_IRQ 26 -#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.mk b/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.mk deleted file mode 100644 index 862319c..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_EX256/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/OLIMEX_SAM7_EX256/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/OLIMEX_SAM7_EX256 diff --git a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.c b/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.c deleted file mode 100644 index e41f7f5..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -/* - * SYS IRQ handling here. - */ -static CH_IRQ_HANDLER(SYSIrqHandler) { - - CH_IRQ_PROLOGUE(); - - if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { - (void) AT91C_BASE_PITC->PITC_PIVR; - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - } - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - /* Watchdog disabled.*/ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - at91sam7_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * LED pins setup. - */ - palClearPad(IOPORT1, PIOA_LED1); - palSetPadMode(IOPORT1, PIOA_LED1, PAL_MODE_OUTPUT_PUSHPULL); - palClearPad(IOPORT1, PIOA_LED2); - palSetPadMode(IOPORT1, PIOA_LED2, PAL_MODE_OUTPUT_PUSHPULL); - - /* - * buttons setup. - */ - palSetGroupMode(IOPORT1, PIOA_B1_MASK | PIOA_B2_MASK, PAL_MODE_INPUT); - - /* - * MMC/SD slot setup. - */ - palSetGroupMode(IOPORT1, - PIOA_MMC_WP_MASK | PIOA_MMC_CP_MASK, - PAL_MODE_INPUT); - - /* - * PIT Initialization. - */ - AIC_ConfigureIT(AT91C_ID_SYS, - AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), - SYSIrqHandler); - AIC_EnableIT(AT91C_ID_SYS); - AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; - AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.h b/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.h deleted file mode 100644 index 40a815f..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the Olimex SAM7-P256 development board. - */ - -/* - * Board identifier. - */ -#define BOARD_OLIMEX_SAM7_P256 - -/* - * Select your platform by modifying the following line. - */ -#if !defined(SAM7_PLATFORM) -#define SAM7_PLATFORM SAM7S256 -#endif - -#include "at91sam7.h" - -#define CLK 18432000 -#define MCK 48054857 - -/* - * Initial I/O setup. - */ -#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOA_OSR 0x00000000 /* Direction. */ -#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ - -/* - * I/O definitions. - */ -#define PIOA_LED1 18 -#define PIOA_LED1_MASK (1 << PIOA_LED1_MASK) -#define PIOA_LED2 17 -#define PIOA_LED2_MASK (1 << PIOA_LED2_MASK) -#define PIOA_B1 19 -#define PIOA_B1_MASK (1 << PIOA_B1) -#define PIOA_B2 20 -#define PIOA_B2_MASK (1 << PIOA_B2) -#define PIOA_DP_PUP 25 -#define PIOA_DD_PUP_MASK (1 << PIOA_DP_PUP) -#define PIOA_USB_D 26 -#define PIOA_USB_D_MASK (1 << PIOA_USB_D) - -#define PIOA_MMC_WP 16 -#define PIOA_MMC_WP_MASK (1 << PIOA_MMC_WP) -#define PIOA_MMC_CP 15 -#define PIOA_MMC_CP_MASK (1 << PIOA_MMC_CP) - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.mk b/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.mk deleted file mode 100644 index 547b797..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_SAM7_P256/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/OLIMEX_SAM7_P256/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/OLIMEX_SAM7_P256 diff --git a/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.c b/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.c deleted file mode 100644 index ae47ec9..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - stm32_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.h b/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.h deleted file mode 100644 index 8c050e5..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the Olimex STM33-P103 proto board. - */ - -/* - * Board identifier. - */ -#define BOARD_OLIMEX_STM32_P103 -#define BOARD_NAME "Olimex STM32-P103" - -/* - * Board frequencies. - */ -#define STM32_LSECLK 32768 -#define STM32_HSECLK 8000000 - -/* - * MCU type, this macro is used by both the ST library and the ChibiOS/RT - * native STM32 HAL. - */ -#define STM32F10X_MD - -/* - * IO pins assignments. - */ -#define GPIOA_BUTTON 0 -#define GPIOA_SPI1NSS 4 - -#define GPIOB_SPI2NSS 12 - -#define GPIOC_MMCWP 6 -#define GPIOC_MMCCP 7 -#define GPIOC_CANCNTL 10 -#define GPIOC_DISC 11 -#define GPIOC_LED 12 - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * - * The digits have the following meaning: - * 0 - Analog input. - * 1 - Push Pull output 10MHz. - * 2 - Push Pull output 2MHz. - * 3 - Push Pull output 50MHz. - * 4 - Digital input. - * 5 - Open Drain output 10MHz. - * 6 - Open Drain output 2MHz. - * 7 - Open Drain output 50MHz. - * 8 - Digital input with PullUp or PullDown resistor depending on ODR. - * 9 - Alternate Push Pull output 10MHz. - * A - Alternate Push Pull output 2MHz. - * B - Alternate Push Pull output 50MHz. - * C - Reserved. - * D - Alternate Open Drain output 10MHz. - * E - Alternate Open Drain output 2MHz. - * F - Alternate Open Drain output 50MHz. - * Please refer to the STM32 Reference Manual for details. - */ - -/* - * Port A setup. - * Everything input with pull-up except: - * PA0 - Normal input (BUTTON). - * PA2 - Alternate output (USART2 TX). - * PA3 - Normal input (USART2 RX). - */ -#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */ -#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */ -#define VAL_GPIOAODR 0xFFFFFFFF - -/* - * Port B setup. - * Everything input with pull-up except: - * PB13 - Alternate output (MMC SPI2 SCK). - * PB14 - Normal input (MMC SPI2 MISO). - * PB15 - Alternate output (MMC SPI2 MOSI). - */ -#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ -#define VAL_GPIOBCRH 0xB4B88888 /* PB15...PB8 */ -#define VAL_GPIOBODR 0xFFFFFFFF - -/* - * Port C setup. - * Everything input with pull-up except: - * PC6 - Normal input because there is an external resistor. - * PC7 - Normal input because there is an external resistor. - * PC11 - Push Pull output (CAN CNTRL). - * PC12 - Push Pull output (LED). - */ -#define VAL_GPIOCCRL 0x44888888 /* PC7...PC0 */ -#define VAL_GPIOCCRH 0x88833888 /* PC15...PC8 */ -#define VAL_GPIOCODR 0xFFFFFFFF - -/* - * Port D setup. - * Everything input with pull-up except: - * PD0 - Normal input (XTAL). - * PD1 - Normal input (XTAL). - */ -#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ -#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ -#define VAL_GPIODODR 0xFFFFFFFF - -/* - * Port E setup. - * Everything input with pull-up except: - */ -#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ -#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ -#define VAL_GPIOEODR 0xFFFFFFFF - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.mk b/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.mk deleted file mode 100644 index cb03841..0000000 --- a/ChibiOS_2.0.8/boards/OLIMEX_STM32_P103/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_P103/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_P103 diff --git a/ChibiOS_2.0.8/boards/RAISONANCE_REVA_STM8S/board.c b/ChibiOS_2.0.8/boards/RAISONANCE_REVA_STM8S/board.c deleted file mode 100644 index cbd5cc6..0000000 --- a/ChibiOS_2.0.8/boards/RAISONANCE_REVA_STM8S/board.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -/* - * TIM 2 clock after the prescaler. - */ -#define TIM2_CLOCK (SYSCLK / 16) -#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1) - -/* - * TIM2 interrupt handler. - */ -CH_IRQ_HANDLER(13) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - TIM2_SR1 = 0; - - CH_IRQ_EPILOGUE(); -} - -/* - * Board initialization code. - */ -void hwinit(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * TIM2 initialization as system tick. - */ - CLK_PCKENR1 |= 32; /* PCKEN15, TIM2 clock source.*/ - TIM2_PSCR = 4; /* Prescaler divide by 2^4=16.*/ - TIM2_ARRH = TIM2_ARR >> 8; - TIM2_ARRL = TIM2_ARR; - TIM2_CNTRH = 0; - TIM2_CNTRL = 0; - TIM2_SR1 = 0; - TIM2_IER = 1; /* UIE */ - TIM2_CR1 = 1; /* CEN */ -} diff --git a/ChibiOS_2.0.8/boards/RAISONANCE_REVA_STM8S/board.h b/ChibiOS_2.0.8/boards/RAISONANCE_REVA_STM8S/board.h deleted file mode 100644 index 3ecb6c0..0000000 --- a/ChibiOS_2.0.8/boards/RAISONANCE_REVA_STM8S/board.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for Raisonance REva V3 + STM8S208RB daughter board. - */ - -/* - * Board identifiers. - */ -#define BOARD_REVA_V3_STM8S208RB -#define BOARD_NAME "Raisonance REva V3 + STM8S208RB" - -/* - * Board frequencies. - */ -#define HSECLK 24000000 - -/* - * MCU model used on the board. - * The available models are listed in the file ./os/hal/platforms/stm8/stm8.h - */ -#define STM8_PLATFORM PLATFORM_STM8S208RB - -/* - * Pin definitions. - */ -#define PA_OSCIN 1 -#define PA_J2_25 2 /* It is also OSCOUT. */ -#define PA_J2_27 3 -#define PA_RX 4 -#define PA_TX 5 - -#define PB_LED(n) (n) -#define PB_LCD_D0 0 -#define PB_LCD_D1 1 -#define PB_LCD_CSB 2 -#define PB_LCD_RESB 3 - -#define PC_ADC_ETR 0 -#define PC_J2_51 1 -#define PC_J2_53 2 -#define PC_J2_55 3 -#define PC_J2_57 4 -#define PC_SCK 5 -#define PC_MOSI 6 -#define PC_MISO 7 - -#define PD_J2_69 0 -#define PD_J2_21 1 -#define PD_J2_67 2 -#define PD_J2_65 3 -#define PD_PWM 4 -#define PD_J2_63 5 -#define PD_J2_61 6 -#define PD_J2_59 7 - -#define PE_P2_49 0 -#define PE_SCL 1 -#define PE_SDA 2 -#define PE_P2_47 3 -#define PE_P2_45 4 -#define PE_P2_43 5 -#define PE_P2_41 6 -#define PE_P2_39 7 - -#define PF_J2_37 0 -#define PF_J2_35 1 -#define PF_J2_33 2 -#define PF_J2_31 3 -#define PF_ANA_IN1 4 -#define PF_ANA_IN2 5 -#define PF_ANA_TEMP 6 -#define PF_ANA_POT 7 - -#define PG_CAN_TX 0 -#define PG_CAN_RX 1 -#define PG_BT5 2 -#define PG_BT6 3 -#define PG_SW4 4 -#define PG_SW3 5 -#define PG_SW2 6 -#define PG_SW1 7 - -#define PI_J2_71 0 - -/* - * Port A initial setup. - */ -#define VAL_GPIOAODR (1 << PA_TX) /* PA_TX initially to 1. */ -#define VAL_GPIOADDR (1 << PA_TX) /* PA_TX output, others inputs. */ -#define VAL_GPIOACR1 0xFF /* All pull-up or push-pull. */ -#define VAL_GPIOACR2 0 - -/* - * Port B initial setup. - */ -#define VAL_GPIOBODR 0xFF /* Initially all set to high. */ -#define VAL_GPIOBDDR 0xFF /* All outputs. */ -#define VAL_GPIOBCR1 0xFF /* All push-pull. */ -#define VAL_GPIOBCR2 0 - -/* - * Port C initial setup. - */ -#define VAL_GPIOCODR 0 -#define VAL_GPIOCDDR 0 /* All inputs. */ -#define VAL_GPIOCCR1 0xFF /* All pull-up. */ -#define VAL_GPIOCCR2 0 - -/* - * Port D initial setup. - */ -#define VAL_GPIODODR 0 -#define VAL_GPIODDDR 0 /* All inputs. */ -#define VAL_GPIODCR1 0xFF /* All pull-up. */ -#define VAL_GPIODCR2 0 - -/* - * Port E initial setup. - */ -#define VAL_GPIOEODR 0 -#define VAL_GPIOEDDR 0 /* All inputs. */ -#define VAL_GPIOECR1 0xFF /* All pull-up. */ -#define VAL_GPIOECR2 0 - -/* - * Port F initial setup. - */ -#define VAL_GPIOFODR 0 -#define VAL_GPIOFDDR 0 /* All inputs. */ -#define VAL_GPIOFCR1 0xFF /* All pull-up. */ -#define VAL_GPIOFCR2 0 - -/* - * Port G initial setup. - */ -#define VAL_GPIOGODR (1 << PG_CAN_TX)/* CAN_TX initially to 1. */ -#define VAL_GPIOGDDR (1 << PG_CAN_TX)/* CAN_TX output, others inputs. */ -#define VAL_GPIOGCR1 0xFF /* All pull-up or push-pull. */ -#define VAL_GPIOGCR2 0 - -/* - * Port H initial setup (dummy, not present). - */ -#define VAL_GPIOHODR 0 -#define VAL_GPIOHDDR 0 /* All inputs. */ -#define VAL_GPIOHCR1 0xFF /* All pull-up. */ -#define VAL_GPIOHCR2 0 - -/* - * Port I initial setup. - */ -#define VAL_GPIOIODR 0 -#define VAL_GPIOIDDR 0 /* All inputs. */ -#define VAL_GPIOICR1 0xFF /* All pull-up. */ -#define VAL_GPIOICR2 0 - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.c b/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.c deleted file mode 100644 index b75ac97..0000000 --- a/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - stm32_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * Remap USART2 to the PD5/PD6 pins, done after halInit since HAL resets - * these. - */ - AFIO->MAPR |= AFIO_MAPR_USART2_REMAP; - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.h b/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.h deleted file mode 100644 index bcecdbc..0000000 --- a/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for the STMicroelectronics STM3210C-EVAL evaluation board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_STM3210C_EVAL -#define BOARD_NAME "ST STM3210C-EVAL" - -/* - * Board frequencies. - */ -#define STM32_LSECLK 32768 -#define STM32_HSECLK 25000000 - -/* - * MCU type, this macro is used by both the ST library and the ChibiOS/RT - * native STM32 HAL. - */ -#define STM32F10X_CL - -/* - * IO pins assignments. - * *********************TO BE COMPLETED********************* - */ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * - * The digits have the following meaning: - * 0 - Analog input. - * 1 - Push Pull output 10MHz. - * 2 - Push Pull output 2MHz. - * 3 - Push Pull output 50MHz. - * 4 - Digital input. - * 5 - Open Drain output 10MHz. - * 6 - Open Drain output 2MHz. - * 7 - Open Drain output 50MHz. - * 8 - Digital input with PullUp or PullDown resistor depending on ODR. - * 9 - Alternate Push Pull output 10MHz. - * A - Alternate Push Pull output 2MHz. - * B - Alternate Push Pull output 50MHz. - * C - Reserved. - * D - Alternate Open Drain output 10MHz. - * E - Alternate Open Drain output 2MHz. - * F - Alternate Open Drain output 50MHz. - * Please refer to the STM32 Reference Manual for details. - */ - -/* - * Port A setup. - * Everything input except: - */ -#define VAL_GPIOACRL 0x44444444 /* PA7...PA0 */ -#define VAL_GPIOACRH 0x44444444 /* PA15...PA8 */ -#define VAL_GPIOAODR 0xFFFFFFFF - -/* - * Port B setup. - * Everything input except: - */ -#define VAL_GPIOBCRL 0x44444444 /* PB7...PB0 */ -#define VAL_GPIOBCRH 0x44444444 /* PB15...PB8 */ -#define VAL_GPIOBODR 0xFFFFFFFF - -/* - * Port C setup. - * Everything input except: - */ -#define VAL_GPIOCCRL 0x44444444 /* PC7...PC0 */ -#define VAL_GPIOCCRH 0x44444444 /* PC15...PC8 */ -#define VAL_GPIOCODR 0xFFFFFFFF - -/* - * Port D setup. - * Everything input except: - * PD5 - USART2TX (remapped) AF PP Output - * PD6 - USART2RX (remapped) Digital Input - * PD7 - LED (LD1) PP Output - */ -#define VAL_GPIODCRL 0x34B44444 /* PD7...PD0 */ -#define VAL_GPIODCRH 0x44444444 /* PD15...PD8 */ -#define VAL_GPIODODR 0x0F0FFFFF - -/* - * Port E setup. - * Everything input except: - */ -#define VAL_GPIOECRL 0x44444444 /* PE7...PE0 */ -#define VAL_GPIOECRH 0x44444444 /* PE15...PE8 */ -#define VAL_GPIOEODR 0xFFFFFFFF - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.mk b/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.mk deleted file mode 100644 index e2c4f9c..0000000 --- a/ChibiOS_2.0.8/boards/ST_STM3210C_EVAL/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS}/boards/ST_STM3210C_EVAL/board.c - -# Required include directories -BOARDINC = ${CHIBIOS}/boards/ST_STM3210C_EVAL diff --git a/ChibiOS_2.0.8/boards/readme.txt b/ChibiOS_2.0.8/boards/readme.txt deleted file mode 100644 index 578c79b..0000000 --- a/ChibiOS_2.0.8/boards/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -This directory contains the support files for various board models. If you -want to support a new board: -- Create a new directory under ./boards, give it the name of your board. -- Copy inside the new directory the files from a similar board. -- Customize board.c, board.h and board.mk in order to correctly initialize - your board. \ No newline at end of file diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/Makefile b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/Makefile deleted file mode 100644 index c65f77d..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/Makefile +++ /dev/null @@ -1,184 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_SAM7_P256/board.mk -include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/ch.ld deleted file mode 100644 index 5729a52..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/ch.ld +++ /dev/null @@ -1,105 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AT91SAM7X256 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x100000, len = 256k - ram : org = 0x200020, len = 64k - 0x20 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash - - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram - - /DISCARD/ : - { - *(.eh_*) - } -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/chconf.h deleted file mode 100644 index 92e562c..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/chconf.h +++ /dev/null @@ -1,475 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @addtogroup config - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. - * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/main.c b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/main.c deleted file mode 100644 index 9d6b76a..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/main.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -static WORKING_AREA(waThread1, 64); -static msg_t Thread1(void *p) { - - (void)p; - while (TRUE) { - palSetPad(IOPORT1, PIOA_LED1); - chThdSleepMilliseconds(100); - palClearPad(IOPORT1, PIOA_LED1); - chThdSleepMilliseconds(900); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - (void)argc; - (void)argv; - - /* - * Activates the serial driver 1 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity. - */ - while (TRUE) { - chThdSleepMilliseconds(500); - if (!palReadPad(IOPORT1, PIOA_B1)) - sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); - if (!palReadPad(IOPORT1, PIOA_B2)) - TestThread(&SD1); - } - - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/mcuconf.h deleted file mode 100644 index 02ce316..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/mcuconf.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AT91SAM7 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ -#define MAC_TRANSMIT_BUFFERS 2 -#define MAC_RECEIVE_BUFFERS 2 -#define MAC_BUFFERS_SIZE 1518 -#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_SAM7_USART0 TRUE -#define USE_SAM7_USART1 TRUE -#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) -#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/readme.txt deleted file mode 100644 index 00bc052..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7S-GCC/readme.txt +++ /dev/null @@ -1,28 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI AT91SAM7S256. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex SAM7-P256 board. - -** The Demo ** - -The demo currently just flashes the LED1 using a thread. -The button B1 prints an "Hello World!" string on RS232_0, the button B2 -activates che ChibiOS/RT test suite, output on RS232_0(port baudrate 38400). - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright -and are licensed under a different license, see the header present in all the -source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. -Also note that not all the files present in the Atmel library are distribuited -with ChibiOS/RT, you can find the whole library on the Atmel web site: - - http://www.atmel.com diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/Makefile b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/Makefile deleted file mode 100644 index 3d2a7dd..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/Makefile +++ /dev/null @@ -1,184 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk -include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/ch.ld deleted file mode 100644 index 805c8a5..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ /dev/null @@ -1,110 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AT91SAM7X256 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x100000, len = 256k - ram : org = 0x200020, len = 64k - 0x20 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.ctors) - *(.dtors) - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/main.c b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/main.c deleted file mode 100644 index 4196956..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/main.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -static WORKING_AREA(waThread1, 64); -static msg_t Thread1(void *p) { - - (void)p; - while (TRUE) { - palSetPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(100); - palClearPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(900); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - (void)argc; - (void)argv; - - /* - * Activates the serial driver 1 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity. - */ - while (TRUE) { - chThdSleepMilliseconds(500); - if (!palReadPad(IOPORT2, PIOB_SW1)) - sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); - if (!palReadPad(IOPORT2, PIOB_SW2)) - TestThread(&SD1); - } - - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/mcuconf.h deleted file mode 100644 index 02ce316..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/mcuconf.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AT91SAM7 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ -#define MAC_TRANSMIT_BUFFERS 2 -#define MAC_RECEIVE_BUFFERS 2 -#define MAC_BUFFERS_SIZE 1518 -#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_SAM7_USART0 TRUE -#define USE_SAM7_USART1 TRUE -#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) -#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/readme.txt deleted file mode 100644 index e33b627..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-GCC/readme.txt +++ /dev/null @@ -1,28 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex SAM7-EX256 board. - -** The Demo ** - -The demo currently just flashes the LCD background using a thread. -The button SW1 prints an "Hello World!" string on COM1, the button SW2 -activates che ChibiOS/RT test suite, output on COM1. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright -and are licensed under a different license, see the header present in all the -source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. -Also note that not all the files present in the Atmel library are distribuited -with ChibiOS/RT, you can find the whole library on the Atmel web site: - - http://www.atmel.com diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile deleted file mode 100644 index b83c41f..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ /dev/null @@ -1,194 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk -include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk -include ./lwip/lwip.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(LWNETIFSRC) \ - $(LWCORESRC) \ - $(LWIPV4SRC) \ - $(LWAPISRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - ./lwip/arch/sys_arch.c \ - ./lwip/lwipthread.c \ - ./web/web.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 \ - ./lwip - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DLWIP_PROVIDE_ERRNO - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld deleted file mode 100644 index 805c8a5..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld +++ /dev/null @@ -1,110 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AT91SAM7X256 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x100000, len = 256k - ram : org = 0x200020, len = 64k - 0x20 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.ctors) - *(.dtors) - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h deleted file mode 100644 index bab624b..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ /dev/null @@ -1,497 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ - /* Space for the LWIP sys_timeouts structure.*/ \ - void *p_lwipspace[1]; \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ - (tp)->p_lwipspace[0] = NULL; \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h deleted file mode 100644 index e438ebb..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC TRUE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h deleted file mode 100644 index bf28818..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __CC_H__ -#define __CC_H__ - -#include - -typedef uint8_t u8_t; -typedef int8_t s8_t; -typedef uint16_t u16_t; -typedef int16_t s16_t; -typedef uint32_t u32_t; -typedef int32_t s32_t; -typedef uint32_t mem_ptr_t; - -#define LWIP_PLATFORM_DIAG(x) -#define LWIP_PLATFORM_ASSERT(x) { \ - chSysHalt(); \ -} - -#define BYTE_ORDER LITTLE_ENDIAN - -#endif /* __CC_H__ */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h deleted file mode 100644 index 4cbd285..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __PERF_H__ -#define __PERF_H__ - -#define PERF_START -#define PERF_STOP(x) - -#endif /* __PERF_H__ */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c deleted file mode 100644 index c9f55e8..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "ch.h" - -#include "lwip/opt.h" -#include "lwip/mem.h" -#include "lwip/sys.h" -#include "lwip/stats.h" - -#include "arch/cc.h" -#include "arch/sys_arch.h" - -void sys_init(void) { - -} - -sys_sem_t sys_sem_new(u8_t count) { - - sys_sem_t sem = chHeapAlloc(NULL, sizeof(Semaphore)); - if (sem == 0) { - SYS_STATS_INC(sem.err); - } - else { - chSemInit(sem, (cnt_t)count); - SYS_STATS_INC(sem.used); - } - return sem; -} - -void sys_sem_free(sys_sem_t sem) { - - chHeapFree(sem); - SYS_STATS_DEC(sem.used); -} - -void sys_sem_signal(sys_sem_t sem) { - - chSemSignal(sem); -} - -u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) { - systime_t time; - - chSysLock(); - time = chTimeNow(); - if (chSemWaitTimeoutS(sem, (systime_t)timeout) != RDY_OK) - time = SYS_ARCH_TIMEOUT; - else - time = chTimeNow() - time; - chSysUnlock(); - return time; -} - -sys_mbox_t sys_mbox_new(int size) { - - sys_mbox_t mbox = chHeapAlloc(NULL, sizeof(Mailbox) + sizeof(msg_t) * size); - if (mbox == 0) { - SYS_STATS_INC(mbox.err); - } - else { - chMBInit(mbox, (void *)(((uint8_t *)mbox) + sizeof(Mailbox)), size); - SYS_STATS_INC(mbox.used); - } - return mbox; -} - -void sys_mbox_free(sys_mbox_t mbox) { - - chHeapFree(mbox); - SYS_STATS_DEC(mbox.used); -} - -void sys_mbox_post(sys_mbox_t mbox, void *msg) { - - chMBPost(mbox, (msg_t)msg, TIME_INFINITE); -} - -err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg) { - - if (chMBPost(mbox, (msg_t)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) - return ERR_MEM; - return ERR_OK; -} - -u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) { - systime_t time; - - chSysLock(); - time = chTimeNow(); - if (chMBFetchS(mbox, (msg_t *)msg, (systime_t)timeout) != RDY_OK) - time = SYS_ARCH_TIMEOUT; - else - time = chTimeNow() - time; - chSysUnlock(); - return time; -} - -u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg) { - - if (chMBFetch(mbox, (msg_t *)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) - return SYS_MBOX_EMPTY; - return 0; -} - -struct sys_timeouts *sys_arch_timeouts(void) { - - return (struct sys_timeouts *)currp->p_lwipspace; -} - -sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), - void *arg, int stacksize, int prio) { - (void)name; - size_t wsz = THD_WA_SIZE(stacksize); - void *wsp = chCoreAlloc(wsz); - if (wsp == NULL) - return NULL; - return (sys_thread_t)chThdCreateStatic(wsp, wsz, prio, (tfunc_t)thread, arg); -} - -sys_prot_t sys_arch_protect(void) { - - chSysLock(); - return 0; -} - -void sys_arch_unprotect(sys_prot_t pval) { - - (void)pval; - chSysUnlock(); -} diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h deleted file mode 100644 index 16601c4..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#ifndef __SYS_ARCH_H__ -#define __SYS_ARCH_H__ - -typedef Semaphore * sys_sem_t; -typedef Mailbox * sys_mbox_t; -typedef Thread * sys_thread_t; -typedef int sys_prot_t; - -#define SYS_MBOX_NULL (Mailbox *)0 -#define SYS_THREAD_NULL (Thread *)0 -#define SYS_SEM_NULL (Semaphore *)0 - -void sys_init(void); -sys_sem_t sys_sem_new(u8_t count); -void sys_sem_free(sys_sem_t sem); -void sys_sem_signal(sys_sem_t sem); -u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); - -sys_mbox_t sys_mbox_new(int size); -void sys_mbox_free(sys_mbox_t mbox); -void sys_mbox_post(sys_mbox_t mbox, void *msg); -err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg); -u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); -u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg); - -struct sys_timeouts *sys_arch_timeouts(void); - -sys_thread_t sys_thread_new(char *name, - void (* thread)(void *arg), - void *arg, - int stacksize, - int prio); - -sys_prot_t sys_arch_protect(void); -void sys_arch_unprotect(sys_prot_t pval); - -#endif /* __SYS_ARCH_H__ */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwip.mk b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwip.mk deleted file mode 100644 index 886eeab..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwip.mk +++ /dev/null @@ -1,44 +0,0 @@ -# List of the required lwIP files. -LWNETIFSRC = \ - ${CHIBIOS}/ext/lwip/src/netif/etharp.c \ - ${CHIBIOS}/ext/lwip/src/netif/loopif.c - -LWCORESRC = \ - ${CHIBIOS}/ext/lwip/src/core/dhcp.c \ - ${CHIBIOS}/ext/lwip/src/core/dns.c \ - ${CHIBIOS}/ext/lwip/src/core/init.c \ - ${CHIBIOS}/ext/lwip/src/core/mem.c \ - ${CHIBIOS}/ext/lwip/src/core/memp.c \ - ${CHIBIOS}/ext/lwip/src/core/netif.c \ - ${CHIBIOS}/ext/lwip/src/core/pbuf.c \ - ${CHIBIOS}/ext/lwip/src/core/raw.c \ - ${CHIBIOS}/ext/lwip/src/core/stats.c \ - ${CHIBIOS}/ext/lwip/src/core/sys.c \ - ${CHIBIOS}/ext/lwip/src/core/tcp.c \ - ${CHIBIOS}/ext/lwip/src/core/tcp_in.c \ - ${CHIBIOS}/ext/lwip/src/core/tcp_out.c \ - ${CHIBIOS}/ext/lwip/src/core/udp.c - -LWIPV4SRC = \ - ${CHIBIOS}/ext/lwip/src/core/ipv4/autoip.c \ - ${CHIBIOS}/ext/lwip/src/core/ipv4/icmp.c \ - ${CHIBIOS}/ext/lwip/src/core/ipv4/igmp.c \ - ${CHIBIOS}/ext/lwip/src/core/ipv4/inet.c \ - ${CHIBIOS}/ext/lwip/src/core/ipv4/inet_chksum.c \ - ${CHIBIOS}/ext/lwip/src/core/ipv4/ip.c \ - ${CHIBIOS}/ext/lwip/src/core/ipv4/ip_addr.c \ - ${CHIBIOS}/ext/lwip/src/core/ipv4/ip_frag.c - -LWAPISRC = \ - ${CHIBIOS}/ext/lwip/src/api/api_lib.c \ - ${CHIBIOS}/ext/lwip/src/api/api_msg.c \ - ${CHIBIOS}/ext/lwip/src/api/err.c \ - ${CHIBIOS}/ext/lwip/src/api/netbuf.c \ - ${CHIBIOS}/ext/lwip/src/api/netdb.c \ - ${CHIBIOS}/ext/lwip/src/api/netifapi.c \ - ${CHIBIOS}/ext/lwip/src/api/sockets.c \ - ${CHIBIOS}/ext/lwip/src/api/tcpip.c - -LWINC = \ - ${CHIBIOS}/ext/lwip/src/include \ - ${CHIBIOS}/ext/lwip/src/include/ipv4 diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c deleted file mode 100644 index 8c59d29..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - * **** This file incorporates work covered by the following copyright and **** - * **** permission notice: **** - * - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/** - * @file lwipthread.c - * @brief LWIP wrapper thread code. - * @addtogroup LWIP_THREAD - * @{ - */ - -#include "ch.h" -#include "hal.h" -#include "evtimer.h" - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include -#include -#include -#include "netif/etharp.h" -#include "netif/ppp_oe.h" - -#include "lwipthread.h" - -#define PERIODIC_TIMER_ID 1 -#define FRAME_RECEIVED_ID 2 - -/** - * Stack area for the LWIP-MAC thread. - */ -WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); - -/* - * Initialization. - */ -static void low_level_init(struct netif *netif) { - /* set MAC hardware address length */ - netif->hwaddr_len = ETHARP_HWADDR_LEN; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* device capabilities */ - /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; - - /* Do whatever else is needed to initialize interface. */ -} - -/* - * Transmits a frame. - */ -static err_t low_level_output(struct netif *netif, struct pbuf *p) { - struct pbuf *q; - MACTransmitDescriptor td; - - (void)netif; - if (macWaitTransmitDescriptor(Ð1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != RDY_OK) - return ERR_TIMEOUT; - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - /* Iterates through the pbuf chain. */ - for(q = p; q != NULL; q = q->next) { - macWriteTransmitDescriptor(&td, (uint8_t *)q->payload, (size_t)q->len); - } - macReleaseTransmitDescriptor(&td); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - - LINK_STATS_INC(link.xmit); - - return ERR_OK; -} - -/* - * Receives a frame. - */ -static struct pbuf *low_level_input(struct netif *netif) { - MACReceiveDescriptor rd; - struct pbuf *p, *q; - u16_t len; - - (void)netif; - if (macWaitReceiveDescriptor(Ð1, &rd, TIME_IMMEDIATE) == RDY_OK) { - len = (u16_t)rd.rd_size; - -#if ETH_PAD_SIZE - len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ -#endif - - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - - if (p != NULL) { - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - /* Iterates through the pbuf chain. */ - for(q = p; q != NULL; q = q->next) { - macReadReceiveDescriptor(&rd, (uint8_t *)q->payload, (size_t)q->len); - } - macReleaseReceiveDescriptor(&rd); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - - LINK_STATS_INC(link.recv); - } - else { - macReleaseReceiveDescriptor(&rd); - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - } - return p; - } - return NULL; -} - -/* - * Initialization. - */ -static err_t ethernetif_init(struct netif *netif) { -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwip"; -#endif /* LWIP_NETIF_HOSTNAME */ - - /* - * Initialize the snmp variables and counters inside the struct netif. - * The last argument should be replaced with your link speed, in units - * of bits per second. - */ - NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LWIP_LINK_SPEED); - - netif->state = NULL; - netif->name[0] = LWIP_IFNAME0; - netif->name[1] = LWIP_IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - /* initialize the hardware */ - low_level_init(netif); - - return ERR_OK; -} - -/** - * @brief LWIP handling thread. - * - * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL - * @return The function does not return. - */ -msg_t lwip_thread(void *p) { - EvTimer evt; - EventListener el0, el1; - struct ip_addr ip, gateway, netmask; - static struct netif thisif; - - /* Initializes the thing.*/ - sys_init(); - mem_init(); - memp_init(); - pbuf_init(); - netif_init(); - ip_init(); - tcpip_init(NULL, NULL); - - /* TCP/IP parameters, runtime or compile time.*/ - if (p) { - struct lwipthread_opts *opts = p; - unsigned i; - - for (i = 0; i < 6; i++) - thisif.hwaddr[i] = opts->macaddress[i]; - ip.addr = opts->address; - gateway.addr = opts->gateway; - netmask.addr = opts->netmask; - } - else { - thisif.hwaddr[0] = LWIP_ETHADDR_0; - thisif.hwaddr[1] = LWIP_ETHADDR_1; - thisif.hwaddr[2] = LWIP_ETHADDR_2; - thisif.hwaddr[3] = LWIP_ETHADDR_3; - thisif.hwaddr[4] = LWIP_ETHADDR_4; - thisif.hwaddr[5] = LWIP_ETHADDR_5; - LWIP_IPADDR(&ip); - LWIP_GATEWAY(&gateway); - LWIP_NETMASK(&netmask); - } - macSetAddress(Ð1, thisif.hwaddr); - netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input); - - netif_set_default(&thisif); - netif_set_up(&thisif); - - /* Setup event sources.*/ - evtInit(&evt, S2ST(5)); - evtStart(&evt); - chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID); - chEvtRegisterMask(macGetReceiveEventSource(Ð1), &el1, FRAME_RECEIVED_ID); - chEvtPend(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID); - - /* Goes to the final priority after initialization.*/ - chThdSetPriority(LWIP_THREAD_PRIORITY); - - while (TRUE) { - eventmask_t mask = chEvtWaitAny(ALL_EVENTS); - if (mask & PERIODIC_TIMER_ID) - (void)macPollLinkStatus(Ð1); - if (mask & FRAME_RECEIVED_ID) { - struct pbuf *p; - while ((p = low_level_input(&thisif)) != NULL) { - struct eth_hdr *ethhdr = p->payload; - switch (htons(ethhdr->type)) { - /* IP or ARP packet? */ - case ETHTYPE_IP: - case ETHTYPE_ARP: -#if PPPOE_SUPPORT - /* PPPoE packet? */ - case ETHTYPE_PPPOEDISC: - case ETHTYPE_PPPOE: -#endif /* PPPOE_SUPPORT */ - /* full packet send to tcpip_thread to process */ - if (thisif.input(p, &thisif) == ERR_OK) - break; - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - default: - pbuf_free(p); - } - } - } - } - return 0; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h deleted file mode 100644 index ddc048c..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file lwipthread.h - * @brief LWIP wrapper thread macros and structures. - * @addtogroup LWIP_THREAD - * @{ - */ - -#ifndef _LWIPTHREAD_H_ -#define _LWIPTHREAD_H_ - -/** @brief MAC thread priority.*/ -#ifndef LWIP_THREAD_PRIORITY -#define LWIP_THREAD_PRIORITY LOWPRIO -#endif - -/** @brief IP Address. */ -#if !defined(LWIP_IPADDR) || defined(__DOXYGEN__) -#define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 1, 20) -#endif - -/** @brief IP Gateway. */ -#if !defined(LWIP_GATEWAY) || defined(__DOXYGEN__) -#define LWIP_GATEWAY(p) IP4_ADDR(p, 192, 168, 1, 1) -#endif - -/** @brief IP netmask. */ -#if !defined(LWIP_NETMASK) || defined(__DOXYGEN__) -#define LWIP_NETMASK(p) IP4_ADDR(p, 255, 255, 255, 0) -#endif - -/** @brief MAC thread stack size. */ -#if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define LWIP_THREAD_STACK_SIZE 512 -#endif - -/** @brief Transmission timeout. */ -#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__) -#define LWIP_SEND_TIMEOUT 50 -#endif - -/** @brief Link speed. */ -#if !defined(LWIP_LINK_SPEED) || defined(__DOXYGEN__) -#define LWIP_LINK_SPEED 100000000 -#endif - -/** @brief MAC Address byte 0. */ -#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_0 0xC2 -#endif - -/** @brief MAC Address byte 1. */ -#if !defined(LWIP_ETHADDR_1) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_1 0xAF -#endif - -/** @brief MAC Address byte 2. */ -#if !defined(LWIP_ETHADDR_2) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_2 0x51 -#endif - -/** @brief MAC Address byte 3. */ -#if !defined(LWIP_ETHADDR_3) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_3 0x03 -#endif - -/** @brief MAC Address byte 4. */ -#if !defined(LWIP_ETHADDR_4) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_4 0xCF -#endif - -/** @brief MAC Address byte 5. */ -#if !defined(LWIP_ETHADDR_5) || defined(__DOXYGEN__) -#define LWIP_ETHADDR_5 0x46 -#endif - -/** @brief Interface name byte 0. */ -#if !defined(LWIP_IFNAME0) || defined(__DOXYGEN__) -#define LWIP_IFNAME0 'm' -#endif - -/** @brief Interface name byte 1. */ -#if !defined(LWIP_IFNAME1) || defined(__DOXYGEN__) -#define LWIP_IFNAME1 's' -#endif - -/** - * @brief Runtime TCP/IP settings. - */ -struct lwipthread_opts { - uint8_t *macaddress; - uint32_t address; - uint32_t netmask; - uint32_t gateway; -}; - -extern WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); - -#ifdef __cplusplus -extern "C" { -#endif - msg_t lwip_thread(void *p); -#ifdef __cplusplus -} -#endif - -#endif /* _LWIPTHREAD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h deleted file mode 100644 index 8707a27..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h +++ /dev/null @@ -1,1801 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIPOPT_H__ -#define __LWIPOPT_H__ - - -/* - ----------------------------------------------- - ---------- Platform specific locking ---------- - ----------------------------------------------- -*/ - -/** - * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain - * critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#ifndef SYS_LIGHTWEIGHT_PROT -#define SYS_LIGHTWEIGHT_PROT 0 -#endif - -/** - * NO_SYS==1: Provides VERY minimal functionality. Otherwise, - * use lwIP facilities. - */ -#ifndef NO_SYS -#define NO_SYS 0 -#endif - -/** - * MEMCPY: override this if you have a faster implementation at hand than the - * one included in your C library - */ -#ifndef MEMCPY -#define MEMCPY(dst,src,len) memcpy(dst,src,len) -#endif - -/** - * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a - * call to memcpy() if the length is known at compile time and is small. - */ -#ifndef SMEMCPY -#define SMEMCPY(dst,src,len) memcpy(dst,src,len) -#endif - -/* - ------------------------------------ - ---------- Memory options ---------- - ------------------------------------ -*/ -/** - * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library - * instead of the lwip internal allocator. Can save code size if you - * already use it. - */ -#ifndef MEM_LIBC_MALLOC -#define MEM_LIBC_MALLOC 0 -#endif - -/** -* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. -* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution -* speed and usage from interrupts! -*/ -#ifndef MEMP_MEM_MALLOC -#define MEMP_MEM_MALLOC 0 -#endif - -/** - * MEM_ALIGNMENT: should be set to the alignment of the CPU - * 4 byte alignment -> #define MEM_ALIGNMENT 4 - * 2 byte alignment -> #define MEM_ALIGNMENT 2 - */ -#ifndef MEM_ALIGNMENT -#define MEM_ALIGNMENT 4 -#endif - -/** - * MEM_SIZE: the size of the heap memory. If the application will send - * a lot of data that needs to be copied, this should be set high. - */ -#ifndef MEM_SIZE -#define MEM_SIZE 1600 -#endif - -/** - * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable - * amount of bytes before and after each memp element in every pool and fills - * it with a prominent default value. - * MEMP_OVERFLOW_CHECK == 0 no checking - * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed - * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time - * memp_malloc() or memp_free() is called (useful but slow!) - */ -#ifndef MEMP_OVERFLOW_CHECK -#define MEMP_OVERFLOW_CHECK 0 -#endif - -/** - * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make - * sure that there are no cycles in the linked lists. - */ -#ifndef MEMP_SANITY_CHECK -#define MEMP_SANITY_CHECK 0 -#endif - -/** - * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set - * of memory pools of various sizes. When mem_malloc is called, an element of - * the smallest pool that can provide the length needed is returned. - * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. - */ -#ifndef MEM_USE_POOLS -#define MEM_USE_POOLS 0 -#endif - -/** - * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next - * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more - * reliable. */ -#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL -#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 -#endif - -/** - * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h - * that defines additional pools beyond the "standard" ones required - * by lwIP. If you set this to 1, you must have lwippools.h in your - * inlude path somewhere. - */ -#ifndef MEMP_USE_CUSTOM_POOLS -#define MEMP_USE_CUSTOM_POOLS 0 -#endif - -/** - * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from - * interrupt context (or another context that doesn't allow waiting for a - * semaphore). - * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, - * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs - * with each loop so that mem_free can run. - * - * ATTENTION: As you can see from the above description, this leads to dis-/ - * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc - * can need longer. - * - * If you don't want that, at least for NO_SYS=0, you can still use the following - * functions to enqueue a deallocation call which then runs in the tcpip_thread - * context: - * - pbuf_free_callback(p); - * - mem_free_callback(m); - */ -#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT -#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 -#endif - -/* - ------------------------------------------------ - ---------- Internal Memory Pool Sizes ---------- - ------------------------------------------------ -*/ -/** - * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). - * If the application sends a lot of data out of ROM (or other static memory), - * this should be set high. - */ -#ifndef MEMP_NUM_PBUF -#define MEMP_NUM_PBUF 16 -#endif - -/** - * MEMP_NUM_RAW_PCB: Number of raw connection PCBs - * (requires the LWIP_RAW option) - */ -#ifndef MEMP_NUM_RAW_PCB -#define MEMP_NUM_RAW_PCB 4 -#endif - -/** - * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One - * per active UDP "connection". - * (requires the LWIP_UDP option) - */ -#ifndef MEMP_NUM_UDP_PCB -#define MEMP_NUM_UDP_PCB 4 -#endif - -/** - * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. - * (requires the LWIP_TCP option) - */ -#ifndef MEMP_NUM_TCP_PCB -#define MEMP_NUM_TCP_PCB 5 -#endif - -/** - * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. - * (requires the LWIP_TCP option) - */ -#ifndef MEMP_NUM_TCP_PCB_LISTEN -#define MEMP_NUM_TCP_PCB_LISTEN 8 -#endif - -/** - * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. - * (requires the LWIP_TCP option) - */ -#ifndef MEMP_NUM_TCP_SEG -#define MEMP_NUM_TCP_SEG 16 -#endif - -/** - * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for - * reassembly (whole packets, not fragments!) - */ -#ifndef MEMP_NUM_REASSDATA -#define MEMP_NUM_REASSDATA 5 -#endif - -/** - * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing - * packets (pbufs) that are waiting for an ARP request (to resolve - * their destination address) to finish. - * (requires the ARP_QUEUEING option) - */ -#ifndef MEMP_NUM_ARP_QUEUE -#define MEMP_NUM_ARP_QUEUE 30 -#endif - -/** - * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces - * can be members et the same time (one per netif - allsystems group -, plus one - * per netif membership). - * (requires the LWIP_IGMP option) - */ -#ifndef MEMP_NUM_IGMP_GROUP -#define MEMP_NUM_IGMP_GROUP 8 -#endif - -/** - * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. - * (requires NO_SYS==0) - */ -#ifndef MEMP_NUM_SYS_TIMEOUT -#define MEMP_NUM_SYS_TIMEOUT (4 + LWIP_DHCP + LWIP_DNS) -#endif - -/** - * MEMP_NUM_NETBUF: the number of struct netbufs. - * (only needed if you use the sequential API, like api_lib.c) - */ -#ifndef MEMP_NUM_NETBUF -#define MEMP_NUM_NETBUF 2 -#endif - -/** - * MEMP_NUM_NETCONN: the number of struct netconns. - * (only needed if you use the sequential API, like api_lib.c) - */ -#ifndef MEMP_NUM_NETCONN -#define MEMP_NUM_NETCONN 4 -#endif - -/** - * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used - * for callback/timeout API communication. - * (only needed if you use tcpip.c) - */ -#ifndef MEMP_NUM_TCPIP_MSG_API -#define MEMP_NUM_TCPIP_MSG_API 8 -#endif - -/** - * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used - * for incoming packets. - * (only needed if you use tcpip.c) - */ -#ifndef MEMP_NUM_TCPIP_MSG_INPKT -#define MEMP_NUM_TCPIP_MSG_INPKT 8 -#endif - -/** - * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. - */ -#ifndef PBUF_POOL_SIZE -#define PBUF_POOL_SIZE 16 -#endif - -/* - --------------------------------- - ---------- ARP options ---------- - --------------------------------- -*/ -/** - * LWIP_ARP==1: Enable ARP functionality. - */ -#ifndef LWIP_ARP -#define LWIP_ARP 1 -#endif - -/** - * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. - */ -#ifndef ARP_TABLE_SIZE -#define ARP_TABLE_SIZE 10 -#endif - -/** - * ARP_QUEUEING==1: Outgoing packets are queued during hardware address - * resolution. - */ -#ifndef ARP_QUEUEING -#define ARP_QUEUEING 1 -#endif - -/** - * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be - * updated with the source MAC and IP addresses supplied in the packet. - * You may want to disable this if you do not trust LAN peers to have the - * correct addresses, or as a limited approach to attempt to handle - * spoofing. If disabled, lwIP will need to make a new ARP request if - * the peer is not already in the ARP table, adding a little latency. - */ -#ifndef ETHARP_TRUST_IP_MAC -#define ETHARP_TRUST_IP_MAC 1 -#endif - -/* - -------------------------------- - ---------- IP options ---------- - -------------------------------- -*/ -/** - * IP_FORWARD==1: Enables the ability to forward IP packets across network - * interfaces. If you are going to run lwIP on a device with only one network - * interface, define this to 0. - */ -#ifndef IP_FORWARD -#define IP_FORWARD 0 -#endif - -/** - * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. - * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. - * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). - */ -#ifndef IP_OPTIONS_ALLOWED -#define IP_OPTIONS_ALLOWED 1 -#endif - -/** - * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that - * this option does not affect outgoing packet sizes, which can be controlled - * via IP_FRAG. - */ -#ifndef IP_REASSEMBLY -#define IP_REASSEMBLY 1 -#endif - -/** - * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note - * that this option does not affect incoming packet sizes, which can be - * controlled via IP_REASSEMBLY. - */ -#ifndef IP_FRAG -#define IP_FRAG 1 -#endif - -/** - * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) - * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived - * in this time, the whole packet is discarded. - */ -#ifndef IP_REASS_MAXAGE -#define IP_REASS_MAXAGE 3 -#endif - -/** - * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. - * Since the received pbufs are enqueued, be sure to configure - * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive - * packets even if the maximum amount of fragments is enqueued for reassembly! - */ -#ifndef IP_REASS_MAX_PBUFS -#define IP_REASS_MAX_PBUFS 10 -#endif - -/** - * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP - * fragmentation. Otherwise pbufs are allocated and reference the original - * packet data to be fragmented. - */ -#ifndef IP_FRAG_USES_STATIC_BUF -#define IP_FRAG_USES_STATIC_BUF 1 -#endif - -/** - * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer - * (requires IP_FRAG_USES_STATIC_BUF==1) - */ -#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) -#define IP_FRAG_MAX_MTU 1500 -#endif - -/** - * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. - */ -#ifndef IP_DEFAULT_TTL -#define IP_DEFAULT_TTL 255 -#endif - -/** - * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast - * filter per pcb on udp and raw send operations. To enable broadcast filter - * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. - */ -#ifndef IP_SOF_BROADCAST -#define IP_SOF_BROADCAST 0 -#endif - -/** - * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast - * filter on recv operations. - */ -#ifndef IP_SOF_BROADCAST_RECV -#define IP_SOF_BROADCAST_RECV 0 -#endif - -/* - ---------------------------------- - ---------- ICMP options ---------- - ---------------------------------- -*/ -/** - * LWIP_ICMP==1: Enable ICMP module inside the IP stack. - * Be careful, disable that make your product non-compliant to RFC1122 - */ -#ifndef LWIP_ICMP -#define LWIP_ICMP 1 -#endif - -/** - * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. - */ -#ifndef ICMP_TTL -#define ICMP_TTL (IP_DEFAULT_TTL) -#endif - -/** - * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) - */ -#ifndef LWIP_BROADCAST_PING -#define LWIP_BROADCAST_PING 0 -#endif - -/** - * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) - */ -#ifndef LWIP_MULTICAST_PING -#define LWIP_MULTICAST_PING 0 -#endif - -/* - --------------------------------- - ---------- RAW options ---------- - --------------------------------- -*/ -/** - * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. - */ -#ifndef LWIP_RAW -#define LWIP_RAW 1 -#endif - -/** - * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. - */ -#ifndef RAW_TTL -#define RAW_TTL (IP_DEFAULT_TTL) -#endif - -/* - ---------------------------------- - ---------- DHCP options ---------- - ---------------------------------- -*/ -/** - * LWIP_DHCP==1: Enable DHCP module. - */ -#ifndef LWIP_DHCP -#define LWIP_DHCP 0 -#endif - -/** - * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. - */ -#ifndef DHCP_DOES_ARP_CHECK -#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) -#endif - -/* - ------------------------------------ - ---------- AUTOIP options ---------- - ------------------------------------ -*/ -/** - * LWIP_AUTOIP==1: Enable AUTOIP module. - */ -#ifndef LWIP_AUTOIP -#define LWIP_AUTOIP 0 -#endif - -/** - * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on - * the same interface at the same time. - */ -#ifndef LWIP_DHCP_AUTOIP_COOP -#define LWIP_DHCP_AUTOIP_COOP 0 -#endif - -/** - * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes - * that should be sent before falling back on AUTOIP. This can be set - * as low as 1 to get an AutoIP address very quickly, but you should - * be prepared to handle a changing IP address when DHCP overrides - * AutoIP. - */ -#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES -#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 -#endif - -/* - ---------------------------------- - ---------- SNMP options ---------- - ---------------------------------- -*/ -/** - * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP - * transport. - */ -#ifndef LWIP_SNMP -#define LWIP_SNMP 0 -#endif - -/** - * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will - * allow. At least one request buffer is required. - */ -#ifndef SNMP_CONCURRENT_REQUESTS -#define SNMP_CONCURRENT_REQUESTS 1 -#endif - -/** - * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap - * destination is required - */ -#ifndef SNMP_TRAP_DESTINATIONS -#define SNMP_TRAP_DESTINATIONS 1 -#endif - -/** - * SNMP_PRIVATE_MIB: - */ -#ifndef SNMP_PRIVATE_MIB -#define SNMP_PRIVATE_MIB 0 -#endif - -/** - * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not - * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). - * Unsafe requests are disabled by default! - */ -#ifndef SNMP_SAFE_REQUESTS -#define SNMP_SAFE_REQUESTS 1 -#endif - -/* - ---------------------------------- - ---------- IGMP options ---------- - ---------------------------------- -*/ -/** - * LWIP_IGMP==1: Turn on IGMP module. - */ -#ifndef LWIP_IGMP -#define LWIP_IGMP 0 -#endif - -/* - ---------------------------------- - ---------- DNS options ----------- - ---------------------------------- -*/ -/** - * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS - * transport. - */ -#ifndef LWIP_DNS -#define LWIP_DNS 0 -#endif - -/** DNS maximum number of entries to maintain locally. */ -#ifndef DNS_TABLE_SIZE -#define DNS_TABLE_SIZE 4 -#endif - -/** DNS maximum host name length supported in the name table. */ -#ifndef DNS_MAX_NAME_LENGTH -#define DNS_MAX_NAME_LENGTH 256 -#endif - -/** The maximum of DNS servers */ -#ifndef DNS_MAX_SERVERS -#define DNS_MAX_SERVERS 2 -#endif - -/** DNS do a name checking between the query and the response. */ -#ifndef DNS_DOES_NAME_CHECK -#define DNS_DOES_NAME_CHECK 1 -#endif - -/** DNS use a local buffer if DNS_USES_STATIC_BUF=0, a static one if - DNS_USES_STATIC_BUF=1, or a dynamic one if DNS_USES_STATIC_BUF=2. - The buffer will be of size DNS_MSG_SIZE */ -#ifndef DNS_USES_STATIC_BUF -#define DNS_USES_STATIC_BUF 1 -#endif - -/** DNS message max. size. Default value is RFC compliant. */ -#ifndef DNS_MSG_SIZE -#define DNS_MSG_SIZE 512 -#endif - -/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, - * you have to define - * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} - * (an array of structs name/address, where address is an u32_t in network - * byte order). - * - * Instead, you can also use an external function: - * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) - * that returns the IP address or INADDR_NONE if not found. - */ -#ifndef DNS_LOCAL_HOSTLIST -#define DNS_LOCAL_HOSTLIST 0 -#endif /* DNS_LOCAL_HOSTLIST */ - -/** If this is turned on, the local host-list can be dynamically changed - * at runtime. */ -#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC -#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - -/* - --------------------------------- - ---------- UDP options ---------- - --------------------------------- -*/ -/** - * LWIP_UDP==1: Turn on UDP. - */ -#ifndef LWIP_UDP -#define LWIP_UDP 1 -#endif - -/** - * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) - */ -#ifndef LWIP_UDPLITE -#define LWIP_UDPLITE 0 -#endif - -/** - * UDP_TTL: Default Time-To-Live value. - */ -#ifndef UDP_TTL -#define UDP_TTL (IP_DEFAULT_TTL) -#endif - -/* - --------------------------------- - ---------- TCP options ---------- - --------------------------------- -*/ -/** - * LWIP_TCP==1: Turn on TCP. - */ -#ifndef LWIP_TCP -#define LWIP_TCP 1 -#endif - -/** - * TCP_TTL: Default Time-To-Live value. - */ -#ifndef TCP_TTL -#define TCP_TTL (IP_DEFAULT_TTL) -#endif - -/** - * TCP_WND: The size of a TCP window. This must be at least - * (2 * TCP_MSS) for things to work well - */ -#ifndef TCP_WND -#define TCP_WND 2048 -#endif - -/** - * TCP_MAXRTX: Maximum number of retransmissions of data segments. - */ -#ifndef TCP_MAXRTX -#define TCP_MAXRTX 12 -#endif - -/** - * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. - */ -#ifndef TCP_SYNMAXRTX -#define TCP_SYNMAXRTX 6 -#endif - -/** - * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. - * Define to 0 if your device is low on memory. - */ -#ifndef TCP_QUEUE_OOSEQ -#define TCP_QUEUE_OOSEQ (LWIP_TCP) -#endif - -/** - * TCP_MSS: TCP Maximum segment size. (default is 128, a *very* - * conservative default.) - * For the receive side, this MSS is advertised to the remote side - * when opening a connection. For the transmit size, this MSS sets - * an upper limit on the MSS advertised by the remote host. - */ -#ifndef TCP_MSS -#define TCP_MSS 128 -#endif - -/** - * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really - * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which - * reflects the available reassembly buffer size at the remote host) and the - * largest size permitted by the IP layer" (RFC 1122) - * Setting this to 1 enables code that checks TCP_MSS against the MTU of the - * netif used for a connection and limits the MSS if it would be too big otherwise. - */ -#ifndef TCP_CALCULATE_EFF_SEND_MSS -#define TCP_CALCULATE_EFF_SEND_MSS 1 -#endif - - -/** - * TCP_SND_BUF: TCP sender buffer space (bytes). - */ -#ifndef TCP_SND_BUF -#define TCP_SND_BUF 256 -#endif - -/** - * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least - * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. - */ -#ifndef TCP_SND_QUEUELEN -#define TCP_SND_QUEUELEN (4 * (TCP_SND_BUF/TCP_MSS)) -#endif - -/** - * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than or equal - * to TCP_SND_BUF. It is the amount of space which must be available in the - * TCP snd_buf for select to return writable. - */ -#ifndef TCP_SNDLOWAT -#define TCP_SNDLOWAT (TCP_SND_BUF/2) -#endif - -/** - * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. - */ -#ifndef TCP_LISTEN_BACKLOG -#define TCP_LISTEN_BACKLOG 0 -#endif - -/** - * The maximum allowed backlog for TCP listen netconns. - * This backlog is used unless another is explicitly specified. - * 0xff is the maximum (u8_t). - */ -#ifndef TCP_DEFAULT_LISTEN_BACKLOG -#define TCP_DEFAULT_LISTEN_BACKLOG 0xff -#endif - -/** - * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. - */ -#ifndef LWIP_TCP_TIMESTAMPS -#define LWIP_TCP_TIMESTAMPS 0 -#endif - -/** - * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an - * explicit window update - */ -#ifndef TCP_WND_UPDATE_THRESHOLD -#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) -#endif - -/** - * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. - * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all - * events (accept, sent, etc) that happen in the system. - * LWIP_CALLBACK_API==1: The PCB callback function is called directly - * for the event. - */ -//#define LWIP_EVENT_API - -/* - ---------------------------------- - ---------- Pbuf options ---------- - ---------------------------------- -*/ -/** - * PBUF_LINK_HLEN: the number of bytes that should be allocated for a - * link level header. The default is 14, the standard value for - * Ethernet. - */ -#ifndef PBUF_LINK_HLEN -#define PBUF_LINK_HLEN 14 -#endif - -/** - * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is - * designed to accomodate single full size TCP frame in one pbuf, including - * TCP_MSS, IP header, and link header. - */ -#ifndef PBUF_POOL_BUFSIZE -#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) -#endif - -/* - ------------------------------------------------ - ---------- Network Interfaces options ---------- - ------------------------------------------------ -*/ -/** - * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname - * field. - */ -#ifndef LWIP_NETIF_HOSTNAME -#define LWIP_NETIF_HOSTNAME 0 -#endif - -/** - * LWIP_NETIF_API==1: Support netif api (in netifapi.c) - */ -#ifndef LWIP_NETIF_API -#define LWIP_NETIF_API 0 -#endif - -/** - * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface - * changes its up/down status (i.e., due to DHCP IP acquistion) - */ -#ifndef LWIP_NETIF_STATUS_CALLBACK -#define LWIP_NETIF_STATUS_CALLBACK 0 -#endif - -/** - * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface - * whenever the link changes (i.e., link down) - */ -#ifndef LWIP_NETIF_LINK_CALLBACK -#define LWIP_NETIF_LINK_CALLBACK 0 -#endif - -/** - * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table - * indices) in struct netif. TCP and UDP can make use of this to prevent - * scanning the ARP table for every sent packet. While this is faster for big - * ARP tables or many concurrent connections, it might be counterproductive - * if you have a tiny ARP table or if there never are concurrent connections. - */ -#ifndef LWIP_NETIF_HWADDRHINT -#define LWIP_NETIF_HWADDRHINT 0 -#endif - -/** - * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP - * address equal to the netif IP address, looping them back up the stack. - */ -#ifndef LWIP_NETIF_LOOPBACK -#define LWIP_NETIF_LOOPBACK 0 -#endif - -/** - * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback - * sending for each netif (0 = disabled) - */ -#ifndef LWIP_LOOPBACK_MAX_PBUFS -#define LWIP_LOOPBACK_MAX_PBUFS 0 -#endif - -/** - * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in - * the system, as netifs must change how they behave depending on this setting - * for the LWIP_NETIF_LOOPBACK option to work. - * Setting this is needed to avoid reentering non-reentrant functions like - * tcp_input(). - * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a - * multithreaded environment like tcpip.c. In this case, netif->input() - * is called directly. - * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. - * The packets are put on a list and netif_poll() must be called in - * the main application loop. - */ -#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING -#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) -#endif - -/** - * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data - * to be sent into one single pbuf. This is for compatibility with DMA-enabled - * MACs that do not support scatter-gather. - * Beware that this might involve CPU-memcpy before transmitting that would not - * be needed without this flag! Use this only if you need to! - * - * @todo: TCP and IP-frag do not work with this, yet: - */ -#ifndef LWIP_NETIF_TX_SINGLE_PBUF -#define LWIP_NETIF_TX_SINGLE_PBUF 0 -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - -/* - ------------------------------------ - ---------- LOOPIF options ---------- - ------------------------------------ -*/ -/** - * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c - */ -#ifndef LWIP_HAVE_LOOPIF -#define LWIP_HAVE_LOOPIF 0 -#endif - -/* - ------------------------------------ - ---------- SLIPIF options ---------- - ------------------------------------ -*/ -/** - * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c - */ -#ifndef LWIP_HAVE_SLIPIF -#define LWIP_HAVE_SLIPIF 0 -#endif - -/* - ------------------------------------ - ---------- Thread options ---------- - ------------------------------------ -*/ -/** - * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. - */ -#ifndef TCPIP_THREAD_NAME -#define TCPIP_THREAD_NAME "tcpip_thread" -#endif - -/** - * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef TCPIP_THREAD_STACKSIZE -#define TCPIP_THREAD_STACKSIZE 1024 -#endif - -/** - * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef TCPIP_THREAD_PRIO -#define TCPIP_THREAD_PRIO (LOWPRIO + 1) -#endif - -/** - * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages - * The queue size value itself is platform-dependent, but is passed to - * sys_mbox_new() when tcpip_init is called. - */ -#ifndef TCPIP_MBOX_SIZE -#define TCPIP_MBOX_SIZE 4 -#endif - -/** - * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. - */ -#ifndef SLIPIF_THREAD_NAME -#define SLIPIF_THREAD_NAME "slipif_loop" -#endif - -/** - * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef SLIPIF_THREAD_STACKSIZE -#define SLIPIF_THREAD_STACKSIZE 1024 -#endif - -/** - * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef SLIPIF_THREAD_PRIO -#define SLIPIF_THREAD_PRIO (LOWPRIO + 1) -#endif - -/** - * PPP_THREAD_NAME: The name assigned to the pppMain thread. - */ -#ifndef PPP_THREAD_NAME -#define PPP_THREAD_NAME "pppMain" -#endif - -/** - * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef PPP_THREAD_STACKSIZE -#define PPP_THREAD_STACKSIZE 1024 -#endif - -/** - * PPP_THREAD_PRIO: The priority assigned to the pppMain thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef PPP_THREAD_PRIO -#define PPP_THREAD_PRIO (LOWPRIO + 1) -#endif - -/** - * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. - */ -#ifndef DEFAULT_THREAD_NAME -#define DEFAULT_THREAD_NAME "lwIP" -#endif - -/** - * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef DEFAULT_THREAD_STACKSIZE -#define DEFAULT_THREAD_STACKSIZE 1024 -#endif - -/** - * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef DEFAULT_THREAD_PRIO -#define DEFAULT_THREAD_PRIO (LOWPRIO + 1) -#endif - -/** - * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#ifndef DEFAULT_RAW_RECVMBOX_SIZE -#define DEFAULT_RAW_RECVMBOX_SIZE 4 -#endif - -/** - * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#ifndef DEFAULT_UDP_RECVMBOX_SIZE -#define DEFAULT_UDP_RECVMBOX_SIZE 4 -#endif - -/** - * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#ifndef DEFAULT_TCP_RECVMBOX_SIZE -#define DEFAULT_TCP_RECVMBOX_SIZE 40 -#endif - -/** - * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. - * The queue size value itself is platform-dependent, but is passed to - * sys_mbox_new() when the acceptmbox is created. - */ -#ifndef DEFAULT_ACCEPTMBOX_SIZE -#define DEFAULT_ACCEPTMBOX_SIZE 4 -#endif - -/* - ---------------------------------------------- - ---------- Sequential layer options ---------- - ---------------------------------------------- -*/ -/** - * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) - * Don't use it if you're not an active lwIP project member - */ -#ifndef LWIP_TCPIP_CORE_LOCKING -#define LWIP_TCPIP_CORE_LOCKING 0 -#endif - -/** - * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) - */ -#ifndef LWIP_NETCONN -#define LWIP_NETCONN 1 -#endif - -/* - ------------------------------------ - ---------- Socket options ---------- - ------------------------------------ -*/ -/** - * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) - */ -#ifndef LWIP_SOCKET -#define LWIP_SOCKET 1 -#endif - -/** - * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. - * (only used if you use sockets.c) - */ -#ifndef LWIP_COMPAT_SOCKETS -#define LWIP_COMPAT_SOCKETS 1 -#endif - -/** - * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. - * Disable this option if you use a POSIX operating system that uses the same - * names (read, write & close). (only used if you use sockets.c) - */ -#ifndef LWIP_POSIX_SOCKETS_IO_NAMES -#define LWIP_POSIX_SOCKETS_IO_NAMES 1 -#endif - -/** - * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT - * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set - * in seconds. (does not require sockets.c, and will affect tcp.c) - */ -#ifndef LWIP_TCP_KEEPALIVE -#define LWIP_TCP_KEEPALIVE 0 -#endif - -/** - * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing. - */ -#ifndef LWIP_SO_RCVTIMEO -#define LWIP_SO_RCVTIMEO 0 -#endif - -/** - * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. - */ -#ifndef LWIP_SO_RCVBUF -#define LWIP_SO_RCVBUF 0 -#endif - -/** - * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. - */ -#ifndef RECV_BUFSIZE_DEFAULT -#define RECV_BUFSIZE_DEFAULT INT_MAX -#endif - -/** - * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE! - */ -#ifndef SO_REUSE -#define SO_REUSE 0 -#endif - -/* - ---------------------------------------- - ---------- Statistics options ---------- - ---------------------------------------- -*/ -/** - * LWIP_STATS==1: Enable statistics collection in lwip_stats. - */ -#ifndef LWIP_STATS -#define LWIP_STATS 1 -#endif - -#if LWIP_STATS - -/** - * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. - */ -#ifndef LWIP_STATS_DISPLAY -#define LWIP_STATS_DISPLAY 0 -#endif - -/** - * LINK_STATS==1: Enable link stats. - */ -#ifndef LINK_STATS -#define LINK_STATS 1 -#endif - -/** - * ETHARP_STATS==1: Enable etharp stats. - */ -#ifndef ETHARP_STATS -#define ETHARP_STATS (LWIP_ARP) -#endif - -/** - * IP_STATS==1: Enable IP stats. - */ -#ifndef IP_STATS -#define IP_STATS 1 -#endif - -/** - * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is - * on if using either frag or reass. - */ -#ifndef IPFRAG_STATS -#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) -#endif - -/** - * ICMP_STATS==1: Enable ICMP stats. - */ -#ifndef ICMP_STATS -#define ICMP_STATS 1 -#endif - -/** - * IGMP_STATS==1: Enable IGMP stats. - */ -#ifndef IGMP_STATS -#define IGMP_STATS (LWIP_IGMP) -#endif - -/** - * UDP_STATS==1: Enable UDP stats. Default is on if - * UDP enabled, otherwise off. - */ -#ifndef UDP_STATS -#define UDP_STATS (LWIP_UDP) -#endif - -/** - * TCP_STATS==1: Enable TCP stats. Default is on if TCP - * enabled, otherwise off. - */ -#ifndef TCP_STATS -#define TCP_STATS (LWIP_TCP) -#endif - -/** - * MEM_STATS==1: Enable mem.c stats. - */ -#ifndef MEM_STATS -#define MEM_STATS 1 -#endif - -/** - * MEMP_STATS==1: Enable memp.c pool stats. - */ -#ifndef MEMP_STATS -#define MEMP_STATS 1 -#endif - -/** - * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). - */ -#ifndef SYS_STATS -#define SYS_STATS 1 -#endif - -#else - -#define LINK_STATS 0 -#define IP_STATS 0 -#define IPFRAG_STATS 0 -#define ICMP_STATS 0 -#define IGMP_STATS 0 -#define UDP_STATS 0 -#define TCP_STATS 0 -#define MEM_STATS 0 -#define MEMP_STATS 0 -#define SYS_STATS 0 -#define LWIP_STATS_DISPLAY 0 - -#endif /* LWIP_STATS */ - -/* - --------------------------------- - ---------- PPP options ---------- - --------------------------------- -*/ -/** - * PPP_SUPPORT==1: Enable PPP. - */ -#ifndef PPP_SUPPORT -#define PPP_SUPPORT 0 -#endif - -/** - * PPPOE_SUPPORT==1: Enable PPP Over Ethernet - */ -#ifndef PPPOE_SUPPORT -#define PPPOE_SUPPORT 0 -#endif - -/** - * PPPOS_SUPPORT==1: Enable PPP Over Serial - */ -#ifndef PPPOS_SUPPORT -#define PPPOS_SUPPORT PPP_SUPPORT -#endif - -#if PPP_SUPPORT - -/** - * NUM_PPP: Max PPP sessions. - */ -#ifndef NUM_PPP -#define NUM_PPP 1 -#endif - -/** - * PAP_SUPPORT==1: Support PAP. - */ -#ifndef PAP_SUPPORT -#define PAP_SUPPORT 0 -#endif - -/** - * CHAP_SUPPORT==1: Support CHAP. - */ -#ifndef CHAP_SUPPORT -#define CHAP_SUPPORT 0 -#endif - -/** - * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! - */ -#ifndef MSCHAP_SUPPORT -#define MSCHAP_SUPPORT 0 -#endif - -/** - * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! - */ -#ifndef CBCP_SUPPORT -#define CBCP_SUPPORT 0 -#endif - -/** - * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! - */ -#ifndef CCP_SUPPORT -#define CCP_SUPPORT 0 -#endif - -/** - * VJ_SUPPORT==1: Support VJ header compression. - */ -#ifndef VJ_SUPPORT -#define VJ_SUPPORT 0 -#endif - -/** - * MD5_SUPPORT==1: Support MD5 (see also CHAP). - */ -#ifndef MD5_SUPPORT -#define MD5_SUPPORT 0 -#endif - -/* - * Timeouts - */ -#ifndef FSM_DEFTIMEOUT -#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ -#endif - -#ifndef FSM_DEFMAXTERMREQS -#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ -#endif - -#ifndef FSM_DEFMAXCONFREQS -#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ -#endif - -#ifndef FSM_DEFMAXNAKLOOPS -#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ -#endif - -#ifndef UPAP_DEFTIMEOUT -#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ -#endif - -#ifndef UPAP_DEFREQTIME -#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ -#endif - -#ifndef CHAP_DEFTIMEOUT -#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ -#endif - -#ifndef CHAP_DEFTRANSMITS -#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ -#endif - -/* Interval in seconds between keepalive echo requests, 0 to disable. */ -#ifndef LCP_ECHOINTERVAL -#define LCP_ECHOINTERVAL 0 -#endif - -/* Number of unanswered echo requests before failure. */ -#ifndef LCP_MAXECHOFAILS -#define LCP_MAXECHOFAILS 3 -#endif - -/* Max Xmit idle time (in jiffies) before resend flag char. */ -#ifndef PPP_MAXIDLEFLAG -#define PPP_MAXIDLEFLAG 100 -#endif - -/* - * Packet sizes - * - * Note - lcp shouldn't be allowed to negotiate stuff outside these - * limits. See lcp.h in the pppd directory. - * (XXX - these constants should simply be shared by lcp.c instead - * of living in lcp.h) - */ -#define PPP_MTU 1500 /* Default MTU (size of Info field) */ -#ifndef PPP_MAXMTU -/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ -#define PPP_MAXMTU 1500 /* Largest MTU we allow */ -#endif -#define PPP_MINMTU 64 -#define PPP_MRU 1500 /* default MRU = max length of info field */ -#define PPP_MAXMRU 1500 /* Largest MRU we allow */ -#ifndef PPP_DEFMRU -#define PPP_DEFMRU 296 /* Try for this */ -#endif -#define PPP_MINMRU 128 /* No MRUs below this */ - - -#define MAXNAMELEN 256 /* max length of hostname or name for auth */ -#define MAXSECRETLEN 256 /* max length of password or secret */ - -#endif /* PPP_SUPPORT */ - -/* - -------------------------------------- - ---------- Checksum options ---------- - -------------------------------------- -*/ -/** - * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. - */ -#ifndef CHECKSUM_GEN_IP -#define CHECKSUM_GEN_IP 1 -#endif - -/** - * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. - */ -#ifndef CHECKSUM_GEN_UDP -#define CHECKSUM_GEN_UDP 1 -#endif - -/** - * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. - */ -#ifndef CHECKSUM_GEN_TCP -#define CHECKSUM_GEN_TCP 1 -#endif - -/** - * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. - */ -#ifndef CHECKSUM_CHECK_IP -#define CHECKSUM_CHECK_IP 1 -#endif - -/** - * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. - */ -#ifndef CHECKSUM_CHECK_UDP -#define CHECKSUM_CHECK_UDP 1 -#endif - -/** - * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. - */ -#ifndef CHECKSUM_CHECK_TCP -#define CHECKSUM_CHECK_TCP 1 -#endif - -/* - --------------------------------------- - ---------- Debugging options ---------- - --------------------------------------- -*/ -/** - * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is - * compared against this value. If it is smaller, then debugging - * messages are written. - */ -#ifndef LWIP_DBG_MIN_LEVEL -#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_OFF -#endif - -/** - * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable - * debug messages of certain types. - */ -#ifndef LWIP_DBG_TYPES_ON -#define LWIP_DBG_TYPES_ON LWIP_DBG_ON -#endif - -/** - * ETHARP_DEBUG: Enable debugging in etharp.c. - */ -#ifndef ETHARP_DEBUG -#define ETHARP_DEBUG LWIP_DBG_OFF -#endif - -/** - * NETIF_DEBUG: Enable debugging in netif.c. - */ -#ifndef NETIF_DEBUG -#define NETIF_DEBUG LWIP_DBG_OFF -#endif - -/** - * PBUF_DEBUG: Enable debugging in pbuf.c. - */ -#ifndef PBUF_DEBUG -#define PBUF_DEBUG LWIP_DBG_OFF -#endif - -/** - * API_LIB_DEBUG: Enable debugging in api_lib.c. - */ -#ifndef API_LIB_DEBUG -#define API_LIB_DEBUG LWIP_DBG_OFF -#endif - -/** - * API_MSG_DEBUG: Enable debugging in api_msg.c. - */ -#ifndef API_MSG_DEBUG -#define API_MSG_DEBUG LWIP_DBG_OFF -#endif - -/** - * SOCKETS_DEBUG: Enable debugging in sockets.c. - */ -#ifndef SOCKETS_DEBUG -#define SOCKETS_DEBUG LWIP_DBG_OFF -#endif - -/** - * ICMP_DEBUG: Enable debugging in icmp.c. - */ -#ifndef ICMP_DEBUG -#define ICMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * IGMP_DEBUG: Enable debugging in igmp.c. - */ -#ifndef IGMP_DEBUG -#define IGMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * INET_DEBUG: Enable debugging in inet.c. - */ -#ifndef INET_DEBUG -#define INET_DEBUG LWIP_DBG_OFF -#endif - -/** - * IP_DEBUG: Enable debugging for IP. - */ -#ifndef IP_DEBUG -#define IP_DEBUG LWIP_DBG_OFF -#endif - -/** - * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. - */ -#ifndef IP_REASS_DEBUG -#define IP_REASS_DEBUG LWIP_DBG_OFF -#endif - -/** - * RAW_DEBUG: Enable debugging in raw.c. - */ -#ifndef RAW_DEBUG -#define RAW_DEBUG LWIP_DBG_OFF -#endif - -/** - * MEM_DEBUG: Enable debugging in mem.c. - */ -#ifndef MEM_DEBUG -#define MEM_DEBUG LWIP_DBG_OFF -#endif - -/** - * MEMP_DEBUG: Enable debugging in memp.c. - */ -#ifndef MEMP_DEBUG -#define MEMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SYS_DEBUG: Enable debugging in sys.c. - */ -#ifndef SYS_DEBUG -#define SYS_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_DEBUG: Enable debugging for TCP. - */ -#ifndef TCP_DEBUG -#define TCP_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. - */ -#ifndef TCP_INPUT_DEBUG -#define TCP_INPUT_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. - */ -#ifndef TCP_FR_DEBUG -#define TCP_FR_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit - * timeout. - */ -#ifndef TCP_RTO_DEBUG -#define TCP_RTO_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. - */ -#ifndef TCP_CWND_DEBUG -#define TCP_CWND_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. - */ -#ifndef TCP_WND_DEBUG -#define TCP_WND_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. - */ -#ifndef TCP_OUTPUT_DEBUG -#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. - */ -#ifndef TCP_RST_DEBUG -#define TCP_RST_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. - */ -#ifndef TCP_QLEN_DEBUG -#define TCP_QLEN_DEBUG LWIP_DBG_OFF -#endif - -/** - * UDP_DEBUG: Enable debugging in UDP. - */ -#ifndef UDP_DEBUG -#define UDP_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCPIP_DEBUG: Enable debugging in tcpip.c. - */ -#ifndef TCPIP_DEBUG -#define TCPIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * PPP_DEBUG: Enable debugging for PPP. - */ -#ifndef PPP_DEBUG -#define PPP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SLIP_DEBUG: Enable debugging in slipif.c. - */ -#ifndef SLIP_DEBUG -#define SLIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * DHCP_DEBUG: Enable debugging in dhcp.c. - */ -#ifndef DHCP_DEBUG -#define DHCP_DEBUG LWIP_DBG_OFF -#endif - -/** - * AUTOIP_DEBUG: Enable debugging in autoip.c. - */ -#ifndef AUTOIP_DEBUG -#define AUTOIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. - */ -#ifndef SNMP_MSG_DEBUG -#define SNMP_MSG_DEBUG LWIP_DBG_OFF -#endif - -/** - * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. - */ -#ifndef SNMP_MIB_DEBUG -#define SNMP_MIB_DEBUG LWIP_DBG_OFF -#endif - -/** - * DNS_DEBUG: Enable debugging for DNS. - */ -#ifndef DNS_DEBUG -#define DNS_DEBUG LWIP_DBG_OFF -#endif - -#endif /* __LWIPOPT_H__ */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c deleted file mode 100644 index d9efe52..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -#include "lwip/lwipthread.h" -#include "web/web.h" - -static WORKING_AREA(waThread1, 64); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(900); - palSetPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(100); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 1 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Creates the LWIP threads (it changes priority internally). - */ - chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1, - lwip_thread, NULL); - - /* - * Creates the HTTP thread (it changes priority internally). - */ - chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1, - http_server, NULL); - - /* - * Normal main() thread activity. - */ - while (TRUE) { - chThdSleepMilliseconds(500); - if (!palReadPad(IOPORT2, PIOB_SW1)) - sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); - if (!palReadPad(IOPORT2, PIOB_SW2)) - TestThread(&SD1); - } - - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h deleted file mode 100644 index 02ce316..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AT91SAM7 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ -#define MAC_TRANSMIT_BUFFERS 2 -#define MAC_RECEIVE_BUFFERS 2 -#define MAC_BUFFERS_SIZE 1518 -#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_SAM7_USART0 TRUE -#define USE_SAM7_USART1 TRUE -#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) -#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt deleted file mode 100644 index d0d8721..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt +++ /dev/null @@ -1,34 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex SAM7-EX256 board. - -** The Demo ** - -The demo currently just flashes the LCD background using a thread and serves -HTTP requests at address 192.168.1.20 on port 80 (remember to change it IP -address into web.c in order to adapt it to your network settings). -The button SW1 prints an "Hello World!" string on COM1, the button SW2 -activates che ChibiOS/RT test suite, output on COM1. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. -The demo requires the patcher lwIP 1.3.1 stack, see: ./ext/readme.txt - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright -and are licensed under a different license, see the header present in all the -source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. -Also note that not all the files present in the Atmel library are distribuited -with ChibiOS/RT, you can find the whole library on the Atmel web site: - - http://www.atmel.com - -The lwIP stack also has its own license, please read the info into the included -lwIP distribution files. diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c deleted file mode 100644 index db00691..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * This file is a modified version of the lwIP web server demo. The original - * author is unknown because the file didn't contain any license information. - */ - -/** - * @file web.c - * @brief HTTP server wrapper thread code. - * @addtogroup WEB_THREAD - * @{ - */ - -#include "ch.h" - -#include "lwip/opt.h" -#include "lwip/arch.h" -#include "lwip/api.h" - -#include "web.h" - -#if LWIP_NETCONN - -static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n"; -static const char http_index_html[] = "Congrats!

Welcome to our lwIP HTTP server!

This is a small test page."; - -static void http_server_serve(struct netconn *conn) { - struct netbuf *inbuf; - char *buf; - u16_t buflen; - - /* Read the data from the port, blocking if nothing yet there. - We assume the request (the part we care about) is in one netbuf */ - inbuf = netconn_recv(conn); - - if (netconn_err(conn) == ERR_OK) { - netbuf_data(inbuf, (void **)&buf, &buflen); - - /* Is this an HTTP GET command? (only check the first 5 chars, since - there are other formats for GET, and we're keeping it very simple )*/ - if (buflen>=5 && - buf[0]=='G' && - buf[1]=='E' && - buf[2]=='T' && - buf[3]==' ' && - buf[4]=='/' ) { - - /* Send the HTML header - * subtract 1 from the size, since we dont send the \0 in the string - * NETCONN_NOCOPY: our data is const static, so no need to copy it - */ - netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY); - - /* Send our HTML page */ - netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY); - } - } - /* Close the connection (server closes in HTTP) */ - netconn_close(conn); - - /* Delete the buffer (netconn_recv gives us ownership, - so we have to make sure to deallocate the buffer) */ - netbuf_delete(inbuf); -} - -/** - * Stack area for the http thread. - */ -WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); - -/** - * HTTP server thread. - */ -msg_t http_server(void *p) { - struct netconn *conn, *newconn; - - (void)p; - - /* Create a new TCP connection handle */ - conn = netconn_new(NETCONN_TCP); - LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;); - - /* Bind to port 80 (HTTP) with default IP address */ - netconn_bind(conn, NULL, WEB_THREAD_PORT); - - /* Put the connection into LISTEN state */ - netconn_listen(conn); - - /* Goes to the final priority after initialization.*/ - chThdSetPriority(WEB_THREAD_PRIORITY); - - while(1) { - newconn = netconn_accept(conn); - http_server_serve(newconn); - netconn_delete(newconn); - } - return RDY_OK; -} - -#endif /* LWIP_NETCONN */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h deleted file mode 100644 index 2b0be04..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file web.h - * @brief HTTP server wrapper thread macros and structures. - * @addtogroup WEB_THREAD - * @{ - */ - -#ifndef _WEB_H_ -#define _WEB_H_ - -#ifndef WEB_THREAD_STACK_SIZE -#define WEB_THREAD_STACK_SIZE 1024 -#endif - -#ifndef WEB_THREAD_PORT -#define WEB_THREAD_PORT 80 -#endif - -#ifndef WEB_THREAD_PRIORITY -#define WEB_THREAD_PRIORITY (LOWPRIO + 2) -#endif - -extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); - -#ifdef __cplusplus -extern "C" { -#endif - msg_t http_server(void *p); -#ifdef __cplusplus -} -#endif - -#endif /* _WEB_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile deleted file mode 100644 index f775778..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ /dev/null @@ -1,198 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk -include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# List of the required uIP source files. -USRC = $(CHIBIOS)/ext/uip-1.0/uip/uip_arp.c \ - $(CHIBIOS)/ext/uip-1.0/uip/psock.c \ - $(CHIBIOS)/ext/uip-1.0/uip/uip.c \ - $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd.c \ - $(CHIBIOS)/ext/uip-1.0/apps/webserver/http-strings.c \ - $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd-fs.c \ - $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd-cgi.c - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(USRC) \ - $(CHIBIOS)/os/various/syscalls.c \ - $(CHIBIOS)/os/various/evtimer.c \ - web/webthread.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 \ - ./web $(CHIBIOS)/ext/uip-1.0/uip $(CHIBIOS)/ext/uip-1.0/apps/webserver - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld deleted file mode 100644 index 805c8a5..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld +++ /dev/null @@ -1,110 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AT91SAM7X256 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x100000, len = 256k - ram : org = 0x200020, len = 64k - 0x20 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.ctors) - *(.dtors) - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h deleted file mode 100644 index e438ebb..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC TRUE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/main.c deleted file mode 100644 index f667441..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/main.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -#include "web/webthread.h" - -static WORKING_AREA(waWebThread, 1024); -static WORKING_AREA(waThread1, 128); - -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palSetPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(100); - palClearPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(900); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Creates the blinker and web server threads. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waWebThread, sizeof(waWebThread), LOWPRIO, WebThread, NULL); - - /* - * Normal main() thread activity. - */ - while (TRUE) { - chThdSleepMilliseconds(500); - if (!palReadPad(IOPORT2, PIOB_SW1)) - sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); - if (!palReadPad(IOPORT2, PIOB_SW2)) - TestThread(&SD1); - } - - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h deleted file mode 100644 index 02ce316..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AT91SAM7 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ -#define MAC_TRANSMIT_BUFFERS 2 -#define MAC_RECEIVE_BUFFERS 2 -#define MAC_BUFFERS_SIZE 1518 -#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_SAM7_USART0 TRUE -#define USE_SAM7_USART1 TRUE -#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) -#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt deleted file mode 100644 index 80fddce..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt +++ /dev/null @@ -1,34 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex SAM7-EX256 board. - -** The Demo ** - -The demo currently just flashes the LCD background using a thread and serves -HTTP requests at address 192.168.1.20 on port 80 (remember to change it IP -address into webthread.c in order to adapt it to your network settings). -The button SW1 prints an "Hello World!" string on COM1, the button SW2 -activates che ChibiOS/RT test suite, output on COM1. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. -The demo requires the patcher uIP 1.0 stack, see: ./ext/readme.txt - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright -and are licensed under a different license, see the header present in all the -source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. -Also note that not all the files present in the Atmel library are distribuited -with ChibiOS/RT, you can find the whole library on the Atmel web site: - - http://www.atmel.com - -The uIP stack also has its own license, please read the info into the included -uIP distribution files. diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h deleted file mode 100644 index ef41b00..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __CC_ARCH_H__ -#define __CC_ARCH_H__ - -#define PACK_STRUCT_FIELD(x) x __attribute__((packed)) -#define PACK_STRUCT_STRUCT __attribute__((packed)) -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_END - -#endif /* __CC_ARCH_H__ */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h deleted file mode 100644 index 118a1b9..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ - */ - -#ifndef __CLOCK_ARCH_H__ -#define __CLOCK_ARCH_H__ - -#include - -typedef systime_t clock_time_t; -#define CLOCK_CONF_SECOND CH_FREQUENCY - -#endif /* __CLOCK_ARCH_H__ */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h deleted file mode 100644 index bc30715..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h +++ /dev/null @@ -1,159 +0,0 @@ -/** - * \addtogroup uipopt - * @{ - */ - -/** - * \name Project-specific configuration options - * @{ - * - * uIP has a number of configuration options that can be overridden - * for each project. These are kept in a project-specific uip-conf.h - * file and all configuration names have the prefix UIP_CONF. - */ - -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ - */ - -/** - * \file - * An example uIP configuration file - * \author - * Adam Dunkels - */ - -#ifndef __UIP_CONF_H__ -#define __UIP_CONF_H__ - -#include - -#include /* patched */ - -/** - * 8 bit datatype - * - * This typedef defines the 8-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint8_t u8_t; - -/** - * 16 bit datatype - * - * This typedef defines the 16-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint16_t u16_t; - -/** - * Statistics datatype - * - * This typedef defines the dataype used for keeping statistics in - * uIP. - * - * \hideinitializer - */ -typedef unsigned short uip_stats_t; - -/** - * Maximum number of TCP connections. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_CONNECTIONS 40 - -/** - * Maximum number of listening TCP ports. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_LISTENPORTS 40 - -/** - * uIP buffer size. - * - * \hideinitializer - */ -#define UIP_CONF_BUFFER_SIZE 1518 - -/** - * CPU byte order. - * - * \hideinitializer - */ -#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN - -/** - * Logging on or off - * - * \hideinitializer - */ -#define UIP_CONF_LOGGING 0 - -/** - * UDP support on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP 0 - -/** - * UDP checksums on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP_CHECKSUMS 1 - -/** - * uIP statistics on or off - * - * \hideinitializer - */ -#define UIP_CONF_STATISTICS 1 - -/* Here we include the header file for the application(s) we use in - our project. */ -/*#include "smtp.h"*/ -/*#include "hello-world.h"*/ -/*#include "telnetd.h"*/ -#include "webserver.h" -/*#include "dhcpc.h"*/ -/*#include "resolv.h"*/ -/*#include "webclient.h"*/ - -#endif /* __UIP_CONF_H__ */ - -/** @} */ -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c deleted file mode 100644 index 7ee143e..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include - -#include "ch.h" -#include "hal.h" -#include "evtimer.h" - -#include "uip.h" -#include "uip_arp.h" -#include "httpd.h" -#include "clock-arch.h" - -#define IPADDR0 192 -#define IPADDR1 168 -#define IPADDR2 1 -#define IPADDR3 20 - -#define SEND_TIMEOUT 50 - -static const struct uip_eth_addr macaddr = { - {0xC2, 0xAF, 0x51, 0x03, 0xCF, 0x46} -}; - -#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) - -/* - * uIP send function wrapping the EMAC functions. - */ -static void network_device_send(void) { - MACTransmitDescriptor td; - - if (macWaitTransmitDescriptor(Ð1, &td, MS2ST(SEND_TIMEOUT)) == RDY_OK) { - if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) - macWriteTransmitDescriptor(&td, uip_buf, uip_len); - else { - macWriteTransmitDescriptor(&td, uip_buf, UIP_LLH_LEN + UIP_TCPIP_HLEN); - macWriteTransmitDescriptor(&td, uip_appdata, - uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); - } - macReleaseTransmitDescriptor(&td); - } - /* Dropped... */ -} - -/* - * uIP receive function wrapping the EMAC function. - */ -static size_t network_device_read(void) { - MACReceiveDescriptor rd; - size_t size; - - if (macWaitReceiveDescriptor(Ð1, &rd, TIME_IMMEDIATE) != RDY_OK) - return 0; - size = rd.rd_size; - macReadReceiveDescriptor(&rd, uip_buf, size); - macReleaseReceiveDescriptor(&rd); - return size; -} - -void clock_init(void) {} - -clock_time_t clock_time( void ) -{ - return chTimeNow(); -} - -/* - * TCP/IP periodic timer. - */ -static void PeriodicTimerHandler(eventid_t id) { - int i; - - (void)id; - for (i = 0; i < UIP_CONNS; i++) { - uip_periodic(i); - if (uip_len > 0) { - uip_arp_out(); - network_device_send(); - } - } -} - -/* - * ARP periodic timer. - */ -static void ARPTimerHandler(eventid_t id) { - - (void)id; - (void)macPollLinkStatus(Ð1); - uip_arp_timer(); -} - -/* - * Ethernet frame received. - */ -static void FrameReceivedHandler(eventid_t id) { - - (void)id; - while ((uip_len = network_device_read()) > 0) { - if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); - uip_input(); - if (uip_len > 0) { - uip_arp_out(); - network_device_send(); - } - } - else if (BUF->type == HTONS(UIP_ETHTYPE_ARP)) { - uip_arp_arpin(); - if (uip_len > 0) - network_device_send(); - } - } -} - -#define FRAME_RECEIVED_ID 0 -#define PERIODIC_TIMER_ID 1 -#define ARP_TIMER_ID 2 - -static const evhandler_t evhndl[] = { - FrameReceivedHandler, - PeriodicTimerHandler, - ARPTimerHandler -}; - -msg_t WebThread(void *p) { - EvTimer evt1, evt2; - EventListener el0, el1, el2; - uip_ipaddr_t ipaddr; - - (void)p; - - /* - * Event sources setup. - */ - chEvtRegister(macGetReceiveEventSource(Ð1), &el0, FRAME_RECEIVED_ID); - chEvtPend(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ - - evtInit(&evt1, MS2ST(500)); - evtStart(&evt1); - chEvtRegister(&evt1.et_es, &el1, PERIODIC_TIMER_ID); - - evtInit(&evt2, S2ST(10)); - evtStart(&evt2); - chEvtRegister(&evt2.et_es, &el2, ARP_TIMER_ID); - - /* - * EMAC settings. - */ - macSetAddress(Ð1, &macaddr.addr[0]); - (void)macPollLinkStatus(Ð1); - - /* - * uIP initialization. - */ - uip_init(); - uip_setethaddr(macaddr); - uip_ipaddr(ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3); - uip_sethostaddr(ipaddr); - httpd_init(); - - while (TRUE) { - chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h b/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h deleted file mode 100644 index f5bdcba..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _WEBTHREAD_H_ -#define _WEBTHREAD_H_ - -#ifdef __cplusplus -extern "C" { -#endif - msg_t WebThread(void *p); - #ifdef __cplusplus -} -#endif - -#endif /* _WEBTHREAD_H_ */ diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/Makefile deleted file mode 100644 index ace0b2b..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/Makefile +++ /dev/null @@ -1,190 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk -include $(CHIBIOS)/ext/fatfs/fatfs.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(FATFSSRC) \ - $(BOARDSRC) \ - ${BOARDPATH}/buzzer.c \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(FATFSINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTDOUT_SD=SD1 -DSTDIN_SD=SD1 - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/ch.ld deleted file mode 100644 index 9529a23..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/ch.ld +++ /dev/null @@ -1,113 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC2148 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.ctors) - *(.dtors) - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/halconf.h deleted file mode 100644 index 32a85fc..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/main.c b/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/main.c deleted file mode 100644 index e02dc96..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/main.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include -#include - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "evtimer.h" -#include "buzzer.h" - -#include "ff.h" - -/** - * @brief FS object. - */ -FATFS MMC_FS; - -/** - * MMC driver instance. - */ -MMCDriver MMCD1; - -/* FS mounted and ready.*/ -static bool_t fs_ready = FALSE; - -/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0).*/ -static SPIConfig hs_spicfg = { - IOPORT1, - PA_SSEL1, - CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), - 0, - 2 -}; - -/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0).*/ -static SPIConfig ls_spicfg = { - IOPORT1, - PA_SSEL1, - CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), - 0, - 254 -}; - -/* MMC configuration (empty).*/ -static const MMCConfig mmc_cfg = {}; - -/* Card insertion verification.*/ -static bool_t mmc_is_inserted(void) { - return !palReadPad(IOPORT2, PB_CP1); -} - -/* Card protection verification.*/ -static bool_t mmc_is_protected(void) { - return palReadPad(IOPORT2, PB_WP1); -} - -/* Generic large buffer.*/ -uint8_t fbuff[1024]; - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(200); - palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(800); - palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); - chThdSleepMilliseconds(200); - palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(800); - } - return 0; -} - -/* - * Yellow LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread2, 128); -static msg_t Thread2(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT1, PA_LEDUSB); - chThdSleepMilliseconds(200); - palSetPad(IOPORT1, PA_LEDUSB); - chThdSleepMilliseconds(300); - } - return 0; -} - -static FRESULT scan_files(char *path) -{ - FRESULT res; - FILINFO fno; - DIR dir; - int i; - char *fn; - - res = f_opendir(&dir, path); - if (res == FR_OK) { - i = strlen(path); - for (;;) { - res = f_readdir(&dir, &fno); - if (res != FR_OK || fno.fname[0] == 0) - break; - if (fno.fname[0] == '.') - continue; - fn = fno.fname; - if (fno.fattrib & AM_DIR) { - siprintf(&path[i], "/%s", fn); - res = scan_files(path); - if (res != FR_OK) - break; - path[i] = 0; - } - else { - iprintf("%s/%s\r\n", path, fn); - } - } - } - return res; -} - -/* - * Executed as event handler at 500mS intervals. - */ -static void TimerHandler(eventid_t id) { - - (void)id; - if (!palReadPad(IOPORT1, PA_BUTTON1)) { - if (fs_ready) { - FRESULT err; - uint32_t clusters; - FATFS *fsp; - - err = f_getfree("/", &clusters, &fsp); - if (err != FR_OK) { - iprintf("FS: f_getfree() failed\r\n"); - return; - } - iprintf("FS: %lu free clusters, %u sectors per cluster, %lu bytes free\r\n", - clusters, MMC_FS.csize, - clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); - fbuff[0] = 0; - scan_files((char *)fbuff); - } - } - else if (!palReadPad(IOPORT1, PA_BUTTON2)) { - static WORKING_AREA(waTestThread, 256); - Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), - NORMALPRIO, TestThread, &SD1); - chThdWait(tp); - buzzPlay(500, MS2ST(100)); - } -} - -/* - * MMC card insertion event. - */ -static void InsertHandler(eventid_t id) { - FRESULT err; - - (void)id; - buzzPlayWait(1000, MS2ST(100)); - buzzPlayWait(2000, MS2ST(100)); - iprintf("MMC: inserted\r\n"); - /* - * On insertion MMC initialization and FS mount. - */ - iprintf("MMC: initialization "); - if (mmcConnect(&MMCD1)) { - iprintf("failed\r\n"); - return; - } - iprintf("ok\r\n"); - iprintf("FS: mount "); - err = f_mount(0, &MMC_FS); - if (err != FR_OK) { - iprintf("failed\r\n"); - mmcDisconnect(&MMCD1); - return; - } - fs_ready = TRUE; - iprintf("ok\r\n"); - buzzPlay(440, MS2ST(200)); -} - -/* - * MMC card removal event. - */ -static void RemoveHandler(eventid_t id) { - - (void)id; - iprintf("MMC: removed\r\n"); - fs_ready = FALSE; - buzzPlayWait(2000, MS2ST(100)); - buzzPlayWait(1000, MS2ST(100)); -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - static const evhandler_t evhndl[] = { - TimerHandler, - InsertHandler, - RemoveHandler - }; - static EvTimer evt; - struct EventListener el0, el1, el2; - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Buzzer driver initialization. - */ - buzzInit(); - - /* - * Initializes the MMC driver to work with SPI2. - */ - mmcObjectInit(&MMCD1, &SPID1, - &ls_spicfg, &hs_spicfg, - mmc_is_protected, mmc_is_inserted); - mmcStart(&MMCD1, &mmc_cfg); - - /* - * Creates the blinker threads. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and listen for events. - */ - evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - chEvtRegister(&MMCD1.mmc_inserted_event, &el1, 1); - chEvtRegister(&MMCD1.mmc_removed_event, &el2, 2); - while (TRUE)// chThdSleepMilliseconds(50); - chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h deleted file mode 100644 index 884af1d..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC214x drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_LPC214x_UART0 TRUE -#define USE_LPC214x_UART1 TRUE -#define LPC214x_UART_FIFO_PRELOAD 16 -#define LPC214x_UART0_PRIORITY 1 -#define LPC214x_UART1_PRIORITY 2 - -/* - * SPI driver system settings. - */ -#define USE_LPC214x_SPI1 TRUE diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/readme.txt deleted file mode 100644 index 68ade5c..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-FATFS-GCC/readme.txt +++ /dev/null @@ -1,19 +0,0 @@ -***************************************************************************** -** ChibiOS/RT + FatFS demo for LPC214x. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex LPC-P2148 board. The port on other boards or other -members of the LPC2000 family should be an easy task. - -** The Demo ** - -The demo blinks the leds on the board by using multiple threads. -By pressing button 1 a directory scan on the MMC slot is performed, by -pressing the button 2 the test suite is activated on serial port 1. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/Makefile b/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/Makefile deleted file mode 100644 index b2a81db..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/Makefile +++ /dev/null @@ -1,184 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -fno-exceptions -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(CHIBIOS)/os/various/ch.cpp main.cpp - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/ch.ld b/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/ch.ld deleted file mode 100644 index 9529a23..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/ch.ld +++ /dev/null @@ -1,113 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC2148 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.ctors) - *(.dtors) - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/chconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/halconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/main.cpp b/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/main.cpp deleted file mode 100644 index 251e88e..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/main.cpp +++ /dev/null @@ -1,189 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.hpp" -#include "hal.h" -#include "test.h" -#include "evtimer.h" - -#define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) - -using namespace chibios_rt; - -/* - * LED blink sequences. - * NOTE: Sequences must always be terminated by a GOTO instruction. - * NOTE: The sequencer language could be easily improved but this is outside - * the scope of this demo. - */ -#define SLEEP 0 -#define GOTO 1 -#define STOP 2 -#define BITCLEAR 3 -#define BITSET 4 - -typedef struct { - uint8_t action; - uint32_t value; -} seqop_t; - -// Flashing sequence for LED1. -static const seqop_t LED1_sequence[] = -{ - {BITCLEAR, PAL_PORT_BIT(PA_LED1)}, - {SLEEP, 200}, - {BITSET, PAL_PORT_BIT(PA_LED1)}, - {SLEEP, 1800}, - {GOTO, 0} -}; - -// Flashing sequence for LED2. -static const seqop_t LED2_sequence[] = -{ - {SLEEP, 1000}, - {BITCLEAR, PAL_PORT_BIT(PA_LED2)}, - {SLEEP, 200}, - {BITSET, PAL_PORT_BIT(PA_LED2)}, - {SLEEP, 1800}, - {GOTO, 1} -}; - -// Flashing sequence for LED3. -static const seqop_t LED3_sequence[] = -{ - {BITCLEAR, PAL_PORT_BIT(PA_LEDUSB)}, - {SLEEP, 200}, - {BITSET, PAL_PORT_BIT(PA_LEDUSB)}, - {SLEEP, 300}, - {GOTO, 0} -}; - -/* - * Sequencer thread class. It can drive LEDs or other output pins. - * Any sequencer is just an instance of this class, all the details are - * totally encapsulated and hidden to the application level. - */ -class SequencerThread : public EnhancedThread<128> { -private: - const seqop_t *base, *curr; // Thread local variables. - -protected: - virtual msg_t Main(void) { - while (true) { - switch(curr->action) { - case SLEEP: - Sleep(curr->value); - break; - case GOTO: - curr = &base[curr->value]; - continue; - case STOP: - return 0; - case BITCLEAR: - palClearPort(IOPORT1, curr->value); - break; - case BITSET: - palSetPort(IOPORT1, curr->value); - break; - } - curr++; - } - } - -public: - SequencerThread(const seqop_t *sequence) : EnhancedThread<128>("sequencer") { - - base = curr = sequence; - } -}; - -/* - * Tester thread class. This thread executes the test suite. - */ -class TesterThread : public EnhancedThread<128> { - -protected: - virtual msg_t Main(void) { - - return TestThread(&SD1); - } - -public: - TesterThread(void) : EnhancedThread<128>("tester") { - } -}; - -/* - * Executed as an event handler at 500mS intervals. - */ -static void TimerHandler(eventid_t id) { - - (void)id; - if (!(palReadPort(IOPORT1) & BOTH_BUTTONS)) { // Both buttons - TesterThread tester; - tester.Wait(); - }; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - static const evhandler_t evhndl[] = { - TimerHandler - }; - static EvTimer evt; - struct EventListener el0; - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - evtInit(&evt, 500); // Initializes an event timer. - evtStart(&evt); // Starts the event timer. - chEvtRegister(&evt.et_es, &el0, 0); // Registers a listener on the source. - - /* - * Starts several instances of the SequencerThread class, each one operating - * on a different LED. - */ - SequencerThread blinker1(LED1_sequence); - SequencerThread blinker2(LED2_sequence); - SequencerThread blinker3(LED3_sequence); - - /* - * Serves timer events. - */ - while (true) - Event::Dispatch(evhndl, Event::WaitOne(ALL_EVENTS)); - - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/mcuconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/mcuconf.h deleted file mode 100644 index 884af1d..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/mcuconf.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC214x drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_LPC214x_UART0 TRUE -#define USE_LPC214x_UART1 TRUE -#define LPC214x_UART_FIFO_PRELOAD 16 -#define LPC214x_UART0_PRIORITY 1 -#define LPC214x_UART1_PRIORITY 2 - -/* - * SPI driver system settings. - */ -#define USE_LPC214x_SPI1 TRUE diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/readme.txt b/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/readme.txt deleted file mode 100644 index 0b53385..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-G++/readme.txt +++ /dev/null @@ -1,25 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI LPC214X using G++. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex LPC-P2148 board. The port on other boards or other -members of the LPC2000 family should be an easy task. - -** The Demo ** - -The demo blinks the leds on the board by using multiple threads implemented -as C++ classes. Pressing both buttons activates the test procedure on the -serial port 1. - -NOTE: the C++ GNU compiler can produce code sizes comparable to C if you - don't use RTTI and standard libraries, those are disabled by default - in the makefile. You can enable them if you have a lot of program space - available. It is possible to use a lot of C++ features without using - runtimes, just see the demo. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/Makefile b/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/Makefile deleted file mode 100644 index caa6149..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/Makefile +++ /dev/null @@ -1,184 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/ch.ld deleted file mode 100644 index 9529a23..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/ch.ld +++ /dev/null @@ -1,113 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC2148 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - *(.ctors) - *(.dtors) - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/main.c b/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/main.c deleted file mode 100644 index 0ac030b..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/main.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -#define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(200); - palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(800); - palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); - chThdSleepMilliseconds(200); - palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(800); - } - return 0; -} - -/* - * Yellow LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread2, 128); -static msg_t Thread2(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT1, PA_LEDUSB); - chThdSleepMilliseconds(200); - palSetPad(IOPORT1, PA_LEDUSB); - chThdSleepMilliseconds(300); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * If a button is pressed during the reset then the blinking leds threads - * are not started in order to make accurate benchmarks. - */ - if ((palReadPort(IOPORT1) & BOTH_BUTTONS) == BOTH_BUTTONS) { - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); - } - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the buttons state. - */ - while (TRUE) { - if (!palReadPad(IOPORT1, PA_BUTTON1)) - sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); - if (!palReadPad(IOPORT1, PA_BUTTON2)) - TestThread(&SD1); - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/mcuconf.h deleted file mode 100644 index 884af1d..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/mcuconf.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC214x drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_LPC214x_UART0 TRUE -#define USE_LPC214x_UART1 TRUE -#define LPC214x_UART_FIFO_PRELOAD 16 -#define LPC214x_UART0_PRIORITY 1 -#define LPC214x_UART1_PRIORITY 2 - -/* - * SPI driver system settings. - */ -#define USE_LPC214x_SPI1 TRUE diff --git a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/readme.txt deleted file mode 100644 index e800b5a..0000000 --- a/ChibiOS_2.0.8/demos/ARM7-LPC214x-GCC/readme.txt +++ /dev/null @@ -1,22 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI LPC214X. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex LPC-P2148 board. The port on other boards or other -members of the LPC2000 family should be an easy task. - -** The Demo ** - -The demo blinks the leds on the board by using multiple threads. By pressing -the buttons on the board it is possible to send a message over the serial -port or activate the test procedure. -See main.c for details. Buzzer.c contains an interesting device driver -example that uses a physical timer for the waveform generation and a virtual -timer for the sound duration. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. diff --git a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/Makefile b/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/Makefile deleted file mode 100644 index bec884f..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/Makefile +++ /dev/null @@ -1,192 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1114/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC11xx/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m0 - -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DLPC1114 -D__NEWLIB__ - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/ch.ld deleted file mode 100644 index 30303cc..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/ch.ld +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC1114 memory setup. - */ -__main_stack_size__ = 0x0100; -__process_stack_size__ = 0x0100; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 32k - ram : org = 0x10000000, len = 8k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ctors : - { - PROVIDE(_ctors_start_ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(_ctors_end_ = .); - } > flash - - .dtors : - { - PROVIDE(_dtors_start_ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(_dtors_end_ = .); - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/main.c b/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/main.c deleted file mode 100644 index aceab8f..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/main.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -/* - * Red LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(GPIO0, GPIO0_LED2); - chThdSleepMilliseconds(500); - palSetPad(GPIO0, GPIO0_LED2); - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * RGB LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread2, 128); -static msg_t Thread2(void *arg) { - - (void)arg; - while (TRUE) { - palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | - PAL_PORT_BIT(GPIO1_LED3R) | - PAL_PORT_BIT(GPIO1_LED3G)); - chThdSleepMilliseconds(250); - palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | - PAL_PORT_BIT(GPIO1_LED3R) | - PAL_PORT_BIT(GPIO1_LED3G)); - palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B)); - chThdSleepMilliseconds(250); - palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | - PAL_PORT_BIT(GPIO1_LED3R) | - PAL_PORT_BIT(GPIO1_LED3G)); - palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3R)); - chThdSleepMilliseconds(250); - palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | - PAL_PORT_BIT(GPIO1_LED3R) | - PAL_PORT_BIT(GPIO1_LED3G)); - palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3G)); - chThdSleepMilliseconds(250); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 1 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Creates the blinker threads. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. - */ - while (TRUE) { - if (!palReadPad(GPIO0, GPIO0_SW3)) - TestThread(&SD1); - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/mcuconf.h deleted file mode 100644 index 477bd48..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM0-LPC1114-GCC/mcuconf.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC1114 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...highest. - */ - -/* - * HAL driver system settings. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/Makefile b/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/Makefile deleted file mode 100644 index 604b821..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/Makefile +++ /dev/null @@ -1,193 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1343/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC13xx/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m3 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DLPC1348 -D__NEWLIB__ - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/ch.ld deleted file mode 100644 index ad0ec6b..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/ch.ld +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC1343 memory setup. - */ -__main_stack_size__ = 0x0100; -__process_stack_size__ = 0x0100; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 32k - ram : org = 0x10000000, len = 8k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ctors : - { - PROVIDE(_ctors_start_ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(_ctors_end_ = .); - } > flash - - .dtors : - { - PROVIDE(_dtors_start_ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(_dtors_end_ = .); - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/main.c b/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/main.c deleted file mode 100644 index aceab8f..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/main.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -/* - * Red LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(GPIO0, GPIO0_LED2); - chThdSleepMilliseconds(500); - palSetPad(GPIO0, GPIO0_LED2); - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * RGB LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread2, 128); -static msg_t Thread2(void *arg) { - - (void)arg; - while (TRUE) { - palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | - PAL_PORT_BIT(GPIO1_LED3R) | - PAL_PORT_BIT(GPIO1_LED3G)); - chThdSleepMilliseconds(250); - palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | - PAL_PORT_BIT(GPIO1_LED3R) | - PAL_PORT_BIT(GPIO1_LED3G)); - palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B)); - chThdSleepMilliseconds(250); - palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | - PAL_PORT_BIT(GPIO1_LED3R) | - PAL_PORT_BIT(GPIO1_LED3G)); - palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3R)); - chThdSleepMilliseconds(250); - palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | - PAL_PORT_BIT(GPIO1_LED3R) | - PAL_PORT_BIT(GPIO1_LED3G)); - palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3G)); - chThdSleepMilliseconds(250); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 1 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Creates the blinker threads. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. - */ - while (TRUE) { - if (!palReadPad(GPIO0, GPIO0_SW3)) - TestThread(&SD1); - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/mcuconf.h deleted file mode 100644 index 386835a..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-LPC1343-GCC/mcuconf.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * LPC13xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - * - * IRQ priorities: - * 7...0 Lowest...highest. - */ - -/* - * HAL driver system settings. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile deleted file mode 100644 index bc7c278..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ /dev/null @@ -1,208 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FWLIB),) - USE_FWLIB = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk -include $(CHIBIOS)/ext/fatfs/fatfs.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(FATFSSRC) \ - $(CHIBIOS)/os/various/shell.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(FATFSINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m3 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -ifeq ($(USE_FWLIB),yes) - include $(CHIBIOS)/ext/stm32lib/stm32lib.mk - CSRC += $(STM32SRC) - INCDIR += $(STM32INC) - USE_OPT += -DUSE_STDPERIPH_DRIVER -endif - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld deleted file mode 100644 index d64ee32..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * ST32F103 memory setup. - */ -__main_stack_size__ = 0x0400; -__process_stack_size__ = 0x0400; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x08000000, len = 128k - ram : org = 0x20000000, len = 20k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ctors : - { - PROVIDE(_ctors_start_ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(_ctors_end_ = .); - } > flash - - .dtors : - { - PROVIDE(_dtors_start_ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(_dtors_end_ = .); - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h deleted file mode 100644 index 32a85fc..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/main.c deleted file mode 100644 index cfee329..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include -#include - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "shell.h" -#include "evtimer.h" - -#include "ff.h" - -/*===========================================================================*/ -/* MMC/SPI related. */ -/*===========================================================================*/ - -/** - * @brief FS object. - */ -FATFS MMC_FS; - -/** - * MMC driver instance. - */ -MMCDriver MMCD1; - -/* FS mounted and ready.*/ -static bool_t fs_ready = FALSE; - -/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/ -static SPIConfig hs_spicfg = {IOPORT2, GPIOB_SPI2NSS, 0}; - -/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).*/ -static SPIConfig ls_spicfg = {IOPORT2, GPIOB_SPI2NSS, SPI_CR1_BR_2 | SPI_CR1_BR_1}; - -/* MMC configuration (empty).*/ -static const MMCConfig mmc_cfg = {}; - -/* Card insertion verification.*/ -static bool_t mmc_is_inserted(void) {return palReadPad(IOPORT3, GPIOC_MMCCP);} - -/* Card protection verification.*/ -static bool_t mmc_is_protected(void) {return !palReadPad(IOPORT3, GPIOC_MMCWP);} - -/* Generic large buffer.*/ -uint8_t fbuff[1024]; - -static FRESULT scan_files(char *path) -{ - FRESULT res; - FILINFO fno; - DIR dir; - int i; - char *fn; - - res = f_opendir(&dir, path); - if (res == FR_OK) { - i = strlen(path); - for (;;) { - res = f_readdir(&dir, &fno); - if (res != FR_OK || fno.fname[0] == 0) - break; - if (fno.fname[0] == '.') - continue; - fn = fno.fname; - if (fno.fattrib & AM_DIR) { - siprintf(&path[i], "/%s", fn); - res = scan_files(path); - if (res != FR_OK) - break; - path[i] = 0; - } - else { - iprintf("%s/%s\r\n", path, fn); - } - } - } - return res; -} - -/*===========================================================================*/ -/* Command line related. */ -/*===========================================================================*/ - -#define SHELL_WA_SIZE THD_WA_SIZE(1024) -#define TEST_WA_SIZE THD_WA_SIZE(256) - -static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { - size_t n, size; - char buf[52]; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: mem"); - return; - } - n = chHeapStatus(NULL, &size); - siprintf(buf, "core free memory : %u bytes", chCoreStatus()); - shellPrintLine(chp, buf); - siprintf(buf, "heap fragments : %u", n); - shellPrintLine(chp, buf); - siprintf(buf, "heap free total : %u bytes", size); - shellPrintLine(chp, buf); -} - -static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSG", - "WTMSG", - "FINAL" - }; - Thread *tp; - char buf[60]; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: threads"); - return; - } - shellPrintLine(chp, " addr stack prio refs state time"); - tp = chRegFirstThread(); - do { - siprintf(buf, "%8lx %8lx %4u %4i %9s %u", - (uint32_t)tp, (uint32_t)tp->p_ctx.r13, - (unsigned int)tp->p_prio, tp->p_refs - 1, - states[tp->p_state], (unsigned int)tp->p_time); - shellPrintLine(chp, buf); - tp = chRegNextThread(tp); - } while (tp != NULL); -} - -static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { - Thread *tp; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: test"); - return; - } - tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), - TestThread, chp); - if (tp == NULL) { - shellPrintLine(chp, "out of memory"); - return; - } - chThdWait(tp); -} - -static void cmd_tree(BaseChannel *chp, int argc, char *argv[]) { - FRESULT err; - uint32_t clusters; - FATFS *fsp; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: tree"); - return; - } - if (!fs_ready) { - shellPrintLine(chp, "File System not mounted"); - return; - } - err = f_getfree("/", &clusters, &fsp); - if (err != FR_OK) { - shellPrintLine(chp, "FS: f_getfree() failed"); - return; - } - siprintf((void *)fbuff, - "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free", - clusters, (uint32_t)MMC_FS.csize, - clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); - shellPrintLine(chp, (void *)fbuff); - fbuff[0] = 0; - scan_files((char *)fbuff); -} - -static const ShellCommand commands[] = { - {"mem", cmd_mem}, - {"threads", cmd_threads}, - {"test", cmd_test}, - {"tree", cmd_tree}, - {NULL, NULL} -}; - -static const ShellConfig shell_cfg1 = { - (BaseChannel *)&SD2, - commands -}; - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palTogglePad(IOPORT3, GPIOC_LED); - if (fs_ready) - chThdSleepMilliseconds(200); - else - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * MMC card insertion event. - */ -static void InsertHandler(eventid_t id) { - FRESULT err; - - (void)id; - /* - * On insertion MMC initialization and FS mount. - */ - if (mmcConnect(&MMCD1)) { - return; - } - err = f_mount(0, &MMC_FS); - if (err != FR_OK) { - mmcDisconnect(&MMCD1); - return; - } - fs_ready = TRUE; -} - -/* - * MMC card removal event. - */ -static void RemoveHandler(eventid_t id) { - - (void)id; - fs_ready = FALSE; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - static const evhandler_t evhndl[] = { - InsertHandler, - RemoveHandler - }; - Thread *shelltp = NULL; - struct EventListener el0, el1; - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD2, NULL); - - /* - * Shell manager initialization. - */ - shellInit(); - - /* - * Initializes the MMC driver to work with SPI2. - */ - palSetPadMode(IOPORT2, GPIOB_SPI2NSS, PAL_MODE_OUTPUT_PUSHPULL); - palSetPad(IOPORT2, GPIOB_SPI2NSS); - mmcObjectInit(&MMCD1, &SPID2, - &ls_spicfg, &hs_spicfg, - mmc_is_protected, mmc_is_inserted); - mmcStart(&MMCD1, &mmc_cfg); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and listen for events. - */ - chEvtRegister(&MMCD1.mmc_inserted_event, &el0, 0); - chEvtRegister(&MMCD1.mmc_removed_event, &el1, 1); - while (TRUE) { - if (!shelltp) - shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); - else if (chThdTerminated(shelltp)) { - chThdRelease(shelltp); /* Recovers memory of the previous shell. */ - shelltp = NULL; /* Triggers spawning of a new shell. */ - } - chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h deleted file mode 100644 index c862cf9..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * STM32 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -/* - * HAL driver system settings. - */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_MCO STM32_MCO_NOCLOCK - -/* - * ADC driver system settings. - */ -#define USE_STM32_ADC1 TRUE -#define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() - -/* - * CAN driver system settings. - */ -#define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 11 - -/* - * PWM driver system settings. - */ -#define USE_STM32_PWM1 TRUE -#define USE_STM32_PWM2 FALSE -#define USE_STM32_PWM3 FALSE -#define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM4_IRQ_PRIORITY 7 - -/* - * SERIAL driver system settings. - */ -#define USE_STM32_USART1 FALSE -#define USE_STM32_USART2 TRUE -#define USE_STM32_USART3 FALSE -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define USE_STM32_UART4 FALSE -#define USE_STM32_UART5 FALSE -#endif -#define STM32_USART1_PRIORITY 12 -#define STM32_USART2_PRIORITY 12 -#define STM32_USART3_PRIORITY 12 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 12 -#define STM32_UART5_PRIORITY 12 -#endif - -/* - * SPI driver system settings. - */ -#define USE_STM32_SPI1 TRUE -#define USE_STM32_SPI2 TRUE -#define STM32_SPI1_DMA_PRIORITY 2 -#define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt deleted file mode 100644 index 1603a6b..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt +++ /dev/null @@ -1,33 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex STM32-P103 board. - -** The Demo ** - -This demo shows how to integrate the FatFs file system and use the SPI and MMC -drivers. -The demo flashes the board LED using a thread and monitors the MMC slot for -a card insertion. When a card is inserted then the file system is mounted -and the LED flashes faster. -A command line shell is spawned on SD2, all the interaction with the demo is -performed using the command shell, type "help" for a list of the available -commands. - -** Build Procedure ** - -The demo has been tested by using the free Codesourcery GCC-based toolchain, -YAGARTO and an experimental WinARM build including GCC 4.3.0. -Just modify the TRGT line in the makefile in order to use different GCC ports. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -ST Microelectronics and are licensed under a different license. -Also note that not all the files present in the ST library are distributed -with ChibiOS/RT, you can find the whole library on the ST web site: - - http://www.st.com diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/Makefile b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/Makefile deleted file mode 100644 index d460644..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FWLIB),) - USE_FWLIB = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m3 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DCORTEX_USE_BASEPRI=TRUE - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -ifeq ($(USE_FWLIB),yes) - include $(CHIBIOS)/ext/stm32lib/stm32lib.mk - CSRC += $(STM32SRC) - INCDIR += $(STM32INC) - USE_OPT += -DUSE_STDPERIPH_DRIVER -endif - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ch.ld deleted file mode 100644 index d64ee32..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ch.ld +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * ST32F103 memory setup. - */ -__main_stack_size__ = 0x0400; -__process_stack_size__ = 0x0400; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x08000000, len = 128k - ram : org = 0x20000000, len = 20k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ctors : - { - PROVIDE(_ctors_start_ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(_ctors_end_ = .); - } > flash - - .dtors : - { - PROVIDE(_dtors_start_ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(_dtors_end_ = .); - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/main.c b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/main.c deleted file mode 100644 index 2473b8a..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/main.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - palSetPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD2, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. - */ - while (TRUE) { - if (palReadPad(IOPORT1, GPIOA_BUTTON)) - TestThread(&SD2); - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/mcuconf.h deleted file mode 100644 index c862cf9..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * STM32 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -/* - * HAL driver system settings. - */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_MCO STM32_MCO_NOCLOCK - -/* - * ADC driver system settings. - */ -#define USE_STM32_ADC1 TRUE -#define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() - -/* - * CAN driver system settings. - */ -#define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 11 - -/* - * PWM driver system settings. - */ -#define USE_STM32_PWM1 TRUE -#define USE_STM32_PWM2 FALSE -#define USE_STM32_PWM3 FALSE -#define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM4_IRQ_PRIORITY 7 - -/* - * SERIAL driver system settings. - */ -#define USE_STM32_USART1 FALSE -#define USE_STM32_USART2 TRUE -#define USE_STM32_USART3 FALSE -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define USE_STM32_UART4 FALSE -#define USE_STM32_UART5 FALSE -#endif -#define STM32_USART1_PRIORITY 12 -#define STM32_USART2_PRIORITY 12 -#define STM32_USART3_PRIORITY 12 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 12 -#define STM32_UART5_PRIORITY 12 -#endif - -/* - * SPI driver system settings. - */ -#define USE_STM32_SPI1 TRUE -#define USE_STM32_SPI2 TRUE -#define STM32_SPI1_DMA_PRIORITY 2 -#define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/readme.txt deleted file mode 100644 index c373926..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/readme.txt +++ /dev/null @@ -1,28 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex STM32-P103 board. - -** The Demo ** - -The demo flashes the board LED using a thread, by pressing the button located -on the board the test procedure is activated with output on the serial port -COM2 (USART2). - -** Build Procedure ** - -The demo has been tested by using the free Codesourcery GCC-based toolchain, -YAGARTO and an experimental WinARM build including GCC 4.3.0. -Just modify the TRGT line in the makefile in order to use different GCC ports. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -ST Microelectronics and are licensed under a different license. -Also note that not all the files present in the ST library are distribited -with ChibiOS/RT, you can find the whole library on the ST web site: - - http://www.st.com diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp deleted file mode 100644 index a0ae9e6..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp +++ /dev/null @@ -1,139 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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- - - - - \ No newline at end of file diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj b/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj deleted file mode 100644 index a63dc4d..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj +++ /dev/null @@ -1,4 +0,0 @@ - - - - \ No newline at end of file diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/Makefile b/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/Makefile deleted file mode 100644 index 147b8c8..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FWLIB),) - USE_FWLIB = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/ST_STM3210C_EVAL/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m3 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DCORTEX_USE_BASEPRI=TRUE - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -ifeq ($(USE_FWLIB),yes) - include $(CHIBIOS)/ext/stm32lib/stm32lib.mk - CSRC += $(STM32SRC) - INCDIR += $(STM32INC) - USE_OPT += -DUSE_STDPERIPH_DRIVER -endif - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/ch.ld b/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/ch.ld deleted file mode 100644 index d5c4f5b..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/ch.ld +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * ST32F107 memory setup. - */ -__main_stack_size__ = 0x0200; -__process_stack_size__ = 0x0400; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x08000000, len = 256k - ram : org = 0x20000000, len = 64k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ctors : - { - PROVIDE(_ctors_start_ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(_ctors_end_ = .); - } > flash - - .dtors : - { - PROVIDE(_dtors_start_ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(_dtors_end_ = .); - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/chconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/halconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/main.c b/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/main.c deleted file mode 100644 index 404eb3c..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/main.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT4, 7); - chThdSleepMilliseconds(500); - palSetPad(IOPORT4, 7); - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD2, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. - */ - while (TRUE) { - if (palReadPad(IOPORT2, 9) == 0) - TestThread(&SD2); - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/mcuconf.h deleted file mode 100644 index 3094692..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/mcuconf.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * STM32 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -/* - * HAL driver system settings. - */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 -#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 -#define STM32_PREDIV1_VALUE 5 -#define STM32_PLLMUL_VALUE 9 -#define STM32_PREDIV2_VALUE 5 -#define STM32_PLL2MUL_VALUE 8 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_MCO STM32_MCO_NOCLOCK - -/* - * ADC driver system settings. - */ -#define USE_STM32_ADC1 TRUE -#define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() - -/* - * CAN driver system settings. - */ -#define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 11 - -/* - * PWM driver system settings. - */ -#define USE_STM32_PWM1 TRUE -#define USE_STM32_PWM2 FALSE -#define USE_STM32_PWM3 FALSE -#define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM4_IRQ_PRIORITY 7 - -/* - * SERIAL driver system settings. - */ -#define USE_STM32_USART1 FALSE -#define USE_STM32_USART2 TRUE -#define USE_STM32_USART3 FALSE -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define USE_STM32_UART4 FALSE -#define USE_STM32_UART5 FALSE -#endif -#define STM32_USART1_PRIORITY 12 -#define STM32_USART2_PRIORITY 12 -#define STM32_USART3_PRIORITY 12 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 12 -#define STM32_UART5_PRIORITY 12 -#endif - -/* - * SPI driver system settings. - */ -#define USE_STM32_SPI1 TRUE -#define USE_STM32_SPI2 TRUE -#define STM32_SPI1_DMA_PRIORITY 2 -#define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/readme.txt b/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/readme.txt deleted file mode 100644 index 165869e..0000000 --- a/ChibiOS_2.0.8/demos/ARMCM3-STM32F107-GCC/readme.txt +++ /dev/null @@ -1,25 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM-Cortex-M3 STM32F107. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an ST STM3210C-EVAL board. - -** The Demo ** - - -** Build Procedure ** - -The demo has been tested by using the free Codesourcery GCC-based toolchain, -YAGARTO and an experimental WinARM build including GCC 4.3.0. -Just modify the TRGT line in the makefile in order to use different GCC ports. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -ST Microelectronics and are licensed under a different license. -Also note that not all the files present in the ST library are distribited -with ChibiOS/RT, you can find the whole library on the ST web site: - - http://www.st.com diff --git a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/Makefile b/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/Makefile deleted file mode 100644 index 90a3798..0000000 --- a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/Makefile +++ /dev/null @@ -1,652 +0,0 @@ -# Hey Emacs, this is a -*- makefile -*- -#---------------------------------------------------------------------------- -# WinAVR Makefile Template written by Eric B. Weddington, Jörg Wunsch, et al. -# -# Released to the Public Domain -# -# Additional material for this makefile was written by: -# Peter Fleury -# Tim Henigan -# Colin O'Flynn -# Reiner Patommel -# Markus Pfaff -# Sander Pool -# Frederik Rouleau -# Carlos Lamas -# -#---------------------------------------------------------------------------- -# On command line: -# -# make all = Make software. -# -# make clean = Clean out built project files. -# -# make coff = Convert ELF to AVR COFF. -# -# make extcoff = Convert ELF to AVR Extended COFF. -# -# make program = Download the hex file to the device, using avrdude. -# Please customize the avrdude settings below first! -# -# make debug = Start either simulavr or avarice as specified for debugging, -# with avr-gdb or avr-insight as the front end for debugging. -# -# make filename.s = Just compile filename.c into the assembler code only. -# -# make filename.i = Create a preprocessed source file for use in submitting -# bug reports to the GCC project. -# -# To rebuild project do "make clean" then "make all". -#---------------------------------------------------------------------------- - - -# MCU name -MCU = at90can128 - - -# Processor frequency. -# This will define a symbol, F_CPU, in all source code files equal to the -# processor frequency. You can then use this symbol in your source code to -# calculate timings. Do NOT tack on a 'UL' at the end, this will be done -# automatically to create a 32-bit value in your source code. -# Typical values are: -# F_CPU = 1000000 -# F_CPU = 1843200 -# F_CPU = 2000000 -# F_CPU = 3686400 -# F_CPU = 4000000 -# F_CPU = 7372800 -# F_CPU = 8000000 -# F_CPU = 11059200 -# F_CPU = 14745600 -# F_CPU = 16000000 -# F_CPU = 18432000 -# F_CPU = 20000000 -F_CPU = 16000000 - - -# Output format. (can be srec, ihex, binary) -FORMAT = ihex - - -# Target file name (without extension). -TARGET = ch - - -# Object files directory -# To put object files in current directory, use a dot (.), do NOT make -# this an empty or blank macro! -OBJDIR = . - - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_AVR_CAN/board.mk -include $(CHIBIOS)/os/hal/platforms/AVR/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/AVR/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - - -# List C source files here. (C dependencies are automatically generated.) -SRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - main.c - - -# List C++ source files here. (C dependencies are automatically generated.) -CPPSRC = - - -# List Assembler source files here. -# Make them always end in a capital .S. Files ending in a lowercase .s -# will not be considered source files but generated files (assembler -# output from the compiler), and will be deleted upon "make clean"! -# Even though the DOS/Win* filesystem matches both .s and .S the same, -# it will preserve the spelling of the filenames, and gcc itself does -# care about how the name is spelled on its command-line. -ASRC = - - -# Optimization level, can be [0, 1, 2, 3, s]. -# 0 = turn off optimization. s = optimize for size. -# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) -OPT = s - - -# Debugging format. -# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs. -# AVR Studio 4.10 requires dwarf-2. -# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run. -DEBUG = dwarf-2 - - -# List any extra directories to look for include files here. -# Each directory must be seperated by a space. -# Use forward slashes for directory separators. -# For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - - -# Compiler flag to set the C Standard level. -# c89 = "ANSI" C -# gnu89 = c89 plus GCC extensions -# c99 = ISO C99 standard (not yet fully implemented) -# gnu99 = c99 plus GCC extensions -CSTANDARD = -std=gnu99 - - -# Place -D or -U options here for C sources -CDEFS = -DF_CPU=$(F_CPU)UL - - -# Place -D or -U options here for ASM sources -ADEFS = -DF_CPU=$(F_CPU) - - -# Place -D or -U options here for C++ sources -CPPDEFS = -DF_CPU=$(F_CPU)UL -#CPPDEFS += -D__STDC_LIMIT_MACROS -#CPPDEFS += -D__STDC_CONSTANT_MACROS - - - -#---------------- Compiler Options C ---------------- -# -g*: generate debugging information -# -O*: optimization level -# -f...: tuning, see GCC manual and avr-libc documentation -# -Wall...: warning level -# -Wa,...: tell GCC to pass this to the assembler. -# -adhlns...: create assembler listing -CFLAGS = -g$(DEBUG) -CFLAGS += $(CDEFS) -CFLAGS += -O$(OPT) -CFLAGS += -funsigned-char -CFLAGS += -funsigned-bitfields -CFLAGS += -fpack-struct -CFLAGS += -fshort-enums -#CFLAGS += -fno-strict-aliasing -CFLAGS += -Wall -CFLAGS += -Wstrict-prototypes -#CFLAGS += -mshort-calls -#CFLAGS += -fno-unit-at-a-time -#CFLAGS += -Wundef -#CFLAGS += -Wunreachable-code -#CFLAGS += -Wsign-compare -CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst) -CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) -CFLAGS += $(CSTANDARD) - - -#---------------- Compiler Options C++ ---------------- -# -g*: generate debugging information -# -O*: optimization level -# -f...: tuning, see GCC manual and avr-libc documentation -# -Wall...: warning level -# -Wa,...: tell GCC to pass this to the assembler. -# -adhlns...: create assembler listing -CPPFLAGS = -g$(DEBUG) -CPPFLAGS += $(CPPDEFS) -CPPFLAGS += -O$(OPT) -CPPFLAGS += -funsigned-char -CPPFLAGS += -funsigned-bitfields -CPPFLAGS += -fpack-struct -CPPFLAGS += -fshort-enums -CPPFLAGS += -fno-exceptions -CPPFLAGS += -Wall -CFLAGS += -Wundef -#CPPFLAGS += -mshort-calls -#CPPFLAGS += -fno-unit-at-a-time -#CPPFLAGS += -Wstrict-prototypes -#CPPFLAGS += -Wunreachable-code -#CPPFLAGS += -Wsign-compare -CPPFLAGS += -Wa,-adhlns=$(<:%.cpp=$(OBJDIR)/%.lst) -CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) -#CPPFLAGS += $(CSTANDARD) - - -#---------------- Assembler Options ---------------- -# -Wa,...: tell GCC to pass this to the assembler. -# -adhlns: create listing -# -gstabs: have the assembler create line number information; note that -# for use in COFF files, additional information about filenames -# and function names needs to be present in the assembler source -# files -- see avr-libc docs [FIXME: not yet described there] -# -listing-cont-lines: Sets the maximum number of continuation lines of hex -# dump that will be displayed for a given single line of source input. -ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100 - - -#---------------- Library Options ---------------- -# Minimalistic printf version -PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min - -# Floating point printf version (requires MATH_LIB = -lm below) -PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt - -# If this is left blank, then it will use the Standard printf version. -PRINTF_LIB = $(PRINTF_LIB_MIN) -#PRINTF_LIB = $(PRINTF_LIB_MIN) -#PRINTF_LIB = $(PRINTF_LIB_FLOAT) - - -# Minimalistic scanf version -SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min - -# Floating point + %[ scanf version (requires MATH_LIB = -lm below) -SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt - -# If this is left blank, then it will use the Standard scanf version. -SCANF_LIB = $(SCANF_LIB_MIN) -#SCANF_LIB = $(SCANF_LIB_MIN) -#SCANF_LIB = $(SCANF_LIB_FLOAT) - - -MATH_LIB = -lm - - -# List any extra directories to look for libraries here. -# Each directory must be seperated by a space. -# Use forward slashes for directory separators. -# For a directory that has spaces, enclose it in quotes. -EXTRALIBDIRS = - - - -#---------------- External Memory Options ---------------- - -# 64 KB of external RAM, starting after internal RAM (ATmega128!), -# used for variables (.data/.bss) and heap (malloc()). -#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff - -# 64 KB of external RAM, starting after internal RAM (ATmega128!), -# only used for heap (malloc()). -#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff - -EXTMEMOPTS = - - - -#---------------- Linker Options ---------------- -# -Wl,...: tell GCC to pass this to linker. -# -Map: create map file -# --cref: add cross reference to map file -LDFLAGS = -Wl,-Map=$(TARGET).map,--cref -LDFLAGS += $(EXTMEMOPTS) -LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS)) -LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB) -#LDFLAGS += -T linker_script.x - - - -#---------------- Programming Options (avrdude) ---------------- - -# Programming hardware: alf avr910 avrisp bascom bsd -# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 -# -# Type: avrdude -c ? -# to get a full listing. -# -AVRDUDE_PROGRAMMER = stk500 - -# com1 = serial port. Use lpt1 to connect to parallel port. -AVRDUDE_PORT = com1 # programmer connected to serial device - -AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex -#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep - - -# Uncomment the following if you want avrdude's erase cycle counter. -# Note that this counter needs to be initialized first using -Yn, -# see avrdude manual. -#AVRDUDE_ERASE_COUNTER = -y - -# Uncomment the following if you do /not/ wish a verification to be -# performed after programming the device. -#AVRDUDE_NO_VERIFY = -V - -# Increase verbosity level. Please use this when submitting bug -# reports about avrdude. See -# to submit bug reports. -#AVRDUDE_VERBOSE = -v -v - -AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) -AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY) -AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE) -AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER) - - - -#---------------- Debugging Options ---------------- - -# For simulavr only - target MCU frequency. -DEBUG_MFREQ = $(F_CPU) - -# Set the DEBUG_UI to either gdb or insight. -# DEBUG_UI = gdb -DEBUG_UI = insight - -# Set the debugging back-end to either avarice, simulavr. -DEBUG_BACKEND = avarice -#DEBUG_BACKEND = simulavr - -# GDB Init Filename. -GDBINIT_FILE = __avr_gdbinit - -# When using avarice settings for the JTAG -JTAG_DEV = /dev/com1 - -# Debugging port used to communicate between GDB / avarice / simulavr. -DEBUG_PORT = 4242 - -# Debugging host used to communicate between GDB / avarice / simulavr, normally -# just set to localhost unless doing some sort of crazy debugging when -# avarice is running on a different computer. -DEBUG_HOST = localhost - - - -#============================================================================ - - -# Define programs and commands. -SHELL = sh -CC = avr-gcc -OBJCOPY = avr-objcopy -OBJDUMP = avr-objdump -SIZE = avr-size -AR = avr-ar rcs -NM = avr-nm -AVRDUDE = avrdude -REMOVE = rm -f -REMOVEDIR = rm -rf -COPY = cp -WINSHELL = cmd - - -# Define Messages -# English -MSG_ERRORS_NONE = Errors: none -MSG_BEGIN = -------- begin -------- -MSG_END = -------- end -------- -MSG_SIZE_BEFORE = Size before: -MSG_SIZE_AFTER = Size after: -MSG_COFF = Converting to AVR COFF: -MSG_EXTENDED_COFF = Converting to AVR Extended COFF: -MSG_FLASH = Creating load file for Flash: -MSG_EEPROM = Creating load file for EEPROM: -MSG_EXTENDED_LISTING = Creating Extended Listing: -MSG_SYMBOL_TABLE = Creating Symbol Table: -MSG_LINKING = Linking: -MSG_COMPILING = Compiling C: -MSG_COMPILING_CPP = Compiling C++: -MSG_ASSEMBLING = Assembling: -MSG_CLEANING = Cleaning project: -MSG_CREATING_LIBRARY = Creating library: - - - - -# Define all object files. -OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o) - -# Define all listing files. -LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst) - - -# Compiler flags to generate dependency files. -GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d - - -# Combine all necessary flags and optional flags. -# Add target processor to flags. -ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS) -ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS) -ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) - - - - - -# Default target. -all: begin gccversion sizebefore build sizeafter end - -# Change the build target to build a HEX file or a library. -build: elf hex bin eep lss sym -#build: lib - - -elf: $(TARGET).elf -hex: $(TARGET).hex -bin: $(TARGET).bin -eep: $(TARGET).eep -lss: $(TARGET).lss -sym: $(TARGET).sym -LIBNAME=lib$(TARGET).a -lib: $(LIBNAME) - - - -# Eye candy. -# AVR Studio 3.x does not check make's exit code but relies on -# the following magic strings to be generated by the compile job. -begin: - @echo - @echo $(MSG_BEGIN) - -end: - @echo $(MSG_END) - @echo - - -# Display size of file. -HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex -ELFSIZE = $(SIZE) --mcu=$(MCU) --format=avr $(TARGET).elf - -sizebefore: - @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \ - 2>/dev/null; echo; fi - -sizeafter: - @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \ - 2>/dev/null; echo; fi - - - -# Display compiler version information. -gccversion : - @$(CC) --version - - - -# Program the device. -program: $(TARGET).hex $(TARGET).eep - $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) - - -# Generate avr-gdb config/init file which does the following: -# define the reset signal, load the target file, connect to target, and set -# a breakpoint at main(). -gdb-config: - @$(REMOVE) $(GDBINIT_FILE) - @echo define reset >> $(GDBINIT_FILE) - @echo SIGNAL SIGHUP >> $(GDBINIT_FILE) - @echo end >> $(GDBINIT_FILE) - @echo file $(TARGET).elf >> $(GDBINIT_FILE) - @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE) -ifeq ($(DEBUG_BACKEND),simulavr) - @echo load >> $(GDBINIT_FILE) -endif - @echo break main >> $(GDBINIT_FILE) - -debug: gdb-config $(TARGET).elf -ifeq ($(DEBUG_BACKEND), avarice) - @echo Starting AVaRICE - Press enter when "waiting to connect" message displays. - @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \ - $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT) - @$(WINSHELL) /c pause - -else - @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \ - $(DEBUG_MFREQ) --port $(DEBUG_PORT) -endif - @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE) - - - - -# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB. -COFFCONVERT = $(OBJCOPY) --debugging -COFFCONVERT += --change-section-address .data-0x800000 -COFFCONVERT += --change-section-address .bss-0x800000 -COFFCONVERT += --change-section-address .noinit-0x800000 -COFFCONVERT += --change-section-address .eeprom-0x810000 - - - -coff: $(TARGET).elf - @echo - @echo $(MSG_COFF) $(TARGET).cof - $(COFFCONVERT) -O coff-avr $< $(TARGET).cof - - -extcoff: $(TARGET).elf - @echo - @echo $(MSG_EXTENDED_COFF) $(TARGET).cof - $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof - - - -# Create final output files (.hex, .eep) from ELF output file. -%.hex: %.elf - @echo - @echo $(MSG_FLASH) $@ - $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ - -%.bin: %.elf - @echo - @echo $(MSG_FLASH) $@ - $(OBJCOPY) -O binary -R .eeprom $< $@ - -%.eep: %.elf - @echo - @echo $(MSG_EEPROM) $@ - -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ - --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0 - -# Create extended listing file from ELF output file. -%.lss: %.elf - @echo - @echo $(MSG_EXTENDED_LISTING) $@ - $(OBJDUMP) -h -S $< > $@ - -# Create a symbol table from ELF output file. -%.sym: %.elf - @echo - @echo $(MSG_SYMBOL_TABLE) $@ - $(NM) -n $< > $@ - - - -# Create library from object files. -.SECONDARY : $(TARGET).a -.PRECIOUS : $(OBJ) -%.a: $(OBJ) - @echo - @echo $(MSG_CREATING_LIBRARY) $@ - $(AR) $@ $(OBJ) - - -# Link: create ELF output file from object files. -.SECONDARY : $(TARGET).elf -.PRECIOUS : $(OBJ) -%.elf: $(OBJ) - @echo - @echo $(MSG_LINKING) $@ - $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS) - - -# Compile: create object files from C source files. -$(OBJDIR)/%.o : %.c - @echo - @echo $(MSG_COMPILING) $< - $(CC) -c $(ALL_CFLAGS) $< -o $@ - - -# Compile: create object files from C++ source files. -$(OBJDIR)/%.o : %.cpp - @echo - @echo $(MSG_COMPILING_CPP) $< - $(CC) -c $(ALL_CPPFLAGS) $< -o $@ - - -# Compile: create assembler files from C source files. -%.s : %.c - $(CC) -S $(ALL_CFLAGS) $< -o $@ - - -# Compile: create assembler files from C++ source files. -%.s : %.cpp - $(CC) -S $(ALL_CPPFLAGS) $< -o $@ - - -# Assemble: create object files from assembler source files. -$(OBJDIR)/%.o : %.S - @echo - @echo $(MSG_ASSEMBLING) $< - $(CC) -c $(ALL_ASFLAGS) $< -o $@ - - -# Create preprocessed source for use in sending a bug report. -%.i : %.c - $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@ - - -# Target: clean project. -clean: begin clean_list end - -clean_list : - @echo - @echo $(MSG_CLEANING) - $(REMOVE) $(TARGET).hex - $(REMOVE) $(TARGET).bin - $(REMOVE) $(TARGET).eep - $(REMOVE) $(TARGET).cof - $(REMOVE) $(TARGET).elf - $(REMOVE) $(TARGET).map - $(REMOVE) $(TARGET).sym - $(REMOVE) $(TARGET).lss - $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o) - $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst) - $(REMOVE) $(SRC:.c=.s) - $(REMOVE) $(SRC:.c=.d) - $(REMOVE) $(SRC:.c=.i) - $(REMOVEDIR) .dep - - -# Create object files directory -$(shell mkdir $(OBJDIR) 2>/dev/null) - - -# Include the dependency files. --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - - -# Listing of phony targets. -.PHONY : all begin finish end sizebefore sizeafter gccversion \ -build elf hex bin eep lss sym coff extcoff \ -clean clean_list program debug gdb-config - - - - - - diff --git a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/chconf.h b/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/chconf.h deleted file mode 100644 index 15e6d4a..0000000 --- a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 128 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC FALSE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/halconf.h b/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/halconf.h deleted file mode 100644 index 255b1a7..0000000 --- a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -#define SERIAL_BUFFERS_SIZE 16 - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/main.c b/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/main.c deleted file mode 100644 index 9ed2d52..0000000 --- a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/main.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "evtimer.h" - -static WORKING_AREA(waThread1, 32); -static msg_t Thread1(void *arg) { - - while (TRUE) { - PORTE ^= PORTE_LED; - chThdSleepMilliseconds(500); - } - return 0; -} - -static void TimerHandler(eventid_t id) { - msg_t TestThread(void *p); - - if (!(PORTE & PORTE_BUTTON)) - TestThread(&SD2); -} - -int main(int argc, char **argv) { - static EvTimer evt; - static evhandler_t handlers[1] = { - TimerHandler - }; - static EventListener el0; - - hwinit(); - - /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. - */ - chSysInit(); - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD2, NULL); - - /* - * Event Timer initialization. - */ - evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - - /* - * Starts the LED blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - while(TRUE) - chEvtDispatch(handlers, chEvtWaitOne(ALL_EVENTS)); - - return 0; -} diff --git a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/mcuconf.h deleted file mode 100644 index 9ecd104..0000000 --- a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/mcuconf.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AVR drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_AVR_USART0 FALSE -#define USE_AVR_USART1 TRUE - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/readme.txt b/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/readme.txt deleted file mode 100644 index 4d2202a..0000000 --- a/ChibiOS_2.0.8/demos/AVR-AT90CANx-GCC/readme.txt +++ /dev/null @@ -1,25 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for Atmel AVR AT90CAN128. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex AVR-CAN board. - -** The Demo ** - -The demo currently just flashes the board LED using a thread. It will be -expanded in next releases. -By pressing the board button the test suite is activated, output on serial -port 2. - -** Build Procedure ** - -The demo was built using the WinAVR toolchain. - -** Notes ** - -The demo requires include files from WinAVR that are not part of the ChibiOS/RT -distribution, please install WinAVR. - - http://winavr.sourceforge.net/ diff --git a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/Makefile b/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/Makefile deleted file mode 100644 index 69247ad..0000000 --- a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/Makefile +++ /dev/null @@ -1,652 +0,0 @@ -# Hey Emacs, this is a -*- makefile -*- -#---------------------------------------------------------------------------- -# WinAVR Makefile Template written by Eric B. Weddington, Jörg Wunsch, et al. -# -# Released to the Public Domain -# -# Additional material for this makefile was written by: -# Peter Fleury -# Tim Henigan -# Colin O'Flynn -# Reiner Patommel -# Markus Pfaff -# Sander Pool -# Frederik Rouleau -# Carlos Lamas -# -#---------------------------------------------------------------------------- -# On command line: -# -# make all = Make software. -# -# make clean = Clean out built project files. -# -# make coff = Convert ELF to AVR COFF. -# -# make extcoff = Convert ELF to AVR Extended COFF. -# -# make program = Download the hex file to the device, using avrdude. -# Please customize the avrdude settings below first! -# -# make debug = Start either simulavr or avarice as specified for debugging, -# with avr-gdb or avr-insight as the front end for debugging. -# -# make filename.s = Just compile filename.c into the assembler code only. -# -# make filename.i = Create a preprocessed source file for use in submitting -# bug reports to the GCC project. -# -# To rebuild project do "make clean" then "make all". -#---------------------------------------------------------------------------- - - -# MCU name -MCU = atmega128 - - -# Processor frequency. -# This will define a symbol, F_CPU, in all source code files equal to the -# processor frequency. You can then use this symbol in your source code to -# calculate timings. Do NOT tack on a 'UL' at the end, this will be done -# automatically to create a 32-bit value in your source code. -# Typical values are: -# F_CPU = 1000000 -# F_CPU = 1843200 -# F_CPU = 2000000 -# F_CPU = 3686400 -# F_CPU = 4000000 -# F_CPU = 7372800 -# F_CPU = 8000000 -# F_CPU = 11059200 -# F_CPU = 14745600 -# F_CPU = 16000000 -# F_CPU = 18432000 -# F_CPU = 20000000 -F_CPU = 16000000 - - -# Output format. (can be srec, ihex, binary) -FORMAT = ihex - - -# Target file name (without extension). -TARGET = ch - - -# Object files directory -# To put object files in current directory, use a dot (.), do NOT make -# this an empty or blank macro! -OBJDIR = . - - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_AVR_MT_128/board.mk -include $(CHIBIOS)/os/hal/platforms/AVR/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/AVR/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - - -# List C source files here. (C dependencies are automatically generated.) -SRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - lcd.c main.c - - -# List C++ source files here. (C dependencies are automatically generated.) -CPPSRC = - - -# List Assembler source files here. -# Make them always end in a capital .S. Files ending in a lowercase .s -# will not be considered source files but generated files (assembler -# output from the compiler), and will be deleted upon "make clean"! -# Even though the DOS/Win* filesystem matches both .s and .S the same, -# it will preserve the spelling of the filenames, and gcc itself does -# care about how the name is spelled on its command-line. -ASRC = - - -# Optimization level, can be [0, 1, 2, 3, s]. -# 0 = turn off optimization. s = optimize for size. -# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) -OPT = 2 - - -# Debugging format. -# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs. -# AVR Studio 4.10 requires dwarf-2. -# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run. -DEBUG = dwarf-2 - - -# List any extra directories to look for include files here. -# Each directory must be seperated by a space. -# Use forward slashes for directory separators. -# For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - - -# Compiler flag to set the C Standard level. -# c89 = "ANSI" C -# gnu89 = c89 plus GCC extensions -# c99 = ISO C99 standard (not yet fully implemented) -# gnu99 = c99 plus GCC extensions -CSTANDARD = -std=gnu99 - - -# Place -D or -U options here for C sources -CDEFS = -DF_CPU=$(F_CPU)UL - - -# Place -D or -U options here for ASM sources -ADEFS = -DF_CPU=$(F_CPU) - - -# Place -D or -U options here for C++ sources -CPPDEFS = -DF_CPU=$(F_CPU)UL -#CPPDEFS += -D__STDC_LIMIT_MACROS -#CPPDEFS += -D__STDC_CONSTANT_MACROS - - - -#---------------- Compiler Options C ---------------- -# -g*: generate debugging information -# -O*: optimization level -# -f...: tuning, see GCC manual and avr-libc documentation -# -Wall...: warning level -# -Wa,...: tell GCC to pass this to the assembler. -# -adhlns...: create assembler listing -CFLAGS = -g$(DEBUG) -CFLAGS += $(CDEFS) -CFLAGS += -O$(OPT) -CFLAGS += -funsigned-char -CFLAGS += -funsigned-bitfields -CFLAGS += -fpack-struct -CFLAGS += -fshort-enums -#CFLAGS += -fno-strict-aliasing -CFLAGS += -Wall -CFLAGS += -Wstrict-prototypes -#CFLAGS += -mshort-calls -#CFLAGS += -fno-unit-at-a-time -#CFLAGS += -Wundef -#CFLAGS += -Wunreachable-code -#CFLAGS += -Wsign-compare -CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst) -CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) -CFLAGS += $(CSTANDARD) - - -#---------------- Compiler Options C++ ---------------- -# -g*: generate debugging information -# -O*: optimization level -# -f...: tuning, see GCC manual and avr-libc documentation -# -Wall...: warning level -# -Wa,...: tell GCC to pass this to the assembler. -# -adhlns...: create assembler listing -CPPFLAGS = -g$(DEBUG) -CPPFLAGS += $(CPPDEFS) -CPPFLAGS += -O$(OPT) -CPPFLAGS += -funsigned-char -CPPFLAGS += -funsigned-bitfields -CPPFLAGS += -fpack-struct -CPPFLAGS += -fshort-enums -CPPFLAGS += -fno-exceptions -CPPFLAGS += -Wall -CFLAGS += -Wundef -#CPPFLAGS += -mshort-calls -#CPPFLAGS += -fno-unit-at-a-time -#CPPFLAGS += -Wstrict-prototypes -#CPPFLAGS += -Wunreachable-code -#CPPFLAGS += -Wsign-compare -CPPFLAGS += -Wa,-adhlns=$(<:%.cpp=$(OBJDIR)/%.lst) -CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) -#CPPFLAGS += $(CSTANDARD) - - -#---------------- Assembler Options ---------------- -# -Wa,...: tell GCC to pass this to the assembler. -# -adhlns: create listing -# -gstabs: have the assembler create line number information; note that -# for use in COFF files, additional information about filenames -# and function names needs to be present in the assembler source -# files -- see avr-libc docs [FIXME: not yet described there] -# -listing-cont-lines: Sets the maximum number of continuation lines of hex -# dump that will be displayed for a given single line of source input. -ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100 - - -#---------------- Library Options ---------------- -# Minimalistic printf version -PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min - -# Floating point printf version (requires MATH_LIB = -lm below) -PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt - -# If this is left blank, then it will use the Standard printf version. -PRINTF_LIB = $(PRINTF_LIB_MIN) -#PRINTF_LIB = $(PRINTF_LIB_MIN) -#PRINTF_LIB = $(PRINTF_LIB_FLOAT) - - -# Minimalistic scanf version -SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min - -# Floating point + %[ scanf version (requires MATH_LIB = -lm below) -SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt - -# If this is left blank, then it will use the Standard scanf version. -SCANF_LIB = $(SCANF_LIB_MIN) -#SCANF_LIB = $(SCANF_LIB_MIN) -#SCANF_LIB = $(SCANF_LIB_FLOAT) - - -MATH_LIB = -lm - - -# List any extra directories to look for libraries here. -# Each directory must be seperated by a space. -# Use forward slashes for directory separators. -# For a directory that has spaces, enclose it in quotes. -EXTRALIBDIRS = - - - -#---------------- External Memory Options ---------------- - -# 64 KB of external RAM, starting after internal RAM (ATmega128!), -# used for variables (.data/.bss) and heap (malloc()). -#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff - -# 64 KB of external RAM, starting after internal RAM (ATmega128!), -# only used for heap (malloc()). -#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff - -EXTMEMOPTS = - - - -#---------------- Linker Options ---------------- -# -Wl,...: tell GCC to pass this to linker. -# -Map: create map file -# --cref: add cross reference to map file -LDFLAGS = -Wl,-Map=$(TARGET).map,--cref -LDFLAGS += $(EXTMEMOPTS) -LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS)) -LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB) -#LDFLAGS += -T linker_script.x - - - -#---------------- Programming Options (avrdude) ---------------- - -# Programming hardware: alf avr910 avrisp bascom bsd -# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 -# -# Type: avrdude -c ? -# to get a full listing. -# -AVRDUDE_PROGRAMMER = stk500 - -# com1 = serial port. Use lpt1 to connect to parallel port. -AVRDUDE_PORT = com1 # programmer connected to serial device - -AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex -#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep - - -# Uncomment the following if you want avrdude's erase cycle counter. -# Note that this counter needs to be initialized first using -Yn, -# see avrdude manual. -#AVRDUDE_ERASE_COUNTER = -y - -# Uncomment the following if you do /not/ wish a verification to be -# performed after programming the device. -#AVRDUDE_NO_VERIFY = -V - -# Increase verbosity level. Please use this when submitting bug -# reports about avrdude. See -# to submit bug reports. -#AVRDUDE_VERBOSE = -v -v - -AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) -AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY) -AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE) -AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER) - - - -#---------------- Debugging Options ---------------- - -# For simulavr only - target MCU frequency. -DEBUG_MFREQ = $(F_CPU) - -# Set the DEBUG_UI to either gdb or insight. -# DEBUG_UI = gdb -DEBUG_UI = insight - -# Set the debugging back-end to either avarice, simulavr. -DEBUG_BACKEND = avarice -#DEBUG_BACKEND = simulavr - -# GDB Init Filename. -GDBINIT_FILE = __avr_gdbinit - -# When using avarice settings for the JTAG -JTAG_DEV = /dev/com1 - -# Debugging port used to communicate between GDB / avarice / simulavr. -DEBUG_PORT = 4242 - -# Debugging host used to communicate between GDB / avarice / simulavr, normally -# just set to localhost unless doing some sort of crazy debugging when -# avarice is running on a different computer. -DEBUG_HOST = localhost - - - -#============================================================================ - - -# Define programs and commands. -SHELL = sh -CC = avr-gcc -OBJCOPY = avr-objcopy -OBJDUMP = avr-objdump -SIZE = avr-size -AR = avr-ar rcs -NM = avr-nm -AVRDUDE = avrdude -REMOVE = rm -f -REMOVEDIR = rm -rf -COPY = cp -WINSHELL = cmd - - -# Define Messages -# English -MSG_ERRORS_NONE = Errors: none -MSG_BEGIN = -------- begin -------- -MSG_END = -------- end -------- -MSG_SIZE_BEFORE = Size before: -MSG_SIZE_AFTER = Size after: -MSG_COFF = Converting to AVR COFF: -MSG_EXTENDED_COFF = Converting to AVR Extended COFF: -MSG_FLASH = Creating load file for Flash: -MSG_EEPROM = Creating load file for EEPROM: -MSG_EXTENDED_LISTING = Creating Extended Listing: -MSG_SYMBOL_TABLE = Creating Symbol Table: -MSG_LINKING = Linking: -MSG_COMPILING = Compiling C: -MSG_COMPILING_CPP = Compiling C++: -MSG_ASSEMBLING = Assembling: -MSG_CLEANING = Cleaning project: -MSG_CREATING_LIBRARY = Creating library: - - - - -# Define all object files. -OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o) - -# Define all listing files. -LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst) - - -# Compiler flags to generate dependency files. -GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d - - -# Combine all necessary flags and optional flags. -# Add target processor to flags. -ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS) -ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS) -ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) - - - - - -# Default target. -all: begin gccversion sizebefore build sizeafter end - -# Change the build target to build a HEX file or a library. -build: elf hex bin eep lss sym -#build: lib - - -elf: $(TARGET).elf -hex: $(TARGET).hex -bin: $(TARGET).bin -eep: $(TARGET).eep -lss: $(TARGET).lss -sym: $(TARGET).sym -LIBNAME=lib$(TARGET).a -lib: $(LIBNAME) - - - -# Eye candy. -# AVR Studio 3.x does not check make's exit code but relies on -# the following magic strings to be generated by the compile job. -begin: - @echo - @echo $(MSG_BEGIN) - -end: - @echo $(MSG_END) - @echo - - -# Display size of file. -HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex -ELFSIZE = $(SIZE) --mcu=$(MCU) --format=avr $(TARGET).elf - -sizebefore: - @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \ - 2>/dev/null; echo; fi - -sizeafter: - @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \ - 2>/dev/null; echo; fi - - - -# Display compiler version information. -gccversion : - @$(CC) --version - - - -# Program the device. -program: $(TARGET).hex $(TARGET).eep - $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) - - -# Generate avr-gdb config/init file which does the following: -# define the reset signal, load the target file, connect to target, and set -# a breakpoint at main(). -gdb-config: - @$(REMOVE) $(GDBINIT_FILE) - @echo define reset >> $(GDBINIT_FILE) - @echo SIGNAL SIGHUP >> $(GDBINIT_FILE) - @echo end >> $(GDBINIT_FILE) - @echo file $(TARGET).elf >> $(GDBINIT_FILE) - @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE) -ifeq ($(DEBUG_BACKEND),simulavr) - @echo load >> $(GDBINIT_FILE) -endif - @echo break main >> $(GDBINIT_FILE) - -debug: gdb-config $(TARGET).elf -ifeq ($(DEBUG_BACKEND), avarice) - @echo Starting AVaRICE - Press enter when "waiting to connect" message displays. - @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \ - $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT) - @$(WINSHELL) /c pause - -else - @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \ - $(DEBUG_MFREQ) --port $(DEBUG_PORT) -endif - @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE) - - - - -# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB. -COFFCONVERT = $(OBJCOPY) --debugging -COFFCONVERT += --change-section-address .data-0x800000 -COFFCONVERT += --change-section-address .bss-0x800000 -COFFCONVERT += --change-section-address .noinit-0x800000 -COFFCONVERT += --change-section-address .eeprom-0x810000 - - - -coff: $(TARGET).elf - @echo - @echo $(MSG_COFF) $(TARGET).cof - $(COFFCONVERT) -O coff-avr $< $(TARGET).cof - - -extcoff: $(TARGET).elf - @echo - @echo $(MSG_EXTENDED_COFF) $(TARGET).cof - $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof - - - -# Create final output files (.hex, .eep) from ELF output file. -%.hex: %.elf - @echo - @echo $(MSG_FLASH) $@ - $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ - -%.bin: %.elf - @echo - @echo $(MSG_FLASH) $@ - $(OBJCOPY) -O binary -R .eeprom $< $@ - -%.eep: %.elf - @echo - @echo $(MSG_EEPROM) $@ - -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ - --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0 - -# Create extended listing file from ELF output file. -%.lss: %.elf - @echo - @echo $(MSG_EXTENDED_LISTING) $@ - $(OBJDUMP) -h -S $< > $@ - -# Create a symbol table from ELF output file. -%.sym: %.elf - @echo - @echo $(MSG_SYMBOL_TABLE) $@ - $(NM) -n $< > $@ - - - -# Create library from object files. -.SECONDARY : $(TARGET).a -.PRECIOUS : $(OBJ) -%.a: $(OBJ) - @echo - @echo $(MSG_CREATING_LIBRARY) $@ - $(AR) $@ $(OBJ) - - -# Link: create ELF output file from object files. -.SECONDARY : $(TARGET).elf -.PRECIOUS : $(OBJ) -%.elf: $(OBJ) - @echo - @echo $(MSG_LINKING) $@ - $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS) - - -# Compile: create object files from C source files. -$(OBJDIR)/%.o : %.c - @echo - @echo $(MSG_COMPILING) $< - $(CC) -c $(ALL_CFLAGS) $< -o $@ - - -# Compile: create object files from C++ source files. -$(OBJDIR)/%.o : %.cpp - @echo - @echo $(MSG_COMPILING_CPP) $< - $(CC) -c $(ALL_CPPFLAGS) $< -o $@ - - -# Compile: create assembler files from C source files. -%.s : %.c - $(CC) -S $(ALL_CFLAGS) $< -o $@ - - -# Compile: create assembler files from C++ source files. -%.s : %.cpp - $(CC) -S $(ALL_CPPFLAGS) $< -o $@ - - -# Assemble: create object files from assembler source files. -$(OBJDIR)/%.o : %.S - @echo - @echo $(MSG_ASSEMBLING) $< - $(CC) -c $(ALL_ASFLAGS) $< -o $@ - - -# Create preprocessed source for use in sending a bug report. -%.i : %.c - $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@ - - -# Target: clean project. -clean: begin clean_list end - -clean_list : - @echo - @echo $(MSG_CLEANING) - $(REMOVE) $(TARGET).hex - $(REMOVE) $(TARGET).bin - $(REMOVE) $(TARGET).eep - $(REMOVE) $(TARGET).cof - $(REMOVE) $(TARGET).elf - $(REMOVE) $(TARGET).map - $(REMOVE) $(TARGET).sym - $(REMOVE) $(TARGET).lss - $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o) - $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst) - $(REMOVE) $(SRC:.c=.s) - $(REMOVE) $(SRC:.c=.d) - $(REMOVE) $(SRC:.c=.i) - $(REMOVEDIR) .dep - - -# Create object files directory -$(shell mkdir $(OBJDIR) 2>/dev/null) - - -# Include the dependency files. --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - - -# Listing of phony targets. -.PHONY : all begin finish end sizebefore sizeafter gccversion \ -build elf hex bin eep lss sym coff extcoff \ -clean clean_list program debug gdb-config - - - - - - diff --git a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/chconf.h b/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/chconf.h deleted file mode 100644 index 15e6d4a..0000000 --- a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 128 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC FALSE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/halconf.h b/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/halconf.h deleted file mode 100644 index 255b1a7..0000000 --- a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -#define SERIAL_BUFFERS_SIZE 16 - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/lcd.c b/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/lcd.c deleted file mode 100644 index 9aabee1..0000000 --- a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/lcd.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "lcd.h" - -static void e_pulse(void) { - volatile uint8_t i; - - PORTC |= PORTC_44780_E; - for (i = 0; i < ELOOPVALUE; i++); - ; - PORTC &= ~PORTC_44780_E; -} - -static void wait_not_busy(void) { - - chThdSleep(2); -} - -/* - * 44780 soft reset procedure. - */ -void lcdInit(void) { - - PORTC = (PORTC & ~(PORTC_44780_DATA | PORTC_44780_RS | PORTC_44780_E | PORTC_44780_RW)) | - (LCD_CMD_INIT8 & PORTC_44780_DATA); - chThdSleep(50); - e_pulse(); - chThdSleep(10); - e_pulse(); - chThdSleep(2); - e_pulse(); - wait_not_busy(); - PORTC = (PORTC & ~(PORTC_44780_DATA | PORTC_44780_RS | PORTC_44780_E | PORTC_44780_RW)) | - (LCD_CMD_INIT4 & PORTC_44780_DATA); - e_pulse(); - lcdCmd(LCD_CMD_INIT4); - lcdCmd(LCD_SET_DM | LCD_DM_DISPLAY_ON); - lcdCmd(LCD_SET_INCREMENT_MODE); -} - -/* - * Sends a command byte to the 44780. - */ -void lcdCmd(uint8_t cmd) { - - wait_not_busy(); - PORTC = (PORTC | PORTC_44780_DATA) & (cmd | (0x0F & ~PORTC_44780_RS)); - e_pulse(); - PORTC = (PORTC | PORTC_44780_DATA) & ((cmd << 4) | (0x0F & ~PORTC_44780_RS)); - e_pulse(); -} - -/* - * Writes a char on the LCD at the current position. - */ -void lcdPutc(char c) { - uint8_t b; - - wait_not_busy(); - b = c | 0x0F; - PORTC = (PORTC | PORTC_44780_DATA | PORTC_44780_RS) & (c | 0x0F); - e_pulse(); - PORTC = (PORTC | PORTC_44780_DATA | PORTC_44780_RS) & ((c << 4) | 0x0F); - e_pulse(); -} - -/* - * Writes a string on the LCD at an absolute address. - */ -void lcdPuts(uint8_t pos, char *p) { - - lcdCmd(LCD_SET_DDRAM_ADDRESS | pos); - while (*p) - lcdPutc(*p++); -} diff --git a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/lcd.h b/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/lcd.h deleted file mode 100644 index a782f73..0000000 --- a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/lcd.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _LCD_H_ -#define _LCD_H_ - -#define ELOOPVALUE 10 - -#define LCD_CLEAR 0x01 - -#define LCD_RETURN_HOME 0x02 - -#define LCD_SET_INCREMENT_MODE 0x06 - -#define LCD_SET_DM 0x08 -#define LCD_DM_DISPLAY_ON 4 -#define LCD_DM_DISPLAY_OFF 0 -#define LCD_DM_CURSOR_ON 2 -#define LCD_DM_CURSOR_OFF 0 -#define LCD_DM_BLINK_ON 1 -#define LCD_DM_BLINK_OFF 0 - -#define LCD_CMD_INIT4 0x28 -#define LCD_CMD_INIT8 0x38 - -#define LCD_SET_DDRAM_ADDRESS 0x80 - -#define LCD_LINE1 0 -#define LCD_LINE2 40 - -void lcdInit(void); -void lcdCmd(uint8_t cmd); -void lcdPutc(char c); -void lcdPuts(uint8_t pos, char *p); - -#endif /* _LCD_H_ */ diff --git a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/main.c b/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/main.c deleted file mode 100644 index 5a0d1a9..0000000 --- a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/main.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "evtimer.h" - -#include "lcd.h" - -static WORKING_AREA(waThread1, 32); -static msg_t Thread1(void *arg) { - - while (TRUE) { - if (!(PINA & PORTA_BUTTON2)) - PORTA ^= PORTA_RELAY; - chThdSleepMilliseconds(1000); - } - return 0; -} - -static void TimerHandler(eventid_t id) { - msg_t TestThread(void *p); - - if (!(PINA & PORTA_BUTTON1)) - TestThread(&SD2); -} - -int main(int argc, char **argv) { - static EvTimer evt; - static evhandler_t handlers[1] = { - TimerHandler - }; - static EventListener el0; - - hwinit(); - - /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. - */ - chSysInit(); - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD2, NULL); - - /* - * This initialization requires the OS already active because it uses delay - * APIs inside. - */ - lcdInit(); - lcdCmd(LCD_CLEAR); - lcdPuts(LCD_LINE1, " ChibiOS/RT "); - lcdPuts(LCD_LINE2, " Hello World! "); - - /* - * Event Timer initialization. - */ - evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - - /* - * Starts the LED blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - while(TRUE) - chEvtDispatch(handlers, chEvtWaitOne(ALL_EVENTS)); - - return 0; -} diff --git a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/mcuconf.h deleted file mode 100644 index 9ecd104..0000000 --- a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/mcuconf.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * AVR drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_AVR_USART0 FALSE -#define USE_AVR_USART1 TRUE - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/readme.txt b/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/readme.txt deleted file mode 100644 index d4a8c5e..0000000 --- a/ChibiOS_2.0.8/demos/AVR-ATmega128-GCC/readme.txt +++ /dev/null @@ -1,24 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for Atmel AVR ATmega128. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex AVR-MT-128 board. - -** The Demo ** - -The demo currently just writes a hello world on the LCD and toggles the relay -using a thread while button 2 is pressed. -By pressing the button 1 the test suite is activated, output on serial port 2. - -** Build Procedure ** - -The demo was built using the WinAVR toolchain. - -** Notes ** - -The demo requires include files from WinAVR that are not part of the ChibiOS/RT -distribution, please install WinAVR. - - http://winavr.sourceforge.net/ diff --git a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/Makefile b/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/Makefile deleted file mode 100644 index 2695202..0000000 --- a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/Makefile +++ /dev/null @@ -1,150 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = no -endif - -# Enable register caching optimization (read documentation). -# Option not tested on MSP430, DO NOT USE. -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = mspgcc/msp430x1611.x - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_MSP430_P1611/board.mk -include $(CHIBIOS)/os/hal/platforms/MSP430/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/MSP430/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources here. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - main.c - -# C++ sources here. -CPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = msp430x1611 - -TRGT = msp430- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/MSP430/rules.mk diff --git a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/chconf.h b/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/chconf.h deleted file mode 100644 index a7c4e75..0000000 --- a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 100 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 10 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 512 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/halconf.h b/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/main.c b/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/main.c deleted file mode 100644 index af50ac7..0000000 --- a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/main.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 64); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palSetPad(IOPORT6, P6_O_LED); - chThdSleepMilliseconds(500); - palClearPad(IOPORT6, P6_O_LED); - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * Entry point, the interrupts are disabled on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Hardware initialization, see board.c. - */ - hwinit(); - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. - */ - chSysInit(); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop. - */ - while (TRUE) { - if (!palReadPad(IOPORT6, P6_I_BUTTON)) - TestThread(&SD1); - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/mcuconf.h b/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/mcuconf.h deleted file mode 100644 index b5b6a47..0000000 --- a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/mcuconf.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * MSP430 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * HAL driver system settings. - */ -#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * MAC driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ -#define USE_MSP430_USART0 TRUE -#define USE_MSP430_USART1 FALSE - -/* - * SPI driver system settings. - */ diff --git a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/mspgcc/msp430x1611.x b/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/mspgcc/msp430x1611.x deleted file mode 100644 index 774cfe9..0000000 --- a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/mspgcc/msp430x1611.x +++ /dev/null @@ -1,201 +0,0 @@ -/* Default linker script, for normal executables */ -OUTPUT_FORMAT("elf32-msp430","elf32-msp430","elf32-msp430") -OUTPUT_ARCH(msp:16) -MEMORY -{ - text (rx) : ORIGIN = 0x4000, LENGTH = 0xbfe0 - data (rwx) : ORIGIN = 0x1100, LENGTH = 0x2800 - vectors (rw) : ORIGIN = 0xffe0 LENGTH = 32 - bootloader(rx) : ORIGIN = 0x0c00, LENGTH = 1K - infomem(rx) : ORIGIN = 0x1000, LENGTH = 256 - infomemnobits(rx) : ORIGIN = 0x1000, LENGTH = 256 -} -SECTIONS -{ - /* Read-only sections, merged into text segment. */ - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rel.init : { *(.rel.init) } - .rela.init : { *(.rela.init) } - .rel.text : - { - *(.rel.text) - *(.rel.text.*) - *(.rel.gnu.linkonce.t*) - } - .rela.text : - { - *(.rela.text) - *(.rela.text.*) - *(.rela.gnu.linkonce.t*) - } - .rel.fini : { *(.rel.fini) } - .rela.fini : { *(.rela.fini) } - .rel.rodata : - { - *(.rel.rodata) - *(.rel.rodata.*) - *(.rel.gnu.linkonce.r*) - } - .rela.rodata : - { - *(.rela.rodata) - *(.rela.rodata.*) - *(.rela.gnu.linkonce.r*) - } - .rel.data : - { - *(.rel.data) - *(.rel.data.*) - *(.rel.gnu.linkonce.d*) - } - .rela.data : - { - *(.rela.data) - *(.rela.data.*) - *(.rela.gnu.linkonce.d*) - } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - /* Internal text space. */ - .text : - { - . = ALIGN(2); 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- *(.infomem.*) - } > infomem - /* Information memory (not loaded into MPU). */ - .infomemnobits : - { - *(.infomemnobits) - . = ALIGN(2); - *(.infomemnobits.*) - } > infomemnobits - .bss SIZEOF(.data) + ADDR(.data) : - { - PROVIDE (__bss_start = .) ; - *(.bss) - *(COMMON) - PROVIDE (__bss_end = .) ; - _end = . ; - } > data - .noinit SIZEOF(.bss) + ADDR(.bss) : - { - PROVIDE (__noinit_start = .) ; - *(.noinit) - *(COMMON) - PROVIDE (__noinit_end = .) ; - _end = . ; - } > data - .vectors : - { - PROVIDE (__vectors_start = .) ; - *(.vectors*) - _vectors_end = . ; - } > vectors - /* Stabs for profiling information*/ - .profiler 0 : { *(.profiler) } - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - PROVIDE (__stack = 0x3900) ; - PROVIDE (__data_start_rom = _etext) ; - PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ; - PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ; - PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ; - PROVIDE (__subdevice_has_heap = 0) ; -} diff --git a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/readme.txt b/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/readme.txt deleted file mode 100644 index 8c27398..0000000 --- a/ChibiOS_2.0.8/demos/MSP430-MSP430x1611-GCC/readme.txt +++ /dev/null @@ -1,24 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for Texas Instruments MSP430. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex MSP430-P1611 board. - -** The Demo ** - -The demo flashes the board LED using a thread, by pressing the button located -on the board the test procedure is activated with output on the serial port -COM1 (USART0). - -** Build Procedure ** - -The demo was built using the MSPGCC toolchain. - -** Notes ** - -The demo requires include files from MSPGCC that are not part of the ChibiOS/RT -distribution, please install MSPGCC. - - http://mspgcc.sourceforge.net/ diff --git a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/Makefile b/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/Makefile deleted file mode 100644 index 061b4fb..0000000 --- a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/Makefile +++ /dev/null @@ -1,154 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = no -endif - -# Enable register caching optimization (read documentation). -# Option not tested on MSP430, DO NOT USE. -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = ./ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/GENERIC_SPC563/board.mk -include $(CHIBIOS)/os/hal/platforms/SPC56x/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/PPC/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources here. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/shell.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources here. -CPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/PPC/SPC56x/ivor.s \ - $(CHIBIOS)/os/ports/GCC/PPC/SPC56x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames - -TRGT = powerpc-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DPPC_VARIANT=PPC_VARIANT_e200z3 - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/ch.ld b/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/ch.ld deleted file mode 100644 index 759d7a0..0000000 --- a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/ch.ld +++ /dev/null @@ -1,118 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * SPC563M64 memory setup. - */ -__irq_stack_size__ = 0x0400; -__process_stack_size__ = 0x0800; -__stacks_total_size__ = __irq_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 1536k - ram : org = 0x40000000, len = 94k -} - -/* - * Derived constants. - */ -__flash_size__ = LENGTH(flash); -__flash_start__ = ORIGIN(flash); -__flash_end__ = ORIGIN(flash) + LENGTH(flash); - -__ram_size__ = LENGTH(ram); -__ram_start__ = ORIGIN(ram); -__ram_end__ = ORIGIN(ram) + LENGTH(ram); - -SECTIONS -{ - . = ORIGIN(flash); - - .text : ALIGN(16) SUBALIGN(16) - { - __ivpr_base__ = .; - KEEP(*(.bam)) - KEEP(*(.handlers)) - . = ALIGN(0x800); - KEEP(*(.vectors)) - *(.text .stub .text.* .gnu.linkonce.t.*) - *(.glue_7t); - *(.glue_7); - *(.ctors); - *(.dtors); - } > flash - - .rodata : ALIGN(16) SUBALIGN(16) - { - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.rodata1) - } > flash - - .sdata2 : ALIGN(16) SUBALIGN(16) - { - __sdata2_start__ = . + 0x8000; - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) - } > flash - - .romdata : ALIGN(16) SUBALIGN(16) - { - __romdata_start__ = .; - } > flash - - .data : AT(__romdata_start__) - { - . = ALIGN(4); - __data_start__ = .; - *(.data .data.* .gnu.linkonce.d.*) - __sdata_start__ = . + 0x8000; - *(.sdata .sdata.* .gnu.linkonce.s.*) - __data_end__ = .; - } > ram - - .sbss : - { - __bss_start__ = .; - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } > ram - - .bss : - { - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - __bss_end__ = .; - } > ram - - /DISCARD/ : - { - *(.eh_*) - } - - __heap_base__ = __bss_end__; - __heap_end__ = __ram_end__ - __stacks_total_size__; -} diff --git a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/chconf.h b/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/halconf.h b/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/halconf.h deleted file mode 100644 index cee4c0d..0000000 --- a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -/*#include "mcuconf.h"*/ - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/main.c b/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/main.c deleted file mode 100644 index e927a6a..0000000 --- a/ChibiOS_2.0.8/demos/PPC-SPC563-GCC/main.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "shell.h" - -#define SHELL_WA_SIZE THD_WA_SIZE(1024) -#define TEST_WA_SIZE THD_WA_SIZE(256) - -static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { - size_t n, size; - char buf[52]; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: mem"); - return; - } - n = chHeapStatus(NULL, &size); - siprintf(buf, "core free memory : %i bytes", chCoreStatus()); - shellPrintLine(chp, buf); - siprintf(buf, "heap fragments : %i", n); - shellPrintLine(chp, buf); - siprintf(buf, "heap free total : %i bytes", size); - shellPrintLine(chp, buf); -} - -static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSG", - "WTMSG", - "FINAL" - }; - Thread *tp; - char buf[60]; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: threads"); - return; - } - shellPrintLine(chp, " addr stack prio refs state time"); - tp = chRegFirstThread(); - do { - siprintf(buf, "%8lx %8lx %4u %4i %9s %u", - (uint32_t)tp, (uint32_t)tp->p_ctx.sp, - (unsigned int)tp->p_prio, tp->p_refs - 1, - states[tp->p_state], (unsigned int)tp->p_time); - shellPrintLine(chp, buf); - tp = chRegNextThread(tp); - } while (tp != NULL); -} - -static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { - Thread *tp; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: test"); - return; - } - tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), - TestThread, chp); - if (tp == NULL) { - shellPrintLine(chp, "out of memory"); - return; - } - chThdWait(tp); -} - -static const ShellCommand commands[] = { - {"mem", cmd_mem}, - {"threads", cmd_threads}, - {"test", cmd_test}, - {NULL, NULL} -}; - -static const ShellConfig shell_cfg1 = { - (BaseChannel *)&SD1, - commands -}; - -/* - * LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - - SIU.GPDO[GPIO_LED1].R = 1; - SIU.GPDO[GPIO_LED2].R = 1; - SIU.GPDO[GPIO_LED3].R = 1; - SIU.GPDO[GPIO_LED4].R = 1; - - while (TRUE) { - SIU.GPDO[GPIO_LED1].R = 0; - chThdSleepMilliseconds(100); - SIU.GPDO[GPIO_LED2].R = 0; - chThdSleepMilliseconds(100); - SIU.GPDO[GPIO_LED3].R = 0; - chThdSleepMilliseconds(100); - SIU.GPDO[GPIO_LED4].R = 0; - chThdSleepMilliseconds(100); - SIU.GPDO[GPIO_LED1].R = 1; - chThdSleepMilliseconds(100); - SIU.GPDO[GPIO_LED2].R = 1; - chThdSleepMilliseconds(100); - SIU.GPDO[GPIO_LED3].R = 1; - chThdSleepMilliseconds(100); - SIU.GPDO[GPIO_LED4].R = 1; - chThdSleepMilliseconds(300); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - Thread *shelltp = NULL; - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 1 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Shell manager initialization. - */ - shellInit(); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity. - */ - while (TRUE) { - - if (!shelltp) - shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); - else if (chThdTerminated(shelltp)) { - chThdRelease(shelltp); /* Recovers memory of the previous shell. */ - shelltp = NULL; /* Triggers spawning of a new shell. */ - } -#if 0 - if (SIU.GPDI[GPIO_BUTTON1].B.PDI) { - volatile msg_t result; -#if 0 - MemoryStream report; - - msObjectInit(&report, report_buffer, sizeof(report_buffer), 0); - result = TestThread(&report); -#else - result = TestThread(&SD1); -#endif - } -#endif - chThdSleepMilliseconds(1000); - } - return 0; -} diff --git a/ChibiOS_2.0.8/demos/Posix-GCC/Makefile b/ChibiOS_2.0.8/demos/Posix-GCC/Makefile deleted file mode 100644 index a3d1f12..0000000 --- a/ChibiOS_2.0.8/demos/Posix-GCC/Makefile +++ /dev/null @@ -1,156 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = -CC = $(TRGT)gcc -AS = $(TRGT)gcc -x assembler-with-cpp - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/Posix/platform.mk -include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk - -# List C source files here -SRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/various/shell.c \ - main.c - -# List ASM source files here -ASRC = - -# List all user directories here -UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# Define optimisation level here -OPT = -ggdb -O2 -fomit-frame-pointer - -# -# End of user defines -############################################################################################## - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) -LIBS = $(DLIBS) $(ULIBS) - -ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm $(DEFS) - -ifeq ($(HOST_OSX),yes) - OSX_SDK = /Developer/SDKs/MacOSX10.5.sdk - OSX_ARCH = -mmacosx-version-min=10.3 -arch i386 - - CPFLAGS += -isysroot $(OSX_SDK) $(OSX_ARCH) - LDFLAGS = -Wl -Map=$(PROJECT).map,-syslibroot,$(OSX_SDK),$(LIBDIR) - LIBS += $(OSX_ARCH) -else - # Linux, or other - CPFLAGS += -Wa,-alms=$(<:.c=.lst) - LDFLAGS += -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# makefile rules -# - -all: $(OBJS) $(PROJECT) - -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -%o : %s - $(AS) -c $(ASFLAGS) $< -o $@ - -$(PROJECT): $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -gcov: - -mkdir gcov - $(COV) -u $(subst /,\,$(SRC)) - -mv *.gcov ./gcov - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT) - -rm -f $(PROJECT).map - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/ChibiOS_2.0.8/demos/Posix-GCC/board.h b/ChibiOS_2.0.8/demos/Posix-GCC/board.h deleted file mode 100644 index b57abb9..0000000 --- a/ChibiOS_2.0.8/demos/Posix-GCC/board.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/demos/Posix-GCC/chconf.h b/ChibiOS_2.0.8/demos/Posix-GCC/chconf.h deleted file mode 100644 index 0828377..0000000 --- a/ChibiOS_2.0.8/demos/Posix-GCC/chconf.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0x20000 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/Posix-GCC/halconf.h b/ChibiOS_2.0.8/demos/Posix-GCC/halconf.h deleted file mode 100644 index 91658d0..0000000 --- a/ChibiOS_2.0.8/demos/Posix-GCC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -/*#include "mcuconf.h"*/ - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/Posix-GCC/main.c b/ChibiOS_2.0.8/demos/Posix-GCC/main.c deleted file mode 100644 index 420a250..0000000 --- a/ChibiOS_2.0.8/demos/Posix-GCC/main.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "shell.h" - -#define SHELL_WA_SIZE THD_WA_SIZE(4096) -#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) -#define TEST_WA_SIZE THD_WA_SIZE(4096) - -#define cputs(msg) chMsgSend(cdtp, (msg_t)msg) - -static Thread *cdtp; -static Thread *shelltp1; -static Thread *shelltp2; - -void cmd_test(BaseChannel *chp, int argc, char *argv[]) { - Thread *tp; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: test"); - return; - } - tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), - TestThread, chp); - if (tp == NULL) { - shellPrintLine(chp, "out of memory"); - return; - } - chThdWait(tp); -} - -static const ShellCommand commands[] = { - {"test", cmd_test}, - {NULL, NULL} -}; - -static const ShellConfig shell_cfg1 = { - (BaseChannel *)&SD1, - commands -}; - -static const ShellConfig shell_cfg2 = { - (BaseChannel *)&SD2, - commands -}; - -/* - * Console print server done using synchronous messages. This makes the access - * to the C printf() thread safe and the print operation atomic among threads. - * In this example the message is the zero termitated string itself. - */ -static msg_t console_thread(void *arg) { - - (void)arg; - while (!chThdShouldTerminate()) { - puts((char *)chMsgWait()); - fflush(stdout); - chMsgRelease(RDY_OK); - } - return 0; -} - -/** - * @brief Shell termination handler. - * - * @param[in] id event id. - */ -static void termination_handler(eventid_t id) { - - (void)id; - if (shelltp1 && chThdTerminated(shelltp1)) { - chThdWait(shelltp1); - shelltp1 = NULL; - chThdSleepMilliseconds(10); - cputs("Init: shell on SD1 terminated"); - chSysLock(); - chOQResetI(&SD1.oqueue); - chSysUnlock(); - } - if (shelltp2 && chThdTerminated(shelltp2)) { - chThdWait(shelltp2); - shelltp2 = NULL; - chThdSleepMilliseconds(10); - cputs("Init: shell on SD2 terminated"); - chSysLock(); - chOQResetI(&SD2.oqueue); - chSysUnlock(); - } -} - -/** - * @brief SD1 status change handler. - * - * @param[in] id event id. - */ -static void sd1_handler(eventid_t id) { - - sdflags_t flags; - - (void)id; - flags = sdGetAndClearFlags(&SD1); - if ((flags & SD_CONNECTED) && (shelltp1 == NULL)) { - cputs("Init: connection on SD1"); - shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); - } - if (flags & SD_DISCONNECTED) { - cputs("Init: disconnection on SD1"); - chSysLock(); - chIQResetI(&SD1.iqueue); - chSysUnlock(); - } -} - -/** - * @brief SD2 status change handler. - * - * @param[in] id event id. - */ -static void sd2_handler(eventid_t id) { - - sdflags_t flags; - - (void)id; - flags = sdGetAndClearFlags(&SD2); - if ((flags & SD_CONNECTED) && (shelltp2 == NULL)) { - cputs("Init: connection on SD2"); - shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); - } - if (flags & SD_DISCONNECTED) { - cputs("Init: disconnection on SD2"); - chSysLock(); - chIQResetI(&SD2.iqueue); - chSysUnlock(); - } -} - -static evhandler_t fhandlers[] = { - termination_handler, - sd1_handler, - sd2_handler -}; - -/*------------------------------------------------------------------------* - * Simulator main. * - *------------------------------------------------------------------------*/ -int main(void) { - EventListener sd1fel, sd2fel, tel; - - /* - * HAL initialization. - */ - halInit(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); - - /* - * Serial ports (simulated) initialization. - */ - sdStart(&SD1, NULL); - sdStart(&SD2, NULL); - - /* - * Shell manager initialization. - */ - shellInit(); - chEvtRegister(&shell_terminated, &tel, 0); - - /* - * Console thread started. - */ - cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, - console_thread, NULL); - - /* - * Initializing connection/disconnection events. - */ - cputs("Shell service started on SD1, SD2"); - cputs(" - Listening for connections on SD1"); - (void) sdGetAndClearFlags(&SD1); - chEvtRegister(&SD1.sevent, &sd1fel, 1); - cputs(" - Listening for connections on SD2"); - (void) sdGetAndClearFlags(&SD2); - chEvtRegister(&SD2.sevent, &sd2fel, 2); - - /* - * Events servicing loop. - */ - while (!chThdShouldTerminate()) - chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); - - /* - * Clean simulator exit. - */ - chEvtUnregister(&SD1.sevent, &sd1fel); - chEvtUnregister(&SD2.sevent, &sd2fel); - return 0; -} diff --git a/ChibiOS_2.0.8/demos/Posix-GCC/readme.txt b/ChibiOS_2.0.8/demos/Posix-GCC/readme.txt deleted file mode 100644 index 111e220..0000000 --- a/ChibiOS_2.0.8/demos/Posix-GCC/readme.txt +++ /dev/null @@ -1,27 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for x86 into a Linux process ** -***************************************************************************** - -** TARGET ** - -The demo runs under x86 Linux as an application program. The serial -I/O is simulated over TCP/IP sockets. - -** The Demo ** - -The demo listens on the two serial ports, when a connection is detected a -thread is started that serves a small command shell. -The demo shows how create/terminate threads at runtime, how listen to events, -how ho work with serial ports, how use the messages. -You can develop your ChibiOS/RT application using this demo as a simulator -then you can recompile it for a different architecture. -See demo.c for details. - -** Build Procedure ** - -GCC required. The Makefile defaults to building for a Linux host. -To build on OS X, use the following command: `make HOST_OSX=yes` - -** Connect to the demo ** - -In order to connect to the demo use telnet on the listening ports. diff --git a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/ch.rapp b/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/ch.rapp deleted file mode 100644 index 0cc2ddb..0000000 --- a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/ch.rapp +++ /dev/null @@ -1,155 +0,0 @@ - - - - - - - - - - -
- - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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- - - - - \ No newline at end of file diff --git a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/ch.rprj b/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/ch.rprj deleted file mode 100644 index a2452b4..0000000 --- a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/ch.rprj +++ /dev/null @@ -1,4 +0,0 @@ - - - - \ No newline at end of file diff --git a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/chconf.h b/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/chconf.h deleted file mode 100644 index 9f77ef6..0000000 --- a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/chconf.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 100 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 10 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 3072 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED FALSE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS FALSE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES FALSE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ - /* Add threads custom fields here.*/ -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/halconf.h b/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/halconf.h deleted file mode 100644 index 40b1798..0000000 --- a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/main.c b/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/main.c deleted file mode 100644 index 11aac51..0000000 --- a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/main.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -/* - * LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 64); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT2, PB_LED(7)); - chThdSleepMilliseconds(500); - palSetPad(IOPORT2, PB_LED(7)); - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * Entry point. - */ -void main(void) { - - /* - * Board/HAL initialization. - */ - hwinit(); - - /* - * OS initialization. - */ - chSysInit(); - - /* - * Activates the serial driver 1 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity. - */ - while (TRUE) { - if (palReadPad(IOPORT7, PG_BT5) == PAL_LOW) - TestThread(&SD1); - if (palReadPad(IOPORT7, PG_BT6) == PAL_LOW) - sdWriteTimeout(&SD1, "Hello World!\r\n", 14, TIME_INFINITE); - chThdSleepMilliseconds(1000); - } -} diff --git a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/mcuconf.h b/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/mcuconf.h deleted file mode 100644 index 9b6354a..0000000 --- a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/mcuconf.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * STM8 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - */ - -/* - * HAL general settings. - */ -#define STM8_CLOCK_SOURCE CLK_SOURCE_HSI -#define STM8_HSI_DIVIDER CLK_HSI_DIV1 -#define STM8_CPU_DIVIDER CLK_CPU_DIV1 - -/* - * SERIAL driver system settings. - */ -#define USE_STM8_UART1 TRUE -#define USE_STM8_UART3 FALSE diff --git a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/readme.txt b/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/readme.txt deleted file mode 100644 index 00eb565..0000000 --- a/ChibiOS_2.0.8/demos/STM8S-STM8S208-RC/readme.txt +++ /dev/null @@ -1,16 +0,0 @@ -***************************************************************************** -** ChibiOS/RT demo for STM8S208RB. ** -***************************************************************************** - -** TARGET ** - -The demo runs on a Raisonance REva+STM8S208RB board. - -** The Demo ** - -The demo flashes the board LED using a thread, by pressing the button located -on the board the test procedure is activated with output on the serial port. - -** Build Procedure ** - -From withing the Ride7 IDE open the project, compile and run it. diff --git a/ChibiOS_2.0.8/demos/Win32-MinGW/Makefile b/ChibiOS_2.0.8/demos/Win32-MinGW/Makefile deleted file mode 100644 index 653f6c7..0000000 --- a/ChibiOS_2.0.8/demos/Win32-MinGW/Makefile +++ /dev/null @@ -1,145 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = mingw32- -CC = $(TRGT)gcc -AS = $(TRGT)gcc -x assembler-with-cpp - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = -lws2_32 - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/Win32/platform.mk -include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk - -# List C source files here -SRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/various/shell.c \ - main.c - -# List ASM source files here -ASRC = - -# List all user directories here -UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# Define optimisation level here -OPT = -ggdb -O2 -fomit-frame-pointer - -# -# End of user defines -############################################################################################## - - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) -LIBS = $(DLIBS) $(ULIBS) - -LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# makefile rules -# - -all: $(OBJS) $(PROJECT).exe - -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -%o : %s - $(AS) -c $(ASFLAGS) $< -o $@ - -%exe: $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -gcov: - -mkdir gcov - $(COV) -u $(subst /,\,$(SRC)) - -mv *.gcov ./gcov - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).exe - -rm -f $(PROJECT).map - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/ChibiOS_2.0.8/demos/Win32-MinGW/board.h b/ChibiOS_2.0.8/demos/Win32-MinGW/board.h deleted file mode 100644 index b57abb9..0000000 --- a/ChibiOS_2.0.8/demos/Win32-MinGW/board.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/demos/Win32-MinGW/chconf.h b/ChibiOS_2.0.8/demos/Win32-MinGW/chconf.h deleted file mode 100644 index 0828377..0000000 --- a/ChibiOS_2.0.8/demos/Win32-MinGW/chconf.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0x20000 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/Win32-MinGW/halconf.h b/ChibiOS_2.0.8/demos/Win32-MinGW/halconf.h deleted file mode 100644 index 91658d0..0000000 --- a/ChibiOS_2.0.8/demos/Win32-MinGW/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -/*#include "mcuconf.h"*/ - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/demos/Win32-MinGW/main.c b/ChibiOS_2.0.8/demos/Win32-MinGW/main.c deleted file mode 100644 index f8d0dc7..0000000 --- a/ChibiOS_2.0.8/demos/Win32-MinGW/main.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "shell.h" - -#define SHELL_WA_SIZE THD_WA_SIZE(4096) -#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) -#define TEST_WA_SIZE THD_WA_SIZE(4096) - -#define cputs(msg) chMsgSend(cdtp, (msg_t)msg) - -static Thread *cdtp; -static Thread *shelltp1; -static Thread *shelltp2; - -static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { - size_t n, size; - char buf[52]; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: mem"); - return; - } - n = chHeapStatus(NULL, &size); - sprintf(buf, "core free memory : %i bytes", chCoreStatus()); - shellPrintLine(chp, buf); - sprintf(buf, "heap fragments : %i", n); - shellPrintLine(chp, buf); - sprintf(buf, "heap free total : %i bytes", size); - shellPrintLine(chp, buf); -} - -static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSG", - "WTMSG", - "FINAL" - }; - Thread *tp; - char buf[60]; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: threads"); - return; - } - shellPrintLine(chp, " addr stack prio refs state time"); - tp = chRegFirstThread(); - do { - sprintf(buf, "%8p %8p %4i %4i %9s %i", - tp, tp->p_ctx.esp, tp->p_prio, tp->p_refs - 1, - states[tp->p_state], tp->p_time); - shellPrintLine(chp, buf); - tp = chRegNextThread(tp); - } while (tp != NULL); -} - -static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { - Thread *tp; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: test"); - return; - } - tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), - TestThread, chp); - if (tp == NULL) { - shellPrintLine(chp, "out of memory"); - return; - } - chThdWait(tp); -} - -static const ShellCommand commands[] = { - {"mem", cmd_mem}, - {"threads", cmd_threads}, - {"test", cmd_test}, - {NULL, NULL} -}; - -static const ShellConfig shell_cfg1 = { - (BaseChannel *)&SD1, - commands -}; - -static const ShellConfig shell_cfg2 = { - (BaseChannel *)&SD2, - commands -}; - -/* - * Console print server done using synchronous messages. This makes the access - * to the C printf() thread safe and the print operation atomic among threads. - * In this example the message is the zero termitated string itself. - */ -static msg_t console_thread(void *arg) { - - (void)arg; - while (!chThdShouldTerminate()) { - puts((char *)chMsgWait()); - fflush(stdout); - chMsgRelease(RDY_OK); - } - return 0; -} - -/** - * @brief Shell termination handler. - * - * @param[in] id event id. - */ -static void termination_handler(eventid_t id) { - - (void)id; - if (shelltp1 && chThdTerminated(shelltp1)) { - chThdWait(shelltp1); - shelltp1 = NULL; - chThdSleepMilliseconds(10); - cputs("Init: shell on SD1 terminated"); - chSysLock(); - chOQResetI(&SD1.oqueue); - chSysUnlock(); - } - if (shelltp2 && chThdTerminated(shelltp2)) { - chThdWait(shelltp2); - shelltp2 = NULL; - chThdSleepMilliseconds(10); - cputs("Init: shell on SD2 terminated"); - chSysLock(); - chOQResetI(&SD2.oqueue); - chSysUnlock(); - } -} - -/** - * @brief SD1 status change handler. - * - * @param[in] id event id. - */ -static void sd1_handler(eventid_t id) { - sdflags_t flags; - - (void)id; - flags = sdGetAndClearFlags(&SD1); - if ((flags & SD_CONNECTED) && (shelltp1 == NULL)) { - cputs("Init: connection on SD1"); - shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); - } - if (flags & SD_DISCONNECTED) { - cputs("Init: disconnection on SD1"); - chSysLock(); - chIQResetI(&SD1.iqueue); - chSysUnlock(); - } -} - -/** - * @brief SD2 status change handler. - * - * @param[in] id event id. - */ -static void sd2_handler(eventid_t id) { - sdflags_t flags; - - (void)id; - flags = sdGetAndClearFlags(&SD2); - if ((flags & SD_CONNECTED) && (shelltp2 == NULL)) { - cputs("Init: connection on SD2"); - shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); - } - if (flags & SD_DISCONNECTED) { - cputs("Init: disconnection on SD2"); - chSysLock(); - chIQResetI(&SD2.iqueue); - chSysUnlock(); - } -} - -static evhandler_t fhandlers[] = { - termination_handler, - sd1_handler, - sd2_handler -}; - -/*------------------------------------------------------------------------* - * Simulator main. * - *------------------------------------------------------------------------*/ -int main(void) { - EventListener sd1fel, sd2fel, tel; - - /* - * HAL initialization. - */ - halInit(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); - - /* - * Serial ports (simulated) initialization. - */ - sdStart(&SD1, NULL); - sdStart(&SD2, NULL); - - /* - * Shell manager initialization. - */ - shellInit(); - chEvtRegister(&shell_terminated, &tel, 0); - - /* - * Console thread started. - */ - cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, - console_thread, NULL); - - /* - * Initializing connection/disconnection events. - */ - cputs("Shell service started on SD1, SD2"); - cputs(" - Listening for connections on SD1"); - (void) sdGetAndClearFlags(&SD1); - chEvtRegister(&SD1.sevent, &sd1fel, 1); - cputs(" - Listening for connections on SD2"); - (void) sdGetAndClearFlags(&SD2); - chEvtRegister(&SD2.sevent, &sd2fel, 2); - - /* - * Events servicing loop. - */ - while (!chThdShouldTerminate()) - chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); - - /* - * Clean simulator exit. - */ - chEvtUnregister(&SD1.sevent, &sd1fel); - chEvtUnregister(&SD2.sevent, &sd2fel); - return 0; -} diff --git a/ChibiOS_2.0.8/demos/Win32-MinGW/readme.txt b/ChibiOS_2.0.8/demos/Win32-MinGW/readme.txt deleted file mode 100644 index 918c020..0000000 --- a/ChibiOS_2.0.8/demos/Win32-MinGW/readme.txt +++ /dev/null @@ -1,33 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for x86 into a Win32 process ** -***************************************************************************** - -** TARGET ** - -The demo runs under any Windows version as an application program. The serial -I/O is simulated over TCP/IP sockets. - -** The Demo ** - -The demo listens on the two serial ports, when a connection is detected a -thread is started that serves a small command shell. -The demo shows how create/terminate threads at runtime, how listen to events, -how ho work with serial ports, how use the messages. -You can develop your ChibiOS/RT application using this demo as a simulator -then you can recompile it for a different architecture. -See demo.c for details. - -** Build Procedure ** - -The demo was built using the MinGW toolchain. - -** Connect to the demo ** - -In order to connect to the demo a telnet client is required. A good choice -is PuTTY: - -http://www.putty.org/ - -Host Name: 127.0.0.1 -Port: 29001 and/or 29002 -Connection Type: Raw diff --git a/ChibiOS_2.0.8/docs/Doxyfile b/ChibiOS_2.0.8/docs/Doxyfile deleted file mode 100644 index 8998d37..0000000 --- a/ChibiOS_2.0.8/docs/Doxyfile +++ /dev/null @@ -1,1658 +0,0 @@ -# Doxyfile 1.6.3 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. 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This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = YES - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = NO - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = NO - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = NO - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed by -# doxygen. The layout file controls the global structure of the generated output files -# in an output format independent way. The create the layout file that represents -# doxygen's defaults, run doxygen with the -l option. You can optionally specify a -# file name after the option, if omitted DoxygenLayout.xml will be used as the name -# of the layout file. - -LAYOUT_FILE = ./rsc/layout.xml - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = YES - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = ../docs/src \ - ../os/kernel \ - ../os/kernel/include \ - ../os/kernel/src \ - ../os/kernel/templates \ - ../os/ports \ - ../os/ports/GCC/AVR \ - ../os/ports/GCC/ARM7 \ - ../os/ports/GCC/ARM7/crt0.s \ - ../os/ports/GCC/ARM7/chcoreasm.s \ - ../os/ports/GCC/ARMCMx \ - ../os/ports/GCC/ARMCMx/crt0.s \ - ../os/ports/GCC/ARMCMx/STM32F10x \ - ../os/ports/GCC/ARMCMx/LPC11xx \ - ../os/ports/GCC/ARMCMx/LPC13xx \ - ../os/ports/GCC/PPC \ - ../os/ports/GCC/PPC/crt0.s \ - ../os/ports/GCC/MSP430 \ - ../os/ports/RC/STM8 \ - ../os/hal \ - ../os/hal/include \ - ../os/hal/src \ - ../os/hal/templates \ - ../os/hal/platforms/AT91SAM7 \ - ../os/hal/platforms/AVR \ - ../os/hal/platforms/LPC11xx \ - ../os/hal/platforms/LPC13xx \ - ../os/hal/platforms/LPC214x \ - ../os/hal/platforms/MSP430 \ - ../os/hal/platforms/SPC56x \ - ../os/hal/platforms/STM32 \ - ../os/hal/platforms/STM8 \ - ../os/various \ - ../test \ - ../ext/ext.dox - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.cc \ - *.cxx \ - *.cpp \ - *.c++ \ - *.d \ - *.java \ - *.ii \ - *.ixx \ - *.ipp \ - *.i++ \ - *.inl \ - *.h \ - *.hh \ - *.hxx \ - *.hpp \ - *.h++ \ - *.idl \ - *.odl \ - *.cs \ - *.php \ - *.php3 \ - *.inc \ - *.m \ - *.mm \ - *.dox \ - *.py \ - *.ddf - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = ../os/hal/platforms/STM32/stm32f10x.h \ - ../os/hal/platforms/LPC11xx/LPC11xx.h \ - ../os/hal/platforms/LPC11xx/system_LPC11xx.h \ - ../os/hal/platforms/LPC13xx/LPC13xx.h \ - ../os/hal/platforms/LPC13xx/system_LPC13xx.h - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = * - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = ./rsc - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = NO - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = NO - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = NO - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = ./rsc/header.html - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = ./rsc/footer.html - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = ./rsc/custom.css - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = YES - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = ../ChibiOS_RT.chm - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = "\"C:/Program Files/HTML Help Workshop/hhc.exe\"" - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and QHP_VIRTUAL_FOLDER -# are set, an additional index file will be generated that can be used as input for -# Qt's qhelpgenerator to generate a Qt Compressed Help (.qch) of the generated -# HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to add. -# For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the custom filter to add.For more information please see -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this project's -# filter section matches. -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 4 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = YES - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = NO - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = YES - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = YES - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = rtf - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = NO - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. This is useful -# if you want to understand what is going on. On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ \ - CH_USE_WAITEXIT=1 \ - CH_USE_SEMAPHORES=1 \ - CH_USE_SEMSW=1 \ - CH_USE_MUTEXES=1 \ - CH_USE_CONDVARS=1 \ - CH_USE_CONDVARS_TIMEOUT=1 \ - CH_USE_EVENTS=1 \ - CH_USE_EVENTS_TIMEOUT=1 \ - CH_USE_QUEUES=1 \ - CH_USE_MEMCORE=1 \ - CH_USE_HEAP=1 \ - CH_USE_MEMPOOLS=1 \ - CH_USE_MESSAGES=1 \ - CH_USE_MAILBOXES=1 \ - CH_USE_DYNAMIC=1 \ - CH_USE_REGISTRY=1 \ - CH_DBG_ENABLE_ASSERTS=1 \ - CH_DBG_ENABLE_CHECKS=1 \ - CH_DBG_ENABLE_TRACE=1 \ - CH_DBG_ENABLE_STACK_CHECK=1 \ - CH_DBG_FILL_THREADS=1 \ - CH_DBG_THREADS_PROFILING=1 \ - CH_USE_ROUNDROBIN=1 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = NO - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = NO - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 8 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = NO - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = NO - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = NO - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = NO - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = png - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 20 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 3 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = YES - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/ChibiOS_2.0.8/docs/html/_a_r_m7_2crt0_8s.html b/ChibiOS_2.0.8/docs/html/_a_r_m7_2crt0_8s.html deleted file mode 100644 index bc941a2..0000000 --- a/ChibiOS_2.0.8/docs/html/_a_r_m7_2crt0_8s.html +++ /dev/null @@ -1,56 +0,0 @@ - - -ChibiOS/RT: crt0.s File Reference - - - - - - - - - - - -
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crt0.s File Reference

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- -

Generic ARM7 startup file for ChibiOS/RT. -More...

- -

Go to the source code of this file.

- -
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Detailed Description

-

Generic ARM7 startup file for ChibiOS/RT.

-

Startup code.

- -

Definition in file ARM7/crt0.s.

-
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- - diff --git a/ChibiOS_2.0.8/docs/html/_a_r_m7_2crt0_8s_source.html b/ChibiOS_2.0.8/docs/html/_a_r_m7_2crt0_8s_source.html deleted file mode 100644 index 6f509e0..0000000 --- a/ChibiOS_2.0.8/docs/html/_a_r_m7_2crt0_8s_source.html +++ /dev/null @@ -1,235 +0,0 @@ - - -ChibiOS/RT: crt0.s Source File - - - - - - - - - - - -
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- - diff --git a/ChibiOS_2.0.8/docs/html/_a_r_m_c_mx_2crt0_8s.html b/ChibiOS_2.0.8/docs/html/_a_r_m_c_mx_2crt0_8s.html deleted file mode 100644 index e21e6cb..0000000 --- a/ChibiOS_2.0.8/docs/html/_a_r_m_c_mx_2crt0_8s.html +++ /dev/null @@ -1,56 +0,0 @@ - - -ChibiOS/RT: crt0.s File Reference - - - - - - - - - - - -
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crt0.s File Reference

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Generic ARM Cortex-Mx startup file for ChibiOS/RT. -More...

-#include "cmparams.h"
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Go to the source code of this file.

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Generic ARM Cortex-Mx startup file for ChibiOS/RT.

- -

Definition in file ARMCMx/crt0.s.

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-Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/_a_r_m_c_mx_2crt0_8s_source.html b/ChibiOS_2.0.8/docs/html/_a_r_m_c_mx_2crt0_8s_source.html deleted file mode 100644 index e37cddb..0000000 --- a/ChibiOS_2.0.8/docs/html/_a_r_m_c_mx_2crt0_8s_source.html +++ /dev/null @@ -1,213 +0,0 @@ - - -ChibiOS/RT: crt0.s Source File - - - - - - - - - - - -
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- - diff --git a/ChibiOS_2.0.8/docs/html/_l_p_c11xx_2cmparams_8h.html b/ChibiOS_2.0.8/docs/html/_l_p_c11xx_2cmparams_8h.html deleted file mode 100644 index 0de2a19..0000000 --- a/ChibiOS_2.0.8/docs/html/_l_p_c11xx_2cmparams_8h.html +++ /dev/null @@ -1,67 +0,0 @@ - - -ChibiOS/RT: cmparams.h File Reference - - - - - - - - - - - -
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cmparams.h File Reference

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ARM Cortex-M0 LPC11xx Specific Parameters. -More...

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Go to the source code of this file.

- - - - - - - - - - -

-Defines

#define CORTEX_MODEL   CORTEX_M0
 Cortex core model.
#define CORTEX_HAS_ST   TRUE
 Systick unit presence.
#define CORTEX_HAS_MPU   FALSE
 Memory Protection unit presence.
#define CORTEX_PRIORITY_BITS   2
 Number of bits in priority masks.
-

Detailed Description

-

ARM Cortex-M0 LPC11xx Specific Parameters.

- -

Definition in file LPC11xx/cmparams.h.

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-Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/_l_p_c11xx_2cmparams_8h_source.html b/ChibiOS_2.0.8/docs/html/_l_p_c11xx_2cmparams_8h_source.html deleted file mode 100644 index ef25a58..0000000 --- a/ChibiOS_2.0.8/docs/html/_l_p_c11xx_2cmparams_8h_source.html +++ /dev/null @@ -1,107 +0,0 @@ - - -ChibiOS/RT: cmparams.h Source File - - - - - - - - - - - -
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- - diff --git a/ChibiOS_2.0.8/docs/html/_l_p_c13xx_2cmparams_8h.html b/ChibiOS_2.0.8/docs/html/_l_p_c13xx_2cmparams_8h.html deleted file mode 100644 index 9c1ee4b..0000000 --- a/ChibiOS_2.0.8/docs/html/_l_p_c13xx_2cmparams_8h.html +++ /dev/null @@ -1,67 +0,0 @@ - - -ChibiOS/RT: cmparams.h File Reference - - - - - - - - - - - -
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cmparams.h File Reference

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ARM Cortex-M3 LPC13xx Specific Parameters. -More...

- -

Go to the source code of this file.

- - - - - - - - - - -

-Defines

#define CORTEX_MODEL   CORTEX_M3
 Cortex core model.
#define CORTEX_HAS_ST   TRUE
 Systick unit presence.
#define CORTEX_HAS_MPU   FALSE
 Memory Protection unit presence.
#define CORTEX_PRIORITY_BITS   3
 Number of bits in priority masks.
-

Detailed Description

-

ARM Cortex-M3 LPC13xx Specific Parameters.

- -

Definition in file LPC13xx/cmparams.h.

-
-
-Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/_l_p_c13xx_2cmparams_8h_source.html b/ChibiOS_2.0.8/docs/html/_l_p_c13xx_2cmparams_8h_source.html deleted file mode 100644 index 2f920ac..0000000 --- a/ChibiOS_2.0.8/docs/html/_l_p_c13xx_2cmparams_8h_source.html +++ /dev/null @@ -1,107 +0,0 @@ - - -ChibiOS/RT: cmparams.h Source File - - - - - - - - - - - -
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crt0.s File Reference

-
-
- -

Generic PowerPC startup file for ChibiOS/RT. -More...

- -

Go to the source code of this file.

- -
-

Detailed Description

-

Generic PowerPC startup file for ChibiOS/RT.

-

Startup code.

- -

Definition in file PPC/crt0.s.

-
-
-Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/_p_p_c_2crt0_8s_source.html b/ChibiOS_2.0.8/docs/html/_p_p_c_2crt0_8s_source.html deleted file mode 100644 index 1c117c6..0000000 --- a/ChibiOS_2.0.8/docs/html/_p_p_c_2crt0_8s_source.html +++ /dev/null @@ -1,170 +0,0 @@ - - -ChibiOS/RT: crt0.s Source File - - - - - - - - - - - -
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cmparams.h File Reference

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ARM Cortex-M3 STM32F10x Specific Parameters. -More...

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Go to the source code of this file.

- - - - - - - - - - -

-Defines

#define CORTEX_MODEL   CORTEX_M3
 Cortex core model.
#define CORTEX_HAS_ST   TRUE
 Systick unit presence.
#define CORTEX_HAS_MPU   FALSE
 Memory Protection unit presence.
#define CORTEX_PRIORITY_BITS   4
 Number of bits in priority masks.
-

Detailed Description

-

ARM Cortex-M3 STM32F10x Specific Parameters.

- -

Definition in file STM32F10x/cmparams.h.

-
-
-Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/_s_t_m32_f10x_2cmparams_8h_source.html b/ChibiOS_2.0.8/docs/html/_s_t_m32_f10x_2cmparams_8h_source.html deleted file mode 100644 index 6a3b928..0000000 --- a/ChibiOS_2.0.8/docs/html/_s_t_m32_f10x_2cmparams_8h_source.html +++ /dev/null @@ -1,107 +0,0 @@ - - -ChibiOS/RT: cmparams.h Source File - - - - - - - - - - - -
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-Generated on Sun Nov 28 2010 14:09:49 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/adc_8c.html b/ChibiOS_2.0.8/docs/html/adc_8c.html deleted file mode 100644 index c83254e..0000000 --- a/ChibiOS_2.0.8/docs/html/adc_8c.html +++ /dev/null @@ -1,75 +0,0 @@ - - -ChibiOS/RT: adc.c File Reference - - - - - - - - - - - -
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adc.c File Reference

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ADC Driver code. -More...

-#include "ch.h"
-#include "hal.h"
- -

Go to the source code of this file.

- - - - - - - - - - - - - - - - -

-Functions

void adcInit (void)
 ADC Driver initialization.
void adcObjectInit (ADCDriver *adcp)
 Initializes the standard part of a ADCDriver structure.
void adcStart (ADCDriver *adcp, const ADCConfig *config)
 Configures and activates the ADC peripheral.
void adcStop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
bool_t adcStartConversion (ADCDriver *adcp, const ADCConversionGroup *grpp, adcsample_t *samples, size_t depth, adccallback_t callback)
 Starts an ADC conversion.
void adcStopConversion (ADCDriver *adcp)
 Stops an ongoing conversion.
msg_t adcWaitConversion (ADCDriver *adcp, systime_t timeout)
 Waits for completion.
-

Detailed Description

-

ADC Driver code.

- -

Definition in file adc.c.

-
-
-Generated on Sun Nov 28 2010 14:09:49 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/adc_8c_source.html b/ChibiOS_2.0.8/docs/html/adc_8c_source.html deleted file mode 100644 index 5b4d478..0000000 --- a/ChibiOS_2.0.8/docs/html/adc_8c_source.html +++ /dev/null @@ -1,286 +0,0 @@ - - -ChibiOS/RT: adc.c Source File - - - - - - - - - - - -
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-Enumerations | -Functions
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adc.h File Reference

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ADC Driver macros and structures. -More...

-#include "adc_lld.h"
- -

Go to the source code of this file.

- - - - - - - - - - - - - - - - - - - -

-Enumerations

enum  adcstate_t {
-  ADC_UNINIT = 0, -ADC_STOP = 1, -ADC_READY = 2, -ADC_RUNNING = 3, -
-  ADC_COMPLETE = 4 -
- }
 

Driver state machine possible states.

- More...

-Functions

void adcInit (void)
 ADC Driver initialization.
void adcObjectInit (ADCDriver *adcp)
 Initializes the standard part of a ADCDriver structure.
void adcStart (ADCDriver *adcp, const ADCConfig *config)
 Configures and activates the ADC peripheral.
void adcStop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
bool_t adcStartConversion (ADCDriver *adcp, const ADCConversionGroup *grpp, adcsample_t *samples, size_t depth, adccallback_t callback)
 Starts an ADC conversion.
void adcStopConversion (ADCDriver *adcp)
 Stops an ongoing conversion.
msg_t adcWaitConversion (ADCDriver *adcp, systime_t timeout)
 Waits for completion.
-

Detailed Description

-

ADC Driver macros and structures.

- -

Definition in file adc.h.

-
-
-Generated on Sun Nov 28 2010 14:09:49 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/adc_8h_source.html b/ChibiOS_2.0.8/docs/html/adc_8h_source.html deleted file mode 100644 index 505efc2..0000000 --- a/ChibiOS_2.0.8/docs/html/adc_8h_source.html +++ /dev/null @@ -1,147 +0,0 @@ - - -ChibiOS/RT: adc.h Source File - - - - - - - - - - - -
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- - diff --git a/ChibiOS_2.0.8/docs/html/annotated.html b/ChibiOS_2.0.8/docs/html/annotated.html deleted file mode 100644 index 0c06e09..0000000 --- a/ChibiOS_2.0.8/docs/html/annotated.html +++ /dev/null @@ -1,129 +0,0 @@ - - -ChibiOS/RT: Data Structures - - - - - - - - - - - -
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Data Structures

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-
-Here are the data structures with brief descriptions: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
__ioportGeneric MSP430 I/O port
_SerialDriverFull duplex serial driver class
ADCConfigDriver configuration structure
ADCConversionGroupConversion group configuration structure
ADCDriverStructure representing an ADC driver
at91sam7_pio_setup_tPIO port setup info
BaseAsynchronousChannelBase asynchronous channel class
BaseAsynchronousChannelVMTBaseAsynchronousChannel virtual methods table
BaseChannelBase channel class
BaseChannelVMTBaseChannel virtual methods table
BaseSequentialStreamBase stream class
BaseSequentialStreamVMTBaseSequentialStream virtual methods table
chibios_rt::BaseThreadBase class for a ChibiOS/RT thread
CANConfigDriver configuration structure
CANDriverStructure representing an CAN driver
CANFilterCAN filter
CANRxFrameCAN received frame
CANTxFrameCAN transmission frame
CM3_NVICStructure representing the NVIC I/O space
CM3_SCBStructure representing the System Control Block I/O space
CM3_STStructure representing the SYSTICK I/O space
cmxctxCortex-Mx exception context
CondVarCondVar structure
chibios_rt::CondVarClass encapsulating a conditional variable
contextPlatform dependent part of the Thread structure
CtxSwcEventTrace buffer record
eabi_frameMandatory part of a stack frame
EMACDescriptorStructure representing a buffer physical descriptor
chibios_rt::EnhancedThread< N >Enhanced threads template class
chibios_rt::EventClass encapsulating an event source
EventListenerEvent Listener structure
EventSourceEvent Source structure
EvTimerEvent timer structure
extctxInterrupt saved context
GenericConfigGeneric I/O ports static initializer
GenericQueueGeneric I/O queue structure
gpio_tGPIO port representation
heap_headerMemory heap block header
intctxSystem saved context
IOBusI/O bus descriptor
lpc111x_gpio_setup_tGPIO port setup info
LPC13xx_gpio_setup_tGPIO port setup info
lpc214x_fio_setup_tFIO port setup info
MACDriverStructure representing a MAC driver
MACReceiveDescriptorStructure representing a receive descriptor
MACTransmitDescriptorStructure representing a transmit descriptor
memory_heapStructure describing a memory heap
MemoryPoolMemory pool descriptor
MemoryStreamMemory stream object
MemStreamVMTMemStream virtual methods table
MMCConfigDriver configuration structure
MMCDriverStructure representing a MMC driver
msp430_dio_setup_tSetup registers common to all the MSP430 ports
chibios_rt::MutexClass encapsulating a mutex
MutexMutex structure
PALConfigAT91SAM7 PIO static initializer
pool_headerMemory pool free object header
port_common_tSimplified MSP430 I/O port representation
PWMChannelConfigPWM driver channel configuration structure
PWMConfigDriver configuration structure
PWMDriverStructure representing an PWM driver
ReadyListReady list header
chibios_rt::SemaphoreClass encapsulating a semaphore
SemaphoreSemaphore structure
SerialConfigGeneric Serial Driver configuration structure
SerialDriverVMTSerialDriver virtual methods table
ShellCommandCustom command entry type
ShellConfigShell descriptor type
SPIConfigDriver configuration structure
SPIDriverStructure representing a SPI driver
stkalign_tBase type for stack and memory alignment
stm32_gpio_setup_tGPIO port setup info
stm8_startctxStart context
chibios_rt::SystemClass encapsulating the base system functionalities
testcaseStructure representing a test case
ThreadStructure representing a thread
ThreadsListGeneric threads single link list, it works like a stack
ThreadsQueueGeneric threads bidirectional linked list header and element
chibios_rt::TimerTimer class
TraceBufferTrace buffer header
VirtualTimerVirtual Timer descriptor structure
VTListVirtual timers list header
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-Generated on Sun Nov 28 2010 14:09:59 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/architecture.html b/ChibiOS_2.0.8/docs/html/architecture.html deleted file mode 100644 index ba7c14c..0000000 --- a/ChibiOS_2.0.8/docs/html/architecture.html +++ /dev/null @@ -1,136 +0,0 @@ - - -ChibiOS/RT: Architecture - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

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Architecture

-
-
-

ChibiOS/RT General Architecture

- -

-Components

-

ChibiOS/RT is composed of several major components, each component can be composed of one of more subsystems. The main components are:

-
    -
  • Kernel, this is the platform independent part of the OS kernel.
    • -
  • HAL, this component contains a set of abstract device drivers that offer a common I/O API to the application across all the support platforms. The HAL code is totally portable across platforms.
    • -
  • Port, this is the platform dependent part of the OS kernel. This component is responsible of the system startup, interrupts abstraction, lock/unlock primitives, context switch related structures and code.
    - The component usually contains very little code because the OS is very portable but the quality of the implementation of the Port component affects heavily the performance of the ported OS. It is probably the most critical part of the whole OS.
    • -
  • Platform, this component contains a set of device drivers implementations.
    • -
  • Various, a library of various extra components that do not belong to any particular component but can make life easier while developing an embedded application.
    • -
-

-Dependencies

-

The following diagram shows the relationships among the various components that compose the system:
-
-

-
-inline_dotgraph_1.dot - -
-

-Kernel Architecture

-

The kernel itself is very modular and is composed of several subsystems, most subsystems are optional and can be switched of in the kernel configuration file chconf.h.
- The current kernel subsystems are divided in five categories:

-
    -
  • Base Kernel Services, this category contains the mandatory kernel subsystems:
      -
    • System Management, low level locks, initialization.
      • -
    • Time and Virtual Timers, virtual timers and time APIs.
      • -
    • Scheduler, scheduler APIs, all the higher level synchronization mechanism are implemented through this subsystem, it is very flexible but not recommended for direct use in user code.
      • -
    • Threads, thread-related APIs.
      • -
    -Base services diagram:
    -
    -
    -inline_dotgraph_2.dot - -
    -
    • -
  • Synchronization, this category contains the synchronization-related subsystems, each one of the provided mechanism can be configured out of the kernel if not needed.
      -
    • Semaphores, counter semaphores subsystem.
      • -
    • Mutexes, mutexes subsystem with support to the priority inheritance algorithm (fully implemented, any depht).
      • -
    • Condition Variables, condition variables, together with mutexes the condition variables allow the implementation of monitor constructs.
      • -
    • Event Flags, event sources and event flags with flexible support for and/or conditions and automatic dispatching to handler functions.
      • -
    • Synchronous Messages, lightweight synchronous messages.
      • -
    • Mailboxes, asynchronous messages queues.
      • -
    -All the synchronization mechanisms are built on top of the Scheduler APIs except Mailboxes that are build on top of Semaphores and Condition Variables that implicitly refer to Mutexes:
    -
    -
    -inline_dotgraph_3.dot - -
    -
    • -
  • Memory Management, memory management, multiple non-alternative schemes are available:
      -
    • Core Memory Manager, centralized core memory manager, this subsystems is used by the other allocators in order to get chunks of memory in a consistent way.
      • -
    • Heaps, central heap manager using a first fit strategy, it also allow the creation of multiple heaps in order to handle non uniform memory areas.
      • -
    • Memory Pools, very fast fixed size objects allocator.
      • -
    • Threads (dynamic), usually threads are static objects in ChibiOS/RT but there is the option for dynamic threads management, please see the article Threads Lifecycle.
      • -
    -The various allocators follow a precise hierarchy:
    -
    -
    -inline_dotgraph_4.dot - -
    - Please also see the article How to manage memory.
    • -
  • I/O Support, the kernel also provides mechanisms and abstract data interfaces that can be used by non-kernel components, the HAL as example.
      -
    • Data Streams, abstract streams interface.
      • -
    • I/O Channels, abstract I/O channels that inherits from the abstract stream interface.
      • -
    • I/O Queues, generic, byte wide, I/O queues APIs.
      • -
    -
    • -
  • Debug, debug services and APIs. The Registry susystem can be seen as part of the debug category even if it finds use in non-debug roles.
    • -
-

-HAL Architecture

-

The HAL is a collection of abstract device drivers, it relies on the Platform component for the low level implementation on specific hardware.
- The current internal HAL organization is the following:
-
-

-
-inline_dotgraph_5.dot - -
-


- See HAL for details about the various HAL subsystems.

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-Generated on Sun Nov 28 2010 14:09:53 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_atomic.html b/ChibiOS_2.0.8/docs/html/article_atomic.html deleted file mode 100644 index 9bc6ffc..0000000 --- a/ChibiOS_2.0.8/docs/html/article_atomic.html +++ /dev/null @@ -1,67 +0,0 @@ - - -ChibiOS/RT: Invoking multiple primitives as a single atomic operation - - - - - - - - - - - -
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Architecture - Reference Manual - Guides
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Invoking multiple primitives as a single atomic operation

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-
-

It is often necessary to invoke multiple operations involving a reschedule as a single atomic operation.
- ChibiOS/RT already implements APIs that perform complex operations, as example the API chSemSignalWait() performs two operations atomically.
- If more complex operations are required in your application then it is possible to build macro-operations, see the following example:

-
  chSysLock();
-
-  chSemSignalI(&sem1);
-  chSemSignalI(&sem2);
-  chMtxUnlockS();
-  chSchRescheduleS();
-
-  chSysUnlock();
-

The above example performs a signal operation on two semaphores, unlocks the last acquired mutex and finally performs a reschedule. All the operations are performed atomically.
- An hypothetical chSemSignalSignalWait() operation could be implemented as follow:

-
  chSysLock();
-
-  chSemSignalI(&sem1);
-  chSemSignalI(&sem2);
-  chSemWaitS(&Sem3);  /* May reschedule or not. */
-  chSchRescheduleS(); /* This one reschedules if necessary. */
-
-  chSysUnlock();
-

In general multiple I-Class and (non rescheduling) S-Class APIs can be included and the block is terminated by a rescheduling S-Class API. An extra chSchRescheduleS() can be present at the very end of the block, it only reschedules if a reschedule is still required.

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- - diff --git a/ChibiOS_2.0.8/docs/html/article_create_thread.html b/ChibiOS_2.0.8/docs/html/article_create_thread.html deleted file mode 100644 index fcd7c05..0000000 --- a/ChibiOS_2.0.8/docs/html/article_create_thread.html +++ /dev/null @@ -1,175 +0,0 @@ - - -ChibiOS/RT: How to create a thread - - - - - - - - - - - -
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How to create a thread

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-
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At the system startup there are already two active threads:

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    -
  • Idle thread. This thread has the lowest priority in the system so it runs only when the other threads in the system are sleeping. This threads usually switches the system in a low power mode and does nothing else.
    • -
  • Main thread. This thread executes your main() function at startup. The main thread is created at the NORMALPRIO level but it can change its own priority if required. It is from the main thread that the other threads are usually created.
    • -
-

There are two kind of threads in ChibiOS/RT:

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    -
  • Static Threads. This kind of threads are statically allocated in memory. The memory used by the thread cannot reused except for restarting the threads.
    • -
  • Dynamic Threads. Threads created by allocating memory from a memory heap or a memory pool.
    • -
-

Creating a static thread

-

In order to create a static thread a working area must be declared using the macro WORKING_AREA as shown:

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static WORKING_AREA(myThreadWorkingArea, 128);
-

This macro reserves 128 bytes of stack for the thread and space for all the required thread related structures. The total size and the alignment problems are handled inside the macro, you only need to specify the pure stack size.
- A thread can be started by invoking chThdCreateStatic() as shown in this example:

-
  Thread *tp = chThdCreateStatic(myThreadWorkingArea,
-                                 sizeof(myThreadWorkingArea),
-                                 NORMALPRIO,    /* Initial priority.    */
-                                 myThread,      /* Thread function.     */
-                                 NULL);         /* Thread parameter.    */
-

The variable tp receives the pointer to the thread object, it is taken by other APIs as parameter.
- Now a complete example:

-
/*
- * My simple application.
- */
-
-#include <ch.h>
-
-/*
- * Working area for the LED flashing thread.
- */
-static WORKING_AREA(myThreadWorkingArea, 128);
-
-/*
- * LED flashing thread.
- */
-static msg_t myThread(void *arg) {
-
-  while (TRUE) {
-    LED_ON();
-    chThdSleepMilliseconds(500);
-    LED_OFF();
-    chThdSleepMilliseconds(500);
-  }
-}
-
-int main(int argc, char *argv[]) {
-
-  /* Starting the flashing LEDs thread.*/
-  (void)chThdCreateStatic(myThreadWorkingArea, sizeof(myThreadWorkingArea),
-                          NORMALPRIO, myThread, NULL);
-  .
-  .
-  .
-}
-

Note that the memory allocated to myThread() is statically defined and cannot be reused. Static threads are ideal for safety applications because there is no risk of a memory allocation failure because progressive heap fragmentation.

-

Creating a dynamic thread using the heap allocator

-

In order to create a thread from a memory heap is very easy:

-
  Thread *tp = chThdCreateFromHeap(NULL,            /* NULL = Default heap. */
-                                   THD_WA_SIZE(128),/* Stack size.          */
-                                   NORMALPRIO,      /* Initial priority.    */
-                                   myThread,        /* Thread function.     */
-                                   NULL);           /* Thread parameter.    */
-

The memory is allocated from the spawned heap and the thread is started. Note that the memory is not freed when the thread terminates but when the thread final status (its return value) is collected by the spawning thread. As example:

-
static msg_t myThread(void *arg) {
-
-  unsigned i = 10;
-  while (i > 0) {
-    LED_ON();
-    chThdSleepMilliseconds(500);
-    LED_OFF();
-    chThdSleepMilliseconds(500);
-    i--;
-  }
-  return (msg_t)i;
-}
-
-int main(int argc, char *argv[]) {
-
-  Thread *tp = chThdCreateFromHeap(NULL, THD_WA_SIZE(128), NORMALPRIO+1,
-                                   myThread, NULL);
-  if (tp == NULL)
-    chSysHalt();    /* Memory exausted. */
-  
-  /* The main thread continues its normal execution.*/
-  .
-  .
-  /*
-   * Now waits for the spawned thread to terminate (if it has not terminated
-   * already) then gets the thread exit message (msg) and returns the
-   * terminated thread memory to the heap (default system heap in this
-   * example).
-   */
-  msg_t msg = chThdWait(tp);
-  .
-  .
-}
-

Creating a dynamic thread using the heap allocator

-

A pool is a collection of equally sized memory blocks, creating a thread from a memry pool is very similar to the previous example but the memory of terminated threads is returned to the memory pool rather than to a heap:

-
static msg_t myThread(void *arg) {
-
-  unsigned i = 10;
-  while (i > 0) {
-    LED_ON();
-    chThdSleepMilliseconds(500);
-    LED_OFF();
-    chThdSleepMilliseconds(500);
-    i--;
-  }
-  return (msg_t)i;
-}
-
-int main(int argc, char *argv[]) {
-
-  Thread *tp = chThdCreateFromMemoryPool(myPool, NORMALPRIO+1, myThread, NULL);
-  if (tp == NULL)
-    chSysHalt();    /* Pool empty. */
-  
-  /* The main thread continues its normal execution.*/
-  .
-  .
-  /*
-   * Now waits for the spawned thread to terminate (if it has not terminated
-   * already) then gets the thread exit message (msg) and returns the
-   * terminated thread memory to the original memory pool.
-   */
-  msg_t msg = chThdWait(tp);
-  .
-  .
-}
-
-
-Generated on Sun Nov 28 2010 14:09:54 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_debug.html b/ChibiOS_2.0.8/docs/html/article_debug.html deleted file mode 100644 index 20e32fa..0000000 --- a/ChibiOS_2.0.8/docs/html/article_debug.html +++ /dev/null @@ -1,125 +0,0 @@ - - -ChibiOS/RT: Debugging ChibiOS/RT applications - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Debugging ChibiOS/RT applications

-
-
-

ChibiOS/RT offers several mechanisms that can help in the debug phase of the development cycle.

-

What this guide does not cover

-

This guide assumes knowledge in following areas:

-
    -
  • General knowledge of embedded development.
    • -
  • RTOS concepts.
    • -
  • Setup of your specific target hardware and toolchain.
    • -
  • Knowledge of your toolchain. The guide will explain what you need to do, not how it is done using you specific debugger, compiler, JTAG probe and target hardware.
    • -
-

Helpful debugging configuration settings

-

There are several settings in your kernel configuration file (see templates/chconf.h) that you may want to enable during debugging and in general during the whole development process.

-
    -
  • CH_OPTIMIZE_SPEED=FALSE, this disables inlining into the kernel code and makes it easier to debug using your debugger, you may also want to reduce or disable compiler optimizations (-O0 using GCC).
    • -
  • CH_DBG_ENABLE_CHECKS=TRUE, this setting enables the checks on the API parameters, useful to understand if you are passing wrong parameters to the OS functions.
    • -
  • CH_DBG_ENABLE_ASSERTS=TRUE, this setting enables the OS internal consistency checks, this can trap several kind of errors in the user code (or in the kernel itself).
    • -
  • CH_DBG_ENABLE_STACK_CHECK=TRUE, this setting enables checks on threads stack overflow. Note that this option is not available in all ports, check your port documentation. If not supported then it is silently ignored, see also the article Stacks and stack sizes.
    • -
  • CH_DBG_FILL_THREADS=TRUE, this setting enables the threads workspace filling, this can help examining the stack usage from your debugger.
    • -
-

Note that all the failed checks lock the kernel into the port_halt() function. In order to assess what triggered the lock the global variable panic_msg must be inspected using the debugger, the variable is a pointer to an error message (a zero terminated string), the pointer may contain NULL if the lock was triggered by a stack overflow.

-

Common errors and symptoms

-

There are some common errors while using an RTOS, use the following table as a check list, if your problem is not a generic programming error then probably it is one of the following common RTOS/embedded related mistakes:

-
    -
  • Insufficient stack allocated to one or more threads.
    - Common symptoms:
      -
    • Target instability.
      • -
    • Target locked into the port_halt() function.
      • -
    • Target trapped into an exception handler (architecture dependent).
      • -
    • Target apparent self reset (not real resets usually).
      • -
    -
    • -
  • Insufficient stack allocated to the IRQ stack (in those architectures that have a separate IRQ stack, ARM as example).
    - Common symptoms:
      -
    • Target instability.
      • -
    • Target trapped into an exception handler (architecture dependent).
      • -
    • Target apparent self reset (not real resets usually).
      • -
    -
    • -
  • Use of a non reentrant function from within an interrupt handler, as example most C runtime functions.
    - Common symptoms:
      -
    • Target instability.
      • -
    • Unexpected application behavior.
      • -
    -
    • -
  • Missing use of a mutual exclusion mechanism to protect data (or non reentrant code) shared among multiple threads and/or threads and interrupt handlers, see also the article Mutual Exclusion guide.
    - Common symptoms:
      -
    • Target instability.
      • -
    • Unexpected application behavior.
      • -
    -
    • -
  • Use of S-class or I-class APIs outside a proper lock state, see the Kernel Concepts article, specifically the API Names Suffixes and System States sections.
    - Common symptoms:
      -
    • Target instability.
      • -
    • Target trapped into an exception handler (architecture dependent).
      • -
    • Target apparent self reset (not real resets usually).
      • -
    -
    • -
  • Use of a non I-class API from an interrupt handler, see the Kernel Concepts article, specifically the API Names Suffixes and System States sections.
    - Common symptoms:
      -
    • Target instability.
      • -
    • Target trapped into an exception handler (architecture dependent).
      • -
    • Target apparent self reset (not real resets usually).
      • -
    -
    • -
  • Wrong threads priority assignment. One of the most critical things to do when designing an RTOS based application is to assign correct priorities to the threads in the system.
    - Common symptoms:
      -
    • Excessive or unpredictable response times.
      • -
    • Threads that appear to be never executed (CPU intensive threads at higher priority).
      • -
    -
    • -
-

General suggestions

-

For the less expert users, there are several things you may do in order to minimize the need for debugging:

-
    -
  • Read carefully the documentation first.
    • -
  • Try to find a code examples for things are you going to do, good sources are: the documentation, the test code, under "./test" you will find examples for almost any API in the ChibiOS/RT kernel and most common RTOS related tasks, under "./testhal" there are examples regarding the various device drivers, the various demos contain good code samples too).
    • -
  • Start your application from an existing demo, add things one at a time and test often, if you add too many things at once then finding a small problem can become a debugging nightmare. Follow the cycle: think, implement, test, repeat.
    • -
  • If you are stuck for too much time then consider asking for advice.
    • -
  • Report bugs and problems, bugs can be fixed, problems can become new articles in the documentation (this and other documentation articles spawned from questions in the forum or in the tracker).
    • -
  • Never give up :-)
    • -
-
-
-Generated on Sun Nov 28 2010 14:09:54 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_design.html b/ChibiOS_2.0.8/docs/html/article_design.html deleted file mode 100644 index 744ef54..0000000 --- a/ChibiOS_2.0.8/docs/html/article_design.html +++ /dev/null @@ -1,98 +0,0 @@ - - -ChibiOS/RT: Designing an embedded application - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Designing an embedded application

-
-
-

ChibiOS/RT offers a variety of mechanisms and primitives, often it is better to focus on a single approach for the system design and use only part of the available subsystems.
- When designing your application you may choose among several design alternatives:

- -

-Single threaded superloop

-

Correct, single thread, it is not mandatory to use the multithreading features of the OS. You may choose to implements everything as a complex state machine handled in the main thread alone. In this scenario the OS still offers a variety of useful mechanisms:

-
    -
  • Interrupt handling.
    • -
  • Virtual Timers, very useful in state machines in order to handle time triggered state transitions.
    • -
  • Power management.
    • -
  • Event Flags and/or Semaphores as communication mechanism between interrupt handlers and the main.
    • -
  • I/O queues.
    • -
  • Memory allocation.
    • -
  • System time.
    • -
-

In this configuration the kernel size is really minimal, everything else is disabled and takes no space. You always have the option to use more threads at a later time in order to perform separate tasks.

-

-Message Passing

-

In this scenario there are multiple threads in the system that never share data, everything is done by exchanging messages. Each thread represents a service, the other threads can request the service by sending a message.
- In this scenario the following subsystems can be used:

-
    -
  • Synchronous Messages.
    • -
  • Mailboxes (asynchronous message queues).
    • -
-

The advantage of this approach is to not have to deal with mutual exclusion, each functionality is encapsulated into a server thread that sequentially serves all the requests. As example, you can have the following scenario:

-
    -
  • A buffers allocator server.
    • -
  • A disk driver server.
    • -
  • A file system server.
    • -
  • One or more client threads.
    • -
-

Example:
-
-

-
-inline_dotgraph_10.dot - -
-


-
- Note that the threads should not exchange complex messages but just pointers to data structures in order to optimize the performance. Also note that a thread can be both client and server at the same time, the FS service in the previous scenario as example.

-

-Threads sharing data

-

This is the most common scenario, several threads have access to both their private data and shared data. Synchronization happens with one of the mechanisms described in the Mutual Exclusion guide article.
-

-

-Mixed

-

All the above approaches can be freely mixed in a single application but usually I prefer to choose a way and consistently design the system around it. The OS is a toolbox that offers a lot of tools but you don't have to use them all necessarily.

-
-
-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_eclipse.html b/ChibiOS_2.0.8/docs/html/article_eclipse.html deleted file mode 100644 index d85a60c..0000000 --- a/ChibiOS_2.0.8/docs/html/article_eclipse.html +++ /dev/null @@ -1,143 +0,0 @@ - - -ChibiOS/RT: Setting up a free embedded IDE - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Setting up a free embedded IDE

-
-
-

Free advanced embedded IDE for ChibiOS/RT. details This article will explain how to setup a free toolchain for use with ChibiOS/RT and general embedded development.
- The guide is meant mainly for Windows users but notes about Linux and MAC OSX are present where the setup differs, mostly the toolchain is exactly the same.

-

What this guide does not cover

-

We will not enter in details of common system tasks like and not limited to:

-
    -
  • Installing applications (unless a special procedure is required).
    • -
  • Creating desktop shortcuts.
    • -
  • Adding paths to the PATH variable.
    • -
  • Creating environment variables.
    • -
  • Any other normal PC usage task.
    • -
  • Use of the toolchain, the use is covered by the Embedded development using Eclipse article.
    • -
-

Article Index

- -

-Required Components

-

The first thing to do is to download all the required components, beginners should avoid the optional components initially:

-
    -
  • A JTAG probe supporting GDB and OpenOCD, a list of compatible devices is available on the OpenOCD home page, more exactly here.
    • -
  • ChibiOS/RT latest stable release.
    • -
  • Java runtime, you probably already have this installed.
    • -
  • Eclipse IDE for C/C++ Developers
    • -
  • YAGARTO ARM toolchain for Windows, note that you need both the compiler and the tools (make and binutils).
    • -
  • Zylin plugin for on-board debugging, see Zylin Plugin Installation section.
    • -
  • OpenOCD binaries for Windows, YAGARTO does not provide those anymore but you can download them from here. Linux users can try here.
    • -
  • Optional, MinGW compiler, needed if you want to compile, debug and run the simulator from within Eclipse. Linux users do not need this one because all Linux distributions include the native GCC.
    • -
  • Optional, Doxygen, it is only required if you want to generate documentation from source files.
    • -
  • Optional, Graphwiz, it is only required if you want to generate diagrams within documentation from source files.
    • -
  • Optional, Eclox, it is only required if you want to generate documentation from source files from within Eclipse.
    • -
-

-ChibiOS/RT Installation

-

Just unzip it into a directory in your home folder, Windows users may consider c:\projects\chibios. It is strongly suggested to not put version numbers into the ChibiOS/RT directory name because Eclipse workspaces have absolute paths inside and you don't want to setup everything again each time a new ChibiOS/RT version is released, use plain "chibios".

-

-GCC ARM Compiler Installation

-

Simply follow the YAGARTO installation guide. Linux/MACOS users have several other options:

-
    -
  • Download the latest CodeSourcery free Linux package.
    • -
  • Build it yourself, Liam recommended a build script here, it looks interesting.
    • -
-

Make sure that the compiler binaries directory is listed in the PATH variable or Eclipse would not be able to locate it.

-

-Eclipse Installation

-

Eclipse is distributed into a compressed archive, there is no installation procedure:

-
    -
  • Verify if you have Java installed, if not install the runtime. You may verify this using the command: "java -version". Make sure you have at least version 1.6.
    • -
  • Create an eclipse directory in your home and unpack the archive there. Windows users may unpack it into c:\program files\eclipse.
    • -
  • Create a desktop shortcut or other way to launch the Eclipse executable easily.
    • -
  • Launch Eclipse.
    • -
  • Eclipse will ask you a directory for its initial workspace, make it point to the ChibiOS/RT root directory (you may have as many workspaces you want, keep this for later), make sure to select the check box or it will ask you again each time.
    -
    -
    -tool001.jpg -
    -
    -
    • -
  • Now you should see the welcome screen, close it and you will be in the normal C/C++ perspective.
    • -
  • Unselect "Project->Build Automatically" unless you like insanity.
    • -
  • Disable the "usage collector" in "Window->Preferences->Usage_Data_Collector" by unselecting "Enable - capture".
    • -
  • If you are behind a proxy or firewall (corporate users usually are) configure the correct parameters in "Window->Preferences->General->Network_Connections".
    • -
  • Let Eclipse auto update to the latest version "Help->Check_for_Updates".
    • -
-

-Zylin Plugin Installation

-

Eclipse requires an hardware debugger component in order to perform on board execution and debug.

-
    -
  • Open Eclipse, then "Help->Install_New_Software...".
    • -
  • Press the "Add..." button and put http://opensource.zylin.com/zylincdt into the location field, then press OK. The Zylin plugin will appear in the available plugins view, select and install it.
    -
    -
    -tool002.jpg -
    -
    • -
-

-OpenOCD Installation

-

Windows users just have to use the installer. Linux user should follow the normal installation procedure for deb or rpm packages, of course it is also possible to build it from the source code.

-

-Doxygen Installation

-

Just use the installer, Linux users probably have Doxygen already available from the repositories. Make sure that the Doxygen binaries directory is listed in the PATH variable or Eclipse would not be able to locate it.

-

-Graphviz Installation

-

Just use the installer, Linux users probably have Graphviz already available from the repositories. Make sure that the Graphviz binaries directory is listed in the PATH variable or Doxygen would not be able to locate it.

-

-Eclox Installation

-

Use the same installation steps used for the Zylin plugin except use http://download.gna.org/eclox/update as URL. Install "Eclox" not "Eclox - Hot". After installing Eclox you will be able to compile Doxygen documentation using the button with the blue @ inside.

-
-
-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_eclipse2.html b/ChibiOS_2.0.8/docs/html/article_eclipse2.html deleted file mode 100644 index 47ef6ed..0000000 --- a/ChibiOS_2.0.8/docs/html/article_eclipse2.html +++ /dev/null @@ -1,229 +0,0 @@ - - -ChibiOS/RT: Embedded development using Eclipse - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Embedded development using Eclipse

-
-
-

Compiling and debugging ChibiOS/RT applications using Eclipse.

-

This article will explain how to use an Eclipse based toolchain (see Setting up a free embedded IDE) to develop ChibiOS/RT based applications. This guide will allow you to:

-
    -
  • Importing ChibiOS/RT demos into the Eclipse environment.
    • -
  • Edit and reformat your source code.
    • -
  • Compile and examine errors and warnings.
    • -
  • Upload your program on the target board.
    • -
  • Debug your code on the target board both in high level language and assembler.
    • -
  • Develop embedded applications with or without ChibiOS/RT.
    • -
-

What this guide does not cover

-

This guide assumes knowledge in following areas:

-
    -
  • OpenOCD setup is not covered by this guide because the setup changes depending on the JTAG probe used, the target MCU and also the target board. The guide will show the setup for a specific JTAG probe and a specific target, a valuable source for the OpenOCD setup is the dedicated forum, most questions you may have about OpenOCD have most likely already been answered there.
    • -
  • Hardware setup.
    • -
-

In general this guide is not a replacement for the Eclipse, GCC, Make, binutils, newlib, GDB, OpenOCD user manuals, the guide simply aims to give you a faster start.

-

Article Index

- -

-Required Components

-

This guide requires:

-
    -
  • An Eclipse/GCC/OpenOCD based toolchain, as example the one described in the article Setting up a free embedded IDE.
    • -
  • An Olimex ARM-USB-OCD JTAG probe, this guide applies to any other ARM JTAG probe as long it is supported by OpenOCD.
    • -
  • An Olimex STM32-P103 target board, this guide applies to any other ARM target except for the OpenOCD setup part.
    • -
  • A terminal emulator for capturing the board serial output, Windows users may use Hyper Terminal, Linux and MAC OS-X users may use CuteCom. All ChibiOS/RT demos generate on the serial port a test report when a button on the target board is pressed, other demos may activate a command shell on the serial port, in both cases a terminal emulator is required.
    • -
-

-Importing existing ChibiOS/RT demos into Eclipse

-

The first step is to import a project into the Eclipse environment. ChibiOS/RT demos do not include Eclipse project files but just a normal Makefile. Eclipse is able to import a Makefile project and create its own project file so this is not a problem. This is how it is done:

-
    -
  • Open you Eclipse environment and select the workspace created into the ChibiOS/RT project directory.
    • -
  • From within Eclipse select "File->New->C_Project", a dialog box will show.
    • -
  • Select "Makefile_project->Empty_Project" in the "Project type:" box.
    • -
  • Select "-- Other Toolchain --" in the "Toolchains:" box.
    • -
  • Unselect the "Use default location" check box.
    • -
  • Select the demo directory using the "Browse..." button. Something like "C:\Projects\ChibiOS-RT\demos\ARMCM3-STM32F103-GCC" will appear in the "Location:" box.
    • -
  • In the project name box put the same name of the directory containing the demo, ARMCM3-STM32F103-GCC in this example.
    -
    -
    -eclipse003.jpg -
    -
    -
    • -
  • Press the "Finish" button and the project will be created and shown in the "Project Explorer".
    • -
  • Right click on the imported project and select "Index->Rebuild", this will make Eclipse build its internal symbols database.
    • -
  • Repeat the above steps for each ChibiOS/RT demo you want to import in Eclipse, all the demos that have a makefile can be imported.
    • -
-

-Creating a new ChibiOS/RT application

-

If you want to create a new application it is recommended that you create a Makefile project first then you can import it into eclipse using the above procedure. Makefile projects have the advantage that can be compiled everywhere even without Eclipse. Creation steps:

-
    -
  • Create your own development directory under the ChibiOS/RT installation directory, as example "chibios/myprojects".
    • -
  • Copy an existing demo, of course choose a demo using your same target, under the new directory and rename it, as example "chibios/myprojects/myapplication".
    • -
  • Customize the Makefile if needed, usually you just need to do this if your application is composed by more than one source file. You may also want to remove the ChibiOS/RT test code from your application.
    • -
  • Once your makefile is ready, import the project under the Eclipse workspace using the procedure described in Importing existing ChibiOS/RT demos into Eclipse.
    • -
-

-Compiling and Cleaning applications

-

Once imported, an application can be compiled by using the "Build All" in the toolbar or by right clicking on the project and selecting "Build - Project". In order to clean a project (removing all the temporary and binary files) right click on the project and select "Clean Project".
-
-

-
-eclipse004.jpg -
-


- The compilation result is visible as a complete log in the "Console" window, the detail of all errors an warnings is available in the "Problems" window.
-
-

-
-eclipse005.jpg -
-


- The build process produces the binary files specified in the Makefile, all the ChibiOS/RT demos produce binary files named ch.elf, ch.bin and/or ch.hex. The image must be loaded on the target board in order to execute it. The build process usually creates also some other useful files containing details about the built application (usually named ch.map and ch.dmp).

-

-Preparing for Debug

-

In order to debug your application a debug configuration must be created. The configuration instructs GDB (the source debugger used by Eclipse) on how to load the image, load the symbols and place the initial breakpoint in the make function. Note that GDB performs its function by connecting to a "GDB server", the DGB server implements the low level communication with the target device through the JTAG probe. In our scenario the GDB server functionality is performed by OpenOCD, this mean that OpenOCD must be running while performing a debug session within Eclipse.

-

-Creating a GDB Debug Configuration

-

A target specific debug configuration is required in order to:

-
    -
  • Establish a connection with the GDB server.
    • -
  • Stop and reset the target.
    • -
  • Upload the binary code in Flash or RAM.
    • -
  • Set an initial breakpoint in the main function.
    • -
  • Start the target (which will immediately stop on the breakpoint).
    • -
-

The first thing to do is to open the "Debug Configurations..." dialog:
-
-

-
-eclipse006.jpg -
-


- The configuration dialog will appear, we must create a native Zylin configuration:
-
-

-
-eclipse007.jpg -
-


- Now we must give the configuration a name, "ARMCM3-STM32F103-GCC (flash and - run)" in this example, then setup the various configuration pages as follow:
-
- The "Main" tab:

-
-eclipse008.jpg -
-


-
- The "Debugger" tab:

-
-eclipse009.jpg -
-


-
- The "Commands" tab:

-
-eclipse010.jpg -
-


- Note that the "Commands" tab contains the part that changes depending on the target. The complete commands sequence (it is not fully visible in the image) for STM32 is:

-
 monitor soft_reset_halt
- monitor wait_halt
- monitor poll
- monitor flash probe 0
- monitor stm32x mass_erase 0
- monitor flash write_bank 0 ch.bin 0
- monitor soft_reset_halt
- symbol-file ch.elf
- thbreak main
- continue
-


-
- The "Common" tab:

-
-eclipse011.jpg -
-


- Now the debug configuration is complete.

-

-Configuring and running OpenOCD

-

OpenOCD must be run, with appropriate parameters, before starting your debug session. Please refer to the OpenOCD documentation in order to properly launch it for your target.
-**To be completed**

-

-Debugging

-

Now we are ready to debug an application on the target. Note that Eclipse have a mechanism called "Perspectives", you edit and compile your source code while you are in the "C/C++ perspective" while the debugging is performed in the "Debug perspective". You can switch perspective at any time, even while there is an active debug session. If you install more of the many Eclipse extension plugins (there are thousands) you may have even more perspectives available.

-

-Starting a Debug Session

-

In order to start a debugging session first make sure that OpenOCD is running then press the drop down menu on the right side of the debug icon in the toolbar (the small green bug) and select your debug configuration (we created just one but you may have multiple debug configurations in your project, as example I usually create another debug configuration that just starts the target without uploading the code).
-
-

-
-eclipse012.jpg -
-


- The debugger will be initialized, you will see the operation in progress on the console then Eclipse will switch to the debug perspective and you will see your program stopped on the default breakpoint in the main function.
-
-

-
-eclipse013.jpg -
-


- From there you can perform all the usual debugging tasks, set breakpoints, single step execution, variables, memory and registers inspection etc. Please refer to the Eclipse documentation about those "normal" operations. Note that if the debugging start procedure hangs then there is probably an error in your configuration or problems with the target, read the console log and/or the OpenOCD output in order to understand where the problem is.

-

-Stopping a Debug Session

-

From the debug perspective press the stop button (small red square) in the debug window, the target will be stopped and you may both return to the C/C++ perspective or start it again.

-
-
-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_events.html b/ChibiOS_2.0.8/docs/html/article_events.html deleted file mode 100644 index 02127f8..0000000 --- a/ChibiOS_2.0.8/docs/html/article_events.html +++ /dev/null @@ -1,73 +0,0 @@ - - -ChibiOS/RT: Events Explained - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Events Explained

-
-
-

Events are an important feature in ChibiOS/RT, most device drivers generate events in order to notify the application that something happened at the I/O level.
- While event flags are not something unknown in other operating systems, their peculiar implementation in ChibiOS/RT requires a more in depth explanation.
- Lets start with the events related terminology:

-
    -
  • Event Source, an EventSource is a system object that can be broadcasted asynchronously in response of a system event, as example, when the CAN driver receives a packet from the CAN bus it broadcasts an event source in order to inform the registered threads that a packet has just arrived.
    • -
  • Broadcast, the operation performed on an event source in order to inform the registered threads that an event just occurred. Broadcasting can happened both in interrupt handlers and in threads.
    • -
  • Event Listener, a system object that associates a Thread object to an event source. The process of associating a Thread to an EventSource using an EventListener is called registration.
    • -
  • Registration, action performed by a thread in order to be informed of events from a specific event source. Of course a thread can be registered on more than one event source by using multiple EventListener objects. Threads can also unregister from an event source.
    • -
  • Pend, each thread has a mask of pending events. The broadcast operation pends an event mask on all the registered threads.
    • -
  • Wait, synchronous operation performed by a thread in order to wait a specific combination of events. The API offers a variety of wait functions, please refer to the events API documentation.
    • -
-

Note that events are asynchronously generated, as example in an interrupt handler, but are synchronously served.

-

Events related data structures

-

The following diagram explains the relationship between an event source, its list of event listeners and the registered threads.

-
-inline_dotgraph_11.dot - -
-

Note that each event listener has a different bit mask to be pended on its associated thread when the event source is broadcasted, this means that each thread can define its own event identifiers independently. A broadcast operation can also pend more than one bit on the registered threads.
- The threads have a variety of wait primitives, they can wait for one or more event flags to become pending, and can also specify AND/OR conditions, as example a thread can wait for any event to become pending or wait for all the specified events to become pending.
- The field p_epending is the mask of the currently pending events, the field p_ewmask is the mask of the events the thread is interested on in that moment (AND or OR condition depending on the invoked wait API).

-

Use Scenarios

-

Events are best used when one of more of the following conditions are required:

-
    -
  • Having to wait on multiple conditions, Events are the only mechanism that easily allow that.
    • -
  • Synchronous response to one or more asynchronous events.
    • -
  • Single threaded applications working in a event driver environment (but events are not limited to single threaded applications).
    • -
-
-
-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_integrationguide.html b/ChibiOS_2.0.8/docs/html/article_integrationguide.html deleted file mode 100644 index 89de6d6..0000000 --- a/ChibiOS_2.0.8/docs/html/article_integrationguide.html +++ /dev/null @@ -1,94 +0,0 @@ - - -ChibiOS/RT: Integration Guide - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Integration Guide

-
-
-

All the delivered ChibiOS/RT demos are stand alone applications so if you just start your application from an existing demo there isn't any integration effort, you are simply using the existing makefiles, the default startup files etc, minimal effort.
- The matter is very different if you are going to integrate the OS into a different runtime framework or if you want to use a different build system, in that case you have the problem to integrate the OS source code into your application.

-

What this guide does not cover

-

This guide has a limited scope, the following topics are handled elsewhere:

-
    -
  • Porting the OS to different architectures or different compilers is not covered in this guide, see Porting ChibiOS/RT for Dummies instead.
    • -
  • This guide does not describe any specific environment or development tool, it is assumed you already know in detail the environment you want to work with.
    • -
-

Article Index

- -

-Integrating the Kernel

-

This section covers the scenario where you want to use the ChibiOS/RT kernel into an existing application. In order to accomplish this you need to import in your project two components:

-
    -
  • The portable kernel.
    • -
  • The port layer for your microcontroller.
    • -
-

See the Architecture for more details. You need to add the following files to your build process:

-
    -
  • All the source files contained under ./os/kernel/src, note that you should add all of them even if you don't plan to use some of the subsystems. Unused subsystems can be excluded from the kernel configuration file chconf.h.
    • -
  • All the source files contained under ./os/ports/<compiler>/<architecture>. Note that those could be both C source files and assembler source files and that some architectures have an extra directories layer containing files required for a specific platform.
    • -
-

You also need to add to the compiler options the following paths for searching header files:

-
    -
  • The portable kernel headers ./os/kernel/include.
    • -
  • The port layer headers ./os/ports/<compiler>/<architecture>.
    • -
-

-Integrating the HAL

-

If, in addition to the kernel as described in the previous section, you also need to integrate the HAL into your application you also need to import the following components:

-
    -
  • HAL portable files.
    • -
  • Platform specific files.
    • -
-

See the Architecture for more details. You need to add the following files to your build process:

-
    -
  • All the source files contained under ./os/hal/src, note that you should add all of them even if you don't plan to use some of the subsystems. Unused drivers can be excluded from the HAL configuration file halconf.h.
    • -
  • All the source files contained under ./os/hal/platforms/<platform>.
    • -
  • All the source files contained under ./boards/<board_model>.
    • -
-

You also need to add to the compiler options the following paths for searching header files:

-
    -
  • The portable HAL headers ./os/hal/include.
    • -
  • The platform layer headers ./os/hal/platforms/<platform>.
    • -
  • The board description headers ./boards/<board_model>.
    • -
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-
-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_interrupts.html b/ChibiOS_2.0.8/docs/html/article_interrupts.html deleted file mode 100644 index 6b5e942..0000000 --- a/ChibiOS_2.0.8/docs/html/article_interrupts.html +++ /dev/null @@ -1,76 +0,0 @@ - - -ChibiOS/RT: How to write interrupt handlers - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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How to write interrupt handlers

-
-
-

Since version 1.1.0 ChibiOS/RT offers a cross-platform method for writing interrupt handlers. Port-related and compiler-related details are encapsulated within standard system macros.

-

Writing Regular Interrupt handlers

-

A Regular Interrupts handler (see Interrupt Classes) must be written using the following general form:

-
CH_IRQ_HANDLER(myIRQ) {
-  CH_IRQ_PROLOGUE();
-  
-  // IRQ handling code, preemptable if the architecture supports it.
-  
-  chSysLockFromIsr();
-  // Invocation of some I-Class system APIs, never preemptable.
-  chSysUnlockFromIsr();
-  
-  // More IRQ handling code, again preemptable.
-
-  CH_IRQ_EPILOGUE();
-}
-

Writing Fast Interrupt handlers

-

In those architectures (ARM7TDMI and ARM Cortex-Mx) supporting Fast Interrupts (see Interrupt Classes) handlers must be written using the following general form:

-
CH_FAST_IRQ_HANDLER(myIRQ) {
-
-  // Fast IRQ handling code, preemptable if the architecture supports it.
-  // The invocation of any API is forbidden here because fast interrupt
-  // handlers can preempt the kernel even within its critical zones in
-  // order to minimize latency.
-}
-

Handlers naming

-

A note about the handler name "myIRQ", in some ports it must be a vector number rather than a function name, it could also be a name from within a predefined set, see the notes about the various ports.

-

Important Notes

-
    -
  • There is an important application note about ARM7 interrupt handlers, please read about it in the ARM7 port section: ARM7 Interrupt Handlers
    • -
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-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_jitter.html b/ChibiOS_2.0.8/docs/html/article_jitter.html deleted file mode 100644 index aae22f3..0000000 --- a/ChibiOS_2.0.8/docs/html/article_jitter.html +++ /dev/null @@ -1,87 +0,0 @@ - - -ChibiOS/RT: Response Time and Jitter - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Response Time and Jitter

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-
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Response time jitter is one of the most sneaky source of problems when designing a real time system. When using a RTOS like ChibiOS/RT one must be aware of what the jitter is and how it can affect the performance of the system. A good place to start is this Wikipedia article.

-

Interrupt handlers execution time

-

The total execution time of an interrupt handler includes:

-
    -
  • Hardware interrupts latency, this parameter is pretty much fixed and characteristic of the system.
    • -
  • Fixed handler overhead, as example registers stacking/unstacking.
    • -
  • Interrupt specific handler code execution time, as example, in a serial driver, this is the time used by the handler to transfer data from/to the UART.
    • -
  • OS overhead. Any operating system requires to run some extra code in interrupt handlers in order to handle correct preemption and Context Switching.
    • -
-

Interrupt Response Time

-

The Interrupt Response Time is the time from an interrupt event and the execution of the handler code. Unfortunately this time is not constant in most cases, see the following graph:

-
-inline_dotgraph_12.dot - -
-

In this scenario the jitter (busy state) is represented by the sum of:

-
    -
  • Higher or equal priority interrupt handlers execution time combined. This time can go from zero to the maximum randomly. This value can be guaranteed to be zero only if the interrupt has the highest priority in the system.
    • -
  • Highest execution time among lower priority handlers. This value is zero on those architectures (Cortex-M3 as example) where interrupt handlers can be preempted by higher priority sources.
    • -
  • Longest time in a kernel lock zone that can delay interrupt servicing. This value is zero for fast interrupt sources, see System States.
    • -
-

Threads Flyback Time

-

This is the time between an event, as example an interrupt, and the execution of the thread that will process it. Imagine the following graph as the continuation of the previous one.

-
-inline_dotgraph_13.dot - -
-

In this scenario all the jitter sources previously discussed are also present and there is the added jitter caused by the activity of the higher priority threads.

-

Jitter Mitigation

-

For each of the previously described jitter sources there are possible mitigation actions.

-

Interrupt handlers optimization

-

An obvious mitigation action is to optimize the interrupt handler code as much as possible for speed.
- Complex actions should never be performed in interrupt handlers. An handler should just serve the interrupt and wakeup a dedicated thread in order to handle the bulk of the work.
- Another possible mitigation action is to evaluate if a specific interrupt handler really needs to interact with the OS, if the handler uses full stand-alone code then it is possible to remove the OS related overhead.
-

-

Kernel lock zones

-

The OS kernel protects some critical internal data structure by disabling (fully in simple architecture, to some extent in more advanced microcontrollers) the interrupt sources. Because of this the kernel itself is a jitter cause, a good OS design minimizes the jitter generated by the kernel by using adequate data structures, algorithms and coding practices.
- A good OS design is not the whole story, some OS primitives may generate more or less jitter depending on the system state, as example the maximum number of threads on a certain queue, the maximum number of nested mutexes and so on. Some algorithms employed internally can have constant execution time but others may have linear execution time or be even more complex.

-

Higher priority threads activity

-

At thread level, the response time is affected by the interrupt-related jitter but mainly by the activity of the higher priority threads and contention on protected resources.
- It is possible to improve the system overall response time and reduce jitter by carefully assigning priorities to the various threads and carefully designing mutual exclusion zones.
- The use of the proper synchronization mechanism (semaphores, mutexes, events, messages and so on) also helps to improve the overall system performance. The use of the Priority Inheritance algorithm implemented in the mutexes subsystem can improve the overall response time and reduce jitter but it is not a magic wand, a proper system design comes first.

-
-
-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_lifecycle.html b/ChibiOS_2.0.8/docs/html/article_lifecycle.html deleted file mode 100644 index 4ab9f00..0000000 --- a/ChibiOS_2.0.8/docs/html/article_lifecycle.html +++ /dev/null @@ -1,60 +0,0 @@ - - -ChibiOS/RT: Threads Lifecycle - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Threads Lifecycle

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In ChibiOS/RT threads are divided in two categories:

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    -
  • Static threads. The memory used for static threads is allocated at compile time so static threads are always there, there is no management to be done.
    • -
  • Dynamic threads. Dynamic threads are allocated at runtime from one of the available allocators (see Heaps, Memory Pools).
    • -
-

Dynamic threads create the problem of who is responsible of releasing their memory because a thread cannot dispose its own memory.
- This is handled in ChibiOS/RT through the mechanism of "thread references", When the CH_USE_DYNAMIC option is enabled the threads become objects with a reference counter. The memory of a thread, if dynamic, is freed when the last reference to the thread is released while the thread is in its THD_STATE_FINAL state.
- The following diagram explains the mechanism:

-
-inline_dotgraph_14.dot - -
-


- As you can see the easiest way to ensure that the memory is released is to make another thread perform a chThdWait() on the dynamic thread.
- If all the references to the threads are released while the thread is still alive then the thread goes in a "detached" state and its memory cannot be recovered unless there is a dedicated task in the system that scans the threads through the Registry subsystem, scanning the registry has the side effect to release the zombies (detached and then terminated threads).

-
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-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_manage_memory.html b/ChibiOS_2.0.8/docs/html/article_manage_memory.html deleted file mode 100644 index 649369b..0000000 --- a/ChibiOS_2.0.8/docs/html/article_manage_memory.html +++ /dev/null @@ -1,80 +0,0 @@ - - -ChibiOS/RT: How to manage memory - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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How to manage memory

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-

ChibiOS/RT is a static kernel so you don't need to manage memory at all if your application doesn't really require it. This doesn't mean that the OS is unable to manage memory but just that memory management is an optional part of the whole.
- The OS offers three distinct ways to manage memory, each one with its weaknesses and strengths:

- -

The three mechanisms are able to coexist and are well integrated, as example the heap allocator uses the core memory manager in order to get more memory blocks, memory pools can optionally do the same thing.

-

The three subsystems

-

This is a small comparison table regarding the three subsystems, C-runtime and static objects are thrown in there for comparison:
-
-

- - - - - - - - - - - - - -
Subsystem Free capable Constant time Safe From IRQ Notes
Static Objects N/A N/A YES YES Preferred solution for safety applications.
Core Memory Manager NO YES YES YES Fast and safe but unable to free allocated memory.
Heap Allocator YES NO NO NO Unsafe because fragmentation and not constant time, cannot be used from IRQ handlers.
Memory Pools YES YES YES YES Fast and safe but it can handle fixed size objects only, you may have multiple memory pools however.
C-Runtime YES NO NO NO Unsafe because fragmentation, not constant time, cannot be used from IRQ handlers and not thread safe. The C runtime must also be modified in order to work with the other allocators.
-


- When designing a system it is recommended to proceed as follow:

-
    -
  1. Use static objects and initializers whenever possible.
    2. -
  2. Where dynamic allocation is required without have to free the allocated memory then use the Core Memory Manager allocation APIs.
    3. -
  3. Where dynamic allocation is required evaluate if one or more memory pools can be used.
    4. -
  4. If all the above points do not satisfy your requirements then use the heap allocator.
    5. -
  5. Consider the C-runtime allocator only for legacy code.
    6. -
-
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-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_mutual_exclusion.html b/ChibiOS_2.0.8/docs/html/article_mutual_exclusion.html deleted file mode 100644 index fb08c95..0000000 --- a/ChibiOS_2.0.8/docs/html/article_mutual_exclusion.html +++ /dev/null @@ -1,174 +0,0 @@ - - -ChibiOS/RT: Mutual Exclusion guide - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Mutual Exclusion guide

-
-
-

The most common problem when writing multithreaded code is the synchronization on the shared resources/services.
- ChibiOS/RT offers a rich variety of mechanisms that apparently solve the same problem. I wrote apparently because each mechanism has its pro and cons. This article will introduce the various mechanisms and the explain the right scenarios for each one.

-

Basics

-

Some of the concepts mentioned in this article can be found in the following Wikipedia articles:

- -

Mutual exclusion by System Locks

-

This is the lowest level mechanism, the system is locked by invoking the chSysLock() API and then unlocked by invoking chSysUnlock().
- The implementation is architecture dependent but it is guaranteed to, at least, disable the interrupt sources with hardware priority below or equal the kernel level.

-

Advantages

-
    -
  • It is the lightest as execution time, often a lock or unlock becomes just a single inlined assembler instruction.
    • -
  • It ensures mutual exclusion among threads but also interrupt handling code.
    • -
  • The implementation would ensure mutual exclusion even on multicore architectures where multiple hardware threads are present.
    • -
-

Disadvantages

-
    -
  • Disabling interrupts for a long period of time can deteriorate the overall system response time and/or introduce jitter.
    • -
-

When use Locks

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    -
  • When mutual exclusion with interrupt handlers is required.
    • -
  • When the operation within the lock zone is very simple and has finite time.
    • -
-

Example

-
 ...
- chSysLock();
- /* Protected code */
- chSysUnlock();
- ...
-

Mutual exclusion by Semaphores

-

In ChibiOS/RT the counting semaphores are mainly meant as a synchronization mechanism between interrupt handlers and high level code running at thread level. Usually a thread waits on a semaphore that is signaled asynchronously by an interrupt handler.
- The semaphores can, however, be used as simple mutexes by initializing the semaphore counter to one.

-

Advantages

-
    -
  • The semaphores code is "already there" if you use the I/O queues or mailboxes and you don't want to enable the mutexes too in order to save space.
    • -
  • Semaphores are lighter than mutexes because their queues are FIFO ordered and do not have any overhead caused by the priority inheritance algorithm.
    • -
  • A semaphore takes less RAM than a mutex (12 vs 16 bytes on 32 bit architectures).
    • -
-

Disadvantages

-
    -
  • Semaphore queues are FIFO ordered by default, an option exist to make them priority ordered but this can impact I/O performance because semaphores are used in I/O queues.
    • -
  • Semaphores do not implement the Priority Inheritance algorithm.
    • -
-

When use Semaphores

-
    -
  • When you don't need queuing by priority nor the Priority Inheritance algorithm.
    • -
  • When RAM/ROM space is scarce.
    • -
-

Example

-
 static Semaphore sem; /* Semaphore declaration */
- ...
- chSemInit(&sem, 1); /* Semaphore initialization before use */
- ...
- chSemWait(&sem);
- /* Protected code */
- chSemSignal(&sem);
- ...
-

Mutual exclusion by Mutexes

-

The mutexes are the mechanism intended as the most general solution for Mutual Exclusion.

-

Advantages

-
    -
  • Mutexes implement the Priority Inheritance algorithm that is an important tool in reducing jitter and improve overall system response time (it is not a magic solution, just another tool for the system designer).
    • -
-

Disadvantages

-
    -
  • Heaviest among all the possible choices. The Priority Inheritance method is efficiently implemented but nothing is more efficient than no code at all.
    • -
-

When use Mutexes

-
    -
  • When you are designing a very complex system with hard realtime requirements.
    • -
-

Example

-
 static Mutex mtx; /* Mutex declaration */
- ...
- chMtxInit(&mtx); /* Mutex initialization before use */
- ...
- chMtxLock(&mtx);
- /* Protected code */
- chMtxUnlock();
- ...
-

Mutual exclusion by priority boost

-

Another way to implement mutual exclusion is to boost the thread priority to a level higher than all of the threads competing for a certain resource. This solution effectively implements an Immediate Priority Ceiling algorithm.

-

Advantages

-
    -
  • Almost free as code size, you need no semaphores nor mutexes.
    • -
  • No RAM overhead.
    • -
  • Fast execution, priority change is a quick operation under ChibiOS/RT.
    • -
  • The Priority Ceiling protocol can help mitigate potential Priority Inversion problems.
    • -
-

Disadvantages

-
    -
  • Makes the design more complicated because priorities must be assigned to not just threads but also assigned to the resources to be protected.
    • -
  • Locking a resource affects all the threads with lower priority even if not interested to the resource.
    • -
  • All the threads that can access the resource must have lower priority than the resource itself.
    • -
  • The mechanism is not easy to understand in the code unless it is clearly documented.
    • -
  • This method does not work in on multicore architectures where multiple hardware threads are present.
    • -
  • Only useful in very simple applications.
    • -
-

Example

-
 /* Priority assigned to the resource, threads must have lower
-    priority than this.*/
- #define AAA_RESOURCE_PRIORITY NORMALPRIO+10
- ...
- /* Locks the resources AAA.*/
- tprio_t aaa_old_prio = chThdSetPriority(AAA_RESOURCE_PRIORITY);
- /* Accessing resource AAA */
- chThdSetPriority(aaa_old_prio); /* Unlocks AAA.*/
- ...
-

Mutual exclusion by message passing

-

Another method is to make a single dedicated thread execute the critical code and make it work as a messages server. The other threads can request the service to the server by sending a properly formatted message and then wait for the answer with the result.
- This method is very useful when integrating into the system components not designed to be reentrant or to be executed in a multithreaded environment, as example a 3rd part file system or a networking protocol stack.

-

Advantages

-
    -
  • It is possible to encapsulate very complex logic without worry about about concurrent accesses.
    • -
  • If the encapsulate code uses a large stack area only the server thread have to allocate enough RAM, the client threads save RAM by just requesting the service to the server.
    • -
  • Clean system architecture.
    • -
  • This method also implements a form of Priority Ceiling. The ceiling is the priority of the server thread itself.
    • -
-

Disadvantages

-
    -
  • More complex implementation, a protocol must be created between clients and server.
    • -
  • Two context switches are required for each request to the server (but ChibiOSRT is very efficient at that).
    • -
  • Requires a dedicated thread as server.
    • -
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-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_portguide.html b/ChibiOS_2.0.8/docs/html/article_portguide.html deleted file mode 100644 index c0f348b..0000000 --- a/ChibiOS_2.0.8/docs/html/article_portguide.html +++ /dev/null @@ -1,95 +0,0 @@ - - -ChibiOS/RT: Porting ChibiOS/RT for Dummies - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Porting ChibiOS/RT for Dummies

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-
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Porting the operating system on a new platform is one of the most common tasks. The difficulty can range from easy to very difficult depending on several factors.
- We can divide in problem in several classes of progressively increasing difficulty:

- -

Another kind of port type is porting to another compiler and this is an added complexity level on the above classes. The kernel itself is portable but the port-specific code usually contains compiler specific extensions to the C language and the asm files syntax is almost never compatible.

-

-Porting the OS to a new board

-

This is the easiest port type, the scenario is that the specific microcontroller is already supported and a demo exists. This scenario also applies when porting the OS on a custom hardware using a supported microcontroller. This task can be easily performed with the following steps:

-
    -
  1. Create a new directory under ./boards and copy inside the board files from another board using the same microcontroller.
    2. -
  2. Customize the board files:
      -
    • board.h This file contains the I/O pins setup for the uC, it may also contain other board-dependent settings, as example, the clock frequency. Customize this file depending on your target hardware.
      • -
    • board.c This file contains the initialization code, it is possible you just need to customize board.h and not this file. If you have some hardware specific initialization code then put it here.
      • -
    -
    3. -
  3. Create a new directory under the ChibiOS/RT installation directory: ./projects/<my_app_name>
    4. -
  4. Copy an existing demo code under the newly created directory.
    5. -
  5. Customize the demo:
      -
    • Makefile You may edit this file in order to remove the test related sources and/or add you application source files.
      • -
    • main.c It contains the demo simple code, clean it and write your own main() function here, use this file just as a template.
      • -
    -
    6. -
  6. Compile your application and debug.
    7. -
-

-Porting the OS to a closely related microcontroller

-

In this scenario all the above steps are required but an analysis must be performed to evaluate the differences between from the supported micro and the target micro. Often the micros just differ for the memory area sizes and a change to the linker script is enough (the file is usually named ch.ld). Chips having more or less peripherals, everything else being the same or compatible are not a problem also as long the timer and the serial peripherals used by the port do not change.
- If there are differences in the internal peripherals, as example non compatible interrupt controllers (this happens in the LPC2000 family) or differences in UARTS, timers etc then the port falls in the following category.

-

-Porting the OS to another microcontroller using the same core

-

This kind of port is required when a target microcontroller has the same core (a common example: ARM7) of a supported microcontroller but has differences in the internal peripherals.
- If this is your case proceed as follow:

-
    -
  1. Create a new directory under ./os/io/platforms and name it with the microcontroller name (or family name).
    - In case of the ARM-based microcontroller you also need to create a equally named directory under ./os/ports/<compiler>/<arch> and put there the microcontroller related files such as the vectors table, see the existing ports as example.
    2. -
  2. Copy into the newly created directory the most closely related existing chip port or the naked template files from ./os/io/templates.
    3. -
  3. Work out the differences in the drivers or implement them if you started from the templates.
    4. -
  4. Edit/create the documentation file platform.dox, this is required if you want to regenerate this documentation including your work.
    5. -
-

Usually this kind of port just requires a serial driver (and those are very similar each other) and some code for the interrupt controller (this one can be part of the core port, as example the Cortex-M3 has this as standard part of the core).
- When the chip port is completed created your application as seen in the previous sections.

-

-Porting the OS to a whole new architecture

-

This is the hardest scenario, the time required by core ports depends strongly by the target architecture complexity and the level of support you need for the architecture specific features.
- As a reference, the MSP430 port took me 2 hours and it worked at the first run, it can be a reference for simple architectures, the ARM Cortex-M3 was painful instead, the architecture enforces you to implement things in a very specific way and I spent 2 week to go through all the documentation and figure out the correct way to implement the port (you can see that the preemption context switch is done in a very peculiar way because the exceptions architecture).
- One thing is sure, port an OS to a new architecture is not an easy task and if you have the required experience for such an effort then probably you don't need any advice from me. Just follow the directory patterns and fill the OS template files, the hardest part is decide the correct and efficient way to implement the context switching.

-
-
-Generated on Sun Nov 28 2010 14:09:55 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_roundrobin.html b/ChibiOS_2.0.8/docs/html/article_roundrobin.html deleted file mode 100644 index 5aaff2f..0000000 --- a/ChibiOS_2.0.8/docs/html/article_roundrobin.html +++ /dev/null @@ -1,55 +0,0 @@ - - -ChibiOS/RT: Round Robin scheduling explained - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Round Robin scheduling explained

-
-
-

Unlike many other RTOSes, ChibiOS/RT supports multiple threads at the same priority level and schedules them using an aggressive round-robin strategy.
- The strategy is defined as aggressive because any scheduling event causes the round-robin threads to rotate.
- A round-robin rotation can happen because of the following events:

-
    -
  • The currently executed thread voluntarily invokes the chThdYield() API in order to allow the execution of another thread at the same priority level, if any.
    • -
  • The currently executed thread voluntarily goes into a sleep state (see Threads States), when the thread is awakened it goes behind any other thread at the same priority level.
    • -
  • The currently executed thread is preempted by an higher priority thread, the thread is reinserted in the ready list (see Scheduling) behind any other thread at the same priority level.
    • -
  • If the CH_TIME_QUANTUM configuration constant is set to a value greater than zero and if the specified time quantum expired and if a thread with equal priority is ready then the currently executing thread is automatically reinserted in the ready list behind any other thread at the same priority level.
    • -
-

As you can see the CH_TIME_QUANTUM setting is really useful only if there are threads at the same priority level that can run not preempted for long periods of time and that do not explicitly yield using chThdYield(). Because of this you should consider setting CH_TIME_QUANTUM to zero in your configuration file, this makes the kernel much faster and smaller and does not forbid the use of multiple threads at the same priority level.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_saveram.html b/ChibiOS_2.0.8/docs/html/article_saveram.html deleted file mode 100644 index f257f5a..0000000 --- a/ChibiOS_2.0.8/docs/html/article_saveram.html +++ /dev/null @@ -1,90 +0,0 @@ - - -ChibiOS/RT: Saving RAM by declaring thread functions "noreturn" - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Saving RAM by declaring thread functions "noreturn"

-
-
-

One of the problems, when writing embedded multi-threaded applications, is that the thread functions do save the registers in the function entry code even if the system does not require it, exiting such a function would terminate the thread so there is no need to preserve the register values. This can waste tens of bytes for each thread.
- Consider the following code:

-
#include <ch.h>
-
-static WORKING_AREA(waMyThread, 64);
-
-static t_msg MyThread(void *arg) {
-  while (!chThdShoudTerminate()) {
-    /* Do thread inner work */
-  }
-  return 1;
-}
-
-main() {
-  chSysInit();
-  ...
-  chThdCreateStatic(waMyThread, sizeof(waMyThread), NORMALPRIO, MyThread, NULL);
-  ...
-}
-

The resulting ASM code for the thread function would be something like this:

-
MyThread:
-        stmfd   sp!, {r4, r5, r6, lr}
-        ...
-        ldmfd   sp!, {r4, r5, r6, pc}
-

Being that function a thread there is no need to save those registers, in embedded applications often the RAM is a scarce resource. That space can be saved by modifying the code as follow, using some advanced GCC extensions:

-
#include <ch.h>
-
-static WORKING_AREA(waMyThread, 64);
-
-__attribute__((noreturn))
-static void MyThread(void *arg) {
-  while (!chThdShoudTerminate()) {
-    /* Do thread inner work */
-  }
-  chThdExit(1);
-}
-
-main() {
-  chSysInit();
-  ...
-  chThdCreateStatic(waMyThread, sizeof(waMyThread), NORMALPRIO,
-                    (tfunc_t)MyThread, NULL);
-  ...
-}
-

This will make GCC believe that the function cannot return and there is no need to save registers. The code will be a bit less readable and less portable on other compilers however.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_stacks.html b/ChibiOS_2.0.8/docs/html/article_stacks.html deleted file mode 100644 index 1d5dfe3..0000000 --- a/ChibiOS_2.0.8/docs/html/article_stacks.html +++ /dev/null @@ -1,86 +0,0 @@ - - -ChibiOS/RT: Stacks and stack sizes - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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- - -
-
-

Stacks and stack sizes

-
-
-

In an RTOS like ChibiOS/RT there are several dedicated stacks, each stack has a dedicated RAM space that must have a correctly sized assigned area.

-

The stacks

-

There are several stacks in the systems, some are always present, some others are present only in some architectures:

-
    -
  • Main stack, this stack is used by the main() function and the thread that execute it. It is not a normal thread stack because it is initialized in the startup code and its size is defined in a port dependent way. Details are in the various ports documentation.
    • -
  • Interrupt Stack, some architectures have a dedicated interrupt stack. This is an important feature in a multithreaded environment, without a dedicated interrupt stack each thread has to reserve enough space, for interrupts servicing, within its own stack. This space, multiplied by the total threads number, can amount to a significant RAM overhead.
    • -
  • Thread Stack, each thread has a dedicated stack for its own execution and context switch.
    • -
  • Other Stacks, some architectures (ARM) can have other stacks but the OS does not directly use any of them.
    • -
-

Risks

-

The most critical thing when writing an embedded multithreaded application is to determine the correct stack size for main, threads and, when present, interrupts.
- Assigning too much space to a stack is a waste of RAM, assigning too little space leads to crashes or, worst scenario, hard to track instability.

-

Assigning the correct size

-

You may try to examine the asm listings in order to calculate the exact stack requirements but this requires much time, experience and patience.
- An alternative way is to use an interactive method. Follow this procedure for each thread in the system:

-
    -
  • Enable the following debug options in the kernel:
      -
    • CH_DBG_ENABLE_STACK_CHECK, this enables a stack check before any context switch. This option halts the system in chSysHalt() just before a stack overflow happens. The halt condition is caused by a stack overflow when the global variable panic_msg is set to NULL, normally it would point to a panic message.
      • -
    • CH_DBG_FILL_THREADS, this option fills the threads working area with an easily recognizable pattern (0x55).
      • -
    -
    • -
  • Assign a large and safe size to the thread stack, as example 256 bytes on 32 MCUs, 128 bytes on 8/16 bit MCUs. This is almost always too much for simple threads.
    • -
  • Run the application, if the application crashes or halts then increase the stack size and repeat (you know how to use the debugger right?).
    • -
  • Let the application run and make sure to trigger the thread in a way to make it follow most or all its code paths. If the application crashes or halts then increase the stack size and repeat.
    • -
  • Stop the application using the debugger and examine the thread working area (you know what a map file is, right?). You can see that the thread stack overwrote the fill pattern (0x55) from the top of the working area downward. You can estimate the excess stack by counting the untouched locations.
    • -
  • Trim down the stack size and repeat until the application still runs correctly and you have a decent margin in the stack.
    • -
  • Repeat for all the thread classes in the system.
    • -
  • Turn off the debug options.
    • -
  • Done.
    • -
-

Final Notes

-

Some useful info:

-
    -
  • Stack overflows are the most common problems source during development, when in trouble with crashes or anomalous behaviors always first verify stack sizes.
    • -
  • The required stack size can, and very often does change when changing compiler vendor, compiler version, compiler options, code type (ARM or THUMB as example).
    • -
  • Code compiled in THUMB mode uses more stack space compared to the same code compiled in ARM mode. In GCC this is related to lack of tail calls optimizations in THUMB mode, this is probably true also in other compilers.
    • -
  • Speed optimized code often requires less stack space compared to space optimized code. Be careful when changing optimizations.
    • -
  • The interrupts space overhead on the thread stacks (INT_REQUIRED_STACK defined in chcore.h) is included in the total working area size by the system macros THD_WA_SIZE() and WORKING_AREA().
    - The correct way to reserve space into the thread stacks for interrupts processing is to override the INT_REQUIRED_STACK default value. Architectures with a dedicated interrupt stack do not require changes to this value. Resizing of the global interrupt stack may be required instead.
    • -
  • Often is a good idea to have some extra space in stacks unless you are really starved on RAM. Anyway, it is best to optimize stack space at the very end of your development cycle.
    • -
-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_stop_os.html b/ChibiOS_2.0.8/docs/html/article_stop_os.html deleted file mode 100644 index ce94cec..0000000 --- a/ChibiOS_2.0.8/docs/html/article_stop_os.html +++ /dev/null @@ -1,132 +0,0 @@ - - -ChibiOS/RT: How to cleanly stop the OS - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

How to cleanly stop the OS

-
-
-

Stopping the OS should not be normally required but there are scenarios where one might want the complete control over the system again. As example entering into a bootload mode, or invoking some flashing algorithm locked in ROM.
- ChibiOS/RT does not have a shutdown API and there is a reason for this, stopping the kernel would not be enough, a well defined operations sequence is required.
- The shutdown operation should always be implemented into the main() function because in that context the stack pointer is guaranteed to be in the area allocated by the startup code. Stopping from a thread would leave the stack pointer "somewhere".
- The shutdown sequence should include the following steps, some steps are optional and depend on the application:

-
    -
  • Safely stop critical threads. As example a thread that uses a File System should flush all the modified buffers to the persistent storage before terminating.
    - The system should be designed to request the thread termination using chThdTerminate() and then wait its termination using chThdWait(). This phase can be skipped for non-critical threads.
    • -
  • Invoke the xxxStop() method on all the active device drivers, this disables the interrupt sources used by the various peripherals. This is required in order to not have interrupts after the shutdown that may invoke OS primitives.
    • -
  • Invoke chSysDisable().
    • -
  • Stop the system timer whose service routine invokes chSysTimerHandlerI().
    • -
  • Disable any other interrupt source that may invoke OS APIs. In general all the interrupt sources that have handlers declared by using the CH_IRQ_HANDLER() macro.
    • -
  • Perform any application related de-initialization.
    • -
  • Invoke chSysEnable().
    • -
-

Now the OS is stopped and you can safely assume there are nothing going on under the hood. From here you can also restart the OS after finishing your critical operations using the following sequence:

-
    -
  • Invoke chSysDisable().
    • -
  • Restart the system timer.
    • -
  • Reinitialize the OS by invoking chSysInit().
    • -
  • Restart your device drivers using the xxxStart() methods.
    • -
  • Restart all your threads.
    • -
-

Example

-

This is an example of an hypothetical application that have to shutdown the OS when a certain event is generated.

-
#include "ch.h"
-#include "hal.h"
-
-/* A shutdown flag.*/
-bool_t shutdown_required;
-
-/* Critical thread.*/
-static void my_thread(void *p) {
-
-  while (!chThdShouldTerminate()) {
-    /* Normal thread activity code.*/
-  }
-  /* Thread de-initialization before terminating, here you put the critical
-     thread finalization code.*/
-  return 0;
-}
-
-/* Main program, it is entered with interrupts disabled.*/
-void main(void) {
-
-  /* HAL initialization, you need to do this just once.*/
-  halInit();
-
-  /* Main loop, the main() function never exits.*/
-  while (TRUE) {
-    Thread *tp;
-
-    shutdown_required = FALSE;
-
-    /* ChibiOS/RT initialization. This function becomes an OS thread.*/
-    chSysInit();
-
-    /* Starting a device driver, SD2 in this case.*/
-    sdStart(&SD2, NULL);
-
-    /* Starting our critical thread.*/
-    tp = chThdCreateFromHeap(NULL, THD_WA_SIZE(256),
-                             NORMALPRIO, my_thread, &SD2);
-
-    /* Main thread activity into a loop.*/
-    while (!shutdown_required) {
-      /* Main activity, OS active until a shutdown becomes necessary.*/
-    }
-
-    /* Starting the shutdown sequence.*/
-    chThdTerminate(tp);     /* Requesting termination.                  */
-    chThdWait(tp);          /* Waiting for the actual termination.      */
-    sdStop(&SD2);           /* Stopping serial port 2.                  */
-    chSysDisable();
-    stop_system_timer();
-    stop_any_other_interrupt();
-    chSysEnable();
-
-    /* Now the main function is again a normal function, no more a
-       OS thread.*/
-    do_funny_stuff();
-
-    /* Restarting the OS but you could also stop the system or trigger a
-       reset instead.*/
-    chSysDisable();
-  }
-}
-

As you can see it is possible to jump in and out of the "OS mode" quite easily. Note that this is just an example, the real code could be very different depending on your requirements.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_timing.html b/ChibiOS_2.0.8/docs/html/article_timing.html deleted file mode 100644 index c60621a..0000000 --- a/ChibiOS_2.0.8/docs/html/article_timing.html +++ /dev/null @@ -1,91 +0,0 @@ - - -ChibiOS/RT: Reliable timings using Threads - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Reliable timings using Threads

-
-
-

One common task is to have threads do something at regular, scheduled, intervals. An obvious solution is to write something like this:

-
msg_t my_thread(void *param) {
-
-  while (TRUE) {
-    do_something();
-    chThdSleepMilliseconds(1000);   // Fixed interval
-  }
-}
-

This example works well assuming that the do_something() execution time is well below the system tick period and that my_thread() is not preempted by other threads that could insert long intervals.
- If the above conditions are not satisfied you may have do_something() executed at irregular intervals, as example:
-
- T0...T0+1000...T0+2002...T0+3002...T0+4005...etc.
-
- Also note that the error increases over time and this kind of behavior can lead to anomalies really hard to debug.

-

A better solution

-

It is possible to rewrite the above code using absolute deadlines rather than fixed intervals:

-
msg_t my_thread(void *param) {
-
-  systick_t time = chTimeNow();     // T0
-  while (TRUE) {
-    time += MS2ST(1000);            // Next deadline
-    do_something();
-    chThdSleepUntil(time);
-  }
-}
-

Using this code do_something() will always be executed at an absolute deadline time and the error will not accumulate over time regardless of the execution time and delays inserted by other threads.
- Note that this solution requires that the do_something() execution time must not exceed the deadline or the thread would stay sleeping into chThdSleepUntil().

-

A different way

-

Another way to perform activities at regular intervals is the use of a virtual timer. Virtual timers are able to generate callbacks at scheduled intervals. Virtual timers are one shot timers so you need to restart them from within the callback if you need a periodic timer like in this case.

-
VirtualTimer vt;
-
-void do_something(void *p) {
-
-  chVTSetI(&vt, MS2ST(1000), do_something, p);      // Restarts the timer.
-  // Periodic code here.
-}
-
-int main(int argc, char **argv) {
-
-  chSysLock();
-  chVTSetI(&vt, MS2ST(1000), do_something, NULL);   // Starts the timer.
-  chSysUnlock();
-  ...
-}
-

Note that the callback code is executed from within the I-Locked state (see System States) so you can only execute I-Class APIs from there (see API Names Suffixes).
- This solution has the advantage to not require a dedicated thread and thus uses much less RAM but the periodic code must have a very short execution time or it would degrade the overall system response time.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/article_wakeup.html b/ChibiOS_2.0.8/docs/html/article_wakeup.html deleted file mode 100644 index 892a1a8..0000000 --- a/ChibiOS_2.0.8/docs/html/article_wakeup.html +++ /dev/null @@ -1,142 +0,0 @@ - - -ChibiOS/RT: How to wake up a thread from an interrupt handler - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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- - -
-
-

How to wake up a thread from an interrupt handler

-
-
-

Waking up a thread after an hardware event is one of the most common tasks that an RTOS must be able to perform efficiently. In ChibiOS/RT there are several mechanisms that can be used, often each mechanism is best suited in a specific scenario.

-

Synchronously waking up a specific thread

-

A common situation is to have to synchronously wake up a specific thread. This can be accomplished without the use of any specific synchronization primitive, it uses the very efficient low level scheduler APIs, note that you can also optionally send a simple message from the IRQ handler to the thread.

-
static Thread *tp = NULL;
-
-void mythread(void *p) {
-
-  while (TRUE) {
-    msg_t msg;
-
-    // Waiting for the IRQ to happen.
-    chSysLock();
-    tp = chThdSelf();
-    chSchGoSleepS(PRSUSPENDED);
-    msg = chThdSelf()->p_rdymsg;    // Retrieving the message, optional
-    chSysUnlock();
-    // Perform processing here.
-  }
-}
-
-CH_IRQ_HANDLER(myIRQ) {
-  CH_IRQ_PROLOGUE();
-
-  // Wakes up the thread.
-  chSysLockFromIsr();
-  if (tp != NULL) {
-    tp->p_rdymsg = (msg_t)55;       // Sending the message, optional
-    chSchReadyI(tp);
-    tp = NULL;
-  }
-  chSysUnlockFromIsr().
-
-  CH_IRQ_EPILOGUE();
-}
-

Synchronously waking up one of the waiting threads

-

Lets assume you have a queue of waiting threads, you want to wake up the threads one by one in FIFO order, if there are no waiting threads then nothing happens.
- This can be accomplished using a Semaphore object initialized to zero:

-
CH_IRQ_HANDLER(myIRQ) {
-  CH_IRQ_PROLOGUE();
-
-  // If there is at least one waiting thread then signal it.
-  chSysLockFromIsr();
-  if (chSemGetCounterI(&mysem) < 0)
-    chSemSignalI(&mysem);
-  chSysUnlockFromIsr().
-
-  CH_IRQ_EPILOGUE();
-}
-

Synchronously waking up all the waiting threads

-

In this scenario you want to synchronously wake up all the waiting threads, if there are no waiting threads then nothing happens.
- This can be accomplished using a Semaphore object initialized to zero:

-
CH_IRQ_HANDLER(myIRQ) {
-  CH_IRQ_PROLOGUE();
-
-  // Wakes up all the threads waiting on the semaphore.
-  chSysLockFromIsr();
-  chSemResetI(&mysem);
-  chSysUnlockFromIsr().
-
-  CH_IRQ_EPILOGUE();
-}
-

Asynchronously waking up a specific thread

-

If you have to asynchronously wake up a specific thread then a simple event flags can be used.

-
static Thread *tp;
-
-void mythread(void *p) {
-
-  tp = chThdSelf();
-  while (TRUE) {
-    // Checks if an IRQ happened else wait.
-    chEvtWaitAny((eventmask_t)1);
-    // Perform processing here.
-  }
-}
-
-CH_IRQ_HANDLER(myIRQ) {
-  CH_IRQ_PROLOGUE();
-
-  // Wakes up the thread.
-  chSysLockFromIsr();
-  chEvtSignalI(tp, (eventmask_t)1);
-  chSysUnlockFromIsr().
-
-  CH_IRQ_EPILOGUE();
-}
-

Asynchronously waking up one or more threads

-

By using event sources it is possible to asynchronously wake up one or more listener threads. The mechanism requires a single initialized EventSource object, all the threads registered as listeners on the event source will be broadcasted.

-
CH_IRQ_HANDLER(myIRQ) {
-  CH_IRQ_PROLOGUE();
-
-  // Pends an event flag on all the listening threads.
-  chSysLockFromIsr();
-  chEvtBroadcastI(&my_event_source);
-  chSysUnlockFromIsr().
-
-  CH_IRQ_EPILOGUE();
-}
-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/articles.html b/ChibiOS_2.0.8/docs/html/articles.html deleted file mode 100644 index c4f8a89..0000000 --- a/ChibiOS_2.0.8/docs/html/articles.html +++ /dev/null @@ -1,49 +0,0 @@ - - -ChibiOS/RT: Articles and Code Samples - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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- - -
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Articles and Code Samples

-
-
-

ChibiOS/RT Articles and Code Samples:

- -
-
-Generated on Sun Nov 28 2010 14:09:53 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/at91sam7_8h_source.html b/ChibiOS_2.0.8/docs/html/at91sam7_8h_source.html deleted file mode 100644 index 82f0abe..0000000 --- a/ChibiOS_2.0.8/docs/html/at91sam7_8h_source.html +++ /dev/null @@ -1,107 +0,0 @@ - - -ChibiOS/RT: at91sam7.h Source File - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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- - -
-Generated on Sun Nov 28 2010 14:09:48 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/at91sam7__mii_8c.html b/ChibiOS_2.0.8/docs/html/at91sam7__mii_8c.html deleted file mode 100644 index 0155140..0000000 --- a/ChibiOS_2.0.8/docs/html/at91sam7__mii_8c.html +++ /dev/null @@ -1,70 +0,0 @@ - - -ChibiOS/RT: at91sam7_mii.c File Reference - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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- - -
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-Functions
-
-

at91sam7_mii.c File Reference

-
-
- -

AT91SAM7 low level MII driver code. -More...

-#include "ch.h"
-#include "hal.h"
-#include "at91sam7_mii.h"
- -

Go to the source code of this file.

- - - - - - - - - - -

-Functions

void miiInit (void)
 Low level MII driver initialization.
void miiReset (MACDriver *macp)
 Resets a PHY device.
phyreg_t miiGet (MACDriver *macp, phyaddr_t addr)
 Reads a PHY register through the MII interface.
void miiPut (MACDriver *macp, phyaddr_t addr, phyreg_t value)
 Writes a PHY register through the MII interface.
-

Detailed Description

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AT91SAM7 low level MII driver code.

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Definition in file at91sam7_mii.c.

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-Defines

#define PHY_HARDWARE   PHY_MICREL_KS8721
 PHY manufacturer and model.
#define PHY_ADDRESS   1
 Pins latched by the PHY at reset.

-Typedefs

typedef uint16_t phyreg_t
 Type of a PHY register value.
typedef uint8_t phyaddr_t
 Type of a PHY register address.

-Functions

void miiInit (void)
 Low level MII driver initialization.
void miiReset (MACDriver *macp)
 Resets a PHY device.
phyreg_t miiGet (MACDriver *macp, phyaddr_t addr)
 Reads a PHY register through the MII interface.
void miiPut (MACDriver *macp, phyaddr_t addr, phyreg_t value)
 Writes a PHY register through the MII interface.
-

Detailed Description

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AT91SAM7 low level MII driver header.

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Definition in file at91sam7_mii.h.

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CAN Driver code. -More...

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-Functions

void canInit (void)
 CAN Driver initialization.
void canObjectInit (CANDriver *canp)
 Initializes the standard part of a CANDriver structure.
void canStart (CANDriver *canp, const CANConfig *config)
 Configures and activates the CAN peripheral.
void canStop (CANDriver *canp)
 Deactivates the CAN peripheral.
msg_t canTransmit (CANDriver *canp, const CANTxFrame *ctfp, systime_t timeout)
 Can frame transmission.
msg_t canReceive (CANDriver *canp, CANRxFrame *crfp, systime_t timeout)
 Can frame receive.
canstatus_t canGetAndClearFlags (CANDriver *canp)
 Returns the current status mask and clears it.
void canSleep (CANDriver *canp)
 Enters the sleep mode.
void canWakeup (CANDriver *canp)
 Enforces leaving the sleep mode.
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CAN Driver code.

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Definition in file can.c.

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can.h File Reference

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-Defines

#define CAN_LIMIT_WARNING   1
 Errors rate warning.
#define CAN_LIMIT_ERROR   2
 Errors rate error.
#define CAN_BUS_OFF_ERROR   4
 Bus off condition reached.
#define CAN_FRAMING_ERROR   8
 Framing error of some kind on the CAN bus.
#define CAN_OVERFLOW_ERROR   16
 Overflow in receive queue.
#define CAN_USE_SLEEP_MODE   TRUE
 Sleep mode related APIs inclusion switch.
#define canAddFlagsI(canp, mask)   ((canp)->cd_status |= (mask))
 Adds some flags to the CAN status mask.

-Enumerations

enum  canstate_t {
-  CAN_UNINIT = 0, -CAN_STOP = 1, -CAN_STARTING = 2, -CAN_READY = 3, -
-  CAN_SLEEP = 4 -
- }
 

Driver state machine possible states.

- More...

-Functions

void canInit (void)
 CAN Driver initialization.
void canObjectInit (CANDriver *canp)
 Initializes the standard part of a CANDriver structure.
void canStart (CANDriver *canp, const CANConfig *config)
 Configures and activates the CAN peripheral.
void canStop (CANDriver *canp)
 Deactivates the CAN peripheral.
msg_t canTransmit (CANDriver *canp, const CANTxFrame *ctfp, systime_t timeout)
 Can frame transmission.
msg_t canReceive (CANDriver *canp, CANRxFrame *crfp, systime_t timeout)
 Can frame receive.
canstatus_t canGetAndClearFlags (CANDriver *canp)
 Returns the current status mask and clears it.
-

Detailed Description

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CAN Driver macros and structures.

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Definition in file can.h.

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-#include "chconf.h"
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-#include "chvt.h"
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-#include "chevents.h"
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#define _CHIBIOS_RT_
 ChibiOS/RT identification macro.
#define CH_KERNEL_VERSION   "2.0.8"
 Kernel version string.
#define CH_KERNEL_MAJOR   2
 Kernel version major number.
#define CH_KERNEL_MINOR   0
 Kernel version minor number.
#define CH_KERNEL_PATCH   8
 Kernel version patch number.
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ChibiOS/RT main include file.

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This header includes all the required kernel headers so it is the only kernel header you usually want to include in your application.

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Definition in file ch.h.

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class  chibios_rt::System
 Class encapsulating the base system functionalities. More...
class  chibios_rt::Timer
 Timer class. More...
class  chibios_rt::BaseThread
 Base class for a ChibiOS/RT thread. More...
class  chibios_rt::EnhancedThread< N >
 Enhanced threads template class. More...
class  chibios_rt::Semaphore
 Class encapsulating a semaphore. More...
class  chibios_rt::Mutex
 Class encapsulating a mutex. More...
class  chibios_rt::CondVar
 Class encapsulating a conditional variable. More...
class  chibios_rt::Event
 Class encapsulating an event source. More...
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void chCondInit (CondVar *cp)
 Initializes s CondVar structure.
void chCondSignal (CondVar *cp)
 Signals one thread that is waiting on the condition variable.
void chCondSignalI (CondVar *cp)
 Signals one thread that is waiting on the condition variable.
void chCondBroadcast (CondVar *cp)
 Signals all threads that are waiting on the condition variable.
void chCondBroadcastI (CondVar *cp)
 Signals all threads that are waiting on the condition variable.
msg_t chCondWait (CondVar *cp)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitS (CondVar *cp)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitTimeout (CondVar *cp, systime_t time)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitTimeoutS (CondVar *cp, systime_t time)
 Waits on the condition variable releasing the mutex lock.
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Condition Variables code.

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Definition in file chcond.c.

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struct  CondVar
 CondVar structure. More...

-Defines

#define _CONDVAR_DATA(name)   {_THREADSQUEUE_DATA(name.c_queue)}
 Data part of a static condition variable initializer.
#define CONDVAR_DECL(name)   CondVar name = _CONDVAR_DATA(name)
 Static condition variable initializer.

-Typedefs

typedef struct CondVar CondVar
 CondVar structure.

-Functions

void chCondInit (CondVar *cp)
 Initializes s CondVar structure.
void chCondSignal (CondVar *cp)
 Signals one thread that is waiting on the condition variable.
void chCondSignalI (CondVar *cp)
 Signals one thread that is waiting on the condition variable.
void chCondBroadcast (CondVar *cp)
 Signals all threads that are waiting on the condition variable.
void chCondBroadcastI (CondVar *cp)
 Signals all threads that are waiting on the condition variable.
msg_t chCondWait (CondVar *cp)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitS (CondVar *cp)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitTimeout (CondVar *cp, systime_t time)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitTimeoutS (CondVar *cp, systime_t time)
 Waits on the condition variable releasing the mutex lock.
-

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Condition Variables macros and structures.

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Definition in file chcond.h.

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-Defines

#define CH_FREQUENCY   1000
 System tick frequency.
#define CH_TIME_QUANTUM   20
 Round robin interval.
#define CH_USE_NESTED_LOCKS   FALSE
 Nested locks.
#define CH_MEMCORE_SIZE   0
 Managed RAM size.
#define CH_OPTIMIZE_SPEED   TRUE
 OS optimization.
#define CH_CURRP_REGISTER_CACHE   "reg"
 Exotic optimization.
#define CH_USE_REGISTRY   TRUE
 Threads registry APIs.
#define CH_USE_WAITEXIT   TRUE
 Threads synchronization APIs.
#define CH_USE_SEMAPHORES   TRUE
 Semaphores APIs.
#define CH_USE_SEMAPHORES_PRIORITY   FALSE
 Semaphores queuing mode.
#define CH_USE_SEMSW   TRUE
 Atomic semaphore API.
#define CH_USE_MUTEXES   TRUE
 Mutexes APIs.
#define CH_USE_CONDVARS   TRUE
 Conditional Variables APIs.
#define CH_USE_CONDVARS_TIMEOUT   TRUE
 Conditional Variables APIs with timeout.
#define CH_USE_EVENTS   TRUE
 Events Flags APIs.
#define CH_USE_EVENTS_TIMEOUT   TRUE
 Events Flags APIs with timeout.
#define CH_USE_MESSAGES   TRUE
 Synchronous Messages APIs.
#define CH_USE_MESSAGES_PRIORITY   FALSE
 Synchronous Messages queuing mode.
#define CH_USE_MAILBOXES   TRUE
 Mailboxes APIs.
#define CH_USE_QUEUES   TRUE
 I/O Queues APIs.
#define CH_USE_MEMCORE   TRUE
 Core Memory Manager APIs.
#define CH_USE_HEAP   TRUE
 Heap Allocator APIs.
#define CH_USE_MALLOC_HEAP   FALSE
 C-runtime allocator.
#define CH_USE_MEMPOOLS   TRUE
 Memory Pools Allocator APIs.
#define CH_USE_DYNAMIC   TRUE
 Dynamic Threads APIs.
#define CH_DBG_ENABLE_CHECKS   FALSE
 Debug option, parameters checks.
#define CH_DBG_ENABLE_ASSERTS   FALSE
 Debug option, consistency checks.
#define CH_DBG_ENABLE_TRACE   FALSE
 Debug option, trace buffer.
#define CH_DBG_ENABLE_STACK_CHECK   FALSE
 Debug option, stack checks.
#define CH_DBG_FILL_THREADS   FALSE
 Debug option, stacks initialization.
#define CH_DBG_THREADS_PROFILING   TRUE
 Debug option, threads profiling.
#define THREAD_EXT_FIELDS
 Threads descriptor structure hook.
#define THREAD_EXT_INIT(tp)
 Threads initialization hook.
#define THREAD_EXT_EXIT(tp)
 Threads finalization hook.
#define IDLE_LOOP_HOOK()
 Idle Loop hook.
-

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Configuration file template.

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A copy of this file must be placed in each project directory, it contains the application specific kernel settings.

- -

Definition in file chconf.h.

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chcore_v6m.c File Reference

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ARMv6-M architecture port code. -More...

-#include "ch.h"
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 CH_IRQ_HANDLER (SysTickVector)
 System Timer vector.
void _port_switch_from_irq (void)
 Post-IRQ switch code.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Start a thread by invoking its work function.

-Variables

regarm_t _port_saved_pc
 PC register temporary storage.
unsigned _port_irq_nesting
 IRQ nesting counter.
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Detailed Description

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ARMv6-M architecture port code.

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Definition in file chcore_v6m.c.

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-Data Structures

struct  cmxctx
 Cortex-Mx exception context. More...

-Defines

#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   8
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   16
 Per-thread stack overhead for interrupts servicing.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void id(void)
 IRQ handler function declaration.
#define PORT_FAST_IRQ_HANDLER(id)   void id(void)
 Fast IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   asm volatile ("cpsid i" : : : "memory")
 Kernel-lock action.
#define port_unlock()   asm volatile ("cpsie i" : : : "memory")
 Kernel-unlock action.
#define port_lock_from_isr()   port_lock()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()   port_unlock()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   asm volatile ("cpsid i" : : : "memory")
 Disables all the interrupt sources.
#define port_suspend()   asm volatile ("cpsid i" : : : "memory")
 Disables the interrupt sources below kernel-level priority.
#define port_enable()   asm volatile ("cpsie i" : : : "memory")
 Enables all the interrupt sources.
#define port_wait_for_interrupt()   asm volatile ("wfi" : : : "memory")
 Enters an architecture-dependent IRQ-waiting mode.

-Functions

void port_halt (void)
 Halts the system.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_switch_from_irq (void)
 Post-IRQ switch code.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

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ARMv6-M architecture port macros and structures.

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Definition in file chcore_v6m.h.

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chcore_v7m.c File Reference

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ARMv7-M architecture port code. -More...

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 CH_IRQ_HANDLER (SysTickVector)
 System Timer vector.
void SVCallVector (void)
 SVC vector.
void _port_irq_epilogue (void)
 Reschedule verification and setup after an IRQ.
void _port_switch_from_isr (void)
 Post-IRQ switch code.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

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ARMv7-M architecture port code.

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Definition in file chcore_v7m.c.

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-Defines

#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   8
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   16
 Per-thread stack overhead for interrupts servicing.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()   _port_irq_epilogue()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void id(void)
 IRQ handler function declaration.
#define PORT_FAST_IRQ_HANDLER(id)   void id(void)
 Fast IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()
 Kernel-lock action.
#define port_unlock()
 Kernel-unlock action.
#define port_lock_from_isr()   port_lock()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()   port_unlock()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   asm volatile ("cpsid i" : : : "memory")
 Disables all the interrupt sources.
#define port_suspend()
 Disables the interrupt sources below kernel-level priority.
#define port_enable()
 Enables all the interrupt sources.
#define port_wait_for_interrupt()
 Enters an architecture-dependent IRQ-waiting mode.

-Functions

void port_halt (void)
 Halts the system.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_irq_epilogue (void)
 Reschedule verification and setup after an IRQ.
void _port_switch_from_isr (void)
 Post-IRQ switch code.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

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ARMv7-M architecture port macros and structures.

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Definition in file chcore_v7m.h.

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chcoreasm.s File Reference

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ARM7 architecture port low level code. -More...

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ARM7 architecture port low level code.

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Definition in file chcoreasm.s.

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chdebug.c File Reference

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ChibiOS/RT Debug code. -More...

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void trace_init (void)
 Trace circular buffer subsystem initialization.
void chDbgTrace (Thread *otp)
 Inserts in the circular debug trace buffer a context switch record.
void chDbgPanic (char *msg)
 Prints a panic message on the console and then halts the system.

-Variables

TraceBuffer trace_buffer
 Public trace buffer.
char * panic_msg
 Pointer to the panic message.
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Detailed Description

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ChibiOS/RT Debug code.

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Definition in file chdebug.c.

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Debug macros and structures. -More...

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-Data Structures

struct  CtxSwcEvent
 Trace buffer record. More...
struct  TraceBuffer
 Trace buffer header. More...

-Defines

#define TRACE_BUFFER_SIZE   64
 Trace buffer entries.
#define STACK_FILL_VALUE   0x55
 Fill value for thread stack area in debug mode.
#define THREAD_FILL_VALUE   0xFF
 Fill value for thread area in debug mode.
#define chDbgCheck(c, func)
 Function parameter check.
#define chDbgAssert(c, m, r)
 Condition assertion.
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Detailed Description

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Debug macros and structures.

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Definition in file chdebug.h.

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chevents.c File Reference

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Events code. -More...

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-Functions

void chEvtRegisterMask (EventSource *esp, EventListener *elp, eventmask_t mask)
 Registers an Event Listener on an Event Source.
void chEvtUnregister (EventSource *esp, EventListener *elp)
 Unregisters an Event Listener from its Event Source.
eventmask_t chEvtClear (eventmask_t mask)
 Clears the pending events specified in the mask.
eventmask_t chEvtPend (eventmask_t mask)
 Pends a set of event flags on the current thread, this is much faster than using chEvtBroadcast() or chEvtSignal().
void chEvtSignal (Thread *tp, eventmask_t mask)
 Pends a set of event flags on the specified Thread.
void chEvtSignalI (Thread *tp, eventmask_t mask)
 Pends a set of event flags on the specified Thread.
void chEvtBroadcast (EventSource *esp)
 Signals all the Event Listeners registered on the specified Event Source.
void chEvtBroadcastI (EventSource *esp)
 Signals all the Event Listeners registered on the specified Event Source.
void chEvtDispatch (const evhandler_t *handlers, eventmask_t mask)
 Invokes the event handlers associated to an event flags mask.
eventmask_t chEvtWaitOne (eventmask_t mask)
 Waits for exactly one of the specified events.
eventmask_t chEvtWaitAny (eventmask_t mask)
 Waits for any of the specified events.
eventmask_t chEvtWaitAll (eventmask_t mask)
 Waits for all the specified events.
eventmask_t chEvtWaitOneTimeout (eventmask_t mask, systime_t time)
 Waits for exactly one of the specified events.
eventmask_t chEvtWaitAnyTimeout (eventmask_t mask, systime_t time)
 Waits for any of the specified events.
eventmask_t chEvtWaitAllTimeout (eventmask_t mask, systime_t time)
 Waits for all the specified events.
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Detailed Description

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Events code.

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Definition in file chevents.c.

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Events macros and structures. -More...

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-Data Structures

struct  EventListener
 Event Listener structure. More...
struct  EventSource
 Event Source structure. More...

-Defines

#define _EVENTSOURCE_DATA(name)   {(void *)(&name)}
 Data part of a static event source initializer.
#define EVENTSOURCE_DECL(name)   EventSource name = _EVENTSOURCE_DATA(name)
 Static event source initializer.
#define ALL_EVENTS   ((eventmask_t)-1)
#define EVENT_MASK(eid)   ((eventmask_t)(1 << (eid)))
#define chEvtRegister(esp, elp, eid)   chEvtRegisterMask(esp, elp, EVENT_MASK(eid))
 Registers an Event Listener on an Event Source.
#define chEvtInit(esp)   ((esp)->es_next = (EventListener *)(void *)(esp))
 Initializes an Event Source.
#define chEvtIsListening(esp)   ((void *)(esp) != (void *)(esp)->es_next)
 Verifies if there is at least one EventListener registered.

-Typedefs

typedef struct EventSource EventSource
 Event Source structure.
typedef void(* evhandler_t )(eventid_t)
 Event Handler callback function.

-Functions

void chEvtRegisterMask (EventSource *esp, EventListener *elp, eventmask_t mask)
 Registers an Event Listener on an Event Source.
void chEvtUnregister (EventSource *esp, EventListener *elp)
 Unregisters an Event Listener from its Event Source.
eventmask_t chEvtClear (eventmask_t mask)
 Clears the pending events specified in the mask.
eventmask_t chEvtPend (eventmask_t mask)
 Pends a set of event flags on the current thread, this is much faster than using chEvtBroadcast() or chEvtSignal().
void chEvtSignal (Thread *tp, eventmask_t mask)
 Pends a set of event flags on the specified Thread.
void chEvtSignalI (Thread *tp, eventmask_t mask)
 Pends a set of event flags on the specified Thread.
void chEvtBroadcast (EventSource *esp)
 Signals all the Event Listeners registered on the specified Event Source.
void chEvtBroadcastI (EventSource *esp)
 Signals all the Event Listeners registered on the specified Event Source.
void chEvtDispatch (const evhandler_t *handlers, eventmask_t mask)
 Invokes the event handlers associated to an event flags mask.
eventmask_t chEvtWaitOneTimeout (eventmask_t mask, systime_t time)
 Waits for exactly one of the specified events.
eventmask_t chEvtWaitAnyTimeout (eventmask_t mask, systime_t time)
 Waits for any of the specified events.
eventmask_t chEvtWaitAllTimeout (eventmask_t mask, systime_t time)
 Waits for all the specified events.
-

Detailed Description

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Events macros and structures.

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Definition in file chevents.h.

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Heaps code. -More...

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-Functions

void heap_init (void)
 Initializes the default heap.
void chHeapInit (MemoryHeap *heapp, void *buf, size_t size)
 Initializes a memory heap from a static memory area.
void * chHeapAlloc (MemoryHeap *heapp, size_t size)
 Allocates a block of memory from the heap by using the first-fit algorithm.
void chHeapFree (void *p)
 Frees a previously allocated memory block.
size_t chHeapStatus (MemoryHeap *heapp, size_t *sizep)
 Reports the heap status.
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Heaps code.

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Definition in file chheap.c.

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chheap.h File Reference

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Heaps macros and structures. -More...

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-Data Structures

union  heap_header
 Memory heap block header. More...
struct  memory_heap
 Structure describing a memory heap. More...

-Functions

void heap_init (void)
 Initializes the default heap.
void chHeapInit (MemoryHeap *heapp, void *buf, size_t size)
 Initializes a memory heap from a static memory area.
void * chHeapAlloc (MemoryHeap *heapp, size_t size)
 Allocates a block of memory from the heap by using the first-fit algorithm.
void chHeapFree (void *p)
 Frees a previously allocated memory block.
size_t chHeapStatus (MemoryHeap *heapp, size_t *sizep)
 Reports the heap status.
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Heaps macros and structures.

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Definition in file chheap.h.

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Kernel inlined functions.

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In this file there are a set of inlined functions if the CH_OPTIMIZE_SPEED is enabled.

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Definition in file chinline.h.

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chioch.h File Reference

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I/O channels. -More...

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-Data Structures

struct  BaseChannelVMT
 BaseChannel virtual methods table. More...
struct  BaseChannel
 Base channel class. More...
struct  BaseAsynchronousChannelVMT
 BaseAsynchronousChannel virtual methods table. More...
struct  BaseAsynchronousChannel
 Base asynchronous channel class. More...

-Defines

#define _base_channel_methods
 BaseChannel specific methods.
#define _base_channel_data   _base_sequential_stream_data
 BaseChannel specific data.
#define chIOPutWouldBlock(ip)   ((ip)->vmt->putwouldblock(ip))
 Channel output check.
#define chIOGetWouldBlock(ip)   ((ip)->vmt->getwouldblock(ip))
 Channel input check.
#define chIOPut(ip, b)   ((ip)->vmt->put(ip, b, TIME_INFINITE))
 Channel blocking byte write.
#define chIOPutTimeout(ip, b, time)   ((ip)->vmt->put(ip, b, time))
 Channel blocking byte write with timeout.
#define chIOGet(ip)   ((ip)->vmt->get(ip, TIME_INFINITE))
 Channel blocking byte read.
#define chIOGetTimeout(ip, time)   ((ip)->vmt->get(ip, time))
 Channel blocking byte read with timeout.
#define chIOWriteTimeout(ip, bp, n, time)   ((ip)->vmt->writet(ip, bp, n, time))
 Channel blocking write with timeout.
#define chIOReadTimeout(ip, bp, n, time)   ((ip)->vmt->readt(ip, bp, n, time))
 Channel blocking read with timeout.
#define _base_asynchronous_channel_methods   _base_channel_methods
 BaseAsynchronousChannel specific methods.
#define _base_asynchronous_channel_data
 BaseAsynchronousChannel specific data.
#define chIOGetWriteEventSource(ip)   (&((ip)->vmt->oevent))
 Returns the write event source.
#define chIOGetReadEventSource(ip)   (&((ip)->vmt->ievent))
 Returns the read event source.
-

Detailed Description

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I/O channels.

-

This header defines abstract interfaces useful to access generic I/O resources in a standardized way.

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Definition in file chioch.h.

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void prio_insert (Thread *tp, ThreadsQueue *tqp)
 Inserts a thread into a priority ordered queue.
void queue_insert (Thread *tp, ThreadsQueue *tqp)
 Inserts a Thread into a queue.
Thread * fifo_remove (ThreadsQueue *tqp)
 Removes the first-out Thread from a queue and returns it.
Thread * lifo_remove (ThreadsQueue *tqp)
 Removes the last-out Thread from a queue and returns it.
Thread * dequeue (Thread *tp)
 Removes a Thread from a queue and returns it.
void list_insert (Thread *tp, ThreadsList *tlp)
 Pushes a Thread on top of a stack list.
Thread * list_remove (ThreadsList *tlp)
 Pops a Thread from the top of a stack list and returns it.
-

Detailed Description

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Thread queues/lists code.

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Definition in file chlists.c.

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-Data Structures

struct  ThreadsQueue
 Generic threads bidirectional linked list header and element. More...
struct  ThreadsList
 Generic threads single link list, it works like a stack. More...

-Defines

#define queue_init(tqp)   ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp));
 Threads queue initialization.
#define list_init(tlp)   ((tlp)->p_next = (Thread *)(tlp))
 Threads list initialization.
#define isempty(p)   ((p)->p_next == (Thread *)(p))
 Evaluates to TRUE if the specified threads queue or list is empty.
#define notempty(p)   ((p)->p_next != (Thread *)(p))
 Evaluates to TRUE if the specified threads queue or list is not empty.
#define _THREADSQUEUE_DATA(name)   {(Thread *)&name, (Thread *)&name}
 Data part of a static threads queue initializer.
#define THREADSQUEUE_DECL(name)   ThreadsQueue name = _THREADSQUEUE_DATA(name)
 Static threads queue initializer.

-Functions

void prio_insert (Thread *tp, ThreadsQueue *tqp)
 Inserts a thread into a priority ordered queue.
void queue_insert (Thread *tp, ThreadsQueue *tqp)
 Inserts a Thread into a queue.
Thread * fifo_remove (ThreadsQueue *tqp)
 Removes the first-out Thread from a queue and returns it.
Thread * lifo_remove (ThreadsQueue *tqp)
 Removes the last-out Thread from a queue and returns it.
Thread * dequeue (Thread *tp)
 Removes a Thread from a queue and returns it.
void list_insert (Thread *tp, ThreadsList *tlp)
 Pushes a Thread on top of a stack list.
Thread * list_remove (ThreadsList *tlp)
 Pops a Thread from the top of a stack list and returns it.
-

Detailed Description

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Thread queues/lists macros and structures.

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Note:
All the macros present in this module, while public, are not an OS API and should not be directly used in the user applications code.
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Definition in file chlists.h.

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void chMBInit (Mailbox *mbp, msg_t *buf, cnt_t n)
 Initializes a Mailbox object.
void chMBReset (Mailbox *mbp)
 Resets a Mailbox object.
msg_t chMBPost (Mailbox *mbp, msg_t msg, systime_t time)
 Posts a message into a mailbox.
msg_t chMBPostS (Mailbox *mbp, msg_t msg, systime_t time)
 Posts a message into a mailbox.
msg_t chMBPostAhead (Mailbox *mbp, msg_t msg, systime_t time)
 Posts an high priority message into a mailbox.
msg_t chMBPostAheadS (Mailbox *mbp, msg_t msg, systime_t time)
 Posts an high priority message into a mailbox.
msg_t chMBFetch (Mailbox *mbp, msg_t *msgp, systime_t time)
 Retrieves a message from a mailbox.
msg_t chMBFetchS (Mailbox *mbp, msg_t *msgp, systime_t time)
 Retrieves a message from a mailbox.
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Detailed Description

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Mailboxes code.

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Definition in file chmboxes.c.

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#define chMBSize(mbp)   ((mbp)->mb_top - (mbp)->mb_buffer)
 Returns the mailbox buffer size.
#define chMBGetEmpty(mbp)   chSemGetCounterI(&(mbp)->mb_emptysem)
 Returns the free space into the mailbox.
#define chMBGetFull(mbp)   chSemGetCounterI(&(mbp)->mb_fullsem)
 Returns the number of messages into the mailbox.
#define chMBPeek(mbp)   (*(mbp)->mb_rdptr)
 Returns the next message in the queue without removing it.
#define _MAILBOX_DATA(name, buffer, size)
 Data part of a static mailbox initializer.
#define MAILBOX_DECL(name, buffer, size)   Mailbox name = _MAILBOX_DATA(name, buffer, size)
 Static mailbox initializer.

-Functions

void chMBInit (Mailbox *mbp, msg_t *buf, cnt_t n)
 Initializes a Mailbox object.
void chMBReset (Mailbox *mbp)
 Resets a Mailbox object.
msg_t chMBPost (Mailbox *mbp, msg_t msg, systime_t time)
 Posts a message into a mailbox.
msg_t chMBPostS (Mailbox *mbp, msg_t msg, systime_t time)
 Posts a message into a mailbox.
msg_t chMBPostAhead (Mailbox *mbp, msg_t msg, systime_t time)
 Posts an high priority message into a mailbox.
msg_t chMBPostAheadS (Mailbox *mbp, msg_t msg, systime_t time)
 Posts an high priority message into a mailbox.
msg_t chMBFetch (Mailbox *mbp, msg_t *msgp, systime_t time)
 Retrieves a message from a mailbox.
msg_t chMBFetchS (Mailbox *mbp, msg_t *msgp, systime_t time)
 Retrieves a message from a mailbox.
-

Detailed Description

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Mailboxes macros and structures.

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Definition in file chmboxes.h.

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Core memory manager code. -More...

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void core_init (void)
 Low level memory manager initialization.
void * chCoreAlloc (size_t size)
 Allocates a memory block.
void * chCoreAllocI (size_t size)
 Allocates a memory block.
size_t chCoreStatus (void)
 Core memory status.
-

Detailed Description

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Core memory manager code.

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Definition in file chmemcore.c.

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-Defines

#define MEM_ALIGN_MASK   (sizeof(stkalign_t) - 1)
 Alignment mask constant.
#define MEM_ALIGN_SIZE(p)   (((size_t)(p) + MEM_ALIGN_MASK) & ~MEM_ALIGN_MASK)
 Alignment helper macro.
#define MEM_IS_ALIGNED(p)   (((size_t)(p) & MEM_ALIGN_MASK) == 0)
 Returns whatever a pointer or memory size is aligned to the type align_t.

-Typedefs

typedef void *(* memgetfunc_t )(size_t size)
 Memory get function.

-Functions

void core_init (void)
 Low level memory manager initialization.
void * chCoreAlloc (size_t size)
 Allocates a memory block.
void * chCoreAllocI (size_t size)
 Allocates a memory block.
size_t chCoreStatus (void)
 Core memory status.
-

Detailed Description

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Core memory manager macros and structures.

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Definition in file chmemcore.h.

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void chPoolInit (MemoryPool *mp, size_t size, memgetfunc_t provider)
 Initializes an empty memory pool.
void * chPoolAllocI (MemoryPool *mp)
 Allocates an object from a memory pool.
void * chPoolAlloc (MemoryPool *mp)
 Allocates an object from a memory pool.
void chPoolFreeI (MemoryPool *mp, void *objp)
 Releases (or adds) an object into (to) a memory pool.
void chPoolFree (MemoryPool *mp, void *objp)
 Releases (or adds) an object into (to) a memory pool.
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Memory Pools code.

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Definition in file chmempools.c.

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struct  pool_header
 Memory pool free object header. More...
struct  MemoryPool
 Memory pool descriptor. More...

-Defines

#define _MEMORYPOOL_DATA(name, size, provider)   {NULL, MEM_ALIGN_SIZE(size), provider}
 Data part of a static memory pool initializer.
#define MEMORYPOOL_DECL(name, size, provider)   MemoryPool name = _MEMORYPOOL_DATA(name, size, provider)
 Static memory pool initializer in hungry mode.

-Functions

void chPoolInit (MemoryPool *mp, size_t size, memgetfunc_t provider)
 Initializes an empty memory pool.
void * chPoolAllocI (MemoryPool *mp)
 Allocates an object from a memory pool.
void * chPoolAlloc (MemoryPool *mp)
 Allocates an object from a memory pool.
void chPoolFreeI (MemoryPool *mp, void *objp)
 Releases (or adds) an object into (to) a memory pool.
void chPoolFree (MemoryPool *mp, void *objp)
 Releases (or adds) an object into (to) a memory pool.
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Detailed Description

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Memory Pools macros and structures.

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Definition in file chmempools.h.

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msg_t chMsgSend (Thread *tp, msg_t msg)
 Sends a message to the specified thread.
msg_t chMsgWait (void)
 Suspends the thread and waits for an incoming message.
msg_t chMsgGet (void)
 Returns the next message in the queue.
void chMsgRelease (msg_t msg)
 Releases the thread waiting on top of the messages queue.
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Messages code.

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Definition in file chmsg.c.

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#define chMsgIsPendingI(tp)   ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue)
 Evaluates to TRUE if the thread has pending messages.
#define chMsgGetI(tp)   ((tp)->p_msgqueue.p_next->p_msg)
 Returns the first message in the queue.

-Functions

msg_t chMsgSend (Thread *tp, msg_t msg)
 Sends a message to the specified thread.
msg_t chMsgWait (void)
 Suspends the thread and waits for an incoming message.
msg_t chMsgGet (void)
 Returns the next message in the queue.
void chMsgRelease (msg_t msg)
 Releases the thread waiting on top of the messages queue.
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Detailed Description

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Messages macros and structures.

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Definition in file chmsg.h.

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chmtx.c File Reference

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void chMtxInit (Mutex *mp)
 Initializes s Mutex structure.
void chMtxLock (Mutex *mp)
 Locks the specified mutex.
void chMtxLockS (Mutex *mp)
 Locks the specified mutex.
bool_t chMtxTryLock (Mutex *mp)
 Tries to lock a mutex.
bool_t chMtxTryLockS (Mutex *mp)
 Tries to lock a mutex.
Mutex * chMtxUnlock (void)
 Unlocks the next owned mutex in reverse lock order.
Mutex * chMtxUnlockS (void)
 Unlocks the next owned mutex in reverse lock order.
void chMtxUnlockAll (void)
 Unlocks all the mutexes owned by the invoking thread.
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Mutexes code.

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Definition in file chmtx.c.

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struct  Mutex
 Mutex structure. More...

-Defines

#define _MUTEX_DATA(name)   {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL}
 Data part of a static mutex initializer.
#define MUTEX_DECL(name)   Mutex name = _MUTEX_DATA(name)
 Static mutex initializer.
#define chMtxQueueNotEmptyS(mp)   notempty(&(mp)->m_queue)
 Returns TRUE if the mutex queue contains at least a waiting thread.

-Typedefs

typedef struct Mutex Mutex
 Mutex structure.

-Functions

void chMtxInit (Mutex *mp)
 Initializes s Mutex structure.
void chMtxLock (Mutex *mp)
 Locks the specified mutex.
void chMtxLockS (Mutex *mp)
 Locks the specified mutex.
bool_t chMtxTryLock (Mutex *mp)
 Tries to lock a mutex.
bool_t chMtxTryLockS (Mutex *mp)
 Tries to lock a mutex.
Mutex * chMtxUnlock (void)
 Unlocks the next owned mutex in reverse lock order.
Mutex * chMtxUnlockS (void)
 Unlocks the next owned mutex in reverse lock order.
void chMtxUnlockAll (void)
 Unlocks all the mutexes owned by the invoking thread.
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Mutexes macros and structures.

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Definition in file chmtx.h.

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void chIQInit (InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy)
 Initializes an input queue.
void chIQResetI (InputQueue *iqp)
 Resets an input queue.
msg_t chIQPutI (InputQueue *iqp, uint8_t b)
 Input queue write.
msg_t chIQGetTimeout (InputQueue *iqp, systime_t time)
 Input queue read with timeout.
size_t chIQReadTimeout (InputQueue *iqp, uint8_t *bp, size_t n, systime_t time)
 Input queue read with timeout.
void chOQInit (OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy)
 Initializes an output queue.
void chOQResetI (OutputQueue *oqp)
 Resets an output queue.
msg_t chOQPutTimeout (OutputQueue *oqp, uint8_t b, systime_t time)
 Output queue write with timeout.
msg_t chOQGetI (OutputQueue *oqp)
 Output queue read.
size_t chOQWriteTimeout (OutputQueue *oqp, const uint8_t *bp, size_t n, systime_t time)
 Output queue write with timeout.
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Detailed Description

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I/O Queues code.

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Definition in file chqueues.c.

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-Data Structures

struct  GenericQueue
 Generic I/O queue structure. More...

-Defines

#define Q_OK   RDY_OK
 Returned by the queue functions if the operation is successful.
#define Q_TIMEOUT   RDY_TIMEOUT
 Returned by the queue functions if a timeout occurs.
#define Q_RESET   RDY_RESET
 Returned by the queue functions if the queue is reset.
#define Q_EMPTY   -3
 Returned by the queue functions if the queue is empty.
#define Q_FULL   -4
 Returned by the queue functions if the queue is full.
#define chQSize(q)   ((q)->q_top - (q)->q_buffer)
 Returns the queue's buffer size.
#define chQSpace(q)   chSemGetCounterI(&(q)->q_sem)
 Queue space.
#define chIQIsEmpty(q)   ((bool_t)(chQSpace(q) <= 0))
 Evaluates to TRUE if the specified Input Queue is empty.
#define chIQIsFull(q)   ((bool_t)(chQSpace(q) >= chQSize(q)))
 Evaluates to TRUE if the specified Input Queue is full.
#define chIQGet(iqp)   chIQGetTimeout(iqp, TIME_INFINITE)
 Input queue read.
#define _INPUTQUEUE_DATA(name, buffer, size, inotify)
 Data part of a static input queue initializer.
#define INPUTQUEUE_DECL(name, buffer, size, inotify)   InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify)
 Static input queue initializer.
#define chOQIsEmpty(q)   ((bool_t)(chQSpace(q) >= chQSize(q)))
 Evaluates to TRUE if the specified Output Queue is empty.
#define chOQIsFull(q)   ((bool_t)(chQSpace(q) <= 0))
 Evaluates to TRUE if the specified Output Queue is full.
#define chOQPut(oqp, b)   chOQPutTimeout(oqp, b, TIME_INFINITE)
 Output queue write.
#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify)
 Data part of a static output queue initializer.
#define OUTPUTQUEUE_DECL(name, buffer, size, onotify)   InputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify)
 Static output queue initializer.

-Typedefs

typedef void(* qnotify_t )(void)
 Queue notification callback type.
typedef GenericQueue InputQueue
 Input queue structure.
typedef GenericQueue OutputQueue
 Output queue structure.

-Functions

void chIQInit (InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy)
 Initializes an input queue.
void chIQResetI (InputQueue *iqp)
 Resets an input queue.
msg_t chIQPutI (InputQueue *iqp, uint8_t b)
 Input queue write.
msg_t chIQGetTimeout (InputQueue *iqp, systime_t time)
 Input queue read with timeout.
size_t chIQReadTimeout (InputQueue *iqp, uint8_t *bp, size_t n, systime_t time)
 Input queue read with timeout.
void chOQInit (OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy)
 Initializes an output queue.
void chOQResetI (OutputQueue *oqp)
 Resets an output queue.
msg_t chOQPutTimeout (OutputQueue *oqp, uint8_t b, systime_t time)
 Output queue write with timeout.
msg_t chOQGetI (OutputQueue *oqp)
 Output queue read.
size_t chOQWriteTimeout (OutputQueue *oqp, const uint8_t *bp, size_t n, systime_t time)
 Output queue write with timeout.
-

Detailed Description

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Queues macros and structures.

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I/O

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Definition in file chqueues.h.

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chregistry.c File Reference

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Threads registry code. -More...

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Thread * chRegFirstThread (void)
 Returns the first thread in the system.
Thread * chRegNextThread (Thread *tp)
 Returns the thread next to the specified one.
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Detailed Description

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Threads registry code.

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Definition in file chregistry.c.

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-Defines

#define REG_REMOVE(tp)
 Removes a thread from the registry list.
#define REG_INSERT(tp)
 Adds a thread to the registry list.

-Functions

Thread * chRegFirstThread (void)
 Returns the first thread in the system.
Thread * chRegNextThread (Thread *tp)
 Returns the thread next to the specified one.
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Detailed Description

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Threads registry macros and structures.

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Definition in file chregistry.h.

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Scheduler code. -More...

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-Functions

void scheduler_init (void)
 Scheduler initialization.
Thread * chSchReadyI (Thread *tp)
 Inserts a thread in the Ready List.
void chSchGoSleepS (tstate_t newstate)
 Puts the current thread to sleep into the specified state.
msg_t chSchGoSleepTimeoutS (tstate_t newstate, systime_t time)
 Puts the current thread to sleep into the specified state with timeout specification.
void chSchWakeupS (Thread *ntp, msg_t msg)
 Wakes up a thread.
void chSchDoRescheduleI (void)
 Switches to the first thread on the runnable queue.
void chSchRescheduleS (void)
 Performs a reschedule if a higher priority thread is runnable.
bool_t chSchIsRescRequiredExI (void)
 Evaluates if a reschedule is required.

-Variables

ReadyList rlist
 Ready list header.
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Detailed Description

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Scheduler code.

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Definition in file chschd.c.

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-Data Structures

struct  ReadyList
 Ready list header. More...

-Defines

#define RDY_OK   0
 Default thread wakeup low level message.
#define RDY_TIMEOUT   -1
 Low level message sent to a thread awakened by a timeout.
#define RDY_RESET   -2
 Low level message sent to a thread awakened by a reset operation.
#define NOPRIO   0
 Ready list header priority.
#define IDLEPRIO   1
 Idle thread priority.
#define LOWPRIO   2
 Lowest user priority.
#define NORMALPRIO   64
 Normal user priority.
#define HIGHPRIO   127
 Highest user priority.
#define ABSPRIO   255
 Greatest possible priority.
#define TIME_IMMEDIATE   ((systime_t)-1)
 Zero time specification for some syscalls with a timeout specification.
#define TIME_INFINITE   ((systime_t)0)
 Infinite time specification for all the syscalls with a timeout specification.
#define firstprio(rlp)   ((rlp)->p_next->p_prio)
 Returns the priority of the first thread on the given ready list.
#define currp   rlist.r_current
 Current thread pointer access macro.
#define setcurrp(tp)   (currp = (tp))
 Current thread pointer change macro.
#define chSchIsRescRequiredI()   (firstprio(&rlist.r_queue) > currp->p_prio)
 Determines if the current thread must reschedule.
#define chSchCanYieldS()   (firstprio(&rlist.r_queue) >= currp->p_prio)
 Determines if yielding is possible.
#define chSchDoYieldS()
 Yields the time slot.

-Functions

void scheduler_init (void)
 Scheduler initialization.
Thread * chSchReadyI (Thread *tp)
 Inserts a thread in the Ready List.
void chSchGoSleepS (tstate_t newstate)
 Puts the current thread to sleep into the specified state.
msg_t chSchGoSleepTimeoutS (tstate_t newstate, systime_t time)
 Puts the current thread to sleep into the specified state with timeout specification.
void chSchWakeupS (Thread *ntp, msg_t msg)
 Wakes up a thread.
void chSchDoRescheduleI (void)
 Switches to the first thread on the runnable queue.
void chSchRescheduleS (void)
 Performs a reschedule if a higher priority thread is runnable.
bool_t chSchIsRescRequiredExI (void)
 Evaluates if a reschedule is required.
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Scheduler macros and structures.

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Definition in file chschd.h.

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void chSemInit (Semaphore *sp, cnt_t n)
 Initializes a semaphore with the specified counter value.
void chSemReset (Semaphore *sp, cnt_t n)
 Performs a reset operation on the semaphore.
void chSemResetI (Semaphore *sp, cnt_t n)
 Performs a reset operation on the semaphore.
msg_t chSemWait (Semaphore *sp)
 Performs a wait operation on a semaphore.
msg_t chSemWaitS (Semaphore *sp)
 Performs a wait operation on a semaphore.
msg_t chSemWaitTimeout (Semaphore *sp, systime_t time)
 Performs a wait operation on a semaphore with timeout specification.
msg_t chSemWaitTimeoutS (Semaphore *sp, systime_t time)
 Performs a wait operation on a semaphore with timeout specification.
void chSemSignal (Semaphore *sp)
 Performs a signal operation on a semaphore.
void chSemSignalI (Semaphore *sp)
 Performs a signal operation on a semaphore.
msg_t chSemSignalWait (Semaphore *sps, Semaphore *spw)
 Performs atomic signal and wait operations on two semaphores.
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Semaphores code.

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Definition in file chsem.c.

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struct  Semaphore
 Semaphore structure. More...

-Defines

#define _SEMAPHORE_DATA(name, n)   {_THREADSQUEUE_DATA(name.s_queue), n}
 Data part of a static semaphore initializer.
#define SEMAPHORE_DECL(name, n)   Semaphore name = _SEMAPHORE_DATA(name, n)
 Static semaphore initializer.
#define chSemFastWaitI(sp)   ((sp)->s_cnt--)
 Decreases the semaphore counter.
#define chSemFastSignalI(sp)   ((sp)->s_cnt++)
 Increases the semaphore counter.
#define chSemGetCounterI(sp)   ((sp)->s_cnt)
 Returns the semaphore counter current value.

-Typedefs

typedef struct Semaphore Semaphore
 Semaphore structure.

-Functions

void chSemInit (Semaphore *sp, cnt_t n)
 Initializes a semaphore with the specified counter value.
void chSemReset (Semaphore *sp, cnt_t n)
 Performs a reset operation on the semaphore.
void chSemResetI (Semaphore *sp, cnt_t n)
 Performs a reset operation on the semaphore.
msg_t chSemWait (Semaphore *sp)
 Performs a wait operation on a semaphore.
msg_t chSemWaitS (Semaphore *sp)
 Performs a wait operation on a semaphore.
msg_t chSemWaitTimeout (Semaphore *sp, systime_t time)
 Performs a wait operation on a semaphore with timeout specification.
msg_t chSemWaitTimeoutS (Semaphore *sp, systime_t time)
 Performs a wait operation on a semaphore with timeout specification.
void chSemSignal (Semaphore *sp)
 Performs a signal operation on a semaphore.
void chSemSignalI (Semaphore *sp)
 Performs a signal operation on a semaphore.
msg_t chSemSignalWait (Semaphore *sps, Semaphore *spw)
 Performs atomic signal and wait operations on two semaphores.
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chstreams.h File Reference

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struct  BaseSequentialStreamVMT
 BaseSequentialStream virtual methods table. More...
struct  BaseSequentialStream
 Base stream class. More...

-Defines

#define _base_sequential_stream_methods
 BaseSequentialStream specific methods.
#define _base_sequential_stream_data
 BaseSequentialStream specific data.
#define chSequentialStreamWrite(ip, bp, n)   ((ip)->vmt->write(ip, bp, n))
 Sequential Stream write.
#define chSequentialStreamRead(ip, bp, n)   ((ip)->vmt->read(ip, bp, n))
 Sequential Stream read.
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Data streams.

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This header defines abstract interfaces useful to access generic data streams in a standardized way.

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void chSysInit (void)
 ChibiOS/RT initialization.
void chSysTimerHandlerI (void)
 Handles time ticks for round robin preemption and timer increments.
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System related code.

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Definition in file chsys.c.

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#define chSysHalt()   port_halt()
 Halts the system.
#define chSysSwitchI(ntp, otp)   port_switch(ntp, otp)
 Performs a context switch.
#define chSysDisable()   port_disable()
 Raises the system interrupt priority mask to the maximum level.
#define chSysSuspend()   port_suspend()
 Raises the system interrupt priority mask to system level.
#define chSysEnable()   port_enable()
 Lowers the system interrupt priority mask to user level.
#define chSysLock()
 Enters the kernel lock mode.
#define chSysUnlock()
 Leaves the kernel lock mode.
#define chSysLockFromIsr()   port_lock_from_isr()
 Enters the kernel lock mode from within an interrupt handler.
#define chSysUnlockFromIsr()   port_unlock_from_isr()
 Leaves the kernel lock mode from within an interrupt handler.
#define CH_IRQ_PROLOGUE()   PORT_IRQ_PROLOGUE()
 IRQ handler enter code.
#define CH_IRQ_EPILOGUE()   PORT_IRQ_EPILOGUE()
 IRQ handler exit code.
#define CH_IRQ_HANDLER(id)   PORT_IRQ_HANDLER(id)
 Standard normal IRQ handler declaration.
#define CH_FAST_IRQ_HANDLER(id)   PORT_FAST_IRQ_HANDLER(id)
 Standard fast IRQ handler declaration.

-Functions

void chSysInit (void)
 ChibiOS/RT initialization.
void chSysTimerHandlerI (void)
 Handles time ticks for round robin preemption and timer increments.
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System related macros and structures.

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Definition in file chsys.h.

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Thread * init_thread (Thread *tp, tprio_t prio)
 Initializes a thread structure.
Thread * chThdCreateI (void *wsp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread into a static memory area.
Thread * chThdCreateStatic (void *wsp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread into a static memory area.
Thread * chThdCreateFromHeap (MemoryHeap *heapp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread allocating the memory from the heap.
Thread * chThdCreateFromMemoryPool (MemoryPool *mp, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread allocating the memory from the specified memory pool.
tprio_t chThdSetPriority (tprio_t newprio)
 Changes the running thread priority level then reschedules if necessary.
Thread * chThdResume (Thread *tp)
 Resumes a suspended thread.
void chThdTerminate (Thread *tp)
 Requests a thread termination.
void chThdSleep (systime_t time)
 Suspends the invoking thread for the specified time.
void chThdSleepUntil (systime_t time)
 Suspends the invoking thread until the system time arrives to the specified value.
void chThdYield (void)
 Yields the time slot.
void chThdExit (msg_t msg)
 Terminates the current thread by specifying an exit status code.
Thread * chThdAddRef (Thread *tp)
 Adds a reference to a thread object.
void chThdRelease (Thread *tp)
 Releases a reference to a thread object.
msg_t chThdWait (Thread *tp)
 Blocks the execution of the invoking thread until the specified thread terminates then the exit code is returned.
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Threads code.

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Definition in file chthreads.c.

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chthreads.h File Reference

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Threads macros and structures. -More...

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Go to the source code of this file.

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-Data Structures

struct  Thread
 Structure representing a thread. More...

-Defines

#define THD_STATE_READY   0
 Thread state: Ready to run, waiting on the ready list.
#define THD_STATE_CURRENT   1
 Thread state: Currently running.
#define THD_STATE_SUSPENDED   2
 Thread state: Thread created in suspended state.
#define THD_STATE_WTSEM   3
 Thread state: Waiting on a semaphore.
#define THD_STATE_WTMTX   4
 Thread state: Waiting on a mutex.
#define THD_STATE_WTCOND   5
 Thread state: Waiting in chCondWait().
#define THD_STATE_SLEEPING   6
 Thread state: Waiting in chThdSleep() or chThdSleepUntil().
#define THD_STATE_WTEXIT   7
 Thread state: Waiting in chThdWait().
#define THD_STATE_WTOREVT   8
 Thread state: Waiting in chEvtWaitXXX().
#define THD_STATE_WTANDEVT   9
 Thread state: Waiting in chEvtWaitAllTimeout().
#define THD_STATE_SNDMSG   10
 Thread state: Waiting in chMsgSend().
#define THD_STATE_WTMSG   11
 Thread state: Waiting in chMsgWait().
#define THD_STATE_FINAL   12
 Thread state: After termination.
#define THD_MEM_MODE_MASK   3
 Thread memory mode mask.
#define THD_MEM_MODE_STATIC   0
 Thread memory mode: static.
#define THD_MEM_MODE_HEAP   1
 Thread memory mode: heap.
#define THD_MEM_MODE_MEMPOOL   2
 Thread memory mode: pool.
#define THD_TERMINATE   4
 Termination requested.
#define chThdSelf()   currp
 Returns a pointer to the current Thread.
#define chThdGetPriority()   (currp->p_prio)
 Returns the current thread priority.
#define chThdLS()   (void *)(currp + 1)
 Returns the pointer to the Thread local storage area, if any.
#define chThdTerminated(tp)   ((tp)->p_state == THD_STATE_FINAL)
 Verifies if the specified thread is in the THD_STATE_FINAL state.
#define chThdShouldTerminate()   (currp->p_flags & THD_TERMINATE)
 Verifies if the current thread has a termination request pending.
#define chThdResumeI(tp)   chSchReadyI(tp)
 Resumes a thread created with chThdInit().
#define chThdSleepS(time)   chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time)
 Suspends the invoking thread for the specified time.
#define chThdSleepSeconds(sec)   chThdSleep(S2ST(sec))
 Delays the invoking thread for the specified number of seconds.
#define chThdSleepMilliseconds(msec)   chThdSleep(MS2ST(msec))
 Delays the invoking thread for the specified number of milliseconds.
#define chThdSleepMicroseconds(usec)   chThdSleep(US2ST(usec))
 Delays the invoking thread for the specified number of microseconds.

-Typedefs

typedef msg_t(* tfunc_t )(void *)
 Thread function.

-Functions

Thread * init_thread (Thread *tp, tprio_t prio)
 Initializes a thread structure.
Thread * chThdCreateI (void *wsp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread into a static memory area.
Thread * chThdCreateStatic (void *wsp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread into a static memory area.
Thread * chThdCreateFromHeap (MemoryHeap *heapp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread allocating the memory from the heap.
Thread * chThdCreateFromMemoryPool (MemoryPool *mp, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread allocating the memory from the specified memory pool.
tprio_t chThdSetPriority (tprio_t newprio)
 Changes the running thread priority level then reschedules if necessary.
Thread * chThdResume (Thread *tp)
 Resumes a suspended thread.
void chThdTerminate (Thread *tp)
 Requests a thread termination.
void chThdSleep (systime_t time)
 Suspends the invoking thread for the specified time.
void chThdSleepUntil (systime_t time)
 Suspends the invoking thread until the system time arrives to the specified value.
void chThdYield (void)
 Yields the time slot.
void chThdExit (msg_t msg)
 Terminates the current thread by specifying an exit status code.
Thread * chThdAddRef (Thread *tp)
 Adds a reference to a thread object.
void chThdRelease (Thread *tp)
 Releases a reference to a thread object.
msg_t chThdWait (Thread *tp)
 Blocks the execution of the invoking thread until the specified thread terminates then the exit code is returned.
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Detailed Description

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Threads macros and structures.

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Definition in file chthreads.h.

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chvt.c File Reference

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Time and Virtual Timers related code. -More...

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-Functions

void vt_init (void)
 Virtual Timers initialization.
void chVTSetI (VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par)
 Enables a virtual timer.
void chVTResetI (VirtualTimer *vtp)
 Disables a Virtual Timer.
bool_t chTimeIsWithin (systime_t start, systime_t end)
 Checks if the current system time is within the specified time window.

-Variables

VTList vtlist
 Virtual timers delta list header.
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Detailed Description

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Time and Virtual Timers related code.

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Definition in file chvt.c.

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chvt.h File Reference

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Time macros and structures. -More...

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-Data Structures

struct  VirtualTimer
 Virtual Timer descriptor structure. More...
struct  VTList
 Virtual timers list header. More...

-Defines

#define S2ST(sec)   ((systime_t)((sec) * CH_FREQUENCY))
 Time conversion utility.
#define MS2ST(msec)   ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L))
 Time conversion utility.
#define US2ST(usec)   ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L))
 Time conversion utility.
#define chVTDoTickI()
 Virtual timers ticker.
#define chVTIsArmedI(vtp)   ((vtp)->vt_func != NULL)
 Returns TRUE if the speciified timer is armed.
#define chTimeNow()   (vtlist.vt_systime)
 Current system time.

-Typedefs

typedef void(* vtfunc_t )(void *)
 Virtual Timer callback function.
typedef struct VirtualTimer VirtualTimer
 Virtual Timer structure type.

-Functions

void vt_init (void)
 Virtual Timers initialization.
void chVTSetI (VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par)
 Enables a virtual timer.
void chVTResetI (VirtualTimer *vtp)
 Disables a Virtual Timer.
bool_t chTimeIsWithin (systime_t start, systime_t end)
 Checks if the current system time is within the specified time window.

-Variables

VTList vtlist
 Virtual timers delta list header.
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Detailed Description

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Time macros and structures.

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Definition in file chvt.h.

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chibios_rt::BaseThread Class Reference

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Base class for a ChibiOS/RT thread. -More...

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#include <ch.hpp>

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Inherited by chibios_rt::EnhancedThread< N >.

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 BaseThread (void *workspace, size_t wsize, tprio_t prio)
 Thread constructor.
msg_t Wait (void)
 Synchronization on Thread exit.
void Resume (void)
 Resumes the thread.
void Terminate (void)
 Requests thread termination.
msg_t SendMessage (msg_t msg)
 Sends a message to the thread and returns the answer.
virtual msg_t Main (void)
 Thread body function.

-Static Public Member Functions

static void Exit (msg_t msg)
 Thread exit.
static void SetPriority (tprio_t newprio)
 Changes the thread priority.
static void Sleep (systime_t n)
 Suspends the thread execution for the specified number of system ticks.
static void SleepUntil (systime_t time)
 Suspends the thread execution until the specified time arrives.
static msg_t SendMessage (::Thread *tp, msg_t msg)
 Sends a message to the thread and returns the answer.
static msg_t WaitMessage (void)
 Waits for a message and returns it.
static msg_t GetMessage (void)
 Returns an enqueued message or NULL.
static void ReleaseMessage (msg_t msg)
 Releases the next message in queue with a reply.
static bool IsPendingMessage (void)
 Returns true if there is at least one message in queue.

-Data Fields

::Thread * thread_ref
 Pointer to the system thread.
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Detailed Description

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Base class for a ChibiOS/RT thread.

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The thread body is the virtual function Main().

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Definition at line 120 of file ch.hpp.

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Constructor & Destructor Documentation

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Definition at line 107 of file ch.cpp.

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chibios_rt::CondVar Class Reference

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Class encapsulating a conditional variable. -More...

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#include <ch.hpp>

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 CondVar (void)
 CondVar constructor.
void Signal (void)
 Signals the CondVar.
void Broadcast (void)
 Broadcasts the CondVar.
msg_t Wait (void)
 Waits on the CondVar while releasing the controlling mutex.
msg_t WaitTimeout (systime_t time)
 Waits on the CondVar while releasing the controlling mutex.

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struct::CondVar condvar
 Embedded CondVar structure.
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Detailed Description

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Class encapsulating a conditional variable.

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Definition at line 410 of file ch.hpp.

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CondVar::CondVar (void  ) 
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CondVar constructor.

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The embedded CondVar structure is initialized.

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Definition at line 234 of file ch.cpp.

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References chCondInit(), and condvar.

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void CondVar::Signal (void  ) 
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Signals the CondVar.

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The next thread waiting on the CondVar, if any, is awakened.

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Definition at line 239 of file ch.cpp.

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References chCondSignal(), and condvar.

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void CondVar::Broadcast (void  ) 
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Broadcasts the CondVar.

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All the threads waiting on the CondVar, if any, are awakened.

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Definition at line 244 of file ch.cpp.

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References chCondBroadcast(), and condvar.

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msg_t CondVar::Wait (void  ) 
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Waits on the CondVar while releasing the controlling mutex.

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The wakep mode.
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RDY_OK if the condvar was signaled using chCondSignal().
RDY_RESET if the condvar was signaled using chCondBroadcast().
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Definition at line 249 of file ch.cpp.

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References chCondWait(), and condvar.

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msg_t CondVar::WaitTimeout (systime_t  time ) 
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Waits on the CondVar while releasing the controlling mutex.

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The wakep mode.
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RDY_OK if the condvar was signaled using chCondSignal().
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RDY_TIMEOUT if the condvar was not signaled within the specified timeout.
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Definition at line 255 of file ch.cpp.

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References chCondWaitTimeout(), and condvar.

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struct ::CondVar chibios_rt::CondVar::condvar
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Embedded CondVar structure.

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Definition at line 415 of file ch.hpp.

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Referenced by Broadcast(), CondVar(), Signal(), Wait(), and WaitTimeout().

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chibios_rt::EnhancedThread< N > Class Template Reference

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Enhanced threads template class. -More...

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Inherits chibios_rt::BaseThread.

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 EnhancedThread (const char *tname, tprio_t prio)
 Full constructor.
 EnhancedThread (const char *tname)
 Simplified constructor.

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const char * name
 The thread name.
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template<int N>
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Enhanced threads template class.

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This class introduces thread names and static working area allocation.

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Definition at line 254 of file ch.hpp.

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chibios_rt::EnhancedThread< N >::EnhancedThread (const char *  tname,
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Full constructor.

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This constructor allows to set a priority level for the new thread.

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Definition at line 271 of file ch.hpp.

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Simplified constructor.

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This constructor allows to create a thread by simply specifying a name. In is assumed NORMALPRIO as initial priority.

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Definition at line 284 of file ch.hpp.

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The thread name.

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Definition at line 262 of file ch.hpp.

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chibios_rt::Event Class Reference

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 Event (void)
 Event constructor.
void Register (EventListener *elp, eventid_t eid)
 Registers a listener on the event source.
void RegisterMask (EventListener *elp, eventmask_t emask)
 Registers an Event Listener on an Event Source.
void Unregister (EventListener *elp)
 Unregisters a listener.
void Broadcast (void)
 Broadcasts an event.

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static eventmask_t Clear (eventmask_t mask)
 Clears specified events from the pending events mask.
static eventmask_t Pend (eventmask_t mask)
 Makes an events mask pending in the current thread.
static void Dispatch (const evhandler_t handlers[], eventmask_t mask)
 Invokes the event handlers associated with a mask.
static eventmask_t WaitOne (eventmask_t ewmask)
 Waits for a single event.
static eventmask_t WaitAny (eventmask_t ewmask)
 Waits for any of the specified events.
static eventmask_t WaitAll (eventmask_t ewmask)
 Waits for all the specified event flags then clears them.
static eventmask_t WaitOneTimeout (eventmask_t ewmask, systime_t time)
 Waits for a single event.
static eventmask_t WaitAnyTimeout (eventmask_t ewmask, systime_t time)
 Waits for any of the specified events.
static eventmask_t WaitAllTimeout (eventmask_t ewmask, systime_t time)
 Waits for all the specified event flags then clears them.

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struct::EventSource event
 Embedded EventSource structure.
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Class encapsulating an event source.

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Definition at line 465 of file ch.hpp.

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Event constructor.

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The embedded EventSource structure is initialized.

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Definition at line 267 of file ch.cpp.

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Definition at line 277 of file ch.cpp.

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Definition at line 292 of file ch.cpp.

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struct ::EventSource chibios_rt::Event::event
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Embedded EventSource structure.

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chibios_rt::Mutex Class Reference

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Class encapsulating a mutex. -More...

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#include <ch.hpp>

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-Public Member Functions

 Mutex (void)
 Mutex constructor.
bool TryLock (void)
 Tries a lock operation on the mutex.
void Lock (void)
 Locks the mutex.

-Static Public Member Functions

static void Unlock (void)
 Unlocks the mutex.
static void UnlockAll (void)
 Unlocks all the mutexes owned by the invoking thread.

-Data Fields

struct::Mutex mutex
 Embedded Mutex structure.
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Detailed Description

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Class encapsulating a mutex.

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Definition at line 361 of file ch.hpp.

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Mutex::Mutex (void  ) 
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Mutex constructor.

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The embedded Mutex structure is initialized.

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Definition at line 205 of file ch.cpp.

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bool Mutex::TryLock (void  ) 
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Tries a lock operation on the mutex.

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Definition at line 210 of file ch.cpp.

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void Mutex::Lock (void  ) 
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Definition at line 215 of file ch.cpp.

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void Mutex::Unlock (void  )  [static]
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Definition at line 220 of file ch.cpp.

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static void chibios_rt::Mutex::UnlockAll (void  )  [static]
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Unlocks all the mutexes owned by the invoking thread.

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This operation is MUCH MORE efficient than releasing the mutexes one by one and not just because the call overhead, this function does not have any overhead related to the priority inheritance mechanism.

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struct ::Mutex chibios_rt::Mutex::mutex
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Embedded Mutex structure.

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Definition at line 366 of file ch.hpp.

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chibios_rt::Semaphore Class Reference

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Class encapsulating a semaphore. -More...

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#include <ch.hpp>

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 Semaphore (cnt_t n)
 Semaphore constructor.
void Reset (cnt_t n)
 Resets a semaphore.
msg_t Wait (void)
 Wait operation on the semaphore.
msg_t WaitTimeout (systime_t time)
 Wait operation on the semaphore with timeout.
void Signal (void)
 Signal operation on the semaphore.

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static msg_t SignalWait (Semaphore *ssem, Semaphore *wsem)
 Atomic signal and wait operations.

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struct::Semaphore sem
 Embedded Semaphore structure.
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Detailed Description

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Class encapsulating a semaphore.

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Definition at line 295 of file ch.hpp.

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Semaphore::Semaphore (cnt_t  n ) 
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The embedded Semaphore structure is initialized.

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Definition at line 168 of file ch.cpp.

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void Semaphore::Reset (cnt_t  n ) 
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Definition at line 173 of file ch.cpp.

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msg_t Semaphore::Wait (void  ) 
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Definition at line 178 of file ch.cpp.

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msg_t Semaphore::WaitTimeout (systime_t  time ) 
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Definition at line 183 of file ch.cpp.

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void Semaphore::Signal (void  ) 
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msg_t Semaphore::SignalWait (Semaphore *  ssem,
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struct ::Semaphore chibios_rt::Semaphore::sem
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Embedded Semaphore structure.

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Definition at line 300 of file ch.hpp.

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chibios_rt::System Class Reference

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Class encapsulating the base system functionalities. -More...

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#include <ch.hpp>

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static void Init (void)
 ChibiOS/RT initialization.
static void Lock (void)
 Kernel lock.
static void Unlock (void)
 Kernel unlock.
static systime_t GetTime (void)
 Returns the system time as system ticks.
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Detailed Description

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Class encapsulating the base system functionalities.

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Definition at line 44 of file ch.hpp.

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Member Function Documentation

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void chibios_rt::System::Init (void  )  [static]
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ChibiOS/RT initialization.

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The system is initialized, the idle thread is spawned and the current instruction flow becomes the main thread with priority NORMALPRIO.

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Definition at line 39 of file ch.cpp.

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void chibios_rt::System::Lock (void  )  [static]
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Kernel lock.

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Definition at line 44 of file ch.cpp.

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void chibios_rt::System::Unlock (void  )  [static]
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Kernel unlock.

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Definition at line 49 of file ch.cpp.

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systime_t chibios_rt::System::GetTime (void  )  [static]
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Returns the system time as system ticks.

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Definition at line 54 of file ch.cpp.

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chibios_rt::Timer Class Reference

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Timer class. -More...

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#include <ch.hpp>

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void Set (systime_t time, vtfunc_t vtfunc, void *par)
 Starts the timer.
void Reset ()
 Resets the timer.
bool IsArmed (void)
 Returns the timer status.

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struct::VirtualTimer timer
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Detailed Description

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Timer class.

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Definition at line 81 of file ch.hpp.

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void chibios_rt::Timer::Set (systime_t  time,
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vtfunc the timer callback function
par the parameter for the callback function
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Definition at line 62 of file ch.cpp.

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void chibios_rt::Timer::Reset ( ) 
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Definition at line 67 of file ch.cpp.

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bool chibios_rt::Timer::IsArmed (void  ) 
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Definition at line 72 of file ch.cpp.

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struct ::VirtualTimer chibios_rt::Timer::timer
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Embedded VirtualTimer structure.

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Definition at line 86 of file ch.hpp.

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Referenced by IsArmed(), Reset(), and Set().

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ADCDriver   CondVar (chibios_rt)   intctx   
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Kernel Concepts

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ChibiOS/RT Kernel Concepts

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-Naming Conventions

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ChibiOS/RT APIs are all named following this convention: ch<group><action><suffix>(). The possible groups are: Sys, Sch, Time, VT, Thd, Sem, Mtx, Cond, Evt, Msg, SequentialStream, IO, IQ, OQ, Dbg, Core, Heap, Pool.

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The suffix can be one of the following:

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Examples: chThdCreateStatic(), chSemSignalI(), chIQGetTimeout().

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In ChibiOS/RT there are three logical interrupt classes:

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When using ChibiOS/RT the system can be in one of the following logical operating states:

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The strategy is very simple the currently ready thread with the highest priority is executed. If more than one thread with equal priority are eligible for execution then they are executed in a round-robin way, the CPU time slice constant is configurable. The ready list is a double linked list of threads ordered by priority.
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Each thread has its own stack, a Thread structure and some preemption areas. All the structures are allocated into a "Thread Working Area", a thread private heap, usually statically declared in your code. Threads do not use any memory outside the allocated working area except when accessing static shared data.
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Copyright and Credits

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Copyright and Credits

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Copyright Statement

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-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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Contributions and Copyright Assignment

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If you plan to contribute code to the ChibiOS/RT project then there is a requirement you should be aware of: contributing code for inclusion in the ChibiOS/RT main line requires assigning the copyright on the contributed code to me (Giovanni Di Sirio).
- This may sound a bit strange but is pretty standard for this kind of projects, there are several reasons for this requirement:

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  • ChibiOS/RT will probably also become a commercial product and it would not be possible to re-license the code without ownership. Note that the commercial product would not be a different or better product, just the same GPL product made available, on request, under a different license. The code will always be available to you under the current licensing terms.
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  • Ownership is required when changing the licensing terms and this happens each time the project goes from development/unstable to stable and back because the addition/removal of the GPL linking exception.
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  • It will be easier for the project adopters to have a single ownership point in case of licensing issues (both GPL or commercial).
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  • Losing the ownership on the code could preclude me the opportunity to make this project a full time job as I hope.
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  • I definitely don't want to have to sort out copyright related issues in the future so better be clear than sorry.
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Note that contributions will always be welcome even without such copyright assignment, the difference is that the contributed code would not be merged into the main line, it will still made available as contributed code with the contributor(s) copyright notice intact.
- Submissions of code with copyright notice should only happen through email, please do not commit code with copyright notices directly on the repository.
- When submitting code please state clearly your intention to keep the copyright on your work by adding your own copyright notice within the source code and by clearly mentioning your intentions in the message. Code contributed without copyright notice will be considered donated.
- If in doubt with licensing issues please don't hesitate to contact me in order to sort out any problem you may have.
- Of course the copyright assignment does not mean you would not be recognized for your hard work, see the following section.

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Credits

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I want to thank all the people that directly or indirectly contributed to the project, I beg pardon if someone is missing:

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  • Adamo Reggiani, working on the Fujitsu port.
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  • Alexander Kozaruk, AT91SAM7S256 demo and description files for the Olimex SAM7-P256 board.
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  • Brian Weaver, STM8 port, STM8 and STM32 testing and improvements.
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  • Egon Carusi, STM32 port improvements, testing and bug fixes.
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  • Enrico Cavazza, working on the Fujitsu port and a GUI subsystem.
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  • Eric Weddington, because his work on WinAVR and helping me sorting out issues with the ChibiOS/RT license.
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  • Isidoro Orabona, co-developer of the ChibiOS/RT grandfather back in 1988, it is a long long story involving a 6502 and a Z80...
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  • Jacek, Ride7 demo for STM32 Primer.
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  • Leon Woestenberg, CondVars idea and implementation, documentation improvements and a lot of other ideas, he also helped with the lwIP port (he is one of the developers of that project too).
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  • Leszek Bednarz, H8S and ColdFire ports and drivers maintainer.
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  • Liam Staskawicz, Posix simulator, AT91SAM7x and STM32 related contributions, general improvements, many bug fixes and excellent suggestions.
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  • Michael Fischer, because the work on YAGARTO and the excellent feedback.
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  • Riccardo Scanu, another long story, this time involving reverse engineering and giant robots...
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  • Vladimir, first tested and fixed the AVR port, I don't know the surname but he has been the first contributor.
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  • Walter Goossens, several fixes to the LPC21xx support.
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- font-weight: bold; -} - -.directory h3 { - margin: 0px; - margin-top: 1em; - font-size: 11pt; -} - -/* -The following two styles can be used to replace the root node title -with an image of your choice. Simply uncomment the next two styles, -specify the name of your image and be sure to set 'height' to the -proper pixel height of your image. -*/ - -/* -.directory h3.swap { - height: 61px; - background-repeat: no-repeat; - background-image: url("yourimage.gif"); -} -.directory h3.swap span { - display: none; -} -*/ - -.directory > h3 { - margin-top: 0; -} - -.directory p { - margin: 0px; - white-space: nowrap; -} - -.directory div { - display: none; - margin: 0px; -} - -.directory img { - vertical-align: -30%; -} - -/* these are for tree view when not used as main index */ - -.directory-alt { - font-size: 100%; - font-weight: bold; -} - -.directory-alt h3 { - margin: 0px; - margin-top: 1em; - font-size: 11pt; -} - -.directory-alt > h3 { - margin-top: 0; -} - -.directory-alt p { - margin: 0px; - white-space: nowrap; -} - -.directory-alt div { - display: none; - margin: 0px; -} - -.directory-alt img { - vertical-align: -30%; -} - -/* @end */ - -address { - font-style: normal; - color: #333; -} diff --git a/ChibiOS_2.0.8/docs/html/doxygen.png b/ChibiOS_2.0.8/docs/html/doxygen.png deleted file mode 100644 index 635ed52..0000000 Binary files a/ChibiOS_2.0.8/docs/html/doxygen.png and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse003.jpg b/ChibiOS_2.0.8/docs/html/eclipse003.jpg deleted file mode 100644 index a5cee79..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse003.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse004.jpg b/ChibiOS_2.0.8/docs/html/eclipse004.jpg deleted file mode 100644 index 4d3fc2a..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse004.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse005.jpg b/ChibiOS_2.0.8/docs/html/eclipse005.jpg deleted file mode 100644 index 63ce31e..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse005.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse006.jpg b/ChibiOS_2.0.8/docs/html/eclipse006.jpg deleted file mode 100644 index fd56acd..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse006.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse007.jpg b/ChibiOS_2.0.8/docs/html/eclipse007.jpg deleted file mode 100644 index 9332d57..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse007.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse008.jpg b/ChibiOS_2.0.8/docs/html/eclipse008.jpg deleted file mode 100644 index f602fa8..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse008.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse009.jpg b/ChibiOS_2.0.8/docs/html/eclipse009.jpg deleted file mode 100644 index fb8264b..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse009.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse010.jpg b/ChibiOS_2.0.8/docs/html/eclipse010.jpg deleted file mode 100644 index d92381b..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse010.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse011.jpg b/ChibiOS_2.0.8/docs/html/eclipse011.jpg deleted file mode 100644 index 1da3052..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse011.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse012.jpg b/ChibiOS_2.0.8/docs/html/eclipse012.jpg deleted file mode 100644 index e40725f..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse012.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/eclipse013.jpg b/ChibiOS_2.0.8/docs/html/eclipse013.jpg deleted file mode 100644 index bc8441e..0000000 Binary files a/ChibiOS_2.0.8/docs/html/eclipse013.jpg and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/evtimer_8c.html b/ChibiOS_2.0.8/docs/html/evtimer_8c.html deleted file mode 100644 index e462e62..0000000 --- a/ChibiOS_2.0.8/docs/html/evtimer_8c.html +++ /dev/null @@ -1,65 +0,0 @@ - - -ChibiOS/RT: evtimer.c File Reference - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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evtimer.c File Reference

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Events Generator Timer code. -More...

-#include "ch.h"
-#include "evtimer.h"
- -

Go to the source code of this file.

- - - - - - -

-Functions

void evtStart (EvTimer *etp)
 Starts the timer.
void evtStop (EvTimer *etp)
 Stops the timer.
-

Detailed Description

-

Events Generator Timer code.

- -

Definition in file evtimer.c.

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-Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/evtimer_8c_source.html b/ChibiOS_2.0.8/docs/html/evtimer_8c_source.html deleted file mode 100644 index dcdea34..0000000 --- a/ChibiOS_2.0.8/docs/html/evtimer_8c_source.html +++ /dev/null @@ -1,120 +0,0 @@ - - -ChibiOS/RT: evtimer.c Source File - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Generated on Sun Nov 28 2010 14:09:49 for ChibiOS/RT by doxygen 1.7.1
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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evtimer.h File Reference

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Events Generator Timer structures and macros. -More...

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Go to the source code of this file.

- - - - - - - - - - - - -

-Data Structures

struct  EvTimer
 Event timer structure. More...

-Defines

#define evtInit(etp, time)
 Initializes an EvTimer structure.

-Functions

void evtStart (EvTimer *etp)
 Starts the timer.
void evtStop (EvTimer *etp)
 Stops the timer.
-

Detailed Description

-

Events Generator Timer structures and macros.

- -

Definition in file evtimer.h.

-
-
-Generated on Sun Nov 28 2010 14:09:50 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/evtimer_8h_source.html b/ChibiOS_2.0.8/docs/html/evtimer_8h_source.html deleted file mode 100644 index f17f993..0000000 --- a/ChibiOS_2.0.8/docs/html/evtimer_8h_source.html +++ /dev/null @@ -1,113 +0,0 @@ - - -ChibiOS/RT: evtimer.h Source File - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Generated on Sun Nov 28 2010 14:09:49 for ChibiOS/RT by doxygen 1.7.1
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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File List

-
-
-Here is a list of all documented files with brief descriptions: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
adc.c [code]ADC Driver code
adc.h [code]ADC Driver macros and structures
templates/adc_lld.c [code]ADC Driver subsystem low level driver source template
platforms/STM32/adc_lld.c [code]STM32 ADC subsystem low level driver source
templates/adc_lld.h [code]ADC Driver subsystem low level driver header template
platforms/STM32/adc_lld.h [code]STM32 ADC subsystem low level driver header
at91sam7.h [code]
at91sam7_mii.c [code]AT91SAM7 low level MII driver code
at91sam7_mii.h [code]AT91SAM7 low level MII driver header
can.c [code]CAN Driver code
can.h [code]CAN Driver macros and structures
templates/can_lld.c [code]CAN Driver subsystem low level driver source template
platforms/STM32/can_lld.c [code]STM32 CAN subsystem low level driver source
templates/can_lld.h [code]CAN Driver subsystem low level driver header template
platforms/STM32/can_lld.h [code]STM32 CAN subsystem low level driver header
ch.cpp [code]C++ wrapper code
ch.h [code]ChibiOS/RT main include file
ch.hpp [code]C++ wrapper classes and definitions
chcond.c [code]Condition Variables code
chcond.h [code]Condition Variables macros and structures
chconf.h [code]Configuration file template
kernel/templates/chcore.c [code]Port related template code
ports/GCC/AVR/chcore.c [code]AVR architecture port code
ports/GCC/ARM7/chcore.c [code]ARM7 architecture port code
ports/GCC/ARMCMx/chcore.c [code]ARM Cortex-Mx port code
ports/GCC/PPC/chcore.c [code]PowerPC architecture port code
ports/GCC/MSP430/chcore.c [code]MSP430 architecture port code
ports/RC/STM8/chcore.c [code]STM8 architecture port code
kernel/templates/chcore.h [code]Port related template macros and structures
ports/GCC/AVR/chcore.h [code]AVR architecture port macros and structures
ports/GCC/ARM7/chcore.h [code]ARM7 architecture port macros and structures
ports/GCC/ARMCMx/chcore.h [code]ARM Cortex-Mx port macros and structures
ports/GCC/PPC/chcore.h [code]PowerPC architecture port macros and structures
ports/GCC/MSP430/chcore.h [code]MSP430 architecture port macros and structures
ports/RC/STM8/chcore.h [code]STM8 architecture port macros and structures
chcore_v6m.c [code]ARMv6-M architecture port code
chcore_v6m.h [code]ARMv6-M architecture port macros and structures
chcore_v7m.c [code]ARMv7-M architecture port code
chcore_v7m.h [code]ARMv7-M architecture port macros and structures
chcoreasm.s [code]ARM7 architecture port low level code
chdebug.c [code]ChibiOS/RT Debug code
chdebug.h [code]Debug macros and structures
chevents.c [code]Events code
chevents.h [code]Events macros and structures
chheap.c [code]Heaps code
chheap.h [code]Heaps macros and structures
chinline.h [code]Kernel inlined functions
chioch.h [code]I/O channels
chlists.c [code]Thread queues/lists code
chlists.h [code]Thread queues/lists macros and structures
chmboxes.c [code]Mailboxes code
chmboxes.h [code]Mailboxes macros and structures
chmemcore.c [code]Core memory manager code
chmemcore.h [code]Core memory manager macros and structures
chmempools.c [code]Memory Pools code
chmempools.h [code]Memory Pools macros and structures
chmsg.c [code]Messages code
chmsg.h [code]Messages macros and structures
chmtx.c [code]Mutexes code
chmtx.h [code]Mutexes macros and structures
chqueues.c [code]I/O Queues code
chqueues.h [code]Queues macros and structures
chregistry.c [code]Threads registry code
chregistry.h [code]Threads registry macros and structures
chschd.c [code]Scheduler code
chschd.h [code]Scheduler macros and structures
chsem.c [code]Semaphores code
chsem.h [code]Semaphores macros and structures
chstreams.h [code]Data streams
chsys.c [code]System related code
chsys.h [code]System related macros and structures
chthreads.c [code]Threads code
chthreads.h [code]Threads macros and structures
kernel/templates/chtypes.h [code]System types template
ports/GCC/AVR/chtypes.h [code]AVR architecture port system types
ports/GCC/ARM7/chtypes.h [code]ARM7 architecture port system types
ports/GCC/ARMCMx/chtypes.h [code]ARM Cortex-Mx port system types
ports/GCC/PPC/chtypes.h [code]PowerPC architecture port system types
ports/GCC/MSP430/chtypes.h [code]MSP430 architecture port system types
ports/RC/STM8/chtypes.h [code]STM8 port system types
chvt.c [code]Time and Virtual Timers related code
chvt.h [code]Time macros and structures
STM32F10x/cmparams.h [code]ARM Cortex-M3 STM32F10x Specific Parameters
LPC11xx/cmparams.h [code]ARM Cortex-M0 LPC11xx Specific Parameters
LPC13xx/cmparams.h [code]ARM Cortex-M3 LPC13xx Specific Parameters
ARM7/crt0.s [code]Generic ARM7 startup file for ChibiOS/RT
ARMCMx/crt0.s [code]Generic ARM Cortex-Mx startup file for ChibiOS/RT
PPC/crt0.s [code]Generic PowerPC startup file for ChibiOS/RT
evtimer.c [code]Events Generator Timer code
evtimer.h [code]Events Generator Timer structures and macros
hal.c [code]HAL subsystem code
hal.h [code]HAL subsystem header
templates/hal_lld.c [code]HAL Driver subsystem low level driver source template
platforms/AT91SAM7/hal_lld.c [code]AT91SAM7 HAL subsystem low level driver source
platforms/AVR/hal_lld.c [code]AVR HAL subsystem low level driver code
platforms/LPC11xx/hal_lld.c [code]LPC11xx HAL subsystem low level driver source
platforms/LPC13xx/hal_lld.c [code]LPC13xx HAL subsystem low level driver source
platforms/LPC214x/hal_lld.c [code]LPC214x HAL subsystem low level driver source
platforms/MSP430/hal_lld.c [code]MSP430 HAL subsystem low level driver source
platforms/SPC56x/hal_lld.c [code]SPC563 HAL subsystem low level driver source
platforms/STM32/hal_lld.c [code]STM32 HAL subsystem low level driver source
platforms/STM8/hal_lld.c [code]STM8 HAL subsystem low level driver source
templates/hal_lld.h [code]HAL subsystem low level driver header template
platforms/AT91SAM7/hal_lld.h [code]AT91SAM7 HAL subsystem low level driver header
platforms/AVR/hal_lld.h [code]AVR HAL subsystem low level driver header
platforms/LPC11xx/hal_lld.h [code]HAL subsystem low level driver header template
platforms/LPC13xx/hal_lld.h [code]HAL subsystem low level driver header template
platforms/LPC214x/hal_lld.h [code]LPC214x HAL subsystem low level driver header
platforms/MSP430/hal_lld.h [code]MSP430 HAL subsystem low level driver header
platforms/SPC56x/hal_lld.h [code]SPC563 HAL subsystem low level driver header
platforms/STM32/hal_lld.h [code]STM32 HAL subsystem low level driver header
platforms/STM8/hal_lld.h [code]STM8 HAL subsystem low level driver source
hal_lld_f103.h [code]STM32F103 HAL subsystem low level driver header
hal_lld_f105_f107.h [code]STM32F10x Connectivity Line HAL subsystem low level driver header
halconf.h [code]HAL configuration header
lpc214x.h [code]LPC214x register definitions
mac.c [code]MAC Driver code
mac.h [code]MAC Driver macros and structures
templates/mac_lld.c [code]MAC Driver subsystem low level driver source template
platforms/AT91SAM7/mac_lld.c [code]AT91SAM7 low level MAC driver code
templates/mac_lld.h [code]MAC Driver subsystem low level driver header template
platforms/AT91SAM7/mac_lld.h [code]AT91SAM7 low level MAC driver header
memstreams.c [code]Memory streams code
memstreams.h [code]Memory streams structures and macros
mii.h [code]
mmc_spi.c [code]MMC over SPI driver code
mmc_spi.h [code]MMC over SPI driver header
mpc563m.h [code]
nvic.c [code]Cortex-Mx NVIC support code
nvic.h [code]Cortex-Mx NVIC support macros and structures
pal.c [code]I/O Ports Abstraction Layer code
pal.h [code]I/O Ports Abstraction Layer macros, types and structures
templates/pal_lld.c [code]PAL subsystem low level driver template
platforms/AT91SAM7/pal_lld.c [code]AT91SAM7 PIO low level driver code
platforms/LPC11xx/pal_lld.c [code]LPC11xx GPIO low level driver code
platforms/LPC13xx/pal_lld.c [code]LPC13xx GPIO low level driver code
platforms/LPC214x/pal_lld.c [code]LPC214x FIO low level driver code
platforms/MSP430/pal_lld.c [code]MSP430 Digital I/O low level driver code
platforms/STM32/pal_lld.c [code]STM32 GPIO low level driver code
platforms/STM8/pal_lld.c [code]STM8 GPIO low level driver code
templates/pal_lld.h [code]PAL subsystem low level driver header template
platforms/AT91SAM7/pal_lld.h [code]AT91SAM7 PIO low level driver header
platforms/LPC11xx/pal_lld.h [code]LPC11xx GPIO low level driver header
platforms/LPC13xx/pal_lld.h [code]LPC13xx GPIO low level driver header
platforms/LPC214x/pal_lld.h [code]LPC214x FIO low level driver header
platforms/MSP430/pal_lld.h [code]MSP430 Digital I/O low level driver header
platforms/STM32/pal_lld.h [code]STM32 GPIO low level driver header
platforms/STM8/pal_lld.h [code]STM8 GPIO low level driver header
pwm.c [code]PWM Driver code
pwm.h [code]PWM Driver macros and structures
templates/pwm_lld.c [code]PWM Driver subsystem low level driver source template
platforms/STM32/pwm_lld.c [code]STM32 PWM subsystem low level driver header
templates/pwm_lld.h [code]PWM Driver subsystem low level driver header template
platforms/STM32/pwm_lld.h [code]STM32 PWM subsystem low level driver header
serial.c [code]Serial Driver code
serial.h [code]Serial Driver macros and structures
templates/serial_lld.c [code]Serial Driver subsystem low level driver source template
platforms/AT91SAM7/serial_lld.c [code]AT91SAM7 low level serial driver code
platforms/AVR/serial_lld.c [code]AVR low level serial driver code
platforms/LPC11xx/serial_lld.c [code]LPC11xx low level serial driver code
platforms/LPC13xx/serial_lld.c [code]LPC13xx low level serial driver code
platforms/LPC214x/serial_lld.c [code]LPC214x low level serial driver code
platforms/MSP430/serial_lld.c [code]MSP430 low level serial driver code
platforms/SPC56x/serial_lld.c [code]SPC563 low level serial driver code
platforms/STM32/serial_lld.c [code]STM32 low level serial driver code
platforms/STM8/serial_lld.c [code]STM8 low level serial driver code
templates/serial_lld.h [code]Serial Driver subsystem low level driver header template
platforms/AT91SAM7/serial_lld.h [code]AT91SAM7 low level serial driver header
platforms/AVR/serial_lld.h [code]AVR low level serial driver header
platforms/LPC11xx/serial_lld.h [code]LPC11xx low level serial driver header
platforms/LPC13xx/serial_lld.h [code]LPC13xx low level serial driver header
platforms/LPC214x/serial_lld.h [code]LPC214x low level serial driver header
platforms/MSP430/serial_lld.h [code]MSP430 low level serial driver header
platforms/SPC56x/serial_lld.h [code]SPC563 low level serial driver header
platforms/STM32/serial_lld.h [code]STM32 low level serial driver header
platforms/STM8/serial_lld.h [code]STM8 low level serial driver header
shell.c [code]Simple CLI shell code
shell.h [code]Simple CLI shell header
spi.c [code]SPI Driver code
spi.h [code]SPI Driver macros and structures
templates/spi_lld.c [code]SPI Driver subsystem low level driver source template
platforms/LPC214x/spi_lld.c [code]LPC214x low level SPI driver code
platforms/STM32/spi_lld.c [code]STM32 SPI subsystem low level driver source
templates/spi_lld.h [code]SPI Driver subsystem low level driver header template
platforms/LPC214x/spi_lld.h [code]LPC214x low level SPI driver header
platforms/STM32/spi_lld.h [code]STM32 SPI subsystem low level driver header
stm32_dma.c [code]STM32 DMA helper driver code
stm32_dma.h [code]STM32 DMA helper driver header
stm8.h [code]
syscalls.c [code]
test.c [code]Tests support code
test.h [code]Tests support header
testbmk.c [code]Kernel Benchmarks source file
testbmk.h [code]Kernel Benchmarks header file
testdyn.c [code]Dynamic thread APIs test source file
testdyn.h [code]Dynamic thread APIs test header file
testevt.c [code]Events test source file
testevt.h [code]Events test header file
testheap.c [code]Heap test source file
testheap.h [code]Heap header file
testmbox.c [code]Mailboxes test source file
testmbox.h [code]Mailboxes header file
testmsg.c [code]Messages test source file
testmsg.h [code]Messages header file
testmtx.c [code]Mutexes and CondVars test source file
testmtx.h [code]Mutexes and CondVars test header file
testpools.c [code]Memory Pools test source file
testpools.h [code]Memory Pools test header file
testqueues.c [code]I/O Queues test source file
testqueues.h [code]I/O Queues test header file
testsem.c [code]Semaphores test source file
testsem.h [code]Semaphores test header file
testthd.c [code]Threads and Scheduler test source file
testthd.h [code]Threads and Scheduler test header file
typedefs.h [code]Dummy typedefs file
vic.c [code]LPC214x VIC peripheral support code
vic.h [code]LPC214x VIC peripheral support header
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Project Goals

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Another RTOS?

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The first question to be answered is: there was really the need for YET ANOTHER RTOS?
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  • The ChibiOS/RT ancestor was created more than 15 years ago and while it had far less features than the current product it was complete and functioning. ChibiOS/RT is just a new (and silly) name given to something created when there were not many free RTOSes around (actually none, at least none in my knowledge, there was no widespread Internet at that time).
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  • When, after a while, I needed a RTOS again, none of the existing FOSS projects met my expectations or my ideas of how a RTOS should be, not even close (see below). I decided that work on that old project was a better idea than contribute to, or fork, something else.
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Why is it different?

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Well, there are some design choices that should be explained and contribute to make ChibiOS/RT a peculiar design. Nothing really new in itself but the whole is interesting:

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Static design

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Everything in the kernel is static, nowhere memory is allocated or freed, there are three allocator subsystems but those are options and not part of core OS. Safety is something you design in, not something you can add later.

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No tables, arrays or other fixed structures

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The kernel has no internal tables, there is nothing that must be configured at compile time or that can overflow at run time. No upper bounds, the internal structures are all dynamic even if all the objects are statically allocated.

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No error conditions and no error checks

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All the system APIs have no error conditions, all the previous points are finalized to this objective. Everything you can invoke in the kernel is designed to not fail unless you pass garbage as parameters, stray pointers as examples. The APIs are not slowed down by parameter checks, parameter checks (and consistency checks) do exist but only when the debug switch is activated.
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Very simple APIs

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Each API should have the parameters you would expect for that function and do just one thing with no options.

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Fast and compact

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Note, first "fast" then "compact", the focus is on speed and execution efficiency and then on code size. This does not mean that the OS is large, the kernel size with all the subsystems activated weighs around 5.3KiB and can shrink down around to 1.2Kib in a minimal configuration (STM32, Cortex-M3). It would be possible to make something even smaller but:

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About the "fast" part, the kernel is able to start/exit over 220,000 threads per second on a 72MHz STM32. The Context Switch takes 1.2 microseconds on the same STM32.

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Tests and metrics

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I think it is nice to know how an OS is tested and how it performs before committing to use it. Test results on all the supported platforms and performance metrics are included in each ChibiOS/RT release. The test code is released as well, all the included demos are capable of executing the test suite and the OS benchmarks, see Testing Strategy.

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ADC Driver
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Generic ADC Driver. -More...

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Description

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Generic ADC Driver.

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This module implements a generic ADC driver. The driver implements a state machine internally:

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The driver supports a continuous conversion mode with circular buffer, callback functions allow to process the converted data in real time. Please refer to the documentation of the function adcStartConversion().

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 ADC Low Level Driver
 

ADC Driver low level driver template.

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-Enumerations

enum  adcstate_t {
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Driver state machine possible states.

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-Functions

void adcInit (void)
 ADC Driver initialization.
void adcObjectInit (ADCDriver *adcp)
 Initializes the standard part of a ADCDriver structure.
void adcStart (ADCDriver *adcp, const ADCConfig *config)
 Configures and activates the ADC peripheral.
void adcStop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
bool_t adcStartConversion (ADCDriver *adcp, const ADCConversionGroup *grpp, adcsample_t *samples, size_t depth, adccallback_t callback)
 Starts an ADC conversion.
void adcStopConversion (ADCDriver *adcp)
 Stops an ongoing conversion.
msg_t adcWaitConversion (ADCDriver *adcp, systime_t timeout)
 Waits for completion.
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Enumeration Type Documentation

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enum adcstate_t
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Driver state machine possible states.

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Enumerator:
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Not initialized.

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Stopped.

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Ready.

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Conversion running.

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Conversion complete.

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Definition at line 63 of file adc.h.

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Function Documentation

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void adcInit (void  ) 
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ADC Driver initialization.

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void adcObjectInit (ADCDriver *  adcp ) 
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Initializes the standard part of a ADCDriver structure.

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Definition at line 69 of file adc.c.

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References ADCDriver::ad_callback, ADCDriver::ad_config, ADCDriver::ad_depth, ADCDriver::ad_grpp, ADCDriver::ad_samples, ADCDriver::ad_sem, ADCDriver::ad_state, and chSemInit().

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void adcStart (ADCDriver *  adcp,
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Configures and activates the ADC peripheral.

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[in] config pointer to the ADCConfig object
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Definition at line 86 of file adc.c.

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void adcStop (ADCDriver *  adcp ) 
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Deactivates the ADC peripheral.

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Definition at line 105 of file adc.c.

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bool_t adcStartConversion (ADCDriver *  adcp,
const ADCConversionGroup *  grpp,
adcsample_t *  samples,
size_t  depth,
adccallback_t  callback 
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Starts an ADC conversion.

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Starts a conversion operation, there are two kind of conversion modes:

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[in] adcp pointer to the ADCDriver object
[in] grpp pointer to a ADCConversionGroup object
[out] samples pointer to the samples buffer
[in] depth buffer depth (matrix rows number). The buffer depth must be one or an even number.
[in] callback pointer to the conversion callback function, this parameter can be NULL if a callback is not required
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Definition at line 150 of file adc.c.

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References ADCDriver::ad_callback, ADCDriver::ad_depth, ADCDriver::ad_grpp, ADCDriver::ad_samples, ADCDriver::ad_state, ADC_COMPLETE, adc_lld_start_conversion(), ADC_READY, ADC_RUNNING, chDbgAssert, chDbgCheck, chSysLock, and chSysUnlock.

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void adcStopConversion (ADCDriver *  adcp ) 
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Stops an ongoing conversion.

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Definition at line 185 of file adc.c.

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References ADCDriver::ad_grpp, ADCDriver::ad_sem, ADCDriver::ad_state, ADC_COMPLETE, adc_lld_stop_conversion(), ADC_READY, ADC_RUNNING, chDbgAssert, chDbgCheck, chSchRescheduleS(), chSemResetI(), chSysLock, and chSysUnlock.

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msg_t adcWaitConversion (ADCDriver *  adcp,
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Waits for completion.

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If the conversion is not completed or not yet started then the invoking thread waits for a conversion completion event.

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[in] adcp pointer to the ADCDriver object
[in] timeout the number of ticks before the operation timeouts, the following special values are allowed:

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RDY_OK conversion finished.
RDY_TIMEOUT conversion not finished within the specified time.
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Definition at line 222 of file adc.c.

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References ADCDriver::ad_sem, ADCDriver::ad_state, ADC_COMPLETE, ADC_READY, ADC_RUNNING, chDbgAssert, chSemWaitTimeoutS(), chSysLock, chSysUnlock, and RDY_TIMEOUT.

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ADC Low Level Driver
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Description

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ADC Driver low level driver template.

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This file is a template for a ADC low level driver.

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-Data Structures

struct  ADCConversionGroup
 Conversion group configuration structure. More...
struct  ADCConfig
 Driver configuration structure. More...
struct  ADCDriver
 Structure representing an ADC driver. More...

-Typedefs

typedef uint16_t adcsample_t
 ADC sample data type.
typedef uint16_t adc_channels_num_t
 Channels number in a conversion group.
typedef void(* adccallback_t )(adcsample_t *buffer, size_t n)
 ADC notification callback type.

-Functions

void adc_lld_init (void)
 Low level ADC driver initialization.
void adc_lld_start (ADCDriver *adcp)
 Configures and activates the ADC peripheral.
void adc_lld_stop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
void adc_lld_start_conversion (ADCDriver *adcp)
 Starts an ADC conversion.
void adc_lld_stop_conversion (ADCDriver *adcp)
 Stops an ongoing conversion.
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Typedef Documentation

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typedef uint16_t adcsample_t
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ADC sample data type.

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Referenced by adcStopConversion(), and CH_IRQ_HANDLER().

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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ARM7TDMI
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Description

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The ARM7 architecture is quite complex for a microcontroller and some explanations are required about the port choices.

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-The ARM7 modes

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The ARM7 port supports three modes:

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  • Pure ARM mode, this is the preferred mode for code speed. The code size is larger however. This mode is enabled when all the modules are compiled in ARM mode, see the Makefiles.
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  • Pure THUMB mode, this is the preferred mode for code size. In this mode the execution speed is slower than the ARM mode. This mode is enabled when all the modules are compiled in THUMB mode, see the Makefiles.
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  • Interworking mode, when in the system there are ARM modules mixed with THUMB modules then the interworking compiler option is enabled. This is usually the slowest mode and the code size is not as good as in pure THUMB mode.
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-Mapping of the System States in the ARM7 port

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The ChibiOS/RT logical System States are mapped as follow in the ARM7 port:

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  • Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated, usually the CPU goes through several hardware states during the startup phase.
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  • Normal. This is the state the system has after executing chSysInit(). In this state the ARM7TDMI has both the interrupt sources (IRQ and FIQ) enabled and is running in ARM System Mode.
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  • Suspended. In this state the IRQ sources are disabled but the FIQ sources are served, the core is running in ARM System Mode.
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  • Disabled. Both the IRQ and FIQ sources are disabled, the core is running in ARM System Mode.
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  • Sleep. The ARM7 code does not have any built-in low power mode but there are clock stop modes implemented in custom ways by the various silicon vendors. This state is implemented in each microcontroller support code in a different way, the core is running (or freezed...) in ARM System Mode.
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  • S-Locked. IRQ sources disabled, core running in ARM System Mode.
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  • I-Locked. IRQ sources disabled, core running in ARM IRQ Mode. Note that this state is not different from the SRI state in this port, the chSysLockI() and chSysUnlockI() APIs do nothing (still use them in order to formally change state because this may change).
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  • Serving Regular Interrupt. IRQ sources disabled, core running in ARM IRQ Mode. See also the I-Locked state.
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  • Serving Fast Interrupt. IRQ and FIQ sources disabled, core running in ARM FIQ Mode.
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  • Serving Non-Maskable Interrupt. There are no asynchronous NMI sources in ARM7 architecture but synchronous SVC, ABT and UND exception handlers can be seen as belonging to this category.
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  • Halted. Implemented as an infinite loop after disabling both IRQ and FIQ sources. The ARM state is whatever the processor was running when chSysHalt() was invoked.
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-The ARM7 modes

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The ARM7 port makes some assumptions on the application code organization:

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  • Each thread has a private user/system stack, the system has a single interrupt stack where all the interrupts are processed.
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  • The threads are started in system mode.
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  • The threads code can run in system mode or user mode, however the code running in user mode cannot invoke the ChibiOS/RT APIs directly because privileged instructions are used inside.
    - The kernel APIs can be eventually invoked by using a SWI entry point that handles the switch in system mode and the return in user mode.
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  • Other modes are not preempt-able because the system code assumes the threads running in system mode. When running in supervisor or other modes make sure that the interrupts are globally disabled.
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  • Interrupts nesting is not supported in the ARM7 code because their implementation, even if possible, is not really efficient in this architecture.
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  • FIQ sources can preempt the kernel (by design) so it is not possible to invoke the kernel APIs from inside a FIQ handler. FIQ handlers are not affected by the kernel activity so there is not added jitter.
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-ARM7 Interrupt Handlers

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ARM7 Interrupt handlers do not save function-saved registers so you need to make sure your code saves them or does not use them (this happens because in the ARM7 port all the OS interrupt handler functions are declared naked).
- Function-trashed registers (R0-R3, R12, LR, SR) are saved/restored by the system macros CH_IRQ_PROLOGUE() and CH_IRQ_EPILOGUE().
- The easiest way to ensure this is to just invoke a normal function from within the interrupt handler, the function code will save all the required registers.
- Example:

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 CH_IRQ_HANDLER(irq_handler) {
-   CH_IRQ_PROLOGUE();
-
-   serve_interrupt();
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-   VICVectAddr = 0; // This is LPC214x-specific.
-   CH_IRQ_EPILOGUE();
- }
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This is not a bug but an implementation choice, this solution allows to have interrupt handlers compiled in thumb mode without have to use an interworking mode (the mode switch is hidden in the macros), this greatly improves code efficiency and size. You can look at the serial driver for real examples of interrupt handlers.
- It is important that the serve_interrupt() interrupt function is not inlined by the compiler into the ISR or the code could still modify the unsaved registers, this can be accomplished using GCC by adding the attribute "noinline" to the function:

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 #if defined(__GNUC__)
- __attribute__((noinline))
- #endif
- static void serve_interrupt(void) {
- }
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Note that several commercial compilers support a GNU-like functions attribute mechanism.
- Alternative ways are to use an appropriate pragma directive or disable inlining optimizations in the modules containing the interrupt handlers.

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-Modules

 Configuration Options
 

ARM7 specific configuration options.

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 Core Port Implementation
 

ARM7 specific port code, structures and macros.

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 Startup Support
 

ARM7 startup code support.

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 AT91SAM7 Support
 

AT91SAM7 specific support.

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 LPC214x Support
 

LPC214x specific support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Configuration Options
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ARM7 specific configuration options. -More...

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ARM7 specific configuration options.

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The ARM7 port allows some architecture-specific configurations settings that can be overridden by redefining them in chconf.h. Usually there is no need to change the default values.

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  • INT_REQUIRED_STACK, this value represent the amount of stack space used by an interrupt handler between the extctx and intctx structures.
    - In practice this value is the stack space used by the chSchDoReschedule() stack frame.
    - This value can be affected by a variety of external things like compiler version, compiler options, kernel settings (speed/size) and so on.
    - The default for this value is 0x10 which should be a safe value, you can trim this down by defining the macro externally. This would save some valuable RAM space for each thread present in the system.
    - The default value is set into ./os/ports/GCC/ARM7/chcore.h.
    • -
  • IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE thread. Usually there is no need to change this value unless inserting code in the IDLE thread hook macro.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines | -Typedefs | -Functions
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Core Port Implementation
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ARM7 specific port code, structures and macros. -More...

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Description

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ARM7 specific port code, structures and macros.

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-Defines

#define ENABLE_WFI_IDLE   0
 If enabled allows the idle thread to enter a low power mode.
#define CH_ARCHITECTURE_ARM7
 Macro defining the ARM7 architecture.
#define CH_ARCHITECTURE_NAME   "ARM"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "ARM7TDMI"
 Name of the architecture variant (optional).
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   4
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   0x10
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   __attribute__((naked)) void id(void)
 IRQ handler function declaration.
#define PORT_FAST_IRQ_HANDLER(id)   __attribute__((interrupt("FIQ"))) void id(void)
 Fast IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   asm volatile ("msr CPSR_c, #0x9F" : : : "memory")
 Kernel-lock action.
#define port_unlock()   asm volatile ("msr CPSR_c, #0x1F" : : : "memory")
 Kernel-unlock action.
#define port_lock_from_isr()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()
 Kernel-unlock action from an interrupt handler.
#define port_disable()
 Disables all the interrupt sources.
#define port_suspend()   asm volatile ("msr CPSR_c, #0x9F" : : : "memory")
 Disables the interrupt sources below kernel-level priority.
#define port_enable()   asm volatile ("msr CPSR_c, #0x1F" : : : "memory")
 Enables all the interrupt sources.
#define port_switch(ntp, otp)
 Performs a context switch between two threads.
#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef uint32_t stkalign_t
 32 bits stack and memory alignment enforcement.
typedef void * regarm_t
 Generic ARM register.
typedef int32_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint32_t tprio_t
typedef int32_t msg_t
typedef int32_t eventid_t
typedef uint32_t eventmask_t
typedef uint32_t systime_t
typedef int32_t cnt_t

-Functions

void port_halt (void)
void _port_thread_start (void)
 Start a thread by invoking its work function.
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Define Documentation

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#define ENABLE_WFI_IDLE   0
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If enabled allows the idle thread to enter a low power mode.

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Definition at line 42 of file ports/GCC/ARM7/chcore.h.

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#define CH_ARCHITECTURE_ARM7
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Macro defining the ARM7 architecture.

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Definition at line 49 of file ports/GCC/ARM7/chcore.h.

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Name of the implemented architecture.

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Definition at line 54 of file ports/GCC/ARM7/chcore.h.

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Name of the architecture variant (optional).

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Definition at line 59 of file ports/GCC/ARM7/chcore.h.

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#define SETUP_CONTEXT( workspace,
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{                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = pf;                                                   \
-  tp->p_ctx.r13->r5 = arg;                                                  \
-  tp->p_ctx.r13->lr = _port_thread_start;                                   \
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Platform dependent part of the chThdInit() API.

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This code usually setup the context switching frame represented by an intctx structure.

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Definition at line 127 of file ports/GCC/ARM7/chcore.h.

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Stack size for the system idle thread.

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This size depends on the idle thread implementation, usually the idle thread should take no more space than those reserved by INT_REQUIRED_STACK.

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Definition at line 145 of file ports/GCC/ARM7/chcore.h.

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Per-thread stack overhead for interrupts servicing.

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This constant is used in the calculation of the correct working area size. This value can be zero on those architecture where there is a separate interrupt stack and the stack space between intctx and extctx is known to be zero.

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Definition at line 159 of file ports/GCC/ARM7/chcore.h.

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#define STACK_ALIGN( n )    ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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Enforces a correct alignment for a stack area size value.

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Definition at line 165 of file ports/GCC/ARM7/chcore.h.

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#define THD_WA_SIZE( n ) 
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STACK_ALIGN(sizeof(Thread) +                         \
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Computes the thread working area global size.

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Definition at line 170 of file ports/GCC/ARM7/chcore.h.

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#define WORKING_AREA( s,
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Static working area allocation.

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This macro is used to allocate a static thread working area aligned as both position and size.

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Definition at line 180 of file ports/GCC/ARM7/chcore.h.

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#define PORT_IRQ_PROLOGUE( ) 
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{                                               \
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-}
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IRQ prologue code.

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This macro must be inserted at the start of all IRQ handlers enabled to invoke system APIs.

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Note:
This macro has a different implementation depending if compiled in ARM or THUMB mode.
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Definition at line 202 of file ports/GCC/ARM7/chcore.h.

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#define PORT_IRQ_EPILOGUE( ) 
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{                                               \
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IRQ epilogue code.

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This macro must be inserted at the end of all IRQ handlers enabled to invoke system APIs.

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Definition at line 220 of file ports/GCC/ARM7/chcore.h.

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#define PORT_IRQ_HANDLER( id )    __attribute__((naked)) void id(void)
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IRQ handler function declaration.

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Definition at line 230 of file ports/GCC/ARM7/chcore.h.

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#define PORT_FAST_IRQ_HANDLER( id )    __attribute__((interrupt("FIQ"))) void id(void)
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Fast IRQ handler function declaration.

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Definition at line 237 of file ports/GCC/ARM7/chcore.h.

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Port-related initialization code.

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Definition at line 244 of file ports/GCC/ARM7/chcore.h.

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#define port_lock( void )    asm volatile ("msr CPSR_c, #0x9F" : : : "memory")
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Kernel-lock action.

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Usually this function just disables interrupts but may perform more actions.

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Definition at line 258 of file ports/GCC/ARM7/chcore.h.

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#define port_unlock( void )    asm volatile ("msr CPSR_c, #0x1F" : : : "memory")
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Kernel-unlock action.

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Usually this function just disables interrupts but may perform more actions.

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Definition at line 272 of file ports/GCC/ARM7/chcore.h.

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#define port_lock_from_isr( void ) 
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Kernel-lock action from an interrupt handler.

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This function is invoked before invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.

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Definition at line 282 of file ports/GCC/ARM7/chcore.h.

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Kernel-unlock action from an interrupt handler.

-

This function is invoked after invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.

-
Note:
Empty in this port.
- -

Definition at line 291 of file ports/GCC/ARM7/chcore.h.

- -
-
- -
-
- - - - - - - - - -
#define port_disable( void ) 
-
-
-Value:
{                                                    \
-  asm volatile ("mrs     r3, CPSR                       \n\t"               \
-                "orr     r3, #0x80                      \n\t"               \
-                "msr     CPSR_c, r3                     \n\t"               \
-                "orr     r3, #0x40                      \n\t"               \
-                "msr     CPSR_c, r3" : : : "r3", "memory");                 \
-}
-
-

Disables all the interrupt sources.

-
Note:
Of course non maskable interrupt sources are not included.
-
-In this port it disables both the IRQ and FIQ sources.
-
-Implements a workaround for spurious interrupts taken from the NXP LPC214x datasheet.
- -

Definition at line 305 of file ports/GCC/ARM7/chcore.h.

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#define port_suspend( void )    asm volatile ("msr CPSR_c, #0x9F" : : : "memory")
-
-
- -

Disables the interrupt sources below kernel-level priority.

-
Note:
Interrupt sources above kernel level remains enabled.
-
-In this port it disables the IRQ sources and enables the FIQ sources.
- -

Definition at line 325 of file ports/GCC/ARM7/chcore.h.

- -
-
- -
-
- - - - - - - - - -
#define port_enable( void )    asm volatile ("msr CPSR_c, #0x1F" : : : "memory")
-
-
- -

Enables all the interrupt sources.

-
Note:
In this port it enables both the IRQ and FIQ sources.
- -

Definition at line 337 of file ports/GCC/ARM7/chcore.h.

- -
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-
- - - - - - - - - - - - - - - - - - -
#define port_switch( ntp,
 otp 
)
-
-
-Value:
{                                             \
-  register Thread *_ntp asm ("r0") = (ntp);                                 \
-  register Thread *_otp asm ("r1") = (otp);                                 \
-  register char *sp asm ("sp");                                             \
-  if (sp - sizeof(struct intctx) - sizeof(Thread) < (char *)_otp)           \
-    asm volatile ("mov     r0, #0                               \n\t"       \
-                  "b       chDbgPanic");                                    \
-  _port_switch_arm(_ntp, _otp);                                             \
-}
-
-

Performs a context switch between two threads.

-

This is the most critical code in any port, this function is responsible for the context switch between 2 threads.

-
Note:
The implementation of this code affects directly the context switch performance so optimize here as much as you can.
-
-Implemented as inlined code for performance reasons.
-
Parameters:
- - - -
[in] ntp the thread to be switched in
[in] otp the thread to be switched out
-
-
- -

Definition at line 368 of file ports/GCC/ARM7/chcore.h.

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#define INLINE   inline
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- -

Inline function modifier.

- -

Definition at line 61 of file ports/GCC/ARM7/chtypes.h.

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#define ROMCONST   const
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- -

ROM constant modifier.

-
Note:
It is set to use the "const" keyword in this port.
- -

Definition at line 67 of file ports/GCC/ARM7/chtypes.h.

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#define PACK_STRUCT_STRUCT   __attribute__((packed))
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Packed structure modifier (within).

-
Note:
It uses the "packed" GCC attribute.
- -

Definition at line 73 of file ports/GCC/ARM7/chtypes.h.

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#define PACK_STRUCT_BEGIN
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Packed structure modifier (before).

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Note:
Empty in this port.
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Definition at line 79 of file ports/GCC/ARM7/chtypes.h.

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#define PACK_STRUCT_END
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Packed structure modifier (after).

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Note:
Empty in this port.
- -

Definition at line 85 of file ports/GCC/ARM7/chtypes.h.

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Typedef Documentation

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typedef uint32_t stkalign_t
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32 bits stack and memory alignment enforcement.

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Definition at line 64 of file ports/GCC/ARM7/chcore.h.

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typedef void* regarm_t
-
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Generic ARM register.

- -

Definition at line 69 of file ports/GCC/ARM7/chcore.h.

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typedef int32_t bool_t
-
-
-

Fast boolean type.

- -

Definition at line 47 of file ports/GCC/ARM7/chtypes.h.

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typedef uint8_t tmode_t
-
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Thread flags.

- -

Definition at line 48 of file ports/GCC/ARM7/chtypes.h.

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typedef uint8_t tstate_t
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Thread state.

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Definition at line 49 of file ports/GCC/ARM7/chtypes.h.

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typedef uint8_t trefs_t
-
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Thread references counter.

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Definition at line 50 of file ports/GCC/ARM7/chtypes.h.

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typedef uint32_t tprio_t
-
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Thread priority.

- -

Definition at line 51 of file ports/GCC/ARM7/chtypes.h.

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typedef int32_t msg_t
-
-
-

Inter-thread message.

- -

Definition at line 52 of file ports/GCC/ARM7/chtypes.h.

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typedef int32_t eventid_t
-
-
-

Event Id.

- -

Definition at line 53 of file ports/GCC/ARM7/chtypes.h.

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typedef uint32_t eventmask_t
-
-
-

Events mask.

- -

Definition at line 54 of file ports/GCC/ARM7/chtypes.h.

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typedef uint32_t systime_t
-
-
-

System time.

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Definition at line 55 of file ports/GCC/ARM7/chtypes.h.

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typedef int32_t cnt_t
-
-
-

Resources counter.

- -

Definition at line 56 of file ports/GCC/ARM7/chtypes.h.

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Function Documentation

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void port_halt (void  ) 
-
-
-

Halts the system.

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void _port_thread_start (void  ) 
-
-
- -

Start a thread by invoking its work function.

-

If the work function returns chThdExit() is automatically invoked.

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-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/group___a_r_m7___c_o_r_e.png b/ChibiOS_2.0.8/docs/html/group___a_r_m7___c_o_r_e.png deleted file mode 100644 index 30111eb..0000000 Binary files a/ChibiOS_2.0.8/docs/html/group___a_r_m7___c_o_r_e.png and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/group___a_r_m7___s_t_a_r_t_u_p.html b/ChibiOS_2.0.8/docs/html/group___a_r_m7___s_t_a_r_t_u_p.html deleted file mode 100644 index 26556cd..0000000 --- a/ChibiOS_2.0.8/docs/html/group___a_r_m7___s_t_a_r_t_u_p.html +++ /dev/null @@ -1,86 +0,0 @@ - - -ChibiOS/RT: Startup Support - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Startup Support
- -[ARM7TDMI] -

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- -

ARM7 startup code support. -More...

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-Collaboration diagram for Startup Support:
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ARM7 startup code support.

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ChibiOS/RT provides its own generic startup file for the ARM7 port. Of course it is not mandatory to use it but care should be taken about the startup phase details.

-

Startup Process

-

The startup process, as implemented, is the following:

-
    -
  1. The stacks are initialized by assigning them the sizes defined in the linker script (usually named ch.ld). Stack areas are allocated from the highest RAM location downward.
    2. -
  2. The ARM state is switched to System with both IRQ and FIQ sources disabled.
    3. -
  3. An early initialization routine hwinit0 is invoked, if the symbol is not defined then an empty default routine is executed (weak symbol).
    4. -
  4. DATA and BSS segments are initialized.
    5. -
  5. A late initialization routine hwinit1 is invoked, if the symbol not defined then an empty default routine is executed (weak symbol).
    - This late initialization function is also the proper place for a bootloader, if your application requires one.
    6. -
  6. The main() function is invoked with the parameters argc and argv set to zero.
    7. -
  7. Should the main() function return a branch is performed to the weak symbol MainExitHandler. The default code is an endless empty loop.
    8. -
-

Expected linker symbols

-

The startup code starts at the symbol ResetHandler and expects the following symbols to be defined in the linker script:

-
    -
  • __ram_end__ RAM end location +1.
    • -
  • __und_stack_size__ Undefined Instruction stack size.
    • -
  • __abt_stack_size__ Memory Abort stack size.
    • -
  • __fiq_stack_size__ FIQ service stack size.
    • -
  • __irq_stack_size__ IRQ service stack size.
    • -
  • __svc_stack_size__ SVC service stack size.
    • -
  • __sys_stack_size__ System/User stack size. This is the stack area used by the main() function.
    • -
  • _textdata address of the data segment source read only data.
    • -
  • _data data segment start location.
    • -
  • _edata data segment end location +1.
    • -
  • _bss_start BSS start location.
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  • _bss_end BSS end location +1.
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-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/group___a_r_m7___s_t_a_r_t_u_p.png b/ChibiOS_2.0.8/docs/html/group___a_r_m7___s_t_a_r_t_u_p.png deleted file mode 100644 index c069fc5..0000000 Binary files a/ChibiOS_2.0.8/docs/html/group___a_r_m7___s_t_a_r_t_u_p.png and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/group___a_r_m_c_mx.html b/ChibiOS_2.0.8/docs/html/group___a_r_m_c_mx.html deleted file mode 100644 index c8c6333..0000000 --- a/ChibiOS_2.0.8/docs/html/group___a_r_m_c_mx.html +++ /dev/null @@ -1,137 +0,0 @@ - - -ChibiOS/RT: ARM Cortex-Mx - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Modules
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ARM Cortex-Mx
- -[Ports] -

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-Collaboration diagram for ARM Cortex-Mx:
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Description

-

This port supports the ARMv6-M and ARMv7-M architectures (all the Cortex-Mx cores).

-

-System logical states in ARMv6-M

-
    -
  • Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated.
    • -
  • Normal. This is the state the system has after executing chSysInit(). In this state interrupts are enabled. The processor is running in thread-privileged mode.
    • -
  • Suspended. In this state the interrupt sources are globally disabled. The processor is running in thread-privileged mode. In this mode this state is not different from the Disabled state.
    • -
  • Disabled. In this state the interrupt sources are globally disabled. The processor is running in thread-privileged mode. In this mode this state is not different from the Suspended state.
    • -
  • Sleep. This state is entered with the execution of the specific instruction wfi.
    • -
  • S-Locked. In this state the interrupt sources are globally disabled. The processor is running in thread-privileged mode.
    • -
  • I-Locked. In this state the interrupt sources are globally disabled. The processor is running in exception-privileged mode.
    • -
  • Serving Regular Interrupt. In this state the interrupt sources are not globally masked but only interrupts with higher priority can preempt the current handler. The processor is running in exception-privileged mode.
    • -
  • Serving Fast Interrupt. This state is not implemented in the ARMv6-M implementation.
    • -
  • Serving Non-Maskable Interrupt. The Cortex-M3 has a specific asynchronous NMI vector and several synchronous fault vectors that can be considered belonging to this category.
    • -
  • Halted. Implemented as an infinite loop after globally masking all the maskable interrupt sources. The ARM state is whatever the processor was running when chSysHalt() was invoked.
    • -
-

-System logical states in ARMv7-M

-

The ChibiOS/RT logical System States are mapped as follow in the ARM Cortex-M3 port:

-
    -
  • Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated.
    • -
  • Normal. This is the state the system has after executing chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register set at CORTEX_BASEPRI_USER level, interrupts are not masked. The processor is running in thread-privileged mode.
    • -
  • Suspended. In this state the interrupt sources are not globally masked but the BASEPRI register is set to CORTEX_BASEPRI_KERNEL thus masking any interrupt source with lower or equal priority. The processor is running in thread-privileged mode.
    • -
  • Disabled. Interrupt sources are globally masked. The processor is running in thread-privileged mode.
    • -
  • Sleep. This state is entered with the execution of the specific instruction wfi.
    • -
  • S-Locked. In this state the interrupt sources are not globally masked but the BASEPRI register is set to CORTEX_BASEPRI_KERNEL thus masking any interrupt source with lower or equal priority. The processor is running in thread-privileged mode.
    • -
  • I-Locked. In this state the interrupt sources are not globally masked but the BASEPRI register is set to CORTEX_BASEPRI_KERNEL thus masking any interrupt source with lower or equal priority. The processor is running in exception-privileged mode.
    • -
  • Serving Regular Interrupt. In this state the interrupt sources are not globally masked but only interrupts with higher priority can preempt the current handler. The processor is running in exception-privileged mode.
    • -
  • Serving Fast Interrupt. It is basically the same of the SRI state but it is not possible to switch to the I-Locked state because fast interrupts can preempt the kernel critical zone.
    • -
  • Serving Non-Maskable Interrupt. The Cortex-M3 has a specific asynchronous NMI vector and several synchronous fault vectors that can be considered belonging to this category.
    • -
  • Halted. Implemented as an infinite loop after globally masking all the maskable interrupt sources. The ARM state is whatever the processor was running when chSysHalt() was invoked.
    • -
-

-The ARM Cortex-Mx port notes

-

The ARM Cortex-Mx port is organized as follow:

-
    -
  • The main() function is invoked in thread-privileged mode.
    • -
  • Each thread has a private process stack, the system has a single main stack where all the interrupts and exceptions are processed.
    • -
  • The threads are started in thread-privileged mode.
    • -
  • Interrupt nesting and the other advanced core/NVIC features are supported.
    • -
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-Modules

 Configuration Options
 

ARM Cortex-Mx Configuration Options.

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 Core Port Implementation
 

ARM Cortex-Mx specific port code, structures and macros.

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 Startup Support
 

ARM Cortex-Mx startup code support.

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 NVIC Support
 

ARM Cortex-Mx NVIC support.

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 STM32F10x Specific Parameters
 LPC11xx Specific Parameters
 LPC13xx Specific Parameters
 LPC11xx Support
 

LPC11xx specific support.

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 LPC13xx Support
 

LPC13xx specific support.

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 STM32 Support
 

STM32 specific support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Configuration Options
- -[ARM Cortex-Mx] -

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ARM Cortex-Mx Configuration Options. -More...

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ARM Cortex-Mx Configuration Options.

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The ARMCMx port allows some architecture-specific configurations settings that can be overridden by redefining them in chconf.h. Usually there is no need to change the default values.

-
    -
  • INT_REQUIRED_STACK, this value represent the amount of stack space used by an interrupt handler between the extctx and intctx structures.
    - In the current implementation this value is guaranteed to be zero so there is no need to modify this value unless changes are done at the interrupts handling code.
    • -
  • IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE thread. Usually there is no need to change this value unless inserting code in the IDLE thread hook macro.
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  • CORTEX_BASEPRI_KERNEL, this is the BASEPRI value for the kernel lock code. Code running at higher priority levels must not invoke any OS API. This setting is specific to the ARMv7-M architecture.
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  • CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
    • -
  • CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
    • -
  • CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
    • -
  • CORTEX_ENABLE_WFI_IDLE, if set to TRUE enables the use of the wfi instruction from within the idle loop. This is defaulted to FALSE because it can create problems with some debuggers. Setting this option to TRUE reduces the system power requirements.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Modules | -Defines | -Typedefs | -Functions
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Core Port Implementation
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ARM Cortex-Mx specific port code, structures and macros. -More...

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Description

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ARM Cortex-Mx specific port code, structures and macros.

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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 ARMv6-M Specific Implementation
 

ARMv6-M specific port code, structures and macros.

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 ARMv7-M Specific Implementation
 

ARMv7-M specific port code, structures and macros.

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-Defines

#define CORTEX_M0   0
 Cortex-M0 variant.
#define CORTEX_M1   1
 Cortex-M1 variant.
#define CORTEX_M3   3
 Cortex-M3 variant.
#define CORTEX_M4   4
 Cortex-M4 variant.
#define CORTEX_PRIORITY_LEVELS   (1 << CORTEX_PRIORITY_BITS)
 Total priority levels.
#define CORTEX_MINIMUM_PRIORITY   (CORTEX_PRIORITY_LEVELS - 1)
 Minimum priority level.
#define CORTEX_MAXIMUM_PRIORITY   0
 Maximum priority level.
#define CORTEX_BASEPRI_DISABLED   0
 Disabled value for BASEPRI register.
#define CORTEX_IS_VALID_PRIORITY(n)   (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
 Priority level verification macro.
#define CORTEX_PRIORITY_MASK(n)   ((n) << (8 - CORTEX_PRIORITY_BITS))
 Priority level to priority mask conversion macro.
#define CORTEX_ENABLE_WFI_IDLE   FALSE
 Enables the use of the WFI instruction in the idle thread loop.
#define CORTEX_PRIORITY_SYSTICK   (CORTEX_PRIORITY_LEVELS >> 1)
 SYSTICK handler priority.
#define CORTEX_PRIORITY_SVCALL   (CORTEX_MAXIMUM_PRIORITY + 1)
 SVCALL handler priority.
#define CORTEX_PRIORITY_PENDSV   CORTEX_MINIMUM_PRIORITY
 PENDSV handler priority.
#define CORTEX_BASEPRI_KERNEL   CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
 BASEPRI level within kernel lock.
#define CORTEX_STACK_ALIGNMENT   64
 Stack alignment enforcement.
#define CH_ARCHITECTURE_ARM
 Macro defining a generic ARM architecture.
#define CH_ARCHITECTURE_ARM_vxm
 Macro defining the specific ARM architecture.
#define CH_ARCHITECTURE_NAME   "ARMvx-M"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "Cortex-Mx"
 Name of the architecture variant (optional).
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef uint64_t stkalign_t __attribute__ ((aligned(8)))
 Stack and memory alignment enforcement.
typedef void * regarm_t
 Generic ARM register.
typedef int32_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint32_t tprio_t
typedef int32_t msg_t
typedef int32_t eventid_t
typedef uint32_t eventmask_t
typedef uint32_t systime_t
typedef int32_t cnt_t

-Functions

void port_halt (void)
 Halts the system.
-

Define Documentation

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#define CORTEX_M0   0
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Cortex-M0 variant.

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Definition at line 44 of file ports/GCC/ARMCMx/chcore.h.

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Cortex-M1 variant.

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Definition at line 45 of file ports/GCC/ARMCMx/chcore.h.

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Cortex-M3 variant.

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Definition at line 46 of file ports/GCC/ARMCMx/chcore.h.

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Definition at line 47 of file ports/GCC/ARMCMx/chcore.h.

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Total priority levels.

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Definition at line 67 of file ports/GCC/ARMCMx/chcore.h.

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Minimum priority level.

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This minimum priority level is calculated from the number of priority bits supported by the specific Cortex-Mx implementation.

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Definition at line 74 of file ports/GCC/ARMCMx/chcore.h.

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Maximum priority level.

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The maximum allowed priority level is always zero.

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Definition at line 80 of file ports/GCC/ARMCMx/chcore.h.

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Disabled value for BASEPRI register.

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Definition at line 86 of file ports/GCC/ARMCMx/chcore.h.

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Priority level verification macro.

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Definition at line 95 of file ports/GCC/ARMCMx/chcore.h.

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Priority level to priority mask conversion macro.

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Definition at line 101 of file ports/GCC/ARMCMx/chcore.h.

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Enables the use of the WFI instruction in the idle thread loop.

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Definition at line 111 of file ports/GCC/ARMCMx/chcore.h.

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SYSTICK handler priority.

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Definition at line 120 of file ports/GCC/ARMCMx/chcore.h.

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SVCALL handler priority.

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Definition at line 138 of file ports/GCC/ARMCMx/chcore.h.

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PENDSV handler priority.

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BASEPRI level within kernel lock.

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Definition at line 171 of file ports/GCC/ARMCMx/chcore.h.

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Stack alignment enforcement.

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Macro defining the specific ARM architecture.

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Name of the implemented architecture.

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Name of the architecture variant (optional).

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Definition at line 208 of file ports/GCC/ARMCMx/chcore.h.

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#define STACK_ALIGN( n )    ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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Enforces a correct alignment for a stack area size value.

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Computes the thread working area global size.

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 n 
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Static working area allocation.

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This macro is used to allocate a static thread working area aligned as both position and size.

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Definition at line 276 of file ports/GCC/ARMCMx/chcore.h.

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Inline function modifier.

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ROM constant modifier.

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It is set to use the "const" keyword in this port.
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Definition at line 65 of file ports/GCC/ARMCMx/chtypes.h.

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#define PACK_STRUCT_STRUCT   __attribute__((packed))
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Packed structure modifier (within).

-
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It uses the "packed" GCC attribute.
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Definition at line 71 of file ports/GCC/ARMCMx/chtypes.h.

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Packed structure modifier (before).

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Empty in this port.
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Definition at line 77 of file ports/GCC/ARMCMx/chtypes.h.

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Packed structure modifier (after).

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Empty in this port.
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Definition at line 83 of file ports/GCC/ARMCMx/chtypes.h.

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Typedef Documentation

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typedef uint64_t stkalign_t __attribute__((aligned(8)))
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Stack and memory alignment enforcement.

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Definition at line 235 of file ports/GCC/ARMCMx/chcore.h.

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Generic ARM register.

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Definition at line 245 of file ports/GCC/ARMCMx/chcore.h.

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Fast boolean type.

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Definition at line 45 of file ports/GCC/ARMCMx/chtypes.h.

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Thread flags.

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Definition at line 46 of file ports/GCC/ARMCMx/chtypes.h.

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Thread state.

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Definition at line 47 of file ports/GCC/ARMCMx/chtypes.h.

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Thread references counter.

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Definition at line 48 of file ports/GCC/ARMCMx/chtypes.h.

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typedef uint32_t tprio_t
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Thread priority.

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Definition at line 49 of file ports/GCC/ARMCMx/chtypes.h.

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typedef int32_t msg_t
-
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Inter-thread message.

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Definition at line 50 of file ports/GCC/ARMCMx/chtypes.h.

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Event Id.

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Definition at line 51 of file ports/GCC/ARMCMx/chtypes.h.

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Events mask.

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Definition at line 52 of file ports/GCC/ARMCMx/chtypes.h.

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System time.

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Definition at line 53 of file ports/GCC/ARMCMx/chtypes.h.

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Resources counter.

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Definition at line 54 of file ports/GCC/ARMCMx/chtypes.h.

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Function Documentation

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void port_halt (void  ) 
-
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Halts the system.

-
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The function is declared as a weak symbol, it is possible to redefine it in your application code.
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Definition at line 45 of file ports/GCC/ARMCMx/chcore.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines
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LPC11xx Specific Parameters
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-Collaboration diagram for LPC11xx Specific Parameters:
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Description

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This file contains the Cortex-M0 specific parameters for the LPC11xx platform.

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-Defines

#define CORTEX_MODEL   CORTEX_M0
 Cortex core model.
#define CORTEX_HAS_ST   TRUE
 Systick unit presence.
#define CORTEX_HAS_MPU   FALSE
 Memory Protection unit presence.
#define CORTEX_PRIORITY_BITS   2
 Number of bits in priority masks.
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Define Documentation

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#define CORTEX_MODEL   CORTEX_M0
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Cortex core model.

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Definition at line 44 of file LPC11xx/cmparams.h.

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Systick unit presence.

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Memory Protection unit presence.

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Number of bits in priority masks.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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LPC13xx Specific Parameters
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-Collaboration diagram for LPC13xx Specific Parameters:
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Description

-

This file contains the Cortex-M3 specific parameters for the LPC13xx platform.

- - - - - - - - - - -

-Defines

#define CORTEX_MODEL   CORTEX_M3
 Cortex core model.
#define CORTEX_HAS_ST   TRUE
 Systick unit presence.
#define CORTEX_HAS_MPU   FALSE
 Memory Protection unit presence.
#define CORTEX_PRIORITY_BITS   3
 Number of bits in priority masks.
-

Define Documentation

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#define CORTEX_MODEL   CORTEX_M3
-
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Cortex core model.

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Definition at line 44 of file LPC13xx/cmparams.h.

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Systick unit presence.

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Memory Protection unit presence.

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Definition at line 54 of file LPC13xx/cmparams.h.

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Number of bits in priority masks.

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Definition at line 59 of file LPC13xx/cmparams.h.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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- - -
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-Data Structures | -Defines | -Typedefs | -Functions
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NVIC Support
- -[ARM Cortex-Mx] -

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ARM Cortex-Mx NVIC support. -More...

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Description

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ARM Cortex-Mx NVIC support.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-Data Structures

struct  CM3_ST
 Structure representing the SYSTICK I/O space. More...
struct  CM3_NVIC
 Structure representing the NVIC I/O space. More...
struct  CM3_SCB
 Structure representing the System Control Block I/O space. More...

-Defines

#define HANDLER_MEM_MANAGE   0
#define HANDLER_BUS_FAULT   1
#define HANDLER_USAGE_FAULT   2
#define HANDLER_SVCALL   7
#define HANDLER_DEBUG_MONITOR   8
#define HANDLER_PENDSV   10
#define HANDLER_SYSTICK   11
#define NVIC_ITCR   (*((IOREG32 *)0xE000E004))
 NVIC ITCR register.
#define NVIC_STIR   (*((IOREG32 *)0xE000EF00))
 NVIC STIR register.
#define STBase   ((CM3_ST *)0xE000E010)
 SYSTICK peripheral base address.
#define NVICBase   ((CM3_NVIC *)0xE000E100)
 NVIC peripheral base address.
#define SCBBase   ((CM3_SCB *)0xE000ED00)
 SCB peripheral base address.

-Typedefs

typedef volatile uint8_t IOREG8
typedef volatile uint32_t IOREG32

-Functions

void NVICEnableVector (uint32_t n, uint32_t prio)
 Sets the priority of an interrupt handler and enables it.
void NVICDisableVector (uint32_t n)
 Disables an interrupt handler.
void NVICSetSystemHandlerPriority (uint32_t handler, uint32_t prio)
 Changes the priority of a system handler.
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Define Documentation

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#define HANDLER_MEM_MANAGE   0
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MEM MANAGE vector id.

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Definition at line 41 of file nvic.h.

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BUS FAULT vector id.

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Definition at line 42 of file nvic.h.

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#define HANDLER_USAGE_FAULT   2
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USAGE FAULT vector id.

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Definition at line 43 of file nvic.h.

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#define HANDLER_SVCALL   7
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SVCALL vector id.

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Definition at line 48 of file nvic.h.

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#define HANDLER_DEBUG_MONITOR   8
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DEBUG MONITOR vector id.

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Definition at line 49 of file nvic.h.

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#define HANDLER_PENDSV   10
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PENDSV vector id.

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Definition at line 51 of file nvic.h.

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#define HANDLER_SYSTICK   11
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SYS TCK vector id.

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Definition at line 52 of file nvic.h.

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#define NVIC_ITCR   (*((IOREG32 *)0xE000E004))
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NVIC ITCR register.

- -

Definition at line 60 of file nvic.h.

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#define NVIC_STIR   (*((IOREG32 *)0xE000EF00))
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NVIC STIR register.

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Definition at line 65 of file nvic.h.

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#define STBase   ((CM3_ST *)0xE000E010)
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SYSTICK peripheral base address.

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Definition at line 80 of file nvic.h.

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#define NVICBase   ((CM3_NVIC *)0xE000E100)
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NVIC peripheral base address.

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Definition at line 125 of file nvic.h.

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SCB peripheral base address.

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Definition at line 156 of file nvic.h.

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Typedef Documentation

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typedef volatile uint8_t IOREG8
-
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8 bits I/O register type.

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Definition at line 54 of file nvic.h.

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typedef volatile uint32_t IOREG32
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32 bits I/O register type.

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Definition at line 55 of file nvic.h.

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Function Documentation

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void NVICEnableVector (uint32_t  n,
uint32_t  prio 
)
-
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Sets the priority of an interrupt handler and enables it.

-
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- - - -
n the interrupt number
prio the interrupt priority mask
-
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Note:
The parameters are not tested for correctness.
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Referenced by pwm_lld_start().

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void NVICDisableVector (uint32_t  n ) 
-
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Disables an interrupt handler.

-
Parameters:
- - -
n the interrupt number
-
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Note:
The parameters are not tested for correctness.
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Referenced by pwm_lld_stop().

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void NVICSetSystemHandlerPriority (uint32_t  handler,
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Changes the priority of a system handler.

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handler the system handler number
prio the system handler priority mask
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The parameters are not tested for correctness.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Startup Support
- -[ARM Cortex-Mx] -

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ARM Cortex-Mx startup code support. -More...

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ARM Cortex-Mx startup code support.

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ChibiOS/RT provides its own generic startup file for the ARM Cortex-Mx port. Of course it is not mandatory to use it but care should be taken about the startup phase details.

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Startup Process

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The startup process, as implemented, is the following:

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  1. Interrupts are masked globally.
    2. -
  2. The two stacks are initialized by assigning them the sizes defined in the linker script (usually named ch.ld). Stack areas are allocated from the highest RAM location downward.
    3. -
  3. An early initialization routine hwinit0 is invoked, if the symbol is not defined then an empty default routine is executed (weak symbol).
    4. -
  4. DATA and BSS segments are initialized.
    5. -
  5. The CPU state is switched to Privileged and the PSP stack is used.
    6. -
  6. A late initialization routine hwinit1 is invoked, if the symbol not defined then an empty default routine is executed (weak symbol).
    - This late initialization function is also the proper place for a bootloader, if your application requires one.
    7. -
  7. The main() function is invoked with the parameters argc and argv set to zero.
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  8. Should the main() function return a branch is performed to the weak symbol MainExitHandler. The default code is an endless empty loop.
    9. -
-

Expected linker symbols

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The startup code starts at the symbol ResetHandler and expects the following symbols to be defined in the linker script:

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  • __ram_end__ RAM end location +1.
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  • __main_stack_size__ Exception stack size.
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  • __process_stack_size__ Process stack size. This is the stack area used by the main() function.
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  • _textdata address of the data segment source read only data.
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  • _data data segment start location.
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  • _edata data segment end location +1.
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  • _bss_start BSS start location.
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  • _bss_end BSS end location +1.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM32F10x Specific Parameters
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Description

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This file contains the Cortex-M3 specific parameters for the STM32F10x platform.

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-Defines

#define CORTEX_MODEL   CORTEX_M3
 Cortex core model.
#define CORTEX_HAS_ST   TRUE
 Systick unit presence.
#define CORTEX_HAS_MPU   FALSE
 Memory Protection unit presence.
#define CORTEX_PRIORITY_BITS   4
 Number of bits in priority masks.
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Define Documentation

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#define CORTEX_MODEL   CORTEX_M3
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Cortex core model.

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Definition at line 44 of file STM32F10x/cmparams.h.

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Systick unit presence.

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Definition at line 49 of file STM32F10x/cmparams.h.

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#define CORTEX_HAS_MPU   FALSE
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Memory Protection unit presence.

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Definition at line 54 of file STM32F10x/cmparams.h.

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#define CORTEX_PRIORITY_BITS   4
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Number of bits in priority masks.

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Definition at line 59 of file STM32F10x/cmparams.h.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Functions | -Variables
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ARMv6-M Specific Implementation
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ARMv6-M specific port code, structures and macros. -More...

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-Collaboration diagram for ARMv6-M Specific Implementation:
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Description

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ARMv6-M specific port code, structures and macros.

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-Data Structures

struct  cmxctx
 Cortex-Mx exception context. More...

-Defines

#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   8
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   16
 Per-thread stack overhead for interrupts servicing.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void id(void)
 IRQ handler function declaration.
#define PORT_FAST_IRQ_HANDLER(id)   void id(void)
 Fast IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   asm volatile ("cpsid i" : : : "memory")
 Kernel-lock action.
#define port_unlock()   asm volatile ("cpsie i" : : : "memory")
 Kernel-unlock action.
#define port_lock_from_isr()   port_lock()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()   port_unlock()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   asm volatile ("cpsid i" : : : "memory")
 Disables all the interrupt sources.
#define port_suspend()   asm volatile ("cpsid i" : : : "memory")
 Disables the interrupt sources below kernel-level priority.
#define port_enable()   asm volatile ("cpsie i" : : : "memory")
 Enables all the interrupt sources.
#define port_wait_for_interrupt()   asm volatile ("wfi" : : : "memory")
 Enters an architecture-dependent IRQ-waiting mode.

-Functions

 CH_IRQ_HANDLER (SysTickVector)
 System Timer vector.
void _port_switch_from_irq (void)
 Post-IRQ switch code.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Start a thread by invoking its work function.
void port_halt (void)
 Halts the system.

-Variables

regarm_t _port_saved_pc
 PC register temporary storage.
unsigned _port_irq_nesting
 IRQ nesting counter.
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Define Documentation

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#define SETUP_CONTEXT( workspace,
 wsize,
 pf,
 arg 
)
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{                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = pf;                                                   \
-  tp->p_ctx.r13->r5 = arg;                                                  \
-  tp->p_ctx.r13->lr = _port_thread_start;                                   \
-}
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Platform dependent part of the chThdInit() API.

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This code usually setup the context switching frame represented by an intctx structure.

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Definition at line 98 of file chcore_v6m.h.

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#define IDLE_THREAD_STACK_SIZE   8
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Stack size for the system idle thread.

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This size depends on the idle thread implementation, usually the idle thread should take no more space than those reserved by INT_REQUIRED_STACK.

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In this port it is set to 8 because the idle thread does have a stack frame when compiling without optimizations. You may reduce this value to zero when compiling with optimizations.
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Definition at line 117 of file chcore_v6m.h.

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#define INT_REQUIRED_STACK   16
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Per-thread stack overhead for interrupts servicing.

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This constant is used in the calculation of the correct working area size. This value can be zero on those architecture where there is a separate interrupt stack and the stack space between intctx and extctx is known to be zero.

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In this port it is conservatively set to 16 because the function chSchDoRescheduleI() can have a stack frame, expecially with compiler optimizations disabled.
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Definition at line 132 of file chcore_v6m.h.

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#define PORT_IRQ_PROLOGUE( ) 
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{                                               \
-  port_lock_from_isr();                                                     \
-  _port_irq_nesting++;                                                      \
-  port_unlock_from_isr();                                                   \
-}
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IRQ prologue code.

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This macro must be inserted at the start of all IRQ handlers enabled to invoke system APIs.

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Definition at line 140 of file chcore_v6m.h.

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#define PORT_IRQ_EPILOGUE( ) 
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{                                               \
-  port_lock_from_isr();                                                     \
-  if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) {             \
-    register struct cmxctx *ctxp;                                           \
-                                                                            \
-    asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : );                      \
-    _port_saved_pc = ctxp->pc;                                              \
-    ctxp->pc = _port_switch_from_irq;                                       \
-    return;                                                                 \
-  }                                                                         \
-  port_unlock_from_isr();                                                   \
-}
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IRQ epilogue code.

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This macro must be inserted at the end of all IRQ handlers enabled to invoke system APIs.

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Definition at line 151 of file chcore_v6m.h.

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#define PORT_IRQ_HANDLER( id )    void id(void)
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IRQ handler function declaration.

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Definition at line 169 of file chcore_v6m.h.

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#define PORT_FAST_IRQ_HANDLER( id )    void id(void)
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Fast IRQ handler function declaration.

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Definition at line 176 of file chcore_v6m.h.

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#define port_init( void ) 
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{                                                       \
-  _port_irq_nesting = 0;                                                    \
-  SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \
-  NVICSetSystemHandlerPriority(HANDLER_SYSTICK,                             \
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \
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Port-related initialization code.

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Definition at line 181 of file chcore_v6m.h.

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#define port_lock( void )    asm volatile ("cpsid i" : : : "memory")
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Kernel-lock action.

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Usually this function just disables interrupts but may perform more actions.

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Definition at line 193 of file chcore_v6m.h.

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#define port_unlock( void )    asm volatile ("cpsie i" : : : "memory")
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Kernel-unlock action.

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Usually this function just disables interrupts but may perform more actions.

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Definition at line 200 of file chcore_v6m.h.

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#define port_lock_from_isr( void )    port_lock()
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Kernel-lock action from an interrupt handler.

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This function is invoked before invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.

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Definition at line 209 of file chcore_v6m.h.

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#define port_unlock_from_isr( void )    port_unlock()
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Kernel-unlock action from an interrupt handler.

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This function is invoked after invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.

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Definition at line 218 of file chcore_v6m.h.

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#define port_disable( void )    asm volatile ("cpsid i" : : : "memory")
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Disables all the interrupt sources.

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Definition at line 223 of file chcore_v6m.h.

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#define port_suspend( void )    asm volatile ("cpsid i" : : : "memory")
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Definition at line 228 of file chcore_v6m.h.

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#define port_enable( void )    asm volatile ("cpsie i" : : : "memory")
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Enables all the interrupt sources.

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Definition at line 233 of file chcore_v6m.h.

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The function is meant to return when an interrupt becomes pending. The simplest implementation is an empty function or macro but this would not take advantage of architecture-specific power saving modes.

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Definition at line 244 of file chcore_v6m.h.

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Function Documentation

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CH_IRQ_HANDLER (SysTickVector  ) 
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System Timer vector.

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This interrupt is used as system tick.

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The timer must be initialized in the startup code.
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Definition at line 52 of file chcore_v6m.c.

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References CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, chSysLockFromIsr, chSysTimerHandlerI(), and chSysUnlockFromIsr.

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void _port_switch_from_irq (void  ) 
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Post-IRQ switch code.

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void port_switch (Thread *  ntp,
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Start a thread by invoking its work function.

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void port_halt (void  ) 
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Halts the system.

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This function is invoked by the operating system when an unrecoverable error is detected (as example because a programming error in the application code that triggers an assertion while in debug mode).

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This function is invoked by the operating system when an unrecoverable error is detected (as example because a programming error in the application code that triggers an assertion while in debug mode).

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Definition at line 45 of file ports/GCC/ARMCMx/chcore.c.

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Variable Documentation

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PC register temporary storage.

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Definition at line 40 of file chcore_v6m.c.

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IRQ nesting counter.

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Definition at line 45 of file chcore_v6m.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-Defines | -Functions
-
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ARMv7-M Specific Implementation
- -[Core Port Implementation] -

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ARMv7-M specific port code, structures and macros. -More...

- -

-Collaboration diagram for ARMv7-M Specific Implementation:
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ARMv7-M specific port code, structures and macros.

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-Defines

#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   8
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   16
 Per-thread stack overhead for interrupts servicing.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()   _port_irq_epilogue()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void id(void)
 IRQ handler function declaration.
#define PORT_FAST_IRQ_HANDLER(id)   void id(void)
 Fast IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()
 Kernel-lock action.
#define port_unlock()
 Kernel-unlock action.
#define port_lock_from_isr()   port_lock()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()   port_unlock()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   asm volatile ("cpsid i" : : : "memory")
 Disables all the interrupt sources.
#define port_suspend()
 Disables the interrupt sources below kernel-level priority.
#define port_enable()
 Enables all the interrupt sources.
#define port_wait_for_interrupt()
 Enters an architecture-dependent IRQ-waiting mode.

-Functions

 CH_IRQ_HANDLER (SysTickVector)
 System Timer vector.
void SVCallVector (void)
 SVC vector.
void _port_irq_epilogue (void)
 Reschedule verification and setup after an IRQ.
void _port_switch_from_isr (void)
 Post-IRQ switch code.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Start a thread by invoking its work function.
void port_halt (void)
 Halts the system.
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 pf,
 arg 
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{                          \
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-  tp->p_ctx.r13->r4 = pf;                                                   \
-  tp->p_ctx.r13->r5 = arg;                                                  \
-  tp->p_ctx.r13->lr = _port_thread_start;                                   \
-}
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Platform dependent part of the chThdInit() API.

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Definition at line 87 of file chcore_v7m.h.

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Definition at line 106 of file chcore_v7m.h.

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Definition at line 121 of file chcore_v7m.h.

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Definition at line 129 of file chcore_v7m.h.

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Definition at line 136 of file chcore_v7m.h.

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Definition at line 143 of file chcore_v7m.h.

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Definition at line 150 of file chcore_v7m.h.

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{                                                       \
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Port-related initialization code.

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Definition at line 155 of file chcore_v7m.h.

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Definition at line 192 of file chcore_v7m.h.

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Definition at line 204 of file chcore_v7m.h.

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Kernel-unlock action from an interrupt handler.

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Definition at line 213 of file chcore_v7m.h.

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Definition at line 221 of file chcore_v7m.h.

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#define port_suspend( void ) 
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{                                                    \
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Disables the interrupt sources below kernel-level priority.

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Definition at line 228 of file chcore_v7m.h.

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Enables all the interrupt sources.

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Definition at line 238 of file chcore_v7m.h.

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#define port_wait_for_interrupt( void ) 
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{                                         \
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Enters an architecture-dependent IRQ-waiting mode.

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Definition at line 253 of file chcore_v7m.h.

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Function Documentation

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CH_IRQ_HANDLER (SysTickVector  ) 
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System Timer vector.

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This interrupt is used as system tick.

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Definition at line 82 of file chcore_v7m.c.

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References CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, chSysLockFromIsr, chSysTimerHandlerI(), and chSysUnlockFromIsr.

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void SVCallVector (void  ) 
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SVC vector.

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The SVC vector is used for exception mode re-entering after a context switch.

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Definition at line 98 of file chcore_v7m.c.

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References port_unlock_from_isr().

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void _port_irq_epilogue (void  ) 
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void _port_switch_from_isr (void  ) 
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Post-IRQ switch code.

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Exception handlers return here for context switching.

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void port_switch (Thread *  ntp,
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Performs a context switch between two threads.

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This is the most critical code in any port, this function is responsible for the context switch between 2 threads.

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Halts the system.

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This function is invoked by the operating system when an unrecoverable error is detected (as example because a programming error in the application code that triggers an assertion while in debug mode).

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This function is invoked by the operating system when an unrecoverable error is detected (as example because a programming error in the application code that triggers an assertion while in debug mode).

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Definition at line 45 of file ports/GCC/ARMCMx/chcore.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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AT91SAM7 Support
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AT91SAM7 specific support. -More...

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Description

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AT91SAM7 specific support.

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The AT91SAM7 support includes:

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  • Buffered, interrupt driven, serial driver.
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  • EMAC driver with MII support.
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  • A demo supporting the kernel test suite.
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  • A Web server demo using the uIP TCP/IP stack.
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  • A Web server demo using the lwIP TCP/IP stack.
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-Modules

 AT91SAM7 HAL Support
 

HAL support.

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 AT91SAM7 I/O Ports Support
 

I/O Ports peripherals support.

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 AT91SAM7 USART Support
 

USART peripherals support.

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 AT91SAM7 EMAC Support
 

EMAC peripheral support.

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 AT91SAM7 MII Support
 

EMAC+PHY peripheral support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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AT91SAM7 HAL Support
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Description

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HAL support.

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-Defines

#define PLATFORM_NAME   "AT91SAM7x"
 Platform name.
#define AT91SAM7_SPURIOUS_HANDLER_HOOK()
 Default action for the spurious handler, nothing.
#define AT91SAM7_USBDIV   AT91C_CKGR_USBDIV_1
 Default divider for the USB clock - half the PLL clock.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void at91sam7_clock_init (void)
 AT91SAM7 clocks and PLL initialization.

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const PALConfig pal_default_config
 PAL setup.
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Definition at line 47 of file platforms/AT91SAM7/hal_lld.h.

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-{
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PAL setup.

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Definition at line 49 of file platforms/AT91SAM7/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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AT91SAM7 EMAC Support
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EMAC peripheral support.

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the MAC Driver supports the AT91SAM7 EMAC peripheral.

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struct  EMACDescriptor
 Structure representing a buffer physical descriptor. More...
struct  MACDriver
 Structure representing a MAC driver. More...
struct  MACTransmitDescriptor
 Structure representing a transmit descriptor. More...
struct  MACReceiveDescriptor
 Structure representing a receive descriptor. More...

-Defines

#define MAC_TRANSMIT_BUFFERS   2
 Number of available transmit buffers.
#define MAC_RECEIVE_BUFFERS   2
 Number of available receive buffers.
#define MAC_BUFFERS_SIZE   1518
 Maximum supported frame size.
#define EMAC_INTERRUPT_PRIORITY   (AT91C_AIC_PRIOR_HIGHEST - 3)
 Interrupt priority level for the EMAC device.

-Functions

 CH_IRQ_HANDLER (irq_handler)
 EMAC IRQ veneer handler.
void mac_lld_init (void)
 Low level MAC initialization.
void mac_lld_set_address (MACDriver *macp, const uint8_t *p)
 Low level MAC address setup.
msg_t max_lld_get_transmit_descriptor (MACDriver *macp, MACTransmitDescriptor *tdp)
 Returns a transmission descriptor.
size_t mac_lld_write_transmit_descriptor (MACTransmitDescriptor *tdp, uint8_t *buf, size_t size)
 Writes to a transmit descriptor's stream.
void mac_lld_release_transmit_descriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t max_lld_get_receive_descriptor (MACDriver *macp, MACReceiveDescriptor *rdp)
 Returns a receive descriptor.
size_t mac_lld_read_receive_descriptor (MACReceiveDescriptor *rdp, uint8_t *buf, size_t size)
 Reads from a receive descriptor's stream.
void mac_lld_release_receive_descriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t mac_lld_poll_link_status (MACDriver *macp)
 Updates and returns the link status.

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MACDriver ETH1
 Ethernet driver 1.
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Low level MAC initialization.

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void mac_lld_set_address (MACDriver *  macp,
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Low level MAC address setup.

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[in] macp pointer to the MACDriver object
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Returns a transmission descriptor.

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One of the available transmission descriptors is locked and returned.

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[out] tdp pointer to a MACTransmitDescriptor structure
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Writes to a transmit descriptor's stream.

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[in] size number of bytes to be written
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Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.

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Returns a receive descriptor.

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[out] rdp pointer to a MACReceiveDescriptor structure
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Reads from a receive descriptor's stream.

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[in] buf pointer to the buffer that will receive the read data
[in] size number of bytes to be read
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Releases a receive descriptor.

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The descriptor and its buffer are made available for more incoming frames.

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bool_t mac_lld_poll_link_status (MACDriver *  macp ) 
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Updates and returns the link status.

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The link status.
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TRUE if the link is active.
FALSE if the link is down.
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Variable Documentation

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MACDriver ETH1
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Ethernet driver 1.

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Definition at line 65 of file platforms/AT91SAM7/mac_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines | -Typedefs | -Functions
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AT91SAM7 MII Support
- -[AT91SAM7 Support] -

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EMAC+PHY peripheral support. -More...

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-Collaboration diagram for AT91SAM7 MII Support:
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Description

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EMAC+PHY peripheral support.

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This driver supports the AT91SAM7 EMAC peripheral communicating with an external PHY transceiver. The driver currently supports the Micrel KS8721 PHY and the Davicom DV9161 modules.

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-Defines

#define PHY_HARDWARE   PHY_MICREL_KS8721
 PHY manufacturer and model.
#define PHY_ADDRESS   1
 Pins latched by the PHY at reset.

-Typedefs

typedef uint16_t phyreg_t
 Type of a PHY register value.
typedef uint8_t phyaddr_t
 Type of a PHY register address.

-Functions

void miiInit (void)
 Low level MII driver initialization.
void miiReset (MACDriver *macp)
 Resets a PHY device.
phyreg_t miiGet (MACDriver *macp, phyaddr_t addr)
 Reads a PHY register through the MII interface.
void miiPut (MACDriver *macp, phyaddr_t addr, phyreg_t value)
 Writes a PHY register through the MII interface.
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Define Documentation

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#define PHY_HARDWARE   PHY_MICREL_KS8721
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PHY manufacturer and model.

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Definition at line 54 of file at91sam7_mii.h.

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#define PHY_ADDRESS   1
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Pins latched by the PHY at reset.

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Definition at line 65 of file at91sam7_mii.h.

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Typedef Documentation

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typedef uint16_t phyreg_t
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Type of a PHY register value.

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Definition at line 90 of file at91sam7_mii.h.

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typedef uint8_t phyaddr_t
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Type of a PHY register address.

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Definition at line 95 of file at91sam7_mii.h.

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Function Documentation

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void miiInit (void  ) 
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Low level MII driver initialization.

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void miiReset (MACDriver *  macp ) 
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Resets a PHY device.

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phyreg_t miiGet (MACDriver *  macp,
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Reads a PHY register through the MII interface.

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[in] macp pointer to the MACDriver object
addr the register address
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void miiPut (MACDriver *  macp,
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phyreg_t  value 
)
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Writes a PHY register through the MII interface.

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[in] macp pointer to the MACDriver object
addr the register address
value the new register value
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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AT91SAM7 I/O Ports Support
- -[AT91SAM7 Support] -

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I/O Ports peripherals support. -More...

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-Collaboration diagram for AT91SAM7 I/O Ports Support:
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Description

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I/O Ports peripherals support.

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This module supports the AT91SAM7 PIO controller. The controller supports the following features (see PAL Driver):

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  • 32 bits wide ports.
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  • Atomic set/reset functions.
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  • Output latched regardless of the pad setting.
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  • Direct read of input pads regardless of the pad setting.
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Supported Setup Modes

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  • PAL_MODE_RESET.
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  • PAL_MODE_UNCONNECTED.
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  • PAL_MODE_INPUT.
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  • PAL_MODE_INPUT_ANALOG (same as PAL_MODE_INPUT).
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  • PAL_MODE_INPUT_PULLUP.
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  • PAL_MODE_OUTPUT_PUSHPULL.
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  • PAL_MODE_OUTPUT_OPENDRAIN.
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Any attempt to setup an invalid mode is ignored.

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Suboptimal Behavior

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Some PIO features are less than optimal:

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  • Pad/port toggling operations are not atomic.
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-Data Structures

struct  at91sam7_pio_setup_t
 PIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define IOPORT1   AT91C_BASE_PIOA
 PIO port A identifier.
#define IOPORT2   AT91C_BASE_PIOB
 PIO port B identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->PIO_PDSR)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->PIO_ODSR)
 Reads the output latch.
#define pal_lld_writeport(port, bits)
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)
 Clears a bits mask on a I/O port.
#define pal_lld_writegroup(port, mask, offset, bits)
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   pal_lld_writegroup(port, 1, pad, bit)
 Writes a logical state on an output pad.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef AT91PS_PIO ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 AT91SAM7 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

const PALConfig pal_default_config
 PAL setup.
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Define Documentation

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#define PAL_IOPORTS_WIDTH   32
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Width, in bits, of an I/O port.

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Definition at line 81 of file platforms/AT91SAM7/pal_lld.h.

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#define IOPORT1   AT91C_BASE_PIOA
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PIO port A identifier.

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Definition at line 103 of file platforms/AT91SAM7/pal_lld.h.

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Definition at line 110 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_init( config )    _pal_lld_init(config)
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Low level PAL subsystem initialization.

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Definition at line 121 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_readport( port )    ((port)->PIO_PDSR)
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Reads the physical I/O port states.

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This function is implemented by reading the PIO_PDSR register, the implementation has no side effects.

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[in] port the port identifier
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Definition at line 134 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_readlatch( port )    ((port)->PIO_ODSR)
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Reads the output latch.

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This function is implemented by reading the PIO_ODSR register, the implementation has no side effects.

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[in] port the port identifier
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The latched logical states.
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Definition at line 147 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_writeport( port,
 bits 
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{                                 \
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Writes a bits mask on a I/O port.

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This function is implemented by writing the PIO_ODSR register, the implementation has no side effects.

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[in] port the port identifier
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Definition at line 160 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_setport( port,
 bits 
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{                                   \
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Sets a bits mask on a I/O port.

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This function is implemented by writing the PIO_SODR register, the implementation has no side effects.

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Definition at line 175 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_clearport( port,
 bits 
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{                                 \
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Clears a bits mask on a I/O port.

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This function is implemented by writing the PIO_CODR register, the implementation has no side effects.

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[in] port the port identifier
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Definition at line 191 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_writegroup( port,
 mask,
 offset,
 bits 
)
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{                  \
-  (port)->PIO_OWER = (mask) << (offset);                                \
-  (port)->PIO_ODSR = (bits) << (offset);                                \
-  (port)->PIO_OWDR = (mask) << (offset);                                \
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Writes a group of bits.

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This function is implemented by writing the PIO_OWER, PIO_ODSR and PIO_OWDR registers, the implementation is not atomic because the multiple accesses.

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[in] port the port identifier
[in] mask the group mask
[in] offset the group bit offset within the port
[in] bits the bits to be written. Values exceeding the group width are masked.
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Definition at line 210 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_setgroupmode( port,
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Pads group mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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[in] port the port identifier
[in] mask the group mask
[in] mode the mode
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Definition at line 230 of file platforms/AT91SAM7/pal_lld.h.

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#define pal_lld_writepad( port,
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Writes a logical state on an output pad.

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[in] port the port identifier
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Definition at line 243 of file platforms/AT91SAM7/pal_lld.h.

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Definition at line 86 of file platforms/AT91SAM7/pal_lld.h.

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Definition at line 94 of file platforms/AT91SAM7/pal_lld.h.

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void _pal_lld_init (const PALConfig *  config ) 
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PIO registers initialization.

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Pads mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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[in] mask the group mask
[in] mode the mode
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Variable Documentation

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PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 49 of file platforms/AT91SAM7/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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AT91SAM7 USART Support
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USART peripherals support. -More...

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Description

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USART peripherals support.

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The serial driver supports the AT91SAM7 USART peripherals.

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struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_SAM7_USART0   TRUE
 UART0 driver enable switch.
#define USE_SAM7_USART1   TRUE
 UART1 driver enable switch.
#define USE_SAM7_DBGU_UART   TRUE
 DBGU UART driver enable switch.
#define SAM7_USART0_PRIORITY   (AT91C_AIC_PRIOR_HIGHEST - 2)
 UART1 interrupt priority level setting.
#define SAM7_USART1_PRIORITY   (AT91C_AIC_PRIOR_HIGHEST - 2)
 UART2 interrupt priority level setting.
#define SAM7_DBGU_UART_PRIORITY   (AT91C_AIC_PRIOR_HIGHEST - 2)
 DBGU_UART interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 USART0 serial driver identifier.
SerialDriver SD2
 USART1 serial driver identifier.
SerialDriver SD3
 DBGU_UART serial driver identifier.
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#define USE_SAM7_USART0   TRUE
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UART0 driver enable switch.

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If set to TRUE the support for USART1 is included.

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Definition at line 54 of file platforms/AT91SAM7/serial_lld.h.

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UART1 driver enable switch.

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Definition at line 63 of file platforms/AT91SAM7/serial_lld.h.

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DBGU UART driver enable switch.

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Definition at line 72 of file platforms/AT91SAM7/serial_lld.h.

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UART1 interrupt priority level setting.

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Definition at line 79 of file platforms/AT91SAM7/serial_lld.h.

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Definition at line 86 of file platforms/AT91SAM7/serial_lld.h.

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DBGU_UART interrupt priority level setting.

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Definition at line 93 of file platforms/AT91SAM7/serial_lld.h.

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#define _serial_driver_data
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_base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Status Change @p EventSource.*/                                        \
-  EventSource               sevent;                                         \
-  /* I/O driver status flags.*/                                             \
-  sdflags_t                 flags;                                          \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
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SerialDriver specific data.

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Definition at line 130 of file platforms/AT91SAM7/serial_lld.h.

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Typedef Documentation

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Serial Driver condition flags type.

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Definition at line 107 of file platforms/AT91SAM7/serial_lld.h.

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Function Documentation

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void sd_lld_init (void  ) 
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Low level serial driver initialization.

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Low level serial driver configuration and (re)start.

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[in] sdp pointer to a SerialDriver object
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Low level serial driver stop.

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De-initializes the USART, stops the associated clock, resets the interrupt vector.

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SerialDriver SD1
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USART0 serial driver identifier.

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Definition at line 68 of file platforms/AT91SAM7/serial_lld.c.

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USART1 serial driver identifier.

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Definition at line 73 of file platforms/AT91SAM7/serial_lld.c.

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SerialDriver SD3
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DBGU_UART serial driver identifier.

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Definition at line 78 of file platforms/AT91SAM7/serial_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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MegaAVR
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Description

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AVR port details. This section how the ChibiOS/RT features are implemented on this architecture.

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-Mapping of the System States in the AVR port

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The ChibiOS/RT logical System States are mapped as follow in the AVR port:

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  • Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated.
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-The AVR port notes

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-Modules

 Configuration Options
 

AVR Configuration Options.

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 AVR Core Implementation
 

AVR specific port code, structures and macros.

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 AVR Drivers
 

Device drivers included in the AVR support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Configuration Options
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AVR Configuration Options. -More...

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AVR Configuration Options.

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The AVR port allows some architecture-specific configurations settings that can be overridden by redefining them in chconf.h. Usually there is no need to change the default values.

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  • INT_REQUIRED_STACK, this value represent the amount of stack space used by the interrupt handlers.
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  • IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE thread. Usually there is no need to change this value unless inserting code in the IDLE thread hook macro.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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AVR Core Implementation
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AVR specific port code, structures and macros. -More...

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Description

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AVR specific port code, structures and macros.

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-Defines

#define ENABLE_WFI_IDLE   0
 If enabled allows the idle thread to enter a low power mode.
#define CH_ARCHITECTURE_AVR
 Macro defining the AVR architecture.
#define CH_ARCHITECTURE_NAME   "AVR"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "MegaAVR"
 Name of the architecture variant (optional).
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   8
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   32
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   ISR(id)
 IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   asm volatile ("cli" : : : "memory")
 Kernel-lock action.
#define port_unlock()   asm volatile ("sei" : : : "memory")
 Kernel-unlock action.
#define port_lock_from_isr()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   asm volatile ("cli" : : : "memory")
 Disables all the interrupt sources.
#define port_suspend()   asm volatile ("cli" : : : "memory")
 Disables the interrupt sources below kernel-level priority.
#define port_enable()   asm volatile ("sei" : : : "memory")
 Enables all the interrupt sources.
#define port_wait_for_interrupt()
 Enters an architecture-dependent IRQ-waiting mode.
#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef uint8_t stkalign_t
 8 bits stack and memory alignment enforcement.
typedef int8_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint8_t tprio_t
typedef int16_t msg_t
typedef uint8_t eventid_t
typedef uint8_t eventmask_t
typedef uint16_t systime_t
typedef int8_t cnt_t

-Functions

void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void port_halt (void)
 Halts the system.
void _port_thread_start (void)
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#define ENABLE_WFI_IDLE   0
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Definition at line 45 of file ports/GCC/AVR/chcore.h.

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Definition at line 149 of file ports/GCC/AVR/chcore.h.

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This constant is used in the calculation of the correct working area size. This value can be zero on those architecture where there is a separate interrupt stack and the stack space between intctx and extctx is known to be zero.

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Definition at line 187 of file ports/GCC/AVR/chcore.h.

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Definition at line 202 of file ports/GCC/AVR/chcore.h.

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Definition at line 211 of file ports/GCC/AVR/chcore.h.

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Definition at line 221 of file ports/GCC/AVR/chcore.h.

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Definition at line 231 of file ports/GCC/AVR/chcore.h.

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Definition at line 237 of file ports/GCC/AVR/chcore.h.

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Definition at line 245 of file ports/GCC/AVR/chcore.h.

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Kernel-unlock action.

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Definition at line 253 of file ports/GCC/AVR/chcore.h.

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Definition at line 262 of file ports/GCC/AVR/chcore.h.

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Definition at line 271 of file ports/GCC/AVR/chcore.h.

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Definition at line 278 of file ports/GCC/AVR/chcore.h.

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Definition at line 286 of file ports/GCC/AVR/chcore.h.

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Definition at line 292 of file ports/GCC/AVR/chcore.h.

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void port_switch (Thread *  ntp,
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Architecture - Reference Manual - Guides
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AVR Drivers
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Device drivers included in the AVR support. -More...

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Device drivers included in the AVR support.

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 AVR HAL Support
 

HAL support.

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 AVR USART Support
 

USART support.

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AVR HAL Support
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HAL support.

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#define PLATFORM_NAME   "ATmega128"
 Platform name.

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void hal_lld_init (void)
 Low level HAL driver initialization.
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Platform name.

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Definition at line 44 of file platforms/AVR/hal_lld.h.

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void hal_lld_init (void  ) 
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Low level HAL driver initialization.

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Architecture - Reference Manual - Guides
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AVR USART Support
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USART support.

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The serial driver supports both the AVR USARTs in asynchronous mode.

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struct  SerialConfig
 Generic Serial Driver configuration structure. More...

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#define USE_AVR_USART0   TRUE
 USART0 driver enable switch.
#define USE_AVR_USART1   TRUE
 USART1 driver enable switch.
#define _serial_driver_data
 SerialDriver specific data.
#define UBRR(b)   ((F_CPU / (b << 4)) - 1)
 Macro for baud rate computation.

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typedef uint8_t sdflags_t
 Serial Driver condition flags type.

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void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

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SerialDriver SD1
 USART0 serial driver identifier.
SerialDriver SD2
 USART1 serial driver identifier.
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#define USE_AVR_USART0   TRUE
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USART0 driver enable switch.

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Definition at line 54 of file platforms/AVR/serial_lld.h.

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Definition at line 63 of file platforms/AVR/serial_lld.h.

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Low level serial driver configuration and (re)start.

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USART0 serial driver identifier.

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CAN Driver
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Generic CAN Driver. -More...

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Generic CAN Driver.

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 CAN Low Level Driver
 

CAN Driver low level driver template.

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#define CAN_LIMIT_WARNING   1
 Errors rate warning.
#define CAN_LIMIT_ERROR   2
 Errors rate error.
#define CAN_BUS_OFF_ERROR   4
 Bus off condition reached.
#define CAN_FRAMING_ERROR   8
 Framing error of some kind on the CAN bus.
#define CAN_OVERFLOW_ERROR   16
 Overflow in receive queue.
#define CAN_USE_SLEEP_MODE   TRUE
 Sleep mode related APIs inclusion switch.
#define canAddFlagsI(canp, mask)   ((canp)->cd_status |= (mask))
 Adds some flags to the CAN status mask.

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enum  canstate_t {
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Driver state machine possible states.

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void canInit (void)
 CAN Driver initialization.
void canObjectInit (CANDriver *canp)
 Initializes the standard part of a CANDriver structure.
void canStart (CANDriver *canp, const CANConfig *config)
 Configures and activates the CAN peripheral.
void canStop (CANDriver *canp)
 Deactivates the CAN peripheral.
msg_t canTransmit (CANDriver *canp, const CANTxFrame *ctfp, systime_t timeout)
 Can frame transmission.
msg_t canReceive (CANDriver *canp, CANRxFrame *crfp, systime_t timeout)
 Can frame receive.
canstatus_t canGetAndClearFlags (CANDriver *canp)
 Returns the current status mask and clears it.
void canSleep (CANDriver *canp)
 Enters the sleep mode.
void canWakeup (CANDriver *canp)
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Definition at line 111 of file can.h.

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CAN_UNINIT  -

Not initialized.

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Stopped.

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Starting.

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Ready.

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Sleep state.

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void canInit (void  ) 
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CAN Driver initialization.

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Definition at line 69 of file can.c.

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References CANDriver::cd_config, CANDriver::cd_error_event, CANDriver::cd_rxfull_event, CANDriver::cd_rxsem, CANDriver::cd_sleep_event, CANDriver::cd_state, CANDriver::cd_status, CANDriver::cd_txempty_event, CANDriver::cd_txsem, CANDriver::cd_wakeup_event, chEvtInit, and chSemInit().

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void canStart (CANDriver *  canp,
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Definition at line 91 of file can.c.

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References can_lld_start(), CAN_READY, CAN_STARTING, CAN_STOP, CANDriver::cd_config, CANDriver::cd_state, chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, and chThdSleepS.

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Definition at line 116 of file can.c.

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References can_lld_stop(), CAN_READY, CAN_STOP, CANDriver::cd_rxsem, CANDriver::cd_state, CANDriver::cd_status, CANDriver::cd_txsem, chDbgAssert, chDbgCheck, chSchRescheduleS(), chSemResetI(), chSysLock, and chSysUnlock.

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msg_t canTransmit (CANDriver *  canp,
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Can frame transmission.

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The specified frame is queued for transmission, if the hardware queue is full then the invoking thread is queued.

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[in] ctfp pointer to the CAN frame to be transmitted
[in] timeout the number of ticks before the operation timeouts, the following special values are allowed:

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RDY_OK the frame has been queued for transmission.
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Definition at line 151 of file can.c.

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References can_lld_can_transmit(), can_lld_transmit(), CAN_READY, CAN_SLEEP, CANDriver::cd_state, CANDriver::cd_txsem, chDbgAssert, chDbgCheck, chSemWaitTimeoutS(), chSysLock, chSysUnlock, and RDY_OK.

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msg_t canReceive (CANDriver *  canp,
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Can frame receive.

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The function waits until a frame is received.

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[in] canp pointer to the CANDriver object
[out] crfp pointer to the buffer where the CAN frame is copied
[in] timeout the number of ticks before the operation timeouts, the following special values are allowed:

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RDY_OK a frame has been received and placed in the buffer.
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Definition at line 192 of file can.c.

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References can_lld_can_receive(), can_lld_receive(), CAN_READY, CAN_SLEEP, CANDriver::cd_rxsem, CANDriver::cd_state, chDbgAssert, chDbgCheck, chSemWaitTimeoutS(), chSysLock, chSysUnlock, and RDY_OK.

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canstatus_t canGetAndClearFlags (CANDriver *  canp ) 
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Definition at line 218 of file can.c.

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Definition at line 234 of file can.c.

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Definition at line 258 of file can.c.

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CAN Low Level Driver
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CAN Driver low level driver template. -More...

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Description

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CAN Driver low level driver template.

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-Data Structures

struct  CANTxFrame
 CAN transmission frame. More...
struct  CANRxFrame
 CAN received frame. More...
struct  CANFilter
 CAN filter. More...
struct  CANConfig
 Driver configuration structure. More...
struct  CANDriver
 Structure representing an CAN driver. More...

-Defines

#define CAN_SUPPORTS_SLEEP   TRUE
 This switch defines whether the driver implementation supports a low power switch mode with automatic an wakeup feature.
#define CAN_USE_SLEEP_MODE   TRUE
 Sleep mode related APIs inclusion switch.

-Typedefs

typedef uint32_t canstatus_t
 CAN status flags.

-Functions

void can_lld_init (void)
 Low level CAN driver initialization.
void can_lld_start (CANDriver *canp)
 Configures and activates the CAN peripheral.
void can_lld_stop (CANDriver *canp)
 Deactivates the CAN peripheral.
bool_t can_lld_can_transmit (CANDriver *canp)
 Determines whether a frame can be transmitted.
void can_lld_transmit (CANDriver *canp, const CANTxFrame *ctfp)
 Inserts a frame into the transmit queue.
bool_t can_lld_can_receive (CANDriver *canp)
 Determines whether a frame has been received.
void can_lld_receive (CANDriver *canp, CANRxFrame *crfp)
 Receives a frame from the input queue.
void can_lld_sleep (CANDriver *canp)
 Enters the sleep mode.
void can_lld_wakeup (CANDriver *canp)
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#define CAN_SUPPORTS_SLEEP   TRUE
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This switch defines whether the driver implementation supports a low power switch mode with automatic an wakeup feature.

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Definition at line 48 of file templates/can_lld.h.

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Definition at line 61 of file templates/can_lld.h.

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typedef uint32_t canstatus_t
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CAN status flags.

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void can_lld_init (void  ) 
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Low level CAN driver initialization.

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void can_lld_start (CANDriver *  canp ) 
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Configures and activates the CAN peripheral.

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Deactivates the CAN peripheral.

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Referenced by canStop().

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Determines whether a frame can be transmitted.

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Inserts a frame into the transmit queue.

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Referenced by canTransmit().

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Determines whether a frame has been received.

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Receives a frame from the input queue.

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Definition at line 142 of file templates/can_lld.c.

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 HAL Low Level Driver
 

HAL Driver low level driver template.

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HAL Driver Configuration.

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void halInit (void  ) 
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HAL initialization.

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Definition at line 57 of file hal.c.

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HAL Driver Configuration.

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#define CH_HAL_USE_PAL   TRUE
 Enables the PAL subsystem.
#define CH_HAL_USE_ADC   TRUE
 Enables the ADC subsystem.
#define CH_HAL_USE_CAN   TRUE
 Enables the CAN subsystem.
#define CH_HAL_USE_MAC   TRUE
 Enables the MAC subsystem.
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 Enables the PWM subsystem.
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HAL Driver low level driver template.

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Description

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Hardware Abstraction Layer.

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Under ChibiOS/RT the set of the various device driver interfaces is called the HAL subsystem: Hardware Abstraction Layer.
- A device driver is usually split in two layers:

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    -
  • High Level Device Driver (HLD). This layer contains the definitions of the driver's APIs and the platform independent part of the driver.
    - An HLD is composed by two files:
      -
    • <driver>.c, the HLD implementation file. This file must be included in the Makefile in order to use the driver.
      • -
    • <driver>.h, the HLD header file. This file is implicitly included by the HAL header file hal.h.
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  • Low Level Device Driver (LLD). This layer contains the platform dependent part of the driver.
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      -
    • <driver>_lld.c, the LLD implementation file. This file must be included in the Makefile in order to use the driver.
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    • <driver>_lld.h, the LLD header file. This file is implicitly included by the HLD header file.
      • -
    -The LLD may be not present in those drivers that do not access the hardware directly but through other device drivers, as example the MMC over SPI Driver driver uses the SPI Driver and PAL Driver drivers in order to implement its functionalities.
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Available Device Drivers

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The I/O subsystem currently includes support for:

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 HAL Driver
 

Hardware Abstraction Layer.

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 PAL Driver
 

I/O Ports Abstraction Layer.

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 Serial Driver
 

Generic Serial Driver.

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 SPI Driver
 

Generic SPI Driver.

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 ADC Driver
 

Generic ADC Driver.

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 CAN Driver
 

Generic CAN Driver.

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 PWM Driver
 

Generic PWM Driver.

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 MAC Driver
 

Generic MAC driver.

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 MMC over SPI Driver
 

Generic MMC driver.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Modules
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LPC11xx Support
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LPC11xx specific support. -More...

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-Collaboration diagram for LPC11xx Support:
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Description

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LPC11xx specific support.

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The LPC11xx support includes:

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  • Buffered, interrupt driven, serial driver.
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  • A demo supporting the kernel test suite.
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-Modules

 LPC11xx HAL Support
 

HAL support.

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 LPC11xx I/O Ports Support
 

I/O Ports peripherals support.

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 LPC11xx UART Support
 

UART peripherals support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines | -Functions | -Variables
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LPC11xx HAL Support
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HAL support. -More...

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Description

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HAL support.

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-Defines

#define FLASHCFG   (*((volatile uint32_t *)0x4003C010))
 Register missing in NXP header file.
#define PLATFORM_NAME   "LPC11xx"
 Platform name.
#define IRCOSCCLK   12000000
#define WDGOSCCLK   1600000
#define SYSPLLCLKSEL_IRCOSC   0
#define SYSPLLCLKSEL_SYSOSC   1
#define SYSMAINCLKSEL_IRCOSC   0
#define SYSMAINCLKSEL_PLLIN   1
#define SYSMAINCLKSEL_WDGOSC   2
#define SYSMAINCLKSEL_PLLOUT   3
#define LPC11xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC
 System PLL clock source.
#define LPC11xx_SYSPLL_MUL   4
 System PLL multiplier.
#define LPC11xx_SYSPLL_DIV   4
 System PLL divider.
#define LPC11xx_MAINCLK_SOURCE   SYSMAINCLKSEL_PLLOUT
 System main clock source.
#define LPC11xx_SYSABHCLK_DIV   1
 AHB clock divider.
#define LPC11xx_UART_PCLK_DIV   1
 UART clock divider.
#define LPC11xx_SYSOSCCTRL   0
 Calculated SYSOSCCTRL setting.
#define LPC11xx_SYSPLLCLKIN   SYSOSCCLK
 PLL input clock frequency.
#define LPC11xx_SYSPLLCTRL_MSEL   (LPC11xx_SYSPLL_MUL - 1)
 MSEL mask in SYSPLLCTRL register.
#define LPC11xx_SYSPLLCTRL_PSEL   (0 << 5)
 PSEL mask in SYSPLLCTRL register.
#define LPC11xx_SYSPLLCCO
 CCP frequency.
#define LPC11xx_SYSPLLCLKOUT   (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)
 PLL output clock frequency.
#define LPC11xx_SYSCLK   (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV)
 AHB clock.
#define LPC11xx_FLASHCFG_FLASHTIM   0
 Flash wait states.
#define LPC11xx_UART_PCLK   (LPC11xx_MAINCLK / LPC11xx_UART_PCLK_DIV)
 UART clock.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void lpc111x_clock_init (void)
 LPC11xx clocks and PLL initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
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Define Documentation

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#define FLASHCFG   (*((volatile uint32_t *)0x4003C010))
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Register missing in NXP header file.

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Definition at line 41 of file platforms/LPC11xx/hal_lld.c.

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#define PLATFORM_NAME   "LPC11xx"
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Platform name.

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Definition at line 48 of file platforms/LPC11xx/hal_lld.h.

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#define IRCOSCCLK   12000000
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High speed internal clock.

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Definition at line 50 of file platforms/LPC11xx/hal_lld.h.

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#define WDGOSCCLK   1600000
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Watchdog internal clock.

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Definition at line 51 of file platforms/LPC11xx/hal_lld.h.

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#define SYSPLLCLKSEL_IRCOSC   0
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Internal RC oscillator clock source.

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Definition at line 53 of file platforms/LPC11xx/hal_lld.h.

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#define SYSPLLCLKSEL_SYSOSC   1
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System oscillator clock source.

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Definition at line 55 of file platforms/LPC11xx/hal_lld.h.

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#define SYSMAINCLKSEL_IRCOSC   0
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Clock source is IRC.

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Definition at line 58 of file platforms/LPC11xx/hal_lld.h.

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#define SYSMAINCLKSEL_PLLIN   1
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Clock source is PLLIN.

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Definition at line 59 of file platforms/LPC11xx/hal_lld.h.

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#define SYSMAINCLKSEL_WDGOSC   2
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Clock source is WDGOSC.

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Definition at line 60 of file platforms/LPC11xx/hal_lld.h.

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#define SYSMAINCLKSEL_PLLOUT   3
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Clock source is PLLOUT.

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Definition at line 61 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC
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System PLL clock source.

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Definition at line 71 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSPLL_MUL   4
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System PLL multiplier.

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Note:
The value must be in the 1..32 range and the final frequency must not exceed the CCO ratings.
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Definition at line 80 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSPLL_DIV   4
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System PLL divider.

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Note:
The value must be chosen between (2, 4, 8, 16).
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Definition at line 88 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_MAINCLK_SOURCE   SYSMAINCLKSEL_PLLOUT
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System main clock source.

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Definition at line 95 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSABHCLK_DIV   1
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AHB clock divider.

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Note:
The value must be chosen between (1...255).
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Definition at line 103 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_UART_PCLK_DIV   1
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UART clock divider.

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Note:
The value must be chosen between (1...255).
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Definition at line 111 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSOSCCTRL   0
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Calculated SYSOSCCTRL setting.

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Definition at line 122 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSPLLCLKIN   SYSOSCCLK
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PLL input clock frequency.

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Definition at line 131 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSPLLCTRL_MSEL   (LPC11xx_SYSPLL_MUL - 1)
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MSEL mask in SYSPLLCTRL register.

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Definition at line 143 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSPLLCTRL_PSEL   (0 << 5)
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PSEL mask in SYSPLLCTRL register.

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Definition at line 152 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSPLLCCO
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-Value:
(LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL *    \
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CCP frequency.

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Definition at line 166 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSPLLCLKOUT   (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)
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PLL output clock frequency.

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Definition at line 176 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_SYSCLK   (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV)
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AHB clock.

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Definition at line 193 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_FLASHCFG_FLASHTIM   0
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Flash wait states.

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Definition at line 202 of file platforms/LPC11xx/hal_lld.h.

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#define LPC11xx_UART_PCLK   (LPC11xx_MAINCLK / LPC11xx_UART_PCLK_DIV)
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UART clock.

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Definition at line 212 of file platforms/LPC11xx/hal_lld.h.

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Function Documentation

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void hal_lld_init (void  ) 
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Low level HAL driver initialization.

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void lpc111x_clock_init (void  ) 
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LPC11xx clocks and PLL initialization.

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Variable Documentation

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const PALConfig pal_default_config
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-Initial value:
 {
- {VAL_GPIO0DATA, VAL_GPIO0DIR},
- {VAL_GPIO1DATA, VAL_GPIO1DIR},
- {VAL_GPIO2DATA, VAL_GPIO2DIR},
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PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 55 of file platforms/LPC11xx/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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LPC11xx I/O Ports Support
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I/O Ports peripherals support. -More...

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-Collaboration diagram for LPC11xx I/O Ports Support:
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Description

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I/O Ports peripherals support.

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This module supports the LPC11xx GPIO controller. The controller supports the following features (see PAL Driver):

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Supported Setup Modes

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Any attempt to setup an invalid mode is ignored.

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Suboptimal Behavior

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Some GPIO features are less than optimal:

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-Data Structures

struct  lpc111x_gpio_setup_t
 GPIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFF)
 Whole port mask.
#define IOPORT1   LPC_GPIO0
 GPIO0 port identifier.
#define IOPORT2   LPC_GPIO1
 GPIO1 port identifier.
#define IOPORT3   LPC_GPIO2
 GPIO2 port identifier.
#define IOPORT4   LPC_GPIO3
 GPIO3 port identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->DATA)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->DATA)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->DATA = (bits))
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0)
 Clears a bits mask on a I/O port.
#define pal_lld_readgroup(port, mask, offset)   ((port)->MASKED_ACCESS[(mask) << (offset)])
 Reads a group of bits.
#define pal_lld_writegroup(port, mask, offset, bits)   ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad))
 Writes a logical state on an output pad.
#define pal_lld_setpad(port, pad)   ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
 Sets a pad logical state to PAL_HIGH.
#define pal_lld_clearpad(port, pad)   ((port)->MASKED_ACCESS[1 << (pad)] = 0)
 Clears a pad logical state to PAL_LOW.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef LPC_GPIO_TypeDef * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 LPC11xx I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
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Define Documentation

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#define PAL_IOPORTS_WIDTH   32
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Width, in bits, of an I/O port.

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Definition at line 89 of file platforms/LPC11xx/pal_lld.h.

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#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFF)
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Whole port mask.

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This macro specifies all the valid bits into a port.

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Definition at line 95 of file platforms/LPC11xx/pal_lld.h.

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#define IOPORT1   LPC_GPIO0
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GPIO0 port identifier.

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Definition at line 114 of file platforms/LPC11xx/pal_lld.h.

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#define IOPORT2   LPC_GPIO1
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GPIO1 port identifier.

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Definition at line 120 of file platforms/LPC11xx/pal_lld.h.

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#define IOPORT3   LPC_GPIO2
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GPIO2 port identifier.

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Definition at line 126 of file platforms/LPC11xx/pal_lld.h.

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#define IOPORT4   LPC_GPIO3
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GPIO3 port identifier.

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Definition at line 132 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_init( config )    _pal_lld_init(config)
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Low level PAL subsystem initialization.

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Parameters:
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[in] config architecture-dependent ports configuration
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Definition at line 145 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_readport( port )    ((port)->DATA)
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Reads the physical I/O port states.

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Note:
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Parameters:
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[in] port port identifier
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The port bits.
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Definition at line 155 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_readlatch( port )    ((port)->DATA)
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Reads the output latch.

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The purpose of this function is to read back the latched output value.

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Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
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The latched logical states.
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Definition at line 167 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_writeport( port,
 bits 
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Writes a bits mask on a I/O port.

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Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
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Definition at line 177 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_setport( port,
 bits 
)   ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
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Sets a bits mask on a I/O port.

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Note:
This function is not meant to be invoked directly by the application code.
-
-The PAL Driver provides a default software implementation of this functionality, implement this function if can optimize it by using special hardware functionalities or special coding.
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- - - -
[in] port port identifier
[in] bits bits to be ORed on the specified port
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Definition at line 190 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_clearport( port,
 bits 
)   ((port)->MASKED_ACCESS[bits] = 0)
-
-
- -

Clears a bits mask on a I/O port.

-
Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] bits bits to be cleared on the specified port
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Definition at line 203 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_readgroup( port,
 mask,
 offset 
)   ((port)->MASKED_ACCESS[(mask) << (offset)])
-
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Reads a group of bits.

-
Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] mask group mask
[in] offset group bit offset within the port
-
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Returns:
The group logical states.
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Definition at line 218 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_writegroup( port,
 mask,
 offset,
 bits 
)   ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
-
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Writes a group of bits.

-
Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] mask group mask
[in] offset group bit offset within the port
[in] bits bits to be written. Values exceeding the group width are masked.
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Definition at line 235 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_setgroupmode( port,
 mask,
 mode 
)   _pal_lld_setgroupmode(port, mask, mode)
-
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Pads group mode setup.

-

This function programs a pads group belonging to the same port with the specified mode.

-
Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] mask group mask
[in] mode group mode
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Definition at line 250 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_writepad( port,
 pad,
 bit 
)   ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad))
-
-
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Writes a logical state on an output pad.

-
Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] pad pad number within the port
[out] bit logical value, the value must be PAL_LOW or PAL_HIGH
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Definition at line 266 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_setpad( port,
 pad 
)   ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
-
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Sets a pad logical state to PAL_HIGH.

-
Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] pad pad number within the port
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Definition at line 280 of file platforms/LPC11xx/pal_lld.h.

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#define pal_lld_clearpad( port,
 pad 
)   ((port)->MASKED_ACCESS[1 << (pad)] = 0)
-
-
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Clears a pad logical state to PAL_LOW.

-
Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] pad pad number within the port
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Definition at line 294 of file platforms/LPC11xx/pal_lld.h.

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Typedef Documentation

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typedef uint32_t ioportmask_t
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Digital I/O port sized unsigned type.

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Definition at line 100 of file platforms/LPC11xx/pal_lld.h.

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typedef LPC_GPIO_TypeDef* ioportid_t
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Port Identifier.

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Definition at line 105 of file platforms/LPC11xx/pal_lld.h.

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Function Documentation

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void _pal_lld_init (const PALConfig *  config ) 
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LPC11xx I/O ports configuration.

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GPIO unit registers initialization.

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[in] config the LPC11xx ports configuration
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void _pal_lld_setgroupmode (ioportid_t  port,
ioportmask_t  mask,
uint_fast8_t  mode 
)
-
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Pads mode setup.

-

This function programs a pads group belonging to the same port with the specified mode.

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Parameters:
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[in] port the port identifier
[in] mask the group mask
[in] mode the mode
-
-
-
Note:
This function is not meant to be invoked directly by the application code.
-
-PAL_MODE_UNCONNECTED is implemented as push pull output with high state.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-Data Structures | -Defines | -Typedefs | -Functions | -Variables
-
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LPC11xx UART Support
- -[LPC11xx Support] -

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UART peripherals support. -More...

- -

-Collaboration diagram for LPC11xx UART Support:
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Description

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UART peripherals support.

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The serial driver supports the LPC11xx UART taking advantage of its deep hardware buffers.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_LPC11xx_UART0   TRUE
 UART0 driver enable switch.
#define LPC11xx_UART_FIFO_PRELOAD   16
 FIFO preload parameter.
#define LPC11xx_UART0_PRIORITY   3
 UART0 interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

 CH_IRQ_HANDLER (Vector94)
 UART0 IRQ handler.
void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 UART0 serial driver identifier.
-

Define Documentation

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#define USE_LPC11xx_UART0   TRUE
-
-
- -

UART0 driver enable switch.

-

If set to TRUE the support for UART0 is included.

-
Note:
The default is TRUE .
- -

Definition at line 99 of file platforms/LPC11xx/serial_lld.h.

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#define LPC11xx_UART_FIFO_PRELOAD   16
-
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FIFO preload parameter.

-

Configuration parameter, this values defines how many bytes are preloaded in the HW transmit FIFO for each interrupt, the maximum value is 16 the minimum is 1.

-
Note:
An high value reduces the number of interrupts generated but can also increase the worst case interrupt response time because the preload loops.
- -

Definition at line 112 of file platforms/LPC11xx/serial_lld.h.

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#define LPC11xx_UART0_PRIORITY   3
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UART0 interrupt priority level setting.

- -

Definition at line 119 of file platforms/LPC11xx/serial_lld.h.

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#define _serial_driver_data
-
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-Value:
_base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Status Change @p EventSource.*/                                        \
-  EventSource               sevent;                                         \
-  /* I/O driver status flags.*/                                             \
-  sdflags_t                 flags;                                          \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_UART_TypeDef        *uart;
-
-

SerialDriver specific data.

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Definition at line 162 of file platforms/LPC11xx/serial_lld.h.

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Typedef Documentation

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typedef uint32_t sdflags_t
-
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Serial Driver condition flags type.

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Definition at line 137 of file platforms/LPC11xx/serial_lld.h.

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Function Documentation

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CH_IRQ_HANDLER (Vector94  ) 
-
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UART0 IRQ handler.

- -

Definition at line 222 of file platforms/LPC11xx/serial_lld.c.

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References CH_IRQ_EPILOGUE, and CH_IRQ_PROLOGUE.

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void sd_lld_init (void  ) 
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Low level serial driver initialization.

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void sd_lld_start (SerialDriver *  sdp,
const SerialConfig *  config 
)
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Low level serial driver configuration and (re)start.

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Parameters:
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[in] sdp pointer to a SerialDriver object
[in] config the architecture-dependent serial driver configuration. If this parameter is set to NULL then a default configuration is used.
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void sd_lld_stop (SerialDriver *  sdp ) 
-
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Low level serial driver stop.

-

De-initializes the UART, stops the associated clock, resets the interrupt vector.

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Parameters:
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[in] sdp pointer to a SerialDriver object
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Variable Documentation

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SerialDriver SD1
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UART0 serial driver identifier.

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Definition at line 46 of file platforms/LPC11xx/serial_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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LPC13xx Support
- -[ARM Cortex-Mx] -

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LPC13xx specific support. -More...

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-Collaboration diagram for LPC13xx Support:
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Description

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LPC13xx specific support.

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The LPC13xx support includes:

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-Modules

 LPC13xx HAL Support
 

HAL support.

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 LPC13xx I/O Ports Support
 

I/O Ports peripherals support.

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 LPC13xx UART Support
 

UART peripherals support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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LPC13xx HAL Support
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HAL support. -More...

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Description

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HAL support.

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-Defines

#define FLASHCFG   (*((volatile uint32_t *)0x4003C010))
 Register missing in NXP header file.
#define PLATFORM_NAME   "LPC13xx"
 Platform name.
#define IRCOSCCLK   12000000
#define WDGOSCCLK   1600000
#define SYSPLLCLKSEL_IRCOSC   0
#define SYSPLLCLKSEL_SYSOSC   1
#define SYSMAINCLKSEL_IRCOSC   0
#define SYSMAINCLKSEL_PLLIN   1
#define SYSMAINCLKSEL_WDGOSC   2
#define SYSMAINCLKSEL_PLLOUT   3
#define LPC13xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC
 System PLL clock source.
#define LPC13xx_SYSPLL_MUL   6
 System PLL multiplier.
#define LPC13xx_SYSPLL_DIV   4
 System PLL divider.
#define LPC13xx_MAINCLK_SOURCE   SYSMAINCLKSEL_PLLOUT
 System main clock source.
#define LPC13xx_SYSABHCLK_DIV   1
 AHB clock divider.
#define LPC13xx_UART_PCLK_DIV   1
 UART clock divider.
#define LPC13xx_SYSOSCCTRL   0
 Calculated SYSOSCCTRL setting.
#define LPC13xx_SYSPLLCLKIN   SYSOSCCLK
 PLL input clock frequency.
#define LPC13xx_SYSPLLCTRL_MSEL   (LPC13xx_SYSPLL_MUL - 1)
 MSEL mask in SYSPLLCTRL register.
#define LPC13xx_SYSPLLCTRL_PSEL   (0 << 5)
 PSEL mask in SYSPLLCTRL register.
#define LPC13xx_SYSPLLCCO
 CCP frequency.
#define LPC13xx_SYSPLLCLKOUT   (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV)
 PLL output clock frequency.
#define LPC13xx_SYSCLK   (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV)
 AHB clock.
#define LPC13xx_FLASHCFG_FLASHTIM   0
 Flash wait states.
#define LPC13xx_UART_PCLK   (LPC13xx_MAINCLK / LPC13xx_UART_PCLK_DIV)
 UART clock.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void LPC13xx_clock_init (void)
 LPC13xx clocks and PLL initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
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Define Documentation

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Register missing in NXP header file.

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Definition at line 41 of file platforms/LPC13xx/hal_lld.c.

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Platform name.

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Definition at line 48 of file platforms/LPC13xx/hal_lld.h.

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#define IRCOSCCLK   12000000
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High speed internal clock.

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#define WDGOSCCLK   1600000
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Watchdog internal clock.

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Definition at line 51 of file platforms/LPC13xx/hal_lld.h.

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#define SYSPLLCLKSEL_IRCOSC   0
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Internal RC oscillator clock source.

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Definition at line 53 of file platforms/LPC13xx/hal_lld.h.

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#define SYSPLLCLKSEL_SYSOSC   1
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System oscillator clock source.

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Definition at line 55 of file platforms/LPC13xx/hal_lld.h.

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#define SYSMAINCLKSEL_IRCOSC   0
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Clock source is IRC.

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Definition at line 58 of file platforms/LPC13xx/hal_lld.h.

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#define SYSMAINCLKSEL_PLLIN   1
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Clock source is PLLIN.

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Definition at line 59 of file platforms/LPC13xx/hal_lld.h.

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#define SYSMAINCLKSEL_WDGOSC   2
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Clock source is WDGOSC.

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Definition at line 60 of file platforms/LPC13xx/hal_lld.h.

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#define SYSMAINCLKSEL_PLLOUT   3
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Clock source is PLLOUT.

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Definition at line 61 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC
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System PLL clock source.

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Definition at line 71 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSPLL_MUL   6
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System PLL multiplier.

-
Note:
The value must be in the 1..32 range and the final frequency must not exceed the CCO ratings.
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Definition at line 80 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSPLL_DIV   4
-
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System PLL divider.

-
Note:
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Definition at line 88 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_MAINCLK_SOURCE   SYSMAINCLKSEL_PLLOUT
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System main clock source.

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Definition at line 95 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSABHCLK_DIV   1
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AHB clock divider.

-
Note:
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Definition at line 103 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_UART_PCLK_DIV   1
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UART clock divider.

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Note:
The value must be chosen between (1...255).
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Definition at line 111 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSOSCCTRL   0
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Calculated SYSOSCCTRL setting.

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Definition at line 122 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSPLLCLKIN   SYSOSCCLK
-
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PLL input clock frequency.

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Definition at line 131 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSPLLCTRL_MSEL   (LPC13xx_SYSPLL_MUL - 1)
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MSEL mask in SYSPLLCTRL register.

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Definition at line 143 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSPLLCTRL_PSEL   (0 << 5)
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PSEL mask in SYSPLLCTRL register.

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Definition at line 152 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSPLLCCO
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(LPC13xx_SYSPLLCLKIN * LPC13xx_SYSPLL_MUL *    \
-                              LPC13xx_SYSPLL_DIV)
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CCP frequency.

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Definition at line 166 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSPLLCLKOUT   (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV)
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PLL output clock frequency.

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Definition at line 176 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_SYSCLK   (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV)
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AHB clock.

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Definition at line 193 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_FLASHCFG_FLASHTIM   0
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Flash wait states.

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Definition at line 202 of file platforms/LPC13xx/hal_lld.h.

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#define LPC13xx_UART_PCLK   (LPC13xx_MAINCLK / LPC13xx_UART_PCLK_DIV)
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UART clock.

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Definition at line 212 of file platforms/LPC13xx/hal_lld.h.

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Function Documentation

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void hal_lld_init (void  ) 
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Low level HAL driver initialization.

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void LPC13xx_clock_init (void  ) 
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LPC13xx clocks and PLL initialization.

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Note:
All the involved constants come from the file board.h.
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Variable Documentation

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const PALConfig pal_default_config
-
-
-Initial value:
 {
- {VAL_GPIO0DATA, VAL_GPIO0DIR},
- {VAL_GPIO1DATA, VAL_GPIO1DIR},
- {VAL_GPIO2DATA, VAL_GPIO2DIR},
- {VAL_GPIO3DATA, VAL_GPIO3DIR},
-}
-
-

PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 55 of file platforms/LPC13xx/hal_lld.c.

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- - diff --git a/ChibiOS_2.0.8/docs/html/group___l_p_c13xx___h_a_l.png b/ChibiOS_2.0.8/docs/html/group___l_p_c13xx___h_a_l.png deleted file mode 100644 index 2362d66..0000000 Binary files a/ChibiOS_2.0.8/docs/html/group___l_p_c13xx___h_a_l.png and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/group___l_p_c13xx___p_a_l.html b/ChibiOS_2.0.8/docs/html/group___l_p_c13xx___p_a_l.html deleted file mode 100644 index a5e440d..0000000 --- a/ChibiOS_2.0.8/docs/html/group___l_p_c13xx___p_a_l.html +++ /dev/null @@ -1,851 +0,0 @@ - - -ChibiOS/RT: LPC13xx I/O Ports Support - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions
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LPC13xx I/O Ports Support
- -[LPC13xx Support] -

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I/O Ports peripherals support. -More...

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-Collaboration diagram for LPC13xx I/O Ports Support:
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Description

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I/O Ports peripherals support.

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This module supports the LPC13xx GPIO controller. The controller supports the following features (see PAL Driver):

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  • 12 bits wide ports.
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  • Atomic set/reset functions.
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  • Atomic set+reset function (atomic bus operations).
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  • Output latched regardless of the pad setting.
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  • Direct read of input pads regardless of the pad setting.
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Supported Setup Modes

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  • PAL_MODE_RESET.
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  • PAL_MODE_UNCONNECTED.
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  • PAL_MODE_INPUT.
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  • PAL_MODE_OUTPUT_PUSHPULL.
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Any attempt to setup an invalid mode is ignored.

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Suboptimal Behavior

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Some GPIO features are less than optimal:

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  • Pad/port toggling operations are not atomic.
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  • Pull-up and Pull-down resistors cannot be programmed through the PAL driver and must be programmed separately.
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  • Reading of the output latch for pads programmed as input is not possible, the input pin value is returned instead.
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-Data Structures

struct  LPC13xx_gpio_setup_t
 GPIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFF)
 Whole port mask.
#define IOPORT1   LPC_GPIO0
 GPIO0 port identifier.
#define IOPORT2   LPC_GPIO1
 GPIO1 port identifier.
#define IOPORT3   LPC_GPIO2
 GPIO2 port identifier.
#define IOPORT4   LPC_GPIO3
 GPIO3 port identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->DATA)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->DATA)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->DATA = (bits))
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0)
 Clears a bits mask on a I/O port.
#define pal_lld_readgroup(port, mask, offset)   ((port)->MASKED_ACCESS[(mask) << (offset)])
 Reads a group of bits.
#define pal_lld_writegroup(port, mask, offset, bits)   ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad))
 Writes a logical state on an output pad.
#define pal_lld_setpad(port, pad)   ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
 Sets a pad logical state to PAL_HIGH.
#define pal_lld_clearpad(port, pad)   ((port)->MASKED_ACCESS[1 << (pad)] = 0)
 Clears a pad logical state to PAL_LOW.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef LPC_GPIO_TypeDef * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 LPC13xx I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
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Define Documentation

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#define PAL_IOPORTS_WIDTH   32
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Width, in bits, of an I/O port.

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Definition at line 89 of file platforms/LPC13xx/pal_lld.h.

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#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFF)
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Whole port mask.

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This macro specifies all the valid bits into a port.

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Definition at line 95 of file platforms/LPC13xx/pal_lld.h.

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#define IOPORT1   LPC_GPIO0
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GPIO0 port identifier.

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Definition at line 114 of file platforms/LPC13xx/pal_lld.h.

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#define IOPORT2   LPC_GPIO1
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GPIO1 port identifier.

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Definition at line 120 of file platforms/LPC13xx/pal_lld.h.

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#define IOPORT3   LPC_GPIO2
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GPIO2 port identifier.

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Definition at line 126 of file platforms/LPC13xx/pal_lld.h.

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#define IOPORT4   LPC_GPIO3
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GPIO3 port identifier.

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Definition at line 132 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_init( config )    _pal_lld_init(config)
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Low level PAL subsystem initialization.

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Parameters:
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[in] config architecture-dependent ports configuration
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Definition at line 145 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_readport( port )    ((port)->DATA)
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Reads the physical I/O port states.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
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The port bits.
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Definition at line 155 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_readlatch( port )    ((port)->DATA)
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Reads the output latch.

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The purpose of this function is to read back the latched output value.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
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The latched logical states.
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Definition at line 167 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_writeport( port,
 bits 
)   ((port)->DATA = (bits))
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Writes a bits mask on a I/O port.

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This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] bits bits to be written on the specified port
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Definition at line 177 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_setport( port,
 bits 
)   ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
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Sets a bits mask on a I/O port.

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Note:
This function is not meant to be invoked directly by the application code.
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-The PAL Driver provides a default software implementation of this functionality, implement this function if can optimize it by using special hardware functionalities or special coding.
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[in] port port identifier
[in] bits bits to be ORed on the specified port
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Definition at line 190 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_clearport( port,
 bits 
)   ((port)->MASKED_ACCESS[bits] = 0)
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Clears a bits mask on a I/O port.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] bits bits to be cleared on the specified port
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Definition at line 203 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_readgroup( port,
 mask,
 offset 
)   ((port)->MASKED_ACCESS[(mask) << (offset)])
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Reads a group of bits.

-
Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] mask group mask
[in] offset group bit offset within the port
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The group logical states.
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Definition at line 218 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_writegroup( port,
 mask,
 offset,
 bits 
)   ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
-
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Writes a group of bits.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] mask group mask
[in] offset group bit offset within the port
[in] bits bits to be written. Values exceeding the group width are masked.
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Definition at line 235 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_setgroupmode( port,
 mask,
 mode 
)   _pal_lld_setgroupmode(port, mask, mode)
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Pads group mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] mask group mask
[in] mode group mode
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Definition at line 250 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_writepad( port,
 pad,
 bit 
)   ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad))
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Writes a logical state on an output pad.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] pad pad number within the port
[out] bit logical value, the value must be PAL_LOW or PAL_HIGH
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Definition at line 266 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_setpad( port,
 pad 
)   ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
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Sets a pad logical state to PAL_HIGH.

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This function is not meant to be invoked directly by the application code.
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[in] pad pad number within the port
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Definition at line 280 of file platforms/LPC13xx/pal_lld.h.

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#define pal_lld_clearpad( port,
 pad 
)   ((port)->MASKED_ACCESS[1 << (pad)] = 0)
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Clears a pad logical state to PAL_LOW.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] pad pad number within the port
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Definition at line 294 of file platforms/LPC13xx/pal_lld.h.

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Typedef Documentation

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typedef uint32_t ioportmask_t
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Digital I/O port sized unsigned type.

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Definition at line 100 of file platforms/LPC13xx/pal_lld.h.

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Port Identifier.

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Definition at line 105 of file platforms/LPC13xx/pal_lld.h.

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Function Documentation

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void _pal_lld_init (const PALConfig *  config ) 
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LPC13xx I/O ports configuration.

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GPIO unit registers initialization.

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void _pal_lld_setgroupmode (ioportid_t  port,
ioportmask_t  mask,
uint_fast8_t  mode 
)
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Pads mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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[in] port the port identifier
[in] mask the group mask
[in] mode the mode
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This function is not meant to be invoked directly by the application code.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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LPC13xx UART Support
- -[LPC13xx Support] -

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UART peripherals support. -More...

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-Collaboration diagram for LPC13xx UART Support:
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Description

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UART peripherals support.

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The serial driver supports the LPC13xx UART taking advantage of its deep hardware buffers.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_LPC13xx_UART0   TRUE
 UART0 driver enable switch.
#define LPC13xx_UART_FIFO_PRELOAD   16
 FIFO preload parameter.
#define LPC13xx_UART0_PRIORITY   3
 UART0 interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

 CH_IRQ_HANDLER (VectorF8)
 UART0 IRQ handler.
void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 UART0 serial driver identifier.
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Define Documentation

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#define USE_LPC13xx_UART0   TRUE
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UART0 driver enable switch.

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If set to TRUE the support for UART0 is included.

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Definition at line 99 of file platforms/LPC13xx/serial_lld.h.

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#define LPC13xx_UART_FIFO_PRELOAD   16
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FIFO preload parameter.

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Configuration parameter, this values defines how many bytes are preloaded in the HW transmit FIFO for each interrupt, the maximum value is 16 the minimum is 1.

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Note:
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Definition at line 112 of file platforms/LPC13xx/serial_lld.h.

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#define LPC13xx_UART0_PRIORITY   3
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UART0 interrupt priority level setting.

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Definition at line 119 of file platforms/LPC13xx/serial_lld.h.

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#define _serial_driver_data
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_base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Status Change @p EventSource.*/                                        \
-  EventSource               sevent;                                         \
-  /* I/O driver status flags.*/                                             \
-  sdflags_t                 flags;                                          \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_UART_TypeDef        *uart;
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SerialDriver specific data.

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Definition at line 162 of file platforms/LPC13xx/serial_lld.h.

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Typedef Documentation

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typedef uint32_t sdflags_t
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Serial Driver condition flags type.

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Definition at line 137 of file platforms/LPC13xx/serial_lld.h.

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Function Documentation

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CH_IRQ_HANDLER (VectorF8  ) 
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UART0 IRQ handler.

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Definition at line 222 of file platforms/LPC13xx/serial_lld.c.

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References CH_IRQ_EPILOGUE, and CH_IRQ_PROLOGUE.

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void sd_lld_init (void  ) 
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Low level serial driver initialization.

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void sd_lld_start (SerialDriver *  sdp,
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)
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Low level serial driver configuration and (re)start.

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Parameters:
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[in] sdp pointer to a SerialDriver object
[in] config the architecture-dependent serial driver configuration. If this parameter is set to NULL then a default configuration is used.
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void sd_lld_stop (SerialDriver *  sdp ) 
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Low level serial driver stop.

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De-initializes the UART, stops the associated clock, resets the interrupt vector.

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[in] sdp pointer to a SerialDriver object
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Variable Documentation

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SerialDriver SD1
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UART0 serial driver identifier.

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Definition at line 46 of file platforms/LPC13xx/serial_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Modules
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LPC214x Support
- -[ARM7TDMI] -

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LPC214x specific support. -More...

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-Collaboration diagram for LPC214x Support:
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Description

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LPC214x specific support.

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The LPC214x support includes:

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  • VIC support code.
    • -
  • I/O ports driver.
    • -
  • Buffered, interrupt driven, serial driver.
    • -
  • SPI driver.
    • -
  • A demo supporting the kernel test suite.
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  • A C++ demo supporting the kernel test suite.
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  • A demo integrating ChibiOS/RT with FatFS.
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-Modules

 VIC Support
 

VIC peripheral support.

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 LPC214x HAL Support
 

HAL support.

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 LPC214x I/O Ports Support
 

I/O Ports peripherals support.

-
 LPC214x UART Support
 

UART peripherals support.

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 LPC214x SPI Support
 

SSP peripheral support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines | -Functions | -Variables
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LPC214x HAL Support
- -[LPC214x Support] -

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HAL support. -More...

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-Collaboration diagram for LPC214x HAL Support:
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Description

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HAL support.

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-Defines

#define PLATFORM_NAME   "LPC214x"
 Platform name.
#define LPC214x_NON_VECTORED_IRQ_HOOK()
 Default action for the non vectored IRQ handler, nothing.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void lpc214x_clock_init (void)
 LPC214x clocks and PLL initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
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Define Documentation

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#define PLATFORM_NAME   "LPC214x"
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Platform name.

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Definition at line 47 of file platforms/LPC214x/hal_lld.h.

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Default action for the non vectored IRQ handler, nothing.

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Definition at line 57 of file platforms/LPC214x/hal_lld.h.

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Function Documentation

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void hal_lld_init (void  ) 
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Low level HAL driver initialization.

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void lpc214x_clock_init (void  ) 
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LPC214x clocks and PLL initialization.

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Note:
All the involved constants come from the file board.h.
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Variable Documentation

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const PALConfig pal_default_config
-
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-Initial value:
-{
-  VAL_PINSEL0,
-  VAL_PINSEL1,
-  VAL_PINSEL2,
-  {VAL_FIO0PIN, VAL_FIO0DIR},
-  {VAL_FIO1PIN, VAL_FIO1DIR}
-}
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PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 49 of file platforms/LPC214x/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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LPC214x I/O Ports Support
- -[LPC214x Support] -

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I/O Ports peripherals support. -More...

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-Collaboration diagram for LPC214x I/O Ports Support:
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Description

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I/O Ports peripherals support.

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This module supports the LPC214x FIO controller. The controller supports the following features (see PAL Driver):

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  • 32 bits wide ports.
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Supported Setup Modes

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  • PAL_MODE_RESET.
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    • -
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    • -
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Any attempt to setup an invalid mode is ignored.

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Suboptimal Behavior

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-Data Structures

struct  lpc214x_fio_setup_t
 FIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define IOPORT1   FIO0Base
 FIO port 0 identifier.
#define IOPORT2   FIO1Base
 FIO port 1 identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 FIO subsystem initialization.
#define pal_lld_readport(port)   ((port)->FIO_PIN)
 Reads an I/O port.
#define pal_lld_readlatch(port)   ((port)->FIO_SET)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->FIO_PIN = (bits))
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)   ((port)->FIO_SET = (bits))
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)   ((port)->FIO_CLR = (bits))
 Clears a bits mask on a I/O port.
#define pal_lld_writegroup(port, mask, offset, bits)
 Writes a value on an I/O bus.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   pal_lld_writegroup(port, 1, pad, bit)
 Writes a logical state on an output pad.
#define pal_lld_lpc214x_set_direction(port, dir)
 FIO port setup.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef FIO * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 LPC214x I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Define Documentation

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#define PAL_IOPORTS_WIDTH   32
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Width, in bits, of an I/O port.

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Definition at line 84 of file platforms/LPC214x/pal_lld.h.

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#define IOPORT1   FIO0Base
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FIO port 0 identifier.

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Definition at line 103 of file platforms/LPC214x/pal_lld.h.

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#define IOPORT2   FIO1Base
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FIO port 1 identifier.

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Definition at line 108 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_init( config )    _pal_lld_init(config)
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FIO subsystem initialization.

-

Enables the access through the fast registers.

- -

Definition at line 119 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_readport( port )    ((port)->FIO_PIN)
-
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Reads an I/O port.

-

This function is implemented by reading the FIO PIN register, the implementation has no side effects.

-
Parameters:
- - -
[in] port the port identifier
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Returns:
the port bits
-
Note:
This function is not meant to be invoked directly by the application code.
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Definition at line 132 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_readlatch( port )    ((port)->FIO_SET)
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Reads the output latch.

-

This function is implemented by reading the FIO SET register, the implementation has no side effects.

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- - -
[in] port the port identifier
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Returns:
The latched logical states.
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Note:
This function is not meant to be invoked directly by the application code.
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Definition at line 145 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_writeport( port,
 bits 
)   ((port)->FIO_PIN = (bits))
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Writes a bits mask on a I/O port.

-

This function is implemented by writing the FIO PIN register, the implementation has no side effects.

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Parameters:
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[in] port the port identifier
[in] bits the bits to be written on the specified port
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This function is not meant to be invoked directly by the application code.
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Definition at line 158 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_setport( port,
 bits 
)   ((port)->FIO_SET = (bits))
-
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Sets a bits mask on a I/O port.

-

This function is implemented by writing the FIO SET register, the implementation has no side effects.

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Parameters:
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[in] port the port identifier
[in] bits the bits to be ORed on the specified port
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This function is not meant to be invoked directly by the application code.
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Definition at line 171 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_clearport( port,
 bits 
)   ((port)->FIO_CLR = (bits))
-
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Clears a bits mask on a I/O port.

-

This function is implemented by writing the FIO CLR register, the implementation has no side effects.

-
Parameters:
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[in] port the port identifier
[in] bits the bits to be cleared on the specified port
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Note:
This function is not meant to be invoked directly by the application code.
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Definition at line 184 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_writegroup( port,
 mask,
 offset,
 bits 
)
-
-
-Value:
{                  \
-  (port)->FIO_MASK = ~((mask) << (offset));                             \
-  (port)->FIO_PIN = (bits) << (offset);                                 \
-  (port)->FIO_MASK = 0;                                                 \
-}
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Writes a value on an I/O bus.

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This function is implemented by writing the FIO PIN and MASK registers, the implementation is not atomic because the multiple accesses.

-
Parameters:
- - - - - -
[in] port the port identifier
[in] mask the group mask, a logical AND is performed on the output data
[in] offset the group bit offset within the port
[in] bits the bits to be written. Values exceeding the group width are masked.
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This function is not meant to be invoked directly by the application code.
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Definition at line 202 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_setgroupmode( port,
 mask,
 mode 
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Pads group mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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[in] port the port identifier
[in] mask the group mask
[in] mode the mode
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Note:
This function is not meant to be invoked directly by the application code.
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Definition at line 224 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_writepad( port,
 pad,
 bit 
)   pal_lld_writegroup(port, 1, pad, bit)
-
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Writes a logical state on an output pad.

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Parameters:
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[in] port the port identifier
[in] pad the pad number within the port
[out] bit the logical value, the value must be 0 or 1
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This function is not meant to be invoked directly by the application code.
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Definition at line 237 of file platforms/LPC214x/pal_lld.h.

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#define pal_lld_lpc214x_set_direction( port,
 dir 
)
-
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{                      \
-  (port)->FIO_DIR = (dir);                                              \
-}
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FIO port setup.

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This function programs the pins direction within a port.

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Definition at line 243 of file platforms/LPC214x/pal_lld.h.

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Typedef Documentation

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typedef uint32_t ioportmask_t
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Digital I/O port sized unsigned type.

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Definition at line 89 of file platforms/LPC214x/pal_lld.h.

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typedef FIO* ioportid_t
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Port Identifier.

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Definition at line 94 of file platforms/LPC214x/pal_lld.h.

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Function Documentation

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void _pal_lld_init (const PALConfig *  config ) 
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LPC214x I/O ports configuration.

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FIO units and PINSEL registers initialization.

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void _pal_lld_setgroupmode (ioportid_t  port,
ioportmask_t  mask,
uint_fast8_t  mode 
)
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Pads mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

-
Parameters:
- - - - -
[in] port the port identifier
[in] mask the group mask
[in] mode the mode
-
-
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Note:
This function is not meant to be invoked directly by the application code.
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Variable Documentation

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const PALConfig pal_default_config
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PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 49 of file platforms/AT91SAM7/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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LPC214x UART Support
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UART peripherals support. -More...

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Description

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UART peripherals support.

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The serial driver supports the LPC214x UART peripherals.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_LPC214x_UART0   TRUE
 UART0 driver enable switch.
#define USE_LPC214x_UART1   TRUE
 UART1 driver enable switch.
#define LPC214x_UART_FIFO_PRELOAD   16
 FIFO preload parameter.
#define LPC214x_UART0_PRIORITY   1
 UART0 interrupt priority level setting.
#define LPC214x_UART1_PRIORITY   2
 UART1 interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

 CH_IRQ_HANDLER (UART0IrqHandler)
 UART0 IRQ handler.
 CH_IRQ_HANDLER (UART1IrqHandler)
 UART1 IRQ handler.
void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 UART0 serial driver identifier.
SerialDriver SD2
 UART1 serial driver identifier.
-

Define Documentation

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#define USE_LPC214x_UART0   TRUE
-
-
- -

UART0 driver enable switch.

-

If set to TRUE the support for UART0 is included.

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Note:
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Definition at line 54 of file platforms/LPC214x/serial_lld.h.

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#define USE_LPC214x_UART1   TRUE
-
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UART1 driver enable switch.

-

If set to TRUE the support for UART1 is included.

-
Note:
The default is TRUE.
- -

Definition at line 63 of file platforms/LPC214x/serial_lld.h.

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#define LPC214x_UART_FIFO_PRELOAD   16
-
-
- -

FIFO preload parameter.

-

Configuration parameter, this values defines how many bytes are preloaded in the HW transmit FIFO for each interrupt, the maximum value is 16 the minimum is 1.

-
Note:
An high value reduces the number of interrupts generated but can also increase the worst case interrupt response time because the preload loops.
- -

Definition at line 76 of file platforms/LPC214x/serial_lld.h.

- -
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-
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#define LPC214x_UART0_PRIORITY   1
-
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UART0 interrupt priority level setting.

- -

Definition at line 83 of file platforms/LPC214x/serial_lld.h.

- -
-
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-
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#define LPC214x_UART1_PRIORITY   2
-
-
- -

UART1 interrupt priority level setting.

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_base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Status Change @p EventSource.*/                                        \
-  EventSource               sevent;                                         \
-  /* I/O driver status flags.*/                                             \
-  sdflags_t                 flags;                                          \
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-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
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SerialDriver specific data.

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Serial Driver condition flags type.

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Definition at line 108 of file platforms/LPC214x/serial_lld.h.

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UART0 IRQ handler.

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Definition at line 238 of file platforms/LPC214x/serial_lld.c.

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UART1 IRQ handler.

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Low level serial driver configuration and (re)start.

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UART0 serial driver identifier.

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UART1 serial driver identifier.

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Definition at line 51 of file platforms/LPC214x/serial_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Functions | -Variables
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LPC214x SPI Support
- -[LPC214x Support] -

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SSP peripheral support. -More...

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-Collaboration diagram for LPC214x SPI Support:
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Description

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SSP peripheral support.

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The SPI driver supports the LPC214x SSP, the driver works in polling mode.

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-Data Structures

struct  SPIConfig
 Driver configuration structure. More...
struct  SPIDriver
 Structure representing a SPI driver. More...

-Defines

#define USE_LPC214x_SPI1   TRUE
 SPI1 (SSP) driver enable switch.

-Functions

void rw8 (size_t n, const uint8_t *txbuf, uint8_t *rxbuf)
 Synchronous SSP transfer.
void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.

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SPIDriver SPID1
 SPI1 driver identifier.
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Define Documentation

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#define USE_LPC214x_SPI1   TRUE
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SPI1 (SSP) driver enable switch.

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If set to TRUE the support for SPI0 is included.

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Definition at line 53 of file platforms/LPC214x/spi_lld.h.

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void rw8 (size_t  n,
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Synchronous SSP transfer.

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[in] n number of bytes to be exchanged
[in] txbuf the pointer to the transmit buffer or NULL
[out] rxbuf the pointer to the receive buffer or NULL
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void spi_lld_init (void  ) 
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Low level SPI driver initialization.

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Configures and activates the SPI peripheral.

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Deactivates the SPI peripheral.

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Asserts the slave select signal and prepares for transfers.

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Deasserts the slave select signal.

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The previously selected peripheral is unselected.

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Ignores data on the SPI bus.

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This function transmits a series of idle words on the SPI bus and ignores the received data. This function can be invoked even when a slave select signal has not been yet asserted.

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[in] n number of words to be ignored
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void spi_lld_exchange (SPIDriver *  spip,
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void *  rxbuf 
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Exchanges data on the SPI bus.

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This function performs a simultaneous transmit/receive operation.

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[in] spip pointer to the SPIDriver object
[in] n number of words to be exchanged
[in] txbuf the pointer to the transmit buffer
[out] rxbuf the pointer to the receive buffer
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void spi_lld_send (SPIDriver *  spip,
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Sends data ever the SPI bus.

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[in] n number of words to send
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void spi_lld_receive (SPIDriver *  spip,
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Receives data from the SPI bus.

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[in] spip pointer to the SPIDriver object
[in] n number of words to receive
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Variable Documentation

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SPIDriver SPID1
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SPI1 driver identifier.

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Definition at line 45 of file platforms/LPC214x/spi_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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VIC Support
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VIC peripheral support. -More...

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Description

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VIC peripheral support.

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-Functions

void vic_init (void)
 VIC Initialization.
void SetVICVector (void *handler, int vector, int source)
 Initializes a VIC vector.
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Function Documentation

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void vic_init (void  ) 
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VIC Initialization.

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void SetVICVector (void *  handler,
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Initializes a VIC vector.

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Set a vector for an interrupt source and enables it.

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[in] handler the pointer to the IRQ service routine
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[in] source the IRQ source to be associated to the vector
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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MAC Driver
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Generic MAC driver. -More...

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Generic MAC driver.

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This module implements a generic interface for MAC (Media Access Control) drivers, as example Ethernet controllers.

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 MAC Low Level Driver
 

MAC Driver low level driver template.

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-Defines

#define macGetReceiveEventSource(macp)   (&(macp)->md_rdevent)
 Returns the received frames event source.
#define macWriteTransmitDescriptor(tdp, buf, size)   mac_lld_write_transmit_descriptor(tdp, buf, size)
 Writes to a transmit descriptor's stream.
#define macReadReceiveDescriptor(rdp, buf, size)   mac_lld_read_receive_descriptor(rdp, buf, size)
 Reads from a receive descriptor's stream.

-Functions

void macInit (void)
 MAC Driver initialization.
void macObjectInit (MACDriver *macp)
 Initialize the standard part of a MACDriver structure.
void macSetAddress (MACDriver *macp, const uint8_t *p)
 MAC address setup.
msg_t macWaitTransmitDescriptor (MACDriver *macp, MACTransmitDescriptor *tdp, systime_t time)
 Allocates a transmission descriptor.
void macReleaseTransmitDescriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t macWaitReceiveDescriptor (MACDriver *macp, MACReceiveDescriptor *rdp, systime_t time)
 Waits for a received frame.
void macReleaseReceiveDescriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t macPollLinkStatus (MACDriver *macp)
 Updates and returns the link status.
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#define macGetReceiveEventSource( macp )    (&(macp)->md_rdevent)
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Definition at line 72 of file mac.h.

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Reads from a receive descriptor's stream.

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Definition at line 99 of file mac.h.

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void macInit (void  ) 
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MAC Driver initialization.

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Definition at line 63 of file mac.c.

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References mac_lld_init().

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void macObjectInit (MACDriver *  macp ) 
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Definition at line 73 of file mac.c.

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MAC address setup.

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[in] macp pointer to the MACDriver object
[in] p pointer to a six bytes buffer containing the MAC address. If this parameter is set to NULL then MAC a system default is used.
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Definition at line 93 of file mac.c.

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msg_t macWaitTransmitDescriptor (MACDriver *  macp,
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Allocates a transmission descriptor.

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One of the available transmission descriptors is locked and returned. If a descriptor is not currently available then the invoking thread is queued until one is freed.

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Definition at line 115 of file mac.c.

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Definition at line 139 of file mac.c.

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msg_t macWaitReceiveDescriptor (MACDriver *  macp,
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Waits for a received frame.

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Definition at line 161 of file mac.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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MAC Low Level Driver
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MAC Driver low level driver template. -More...

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Description

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MAC Driver low level driver template.

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This file is a template for a MAC low level driver.

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-Data Structures

struct  MACDriver
 Structure representing a MAC driver. More...
struct  MACTransmitDescriptor
 Structure representing a transmit descriptor. More...
struct  MACReceiveDescriptor
 Structure representing a receive descriptor. More...

-Defines

#define MAC_TRANSMIT_BUFFERS   2
 Number of available transmit buffers.
#define MAC_RECEIVE_BUFFERS   2
 Number of available receive buffers.
#define MAC_BUFFERS_SIZE   1518
 Maximum supported frame size.

-Functions

void mac_lld_init (void)
 Low level MAC initialization.
void mac_lld_set_address (MACDriver *macp, const uint8_t *p)
 Low level MAC address setup.
msg_t max_lld_get_transmit_descriptor (MACDriver *macp, MACTransmitDescriptor *tdp)
 Returns a transmission descriptor.
size_t mac_lld_write_transmit_descriptor (MACTransmitDescriptor *tdp, uint8_t *buf, size_t size)
 Writes to a transmit descriptor's stream.
void mac_lld_release_transmit_descriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t max_lld_get_receive_descriptor (MACDriver *macp, MACReceiveDescriptor *rdp)
 Returns a receive descriptor.
size_t mac_lld_read_receive_descriptor (MACReceiveDescriptor *rdp, uint8_t *buf, size_t size)
 Reads from a receive descriptor's stream.
void mac_lld_release_receive_descriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t mac_lld_poll_link_status (MACDriver *macp)
 Updates and returns the link status.
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Define Documentation

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#define MAC_TRANSMIT_BUFFERS   2
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Number of available transmit buffers.

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Definition at line 52 of file templates/mac_lld.h.

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Number of available receive buffers.

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Definition at line 59 of file templates/mac_lld.h.

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Maximum supported frame size.

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Function Documentation

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void mac_lld_init (void  ) 
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Low level MAC initialization.

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Low level MAC address setup.

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Referenced by macSetAddress().

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msg_t max_lld_get_transmit_descriptor (MACDriver *  macp,
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Returns a transmission descriptor.

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One of the available transmission descriptors is locked and returned.

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Referenced by macWaitTransmitDescriptor().

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Writes to a transmit descriptor's stream.

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Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.

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Referenced by macReleaseTransmitDescriptor().

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Returns a receive descriptor.

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Referenced by macWaitReceiveDescriptor().

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Reads from a receive descriptor's stream.

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Releases a receive descriptor.

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Referenced by macReleaseReceiveDescriptor().

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The link status.
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TRUE if the link is active.
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Referenced by macPollLinkStatus().

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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MMC over SPI Driver
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Generic MMC driver. -More...

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Description

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Generic MMC driver.

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This module implements a portable MMC driver that uses a SPI driver as physical layer.
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The MMC drivers currently supports only cards with capacity up to 2GB and does not implement CRC checking. Hot plugging and removal are supported through kernel events.

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-Data Structures

struct  MMCConfig
 Driver configuration structure. More...
struct  MMCDriver
 Structure representing a MMC driver. More...

-Defines

#define MMC_SECTOR_SIZE   512
 Block size for MMC transfers.
#define MMC_NICE_WAITING   TRUE
 Delays insertions.
#define MMC_POLLING_INTERVAL   10
 Number of positive insertion queries before generating the insertion event.
#define MMC_POLLING_DELAY   10
 Interval, in milliseconds, between insertion queries.
#define mmcGetDriverState(mmcp)   ((mmcp)->mmc_state)
 Returns the driver state.
#define mmcIsWriteProtected(mmcp)   ((mmcp)->mmc_is_protected())
 Returns the write protect status.

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typedef bool_t(* mmcquery_t )(void)
 Function used to query some hardware status bits.

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enum  mmcstate_t {
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Driver state machine possible states.

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void mmcInit (void)
 MMC over SPI driver initialization.
void mmcObjectInit (MMCDriver *mmcp, SPIDriver *spip, const SPIConfig *lscfg, const SPIConfig *hscfg, mmcquery_t is_protected, mmcquery_t is_inserted)
 Initializes an instance.
void mmcStart (MMCDriver *mmcp, const MMCConfig *config)
 Configures and activates the MMC peripheral.
void mmcStop (MMCDriver *mmcp)
 Disables the MMC peripheral.
bool_t mmcConnect (MMCDriver *mmcp)
 Performs the initialization procedure on the inserted card.
bool_t mmcDisconnect (MMCDriver *mmcp)
 Brings the driver in a state safe for card removal.
bool_t mmcStartSequentialRead (MMCDriver *mmcp, uint32_t startblk)
 Starts a sequential read.
bool_t mmcSequentialRead (MMCDriver *mmcp, uint8_t *buffer)
 Reads a block within a sequential read operation.
bool_t mmcStopSequentialRead (MMCDriver *mmcp)
 Stops a sequential read gracefully.
bool_t mmcStartSequentialWrite (MMCDriver *mmcp, uint32_t startblk)
 Starts a sequential write.
bool_t mmcSequentialWrite (MMCDriver *mmcp, const uint8_t *buffer)
 Writes a block within a sequential write operation.
bool_t mmcStopSequentialWrite (MMCDriver *mmcp)
 Stops a sequential write gracefully.
void tmrfunc (void *p)
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Define Documentation

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Definition at line 66 of file mmc_spi.h.

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If enabled this options inserts delays into the MMC waiting routines releasing some extra CPU time for the threads with lower priority, this may slow down the driver a bit however. This option is recommended also if the SPI driver does not use a DMA channel and heavily loads the CPU.

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Definition at line 78 of file mmc_spi.h.

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Reading.

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Definition at line 193 of file mmc_spi.c.

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void mmcObjectInit (MMCDriver *  mmcp,
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Initializes an instance.

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[in] spip pointer to the SPI driver to be used as interface
[in] lscfg low speed configuration for the SPI driver
[in] hscfg high speed configuration for the SPI driver
[in] is_protected function that returns the card write protection setting
[in] is_inserted function that returns the card insertion sensor status
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Definition at line 209 of file mmc_spi.c.

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References chEvtInit, MMCDriver::mmc_config, MMCDriver::mmc_hscfg, MMCDriver::mmc_inserted_event, MMCDriver::mmc_is_inserted, MMCDriver::mmc_is_protected, MMCDriver::mmc_lscfg, MMCDriver::mmc_removed_event, MMCDriver::mmc_spip, and MMCDriver::mmc_state.

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Definition at line 230 of file mmc_spi.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, chVTSetI(), MMCDriver::mmc_cnt, MMCDriver::mmc_config, MMC_POLLING_DELAY, MMCDriver::mmc_state, MMC_STOP, MMCDriver::mmc_vt, MS2ST, and tmrfunc().

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Definition at line 248 of file mmc_spi.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, chVTResetI(), MMC_READING, MMCDriver::mmc_spip, MMCDriver::mmc_state, MMC_STOP, MMC_UNINIT, MMCDriver::mmc_vt, MMC_WRITING, and spiStop().

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bool_t mmcConnect (MMCDriver *  mmcp ) 
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This function should be invoked when a card is inserted and brings the driver in the MMC_READY state where it is possible to perform read and write operations.

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Definition at line 280 of file mmc_spi.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, chThdSleepMilliseconds, MMCDriver::mmc_hscfg, MMC_INSERTED, MMCDriver::mmc_lscfg, MMC_READY, MMC_SECTOR_SIZE, MMCDriver::mmc_spip, MMCDriver::mmc_state, MMC_STOP, MMC_UNINIT, spiIgnore(), and spiStart().

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bool_t mmcDisconnect (MMCDriver *  mmcp ) 
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Definition at line 352 of file mmc_spi.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, MMC_INSERTED, MMC_READY, MMCDriver::mmc_spip, MMCDriver::mmc_state, MMC_STOP, MMC_UNINIT, and spiStop().

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bool_t mmcStartSequentialRead (MMCDriver *  mmcp,
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Starts a sequential read.

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Definition at line 387 of file mmc_spi.c.

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References chDbgCheck, chSysLock, chSysUnlock, MMCDriver::mmc_hscfg, MMC_READING, MMC_READY, MMC_SECTOR_SIZE, MMCDriver::mmc_spip, MMCDriver::mmc_state, spiSelect(), spiStart(), and spiUnselect().

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Reads a block within a sequential read operation.

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Definition at line 422 of file mmc_spi.c.

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Definition at line 460 of file mmc_spi.c.

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Definition at line 496 of file mmc_spi.c.

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References chDbgCheck, chSysLock, chSysUnlock, MMCDriver::mmc_hscfg, MMC_READY, MMC_SECTOR_SIZE, MMCDriver::mmc_spip, MMCDriver::mmc_state, MMC_WRITING, spiSelect(), spiStart(), and spiUnselect().

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Definition at line 531 of file mmc_spi.c.

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Definition at line 570 of file mmc_spi.c.

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Definition at line 57 of file mmc_spi.c.

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References chEvtBroadcastI(), chVTSetI(), MMCDriver::mmc_cnt, MMCDriver::mmc_inserted_event, MMCDriver::mmc_is_inserted, MMC_POLLING_DELAY, MMCDriver::mmc_removed_event, MMCDriver::mmc_state, MMCDriver::mmc_vt, and MS2ST.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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MSP430
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Description

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MSP430 port details. This section how the ChibiOS/RT features are implemented on this architecture.

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-Mapping of the System States in the MSP430 port

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The ChibiOS/RT logical System States are mapped as follow in the MSP430 port:

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 Configuration Options
 

MSP430 Configuration Options.

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 Core Port Implementation
 

MSP430 specific port code, structures and macros.

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 MSP430 Drivers
 

Device drivers included in the MSP430 support.

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Configuration Options
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MSP430 Configuration Options. -More...

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MSP430 Configuration Options.

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The MSP430 port allows some architecture-specific configurations settings that can be overridden by redefining them in chconf.h. Usually there is no need to change the default values.

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Core Port Implementation
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MSP430 specific port code, structures and macros. -More...

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MSP430 specific port code, structures and macros.

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#define ENABLE_WFI_IDLE   0
 Enables the use of a wait state in the idle thread loop.
#define CH_ARCHITECTURE_MSP430
 Macro defining the MSP430 architecture.
#define CH_ARCHITECTURE_NAME   "MSP430"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "MSP430"
 Name of the architecture variant (optional).
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   0
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   32
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   interrupt(id) _vect_##id(void)
 IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   asm volatile ("dint" : : : "memory")
 Kernel-lock action.
#define port_unlock()   asm volatile ("eint" : : : "memory")
 Kernel-unlock action.
#define port_lock_from_isr()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   asm volatile ("dint" : : : "memory")
 Disables all the interrupt sources.
#define port_suspend()   asm volatile ("dint" : : : "memory")
 Disables the interrupt sources below kernel-level priority.
#define port_enable()   asm volatile ("eint" : : : "memory")
 Enables all the interrupt sources.
#define port_wait_for_interrupt()
 Enters an architecture-dependent IRQ-waiting mode.
#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef uint16_t stkalign_t
 16 bits stack and memory alignment enforcement.
typedef void * regmsp_t
 Generic MSP430 register.
typedef int16_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint16_t tprio_t
typedef int16_t msg_t
typedef int16_t eventid_t
typedef uint16_t eventmask_t
typedef uint16_t systime_t
typedef int16_t cnt_t

-Functions

void port_switch (Thread *ntp, Thread *otp)
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void port_halt (void)
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void _port_thread_start (void)
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Define Documentation

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#define ENABLE_WFI_IDLE   0
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Per-thread stack overhead for interrupts servicing.

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This constant is used in the calculation of the correct working area size. This value can be zero on those architecture where there is a separate interrupt stack and the stack space between intctx and extctx is known to be zero.

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- -

Definition at line 153 of file ports/GCC/MSP430/chcore.h.

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Enforces a correct alignment for a stack area size value.

- -

Definition at line 159 of file ports/GCC/MSP430/chcore.h.

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-
-
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STACK_ALIGN(sizeof(Thread) +                     \
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Computes the thread working area global size.

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Definition at line 164 of file ports/GCC/MSP430/chcore.h.

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 n 
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-
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Static working area allocation.

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This macro is used to allocate a static thread working area aligned as both position and size.

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Definition at line 174 of file ports/GCC/MSP430/chcore.h.

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-
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IRQ prologue code.

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Definition at line 181 of file ports/GCC/MSP430/chcore.h.

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{                                           \
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-}
-
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IRQ epilogue code.

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This macro must be inserted at the end of all IRQ handlers enabled to invoke system APIs.

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Definition at line 188 of file ports/GCC/MSP430/chcore.h.

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IRQ handler function declaration.

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Definition at line 198 of file ports/GCC/MSP430/chcore.h.

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Port-related initialization code.

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Definition at line 204 of file ports/GCC/MSP430/chcore.h.

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Kernel-lock action.

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Definition at line 212 of file ports/GCC/MSP430/chcore.h.

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Kernel-unlock action.

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Definition at line 220 of file ports/GCC/MSP430/chcore.h.

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Kernel-lock action from an interrupt handler.

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Definition at line 229 of file ports/GCC/MSP430/chcore.h.

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Kernel-unlock action from an interrupt handler.

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Definition at line 238 of file ports/GCC/MSP430/chcore.h.

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Disables all the interrupt sources.

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Definition at line 245 of file ports/GCC/MSP430/chcore.h.

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Disables the interrupt sources below kernel-level priority.

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Definition at line 253 of file ports/GCC/MSP430/chcore.h.

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Enables all the interrupt sources.

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Definition at line 259 of file ports/GCC/MSP430/chcore.h.

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Enters an architecture-dependent IRQ-waiting mode.

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The function is meant to return when an interrupt becomes pending. The simplest implementation is an empty function or macro but this would not take advantage of architecture-specific power saving modes.

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This port function is implemented as inlined code for performance reasons.
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Definition at line 280 of file ports/GCC/MSP430/chcore.h.

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Inline function modifier.

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Definition at line 61 of file ports/GCC/MSP430/chtypes.h.

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ROM constant modifier.

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Definition at line 67 of file ports/GCC/MSP430/chtypes.h.

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Packed structure modifier (within).

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It uses the "packed" GCC attribute.
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Definition at line 73 of file ports/GCC/MSP430/chtypes.h.

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Packed structure modifier (before).

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Empty in this port.
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Definition at line 79 of file ports/GCC/MSP430/chtypes.h.

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Packed structure modifier (after).

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Note:
Empty in this port.
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Definition at line 85 of file ports/GCC/MSP430/chtypes.h.

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Typedef Documentation

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typedef uint16_t stkalign_t
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16 bits stack and memory alignment enforcement.

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Definition at line 66 of file ports/GCC/MSP430/chcore.h.

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Generic MSP430 register.

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Definition at line 71 of file ports/GCC/MSP430/chcore.h.

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Fast boolean type.

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Definition at line 47 of file ports/GCC/MSP430/chtypes.h.

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Thread flags.

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Definition at line 48 of file ports/GCC/MSP430/chtypes.h.

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typedef uint8_t tstate_t
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Thread state.

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Definition at line 49 of file ports/GCC/MSP430/chtypes.h.

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typedef uint8_t trefs_t
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Thread references counter.

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Definition at line 50 of file ports/GCC/MSP430/chtypes.h.

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Thread priority.

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Definition at line 51 of file ports/GCC/MSP430/chtypes.h.

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typedef int16_t msg_t
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Inter-thread message.

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Definition at line 52 of file ports/GCC/MSP430/chtypes.h.

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Event Id.

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Definition at line 53 of file ports/GCC/MSP430/chtypes.h.

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Events mask.

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Definition at line 54 of file ports/GCC/MSP430/chtypes.h.

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-
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System time.

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Definition at line 55 of file ports/GCC/MSP430/chtypes.h.

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-
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Resources counter.

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Definition at line 56 of file ports/GCC/MSP430/chtypes.h.

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Function Documentation

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void port_switch (Thread *  ntp,
Thread *  otp 
)
-
-
- -

Performs a context switch between two threads.

-

This is the most critical code in any port, this function is responsible for the context switch between 2 threads.

-
Note:
The implementation of this code affects directly the context switch performance so optimize here as much as you can.
-
-The function is declared as a weak symbol, it is possible to redefine it in your application code.
-
Parameters:
- - - -
[in] ntp the thread to be switched in
[in] otp the thread to be switched out
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void port_halt (void  ) 
-
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Halts the system.

-

This function is invoked by the operating system when an unrecoverable error is detected (as example because a programming error in the application code that triggers an assertion while in debug mode).

-
Note:
The function is declared as a weak symbol, it is possible to redefine it in your application code.
- -

Definition at line 45 of file ports/GCC/ARMCMx/chcore.c.

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void _port_thread_start (void  ) 
-
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Start a thread by invoking its work function.

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If the work function returns chThdExit() is automatically invoked.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Modules
-
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MSP430 Drivers
- -[MSP430] -

-
-
- -

Device drivers included in the MSP430 support. -More...

- -

-Collaboration diagram for MSP430 Drivers:
-
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- - -
-
-

-

Description

-

Device drivers included in the MSP430 support.

- - - - -

-

- - -

-

- - -

-

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-Modules

 MSP430 HAL Support
 

HAL support.

-
 MSP430 I/O Ports Support
 

I/O Ports peripherals support.

-
 MSP430 USART Support
 

USART support.

-
-
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-Generated on Sun Nov 28 2010 14:09:58 for ChibiOS/RT by doxygen 1.7.1
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines | -Functions | -Variables
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MSP430 HAL Support
- -[MSP430 Drivers] -

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HAL support. -More...

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-Collaboration diagram for MSP430 HAL Support:
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Description

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HAL support.

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-Defines

#define PLATFORM_NAME   "MSP430x16x"
 Platform name.
#define MSP430_USE_CLOCK   MSP430_CLOCK_SOURCE_XT2CLK
 Clock source.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Define Documentation

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#define PLATFORM_NAME   "MSP430x16x"
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Platform name.

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Definition at line 46 of file platforms/MSP430/hal_lld.h.

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#define MSP430_USE_CLOCK   MSP430_CLOCK_SOURCE_XT2CLK
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Clock source.

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The clock source can be selected from:

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  • MSP430_CLOCK_SOURCE_DCOCLK.
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Definition at line 63 of file platforms/MSP430/hal_lld.h.

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Function Documentation

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void hal_lld_init (void  ) 
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Low level HAL driver initialization.

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Variable Documentation

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const PALConfig pal_default_config
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-{
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PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 45 of file platforms/MSP430/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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MSP430 I/O Ports Support
- -[MSP430 Drivers] -

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I/O Ports peripherals support. -More...

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-Collaboration diagram for MSP430 I/O Ports Support:
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Description

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I/O Ports peripherals support.

-

This module supports the MSP430 Digital I/O controller. The controller supports the following features (see PAL Driver):

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    -
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    • -
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Supported Setup Modes

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Any attempt to setup an invalid mode is ignored.

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Suboptimal Behavior

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-Data Structures

struct  port_common_t
 Simplified MSP430 I/O port representation. More...
union  __ioport
 Generic MSP430 I/O port. More...
struct  msp430_dio_setup_t
 Setup registers common to all the MSP430 ports. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   8
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFF)
 Whole port mask.
#define IOPORT1   ((ioportid_t)0x0020)
 I/O port A identifier.
#define IOPORT2   ((ioportid_t)0x0028)
 I/O port B identifier.
#define IOPORT3   ((ioportid_t)0x0018)
 I/O port C identifier.
#define IOPORT4   ((ioportid_t)0x001c)
 I/O port D identifier.
#define IOPORT5   ((ioportid_t)0x0030)
 I/O port E identifier.
#define IOPORT6   ((ioportid_t)0x0034)
 I/O port F identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->iop_common.in.reg_p)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->iop_common.out.reg_p)
 Reads the output latch.
#define pal_lld_writeport(port, bits)
 Writes a bits mask on a I/O port.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.

-Typedefs

typedef uint8_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef union __ioport * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 MSP430 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Define Documentation

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#define PAL_IOPORTS_WIDTH   8
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Width, in bits, of an I/O port.

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Definition at line 129 of file platforms/MSP430/pal_lld.h.

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#define PAL_WHOLE_PORT   ((ioportmask_t)0xFF)
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Whole port mask.

-

This macro specifies all the valid bits into a port.

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Definition at line 135 of file platforms/MSP430/pal_lld.h.

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#define IOPORT1   ((ioportid_t)0x0020)
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I/O port A identifier.

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This port identifier is mapped on the MSP430 port 1 (P1).

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Definition at line 161 of file platforms/MSP430/pal_lld.h.

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I/O port B identifier.

-

This port identifier is mapped on the MSP430 port 2 (P2).

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Definition at line 171 of file platforms/MSP430/pal_lld.h.

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I/O port C identifier.

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This port identifier is mapped on the MSP430 port 3 (P3).

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Definition at line 181 of file platforms/MSP430/pal_lld.h.

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I/O port D identifier.

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This port identifier is mapped on the MSP430 port 4 (P4).

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Definition at line 191 of file platforms/MSP430/pal_lld.h.

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I/O port E identifier.

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This port identifier is mapped on the MSP430 port 5 (P5).

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Definition at line 201 of file platforms/MSP430/pal_lld.h.

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I/O port F identifier.

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This port identifier is mapped on the MSP430 port 6 (P6).

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Definition at line 211 of file platforms/MSP430/pal_lld.h.

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#define pal_lld_init( config )    _pal_lld_init(config)
-
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Low level PAL subsystem initialization.

-

In MSP430 programs all the ports as input.

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[in] config the MSP430 ports configuration
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Definition at line 225 of file platforms/MSP430/pal_lld.h.

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-
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Reads the physical I/O port states.

-

This function is implemented by reading the PxIN register, the implementation has no side effects.

-
Parameters:
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[in] port the port identifier
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The port bits.
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This function is not meant to be invoked directly by the application code.
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Definition at line 238 of file platforms/MSP430/pal_lld.h.

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#define pal_lld_readlatch( port )    ((port)->iop_common.out.reg_p)
-
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Reads the output latch.

-

This function is implemented by reading the PxOUT register, the implementation has no side effects.

-
Parameters:
- - -
[in] port the port identifier
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The latched logical states.
-
Note:
This function is not meant to be invoked directly by the application code.
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Definition at line 251 of file platforms/MSP430/pal_lld.h.

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#define pal_lld_writeport( port,
 bits 
)
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{                                 \
-  (port)->iop_common.out.reg_p = (bits);                                \
-}
-
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Writes a bits mask on a I/O port.

-

This function is implemented by writing the PxOUT register, the implementation has no side effects.

-
Parameters:
- - - -
[in] port the port identifier
[in] bits the bits to be written on the specified port
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Definition at line 264 of file platforms/MSP430/pal_lld.h.

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#define pal_lld_setgroupmode( port,
 mask,
 mode 
)   _pal_lld_setgroupmode(port, mask, mode)
-
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Pads group mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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[in] port the port identifier
[in] mask the group mask
[in] mode the mode
-
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Note:
This function is not meant to be invoked directly by the application code.
-
-PAL_MODE_UNCONNECTED is implemented as output as recommended by the MSP430x1xx Family User's Guide.
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Definition at line 284 of file platforms/MSP430/pal_lld.h.

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Typedef Documentation

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typedef uint8_t ioportmask_t
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Digital I/O port sized unsigned type.

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Definition at line 140 of file platforms/MSP430/pal_lld.h.

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typedef union __ioport* ioportid_t
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Port Identifier.

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This type can be a scalar or some kind of pointer, do not make any assumption about it, use the provided macros when populating variables of this type.

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Definition at line 148 of file platforms/MSP430/pal_lld.h.

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Function Documentation

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void _pal_lld_init (const PALConfig *  config ) 
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MSP430 I/O ports configuration.

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Parameters:
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[in] config the MSP430 ports configuration
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Note:
The PxIFG, PxIE and PxSEL registers are cleared. PxOUT and PxDIR are configured as specified.
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void _pal_lld_setgroupmode (ioportid_t  port,
ioportmask_t  mask,
uint_fast8_t  mode 
)
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Pads mode setup.

-

This function programs a pads group belonging to the same port with the specified mode.

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Parameters:
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[in] port the port identifier
[in] mask the group mask
[in] mode the mode
-
-
-
Note:
This function is not meant to be invoked directly by the application code.
-
-PAL_MODE_UNCONNECTED is implemented as output as recommended by the MSP430x1xx Family User's Guide. Unconnected pads are set to high logic state by default.
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Variable Documentation

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const PALConfig pal_default_config
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PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 49 of file platforms/AT91SAM7/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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MSP430 USART Support
- -[MSP430 Drivers] -

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USART support. -More...

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-Collaboration diagram for MSP430 USART Support:
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Description

-

USART support.

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The serial driver supports both the MSP430 USARTs in asynchronous mode.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_MSP430_USART0   TRUE
 USART0 driver enable switch.
#define USE_MSP430_USART1   TRUE
 USART1 driver enable switch.
#define _serial_driver_data
 SerialDriver specific data.
#define UBR(b)   (SMCLK / (b))
 Macro for baud rate computation.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 USART0 serial driver identifier.
SerialDriver SD2
 USART1 serial driver identifier.
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Define Documentation

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#define USE_MSP430_USART0   TRUE
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USART0 driver enable switch.

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If set to TRUE the support for USART0 is included.

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Note:
The default is TRUE.
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Definition at line 54 of file platforms/MSP430/serial_lld.h.

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#define USE_MSP430_USART1   TRUE
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USART1 driver enable switch.

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If set to TRUE the support for USART1 is included.

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Note:
The default is FALSE.
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Definition at line 63 of file platforms/MSP430/serial_lld.h.

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#define _serial_driver_data
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_base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Status Change @p EventSource.*/                                        \
-  EventSource               sevent;                                         \
-  /* I/O driver status flags.*/                                             \
-  sdflags_t                 flags;                                          \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-
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SerialDriver specific data.

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Definition at line 102 of file platforms/MSP430/serial_lld.h.

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#define UBR( b )    (SMCLK / (b))
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Macro for baud rate computation.

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Note:
Make sure the final baud rate is within tolerance.
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Definition at line 128 of file platforms/MSP430/serial_lld.h.

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Typedef Documentation

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typedef uint8_t sdflags_t
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Serial Driver condition flags type.

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Definition at line 77 of file platforms/MSP430/serial_lld.h.

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Function Documentation

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void sd_lld_init (void  ) 
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Low level serial driver initialization.

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void sd_lld_start (SerialDriver *  sdp,
const SerialConfig *  config 
)
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Low level serial driver configuration and (re)start.

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Parameters:
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[in] sdp pointer to a SerialDriver object
[in] config the architecture-dependent serial driver configuration. If this parameter is set to NULL then a default configuration is used.
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void sd_lld_stop (SerialDriver *  sdp ) 
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Low level serial driver stop.

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De-initializes the USART, stops the associated clock, resets the interrupt vector.

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[in] sdp pointer to a SerialDriver object
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Variable Documentation

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SerialDriver SD1
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USART0 serial driver identifier.

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Definition at line 48 of file platforms/MSP430/serial_lld.c.

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SerialDriver SD2
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USART1 serial driver identifier.

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Definition at line 52 of file platforms/MSP430/serial_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
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-Data Structures | -Modules | -Defines | -Functions
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PAL Driver
- -[HAL] -

-
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I/O Ports Abstraction Layer. -More...

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-Collaboration diagram for PAL Driver:
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Description

-

I/O Ports Abstraction Layer.

-

This module defines an abstract interface for digital I/O ports. Note that most I/O ports functions are just macros. The macros have default software implementations that can be redefined in a PAL Low Level Driver if the target hardware supports special features like, as example, atomic bit set/reset/masking. Please refer to the ports specific documentation for details.
- The PAL Driver has the advantage to make the access to the I/O ports platform independent and still be optimized for the specific architectures.
- Note that the PAL Low Level Driver may also offer non standard macro and functions in order to support specific features but, of course, the use of such interfaces would not be portable. Such interfaces shall be marked with the architecture name inside the function names.

-

Implementation Rules

-

In implementing an PAL Low Level Driver there are some rules/behaviors that should be respected.

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Writing on input pads

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The behavior is not specified but there are implementations better than others, this is the list of possible implementations, preferred options are on top:

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    -
  1. The written value is not actually output but latched, should the pads be reprogrammed as outputs the value would be in effect.
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  2. The write operation is ignored.
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  3. The write operation has side effects, as example disabling/enabling pull up/down resistors or changing the pad direction. This scenario is discouraged, please try to avoid this scenario.
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Reading from output pads

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The behavior is not specified but there are implementations better than others, this is the list of possible implementations, preferred options are on top:

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  1. The actual pads states are read (not the output latch).
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  2. The output latch value is read (regardless of the actual pads states).
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  3. Unspecified, please try to avoid this scenario.
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Writing unused or unimplemented port bits

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The behavior is not specified.

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Reading from unused or unimplemented port bits

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The behavior is not specified.

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Reading or writing on pins associated to other functionalities

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The behavior is not specified.

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Usage

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The use of I/O ports requires the inclusion of the header file pal.h, this file is not automatically included ch.h like the other header files.

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-Data Structures

struct  IOBus
 I/O bus descriptor. More...

-Modules

 PAL Low Level Driver
 

PAL Driver low level driver template.

-

-Defines

#define PAL_MODE_MASK   0xF
 Bits in a mode word dedicated as mode selector.
#define PAL_MODE_RESET   0
 After reset state.
#define PAL_MODE_UNCONNECTED   1
 Safe state for unconnected pads.
#define PAL_MODE_INPUT   2
 Regular input high-Z pad.
#define PAL_MODE_INPUT_PULLUP   3
 Input pad with weak pull up resistor.
#define PAL_MODE_INPUT_PULLDOWN   4
 Input pad with weak pull down resistor.
#define PAL_MODE_INPUT_ANALOG   5
 Analog input mode.
#define PAL_MODE_OUTPUT_PUSHPULL   6
 Push-pull output pad.
#define PAL_MODE_OUTPUT_OPENDRAIN   7
 Open-drain output pad.
#define PAL_LOW   0
 Logical low state.
#define PAL_HIGH   1
 Logical high state.
#define PAL_PORT_BIT(n)   ((ioportmask_t)(1 << (n)))
 Port bit helper macro.
#define PAL_GROUP_MASK(width)   ((ioportmask_t)(1 << (width)) - 1)
 Bits group mask helper.
#define _IOBUS_DATA(name, port, width, offset)   {port, PAL_GROUP_MASK(width), offset}
 Data part of a static I/O bus initializer.
#define IOBUS_DECL(name, port, width, offset)   IOBus name = _IOBUS_DATA(name, port, width, offset)
 Static I/O bus initializer.
#define palInit(config)   pal_lld_init(config)
 PAL subsystem initialization.
#define palReadPort(port)   ((void)(port), 0)
 Reads the physical I/O port states.
#define palReadLatch(port)   ((void)(port), 0)
 Reads the output latch.
#define palWritePort(port, bits)   ((void)(port), (void)(bits))
 Writes a bits mask on a I/O port.
#define palSetPort(port, bits)
 Sets a bits mask on a I/O port.
#define palClearPort(port, bits)
 Clears a bits mask on a I/O port.
#define palTogglePort(port, bits)
 Toggles a bits mask on a I/O port.
#define palReadGroup(port, mask, offset)   ((palReadPort(port) >> (offset)) & (mask))
 Reads a group of bits.
#define palWriteGroup(port, mask, offset, bits)
 Writes a group of bits.
#define palSetGroupMode(port, mask, mode)
 Pads group mode setup.
#define palReadPad(port, pad)   ((palReadPort(port) >> (pad)) & 1)
 Reads an input pad logical state.
#define palWritePad(port, pad, bit)
 Writes a logical state on an output pad.
#define palSetPad(port, pad)   palSetPort(port, PAL_PORT_BIT(pad))
 Sets a pad logical state to PAL_HIGH.
#define palClearPad(port, pad)   palClearPort(port, PAL_PORT_BIT(pad))
 Clears a pad logical state to PAL_LOW.
#define palTogglePad(port, pad)   palTogglePort(port, PAL_PORT_BIT(pad))
 Toggles a pad logical state.
#define palSetPadMode(port, pad, mode)   palSetGroupMode(port, PAL_PORT_BIT(pad), mode)
 Pad mode setup.

-Functions

ioportmask_t palReadBus (IOBus *bus)
 Read from an I/O bus.
void palWriteBus (IOBus *bus, ioportmask_t bits)
 Write to an I/O bus.
void palSetBusMode (IOBus *bus, uint_fast8_t mode)
 Programs a bus with the specified mode.
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Define Documentation

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#define PAL_MODE_MASK   0xF
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Bits in a mode word dedicated as mode selector.

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The other bits are not defined and may be used as device-specific option bits.

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Definition at line 49 of file pal.h.

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#define PAL_MODE_RESET   0
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After reset state.

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The state itself is not specified and is architecture dependent, it is guaranteed to be equal to the after-reset state. It is usually an input state.

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Definition at line 57 of file pal.h.

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#define PAL_MODE_UNCONNECTED   1
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Safe state for unconnected pads.

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The state itself is not specified and is architecture dependent, it may be mapped on PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLDOWN or PAL_MODE_OUTPUT_PUSHPULL as example.

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Definition at line 66 of file pal.h.

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#define PAL_MODE_INPUT   2
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Regular input high-Z pad.

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Definition at line 71 of file pal.h.

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#define PAL_MODE_INPUT_PULLUP   3
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Input pad with weak pull up resistor.

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Definition at line 76 of file pal.h.

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#define PAL_MODE_INPUT_PULLDOWN   4
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Input pad with weak pull down resistor.

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Definition at line 81 of file pal.h.

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#define PAL_MODE_INPUT_ANALOG   5
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Analog input mode.

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Definition at line 86 of file pal.h.

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#define PAL_MODE_OUTPUT_PUSHPULL   6
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Push-pull output pad.

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Definition at line 91 of file pal.h.

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#define PAL_MODE_OUTPUT_OPENDRAIN   7
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Open-drain output pad.

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Definition at line 96 of file pal.h.

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#define PAL_LOW   0
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Logical low state.

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Definition at line 101 of file pal.h.

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#define PAL_HIGH   1
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Logical high state.

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Definition at line 106 of file pal.h.

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#define PAL_PORT_BIT( n )    ((ioportmask_t)(1 << (n)))
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Port bit helper macro.

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This macro calculates the mask of a bit within a port.

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[in] n bit position within the port
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The bit mask.
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Definition at line 157 of file pal.h.

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#define PAL_GROUP_MASK( width )    ((ioportmask_t)(1 << (width)) - 1)
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Bits group mask helper.

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This macro calculates the mask of a bits group.

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Parameters:
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[in] width group width
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The group mask.
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Definition at line 167 of file pal.h.

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#define _IOBUS_DATA( name,
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Data part of a static I/O bus initializer.

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This macro should be used when statically initializing an I/O bus that is part of a bigger structure.

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[in] port I/O port descriptor
[in] width bus width in bits
[in] offset bus bit offset within the port
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Definition at line 179 of file pal.h.

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#define IOBUS_DECL( name,
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Static I/O bus initializer.

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Parameters:
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[in] name name of the IOBus variable
[in] port I/O port descriptor
[in] width bus width in bits
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Definition at line 190 of file pal.h.

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#define palInit( config )    pal_lld_init(config)
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PAL subsystem initialization.

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Definition at line 200 of file pal.h.

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Referenced by halInit().

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#define palReadPort( port )    ((void)(port), 0)
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Reads the physical I/O port states.

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[in] port port identifier
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The port logical states.
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Definition at line 211 of file pal.h.

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#define palReadLatch( port )    ((void)(port), 0)
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Reads the output latch.

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The purpose of this function is to read back the latched output value.

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Note:
The default implementation always return zero and computes the parameter eventual side effects.
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Parameters:
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[in] port port identifier
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The latched logical states.
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Definition at line 227 of file pal.h.

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#define palWritePort( port,
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Writes a bits mask on a I/O port.

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Note:
The default implementation does nothing except computing the parameters eventual side effects.
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[in] port port identifier
[in] bits bits to be written on the specified port
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Definition at line 241 of file pal.h.

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#define palSetPort( port,
 bits 
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{                                        \
-  palWritePort(port, palReadLatch(port) | (bits));                      \
-}
-
-

Sets a bits mask on a I/O port.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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[in] port port identifier
[in] bits bits to be ORed on the specified port
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Definition at line 260 of file pal.h.

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#define palClearPort( port,
 bits 
)
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{                                      \
-  palWritePort(port, palReadLatch(port) & ~(bits));                     \
-}
-
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Clears a bits mask on a I/O port.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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[in] port port identifier
[in] bits bits to be cleared on the specified port
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Definition at line 282 of file pal.h.

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#define palTogglePort( port,
 bits 
)
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{                                     \
-  palWritePort(port, palReadLatch(port) ^ (bits));                      \
-}
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Toggles a bits mask on a I/O port.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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[in] port port identifier
[in] bits bits to be XORed on the specified port
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Definition at line 303 of file pal.h.

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#define palReadGroup( port,
 mask,
 offset 
)   ((palReadPort(port) >> (offset)) & (mask))
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Reads a group of bits.

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[in] port port identifier
[in] mask group mask, a logical AND is performed on the input data
[in] offset group bit offset within the port
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The group logical states.
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Definition at line 320 of file pal.h.

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Referenced by palReadBus().

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#define palWriteGroup( port,
 mask,
 offset,
 bits 
)
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{                       \
-  palWritePort(port, (palReadLatch(port) & ~((mask) << (offset))) |     \
-                     (((bits) & (mask)) << (offset)));                  \
-}
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Writes a group of bits.

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[in] port port identifier
[in] mask group mask, a logical AND is performed on the output data
[in] offset group bit offset within the port
[in] bits bits to be written. Values exceeding the group width are masked.
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Definition at line 337 of file pal.h.

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Referenced by palWriteBus().

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#define palSetGroupMode( port,
 mask,
 mode 
)
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Pads group mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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Note:
Programming an unknown or unsupported mode is silently ignored.
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[in] port port identifier
[in] mask group mask
[in] mode group mode
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Definition at line 359 of file pal.h.

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Referenced by palSetBusMode().

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#define palReadPad( port,
 pad 
)   ((palReadPort(port) >> (pad)) & 1)
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Reads an input pad logical state.

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Note:
The default implementation not necessarily optimal. Low level drivers may optimize the function by using specific hardware or coding.
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[in] port port identifier
[in] pad pad number within the port
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The logical state.
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PAL_LOW low logical state.
PAL_HIGH high logical state.
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Definition at line 379 of file pal.h.

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#define palWritePad( port,
 pad,
 bit 
)
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{                                   \
-  palWritePort(port, (palReadLatch(port) & ~PAL_PORT_BIT(pad)) |        \
-                     (((bit) & 1) << pad));                             \
-}
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Writes a logical state on an output pad.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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Parameters:
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[in] port port identifier
[in] pad pad number within the port
[in] bit logical value, the value must be PAL_LOW or PAL_HIGH
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Definition at line 402 of file pal.h.

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#define palSetPad( port,
 pad 
)   palSetPort(port, PAL_PORT_BIT(pad))
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Sets a pad logical state to PAL_HIGH.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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[in] port port identifier
[in] pad pad number within the port
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Definition at line 425 of file pal.h.

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#define palClearPad( port,
 pad 
)   palClearPort(port, PAL_PORT_BIT(pad))
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Clears a pad logical state to PAL_LOW.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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[in] port port identifier
[in] pad pad number within the port
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Definition at line 445 of file pal.h.

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#define palTogglePad( port,
 pad 
)   palTogglePort(port, PAL_PORT_BIT(pad))
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Toggles a pad logical state.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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[in] port port identifier
[in] pad pad number within the port
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Definition at line 465 of file pal.h.

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#define palSetPadMode( port,
 pad,
 mode 
)   palSetGroupMode(port, PAL_PORT_BIT(pad), mode)
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Pad mode setup.

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This function programs a pad with the specified mode.

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Note:
The default implementation not necessarily optimal. Low level drivers may optimize the function by using specific hardware or coding.
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-Programming an unknown or unsupported mode is silently ignored.
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[in] port port identifier
[in] pad pad number within the port
[in] mode pad mode
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Definition at line 484 of file pal.h.

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Function Documentation

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ioportmask_t palReadBus (IOBus *  bus ) 
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Read from an I/O bus.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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-The function internally uses the palReadGroup() macro. The use of this function is preferred when you value code size, readability and error checking over speed.
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Parameters:
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[in] bus the I/O bus, pointer to a IOBus structure
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The bus logical states.
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Definition at line 69 of file pal.c.

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References IOBus::bus_mask, IOBus::bus_offset, IOBus::bus_portid, chDbgCheck, PAL_IOPORTS_WIDTH, and palReadGroup.

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void palWriteBus (IOBus *  bus,
ioportmask_t  bits 
)
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Write to an I/O bus.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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Parameters:
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[in] bus the I/O bus, pointer to a IOBus structure
[in] bits the bits to be written on the I/O bus. Values exceeding the bus width are masked so most significant bits are lost.
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Definition at line 92 of file pal.c.

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References IOBus::bus_mask, IOBus::bus_offset, IOBus::bus_portid, chDbgCheck, PAL_IOPORTS_WIDTH, and palWriteGroup.

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void palSetBusMode (IOBus *  bus,
uint_fast8_t  mode 
)
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Programs a bus with the specified mode.

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Note:
The operation is not guaranteed to be atomic on all the architectures, for atomicity and/or portability reasons you may need to enclose port I/O operations between chSysLock() and chSysUnlock().
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Parameters:
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[in] bus the I/O bus, pointer to a IOBus structure
[in] mode the mode
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Definition at line 113 of file pal.c.

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References IOBus::bus_mask, IOBus::bus_offset, IOBus::bus_portid, chDbgCheck, PAL_IOPORTS_WIDTH, and palSetGroupMode.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs
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PAL Low Level Driver
- -[PAL Driver] -

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PAL Driver low level driver template. -More...

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-Collaboration diagram for PAL Low Level Driver:
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Description

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PAL Driver low level driver template.

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This file is a template for an I/O port low level driver.

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-Data Structures

struct  GenericConfig
 Generic I/O ports static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFFFFFFF)
 Whole port mask.
#define IOPORT1   0
 First I/O port identifier.
#define pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)
 Reads the output latch.
#define pal_lld_writeport(port, bits)
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)
 Clears a bits mask on a I/O port.
#define pal_lld_toggleport(port, bits)
 Toggles a bits mask on a I/O port.
#define pal_lld_readgroup(port, mask, offset)
 Reads a group of bits.
#define pal_lld_writegroup(port, mask, offset, bits)
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_readpad(port, pad)
 Reads a logical state from an I/O pad.
#define pal_lld_writepad(port, pad, bit)
 Writes a logical state on an output pad.
#define pal_lld_setpad(port, pad)
 Sets a pad logical state to PAL_HIGH.
#define pal_lld_clearpad(port, pad)
 Clears a pad logical state to PAL_LOW.
#define pal_lld_togglepad(port, pad)
 Toggles a pad logical state.
#define pal_lld_setpadmode(port, pad, mode)
 Pad mode setup.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef uint32_t ioportid_t
 Port Identifier.
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Define Documentation

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#define PAL_IOPORTS_WIDTH   32
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Width, in bits, of an I/O port.

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Definition at line 70 of file templates/pal_lld.h.

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Referenced by palReadBus(), palSetBusMode(), and palWriteBus().

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#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFFFFFFF)
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Whole port mask.

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This macro specifies all the valid bits into a port.

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Definition at line 76 of file templates/pal_lld.h.

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#define IOPORT1   0
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First I/O port identifier.

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Low level drivers can define multiple ports, it is suggested to use this naming convention.

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Definition at line 100 of file templates/pal_lld.h.

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#define pal_lld_init( config ) 
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Low level PAL subsystem initialization.

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Parameters:
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[in] config architecture-dependent ports configuration
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Definition at line 112 of file templates/pal_lld.h.

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#define pal_lld_readport( port ) 
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Reads the physical I/O port states.

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Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
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The port bits.
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Definition at line 122 of file templates/pal_lld.h.

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#define pal_lld_readlatch( port ) 
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Reads the output latch.

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The purpose of this function is to read back the latched output value.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
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The latched logical states.
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Definition at line 134 of file templates/pal_lld.h.

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#define pal_lld_writeport( port,
 bits 
)
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Writes a bits mask on a I/O port.

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Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] bits bits to be written on the specified port
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Definition at line 144 of file templates/pal_lld.h.

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#define pal_lld_setport( port,
 bits 
)
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Sets a bits mask on a I/O port.

-
Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] bits bits to be ORed on the specified port
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Definition at line 157 of file templates/pal_lld.h.

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#define pal_lld_clearport( port,
 bits 
)
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Clears a bits mask on a I/O port.

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Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] bits bits to be cleared on the specified port
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Definition at line 170 of file templates/pal_lld.h.

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#define pal_lld_toggleport( port,
 bits 
)
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Toggles a bits mask on a I/O port.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] bits bits to be XORed on the specified port
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Definition at line 183 of file templates/pal_lld.h.

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#define pal_lld_readgroup( port,
 mask,
 offset 
)
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Reads a group of bits.

-
Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] mask group mask
[in] offset group bit offset within the port
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The group logical states.
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Definition at line 198 of file templates/pal_lld.h.

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#define pal_lld_writegroup( port,
 mask,
 offset,
 bits 
)
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Writes a group of bits.

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Note:
This function is not meant to be invoked directly by the application code.
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Parameters:
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[in] port port identifier
[in] mask group mask
[in] offset group bit offset within the port
[in] bits bits to be written. Values exceeding the group width are masked.
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Definition at line 214 of file templates/pal_lld.h.

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#define pal_lld_setgroupmode( port,
 mask,
 mode 
)
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Pads group mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port port identifier
[in] mask group mask
[in] mode group mode
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Definition at line 228 of file templates/pal_lld.h.

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#define pal_lld_readpad( port,
 pad 
)
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Reads a logical state from an I/O pad.

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Note:
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[in] port port identifier
[in] pad pad number within the port
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The logical state.
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PAL_LOW low logical state.
PAL_HIGH high logical state.
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Definition at line 244 of file templates/pal_lld.h.

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#define pal_lld_writepad( port,
 pad,
 bit 
)
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Writes a logical state on an output pad.

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Note:
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[in] port port identifier
[in] pad pad number within the port
[out] bit logical value, the value must be PAL_LOW or PAL_HIGH
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Definition at line 259 of file templates/pal_lld.h.

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#define pal_lld_setpad( port,
 pad 
)
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Sets a pad logical state to PAL_HIGH.

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Note:
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[in] port port identifier
[in] pad pad number within the port
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Definition at line 272 of file templates/pal_lld.h.

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#define pal_lld_clearpad( port,
 pad 
)
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Clears a pad logical state to PAL_LOW.

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Note:
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[in] port port identifier
[in] pad pad number within the port
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Definition at line 285 of file templates/pal_lld.h.

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#define pal_lld_togglepad( port,
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Toggles a pad logical state.

-
Note:
This function is not meant to be invoked directly by the application code.
-
-The PAL Driver provides a default software implementation of this functionality, implement this function if can optimize it by using special hardware functionalities or special coding.
-
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- - - -
[in] port port identifier
[in] pad pad number within the port
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Definition at line 298 of file templates/pal_lld.h.

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#define pal_lld_setpadmode( port,
 pad,
 mode 
)
-
-
- -

Pad mode setup.

-

This function programs a pad with the specified mode.

-
Note:
This function is not meant to be invoked directly by the application code.
-
-The PAL Driver provides a default software implementation of this functionality, implement this function if can optimize it by using special hardware functionalities or special coding.
-
-Programming an unknown or unsupported mode is silently ignored.
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- - - - -
[in] port port identifier
[in] pad pad number within the port
[in] mode pad mode
-
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Definition at line 314 of file templates/pal_lld.h.

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Typedef Documentation

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typedef uint32_t ioportmask_t
-
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- -

Digital I/O port sized unsigned type.

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Definition at line 81 of file templates/pal_lld.h.

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typedef uint32_t ioportid_t
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Port Identifier.

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This type can be a scalar or some kind of pointer, do not make any assumption about it, use the provided macros when populating variables of this type.

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Definition at line 89 of file templates/pal_lld.h.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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PowerPC
- -[Ports] -

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-Collaboration diagram for PowerPC:
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-

Description

-

PowerPC port details. This section describes how the ChibiOS/RT features are implemented on this architecture.

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-Mapping of the System States in the PowerPC port

-

The ChibiOS/RT logical System States are mapped as follow in the PowerPC port:

-
    -
  • Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated.
    • -
  • Normal. This is the state the system has after executing chSysInit(). Interrupts are enabled.
    • -
  • Suspended. Interrupts are disabled.
    • -
  • Disabled. Interrupts are disabled. This state is equivalent to the Suspended state because there are no fast interrupts in this architecture.
    • -
  • Sleep. This state is entered with the execution of the specific instruction wait.
    • -
  • S-Locked. Interrupts are disabled.
    • -
  • I-Locked. This state is equivalent to the SRI state, the chSysLockI() and chSysUnlockI() APIs do nothing (still use them in order to formally change state because this may change).
    • -
  • Serving Regular Interrupt. Normal interrupt service code.
    • -
  • Serving Fast Interrupt. Not present in this architecture.
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  • Serving Non-Maskable Interrupt. The PowerPC has several non maskable interrupt sources that can be associated to this state.
    • -
  • Halted. Implemented as an infinite loop with interrupts disabled.
    • -
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-The PowerPC port notes

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The PowerPC port is organized as follow:

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  • The main() function is invoked in privileged mode.
    • -
  • Each thread has a private stack with extra storage for interrupts servicing.
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  • The Book-E Decrementer Timer, mapped on IVOR10, is used for system tick.
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-Modules

 Configuration Options
 

PowerPC Configuration Options.

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 Core Port Implementation
 

PowerPC specific port code, structures and macros.

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 Startup Support
 

PPC startup code support.

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 SPC563 Drivers
 

Device drivers included in the SPC563 support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Configuration Options
- -[PowerPC] -

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PowerPC Configuration Options. -More...

- -

-Collaboration diagram for Configuration Options:
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PowerPC Configuration Options.

-

The PowerPC port allows some architecture-specific configurations settings that can be overridden by redefining them in chconf.h. Usually there is no need to change the default values.

-
    -
  • INT_REQUIRED_STACK, this value represent the amount of stack space used by an interrupt handler between the extctx and intctx structures. The default for this value is 128 bytes, this space is allocated for each thread so be careful in order to not waste precious RAM space.
    - The default value is set into ./os/ports/GCC/PPC/chcore.h.
    • -
  • IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE thread. Usually there is no need to change this value unless inserting code in the IDLE thread hook macro.
    • -
  • ENABLE_WFI_IDLE, if set to TRUE enables the use of the wait instruction from within the idle loop. This is defaulted to 0 because it can create problems with some debuggers. Setting this option to 1 reduces the system power requirements.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions
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Core Port Implementation
- -[PowerPC] -

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PowerPC specific port code, structures and macros. -More...

- -

-Collaboration diagram for Core Port Implementation:
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Description

-

PowerPC specific port code, structures and macros.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-Data Structures

struct  stkalign_t
 Base type for stack and memory alignment. More...
struct  eabi_frame
 Mandatory part of a stack frame. More...

-Defines

#define ENABLE_WFI_IDLE   0
 Enables the use of the WFI instruction.
#define PPC_VARIANT_e200z3   3
#define PPC_VARIANT_e200z4   4
#define PPC_VARIANT   PPC_VARIANT_e200z3
 Core variant selector.
#define CH_ARCHITECTURE_PPC
 Unique macro for the implemented architecture.
#define CH_ARCHITECTURE_NAME   "PowerPC"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "e200z3"
 Name of the architecture variant.
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   0
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   128
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void id(void)
 IRQ handler function declaration.
#define port_init()
 Kernel port layer initialization.
#define port_lock()   asm volatile ("wrteei 0" : : : "memory")
#define port_unlock()   asm volatile("wrteei 1" : : : "memory")
#define port_lock_from_isr()
#define port_unlock_from_isr()
#define port_disable()   asm volatile ("wrteei 0" : : : "memory")
#define port_suspend()   asm volatile ("wrteei 0" : : : "memory")
#define port_enable()   asm volatile ("wrteei 1" : : : "memory")
#define port_wait_for_interrupt()
#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef void * regppc_t
 Generic PPC register.
typedef volatile int8_t vint8_t
typedef volatile uint8_t vuint8_t
typedef volatile int16_t vint16_t
typedef volatile uint16_t vuint16_t
typedef volatile int32_t vint32_t
typedef volatile uint32_t vuint32_t
typedef int32_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint32_t tprio_t
typedef int32_t msg_t
typedef int32_t eventid_t
typedef uint32_t eventmask_t
typedef uint32_t systime_t
typedef int32_t cnt_t

-Functions

void port_halt (void)
 Halts the system.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Define Documentation

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#define ENABLE_WFI_IDLE   0
-
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Enables the use of the WFI instruction.

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Definition at line 46 of file ports/GCC/PPC/chcore.h.

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#define PPC_VARIANT_e200z3   3
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e200z3 core identifier.

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Definition at line 50 of file ports/GCC/PPC/chcore.h.

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#define PPC_VARIANT_e200z4   4
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e200z4 core identifier.

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Definition at line 51 of file ports/GCC/PPC/chcore.h.

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#define PPC_VARIANT   PPC_VARIANT_e200z3
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Core variant selector.

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This setting affects the predefined architecture strings and possibly code paths and structures into the port layer.

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Definition at line 59 of file ports/GCC/PPC/chcore.h.

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#define CH_ARCHITECTURE_PPC
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Unique macro for the implemented architecture.

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Definition at line 65 of file ports/GCC/PPC/chcore.h.

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#define CH_ARCHITECTURE_NAME   "PowerPC"
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Name of the implemented architecture.

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Definition at line 70 of file ports/GCC/PPC/chcore.h.

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#define CH_CORE_VARIANT_NAME   "e200z3"
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Name of the architecture variant.

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Definition at line 76 of file ports/GCC/PPC/chcore.h.

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#define SETUP_CONTEXT( workspace,
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 pf,
 arg 
)
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{                          \
-  uint8_t *sp = (uint8_t *)workspace + wsize - sizeof(struct eabi_frame);   \
-  ((struct eabi_frame *)sp)->slink = 0;                                     \
-  ((struct eabi_frame *)sp)->shole = _port_thread_start;                    \
-  tp->p_ctx.sp = (struct intctx *)(sp - sizeof(struct intctx));             \
-  tp->p_ctx.sp->r31 = arg;                                                  \
-  tp->p_ctx.sp->r30 = pf;                                                   \
-}
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Platform dependent part of the chThdInit() API.

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This code usually setup the context switching frame represented by an intctx structure.

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Definition at line 187 of file ports/GCC/PPC/chcore.h.

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#define IDLE_THREAD_STACK_SIZE   0
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Stack size for the system idle thread.

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This size depends on the idle thread implementation, usually the idle thread should take no more space than those reserved by INT_REQUIRED_STACK.

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Definition at line 203 of file ports/GCC/PPC/chcore.h.

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#define INT_REQUIRED_STACK   128
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Per-thread stack overhead for interrupts servicing.

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This constant is used in the calculation of the correct working area size. This value can be zero on those architecture where there is a separate interrupt stack and the stack space between intctx and extctx is known to be zero.

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Definition at line 215 of file ports/GCC/PPC/chcore.h.

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#define STACK_ALIGN( n )    ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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Enforces a correct alignment for a stack area size value.

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Definition at line 221 of file ports/GCC/PPC/chcore.h.

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#define THD_WA_SIZE( n ) 
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STACK_ALIGN(sizeof(Thread) +                     \
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Computes the thread working area global size.

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Definition at line 226 of file ports/GCC/PPC/chcore.h.

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#define WORKING_AREA( s,
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Static working area allocation.

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This macro is used to allocate a static thread working area aligned as both position and size.

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Definition at line 236 of file ports/GCC/PPC/chcore.h.

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#define PORT_IRQ_PROLOGUE( ) 
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IRQ prologue code.

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This macro must be inserted at the start of all IRQ handlers enabled to invoke system APIs.

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Definition at line 243 of file ports/GCC/PPC/chcore.h.

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#define PORT_IRQ_EPILOGUE( ) 
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IRQ epilogue code.

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This macro must be inserted at the end of all IRQ handlers enabled to invoke system APIs.

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Definition at line 250 of file ports/GCC/PPC/chcore.h.

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#define PORT_IRQ_HANDLER( id )    void id(void)
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IRQ handler function declaration.

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id can be a function name or a vector number depending on the port implementation.
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Definition at line 257 of file ports/GCC/PPC/chcore.h.

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#define port_init( void ) 
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{                                                       \
-  asm volatile ("li          %r3, IVOR4@l         \t\n"                   \
-                  "mtIVOR4     %r3                  \t\n"                   \
-                  "li          %r3, IVOR10@l        \t\n"                   \
-                  "mtIVOR10    %r3");                                       \
-}
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Kernel port layer initialization.

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IVPR4 and IVPR10 initialization, INTC_IACKR_PRC0 initialization.

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Definition at line 263 of file ports/GCC/PPC/chcore.h.

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#define port_lock( void )    asm volatile ("wrteei 0" : : : "memory")
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Implemented as global interrupt disable.

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Definition at line 273 of file ports/GCC/PPC/chcore.h.

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#define port_unlock( void )    asm volatile("wrteei 1" : : : "memory")
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Implemented as global interrupt enable.

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Definition at line 278 of file ports/GCC/PPC/chcore.h.

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#define port_lock_from_isr( void ) 
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Implemented as global interrupt disable.

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Definition at line 283 of file ports/GCC/PPC/chcore.h.

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#define port_unlock_from_isr( void ) 
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Implemented as global interrupt enable.

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Definition at line 288 of file ports/GCC/PPC/chcore.h.

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#define port_disable( void )    asm volatile ("wrteei 0" : : : "memory")
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Implemented as global interrupt disable.

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Definition at line 293 of file ports/GCC/PPC/chcore.h.

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#define port_suspend( void )    asm volatile ("wrteei 0" : : : "memory")
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Same as port_disable() in this port, there is no difference between the two states.

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Definition at line 299 of file ports/GCC/PPC/chcore.h.

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#define port_enable( void )    asm volatile ("wrteei 1" : : : "memory")
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Implemented as global interrupt enable.

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Definition at line 304 of file ports/GCC/PPC/chcore.h.

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#define port_wait_for_interrupt( void ) 
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This port function is implemented as inlined code for performance reasons.

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Definition at line 317 of file ports/GCC/PPC/chcore.h.

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#define INLINE   inline
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Inline function modifier.

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Definition at line 73 of file ports/GCC/PPC/chtypes.h.

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#define ROMCONST   const
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ROM constant modifier.

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Note:
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Definition at line 79 of file ports/GCC/PPC/chtypes.h.

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#define PACK_STRUCT_STRUCT   __attribute__((packed))
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Packed structure modifier (within).

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It uses the "packed" GCC attribute.
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Definition at line 85 of file ports/GCC/PPC/chtypes.h.

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#define PACK_STRUCT_BEGIN
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Packed structure modifier (before).

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Note:
Empty in this port.
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Definition at line 91 of file ports/GCC/PPC/chtypes.h.

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#define PACK_STRUCT_END
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Packed structure modifier (after).

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Note:
Empty in this port.
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Definition at line 97 of file ports/GCC/PPC/chtypes.h.

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Typedef Documentation

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typedef void* regppc_t
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Generic PPC register.

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Definition at line 93 of file ports/GCC/PPC/chcore.h.

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typedef volatile int8_t vint8_t
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Volatile signed 8 bits.

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Definition at line 49 of file ports/GCC/PPC/chtypes.h.

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typedef volatile uint8_t vuint8_t
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Volatile unsigned 8 bits.

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Definition at line 50 of file ports/GCC/PPC/chtypes.h.

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typedef volatile int16_t vint16_t
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Volatile signed 16 bits.

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Definition at line 51 of file ports/GCC/PPC/chtypes.h.

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typedef volatile uint16_t vuint16_t
-
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Volatile unsigned 16 bits.

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Definition at line 52 of file ports/GCC/PPC/chtypes.h.

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typedef volatile int32_t vint32_t
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Volatile signed 32 bits.

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Definition at line 53 of file ports/GCC/PPC/chtypes.h.

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typedef volatile uint32_t vuint32_t
-
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Volatile unsigned 32 bits.

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Definition at line 54 of file ports/GCC/PPC/chtypes.h.

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typedef int32_t bool_t
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Fast boolean type.

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Definition at line 59 of file ports/GCC/PPC/chtypes.h.

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typedef uint8_t tmode_t
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Thread flags.

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Definition at line 60 of file ports/GCC/PPC/chtypes.h.

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typedef uint8_t tstate_t
-
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Thread state.

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Definition at line 61 of file ports/GCC/PPC/chtypes.h.

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typedef uint8_t trefs_t
-
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Thread references counter.

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Definition at line 62 of file ports/GCC/PPC/chtypes.h.

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typedef uint32_t tprio_t
-
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Thread priority.

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Definition at line 63 of file ports/GCC/PPC/chtypes.h.

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Function Documentation

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Startup Support
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PPC startup code support. -More...

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PPC startup code support.

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ChibiOS/RT provides its own generic startup file for the PowerPC port. Of course it is not mandatory to use it but care should be taken about the startup phase details.

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Startup Process

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The startup process, as implemented, is the following:

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  6. A late initialization routine hwinit1 is invoked, if the symbol not defined then an empty default routine is executed (weak symbol).
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Expected linker symbols

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Modules | -Defines | -Typedefs | -Enumerations | -Functions
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PWM Driver
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Generic PWM Driver. -More...

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Description

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Generic PWM Driver.

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This module implements a generic PWM driver. The driver implements a state machine internally:

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-Data Structures

struct  PWMChannelConfig
 PWM driver channel configuration structure. More...
struct  PWMConfig
 Driver configuration structure. More...
struct  PWMDriver
 Structure representing an PWM driver. More...

-Modules

 PWM Low Level Driver
 

PWM Driver low level driver template.

-

-Defines

#define pwmEnableChannelI(pwmp, channel, width)   pwm_lld_enable_channel(pwmp, channel, width)
 Enables a PWM channel.
#define pwmDisableChannelI(pwmp, channel)   pwm_lld_disable_channel(pwmp, channel)
 Disables a PWM channel.
#define PWM_CHANNELS   4
 Number of PWM channels per PWM driver.
#define USE_STM32_PWM1   TRUE
 PWM1 driver enable switch.
#define USE_STM32_PWM2   TRUE
 PWM2 driver enable switch.
#define USE_STM32_PWM3   TRUE
 PWM3 driver enable switch.
#define USE_STM32_PWM4   TRUE
 PWM4 driver enable switch.
#define STM32_PWM1_IRQ_PRIORITY   7
 PWM1 interrupt priority level setting.
#define STM32_PWM2_IRQ_PRIORITY   7
 PWM2 interrupt priority level setting.
#define STM32_PWM3_IRQ_PRIORITY   7
 PWM3 interrupt priority level setting.
#define STM32_PWM4_IRQ_PRIORITY   7
 PWM4 interrupt priority level setting.
#define PWM_COMPUTE_PSC(clksrc, pwmclk)   ((uint16_t)(((clksrc) / (pwmclk)) - 1))
 PWM clock prescaler initialization utility.
#define PWM_COMPUTE_ARR(pwmclk, pwmperiod)   ((uint16_t)(((pwmclk) / (1000000000 / (pwmperiod))) - 1))
 PWM cycle period initialization utility.
#define PWM_FRACTION_TO_WIDTH(pwmp, numerator, denominator)
 Converts from fraction to pulse width.
#define PWM_DEGREES_TO_WIDTH(pwmp, degrees)   PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees)
 Converts from degrees to pulse width.
#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage)   PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage)
 Converts from percentage to pulse width.

-Typedefs

typedef uint8_t pwmchannel_t
 PWM channel type.
typedef uint16_t pwmcnt_t
 PWM counter type.
typedef struct PWMDriver PWMDriver
 Type of a structure representing an PWM driver.
typedef void(* pwmcallback_t )(PWMDriver *pwmp)
 PWM notification callback type.

-Enumerations

enum  pwmstate_t { PWM_UNINIT = 0, -PWM_STOP = 1, -PWM_READY = 2 - }
 

Driver state machine possible states.

- More...
enum  pwmmode_t { PWM_OUTPUT_DISABLED = 0, -PWM_OUTPUT_ACTIVE_HIGH = 1, -PWM_OUTPUT_ACTIVE_LOW = 2 - }
 

PWM logic mode.

- More...

-Functions

void pwmInit (void)
 PWM Driver initialization.
void pwmObjectInit (PWMDriver *pwmp)
 Initializes the standard part of a PWMDriver structure.
void pwmStart (PWMDriver *pwmp, const PWMConfig *config)
 Configures and activates the PWM peripheral.
void pwmStop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
void pwmEnableChannel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwmDisableChannel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.
void pwm_lld_init (void)
 Low level PWM driver initialization.
void pwm_lld_start (PWMDriver *pwmp)
 Configures and activates the PWM peripheral.
void pwm_lld_stop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
void pwm_lld_enable_channel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwm_lld_disable_channel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.
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Define Documentation

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#define pwmEnableChannelI( pwmp,
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 width 
)   pwm_lld_enable_channel(pwmp, channel, width)
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Enables a PWM channel.

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Programs (or reprograms) a PWM channel.

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[in] pwmp pointer to a PWMDriver object
[in] channel PWM channel identifier
[in] width PWM pulse width as clock pulses number
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Definition at line 89 of file pwm.h.

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#define pwmDisableChannelI( pwmp,
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Disables a PWM channel.

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The channel is disabled and its output line returned to the idle state.

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[in] channel PWM channel identifier
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Definition at line 101 of file pwm.h.

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Number of PWM channels per PWM driver.

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Definition at line 40 of file platforms/STM32/pwm_lld.h.

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PWM1 driver enable switch.

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Definition at line 52 of file platforms/STM32/pwm_lld.h.

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PWM2 driver enable switch.

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Definition at line 61 of file platforms/STM32/pwm_lld.h.

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PWM3 driver enable switch.

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Definition at line 70 of file platforms/STM32/pwm_lld.h.

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PWM4 driver enable switch.

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Definition at line 79 of file platforms/STM32/pwm_lld.h.

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PWM1 interrupt priority level setting.

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Definition at line 86 of file platforms/STM32/pwm_lld.h.

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PWM2 interrupt priority level setting.

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Definition at line 93 of file platforms/STM32/pwm_lld.h.

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PWM3 interrupt priority level setting.

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Definition at line 100 of file platforms/STM32/pwm_lld.h.

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PWM4 interrupt priority level setting.

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Definition at line 107 of file platforms/STM32/pwm_lld.h.

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#define PWM_COMPUTE_PSC( clksrc,
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PWM clock prescaler initialization utility.

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[in] clksrc clock source frequency, depending on the target timer cell it can be one of:

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[in] pwmclk PWM clock frequency in cycles
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Definition at line 245 of file platforms/STM32/pwm_lld.h.

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#define PWM_COMPUTE_ARR( pwmclk,
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PWM cycle period initialization utility.

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[in] pwmclk PWM clock frequency in cycles
[in] pwmperiod PWM cycle period in nanoseconds
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Definition at line 257 of file platforms/STM32/pwm_lld.h.

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#define PWM_FRACTION_TO_WIDTH( pwmp,
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Converts from fraction to pulse width.

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[in] numerator numerator of the fraction
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The pulse width to be passed to pwmEnableChannel().
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Definition at line 273 of file platforms/STM32/pwm_lld.h.

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Converts from degrees to pulse width.

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[in] pwmp pointer to a PWMDriver object
[in] degrees degrees as an integer between 0 and 36000
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The pulse width to be passed to pwmEnableChannel().
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Definition at line 290 of file platforms/STM32/pwm_lld.h.

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#define PWM_PERCENTAGE_TO_WIDTH( pwmp,
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Converts from percentage to pulse width.

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[in] percentage percentage as an integer between 0 and 10000
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Definition at line 306 of file platforms/STM32/pwm_lld.h.

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PWM channel type.

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Definition at line 130 of file platforms/STM32/pwm_lld.h.

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PWM counter type.

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Definition at line 140 of file platforms/STM32/pwm_lld.h.

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Definition at line 147 of file platforms/STM32/pwm_lld.h.

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Driver state machine possible states.

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Not initialized.

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Stopped.

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Ready.

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Definition at line 59 of file pwm.h.

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PWM logic mode.

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Output not driven, callback only.

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Idle is logic level 0.

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Idle is logic level 1.

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Definition at line 68 of file pwm.h.

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void pwmInit (void  ) 
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PWM Driver initialization.

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Definition at line 59 of file pwm.c.

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void pwmObjectInit (PWMDriver *  pwmp ) 
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Definition at line 69 of file pwm.c.

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void pwmStart (PWMDriver *  pwmp,
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Configures and activates the PWM peripheral.

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[in] config pointer to a PWMConfig object
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Definition at line 84 of file pwm.c.

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void pwmStop (PWMDriver *  pwmp ) 
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Deactivates the PWM peripheral.

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Definition at line 102 of file pwm.c.

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void pwmEnableChannel (PWMDriver *  pwmp,
pwmchannel_t  channel,
pwmcnt_t  width 
)
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Enables a PWM channel.

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Programs (or reprograms) a PWM channel.

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[in] pwmp pointer to a PWMDriver object
[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
[in] width PWM pulse width as clock pulses number
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Definition at line 122 of file pwm.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, PWMDriver::pd_state, PWM_CHANNELS, pwm_lld_enable_channel(), and PWM_READY.

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void pwmDisableChannel (PWMDriver *  pwmp,
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Disables a PWM channel.

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[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
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Definition at line 144 of file pwm.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, PWMDriver::pd_state, PWM_CHANNELS, pwm_lld_disable_channel(), and PWM_READY.

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void pwm_lld_init (void  ) 
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Low level PWM driver initialization.

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Definition at line 206 of file platforms/STM32/pwm_lld.c.

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void pwm_lld_start (PWMDriver *  pwmp ) 
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Configures and activates the PWM peripheral.

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Definition at line 258 of file platforms/STM32/pwm_lld.c.

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References CORTEX_PRIORITY_MASK, NVICEnableVector(), PWMConfig::pc_arr, PWMConfig::pc_callback, PWMConfig::pc_channels, PWMConfig::pc_cr2, PWMConfig::pc_psc, PWMChannelConfig::pcc_mode, PWMDriver::pd_config, PWMDriver::pd_enabled_channels, PWMDriver::pd_state, PWMDriver::pd_tim, PWM_OUTPUT_ACTIVE_HIGH, PWM_OUTPUT_ACTIVE_LOW, PWM_STOP, STM32_PWM1_IRQ_PRIORITY, STM32_PWM2_IRQ_PRIORITY, STM32_PWM3_IRQ_PRIORITY, and STM32_PWM4_IRQ_PRIORITY.

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void pwm_lld_stop (PWMDriver *  pwmp ) 
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Deactivates the PWM peripheral.

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Definition at line 370 of file platforms/STM32/pwm_lld.c.

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References NVICDisableVector(), PWMDriver::pd_enabled_channels, PWMDriver::pd_state, PWMDriver::pd_tim, and PWM_READY.

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Referenced by pwmStop().

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void pwm_lld_enable_channel (PWMDriver *  pwmp,
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pwmcnt_t  width 
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Enables a PWM channel.

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[in] pwmp pointer to a PWMDriver object
[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
[in] width PWM pulse width as clock pulses number
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Definition at line 421 of file platforms/STM32/pwm_lld.c.

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References PWMConfig::pc_channels, PWMChannelConfig::pcc_callback, PWMDriver::pd_config, PWMDriver::pd_enabled_channels, and PWMDriver::pd_tim.

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Referenced by pwmEnableChannel().

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void pwm_lld_disable_channel (PWMDriver *  pwmp,
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Disables a PWM channel.

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The channel is disabled and its output line returned to the idle state.

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[in] pwmp pointer to a PWMDriver object
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Definition at line 446 of file platforms/STM32/pwm_lld.c.

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References PWMDriver::pd_enabled_channels, and PWMDriver::pd_tim.

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Referenced by pwmDisableChannel().

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions
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PWM Low Level Driver
- -[PWM Driver] -

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PWM Driver low level driver template. -More...

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Description

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PWM Driver low level driver template.

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-Data Structures

struct  PWMChannelConfig
 PWM driver channel configuration structure. More...
struct  PWMConfig
 Driver configuration structure. More...
struct  PWMDriver
 Structure representing an PWM driver. More...

-Defines

#define PWM_CHANNELS   1
 Number of PWM channels per PWM driver.
#define PWM_FRACTION_TO_WIDTH(pwmp, numerator, denominator)   0
 Converts from fraction to pulse width.
#define PWM_DEGREES_TO_WIDTH(pwmp, degrees)   PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees)
 Converts from degrees to pulse width.
#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage)   PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage)
 Converts from percentage to pulse width.

-Typedefs

typedef uint8_t pwmchannel_t
 PWM channel type.
typedef uint16_t pwmcnt_t
 PWM counter type.
typedef struct PWMDriver PWMDriver
 Type of a structure representing an PWM driver.
typedef void(* pwmcallback_t )(PWMDriver *pwmp)
 PWM notification callback type.

-Functions

void pwm_lld_init (void)
 Low level PWM driver initialization.
void pwm_lld_start (PWMDriver *pwmp)
 Configures and activates the PWM peripheral.
void pwm_lld_stop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
bool_t pwm_lld_is_enabled (PWMDriver *pwmp, pwmchannel_t channel)
 Determines whatever the PWM channel is already enabled.
void pwm_lld_enable_channel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwm_lld_disable_channel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.
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Define Documentation

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#define PWM_CHANNELS   1
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Number of PWM channels per PWM driver.

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Definition at line 52 of file templates/pwm_lld.h.

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Referenced by pwmDisableChannel(), and pwmEnableChannel().

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#define PWM_FRACTION_TO_WIDTH( pwmp,
 numerator,
 denominator 
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Converts from fraction to pulse width.

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Be careful with rounding errors, this is integer math not magic. You can specify tenths of thousandth but make sure you have the proper hardware resolution by carefully choosing the clock source and prescaler settings, see PWM_COMPUTE_PSC.
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Parameters:
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[in] numerator numerator of the fraction
[in] denominator percentage as an integer between 0 and numerator
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The pulse width to be passed to pwmEnableChannel().
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Definition at line 160 of file templates/pwm_lld.h.

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#define PWM_DEGREES_TO_WIDTH( pwmp,
 degrees 
)   PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees)
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Converts from degrees to pulse width.

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Be careful with rounding errors, this is integer math not magic. You can specify hundredths of degrees but make sure you have the proper hardware resolution by carefully choosing the clock source and prescaler settings, see PWM_COMPUTE_PSC.
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[in] pwmp pointer to a PWMDriver object
[in] degrees degrees as an integer between 0 and 36000
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The pulse width to be passed to pwmEnableChannel().
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Definition at line 175 of file templates/pwm_lld.h.

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#define PWM_PERCENTAGE_TO_WIDTH( pwmp,
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Converts from percentage to pulse width.

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Note:
Be careful with rounding errors, this is integer math not magic. You can specify tenths of thousandth but make sure you have the proper hardware resolution by carefully choosing the clock source and prescaler settings, see PWM_COMPUTE_PSC.
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[in] pwmp pointer to a PWMDriver object
[in] percentage percentage as an integer between 0 and 10000
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The pulse width to be passed to pwmEnableChannel().
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Definition at line 191 of file templates/pwm_lld.h.

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Typedef Documentation

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typedef uint8_t pwmchannel_t
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PWM channel type.

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Definition at line 66 of file templates/pwm_lld.h.

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PWM counter type.

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Definition at line 71 of file templates/pwm_lld.h.

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Type of a structure representing an PWM driver.

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Definition at line 76 of file templates/pwm_lld.h.

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PWM notification callback type.

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Definition at line 83 of file templates/pwm_lld.h.

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void pwm_lld_init (void  ) 
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Low level PWM driver initialization.

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void pwm_lld_start (PWMDriver *  pwmp ) 
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Configures and activates the PWM peripheral.

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Referenced by pwmStart().

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void pwm_lld_stop (PWMDriver *  pwmp ) 
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Deactivates the PWM peripheral.

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Referenced by pwmStop().

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bool_t pwm_lld_is_enabled (PWMDriver *  pwmp,
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Determines whatever the PWM channel is already enabled.

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[in] pwmp pointer to the PWMDriver object
[in] channel PWM channel identifier
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The PWM channel status.
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FALSE the channel is not enabled.
TRUE the channel is enabled.
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void pwm_lld_enable_channel (PWMDriver *  pwmp,
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Enables a PWM channel.

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[in] pwmp pointer to a PWMDriver object
[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
[in] width PWM pulse width as clock pulses number
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Referenced by pwmEnableChannel().

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void pwm_lld_disable_channel (PWMDriver *  pwmp,
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Disables a PWM channel.

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The channel is disabled and its output line returned to the idle state.

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[in] pwmp pointer to a PWMDriver object
[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
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Referenced by pwmDisableChannel().

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Modules | -Defines | -Typedefs | -Enumerations | -Functions
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Serial Driver
- -[HAL] -

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Generic Serial Driver. -More...

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Description

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Generic Serial Driver.

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This module implements a generic full duplex serial driver. The driver implements a SerialDriver interface and uses I/O Queues for communication between the upper and the lower driver. Event flags are used to notify the application about incoming data, outgoing data and other I/O events.
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-Data Structures

struct  SerialDriverVMT
 SerialDriver virtual methods table. More...
struct  _SerialDriver
 Full duplex serial driver class. More...

-Modules

 Serial Low Level Driver
 

Serial Driver low level driver template.

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-Defines

#define SD_NO_ERROR   0
 No pending conditions.
#define SD_CONNECTED   1
 Connection happened.
#define SD_DISCONNECTED   2
 Disconnection happened.
#define SD_PARITY_ERROR   4
 Parity error happened.
#define SD_FRAMING_ERROR   8
 Framing error happened.
#define SD_OVERRUN_ERROR   16
 Overflow happened.
#define SD_NOISE_ERROR   32
 Noise on the line.
#define SD_BREAK_DETECTED   64
 Break detected.
#define SERIAL_DEFAULT_BITRATE   38400
 Default bit rate.
#define SERIAL_BUFFERS_SIZE   64
 Serial buffers size.
#define _serial_driver_methods   _base_asynchronous_channel_methods
 SerialDriver specific methods.
#define sdPutWouldBlock(sdp)   chOQIsFull(&(sdp)->oqueue)
 Direct output check on a SerialDriver.
#define sdGetWouldBlock(sdp)   chIQIsEmpty(&(sdp)->iqueue)
 Direct input check on a SerialDriver.
#define sdPut(sdp, b)   chOQPut(&(sdp)->oqueue, b)
 Direct write to a SerialDriver.
#define sdPutTimeout(sdp, b, t)   chOQPutTimeout(&(sdp)->iqueue, b, t)
 Direct write to a SerialDriver with timeout specification.
#define sdGet(sdp)   chIQGet(&(sdp)->iqueue)
 Direct read from a SerialDriver.
#define sdGetTimeout(sdp, t)   chIQGetTimeout(&(sdp)->iqueue, t)
 Direct read from a SerialDriver with timeout specification.
#define sdWrite(sdp, b, n)   chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE)
 Direct blocking write to a SerialDriver.
#define sdWriteTimeout(sdp, b, n, t)   chOQWriteTimeout(&(sdp)->oqueue, b, n, t)
 Direct blocking write to a SerialDriver with timeout specification.
#define sdAsynchronousWrite(sdp, b, n)   chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE)
 Direct non-blocking write to a SerialDriver.
#define sdRead(sdp, b, n)   chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE)
 Direct blocking read from a SerialDriver.
#define sdReadTimeout(sdp, b, n, t)   chIQReadTimeout(&(sdp)->iqueue, b, n, t)
 Direct blocking read from a SerialDriver with timeout specification.
#define sdAsynchronousRead(sdp, b, n)   chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE)
 Direct non-blocking read from a SerialDriver.
#define sdGetStatusChangeEventSource(ip)   (&((ip)->vmt->sevent))
 Returns the status change event source.

-Typedefs

typedef struct _SerialDriver SerialDriver
 Structure representing a serial driver.

-Enumerations

enum  sdstate_t { SD_UNINIT = 0, -SD_STOP = 1, -SD_READY = 2 - }
 

Driver state machine possible states.

- More...

-Functions

void sdInit (void)
 Serial Driver initialization.
void sdObjectInit (SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify)
 Initializes a generic full duplex driver object.
void sdStart (SerialDriver *sdp, const SerialConfig *config)
 Configures and starts the driver.
void sdStop (SerialDriver *sdp)
 Stops the driver.
void sdIncomingDataI (SerialDriver *sdp, uint8_t b)
 Handles incoming data.
msg_t sdRequestDataI (SerialDriver *sdp)
 Handles outgoing data.
void sdAddFlagsI (SerialDriver *sdp, sdflags_t mask)
 Handles communication events/errors.
sdflags_t sdGetAndClearFlags (SerialDriver *sdp)
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Noise on the line.

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Default bit rate.

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Serial buffers size.

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Definition at line 116 of file serial.h.

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#define sdPutWouldBlock( sdp )    chOQIsFull(&(sdp)->oqueue)
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Direct output check on a SerialDriver.

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chIOPutWouldBlock()
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Definition at line 151 of file serial.h.

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#define sdGetWouldBlock( sdp )    chIQIsEmpty(&(sdp)->iqueue)
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Direct input check on a SerialDriver.

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chIOGetWouldBlock()
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Definition at line 161 of file serial.h.

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#define sdPut( sdp,
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Direct write to a SerialDriver.

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chIOPut()
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Definition at line 171 of file serial.h.

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#define sdPutTimeout( sdp,
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Direct write to a SerialDriver with timeout specification.

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chIOPutTimeout()
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Definition at line 181 of file serial.h.

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#define sdGet( sdp )    chIQGet(&(sdp)->iqueue)
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Direct read from a SerialDriver.

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chIOGet()
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Definition at line 191 of file serial.h.

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#define sdGetTimeout( sdp,
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Direct read from a SerialDriver with timeout specification.

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This function bypasses the indirect access to the channel and reads directly from the input queue. This is faster but cannot be used to read from different channels implementations.

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chIOGetTimeout()
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Definition at line 201 of file serial.h.

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#define sdWrite( sdp,
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Direct blocking write to a SerialDriver.

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Definition at line 211 of file serial.h.

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chIOWriteTimeout()
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Definition at line 223 of file serial.h.

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Direct non-blocking write to a SerialDriver.

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Definition at line 234 of file serial.h.

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#define sdRead( sdp,
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Direct blocking read from a SerialDriver.

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chIOReadTimeout()
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Definition at line 245 of file serial.h.

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Direct blocking read from a SerialDriver with timeout specification.

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Definition at line 257 of file serial.h.

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Direct non-blocking read from a SerialDriver.

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chIOReadTimeout()
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Definition at line 268 of file serial.h.

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#define sdGetStatusChangeEventSource( ip )    (&((ip)->vmt->sevent))
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Returns the status change event source.

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The status change event source is broadcasted when the channel status is updated, the status flags can then be fetched and cheared by using sdGetAndClearFlags().

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Definition at line 280 of file serial.h.

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typedef struct _SerialDriver SerialDriver
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Structure representing a serial driver.

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Definition at line 109 of file serial.h.

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enum sdstate_t
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Driver state machine possible states.

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Not initialized.

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Stopped.

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Ready.

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Definition at line 100 of file serial.h.

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void sdInit (void  ) 
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Serial Driver initialization.

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Definition at line 110 of file serial.c.

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Referenced by halInit().

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void sdObjectInit (SerialDriver *  sdp,
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qnotify_t  onotify 
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Initializes a generic full duplex driver object.

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The HW dependent part of the initialization has to be performed outside, usually in the hardware initialization code.

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[out] sdp pointer to a SerialDriver structure
[in] inotify pointer to a callback function that is invoked when some data is read from the Queue. The value can be NULL.
[in] onotify pointer to a callback function that is invoked when some data is written in the Queue. The value can be NULL.
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Definition at line 128 of file serial.c.

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void sdStart (SerialDriver *  sdp,
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Configures and starts the driver.

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Definition at line 148 of file serial.c.

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void sdStop (SerialDriver *  sdp ) 
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Stops the driver.

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Any thread waiting on the driver's queues will be awakened with the message Q_RESET.

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[in] sdp pointer to a SerialDrive object
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Definition at line 168 of file serial.c.

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void sdIncomingDataI (SerialDriver *  sdp,
uint8_t  b 
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Handles incoming data.

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This function must be called from the input interrupt service routine in order to enqueue incoming data and generate the related events.

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Definition at line 198 of file serial.c.

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msg_t sdRequestDataI (SerialDriver *  sdp ) 
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Handles outgoing data.

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Must be called from the output interrupt service routine in order to get the next byte to be transmitted.

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Q_EMPTY if the queue is empty (the lower driver usually disables the interrupt source when this happens).
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Definition at line 221 of file serial.c.

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void sdAddFlagsI (SerialDriver *  sdp,
sdflags_t  mask 
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Handles communication events/errors.

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Must be called from the I/O interrupt service routine in order to notify I/O conditions as errors, signals change etc.

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Definition at line 240 of file serial.c.

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sdflags_t sdGetAndClearFlags (SerialDriver *  sdp ) 
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Returns and clears the errors mask associated to the driver.

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Definition at line 255 of file serial.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Serial Low Level Driver
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Serial Driver low level driver template. -More...

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Description

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Serial Driver low level driver template.

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This file is a template for a serial low level driver.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
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#define _serial_driver_data
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_base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Status Change @p EventSource.*/                                        \
-  EventSource               sevent;                                         \
-  /* I/O driver status flags.*/                                             \
-  sdflags_t                 flags;                                          \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
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SerialDriver specific data.

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Definition at line 76 of file templates/serial_lld.h.

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Typedef Documentation

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Definition at line 59 of file templates/serial_lld.h.

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Function Documentation

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void sd_lld_init (void  ) 
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void sd_lld_start (SerialDriver *  sdp,
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Command Shell
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Description

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Small extendible command line shell.

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This module implements a generic extendible command line interface. The CLI just requires an I/O channel (BaseChannel), more commands can be added to the shell using the configuration structure.

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struct  ShellCommand
 Custom command entry type. More...
struct  ShellConfig
 Shell descriptor type. More...

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#define SHELL_MAX_LINE_LENGTH   64
 Shell maximum input line length.
#define SHELL_MAX_ARGUMENTS   4
 Shell maximum arguments per command.
#define SHELL_USE_IPRINTF   TRUE
 Enforces the use of iprintf() on newlib.

-Typedefs

typedef void(* shellcmd_t )(BaseChannel *chp, int argc, char *argv[])
 Command handler function type.

-Functions

void shellInit (void)
 Shell manager initialization.
Thread * shellCreate (const ShellConfig *scp, size_t size, tprio_t prio)
 Spawns a new shell.
void shellPrint (BaseChannel *chp, const char *msg)
 Prints a string.
void shellPrintLine (BaseChannel *chp, const char *msg)
 Prints a string with a final newline.
bool_t shellGetLine (BaseChannel *chp, char *line, unsigned size)
 Reads a whole line from the input channel.

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EventSource shell_terminated
 Shell termination event source.
EventSource shell_terminated
 Shell termination event source.
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Shell maximum input line length.

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Function Documentation

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void shellInit (void  ) 
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Shell manager initialization.

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[in] size size of the shell working area to be allocated
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[in] msg pointer to the string
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[in] line pointer to the line buffer
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The operation status.
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TRUE the channel was reset or CTRL-D pressed.
FALSE operation successful.
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Shell termination event source.

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Definition at line 48 of file shell.c.

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Shell termination event source.

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Definition at line 48 of file shell.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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SPC563 Drivers
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Device drivers included in the SPC563 support. -More...

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-Collaboration diagram for SPC563 Drivers:
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Description

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Device drivers included in the SPC563 support.

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-Modules

 SPC563 HAL Support
 

HAL support.

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 SPC563 ESCI Support
 

ESCI support.

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-Generated on Sun Nov 28 2010 14:09:59 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/group___s_p_c563___d_r_i_v_e_r_s.png b/ChibiOS_2.0.8/docs/html/group___s_p_c563___d_r_i_v_e_r_s.png deleted file mode 100644 index 1d37ffa..0000000 Binary files a/ChibiOS_2.0.8/docs/html/group___s_p_c563___d_r_i_v_e_r_s.png and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/group___s_p_c563___h_a_l.html b/ChibiOS_2.0.8/docs/html/group___s_p_c563___h_a_l.html deleted file mode 100644 index 6e8da3b..0000000 --- a/ChibiOS_2.0.8/docs/html/group___s_p_c563___h_a_l.html +++ /dev/null @@ -1,1031 +0,0 @@ - - -ChibiOS/RT: SPC563 HAL Support - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines | -Functions
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SPC563 HAL Support
- -[SPC563 Drivers] -

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HAL support. -More...

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-Collaboration diagram for SPC563 HAL Support:
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Description

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HAL support.

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-Defines

#define PLATFORM_NAME   "SPC563M64"
 Platform name.
#define RFD_DIV2   0
#define RFD_DIV4   1
#define RFD_DIV8   2
#define RFD_DIV16   3
#define BIUCR_BANK1_TOO   0x01000000
#define BIUCR_MASTER7_PREFETCH   0x00800000
#define BIUCR_MASTER6_PREFETCH   0x00400000
#define BIUCR_MASTER5_PREFETCH   0x00200000
#define BIUCR_MASTER4_PREFETCH   0x00100000
#define BIUCR_MASTER3_PREFETCH   0x00080000
#define BIUCR_MASTER2_PREFETCH   0x00040000
#define BIUCR_MASTER1_PREFETCH   0x00020000
#define BIUCR_MASTER0_PREFETCH   0x00010000
#define BIUCR_APC_MASK   0x0000E000
#define BIUCR_APC_0   (0 << 13)
#define BIUCR_APC_1   (1 << 13)
#define BIUCR_APC_2   (2 << 13)
#define BIUCR_APC_3   (3 << 13)
#define BIUCR_APC_4   (4 << 13)
#define BIUCR_APC_5   (5 << 13)
#define BIUCR_APC_6   (6 << 13)
#define BIUCR_WWSC_MASK   0x00001800
#define BIUCR_WWSC_0   (0 << 11)
#define BIUCR_WWSC_1   (1 << 11)
#define BIUCR_WWSC_2   (2 << 11)
#define BIUCR_WWSC_3   (3 << 11)
#define BIUCR_RWSC_MASK   0x00001800
#define BIUCR_RWSC_0   (0 << 8)
#define BIUCR_RWSC_1   (1 << 8)
#define BIUCR_RWSC_2   (2 << 8)
#define BIUCR_RWSC_3   (3 << 8)
#define BIUCR_RWSC_4   (4 << 8)
#define BIUCR_RWSC_5   (5 << 8)
#define BIUCR_RWSC_6   (6 << 8)
#define BIUCR_RWSC_7   (7 << 8)
#define BIUCR_DPFEN   0x00000040
#define BIUCR_IPFEN   0x00000010
#define BIUCR_PFLIM_MASK   0x00000060
#define BIUCR_PFLIM_NO   (0 << 1)
#define BIUCR_PFLIM_ON_MISS   (1 << 1)
#define BIUCR_PFLIM_ON_HITMISS   (2 << 1)
#define BIUCR_BFEN   0x00000001
#define SPC563_CLK_BYPASS   FALSE
 Clock bypass.
#define SPC563_ALLOW_OVERCLOCK   FALSE
 Disables the overclock checks.
#define SPC563_CLK_PREDIV   0
 External clock pre-divider.
#define SPC563_CLK_MFD   40
 Multiplication factor divider.
#define SPC563_CLK_RFD   RFD_DIV4
 Reduced frequency divider.
#define SPC563_FLASH_BIUCR
 Flash buffer and prefetching settings.
#define SPC563_PLLCLK   ((EXTCLK / (SPC563_CLK_PREDIV + 1)) * SPC563_CLK_MFD)
 PLL output clock.
#define SPC563_SYSCLK   (SPC563_PLLCLK / (1 << (SPC563_CLK_RFD + 1)))
 PLL output clock.
#define SPC563_FLASH_WS   (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1)
 Flash wait states are a function of the system clock.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void spc563_clock_init (void)
 SPC563 clocks and PLL initialization.
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Define Documentation

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#define PLATFORM_NAME   "SPC563M64"
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Platform name.

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Definition at line 47 of file platforms/SPC56x/hal_lld.h.

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#define RFD_DIV2   0
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Divide VCO frequency by 2.

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Definition at line 49 of file platforms/SPC56x/hal_lld.h.

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#define RFD_DIV4   1
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Divide VCO frequency by 4.

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Definition at line 50 of file platforms/SPC56x/hal_lld.h.

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#define RFD_DIV8   2
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Divide VCO frequency by 8.

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Definition at line 51 of file platforms/SPC56x/hal_lld.h.

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#define RFD_DIV16   3
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Divide VCO frequency by 16.

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Definition at line 52 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_BANK1_TOO   0x01000000
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Use settings for bank1 too.

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Definition at line 56 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_MASTER7_PREFETCH   0x00800000
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Enable master 7 prefetch.

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Definition at line 57 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_MASTER6_PREFETCH   0x00400000
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Enable master 6 prefetch.

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Definition at line 58 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_MASTER5_PREFETCH   0x00200000
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Enable master 5 prefetch.

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Definition at line 59 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_MASTER4_PREFETCH   0x00100000
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Enable master 4 prefetch.

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Definition at line 60 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_MASTER3_PREFETCH   0x00080000
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Enable master 3 prefetch.

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Definition at line 61 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_MASTER2_PREFETCH   0x00040000
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Enable master 2 prefetch.

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Definition at line 62 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_MASTER1_PREFETCH   0x00020000
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Enable master 1 prefetch.

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Definition at line 63 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_MASTER0_PREFETCH   0x00010000
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Enable master 0 prefetch.

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Definition at line 64 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_APC_MASK   0x0000E000
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APC field mask.

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Definition at line 65 of file platforms/SPC56x/hal_lld.h.

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No additional hold cycles.

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Definition at line 66 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_APC_1   (1 << 13)
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1 additional hold cycle.

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Definition at line 67 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_APC_2   (2 << 13)
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2 additional hold cycles.

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Definition at line 68 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_APC_3   (3 << 13)
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3 additional hold cycles.

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Definition at line 69 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_APC_4   (4 << 13)
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4 additional hold cycles.

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Definition at line 70 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_APC_5   (5 << 13)
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5 additional hold cycles.

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Definition at line 71 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_APC_6   (6 << 13)
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6 additional hold cycles.

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Definition at line 72 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_WWSC_MASK   0x00001800
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WWSC field mask.

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Definition at line 73 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_WWSC_0   (0 << 11)
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No write wait states.

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Definition at line 74 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_WWSC_1   (1 << 11)
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1 write wait state.

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Definition at line 75 of file platforms/SPC56x/hal_lld.h.

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2 write wait states.

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Definition at line 76 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_WWSC_3   (3 << 11)
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3 write wait states.

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Definition at line 77 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_RWSC_MASK   0x00001800
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RWSC field mask.

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Definition at line 78 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_RWSC_0   (0 << 8)
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No read wait states.

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Definition at line 79 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_RWSC_1   (1 << 8)
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1 read wait state.

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Definition at line 80 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_RWSC_2   (2 << 8)
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2 read wait states.

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Definition at line 81 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_RWSC_3   (3 << 8)
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3 read wait states.

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Definition at line 82 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_RWSC_4   (4 << 8)
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4 read wait states.

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Definition at line 83 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_RWSC_5   (5 << 8)
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5 read wait states.

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Definition at line 84 of file platforms/SPC56x/hal_lld.h.

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6 read wait states.

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Definition at line 85 of file platforms/SPC56x/hal_lld.h.

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7 read wait states.

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Definition at line 86 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_DPFEN   0x00000040
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Data prefetch enable.

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Definition at line 87 of file platforms/SPC56x/hal_lld.h.

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Instr. prefetch enable.

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Definition at line 88 of file platforms/SPC56x/hal_lld.h.

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PFLIM field mask.

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Definition at line 89 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_PFLIM_NO   (0 << 1)
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No prefetching.

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Definition at line 90 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_PFLIM_ON_MISS   (1 << 1)
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Prefetch on miss.

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Definition at line 91 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_PFLIM_ON_HITMISS   (2 << 1)
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Prefetch on hit and miss.

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Definition at line 92 of file platforms/SPC56x/hal_lld.h.

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#define BIUCR_BFEN   0x00000001
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Flash buffering enable.

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Definition at line 93 of file platforms/SPC56x/hal_lld.h.

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Clock bypass.

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Definition at line 106 of file platforms/SPC56x/hal_lld.h.

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#define SPC563_ALLOW_OVERCLOCK   FALSE
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Disables the overclock checks.

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Definition at line 113 of file platforms/SPC56x/hal_lld.h.

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#define SPC563_CLK_PREDIV   0
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External clock pre-divider.

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Note:
Must be in range 0...14.
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Definition at line 122 of file platforms/SPC56x/hal_lld.h.

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#define SPC563_CLK_MFD   40
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Multiplication factor divider.

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Must be in range 32...96.
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Definition at line 130 of file platforms/SPC56x/hal_lld.h.

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#define SPC563_CLK_RFD   RFD_DIV4
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Reduced frequency divider.

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Definition at line 137 of file platforms/SPC56x/hal_lld.h.

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#define SPC563_FLASH_BIUCR
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(BIUCR_BANK1_TOO |                      \
-                                     BIUCR_MASTER4_PREFETCH |               \
-                                     BIUCR_MASTER0_PREFETCH |               \
-                                     BIUCR_DPFEN |                          \
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Flash buffer and prefetching settings.

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Note:
Please refer to the SPC563M64 reference manual about the meaning of the following bits, if in doubt DO NOT MODIFY IT.
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Definition at line 149 of file platforms/SPC56x/hal_lld.h.

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#define SPC563_PLLCLK   ((EXTCLK / (SPC563_CLK_PREDIV + 1)) * SPC563_CLK_MFD)
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PLL output clock.

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Definition at line 178 of file platforms/SPC56x/hal_lld.h.

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PLL output clock.

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Low level HAL driver initialization.

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SPC563 clocks and PLL initialization.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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SPC563 ESCI Support
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ESCI support. -More...

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Description

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ESCI support.

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The serial driver supports both the SPC563 ESCIs in asynchronous mode.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

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#define SD_MODE_PARITY   0x03
 Parity field mask.
#define SD_MODE_PARITY_NONE   0x00
 No parity.
#define SD_MODE_PARITY_EVEN   0x01
 Even parity.
#define SD_MODE_PARITY_ODD   0x02
 Odd parity.
#define SD_MODE_NORMAL   0x00
 Normal operations.
#define SD_MODE_LOOPBACK   0x80
 Internal loopback.
#define USE_SPC563_ESCIA   TRUE
 eSCI-A driver enable switch.
#define USE_SPC563_ESCIB   TRUE
 eSCI-B driver enable switch.
#define SPC563_ESCIA_PRIORITY   8
 eSCI-A interrupt priority level setting.
#define SPC563_ESCIB_PRIORITY   8
 eSCI-B interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

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 CH_IRQ_HANDLER (vector146)
 eSCI-A interrupt handler.
 CH_IRQ_HANDLER (vector149)
 eSCI-B interrupt handler.
void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

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SerialDriver SD1
 eSCI-A serial driver identifier.
SerialDriver SD2
 eSCI-B serial driver identifier.
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#define SD_MODE_PARITY   0x03
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Parity field mask.

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No parity.

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Even parity.

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Odd parity.

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Definition at line 85 of file platforms/SPC56x/serial_lld.h.

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#define _serial_driver_data
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_base_asynchronous_channel_data                                           \
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-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
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Definition at line 123 of file platforms/SPC56x/serial_lld.h.

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Serial Driver condition flags type.

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Definition at line 99 of file platforms/SPC56x/serial_lld.h.

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CH_IRQ_HANDLER (vector146  ) 
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eSCI-A interrupt handler.

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Definition at line 226 of file platforms/SPC56x/serial_lld.c.

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CH_IRQ_HANDLER (vector149  ) 
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eSCI-B interrupt handler.

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Definition at line 240 of file platforms/SPC56x/serial_lld.c.

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void sd_lld_start (SerialDriver *  sdp,
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Low level serial driver configuration and (re)start.

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SerialDriver SD1
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eSCI-A serial driver identifier.

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Definition at line 48 of file platforms/SPC56x/serial_lld.c.

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eSCI-B serial driver identifier.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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SPI Driver
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Generic SPI Driver. -More...

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Description

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Generic SPI Driver.

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This module implements a generic SPI driver. The driver implements a state machine internally:

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The driver is not thread safe for performance reasons, if you need to access the SPI bus from multiple thread then use the spiAcquireBus() and spiReleaseBus() APIs in order to gain exclusive access.

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 SPI Low Level Driver
 

SPI Driver low level driver template.

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-Defines

#define SPI_USE_MUTUAL_EXCLUSION   TRUE
 Enables the mutual exclusion APIs on the SPI bus.

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enum  spistate_t { SPI_UNINIT = 0, -SPI_STOP = 1, -SPI_READY = 2, -SPI_ACTIVE = 3 - }
 

Driver state machine possible states.

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void spiInit (void)
 SPI Driver initialization.
void spiObjectInit (SPIDriver *spip)
 Initializes the standard part of a SPIDriver structure.
void spiStart (SPIDriver *spip, const SPIConfig *config)
 Configures and activates the SPI peripheral.
void spiStop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spiSelect (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spiUnselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spiIgnore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spiExchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spiSend (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data over the SPI bus.
void spiReceive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.
void spiAcquireBus (SPIDriver *spip)
 Gains exclusive access to the SPI bus.
void spiReleaseBus (SPIDriver *spip)
 Releases exclusive access to the SPI bus.
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#define SPI_USE_MUTUAL_EXCLUSION   TRUE
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Enables the mutual exclusion APIs on the SPI bus.

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Definition at line 52 of file spi.h.

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enum spistate_t
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Driver state machine possible states.

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Not initialized.

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Stopped.

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Ready.

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Slave selected.

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void spiInit (void  ) 
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SPI Driver initialization.

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Definition at line 59 of file spi.c.

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Definition at line 69 of file spi.c.

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void spiStart (SPIDriver *  spip,
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Configures and activates the SPI peripheral.

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Definition at line 88 of file spi.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, SPIDriver::spd_config, SPIDriver::spd_state, spi_lld_start(), SPI_READY, and SPI_STOP.

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Referenced by mmcConnect(), mmcStartSequentialRead(), and mmcStartSequentialWrite().

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void spiStop (SPIDriver *  spip ) 
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Definition at line 107 of file spi.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, SPIDriver::spd_state, spi_lld_stop(), SPI_READY, and SPI_STOP.

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void spiSelect (SPIDriver *  spip ) 
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Asserts the slave select signal and prepares for transfers.

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Definition at line 125 of file spi.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, SPIDriver::spd_state, SPI_ACTIVE, spi_lld_select(), and SPI_READY.

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Referenced by mmcStartSequentialRead(), and mmcStartSequentialWrite().

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void spiUnselect (SPIDriver *  spip ) 
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Deasserts the slave select signal.

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The previously selected peripheral is unselected.

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Definition at line 145 of file spi.c.

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References chDbgAssert, chDbgCheck, chSysLock, chSysUnlock, SPIDriver::spd_state, SPI_ACTIVE, spi_lld_unselect(), and SPI_READY.

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Referenced by mmcSequentialRead(), mmcSequentialWrite(), mmcStartSequentialRead(), mmcStartSequentialWrite(), mmcStopSequentialRead(), and mmcStopSequentialWrite().

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void spiIgnore (SPIDriver *  spip,
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Ignores data on the SPI bus.

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This function transmits a series of idle words on the SPI bus and ignores the received data. This function can be invoked even when a slave select signal has not been yet asserted.

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[in] n number of words to be ignored
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Definition at line 168 of file spi.c.

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References chDbgAssert, chDbgCheck, SPIDriver::spd_state, SPI_ACTIVE, spi_lld_ignore(), and SPI_READY.

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Referenced by mmcConnect(), mmcSequentialRead(), and mmcSequentialWrite().

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void spiExchange (SPIDriver *  spip,
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Exchanges data on the SPI bus.

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This function performs a simultaneous transmit/receive operation.

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[in] n number of words to be exchanged
[in] txbuf the pointer to the transmit buffer
[out] rxbuf the pointer to the receive buffer
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Definition at line 189 of file spi.c.

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void spiSend (SPIDriver *  spip,
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Sends data over the SPI bus.

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Definition at line 209 of file spi.c.

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References chDbgAssert, chDbgCheck, SPIDriver::spd_state, SPI_ACTIVE, and spi_lld_send().

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Referenced by mmcSequentialWrite(), mmcStopSequentialRead(), and mmcStopSequentialWrite().

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Receives data from the SPI bus.

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Definition at line 229 of file spi.c.

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Definition at line 251 of file spi.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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SPI Low Level Driver
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SPI Driver low level driver template. -More...

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Description

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SPI Driver low level driver template.

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This file is a template for a SPI low level driver.

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-Data Structures

struct  SPIConfig
 Driver configuration structure. More...
struct  SPIDriver
 Structure representing a SPI driver. More...

-Functions

void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.
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Function Documentation

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void spi_lld_init (void  ) 
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Low level SPI driver initialization.

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Configures and activates the SPI peripheral.

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Deactivates the SPI peripheral.

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Asserts the slave select signal and prepares for transfers.

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Deasserts the slave select signal.

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The previously selected peripheral is unselected.

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Ignores data on the SPI bus.

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This function transmits a series of idle words on the SPI bus and ignores the received data. This function can be invoked even when a slave select signal has not been yet asserted.

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Exchanges data on the SPI bus.

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[in] n number of words to be exchanged
[in] txbuf the pointer to the transmit buffer
[out] rxbuf the pointer to the receive buffer
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Sends data ever the SPI bus.

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Receives data from the SPI bus.

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Referenced by spiReceive().

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM32 Support
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STM32 specific support. -More...

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Description

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STM32 specific support.

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The STM32 support includes:

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  • DMA capable, high performance, ADC driver.
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 STM32 HAL Support
 

HAL support.

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 STM32 I/O Ports Support
 

I/O Ports peripherals support.

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 STM32 USART Support
 

USART peripherals support.

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 STM32 DMA Support
 

DMA support.

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 STM32 ADC Support
 

ADC peripherals support.

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 STM32 CAN Support
 

CAN peripheral support.

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 STM32 PWM Support
 

TIMx peripherals as PWM generators support.

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 STM32 SPI Support
 

SPI peripherals support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM32 ADC Support
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Description

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ADC peripherals support.

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The ADC driver supports the STM32 ADCs using DMA channels for improved performance.

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-Data Structures

struct  ADCConversionGroup
 Conversion group configuration structure. More...
struct  ADCConfig
 Driver configuration structure. More...
struct  ADCDriver
 Structure representing an ADC driver. More...

-Defines

#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 17)
 Trigger source.
#define ADC_CR2_EXTSEL_SWSTART   (7 << 17)
 Software trigger.
#define ADC_CHANNEL_IN0   0
 External analog input 0.
#define ADC_CHANNEL_IN1   1
 External analog input 1.
#define ADC_CHANNEL_IN2   2
 External analog input 2.
#define ADC_CHANNEL_IN3   3
 External analog input 3.
#define ADC_CHANNEL_IN4   4
 External analog input 4.
#define ADC_CHANNEL_IN5   5
 External analog input 5.
#define ADC_CHANNEL_IN6   6
 External analog input 6.
#define ADC_CHANNEL_IN7   7
 External analog input 7.
#define ADC_CHANNEL_IN8   8
 External analog input 8.
#define ADC_CHANNEL_IN9   9
 External analog input 9.
#define ADC_CHANNEL_IN10   10
 External analog input 10.
#define ADC_CHANNEL_IN11   11
 External analog input 11.
#define ADC_CHANNEL_IN12   12
 External analog input 12.
#define ADC_CHANNEL_IN13   13
 External analog input 13.
#define ADC_CHANNEL_IN14   14
 External analog input 14.
#define ADC_CHANNEL_IN15   15
 External analog input 15.
#define ADC_CHANNEL_SENSOR   16
 Internal temperature sensor.
#define ADC_CHANNEL_VREFINT   17
 Internal reference.
#define USE_STM32_ADC1   TRUE
 ADC1 driver enable switch.
#define STM32_ADC1_DMA_PRIORITY   3
 ADC1 DMA priority (0..3|lowest..highest).
#define STM32_ADC1_IRQ_PRIORITY   5
 ADC1 interrupt priority level setting.
#define STM32_ADC1_DMA_ERROR_HOOK()   chSysHalt()
 ADC1 DMA error hook.

-Typedefs

typedef uint16_t adcsample_t
 ADC sample data type.
typedef uint16_t adc_channels_num_t
 Channels number in a conversion group.
typedef void(* adccallback_t )(adcsample_t *buffer, size_t n)
 ADC notification callback type.

-Functions

 CH_IRQ_HANDLER (Vector6C)
 ADC1 DMA interrupt handler (channel 1).
void adc_lld_init (void)
 Low level ADC driver initialization.
void adc_lld_start (ADCDriver *adcp)
 Configures and activates the ADC peripheral.
void adc_lld_stop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
void adc_lld_start_conversion (ADCDriver *adcp)
 Starts an ADC conversion.
void adc_lld_stop_conversion (ADCDriver *adcp)
 Stops an ongoing conversion.

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ADCDriver ADCD1
 ADC1 driver identifier.
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Define Documentation

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#define ADC_CR2_EXTSEL_SRC( n )    ((n) << 17)
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Trigger source.

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Definition at line 43 of file platforms/STM32/adc_lld.h.

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Software trigger.

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External analog input 0.

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External analog input 1.

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External analog input 2.

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External analog input 3.

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External analog input 4.

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External analog input 5.

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External analog input 6.

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External analog input 7.

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External analog input 8.

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External analog input 9.

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External analog input 11.

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External analog input 12.

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External analog input 13.

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Definition at line 59 of file platforms/STM32/adc_lld.h.

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External analog input 14.

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Definition at line 60 of file platforms/STM32/adc_lld.h.

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External analog input 15.

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Definition at line 61 of file platforms/STM32/adc_lld.h.

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Internal temperature sensor.

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Definition at line 62 of file platforms/STM32/adc_lld.h.

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Internal reference.

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ADC1 driver enable switch.

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Definition at line 75 of file platforms/STM32/adc_lld.h.

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ADC1 DMA priority (0..3|lowest..highest).

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Definition at line 89 of file platforms/STM32/adc_lld.h.

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ADC1 DMA error hook.

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Definition at line 98 of file platforms/STM32/adc_lld.h.

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Typedef Documentation

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ADC sample data type.

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References ADCConversionGroup::acg_circular, ADCDriver::ad_callback, ADCDriver::ad_depth, ADCDriver::ad_grpp, ADCDriver::ad_samples, ADCDriver::ad_sem, ADCDriver::ad_state, adc_lld_stop_conversion(), CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, chSemResetI(), chSysLockFromIsr, chSysUnlockFromIsr, and STM32_ADC1_DMA_ERROR_HOOK.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM32 CAN Support
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CAN peripheral support. -More...

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Description

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CAN peripheral support.

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The CAN driver supports the STM32 bxCAN unit.

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struct  CANTxFrame
 CAN transmission frame. More...
struct  CANRxFrame
 CAN received frame. More...
struct  CANFilter
 CAN filter. More...
struct  CANConfig
 Driver configuration structure. More...
struct  CANDriver
 Structure representing an CAN driver. More...

-Defines

#define CAN_SUPPORTS_SLEEP   TRUE
 This switch defines whether the driver implementation supports a low power switch mode with automatic an wakeup feature.
#define CAN_MAX_FILTERS   28
 Minimum number of CAN filters.
#define CAN_BTR_BRP(n)   (n)
 BRP field macro.
#define CAN_BTR_TS1(n)   ((n) << 16)
 TS1 field macro.
#define CAN_BTR_TS2(n)   ((n) << 20)
 TS2 field macro.
#define CAN_BTR_SJW(n)   ((n) << 24)
 SJW field macro.
#define CAN_IDE_STD   0
 Standard id.
#define CAN_IDE_EXT   1
 Extended id.
#define CAN_RTR_DATA   0
 Data frame.
#define CAN_RTR_REMOTE   1
 Remote frame.
#define USE_STM32_CAN1   TRUE
 CAN1 driver enable switch.
#define STM32_CAN1_IRQ_PRIORITY   11
 CAN1 interrupt priority level setting.

-Typedefs

typedef uint32_t canstatus_t
 CAN status flags.

-Functions

void can_lld_init (void)
 Low level CAN driver initialization.
void can_lld_start (CANDriver *canp)
 Configures and activates the CAN peripheral.
void can_lld_stop (CANDriver *canp)
 Deactivates the CAN peripheral.
bool_t can_lld_can_transmit (CANDriver *canp)
 Determines whether a frame can be transmitted.
void can_lld_transmit (CANDriver *canp, const CANTxFrame *ctfp)
 Inserts a frame into the transmit queue.
bool_t can_lld_can_receive (CANDriver *canp)
 Determines whether a frame has been received.
void can_lld_receive (CANDriver *canp, CANRxFrame *crfp)
 Receives a frame from the input queue.
void can_lld_sleep (CANDriver *canp)
 Enters the sleep mode.
void can_lld_wakeup (CANDriver *canp)
 Enforces leaving the sleep mode.

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CANDriver CAND1
 ADC1 driver identifier.
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This switch defines whether the driver implementation supports a low power switch mode with automatic an wakeup feature.

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Definition at line 56 of file platforms/STM32/can_lld.h.

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Standard id.

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Definition at line 73 of file platforms/STM32/can_lld.h.

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Data frame.

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Remote frame.

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CAN1 driver enable switch.

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Definition at line 88 of file platforms/STM32/can_lld.h.

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CAN1 interrupt priority level setting.

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Definition at line 95 of file platforms/STM32/can_lld.h.

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void can_lld_init (void  ) 
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Low level CAN driver initialization.

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Configures and activates the CAN peripheral.

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Determines whether a frame can be transmitted.

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Inserts a frame into the transmit queue.

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Determines whether a frame has been received.

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Receives a frame from the input queue.

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DMA support.

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The DMA helper driver allows to stop the DMA clock when no other driver requires its services.

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#define DMA1_ID   0
 DMA1 identifier.
#define DMA2_ID   1
 DMA2 identifier.

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void dmaInit (void)
 STM32 DMA helper initialization.
void dmaEnable (uint32_t dma)
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HAL support.

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 STM32F103 HAL Support
 

HAL support for STM32 LD, MD and HD families.

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HAL support for STM32 CL (Connectivity Line) family.

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#define PLATFORM_NAME   "STM32 MD"
 Platform name.

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void hal_lld_init (void)
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void stm32_clock_init (void)
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STM32 I/O Ports Support
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I/O Ports peripherals support.

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This module supports the STM3 GPIO controller. The controller supports the following features (see PAL Driver):

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struct  stm32_gpio_setup_t
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struct  PALConfig
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#define PAL_MODE_STM32_ALTERNATE_PUSHPULL   16
 STM32 specific alternate push-pull output mode.
#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN   17
 STM32 specific alternate open-drain output mode.
#define PAL_IOPORTS_WIDTH   16
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFFF)
 Whole port mask.
#define IOPORT1   GPIOA
 GPIO port A identifier.
#define IOPORT2   GPIOB
 GPIO port B identifier.
#define IOPORT3   GPIOC
 GPIO port C identifier.
#define IOPORT4   GPIOD
 GPIO port D identifier.
#define IOPORT5   GPIOE
 GPIO port E identifier.
#define IOPORT6   GPIOF
 GPIO port F identifier.
#define IOPORT7   GPIOG
 GPIO port G identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 GPIO ports subsystem initialization.
#define pal_lld_readport(port)   ((port)->IDR)
 Reads an I/O port.
#define pal_lld_readlatch(port)   ((port)->ODR)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->ODR = (bits))
 Writes on a I/O port.
#define pal_lld_setport(port, bits)   ((port)->BSRR = (bits))
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)   ((port)->BRR = (bits))
 Clears a bits mask on a I/O port.
#define pal_lld_writegroup(port, mask, offset, bits)
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   pal_lld_writegroup(port, 1, pad, bit)
 Writes a logical state on an output pad.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef GPIO_TypeDef * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 STM32 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

const PALConfig pal_default_config
 PAL setup.
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Define Documentation

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#define PAL_MODE_STM32_ALTERNATE_PUSHPULL   16
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STM32 specific alternate push-pull output mode.

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Definition at line 47 of file platforms/STM32/pal_lld.h.

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STM32 specific alternate open-drain output mode.

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Definition at line 52 of file platforms/STM32/pal_lld.h.

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Width, in bits, of an I/O port.

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Definition at line 101 of file platforms/STM32/pal_lld.h.

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Whole port mask.

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This macro specifies all the valid bits into a port.

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Definition at line 107 of file platforms/STM32/pal_lld.h.

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GPIO port A identifier.

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Definition at line 131 of file platforms/STM32/pal_lld.h.

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GPIO port B identifier.

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GPIO port C identifier.

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Definition at line 141 of file platforms/STM32/pal_lld.h.

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GPIO port D identifier.

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Definition at line 146 of file platforms/STM32/pal_lld.h.

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GPIO port E identifier.

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Definition at line 152 of file platforms/STM32/pal_lld.h.

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GPIO port F identifier.

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Definition at line 159 of file platforms/STM32/pal_lld.h.

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GPIO port G identifier.

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Definition at line 164 of file platforms/STM32/pal_lld.h.

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GPIO ports subsystem initialization.

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Definition at line 175 of file platforms/STM32/pal_lld.h.

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Reads an I/O port.

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This function is implemented by reading the GPIO IDR register, the implementation has no side effects.

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The port bits.
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Definition at line 187 of file platforms/STM32/pal_lld.h.

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Reads the output latch.

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This function is implemented by reading the GPIO ODR register, the implementation has no side effects.

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[in] port the port identifier
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The latched logical states.
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Definition at line 199 of file platforms/STM32/pal_lld.h.

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#define pal_lld_writeport( port,
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Writes on a I/O port.

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This function is implemented by writing the GPIO ODR register, the implementation has no side effects.

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Note:
This function is not meant to be invoked directly by the application code.
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Definition at line 214 of file platforms/STM32/pal_lld.h.

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#define pal_lld_setport( port,
 bits 
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Sets a bits mask on a I/O port.

-

This function is implemented by writing the GPIO BSRR register, the implementation has no side effects.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port the port identifier
[in] bits the bits to be ORed on the specified port
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Definition at line 229 of file platforms/STM32/pal_lld.h.

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#define pal_lld_clearport( port,
 bits 
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Clears a bits mask on a I/O port.

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This function is implemented by writing the GPIO BRR register, the implementation has no side effects.

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Note:
This function is not meant to be invoked directly by the application code.
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[in] port the port identifier
[in] bits the bits to be cleared on the specified port
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Definition at line 244 of file platforms/STM32/pal_lld.h.

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#define pal_lld_writegroup( port,
 mask,
 offset,
 bits 
)
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{                      \
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Writes a group of bits.

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This function is implemented by writing the GPIO BSRR register, the implementation has no side effects.

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This function is not meant to be invoked directly by the application code.
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[in] port the port identifier
[in] mask the group mask
[in] offset the group bit offset within the port
[in] bits the bits to be written. Values exceeding the group width are masked.
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Definition at line 262 of file platforms/STM32/pal_lld.h.

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#define pal_lld_setgroupmode( port,
 mask,
 mode 
)   _pal_lld_setgroupmode(port, mask, mode)
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Pads group mode setup.

-

This function programs a pads group belonging to the same port with the specified mode.

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This function is not meant to be invoked directly by the application code.
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[in] mask the group mask
[in] mode the mode
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Definition at line 281 of file platforms/STM32/pal_lld.h.

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#define pal_lld_writepad( port,
 pad,
 bit 
)   pal_lld_writegroup(port, 1, pad, bit)
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Writes a logical state on an output pad.

-
Note:
This function is not meant to be invoked directly by the application code.
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[in] port the port identifier
[in] pad the pad number within the port
[in] bit logical value, the value must be PAL_LOW or PAL_HIGH
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Definition at line 297 of file platforms/STM32/pal_lld.h.

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Typedef Documentation

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typedef uint32_t ioportmask_t
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Digital I/O port sized unsigned type.

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Definition at line 112 of file platforms/STM32/pal_lld.h.

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typedef GPIO_TypeDef* ioportid_t
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Port Identifier.

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This type can be a scalar or some kind of pointer, do not make any assumption about it, use the provided macros when populating variables of this type.

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Definition at line 120 of file platforms/STM32/pal_lld.h.

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Function Documentation

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void _pal_lld_init (const PALConfig *  config ) 
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STM32 I/O ports configuration.

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Ports A-D(E, F, G) clocks enabled, AFIO clock enabled.

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[in] config the STM32 ports configuration
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void _pal_lld_setgroupmode (ioportid_t  port,
ioportmask_t  mask,
uint_fast8_t  mode 
)
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Pads mode setup.

-

This function programs a pads group belonging to the same port with the specified mode.

-
Note:
This function is not meant to be invoked directly by the application code.
-
-PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
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-Writing on pads programmed as pull-up or pull-down has the side effect to modify the resistor setting because the output latched data is used for the resistor selection.
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[in] port the port identifier
[in] mask the group mask
[in] mode the mode
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Variable Documentation

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const PALConfig pal_default_config
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PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 49 of file platforms/AT91SAM7/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Functions | -Variables
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STM32 PWM Support
- -[STM32 Support] -

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TIMx peripherals as PWM generators support. -More...

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-Collaboration diagram for STM32 PWM Support:
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Description

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TIMx peripherals as PWM generators support.

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The PWM driver supports the STM32 TIMx units as PWM generators.

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-Functions

void pwm_lld_init (void)
 Low level PWM driver initialization.
void pwm_lld_start (PWMDriver *pwmp)
 Configures and activates the PWM peripheral.
void pwm_lld_stop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
void pwm_lld_enable_channel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwm_lld_disable_channel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.

-Variables

PWMDriver PWMD1
 PWM1 driver identifier.
PWMDriver PWMD2
 PWM2 driver identifier.
PWMDriver PWMD3
 PWM3 driver identifier.
PWMDriver PWMD4
 PWM4 driver identifier.
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Function Documentation

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void pwm_lld_init (void  ) 
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Low level PWM driver initialization.

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Definition at line 206 of file platforms/STM32/pwm_lld.c.

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References PWMDriver::pd_enabled_channels, PWMDriver::pd_tim, and pwmObjectInit().

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void pwm_lld_start (PWMDriver *  pwmp ) 
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Configures and activates the PWM peripheral.

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[in] pwmp pointer to a PWMDriver object
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Definition at line 258 of file platforms/STM32/pwm_lld.c.

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References CORTEX_PRIORITY_MASK, NVICEnableVector(), PWMConfig::pc_arr, PWMConfig::pc_callback, PWMConfig::pc_channels, PWMConfig::pc_cr2, PWMConfig::pc_psc, PWMChannelConfig::pcc_mode, PWMDriver::pd_config, PWMDriver::pd_enabled_channels, PWMDriver::pd_state, PWMDriver::pd_tim, PWM_OUTPUT_ACTIVE_HIGH, PWM_OUTPUT_ACTIVE_LOW, PWM_STOP, STM32_PWM1_IRQ_PRIORITY, STM32_PWM2_IRQ_PRIORITY, STM32_PWM3_IRQ_PRIORITY, and STM32_PWM4_IRQ_PRIORITY.

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void pwm_lld_stop (PWMDriver *  pwmp ) 
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Deactivates the PWM peripheral.

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[in] pwmp pointer to a PWMDriver object
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Definition at line 370 of file platforms/STM32/pwm_lld.c.

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References NVICDisableVector(), PWMDriver::pd_enabled_channels, PWMDriver::pd_state, PWMDriver::pd_tim, and PWM_READY.

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void pwm_lld_enable_channel (PWMDriver *  pwmp,
pwmchannel_t  channel,
pwmcnt_t  width 
)
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Enables a PWM channel.

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Parameters:
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[in] pwmp pointer to a PWMDriver object
[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
[in] width PWM pulse width as clock pulses number
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Definition at line 421 of file platforms/STM32/pwm_lld.c.

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References PWMConfig::pc_channels, PWMChannelConfig::pcc_callback, PWMDriver::pd_config, PWMDriver::pd_enabled_channels, and PWMDriver::pd_tim.

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void pwm_lld_disable_channel (PWMDriver *  pwmp,
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)
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Disables a PWM channel.

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The channel is disabled and its output line returned to the idle state.

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[in] pwmp pointer to a PWMDriver object
[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
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Definition at line 446 of file platforms/STM32/pwm_lld.c.

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References PWMDriver::pd_enabled_channels, and PWMDriver::pd_tim.

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Variable Documentation

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PWM1 driver identifier.

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Definition at line 49 of file platforms/STM32/pwm_lld.c.

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PWM2 driver identifier.

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Definition at line 57 of file platforms/STM32/pwm_lld.c.

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PWM3 driver identifier.

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Definition at line 65 of file platforms/STM32/pwm_lld.c.

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PWM4 driver identifier.

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Definition at line 73 of file platforms/STM32/pwm_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM32 USART Support
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USART peripherals support. -More...

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Description

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USART peripherals support.

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The serial driver supports the STM32 USARTs in asynchronous mode.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_STM32_USART1   TRUE
 USART1 driver enable switch.
#define USE_STM32_USART2   TRUE
 USART2 driver enable switch.
#define USE_STM32_USART3   TRUE
 USART3 driver enable switch.
#define USE_STM32_UART4   TRUE
 UART4 driver enable switch.
#define USE_STM32_UART5   TRUE
 UART5 driver enable switch.
#define STM32_USART1_PRIORITY   12
 USART1 interrupt priority level setting.
#define STM32_USART2_PRIORITY   12)
 USART2 interrupt priority level setting.
#define STM32_USART3_PRIORITY   12
 USART3 interrupt priority level setting.
#define STM32_UART4_PRIORITY   12
 UART4 interrupt priority level setting.
#define STM32_UART5_PRIORITY   12
 UART5 interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.
#define USART_CR2_STOP1_BITS   (0 << 12)
 CR2 1 stop bit value.
#define USART_CR2_STOP0P5_BITS   (1 << 12)
 CR2 0.5 stop bit value.
#define USART_CR2_STOP2_BITS   (2 << 12)
 CR2 2 stop bit value.
#define USART_CR2_STOP1P5_BITS   (3 << 12)
 CR2 1.5 stop bit value.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 USART1 serial driver identifier.
SerialDriver SD2
 USART2 serial driver identifier.
SerialDriver SD3
 USART3 serial driver identifier.
SerialDriver SD4
 UART4 serial driver identifier.
SerialDriver SD5
 UART5 serial driver identifier.
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Define Documentation

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USART1 driver enable switch.

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USART2 driver enable switch.

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USART3 driver enable switch.

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UART4 driver enable switch.

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UART5 driver enable switch.

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Definition at line 92 of file platforms/STM32/serial_lld.h.

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USART1 interrupt priority level setting.

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USART2 interrupt priority level setting.

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USART3 interrupt priority level setting.

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UART4 interrupt priority level setting.

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UART5 interrupt priority level setting.

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Definition at line 129 of file platforms/STM32/serial_lld.h.

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#define _serial_driver_data
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_base_asynchronous_channel_data                                           \
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-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Status Change @p EventSource.*/                                        \
-  EventSource               sevent;                                         \
-  /* I/O driver status flags.*/                                             \
-  sdflags_t                 flags;                                          \
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-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
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SerialDriver specific data.

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Definition at line 176 of file platforms/STM32/serial_lld.h.

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CR2 1 stop bit value.

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CR2 0.5 stop bit value.

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Typedef Documentation

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Serial Driver condition flags type.

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Definition at line 144 of file platforms/STM32/serial_lld.h.

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Function Documentation

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void sd_lld_init (void  ) 
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Low level serial driver initialization.

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Low level serial driver configuration and (re)start.

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Low level serial driver stop.

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De-initializes the USART, stops the associated clock, resets the interrupt vector.

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Variable Documentation

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SerialDriver SD1
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USART1 serial driver identifier.

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Definition at line 46 of file platforms/STM32/serial_lld.c.

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USART2 serial driver identifier.

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USART3 serial driver identifier.

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UART4 serial driver identifier.

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UART5 serial driver identifier.

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Definition at line 67 of file platforms/STM32/serial_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM32 SPI Support
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SPI peripherals support. -More...

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Description

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SPI peripherals support.

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The SPI driver supports the STM32 SPIs using DMA channels for improved performance.

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-Data Structures

struct  SPIConfig
 Driver configuration structure. More...
struct  SPIDriver
 Structure representing a SPI driver. More...

-Defines

#define USE_STM32_SPI1   TRUE
 SPI1 driver enable switch.
#define USE_STM32_SPI2   TRUE
 SPI2 driver enable switch.
#define STM32_SPI1_DMA_PRIORITY   2
 SPI1 DMA priority (0..3|lowest..highest).
#define STM32_SPI2_DMA_PRIORITY   2
 SPI2 DMA priority (0..3|lowest..highest).
#define STM32_SPI1_IRQ_PRIORITY   10
 SPI1 interrupt priority level setting.
#define STM32_SPI2_IRQ_PRIORITY   10
 SPI2 interrupt priority level setting.
#define STM32_SPI1_DMA_ERROR_HOOK()   chSysHalt()
 SPI1 DMA error hook.
#define STM32_SPI2_DMA_ERROR_HOOK()   chSysHalt()
 SPI2 DMA error hook.

-Functions

 CH_IRQ_HANDLER (Vector70)
 SPI1 RX DMA interrupt handler (channel 2).
 CH_IRQ_HANDLER (Vector74)
 SPI1 TX DMA interrupt handler (channel 3).
 CH_IRQ_HANDLER (Vector78)
 SPI2 RX DMA interrupt handler (channel 4).
 CH_IRQ_HANDLER (Vector7C)
 SPI2 TX DMA interrupt handler (channel 5).
void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.

-Variables

SPIDriver SPID1
 SPI1 driver identifier.
SPIDriver SPID2
 SPI2 driver identifier.
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Define Documentation

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#define USE_STM32_SPI1   TRUE
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SPI1 driver enable switch.

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If set to TRUE the support for SPI1 is included.

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Definition at line 54 of file platforms/STM32/spi_lld.h.

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SPI2 driver enable switch.

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If set to TRUE the support for SPI2 is included.

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Definition at line 63 of file platforms/STM32/spi_lld.h.

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#define STM32_SPI1_DMA_PRIORITY   2
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SPI1 DMA priority (0..3|lowest..highest).

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Definition at line 73 of file platforms/STM32/spi_lld.h.

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#define STM32_SPI2_DMA_PRIORITY   2
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SPI2 DMA priority (0..3|lowest..highest).

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Definition at line 83 of file platforms/STM32/spi_lld.h.

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#define STM32_SPI1_IRQ_PRIORITY   10
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SPI1 interrupt priority level setting.

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Definition at line 90 of file platforms/STM32/spi_lld.h.

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#define STM32_SPI2_IRQ_PRIORITY   10
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SPI2 interrupt priority level setting.

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Definition at line 97 of file platforms/STM32/spi_lld.h.

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#define STM32_SPI1_DMA_ERROR_HOOK( )    chSysHalt()
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SPI1 DMA error hook.

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Definition at line 106 of file platforms/STM32/spi_lld.h.

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Referenced by CH_IRQ_HANDLER().

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#define STM32_SPI2_DMA_ERROR_HOOK( )    chSysHalt()
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SPI2 DMA error hook.

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Definition at line 115 of file platforms/STM32/spi_lld.h.

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Referenced by CH_IRQ_HANDLER().

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Function Documentation

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CH_IRQ_HANDLER (Vector70  ) 
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SPI1 RX DMA interrupt handler (channel 2).

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Definition at line 120 of file platforms/STM32/spi_lld.c.

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References CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, and STM32_SPI1_DMA_ERROR_HOOK.

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CH_IRQ_HANDLER (Vector74  ) 
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SPI1 TX DMA interrupt handler (channel 3).

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Definition at line 137 of file platforms/STM32/spi_lld.c.

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References CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, and STM32_SPI1_DMA_ERROR_HOOK.

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CH_IRQ_HANDLER (Vector78  ) 
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SPI2 RX DMA interrupt handler (channel 4).

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Definition at line 153 of file platforms/STM32/spi_lld.c.

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References CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, and STM32_SPI2_DMA_ERROR_HOOK.

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CH_IRQ_HANDLER (Vector7C  ) 
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SPI2 TX DMA interrupt handler (channel 5).

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Definition at line 170 of file platforms/STM32/spi_lld.c.

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References CH_IRQ_EPILOGUE, CH_IRQ_PROLOGUE, and STM32_SPI2_DMA_ERROR_HOOK.

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void spi_lld_init (void  ) 
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The previously selected peripheral is unselected.

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Ignores data on the SPI bus.

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This function transmits a series of idle words on the SPI bus and ignores the received data. This function can be invoked even when a slave select signal has not been yet asserted.

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Exchanges data on the SPI bus.

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This function performs a simultaneous transmit/receive operation.

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[in] n number of words to be exchanged
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Variable Documentation

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SPI1 driver identifier.

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Definition at line 45 of file platforms/STM32/spi_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM32F103 HAL Support
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HAL support for STM32 LD, MD and HD families. -More...

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Description

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HAL support for STM32 LD, MD and HD families.

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-Defines

#define STM32_HSICLK   8000000
#define STM32_LSICLK   40000
#define STM32_SW_HSI   (0 << 0)
#define STM32_SW_HSE   (1 << 0)
#define STM32_SW_PLL   (2 << 0)
#define STM32_HPRE_DIV1   (0 << 4)
#define STM32_HPRE_DIV2   (8 << 4)
#define STM32_HPRE_DIV4   (9 << 4)
#define STM32_HPRE_DIV8   (10 << 4)
#define STM32_HPRE_DIV16   (11 << 4)
#define STM32_HPRE_DIV64   (12 << 4)
#define STM32_HPRE_DIV128   (13 << 4)
#define STM32_HPRE_DIV256   (14 << 4)
#define STM32_HPRE_DIV512   (15 << 4)
#define STM32_PPRE1_DIV1   (0 << 8)
#define STM32_PPRE1_DIV2   (4 << 8)
#define STM32_PPRE1_DIV4   (5 << 8)
#define STM32_PPRE1_DIV8   (6 << 8)
#define STM32_PPRE1_DIV16   (7 << 8)
#define STM32_PPRE2_DIV1   (0 << 11)
#define STM32_PPRE2_DIV2   (4 << 11)
#define STM32_PPRE2_DIV4   (5 << 11)
#define STM32_PPRE2_DIV8   (6 << 11)
#define STM32_PPRE2_DIV16   (7 << 11)
#define STM32_ADCPRE_DIV2   (0 << 14)
#define STM32_ADCPRE_DIV4   (1 << 14)
#define STM32_ADCPRE_DIV6   (2 << 14)
#define STM32_ADCPRE_DIV8   (3 << 14)
#define STM32_PLLSRC_HSI   (0 << 16)
#define STM32_PLLSRC_HSE   (1 << 16)
#define STM32_PLLXTPRE_DIV1   (0 << 17)
#define STM32_PLLXTPRE_DIV2   (1 << 17)
#define STM32_MCO_NOCLOCK   (0 << 24)
#define STM32_MCO_SYSCLK   (4 << 24)
#define STM32_MCO_HSI   (5 << 24)
#define STM32_MCO_HSE   (6 << 24)
#define STM32_MCO_PLLDIV2   (7 << 24)
#define WWDG_IRQHandler   Vector40
#define PVD_IRQHandler   Vector44
#define TAMPER_IRQHandler   Vector48
#define RTC_IRQHandler   Vector4C
#define FLASH_IRQHandler   Vector50
#define RCC_IRQHandler   Vector54
#define EXTI0_IRQHandler   Vector58
#define EXTI1_IRQHandler   Vector5C
#define EXTI2_IRQHandler   Vector60
#define EXTI3_IRQHandler   Vector64
#define EXTI4_IRQHandler   Vector68
#define DMA1_Ch1_IRQHandler   Vector6C
#define DMA1_Ch2_IRQHandler   Vector70
#define DMA1_Ch3_IRQHandler   Vector74
#define DMA1_Ch4_IRQHandler   Vector78
#define DMA1_Ch5_IRQHandler   Vector7C
#define DMA1_Ch6_IRQHandler   Vector80
#define DMA1_Ch7_IRQHandler   Vector84
#define ADC1_2_IRQHandler   Vector88
#define CAN1_TX_IRQHandler   Vector8C
#define USB_HP_IRQHandler   Vector8C
#define CAN1_RX0_IRQHandler   Vector90
#define USB_LP_IRQHandler   Vector90
#define CAN1_RX1_IRQHandler   Vector94
#define CAN1_SCE_IRQHandler   Vector98
#define EXTI9_5_IRQHandler   Vector9C
#define TIM1_BRK_IRQHandler   VectorA0
#define TIM1_UP_IRQHandler   VectorA4
#define TIM1_TRG_COM_IRQHandler   VectorA8
#define TIM1_CC_IRQHandler   VectorAC
#define TIM2_IRQHandler   VectorB0
#define TIM3_IRQHandler   VectorB4
#define TIM4_IRQHandler   VectorB8
#define I2C1_EV_IRQHandler   VectorBC
#define I2C1_ER_IRQHandler   VectorC0
#define I2C2_EV_IRQHandler   VectorC4
#define I2C2_ER_IRQHandler   VectorC8
#define SPI1_IRQHandler   VectorCC
#define SPI2_IRQHandler   VectorD0
#define USART1_IRQHandler   VectorD4
#define USART2_IRQHandler   VectorD8
#define USART3_IRQHandler   VectorDC
#define EXTI15_10_IRQHandler   VectorE0
#define RTCAlarm_IRQHandler   VectorE4
#define USBWakeUp_IRQHandler   VectorE8
#define TIM8_BRK_IRQHandler   VectorEC
#define TIM8_UP_IRQHandler   VectorF0
#define TIM8_TRG_COM_IRQHandler   VectorF4
#define TIM8_CC_IRQHandler   VectorF8
#define ADC3_IRQHandler   VectorFC
#define FSMC_IRQHandler   Vector100
#define SDIO_IRQHandler   Vector104
#define TIM5_IRQHandler   Vector108
#define SPI3_IRQHandler   Vector10C
#define UART4_IRQHandler   Vector110
#define UART5_IRQHandler   Vector114
#define TIM6_IRQHandler   Vector118
#define TIM7_IRQHandler   Vector11C
#define DMA2_Ch1_IRQHandler   Vector120
#define DMA2_Ch2_IRQHandler   Vector124
#define DMA2_Ch3_IRQHandler   Vector128
#define DMA2_Ch4_5_IRQHandler   Vector12C
#define STM32_SW   STM32_SW_PLL
 Main clock source selection.
#define STM32_PLLSRC   STM32_PLLSRC_HSE
 Clock source for the PLL.
#define STM32_PLLXTPRE   STM32_PLLXTPRE_DIV1
 Crystal PLL pre-divider.
#define STM32_PLLMUL_VALUE   9
 PLL multiplier value.
#define STM32_HPRE   STM32_HPRE_DIV1
 AHB prescaler value.
#define STM32_PPRE1   STM32_PPRE1_DIV2
 APB1 prescaler value.
#define STM32_PPRE2   STM32_PPRE2_DIV2
 APB2 prescaler value.
#define STM32_ADCPRE   STM32_ADCPRE_DIV4
 ADC prescaler value.
#define STM32_MCO   STM32_MCO_NOCLOCK
 MCO pin setting.
#define STM32_PLLMUL   ((STM32_PLLMUL_VALUE - 2) << 18)
 PLLMUL field.
#define STM32_PLLCLKIN   (STM32_HSECLK / 1)
 PLL input clock frequency.
#define STM32_PLLCLKOUT   (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
 PLL output clock frequency.
#define STM32_SYSCLK   STM32_PLLCLKOUT
 System clock source.
#define STM32_HCLK   (STM32_SYSCLK / 1)
 AHB frequency.
#define STM32_PCLK1   (STM32_HCLK / 1)
 APB1 frequency.
#define STM32_PCLK2   (STM32_HCLK / 1)
 APB2 frequency.
#define STM32_ADCCLK   (STM32_PCLK2 / 2)
 ADC frequency.
#define STM32_TIMCLK1   (STM32_PCLK1 * 1)
 Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
#define STM32_TIMCLK2   (STM32_PCLK2 * 1)
 Timers 1, 8, 9, 10 and 11 clock.
#define STM32_FLASHBITS   0x00000010
 Flash settings.
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Define Documentation

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#define STM32_HSICLK   8000000
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High speed internal clock.

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Definition at line 42 of file hal_lld_f103.h.

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#define STM32_LSICLK   40000
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Low speed internal clock.

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Definition at line 43 of file hal_lld_f103.h.

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#define STM32_SW_HSI   (0 << 0)
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SYSCLK source is HSI.

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Definition at line 46 of file hal_lld_f103.h.

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#define STM32_SW_HSE   (1 << 0)
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SYSCLK source is HSE.

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Definition at line 47 of file hal_lld_f103.h.

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#define STM32_SW_PLL   (2 << 0)
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SYSCLK source is PLL.

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Definition at line 48 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV1   (0 << 4)
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SYSCLK divided by 1.

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Definition at line 50 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV2   (8 << 4)
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SYSCLK divided by 2.

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Definition at line 51 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV4   (9 << 4)
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SYSCLK divided by 4.

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Definition at line 52 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV8   (10 << 4)
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SYSCLK divided by 8.

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Definition at line 53 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV16   (11 << 4)
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SYSCLK divided by 16.

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Definition at line 54 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV64   (12 << 4)
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SYSCLK divided by 64.

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Definition at line 55 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV128   (13 << 4)
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SYSCLK divided by 128.

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Definition at line 56 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV256   (14 << 4)
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SYSCLK divided by 256.

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Definition at line 57 of file hal_lld_f103.h.

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#define STM32_HPRE_DIV512   (15 << 4)
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SYSCLK divided by 512.

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Definition at line 58 of file hal_lld_f103.h.

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#define STM32_PPRE1_DIV1   (0 << 8)
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HCLK divided by 1.

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Definition at line 60 of file hal_lld_f103.h.

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#define STM32_PPRE1_DIV2   (4 << 8)
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HCLK divided by 2.

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Definition at line 61 of file hal_lld_f103.h.

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#define STM32_PPRE1_DIV4   (5 << 8)
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HCLK divided by 4.

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Definition at line 62 of file hal_lld_f103.h.

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#define STM32_PPRE1_DIV8   (6 << 8)
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HCLK divided by 8.

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Definition at line 63 of file hal_lld_f103.h.

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#define STM32_PPRE1_DIV16   (7 << 8)
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HCLK divided by 16.

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Definition at line 64 of file hal_lld_f103.h.

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#define STM32_PPRE2_DIV1   (0 << 11)
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HCLK divided by 1.

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Definition at line 66 of file hal_lld_f103.h.

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#define STM32_PPRE2_DIV2   (4 << 11)
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HCLK divided by 2.

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Definition at line 67 of file hal_lld_f103.h.

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#define STM32_PPRE2_DIV4   (5 << 11)
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HCLK divided by 4.

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Definition at line 68 of file hal_lld_f103.h.

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#define STM32_PPRE2_DIV8   (6 << 11)
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HCLK divided by 8.

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Definition at line 69 of file hal_lld_f103.h.

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#define STM32_PPRE2_DIV16   (7 << 11)
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HCLK divided by 16.

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Definition at line 70 of file hal_lld_f103.h.

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#define STM32_ADCPRE_DIV2   (0 << 14)
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HCLK divided by 2.

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Definition at line 72 of file hal_lld_f103.h.

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#define STM32_ADCPRE_DIV4   (1 << 14)
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HCLK divided by 4.

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Definition at line 73 of file hal_lld_f103.h.

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#define STM32_ADCPRE_DIV6   (2 << 14)
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HCLK divided by 6.

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Definition at line 74 of file hal_lld_f103.h.

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#define STM32_ADCPRE_DIV8   (3 << 14)
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HCLK divided by 8.

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Definition at line 75 of file hal_lld_f103.h.

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#define STM32_PLLSRC_HSI   (0 << 16)
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PLL clock source is HSI.

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Definition at line 77 of file hal_lld_f103.h.

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#define STM32_PLLSRC_HSE   (1 << 16)
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PLL clock source is HSE.

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Definition at line 78 of file hal_lld_f103.h.

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#define STM32_PLLXTPRE_DIV1   (0 << 17)
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HSE divided by 1.

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Definition at line 80 of file hal_lld_f103.h.

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#define STM32_PLLXTPRE_DIV2   (1 << 17)
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HSE divided by 2.

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Definition at line 81 of file hal_lld_f103.h.

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#define STM32_MCO_NOCLOCK   (0 << 24)
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No clock on MCO pin.

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Definition at line 83 of file hal_lld_f103.h.

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#define STM32_MCO_SYSCLK   (4 << 24)
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SYSCLK on MCO pin.

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Definition at line 84 of file hal_lld_f103.h.

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#define STM32_MCO_HSI   (5 << 24)
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HSI clock on MCO pin.

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Definition at line 85 of file hal_lld_f103.h.

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#define STM32_MCO_HSE   (6 << 24)
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HSE clock on MCO pin.

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Definition at line 86 of file hal_lld_f103.h.

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#define STM32_MCO_PLLDIV2   (7 << 24)
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PLL/2 clock on MCO pin.

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Definition at line 87 of file hal_lld_f103.h.

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#define WWDG_IRQHandler   Vector40
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Window Watchdog.

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Definition at line 93 of file hal_lld_f103.h.

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#define PVD_IRQHandler   Vector44
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PVD through EXTI Line detect.

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Definition at line 94 of file hal_lld_f103.h.

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#define TAMPER_IRQHandler   Vector48
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Tamper.

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Definition at line 96 of file hal_lld_f103.h.

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#define RTC_IRQHandler   Vector4C
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RTC.

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Definition at line 97 of file hal_lld_f103.h.

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#define FLASH_IRQHandler   Vector50
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Flash.

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Definition at line 98 of file hal_lld_f103.h.

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#define RCC_IRQHandler   Vector54
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RCC.

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Definition at line 99 of file hal_lld_f103.h.

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#define EXTI0_IRQHandler   Vector58
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EXTI Line 0.

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Definition at line 100 of file hal_lld_f103.h.

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#define EXTI1_IRQHandler   Vector5C
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EXTI Line 1.

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Definition at line 101 of file hal_lld_f103.h.

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#define EXTI2_IRQHandler   Vector60
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EXTI Line 2.

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Definition at line 102 of file hal_lld_f103.h.

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#define EXTI3_IRQHandler   Vector64
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EXTI Line 3.

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Definition at line 103 of file hal_lld_f103.h.

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#define EXTI4_IRQHandler   Vector68
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EXTI Line 4.

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Definition at line 104 of file hal_lld_f103.h.

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#define DMA1_Ch1_IRQHandler   Vector6C
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DMA1 Channel 1.

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Definition at line 105 of file hal_lld_f103.h.

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#define DMA1_Ch2_IRQHandler   Vector70
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DMA1 Channel 2.

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Definition at line 106 of file hal_lld_f103.h.

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#define DMA1_Ch3_IRQHandler   Vector74
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DMA1 Channel 3.

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Definition at line 107 of file hal_lld_f103.h.

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#define DMA1_Ch4_IRQHandler   Vector78
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DMA1 Channel 4.

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Definition at line 108 of file hal_lld_f103.h.

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#define DMA1_Ch5_IRQHandler   Vector7C
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DMA1 Channel 5.

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Definition at line 109 of file hal_lld_f103.h.

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#define DMA1_Ch6_IRQHandler   Vector80
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DMA1 Channel 6.

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Definition at line 110 of file hal_lld_f103.h.

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#define DMA1_Ch7_IRQHandler   Vector84
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DMA1 Channel 7.

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Definition at line 111 of file hal_lld_f103.h.

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#define ADC1_2_IRQHandler   Vector88
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ADC1_2.

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Definition at line 112 of file hal_lld_f103.h.

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#define CAN1_TX_IRQHandler   Vector8C
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CAN1 TX.

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Definition at line 113 of file hal_lld_f103.h.

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#define USB_HP_IRQHandler   Vector8C
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USB High Priority, CAN1 TX.

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Definition at line 114 of file hal_lld_f103.h.

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#define CAN1_RX0_IRQHandler   Vector90
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CAN1 RX0.

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Definition at line 115 of file hal_lld_f103.h.

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#define USB_LP_IRQHandler   Vector90
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USB Low Priority, CAN1 RX0.

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Definition at line 116 of file hal_lld_f103.h.

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#define CAN1_RX1_IRQHandler   Vector94
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CAN1 RX1.

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Definition at line 117 of file hal_lld_f103.h.

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#define CAN1_SCE_IRQHandler   Vector98
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CAN1 SCE.

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Definition at line 118 of file hal_lld_f103.h.

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#define EXTI9_5_IRQHandler   Vector9C
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EXTI Line 9..5.

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Definition at line 119 of file hal_lld_f103.h.

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#define TIM1_BRK_IRQHandler   VectorA0
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TIM1 Break.

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Definition at line 120 of file hal_lld_f103.h.

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#define TIM1_UP_IRQHandler   VectorA4
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TIM1 Update.

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Definition at line 121 of file hal_lld_f103.h.

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#define TIM1_TRG_COM_IRQHandler   VectorA8
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TIM1 Trigger and Commutation.

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Definition at line 122 of file hal_lld_f103.h.

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#define TIM1_CC_IRQHandler   VectorAC
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TIM1 Capture Compare.

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Definition at line 124 of file hal_lld_f103.h.

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#define TIM2_IRQHandler   VectorB0
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TIM2.

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Definition at line 125 of file hal_lld_f103.h.

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#define TIM3_IRQHandler   VectorB4
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TIM3.

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Definition at line 126 of file hal_lld_f103.h.

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#define TIM4_IRQHandler   VectorB8
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TIM4.

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Definition at line 128 of file hal_lld_f103.h.

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#define I2C1_EV_IRQHandler   VectorBC
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I2C1 Event.

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Definition at line 130 of file hal_lld_f103.h.

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#define I2C1_ER_IRQHandler   VectorC0
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I2C1 Error.

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Definition at line 131 of file hal_lld_f103.h.

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#define I2C2_EV_IRQHandler   VectorC4
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I2C2 Event.

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Definition at line 133 of file hal_lld_f103.h.

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#define I2C2_ER_IRQHandler   VectorC8
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I2C2 Error.

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Definition at line 134 of file hal_lld_f103.h.

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#define SPI1_IRQHandler   VectorCC
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SPI1.

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Definition at line 136 of file hal_lld_f103.h.

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#define SPI2_IRQHandler   VectorD0
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SPI2.

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Definition at line 138 of file hal_lld_f103.h.

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#define USART1_IRQHandler   VectorD4
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USART1.

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Definition at line 140 of file hal_lld_f103.h.

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#define USART2_IRQHandler   VectorD8
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USART2.

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Definition at line 141 of file hal_lld_f103.h.

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#define USART3_IRQHandler   VectorDC
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USART3.

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Definition at line 143 of file hal_lld_f103.h.

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#define EXTI15_10_IRQHandler   VectorE0
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EXTI Line 15..10.

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Definition at line 145 of file hal_lld_f103.h.

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#define RTCAlarm_IRQHandler   VectorE4
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RTC Alarm through EXTI.

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Definition at line 146 of file hal_lld_f103.h.

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#define USBWakeUp_IRQHandler   VectorE8
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USB Wakeup from suspend.

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Definition at line 147 of file hal_lld_f103.h.

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#define TIM8_BRK_IRQHandler   VectorEC
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TIM8 Break.

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Definition at line 149 of file hal_lld_f103.h.

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#define TIM8_UP_IRQHandler   VectorF0
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TIM8 Update.

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Definition at line 150 of file hal_lld_f103.h.

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#define TIM8_TRG_COM_IRQHandler   VectorF4
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TIM8 Trigger and Commutation.

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Definition at line 151 of file hal_lld_f103.h.

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#define TIM8_CC_IRQHandler   VectorF8
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TIM8 Capture Compare.

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Definition at line 153 of file hal_lld_f103.h.

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#define ADC3_IRQHandler   VectorFC
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ADC3.

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Definition at line 154 of file hal_lld_f103.h.

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#define FSMC_IRQHandler   Vector100
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FSMC.

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Definition at line 155 of file hal_lld_f103.h.

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#define SDIO_IRQHandler   Vector104
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SDIO.

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Definition at line 156 of file hal_lld_f103.h.

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#define TIM5_IRQHandler   Vector108
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TIM5.

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Definition at line 157 of file hal_lld_f103.h.

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#define SPI3_IRQHandler   Vector10C
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SPI3.

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Definition at line 158 of file hal_lld_f103.h.

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#define UART4_IRQHandler   Vector110
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UART4.

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Definition at line 159 of file hal_lld_f103.h.

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#define UART5_IRQHandler   Vector114
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UART5.

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Definition at line 160 of file hal_lld_f103.h.

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#define TIM6_IRQHandler   Vector118
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TIM6.

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Definition at line 161 of file hal_lld_f103.h.

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#define TIM7_IRQHandler   Vector11C
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TIM7.

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Definition at line 162 of file hal_lld_f103.h.

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#define DMA2_Ch1_IRQHandler   Vector120
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DMA2 Channel1.

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Definition at line 163 of file hal_lld_f103.h.

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#define DMA2_Ch2_IRQHandler   Vector124
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DMA2 Channel2.

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Definition at line 164 of file hal_lld_f103.h.

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#define DMA2_Ch3_IRQHandler   Vector128
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DMA2 Channel3.

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Definition at line 165 of file hal_lld_f103.h.

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#define DMA2_Ch4_5_IRQHandler   Vector12C
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DMA2 Channel4 & Channel5.

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Definition at line 166 of file hal_lld_f103.h.

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#define STM32_SW   STM32_SW_PLL
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Main clock source selection.

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Definition at line 181 of file hal_lld_f103.h.

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#define STM32_PLLSRC   STM32_PLLSRC_HSE
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Clock source for the PLL.

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Definition at line 192 of file hal_lld_f103.h.

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#define STM32_PLLXTPRE   STM32_PLLXTPRE_DIV1
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Crystal PLL pre-divider.

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Definition at line 203 of file hal_lld_f103.h.

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#define STM32_PLLMUL_VALUE   9
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PLL multiplier value.

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Definition at line 213 of file hal_lld_f103.h.

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#define STM32_HPRE   STM32_HPRE_DIV1
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AHB prescaler value.

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Definition at line 222 of file hal_lld_f103.h.

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#define STM32_PPRE1   STM32_PPRE1_DIV2
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APB1 prescaler value.

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Definition at line 229 of file hal_lld_f103.h.

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#define STM32_PPRE2   STM32_PPRE2_DIV2
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APB2 prescaler value.

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Definition at line 236 of file hal_lld_f103.h.

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#define STM32_ADCPRE   STM32_ADCPRE_DIV4
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ADC prescaler value.

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Definition at line 243 of file hal_lld_f103.h.

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#define STM32_MCO   STM32_MCO_NOCLOCK
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MCO pin setting.

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Definition at line 250 of file hal_lld_f103.h.

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#define STM32_PLLMUL   ((STM32_PLLMUL_VALUE - 2) << 18)
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PLLMUL field.

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Definition at line 267 of file hal_lld_f103.h.

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#define STM32_PLLCLKIN   (STM32_HSECLK / 1)
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PLL input clock frequency.

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Definition at line 277 of file hal_lld_f103.h.

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#define STM32_PLLCLKOUT   (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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PLL output clock frequency.

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Definition at line 295 of file hal_lld_f103.h.

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#define STM32_SYSCLK   STM32_PLLCLKOUT
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System clock source.

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Definition at line 306 of file hal_lld_f103.h.

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#define STM32_HCLK   (STM32_SYSCLK / 1)
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AHB frequency.

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Definition at line 324 of file hal_lld_f103.h.

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#define STM32_PCLK1   (STM32_HCLK / 1)
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APB1 frequency.

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Definition at line 354 of file hal_lld_f103.h.

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#define STM32_PCLK2   (STM32_HCLK / 1)
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APB2 frequency.

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Definition at line 376 of file hal_lld_f103.h.

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#define STM32_ADCCLK   (STM32_PCLK2 / 2)
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ADC frequency.

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Definition at line 398 of file hal_lld_f103.h.

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#define STM32_TIMCLK1   (STM32_PCLK1 * 1)
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Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.

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Definition at line 418 of file hal_lld_f103.h.

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#define STM32_TIMCLK2   (STM32_PCLK2 * 1)
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Timers 1, 8, 9, 10 and 11 clock.

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Definition at line 427 of file hal_lld_f103.h.

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#define STM32_FLASHBITS   0x00000010
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Flash settings.

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Definition at line 436 of file hal_lld_f103.h.

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-Generated on Sun Nov 28 2010 14:09:59 for ChibiOS/RT by doxygen 1.7.1
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines
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STM32F105/F107 HAL Support
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HAL support for STM32 CL (Connectivity Line) family. -More...

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-Collaboration diagram for STM32F105/F107 HAL Support:
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Description

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HAL support for STM32 CL (Connectivity Line) family.

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-Defines

#define STM32_HSICLK   8000000
#define STM32_LSICLK   40000
#define STM32_SW_HSI   (0 << 0)
#define STM32_SW_HSE   (1 << 0)
#define STM32_SW_PLL   (2 << 0)
#define STM32_HPRE_DIV1   (0 << 4)
#define STM32_HPRE_DIV2   (8 << 4)
#define STM32_HPRE_DIV4   (9 << 4)
#define STM32_HPRE_DIV8   (10 << 4)
#define STM32_HPRE_DIV16   (11 << 4)
#define STM32_HPRE_DIV64   (12 << 4)
#define STM32_HPRE_DIV128   (13 << 4)
#define STM32_HPRE_DIV256   (14 << 4)
#define STM32_HPRE_DIV512   (15 << 4)
#define STM32_PPRE1_DIV1   (0 << 8)
#define STM32_PPRE1_DIV2   (4 << 8)
#define STM32_PPRE1_DIV4   (5 << 8)
#define STM32_PPRE1_DIV8   (6 << 8)
#define STM32_PPRE1_DIV16   (7 << 8)
#define STM32_PPRE2_DIV1   (0 << 11)
#define STM32_PPRE2_DIV2   (4 << 11)
#define STM32_PPRE2_DIV4   (5 << 11)
#define STM32_PPRE2_DIV8   (6 << 11)
#define STM32_PPRE2_DIV16   (7 << 11)
#define STM32_ADCPRE_DIV2   (0 << 14)
#define STM32_ADCPRE_DIV4   (1 << 14)
#define STM32_ADCPRE_DIV6   (2 << 14)
#define STM32_ADCPRE_DIV8   (3 << 14)
#define STM32_PLLSRC_HSI   (0 << 16)
#define STM32_PLLSRC_PREDIV1   (1 << 16)
#define STM32_OTGFSPRE_DIV2   (1 << 22)
#define STM32_OTGFSPRE_DIV3   (0 << 22)
#define STM32_MCO_NOCLOCK   (0 << 24)
#define STM32_MCO_SYSCLK   (4 << 24)
#define STM32_MCO_HSI   (5 << 24)
#define STM32_MCO_HSE   (6 << 24)
#define STM32_MCO_PLLDIV2   (7 << 24)
#define STM32_MCO_PLL2   (8 << 24)
#define STM32_MCO_PLL3DIV2   (9 << 24)
#define STM32_MCO_XT1   (10 << 24)
#define STM32_MCO_PLL3   (11 << 24)
#define STM32_PREDIV1SRC_HSE   (0 << 16)
#define STM32_PREDIV1SRC_PLL2   (1 << 16)
#define WWDG_IRQHandler   Vector40
#define PVD_IRQHandler   Vector44
#define TAMPER_IRQHandler   Vector48
#define RTC_IRQHandler   Vector4C
#define FLASH_IRQHandler   Vector50
#define RCC_IRQHandler   Vector54
#define EXTI0_IRQHandler   Vector58
#define EXTI1_IRQHandler   Vector5C
#define EXTI2_IRQHandler   Vector60
#define EXTI3_IRQHandler   Vector64
#define EXTI4_IRQHandler   Vector68
#define DMA1_Ch1_IRQHandler   Vector6C
#define DMA1_Ch2_IRQHandler   Vector70
#define DMA1_Ch3_IRQHandler   Vector74
#define DMA1_Ch4_IRQHandler   Vector78
#define DMA1_Ch5_IRQHandler   Vector7C
#define DMA1_Ch6_IRQHandler   Vector80
#define DMA1_Ch7_IRQHandler   Vector84
#define ADC1_2_IRQHandler   Vector88
#define CAN1_TX_IRQHandler   Vector8C
#define CAN1_RX0_IRQHandler   Vector90
#define CAN1_RX1_IRQHandler   Vector94
#define CAN1_SCE_IRQHandler   Vector98
#define EXTI9_5_IRQHandler   Vector9C
#define TIM1_BRK_IRQHandler   VectorA0
#define TIM1_UP_IRQHandler   VectorA4
#define TIM1_TRG_COM_IRQHandler   VectorA8
#define TIM1_CC_IRQHandler   VectorAC
#define TIM2_IRQHandler   VectorB0
#define TIM3_IRQHandler   VectorB4
#define TIM4_IRQHandler   VectorB8
#define I2C1_EV_IRQHandler   VectorBC
#define I2C1_ER_IRQHandler   VectorC0
#define I2C2_EV_IRQHandler   VectorC4
#define I2C2_ER_IRQHandler   VectorC8
#define SPI1_IRQHandler   VectorCC
#define SPI2_IRQHandler   VectorD0
#define USART1_IRQHandler   VectorD4
#define USART2_IRQHandler   VectorD8
#define USART3_IRQHandler   VectorDC
#define EXTI15_10_IRQHandler   VectorE0
#define RTCAlarm_IRQHandler   VectorE4
#define OTG_FS_WKUP_IRQHandler   VectorE8
#define TIM5_IRQHandler   Vector108
#define SPI3_IRQHandler   Vector10C
#define UART4_IRQHandler   Vector110
#define UART5_IRQHandler   Vector114
#define TIM6_IRQHandler   Vector118
#define TIM7_IRQHandler   Vector11C
#define DMA2_Ch1_IRQHandler   Vector120
#define DMA2_Ch2_IRQHandler   Vector124
#define DMA2_Ch3_IRQHandler   Vector128
#define DMA2_Ch4_IRQHandler   Vector12C
#define DMA2_Ch5_IRQHandler   Vector130
#define ETH_IRQHandler   Vector134
#define ETH_WKUP_IRQHandler   Vector138
#define CAN2_TX_IRQHandler   Vector13C
#define CAN2_RX0_IRQHandler   Vector140
#define CAN2_RX1_IRQHandler   Vector144
#define CAN2_SCE_IRQHandler   Vector148
#define OTG_FS_IRQHandler   Vector14C
#define STM32_SW   STM32_SW_PLL
 Main clock source selection.
#define STM32_PLLSRC   STM32_PLLSRC_PREDIV1
 Clock source for the PLL.
#define STM32_PREDIV1SRC   STM32_PREDIV1SRC_PLL2
 PREDIV1 clock source.
#define STM32_PREDIV1_VALUE   5
 PREDIV1 division factor.
#define STM32_PLLMUL_VALUE   9
 PLL multiplier value.
#define STM32_PREDIV2_VALUE   5
 PREDIV2 division factor.
#define STM32_PLL2MUL_VALUE   8
 PLL2 multiplier value.
#define STM32_HPRE   STM32_HPRE_DIV1
 AHB prescaler value.
#define STM32_PPRE1   STM32_PPRE1_DIV2
 APB1 prescaler value.
#define STM32_PPRE2   STM32_PPRE2_DIV2
 APB2 prescaler value.
#define STM32_ADCPRE   STM32_ADCPRE_DIV4
 ADC prescaler value.
#define STM32_MCO   STM32_MCO_NOCLOCK
 MCO pin setting.
#define STM32_PREDIV1   ((STM32_PREDIV1_VALUE - 1) << 0)
 PREDIV1 field.
#define STM32_PREDIV2   ((STM32_PREDIV2_VALUE - 1) << 4)
 PREDIV2 field.
#define STM32_PLLMUL   ((STM32_PLLMUL_VALUE - 2) << 18)
 PLLMUL field.
#define STM32_PLL2MUL   ((STM32_PLL2MUL_VALUE - 2) << 8)
 PLL2MUL field.
#define STM32_PLL2CLKIN   (STM32_HSECLK / STM32_PREDIV2_VALUE)
 PLL2 input frequency.
#define STM32_PLL2CLKOUT   (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)
 PLL2 output clock frequency.
#define STM32_PREDIV1CLK   STM32_PLL2CLKOUT
 PREDIV1 input frequency.
#define STM32_PLLCLKIN   (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
 PLL input clock frequency.
#define STM32_PLLCLKOUT   (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
 PLL output clock frequency.
#define STM32_SYSCLK   STM32_PLLCLKOUT
 System clock source.
#define STM32_HCLK   (STM32_SYSCLK / 1)
 AHB frequency.
#define STM32_PCLK1   (STM32_HCLK / 1)
 APB1 frequency.
#define STM32_PCLK2   (STM32_HCLK / 1)
 APB2 frequency.
#define STM32_ADCCLK   (STM32_PCLK2 / 2)
 ADC frequency.
#define STM32_TIMCLK1   (STM32_PCLK1 * 1)
 Timers 2, 3, 4, 5, 6, 7 clock.
#define STM32_TIMCLK2   (STM32_PCLK2 * 1)
 Timer 1 clock.
#define STM32_FLASHBITS   0x00000010
 Flash settings.
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#define STM32_HSICLK   8000000
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High speed internal clock.

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Definition at line 42 of file hal_lld_f105_f107.h.

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#define STM32_LSICLK   40000
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Low speed internal clock.

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Definition at line 43 of file hal_lld_f105_f107.h.

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#define STM32_SW_HSI   (0 << 0)
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SYSCLK source is HSI.

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Definition at line 46 of file hal_lld_f105_f107.h.

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#define STM32_SW_HSE   (1 << 0)
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SYSCLK source is HSE.

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Definition at line 47 of file hal_lld_f105_f107.h.

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#define STM32_SW_PLL   (2 << 0)
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SYSCLK source is PLL.

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Definition at line 48 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV1   (0 << 4)
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SYSCLK divided by 1.

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Definition at line 50 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV2   (8 << 4)
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Definition at line 51 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV4   (9 << 4)
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SYSCLK divided by 4.

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Definition at line 52 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV8   (10 << 4)
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Definition at line 53 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV16   (11 << 4)
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SYSCLK divided by 16.

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Definition at line 54 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV64   (12 << 4)
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Definition at line 55 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV128   (13 << 4)
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Definition at line 56 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV256   (14 << 4)
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Definition at line 57 of file hal_lld_f105_f107.h.

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#define STM32_HPRE_DIV512   (15 << 4)
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Definition at line 58 of file hal_lld_f105_f107.h.

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#define STM32_PPRE1_DIV1   (0 << 8)
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Definition at line 60 of file hal_lld_f105_f107.h.

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#define STM32_PPRE1_DIV2   (4 << 8)
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Definition at line 61 of file hal_lld_f105_f107.h.

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#define STM32_PPRE1_DIV4   (5 << 8)
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Definition at line 63 of file hal_lld_f105_f107.h.

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#define STM32_PPRE1_DIV16   (7 << 8)
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Definition at line 64 of file hal_lld_f105_f107.h.

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#define STM32_PPRE2_DIV1   (0 << 11)
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Definition at line 66 of file hal_lld_f105_f107.h.

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#define STM32_PPRE2_DIV2   (4 << 11)
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Definition at line 67 of file hal_lld_f105_f107.h.

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Definition at line 68 of file hal_lld_f105_f107.h.

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#define STM32_PPRE2_DIV8   (6 << 11)
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Definition at line 69 of file hal_lld_f105_f107.h.

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#define STM32_PPRE2_DIV16   (7 << 11)
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-
-

HCLK divided by 16.

- -

Definition at line 70 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_ADCPRE_DIV2   (0 << 14)
-
-
-

HCLK divided by 2.

- -

Definition at line 72 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_ADCPRE_DIV4   (1 << 14)
-
-
-

HCLK divided by 4.

- -

Definition at line 73 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_ADCPRE_DIV6   (2 << 14)
-
-
-

HCLK divided by 6.

- -

Definition at line 74 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_ADCPRE_DIV8   (3 << 14)
-
-
-

HCLK divided by 8.

- -

Definition at line 75 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLLSRC_HSI   (0 << 16)
-
-
-

PLL clock source is HSI.

- -

Definition at line 77 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLLSRC_PREDIV1   (1 << 16)
-
-
-

PLL clock source is PREDIV1.

- -

Definition at line 78 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_OTGFSPRE_DIV2   (1 << 22)
-
-
-

HCLK*2 divided by 2.

- -

Definition at line 81 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_OTGFSPRE_DIV3   (0 << 22)
-
-
-

HCLK*2 divided by 3.

- -

Definition at line 82 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_NOCLOCK   (0 << 24)
-
-
-

No clock on MCO pin.

- -

Definition at line 84 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_SYSCLK   (4 << 24)
-
-
-

SYSCLK on MCO pin.

- -

Definition at line 85 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_HSI   (5 << 24)
-
-
-

HSI clock on MCO pin.

- -

Definition at line 86 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_HSE   (6 << 24)
-
-
-

HSE clock on MCO pin.

- -

Definition at line 87 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_PLLDIV2   (7 << 24)
-
-
-

PLL/2 clock on MCO pin.

- -

Definition at line 88 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_PLL2   (8 << 24)
-
-
-

PLL2 clock on MCO pin.

- -

Definition at line 89 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_PLL3DIV2   (9 << 24)
-
-
-

PLL3/2 clock on MCO pin.

- -

Definition at line 90 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_XT1   (10 << 24)
-
-
-

XT1 clock on MCO pin.

- -

Definition at line 91 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO_PLL3   (11 << 24)
-
-
-

PLL3 clock on MCO pin.

- -

Definition at line 92 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PREDIV1SRC_HSE   (0 << 16)
-
-
-

PREDIV1 source is HSE.

- -

Definition at line 95 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PREDIV1SRC_PLL2   (1 << 16)
-
-
-

PREDIV1 source is PLL2.

- -

Definition at line 96 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define WWDG_IRQHandler   Vector40
-
-
-

Window Watchdog.

- -

Definition at line 102 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define PVD_IRQHandler   Vector44
-
-
-

PVD through EXTI Line detect.

- -

Definition at line 103 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TAMPER_IRQHandler   Vector48
-
-
-

Tamper.

- -

Definition at line 105 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define RTC_IRQHandler   Vector4C
-
-
-

RTC.

- -

Definition at line 106 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define FLASH_IRQHandler   Vector50
-
-
-

Flash.

- -

Definition at line 107 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define RCC_IRQHandler   Vector54
-
-
-

RCC.

- -

Definition at line 108 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define EXTI0_IRQHandler   Vector58
-
-
-

EXTI Line 0.

- -

Definition at line 109 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define EXTI1_IRQHandler   Vector5C
-
-
-

EXTI Line 1.

- -

Definition at line 110 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define EXTI2_IRQHandler   Vector60
-
-
-

EXTI Line 2.

- -

Definition at line 111 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define EXTI3_IRQHandler   Vector64
-
-
-

EXTI Line 3.

- -

Definition at line 112 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define EXTI4_IRQHandler   Vector68
-
-
-

EXTI Line 4.

- -

Definition at line 113 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA1_Ch1_IRQHandler   Vector6C
-
-
-

DMA1 Channel 1.

- -

Definition at line 114 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA1_Ch2_IRQHandler   Vector70
-
-
-

DMA1 Channel 2.

- -

Definition at line 115 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA1_Ch3_IRQHandler   Vector74
-
-
-

DMA1 Channel 3.

- -

Definition at line 116 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA1_Ch4_IRQHandler   Vector78
-
-
-

DMA1 Channel 4.

- -

Definition at line 117 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA1_Ch5_IRQHandler   Vector7C
-
-
-

DMA1 Channel 5.

- -

Definition at line 118 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA1_Ch6_IRQHandler   Vector80
-
-
-

DMA1 Channel 6.

- -

Definition at line 119 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA1_Ch7_IRQHandler   Vector84
-
-
-

DMA1 Channel 7.

- -

Definition at line 120 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define ADC1_2_IRQHandler   Vector88
-
-
-

ADC1 and ADC2.

- -

Definition at line 121 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define CAN1_TX_IRQHandler   Vector8C
-
-
-

CAN1 TX.

- -

Definition at line 122 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define CAN1_RX0_IRQHandler   Vector90
-
-
-

CAN1 RX0.

- -

Definition at line 123 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define CAN1_RX1_IRQHandler   Vector94
-
-
-

CAN1 RX1.

- -

Definition at line 124 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define CAN1_SCE_IRQHandler   Vector98
-
-
-

CAN1 SCE.

- -

Definition at line 125 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define EXTI9_5_IRQHandler   Vector9C
-
-
-

EXTI Line 9..5.

- -

Definition at line 126 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM1_BRK_IRQHandler   VectorA0
-
-
-

TIM1 Break.

- -

Definition at line 127 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM1_UP_IRQHandler   VectorA4
-
-
-

TIM1 Update.

- -

Definition at line 128 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM1_TRG_COM_IRQHandler   VectorA8
-
-
-

TIM1 Trigger and Commutation.

- -

Definition at line 129 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM1_CC_IRQHandler   VectorAC
-
-
-

TIM1 Capture Compare.

- -

Definition at line 131 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM2_IRQHandler   VectorB0
-
-
-

TIM2.

- -

Definition at line 132 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM3_IRQHandler   VectorB4
-
-
-

TIM3.

- -

Definition at line 133 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM4_IRQHandler   VectorB8
-
-
-

TIM4.

- -

Definition at line 134 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define I2C1_EV_IRQHandler   VectorBC
-
-
-

I2C1 Event.

- -

Definition at line 135 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define I2C1_ER_IRQHandler   VectorC0
-
-
-

I2C1 Error.

- -

Definition at line 136 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define I2C2_EV_IRQHandler   VectorC4
-
-
-

I2C2 Event.

- -

Definition at line 137 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define I2C2_ER_IRQHandler   VectorC8
-
-
-

I2C1 Error.

- -

Definition at line 138 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define SPI1_IRQHandler   VectorCC
-
-
-

SPI1.

- -

Definition at line 139 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define SPI2_IRQHandler   VectorD0
-
-
-

SPI2.

- -

Definition at line 140 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define USART1_IRQHandler   VectorD4
-
-
-

USART1.

- -

Definition at line 141 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define USART2_IRQHandler   VectorD8
-
-
-

USART2.

- -

Definition at line 142 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define USART3_IRQHandler   VectorDC
-
-
-

USART3.

- -

Definition at line 143 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define EXTI15_10_IRQHandler   VectorE0
-
-
-

EXTI Line 15..10.

- -

Definition at line 144 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define RTCAlarm_IRQHandler   VectorE4
-
-
-

RTC alarm through EXTI line.

- -

Definition at line 145 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define OTG_FS_WKUP_IRQHandler   VectorE8
-
-
-

USB OTG FS Wakeup through EXTI line.

- -

Definition at line 147 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM5_IRQHandler   Vector108
-
-
-

TIM5.

- -

Definition at line 149 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define SPI3_IRQHandler   Vector10C
-
-
-

SPI3.

- -

Definition at line 150 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define UART4_IRQHandler   Vector110
-
-
-

UART4.

- -

Definition at line 151 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define UART5_IRQHandler   Vector114
-
-
-

UART5.

- -

Definition at line 152 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM6_IRQHandler   Vector118
-
-
-

TIM6.

- -

Definition at line 153 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define TIM7_IRQHandler   Vector11C
-
-
-

TIM7.

- -

Definition at line 154 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA2_Ch1_IRQHandler   Vector120
-
-
-

DMA2 Channel1.

- -

Definition at line 155 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA2_Ch2_IRQHandler   Vector124
-
-
-

DMA2 Channel2.

- -

Definition at line 156 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA2_Ch3_IRQHandler   Vector128
-
-
-

DMA2 Channel3.

- -

Definition at line 157 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA2_Ch4_IRQHandler   Vector12C
-
-
-

DMA2 Channel4.

- -

Definition at line 158 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define DMA2_Ch5_IRQHandler   Vector130
-
-
-

DMA2 Channel5.

- -

Definition at line 159 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define ETH_IRQHandler   Vector134
-
-
-

Ethernet.

- -

Definition at line 160 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define ETH_WKUP_IRQHandler   Vector138
-
-
-

Ethernet Wakeup through EXTI line.

- -

Definition at line 161 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define CAN2_TX_IRQHandler   Vector13C
-
-
-

CAN2 TX.

- -

Definition at line 163 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define CAN2_RX0_IRQHandler   Vector140
-
-
-

CAN2 RX0.

- -

Definition at line 164 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define CAN2_RX1_IRQHandler   Vector144
-
-
-

CAN2 RX1.

- -

Definition at line 165 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define CAN2_SCE_IRQHandler   Vector148
-
-
-

CAN2 SCE.

- -

Definition at line 166 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define OTG_FS_IRQHandler   Vector14C
-
-
-

USB OTG FS.

- -

Definition at line 167 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_SW   STM32_SW_PLL
-
-
- -

Main clock source selection.

-
Note:
If the selected clock source is not the PLL then the PLL is not initialized and started.
-
-The default value is calculated for a 72MHz system clock from a 25MHz crystal using both PLL and PLL2.
- -

Definition at line 181 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLLSRC   STM32_PLLSRC_PREDIV1
-
-
- -

Clock source for the PLL.

-
Note:
This setting has only effect if the PLL is selected as the system clock source.
-
-The default value is calculated for a 72MHz system clock from a 25MHz crystal using both PLL and PLL2.
- -

Definition at line 192 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PREDIV1SRC   STM32_PREDIV1SRC_PLL2
-
-
- -

PREDIV1 clock source.

-
Note:
This setting has only effect if the PLL is selected as the system clock source.
-
-The default value is calculated for a 72MHz system clock from a 25MHz crystal using both PLL and PLL2.
- -

Definition at line 203 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PREDIV1_VALUE   5
-
-
- -

PREDIV1 division factor.

-
Note:
This setting has only effect if the PLL is selected as the system clock source.
-
-The allowed range is 1...16.
-
-The default value is calculated for a 72MHz system clock from a 25MHz crystal using both PLL and PLL2.
- -

Definition at line 215 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLLMUL_VALUE   9
-
-
- -

PLL multiplier value.

-
Note:
The allowed range is 4...9.
-
-The default value is calculated for a 72MHz system clock from a 25MHz crystal using both PLL and PLL2.
- -

Definition at line 225 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PREDIV2_VALUE   5
-
-
- -

PREDIV2 division factor.

-
Note:
This setting has only effect if the PLL2 is selected as the clock source for the PLL.
-
-The allowed range is 1...16.
-
-The default value is calculated for a 72MHz system clock from a 25MHz crystal using both PLL and PLL2.
- -

Definition at line 237 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLL2MUL_VALUE   8
-
-
- -

PLL2 multiplier value.

-
Note:
The default value is calculated for a 72MHz system clock from a 25MHz crystal using both PLL and PLL2.
- -

Definition at line 246 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_HPRE   STM32_HPRE_DIV1
-
-
- -

AHB prescaler value.

-
Note:
The default value is calculated for a 72MHz system clock from a 25MHz crystal using both PLL and PLL2.
- -

Definition at line 255 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PPRE1   STM32_PPRE1_DIV2
-
-
- -

APB1 prescaler value.

- -

Definition at line 262 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PPRE2   STM32_PPRE2_DIV2
-
-
- -

APB2 prescaler value.

- -

Definition at line 269 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_ADCPRE   STM32_ADCPRE_DIV4
-
-
- -

ADC prescaler value.

- -

Definition at line 276 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_MCO   STM32_MCO_NOCLOCK
-
-
- -

MCO pin setting.

- -

Definition at line 283 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PREDIV1   ((STM32_PREDIV1_VALUE - 1) << 0)
-
-
- -

PREDIV1 field.

- -

Definition at line 295 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PREDIV2   ((STM32_PREDIV2_VALUE - 1) << 4)
-
-
- -

PREDIV2 field.

- -

Definition at line 305 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLLMUL   ((STM32_PLLMUL_VALUE - 2) << 18)
-
-
- -

PLLMUL field.

- -

Definition at line 315 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLL2MUL   ((STM32_PLL2MUL_VALUE - 2) << 8)
-
-
- -

PLL2MUL field.

- -

Definition at line 325 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLL2CLKIN   (STM32_HSECLK / STM32_PREDIV2_VALUE)
-
-
- -

PLL2 input frequency.

- -

Definition at line 340 of file hal_lld_f105_f107.h.

- -
-
- -
-
- - - - -
#define STM32_PLL2CLKOUT   (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)
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PLL2 output clock frequency.

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Definition at line 350 of file hal_lld_f105_f107.h.

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#define STM32_PREDIV1CLK   STM32_PLL2CLKOUT
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PREDIV1 input frequency.

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Definition at line 362 of file hal_lld_f105_f107.h.

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#define STM32_PLLCLKIN   (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
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PLL input clock frequency.

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Definition at line 373 of file hal_lld_f105_f107.h.

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#define STM32_PLLCLKOUT   (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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PLL output clock frequency.

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Definition at line 388 of file hal_lld_f105_f107.h.

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#define STM32_SYSCLK   STM32_PLLCLKOUT
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System clock source.

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Definition at line 399 of file hal_lld_f105_f107.h.

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#define STM32_HCLK   (STM32_SYSCLK / 1)
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AHB frequency.

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Definition at line 417 of file hal_lld_f105_f107.h.

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APB1 frequency.

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Definition at line 447 of file hal_lld_f105_f107.h.

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#define STM32_PCLK2   (STM32_HCLK / 1)
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APB2 frequency.

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Definition at line 469 of file hal_lld_f105_f107.h.

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#define STM32_ADCCLK   (STM32_PCLK2 / 2)
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ADC frequency.

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Definition at line 491 of file hal_lld_f105_f107.h.

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#define STM32_TIMCLK1   (STM32_PCLK1 * 1)
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Timers 2, 3, 4, 5, 6, 7 clock.

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Definition at line 511 of file hal_lld_f105_f107.h.

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#define STM32_TIMCLK2   (STM32_PCLK2 * 1)
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Timer 1 clock.

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Definition at line 520 of file hal_lld_f105_f107.h.

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#define STM32_FLASHBITS   0x00000010
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Flash settings.

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Definition at line 529 of file hal_lld_f105_f107.h.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Modules
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STM8
- -[Ports] -

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-Collaboration diagram for STM8:
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Description

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STM8 port details. This section how the ChibiOS/RT features are implemented on this architecture.

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-Mapping of the System States in the STM8 port

-

The ChibiOS/RT logical System States are mapped as follow in the STM8 port:

-
    -
  • Init. This state is represented by the startup code and the initialization code before chSysInit() is executed. It has not a special hardware state associated.
    • -
  • Normal. This is the state the system has after executing chSysInit(). Interrupts are enabled.
    • -
  • Suspended. Interrupts are disabled.
    • -
  • Disabled. Interrupts are disabled. This state is equivalent to the Suspended state because there are no fast interrupts in this architecture.
    • -
  • Sleep. Implemented with "wait" instruction insertion in the idle loop.
    • -
  • S-Locked. Interrupts are disabled.
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  • I-Locked. This state is equivalent to the SRI state, the chSysLockI() and chSysUnlockI() APIs do nothing (still use them in order to formally change state because this may change).
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  • Serving Regular Interrupt. Normal interrupt service code.
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  • Serving Fast Interrupt. Not present in this architecture.
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  • Serving Non-Maskable Interrupt. The STM8 ha non maskable interrupt sources that can be associated to this state.
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  • Halted. Implemented as an infinite loop with interrupts disabled.
    • -
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-The STM8 port notes

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    -
  • The STM8 does not have a dedicated interrupt stack, make sure to reserve enough stack space for interrupts in each thread stack. This can be done by modifying the INT_REQUIRED_STACK macro into ./os/ports/RC/STM8/chcore.h.
    • -
  • The kernel currently supports only the small memory model so the kernel files should be loaded in the first 64K. Note that this is not a problem because upper addresses can be used by the user code, the kernel can context switch code running there.
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  • The configuration option CH_OPTIMIZE_SPEED is not currently supported because the missing support of the inline "C" keyword in the compiler.
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-Modules

 Configuration Options
 

STM8 Configuration Options.

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 Core Port Implementation
 

STM8 specific port code, structures and macros.

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 STM8 Drivers
 

Device drivers included in the STM8 support.

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-Generated on Sun Nov 28 2010 14:09:57 for ChibiOS/RT by doxygen 1.7.1
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Configuration Options
- -[STM8] -

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STM8 Configuration Options. -More...

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-Collaboration diagram for Configuration Options:
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STM8 Configuration Options.

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The STM8 port allows some architecture-specific configurations settings that can be specified externally, as example on the compiler command line:

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    -
  • INT_REQUIRED_STACK, this value represent the amount of stack space used by the interrupt handlers.
    - The default for this value is 32, this space is allocated for each thread so be careful in order to not waste precious RAM space.
    - The default value is set into ./os/ports/RC/STM8/chcore.h.
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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Core Port Implementation
- -[STM8] -

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STM8 specific port code, structures and macros. -More...

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-Collaboration diagram for Core Port Implementation:
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Description

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STM8 specific port code, structures and macros.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-Data Structures

struct  stm8_startctx
 Start context. More...
struct  ReadyList
 Ready list header. More...

-Defines

#define STM8_ENABLE_WFI_IDLE   FALSE
 Enables the use of the WFI instruction in the idle thread loop.
#define CH_ARCHITECTURE_STM8
 Unique macro for the implemented architecture.
#define CH_ARCHITECTURE_NAME   "STM8"
 Name of the implemented architecture.
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   0
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   32
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void irq##id(void) interrupt id
 IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   _sim_()
 Kernel-lock action.
#define port_unlock()   _rim_()
 Kernel-unlock action.
#define port_lock_from_isr()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   _sim_()
 Disables all the interrupt sources.
#define port_suspend()   _sim_()
 Disables the interrupt sources that are not supposed to preempt the kernel.
#define port_enable()   _rim_()
 Enables all the interrupt sources.
#define port_wait_for_interrupt()   _wfi_()
 Enters an architecture-dependent halt mode.
#define port_switch(ntp, otp)   _port_switch(otp)
 Performs a context switch between two threads.
#define INLINE   inline
 Inline function modifier.
#define ROMCONST   code
 ROM constant modifier.
#define PACK_STRUCT_STRUCT
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef uint8_t stkalign_t
 Base type for stack alignment.
typedef void(* stm8func_t )(void)
 Generic STM8 function pointer.
typedef unsigned char uint8_t
typedef signed char int8_t
typedef unsigned int uint16_t
typedef signed int int16_t
typedef unsigned long uint32_t
typedef signed long int32_t
typedef uint8_t uint_fast8_t
typedef uint16_t uint_fast16_t
typedef uint32_t uint_fast32_t
typedef int8_t bool_t
 Boolean, recommended the fastest signed.
typedef uint8_t tmode_t
 Thread mode flags, uint8_t is ok.
typedef uint8_t tstate_t
 Thread state, uint8_t is ok.
typedef uint8_t trefs_t
 Thread references counter, uint8_t is ok.
typedef uint8_t tprio_t
 Priority, use the fastest unsigned type.
typedef int16_t msg_t
 Message, use signed pointer equivalent.
typedef int8_t eventid_t
 Event Id, use fastest signed.
typedef uint8_t eventmask_t
 Event Mask, recommended fastest unsigned.
typedef uint16_t systime_t
 System Time, recommended fastest unsigned.
typedef int16_t cnt_t
 Counter, recommended fastest signed.

-Functions

void _port_switch (Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Thread start code.
void port_halt (void)
 Halts the system.

-Variables

page0 ReadyList rlist
 Ready list header.
page0 ReadyList rlist
 Ready list header.
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Define Documentation

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#define STM8_ENABLE_WFI_IDLE   FALSE
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Enables the use of the WFI instruction in the idle thread loop.

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Definition at line 48 of file ports/RC/STM8/chcore.h.

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#define CH_ARCHITECTURE_STM8
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Unique macro for the implemented architecture.

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Definition at line 58 of file ports/RC/STM8/chcore.h.

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#define CH_ARCHITECTURE_NAME   "STM8"
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Name of the implemented architecture.

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Definition at line 63 of file ports/RC/STM8/chcore.h.

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#define SETUP_CONTEXT( workspace,
 wsize,
 pf,
 arg 
)
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-Value:
{                          \
-  struct stm8_startctx *scp;                                                \
-  scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize -             \
-                                 sizeof(struct stm8_startctx));             \
-  scp->ts   = _port_thread_start;                                           \
-  scp->arg  = arg;                                                          \
-  scp->pc   = (stm8func_t)pf;                                               \
-  scp->ret  = (stm8func_t)chThdExit;                                        \
-  tp->p_ctx.sp = (struct intctx *)scp;                                      \
-}
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Platform dependent part of the chThdInit() API.

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This code usually setup the context switching frame represented by an intctx structure.

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Definition at line 147 of file ports/RC/STM8/chcore.h.

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#define IDLE_THREAD_STACK_SIZE   0
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Stack size for the system idle thread.

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This size depends on the idle thread implementation, usually the idle thread should take no more space than those reserved by INT_REQUIRED_STACK.

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Definition at line 165 of file ports/RC/STM8/chcore.h.

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#define INT_REQUIRED_STACK   32
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Per-thread stack overhead for interrupts servicing.

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This constant is used in the calculation of the correct working area size. This value can be zero on those architecture where there is a separate interrupt stack and the stack space between intctx and extctx is known to be zero.

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Definition at line 177 of file ports/RC/STM8/chcore.h.

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#define STACK_ALIGN( n )    ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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Enforces a correct alignment for a stack area size value.

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Definition at line 183 of file ports/RC/STM8/chcore.h.

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#define THD_WA_SIZE( n ) 
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Computes the thread working area global size.

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Definition at line 188 of file ports/RC/STM8/chcore.h.

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#define WORKING_AREA( s,
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Static working area allocation.

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This macro is used to allocate a static thread working area aligned as both position and size.

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Definition at line 198 of file ports/RC/STM8/chcore.h.

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#define PORT_IRQ_PROLOGUE( ) 
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IRQ prologue code.

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This macro must be inserted at the start of all IRQ handlers enabled to invoke system APIs.

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Definition at line 205 of file ports/RC/STM8/chcore.h.

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#define PORT_IRQ_EPILOGUE( ) 
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{                                               \
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-    chSchDoRescheduleI();                                                   \
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IRQ epilogue code.

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This macro must be inserted at the end of all IRQ handlers enabled to invoke system APIs.

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Definition at line 212 of file ports/RC/STM8/chcore.h.

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#define PORT_IRQ_HANDLER( id )    void irq##id(void) interrupt id
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IRQ handler function declaration.

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Definition at line 222 of file ports/RC/STM8/chcore.h.

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#define port_init( void ) 
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Port-related initialization code.

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Definition at line 228 of file ports/RC/STM8/chcore.h.

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#define port_lock( void )    _sim_()
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Kernel-lock action.

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Definition at line 234 of file ports/RC/STM8/chcore.h.

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#define port_unlock( void )    _rim_()
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Kernel-unlock action.

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Definition at line 240 of file ports/RC/STM8/chcore.h.

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#define port_lock_from_isr( void ) 
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Kernel-lock action from an interrupt handler.

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Definition at line 246 of file ports/RC/STM8/chcore.h.

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#define port_unlock_from_isr( void ) 
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Kernel-unlock action from an interrupt handler.

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Definition at line 252 of file ports/RC/STM8/chcore.h.

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#define port_disable( void )    _sim_()
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Disables all the interrupt sources.

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Definition at line 259 of file ports/RC/STM8/chcore.h.

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#define port_suspend( void )    _sim_()
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Disables the interrupt sources that are not supposed to preempt the kernel.

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Definition at line 267 of file ports/RC/STM8/chcore.h.

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#define port_enable( void )    _rim_()
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Enables all the interrupt sources.

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Definition at line 273 of file ports/RC/STM8/chcore.h.

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#define port_wait_for_interrupt( void )    _wfi_()
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Enters an architecture-dependent halt mode.

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Definition at line 280 of file ports/RC/STM8/chcore.h.

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#define port_switch( ntp,
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Performs a context switch between two threads.

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This is the most critical code in any port, this function is responsible for the context switch between 2 threads.

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Note:
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ntp the thread to be switched in
otp the thread to be switched out
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Definition at line 294 of file ports/RC/STM8/chcore.h.

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#define INLINE   inline
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Inline function modifier.

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Definition at line 109 of file ports/RC/STM8/chtypes.h.

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#define ROMCONST   code
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ROM constant modifier.

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Definition at line 115 of file ports/RC/STM8/chtypes.h.

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#define PACK_STRUCT_STRUCT
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Packed structure modifier (within).

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Empty in this port.
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Definition at line 121 of file ports/RC/STM8/chtypes.h.

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#define PACK_STRUCT_BEGIN
-
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Packed structure modifier (before).

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Note:
Empty in this port.
- -

Definition at line 127 of file ports/RC/STM8/chtypes.h.

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#define PACK_STRUCT_END
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Packed structure modifier (after).

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Note:
Empty in this port.
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Definition at line 133 of file ports/RC/STM8/chtypes.h.

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Typedef Documentation

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typedef uint8_t stkalign_t
-
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Base type for stack alignment.

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Note:
No alignment constraints so uint8_t.
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Definition at line 73 of file ports/RC/STM8/chcore.h.

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typedef void(* stm8func_t)(void)
-
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Generic STM8 function pointer.

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Note:
It is used to allocate the proper size for return addresses in context-related structures.
- -

Definition at line 80 of file ports/RC/STM8/chcore.h.

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typedef unsigned char uint8_t
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C99-style 8 bits unsigned.

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Definition at line 46 of file ports/RC/STM8/chtypes.h.

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typedef signed char int8_t
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C99-style 8 bits signed.

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Definition at line 47 of file ports/RC/STM8/chtypes.h.

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typedef unsigned int uint16_t
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM8 Drivers
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Device drivers included in the STM8 support. -More...

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Description

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Device drivers included in the STM8 support.

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-Modules

 STM8 HAL Support
 

HAL support.

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 STM8 I/O Ports Support
 

I/O Ports peripherals support.

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 STM8 UART Support
 

USART support.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM8 HAL Support
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HAL support. -More...

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Description

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HAL support.

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-Defines

#define PLATFORM_NAME   "STM8x"
 Platform name.
#define LSICLK   128000
#define HSICLK   16000000
#define CLK_SOURCE_DEFAULT   0
#define CLK_SOURCE_HSI   0xE1
#define CLK_SOURCE_LSI   0xD2
#define CLK_SOURCE_HSE   0xB4
#define CLK_HSI_DIV1   0
#define CLK_HSI_DIV2   1
#define CLK_HSI_DIV4   2
#define CLK_HSI_DIV8   3
#define CLK_CPU_DIV1   0
#define CLK_CPU_DIV2   1
#define CLK_CPU_DIV4   2
#define CLK_CPU_DIV8   3
#define CLK_CPU_DIV16   4
#define CLK_CPU_DIV32   5
#define CLK_CPU_DIV64   6
#define CLK_CPU_DIV128   7
#define STM8_CLOCK_SOURCE   CLK_SOURCE_DEFAULT
 Clock source setting.
#define STM8_HSI_DIVIDER   CLK_HSI_DIV8
 HSI clock divider.
#define STM8_CPU_DIVIDER   CLK_CPU_DIV1
 CPU clock divider.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.

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ROMCONST PALConfig pal_default_config
 PAL setup.
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#define PLATFORM_NAME   "STM8x"
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Definition at line 47 of file platforms/STM8/hal_lld.h.

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ROMCONST PALConfig pal_default_config
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-    {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
-    {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
-    {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
-    {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
-    {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
-    {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
-    {VAL_GPIOHODR, 0, VAL_GPIOHDDR, VAL_GPIOHCR1, VAL_GPIOHCR2},
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STM8 I/O Ports Support
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I/O Ports peripherals support.

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This module supports the STM8 GPIO controller. The controller supports the following features (see PAL Driver):

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-Data Structures

struct  gpio_t
 GPIO port representation. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_MODE_OUTPUT_PUSHPULL_SLOW   16
 STM8 specific alternate push-pull slow output mode.
#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW   17
 STM8 specific alternate open-drain slow output mode.
#define PAL_IOPORTS_WIDTH   8
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFF)
 Whole port mask.
#define IOPORTS   ((PALConfig *)0x5000)
 GPIO ports as a whole.
#define IOPORT1   ((gpio_t *)0x5000)
 GPIO port A identifier.
#define IOPORT2   ((gpio_t *)0x5005)
 GPIO port B identifier.
#define IOPORT3   ((gpio_t *)0x500A)
 GPIO port C identifier.
#define IOPORT4   ((gpio_t *)0x500F)
 GPIO port D identifier.
#define IOPORT5   ((gpio_t *)0x5014)
 GPIO port E identifier.
#define IOPORT6   ((gpio_t *)0x5019)
 GPIO port F identifier.
#define IOPORT7   ((gpio_t *)0x501E)
 GPIO port G identifier.
#define IOPORT8   ((gpio_t *)0x5023)
 GPIO port H identifier.
#define IOPORT9   ((gpio_t *)0x5028)
 GPIO port I identifier.
#define pal_lld_init(config)   *IOPORTS = *(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->IDR)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->ODR)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->ODR = (bits))
 Writes a bits mask on a I/O port.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.

-Typedefs

typedef uint8_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef gpio_t * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

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ROMCONST PALConfig pal_default_config
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Whole port mask.

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GPIO port C identifier.

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Definition at line 127 of file platforms/STM8/pal_lld.h.

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GPIO port D identifier.

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#define IOPORT6   ((gpio_t *)0x5019)
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GPIO port F identifier.

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GPIO port G identifier.

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GPIO port H identifier.

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GPIO port I identifier.

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Definition at line 163 of file platforms/STM8/pal_lld.h.

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Low level PAL subsystem initialization.

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Reads the physical I/O port states.

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Definition at line 186 of file platforms/STM8/pal_lld.h.

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Reads the output latch.

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[in] port port identifier
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Definition at line 208 of file platforms/STM8/pal_lld.h.

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Pads group mode setup.

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[in] mode group mode
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Definition at line 223 of file platforms/STM8/pal_lld.h.

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typedef uint8_t ioportmask_t
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Port Identifier.

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void _pal_lld_setgroupmode (ioportid_t  port,
ioportmask_t  mask,
uint_fast8_t  mode 
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Pads mode setup.

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This function programs a pads group belonging to the same port with the specified mode.

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ROMCONST PALConfig pal_default_config
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PAL setup.

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Digital I/O ports static configuration as defined in board.h.

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Definition at line 49 of file platforms/AT91SAM7/hal_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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STM8 UART Support
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USART support. -More...

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Description

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USART support.

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The serial driver supports the STM8 USARTs in asynchronous mode.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define SD_MODE_PARITY   0x07
 Parity field mask.
#define SD_MODE_PARITY_NONE   0x00
 No parity.
#define SD_MODE_PARITY_EVEN   0x05
 Even parity.
#define SD_MODE_PARITY_ODD   0x07
 Odd parity.
#define SD_MODE_STOP   0x30
 Stop bits mask.
#define SD_MODE_STOP_1   0x00
 One stop bit.
#define SD_MODE_STOP_2   0x20
 Two stop bits.
#define SD_MODE_STOP_1P5   0x30
 1.5 stop bits.
#define USE_STM8_UART1   TRUE
 UART1 driver enable switch.
#define USE_STM8_UART3   TRUE
 UART3 driver enable switch.
#define _serial_driver_data
 SerialDriver specific data.
#define BBR(b)   (SYSCLK / (b))
 Macro for baud rate computation.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 UART1 serial driver identifier.
SerialDriver SD3
 UART3 serial driver identifier.
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#define SD_MODE_PARITY   0x07
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Parity field mask.

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No parity.

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Even parity.

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Odd parity.

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Definition at line 47 of file platforms/STM8/serial_lld.h.

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Stop bits mask.

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Definition at line 49 of file platforms/STM8/serial_lld.h.

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One stop bit.

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Definition at line 50 of file platforms/STM8/serial_lld.h.

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Two stop bits.

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Definition at line 51 of file platforms/STM8/serial_lld.h.

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1.5 stop bits.

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Definition at line 52 of file platforms/STM8/serial_lld.h.

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#define USE_STM8_UART1   TRUE
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UART1 driver enable switch.

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Definition at line 64 of file platforms/STM8/serial_lld.h.

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#define USE_STM8_UART3   TRUE
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UART3 driver enable switch.

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The default is TRUE.
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Definition at line 73 of file platforms/STM8/serial_lld.h.

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#define _serial_driver_data
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_base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Status Change @p EventSource.*/                                        \
-  EventSource               sevent;                                         \
-  /* I/O driver status flags.*/                                             \
-  sdflags_t                 flags;                                          \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
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SerialDriver specific data.

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Definition at line 111 of file platforms/STM8/serial_lld.h.

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#define BBR( b )    (SYSCLK / (b))
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Macro for baud rate computation.

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Definition at line 137 of file platforms/STM8/serial_lld.h.

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Typedef Documentation

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typedef uint8_t sdflags_t
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Serial Driver condition flags type.

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Definition at line 87 of file platforms/STM8/serial_lld.h.

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Function Documentation

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void sd_lld_init (void  ) 
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Low level serial driver initialization.

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void sd_lld_start (SerialDriver *  sdp,
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Low level serial driver configuration and (re)start.

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[in] sdp pointer to a SerialDriver object
[in] config the architecture-dependent serial driver configuration. If this parameter is set to NULL then a default configuration is used.
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void sd_lld_stop (SerialDriver *  sdp ) 
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Low level serial driver stop.

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De-initializes the USART, stops the associated clock, resets the interrupt vector.

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[in] sdp pointer to a SerialDriver object
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Variable Documentation

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SerialDriver SD1
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UART1 serial driver identifier.

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Definition at line 72 of file platforms/STM8/serial_lld.c.

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UART3 serial driver identifier.

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Definition at line 79 of file platforms/STM8/serial_lld.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Base Kernel Services
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Base kernel services, the base subsystems are always included in the OS builds.

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 System Management
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 Time and Virtual Timers
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Condition Variables
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Description

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This module implements the Condition Variables mechanism. Condition variables are an extensions to the Mutex subsystem and cannot work alone.

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Operation mode

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The condition variable is a synchronization object meant to be used inside a zone protected by a Mutex. Mutexes and CondVars together can implement a Monitor construct.
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struct  CondVar
 CondVar structure. More...

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#define _CONDVAR_DATA(name)   {_THREADSQUEUE_DATA(name.c_queue)}
 Data part of a static condition variable initializer.
#define CONDVAR_DECL(name)   CondVar name = _CONDVAR_DATA(name)
 Static condition variable initializer.

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typedef struct CondVar CondVar
 CondVar structure.

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void chCondInit (CondVar *cp)
 Initializes s CondVar structure.
void chCondSignal (CondVar *cp)
 Signals one thread that is waiting on the condition variable.
void chCondSignalI (CondVar *cp)
 Signals one thread that is waiting on the condition variable.
void chCondBroadcast (CondVar *cp)
 Signals all threads that are waiting on the condition variable.
void chCondBroadcastI (CondVar *cp)
 Signals all threads that are waiting on the condition variable.
msg_t chCondWait (CondVar *cp)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitS (CondVar *cp)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitTimeout (CondVar *cp, systime_t time)
 Waits on the condition variable releasing the mutex lock.
msg_t chCondWaitTimeoutS (CondVar *cp, systime_t time)
 Waits on the condition variable releasing the mutex lock.
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Define Documentation

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#define _CONDVAR_DATA( name )    {_THREADSQUEUE_DATA(name.c_queue)}
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Data part of a static condition variable initializer.

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Static condition variable initializer.

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Statically initialized condition variables require no explicit initialization using chCondInit().

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CondVar structure.

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Initializes s CondVar structure.

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References CondVar::c_queue, chDbgCheck, and queue_init.

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Definition at line 86 of file chcond.c.

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Definition at line 99 of file chcond.c.

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Referenced by chibios_rt::CondVar::Broadcast().

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Signals all threads that are waiting on the condition variable.

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Definition at line 112 of file chcond.c.

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Waits on the condition variable releasing the mutex lock.

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Releases the currently owned mutex, waits on the condition variable, and finally acquires the mutex again. All the sequence is performed atomically.

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The wakep mode.
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RDY_OK if the condvar was signaled using chCondSignal().
RDY_RESET if the condvar was signaled using chCondBroadcast().
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Definition at line 136 of file chcond.c.

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References chCondWaitS(), chSysLock, and chSysUnlock.

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Releases the currently owned mutex, waits on the condition variable, and finally acquires the mutex again. All the sequence is performed atomically.

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The wakep mode.
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RDY_OK if the condvar was signaled using chCondSignal().
RDY_RESET if the condvar was signaled using chCondBroadcast().
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Definition at line 158 of file chcond.c.

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References CondVar::c_queue, chDbgAssert, chDbgCheck, chMtxLockS(), chMtxUnlockS(), chSchGoSleepS(), Thread::p_mtxlist, Thread::p_u, prio_insert(), Thread::rdymsg, THD_STATE_WTCOND, and Thread::wtobjp.

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Releases the currently owned mutex, waits on the condition variable, and finally acquires the mutex again. All the sequence is performed atomically.

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[in] time the number of ticks before the operation timeouts, the special value TIME_INFINITE is allowed. It is not possible to specify zero TIME_IMMEDIATE as timeout specification because it would make no sense in this function.
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The wakep mode.
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RDY_OK if the condvar was signaled using chCondSignal().
RDY_RESET if the condvar was signaled using chCondBroadcast().
RDY_TIMEOUT if the condvar was not signaled within the specified timeout.
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Definition at line 200 of file chcond.c.

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References chCondWaitTimeoutS(), chSysLock, and chSysUnlock.

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Referenced by chibios_rt::CondVar::WaitTimeout().

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msg_t chCondWaitTimeoutS (CondVar *  cp,
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Waits on the condition variable releasing the mutex lock.

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Releases the currently owned mutex, waits on the condition variable, and finally acquires the mutex again. All the sequence is performed atomically.

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[in] time the number of ticks before the operation timeouts, the special value TIME_INFINITE is allowed. It is not possible to specify zero TIME_IMMEDIATE as timeout specification because it would make no sense in this function.
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The wakep mode.
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RDY_OK if the condvar was signaled using chCondSignal().
RDY_RESET if the condvar was signaled using chCondBroadcast().
RDY_TIMEOUT if the condvar was not signaled within the specified timeout.
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Definition at line 231 of file chcond.c.

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References CondVar::c_queue, chDbgAssert, chDbgCheck, chMtxLockS(), chMtxUnlockS(), chSchGoSleepTimeoutS(), currp, prio_insert(), RDY_TIMEOUT, and THD_STATE_WTCOND.

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Referenced by chCondWaitTimeout().

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines
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Configuration
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Description

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Kernel related settings and hooks.

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-Defines

#define CH_FREQUENCY   1000
 System tick frequency.
#define CH_TIME_QUANTUM   20
 Round robin interval.
#define CH_USE_NESTED_LOCKS   FALSE
 Nested locks.
#define CH_MEMCORE_SIZE   0
 Managed RAM size.
#define CH_OPTIMIZE_SPEED   TRUE
 OS optimization.
#define CH_CURRP_REGISTER_CACHE   "reg"
 Exotic optimization.
#define CH_USE_REGISTRY   TRUE
 Threads registry APIs.
#define CH_USE_WAITEXIT   TRUE
 Threads synchronization APIs.
#define CH_USE_SEMAPHORES   TRUE
 Semaphores APIs.
#define CH_USE_SEMAPHORES_PRIORITY   FALSE
 Semaphores queuing mode.
#define CH_USE_SEMSW   TRUE
 Atomic semaphore API.
#define CH_USE_MUTEXES   TRUE
 Mutexes APIs.
#define CH_USE_CONDVARS   TRUE
 Conditional Variables APIs.
#define CH_USE_CONDVARS_TIMEOUT   TRUE
 Conditional Variables APIs with timeout.
#define CH_USE_EVENTS   TRUE
 Events Flags APIs.
#define CH_USE_EVENTS_TIMEOUT   TRUE
 Events Flags APIs with timeout.
#define CH_USE_MESSAGES   TRUE
 Synchronous Messages APIs.
#define CH_USE_MESSAGES_PRIORITY   FALSE
 Synchronous Messages queuing mode.
#define CH_USE_MAILBOXES   TRUE
 Mailboxes APIs.
#define CH_USE_QUEUES   TRUE
 I/O Queues APIs.
#define CH_USE_MEMCORE   TRUE
 Core Memory Manager APIs.
#define CH_USE_HEAP   TRUE
 Heap Allocator APIs.
#define CH_USE_MALLOC_HEAP   FALSE
 C-runtime allocator.
#define CH_USE_MEMPOOLS   TRUE
 Memory Pools Allocator APIs.
#define CH_USE_DYNAMIC   TRUE
 Dynamic Threads APIs.
#define CH_DBG_ENABLE_CHECKS   FALSE
 Debug option, parameters checks.
#define CH_DBG_ENABLE_ASSERTS   FALSE
 Debug option, consistency checks.
#define CH_DBG_ENABLE_TRACE   FALSE
 Debug option, trace buffer.
#define CH_DBG_ENABLE_STACK_CHECK   FALSE
 Debug option, stack checks.
#define CH_DBG_FILL_THREADS   FALSE
 Debug option, stacks initialization.
#define CH_DBG_THREADS_PROFILING   TRUE
 Debug option, threads profiling.
#define THREAD_EXT_FIELDS
 Threads descriptor structure hook.
#define THREAD_EXT_INIT(tp)
 Threads initialization hook.
#define THREAD_EXT_EXIT(tp)
 Threads finalization hook.
#define IDLE_LOOP_HOOK()
 Idle Loop hook.
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Define Documentation

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#define CH_FREQUENCY   1000
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System tick frequency.

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Frequency of the system timer that drives the system ticks. This setting also defines the system tick time unit.

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Definition at line 51 of file chconf.h.

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#define CH_TIME_QUANTUM   20
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Round robin interval.

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This constant is the number of system ticks allowed for the threads before preemption occurs. Setting this value to zero disables the preemption for threads with equal priority and the round robin becomes cooperative. Note that higher priority threads can still preempt, the kernel is always preemptive.

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Disabling the round robin preemption makes the kernel more compact and generally faster.
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Definition at line 66 of file chconf.h.

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#define CH_USE_NESTED_LOCKS   FALSE
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Nested locks.

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If enabled then the use of nested chSysLock() / chSysUnlock() operations is allowed.
- For performance and code size reasons the recommended setting is to leave this option disabled.
- You may use this option if you need to merge ChibiOS/RT with external libraries that require nested lock/unlock operations.

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T he default is FALSE.
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Definition at line 81 of file chconf.h.

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#define CH_MEMCORE_SIZE   0
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Managed RAM size.

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Size of the RAM area to be managed by the OS. If set to zero then the whole available RAM is used. The core memory is made available to the heap allocator and/or can be used directly through the simplified core memory allocator.

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In order to let the OS manage the whole RAM the linker script must provide the __heap_base__ and __heap_end__ symbols.
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Definition at line 96 of file chconf.h.

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Referenced by core_init().

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#define CH_OPTIMIZE_SPEED   TRUE
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OS optimization.

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If enabled then time efficient rather than space efficient code is used when two possible implementations exist.

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This is not related to the compiler optimization options.
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Definition at line 112 of file chconf.h.

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#define CH_CURRP_REGISTER_CACHE   "reg"
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Exotic optimization.

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If defined then a CPU register is used as storage for the global currp variable. Caching this variable in a register greatly improves both space and time OS efficiency. A side effect is that one less register has to be saved during the context switch resulting in lower RAM usage and faster context switch.

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This option is only usable with the GCC compiler and is only useful on processors with many registers like ARM cores.
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Definition at line 132 of file chconf.h.

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#define CH_USE_REGISTRY   TRUE
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Threads registry APIs.

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If enabled then the registry APIs are included in the kernel.

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The default is TRUE.
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Definition at line 146 of file chconf.h.

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#define CH_USE_WAITEXIT   TRUE
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Threads synchronization APIs.

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If enabled then the chThdWait() function is included in the kernel.

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Definition at line 157 of file chconf.h.

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#define CH_USE_SEMAPHORES   TRUE
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Semaphores APIs.

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If enabled then the Semaphores APIs are included in the kernel.

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Definition at line 167 of file chconf.h.

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#define CH_USE_SEMAPHORES_PRIORITY   FALSE
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Semaphores queuing mode.

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If enabled then the threads are enqueued on semaphores by priority rather than in FIFO order.

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The default is FALSE. Enable this if you have special requirements.
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Definition at line 179 of file chconf.h.

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#define CH_USE_SEMSW   TRUE
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Atomic semaphore API.

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If enabled then the semaphores the chSemSignalWait() API is included in the kernel.

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Definition at line 191 of file chconf.h.

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#define CH_USE_MUTEXES   TRUE
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Mutexes APIs.

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If enabled then the mutexes APIs are included in the kernel.

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Definition at line 201 of file chconf.h.

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Conditional Variables APIs.

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If enabled then the conditional variables APIs are included in the kernel.

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Definition at line 213 of file chconf.h.

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#define CH_USE_CONDVARS_TIMEOUT   TRUE
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Conditional Variables APIs with timeout.

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If enabled then the conditional variables APIs with timeout specification are included in the kernel.

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Definition at line 225 of file chconf.h.

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Events Flags APIs.

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If enabled then the event flags APIs are included in the kernel.

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Definition at line 235 of file chconf.h.

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Events Flags APIs with timeout.

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If enabled then the events APIs with timeout specification are included in the kernel.

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Definition at line 247 of file chconf.h.

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Synchronous Messages APIs.

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If enabled then the synchronous messages APIs are included in the kernel.

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Definition at line 258 of file chconf.h.

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Synchronous Messages queuing mode.

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If enabled then messages are served by priority rather than in FIFO order.

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Definition at line 270 of file chconf.h.

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Mailboxes APIs.

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If enabled then the asynchronous messages (mailboxes) APIs are included in the kernel.

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Definition at line 282 of file chconf.h.

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I/O Queues APIs.

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If enabled then the I/O queues APIs are included in the kernel.

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Definition at line 293 of file chconf.h.

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Core Memory Manager APIs.

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If enabled then the core memory manager APIs are included in the kernel.

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Definition at line 304 of file chconf.h.

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Heap Allocator APIs.

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If enabled then the memory heap allocator APIs are included in the kernel.

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Definition at line 318 of file chconf.h.

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C-runtime allocator.

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If enabled the the heap allocator APIs just wrap the C-runtime malloc() and free() functions.

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Definition at line 332 of file chconf.h.

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Memory Pools Allocator APIs.

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If enabled then the memory pools allocator APIs are included in the kernel.

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Definition at line 343 of file chconf.h.

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Dynamic Threads APIs.

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If enabled then the dynamic threads creation APIs are included in the kernel.

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Definition at line 356 of file chconf.h.

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Debug option, parameters checks.

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If enabled then the checks on the API functions input parameters are activated.

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Definition at line 371 of file chconf.h.

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Debug option, consistency checks.

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If enabled then all the assertions in the kernel code are activated. This includes consistency checks inside the kernel, runtime anomalies and port-defined checks.

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Definition at line 383 of file chconf.h.

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Debug option, trace buffer.

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If enabled then the context switch circular trace buffer is activated.

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Definition at line 394 of file chconf.h.

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Debug option, stack checks.

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Definition at line 408 of file chconf.h.

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Debug option, stacks initialization.

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If enabled then the threads working area is filled with a byte value when a thread is created. This can be useful for the runtime measurement of the used stack.

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Definition at line 420 of file chconf.h.

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Debug option, threads profiling.

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If enabled then a field is added to the Thread structure that counts the system ticks occurred while executing the thread.

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Definition at line 433 of file chconf.h.

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Threads descriptor structure hook.

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User fields added to the end of the Thread structure.

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Definition at line 445 of file chconf.h.

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Threads initialization hook.

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User initialization code added to the chThdInit() API.

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Definition at line 459 of file chconf.h.

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Threads finalization hook.

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User finalization code added to the chThdExit() API.

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Definition at line 473 of file chconf.h.

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Idle Loop hook.

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This hook is continuously invoked by the idle thread loop.

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Definition at line 483 of file chconf.h.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Port Templates
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Description

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Non portable code templates.

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-Data Structures

struct  extctx
 Interrupt saved context. More...
struct  intctx
 System saved context. More...
struct  context
 Platform dependent part of the Thread structure. More...

-Defines

#define CH_ARCHITECTURE_XXX
 Unique macro for the implemented architecture.
#define CH_ARCHITECTURE_NAME   ""
 Name of the implemented architecture.
#define CH_ARCHITECTURE_VARIANT_NAME   ""
 Name of the architecture variant (optional).
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   0
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   0
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void id(void)
 IRQ handler function declaration.
#define PORT_FAST_IRQ_HANDLER(id)   void id(void)
 Fast IRQ handler function declaration.

-Typedefs

typedef uint8_t stkalign_t
 Base type for stack and memory alignment.

-Functions

void port_init (void)
 Port-related initialization code.
void port_lock (void)
 Kernel-lock action.
void port_unlock (void)
 Kernel-unlock action.
void port_lock_from_isr (void)
 Kernel-lock action from an interrupt handler.
void port_unlock_from_isr (void)
 Kernel-unlock action from an interrupt handler.
void port_disable (void)
 Disables all the interrupt sources.
void port_suspend (void)
 Disables the interrupt sources below kernel-level priority.
void port_enable (void)
 Enables all the interrupt sources.
void port_wait_for_interrupt (void)
 Enters an architecture-dependent IRQ-waiting mode.
void port_halt (void)
 Halts the system.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
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Define Documentation

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#define CH_ARCHITECTURE_XXX
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Unique macro for the implemented architecture.

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Definition at line 43 of file kernel/templates/chcore.h.

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Name of the implemented architecture.

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Definition at line 48 of file kernel/templates/chcore.h.

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Definition at line 53 of file kernel/templates/chcore.h.

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#define SETUP_CONTEXT( workspace,
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{                          \
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Platform dependent part of the chThdInit() API.

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This code usually setup the context switching frame represented by an intctx structure.

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Definition at line 90 of file kernel/templates/chcore.h.

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#define IDLE_THREAD_STACK_SIZE   0
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Stack size for the system idle thread.

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This size depends on the idle thread implementation, usually the idle thread should take no more space than those reserved by INT_REQUIRED_STACK.

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Definition at line 100 of file kernel/templates/chcore.h.

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#define INT_REQUIRED_STACK   0
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Per-thread stack overhead for interrupts servicing.

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This constant is used in the calculation of the correct working area size. This value can be zero on those architecture where there is a separate interrupt stack and the stack space between intctx and extctx is known to be zero.

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Definition at line 112 of file kernel/templates/chcore.h.

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#define STACK_ALIGN( n )    ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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Enforces a correct alignment for a stack area size value.

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Definition at line 118 of file kernel/templates/chcore.h.

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#define THD_WA_SIZE( n ) 
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STACK_ALIGN(sizeof(Thread) +                         \
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Computes the thread working area global size.

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Definition at line 123 of file kernel/templates/chcore.h.

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#define WORKING_AREA( s,
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Static working area allocation.

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This macro is used to allocate a static thread working area aligned as both position and size.

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Definition at line 133 of file kernel/templates/chcore.h.

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#define PORT_IRQ_PROLOGUE( ) 
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IRQ prologue code.

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This macro must be inserted at the start of all IRQ handlers enabled to invoke system APIs.

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Definition at line 140 of file kernel/templates/chcore.h.

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#define PORT_IRQ_EPILOGUE( ) 
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IRQ epilogue code.

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Definition at line 147 of file kernel/templates/chcore.h.

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#define PORT_IRQ_HANDLER( id )    void id(void)
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IRQ handler function declaration.

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Definition at line 154 of file kernel/templates/chcore.h.

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#define PORT_FAST_IRQ_HANDLER( id )    void id(void)
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Fast IRQ handler function declaration.

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Definition at line 163 of file kernel/templates/chcore.h.

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Typedef Documentation

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typedef uint8_t stkalign_t
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Base type for stack and memory alignment.

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Definition at line 58 of file kernel/templates/chcore.h.

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Function Documentation

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void port_init (void  ) 
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Port-related initialization code.

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void port_lock (void  ) 
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Kernel-lock action.

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Kernel-unlock action.

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Kernel-lock action from an interrupt handler.

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This function is invoked before invoking I-class APIs from interrupt handlers. The implementation is architecture dependent, in its simplest form it is void.

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Kernel-unlock action from an interrupt handler.

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Disables all the interrupt sources.

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Enters an architecture-dependent IRQ-waiting mode.

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Halts the system.

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void port_switch (Thread *  ntp,
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Performs a context switch between two threads.

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This is the most critical code in any port, this function is responsible for the context switch between 2 threads.

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[in] otp the thread to be switched out
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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C++ Wrapper
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C++ wrapper module. -More...

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Description

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C++ wrapper module.

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This module allows to use the ChibiOS/RT functionalities from C++ as classes and objects rather the traditional "C" APIs.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Data Streams
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Description

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This module define an abstract interface for generic data streams. Note that no code is present, streams are just abstract interfaces like structures, you should look at the systems as to a set of abstract C++ classes (even if written in C). This system has the advantage to make the access to streams independent from the implementation logic.
- The stream interface can be used as base class for high level object types such as files, sockets, serial ports, pipes etc.

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-Data Structures

struct  BaseSequentialStreamVMT
 BaseSequentialStream virtual methods table. More...
struct  BaseSequentialStream
 Base stream class. More...

-Defines

#define _base_sequential_stream_methods
 BaseSequentialStream specific methods.
#define _base_sequential_stream_data
 BaseSequentialStream specific data.
#define chSequentialStreamWrite(ip, bp, n)   ((ip)->vmt->write(ip, bp, n))
 Sequential Stream write.
#define chSequentialStreamRead(ip, bp, n)   ((ip)->vmt->read(ip, bp, n))
 Sequential Stream read.
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/* Stream write buffer method.*/                                          \
-  size_t (*write)(void *instance, const uint8_t *bp, size_t n);             \
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BaseSequentialStream specific methods.

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Definition at line 62 of file chstreams.h.

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#define chSequentialStreamWrite( ip,
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Sequential Stream write.

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The function writes data from a buffer to a stream.

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[in] ip pointer to a BaseSequentialStream or derived class
[in] bp pointer to the data buffer
[in] n the maximum amount of data to be transferred
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Definition at line 94 of file chstreams.h.

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Sequential Stream read.

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The function reads data from a stream into a buffer.

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Definition at line 107 of file chstreams.h.

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Debug APIs and services:

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-Data Structures

struct  CtxSwcEvent
 Trace buffer record. More...
struct  TraceBuffer
 Trace buffer header. More...

-Defines

#define TRACE_BUFFER_SIZE   64
 Trace buffer entries.
#define STACK_FILL_VALUE   0x55
 Fill value for thread stack area in debug mode.
#define THREAD_FILL_VALUE   0xFF
 Fill value for thread area in debug mode.
#define chDbgCheck(c, func)
 Function parameter check.
#define chDbgAssert(c, m, r)
 Condition assertion.

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void trace_init (void)
 Trace circular buffer subsystem initialization.
void chDbgTrace (Thread *otp)
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void chDbgPanic (char *msg)
 Prints a panic message on the console and then halts the system.

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TraceBuffer trace_buffer
 Public trace buffer.
char * panic_msg
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Trace buffer entries.

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Definition at line 42 of file chdebug.h.

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Definition at line 60 of file chdebug.h.

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Function parameter check.

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If the condition check fails then the kernel panics and halts.

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Referenced by adcStart(), adcStartConversion(), adcStop(), adcStopConversion(), canReceive(), canSleep(), canStart(), canStop(), canTransmit(), canWakeup(), chCondBroadcastI(), chCondInit(), chCondSignal(), chCondSignalI(), chCondWaitS(), chCondWaitTimeoutS(), chEvtBroadcastI(), chEvtDispatch(), chEvtRegisterMask(), chEvtSignal(), chEvtSignalI(), chEvtUnregister(), chHeapFree(), chHeapInit(), chIQReadTimeout(), chMBFetchS(), chMBInit(), chMBPostAheadS(), chMBPostS(), chMBReset(), chMsgSend(), chMtxInit(), chMtxLockS(), chMtxTryLockS(), chOQWriteTimeout(), chPoolAllocI(), chPoolFreeI(), chPoolInit(), chSemInit(), chSemResetI(), chSemSignal(), chSemSignalI(), chSemSignalWait(), chSemWaitS(), chSemWaitTimeoutS(), chThdCreateFromMemoryPool(), chThdCreateI(), chThdSetPriority(), chThdSleep(), chThdWait(), chVTResetI(), chVTSetI(), mmcConnect(), mmcDisconnect(), mmcSequentialRead(), mmcSequentialWrite(), mmcStart(), mmcStartSequentialRead(), mmcStartSequentialWrite(), mmcStop(), mmcStopSequentialRead(), mmcStopSequentialWrite(), palReadBus(), palSetBusMode(), palWriteBus(), pwmDisableChannel(), pwmEnableChannel(), pwmStart(), pwmStop(), sdAddFlagsI(), sdGetAndClearFlags(), sdIncomingDataI(), sdRequestDataI(), sdStart(), sdStop(), spiAcquireBus(), spiExchange(), spiIgnore(), spiReceive(), spiReleaseBus(), spiSelect(), spiSend(), spiStart(), spiStop(), and spiUnselect().

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Condition assertion.

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If the condition check fails then the kernel panics with the specified message and halts.

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Definition at line 128 of file chdebug.h.

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Trace circular buffer subsystem initialization.

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Definition at line 51 of file chdebug.c.

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Definition at line 62 of file chdebug.c.

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References chTimeNow, CtxSwcEvent::cse_state, CtxSwcEvent::cse_tid, CtxSwcEvent::cse_time, CtxSwcEvent::cse_wtobjp, currp, Thread::p_state, Thread::p_u, TraceBuffer::tb_buffer, TraceBuffer::tb_ptr, TRACE_BUFFER_SIZE, and Thread::wtobjp.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Periodic Events Timer
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Periodic Event Timer. -More...

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Description

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Periodic Event Timer.

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This timer generates an event at regular intervals. The listening threads can use the event to perform time related activities. Multiple threads can listen to the same timer.

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-Data Structures

struct  EvTimer
 Event timer structure. More...

-Defines

#define evtInit(etp, time)
 Initializes an EvTimer structure.

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void evtStart (EvTimer *etp)
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void evtStop (EvTimer *etp)
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#define evtInit( etp,
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Initializes an EvTimer structure.

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Starts the timer.

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ChibiOS/RT LogoChibiOS/RT

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Event Flags
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Description

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Event Flags, Event Sources and Event Listeners.

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Operation mode

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Each thread has a mask of pending event flags inside its Thread structure. Operations defined for event flags:

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An Event Source is a special object that can be "broadcasted" by a thread or an interrupt service routine. Broadcasting an Event Source has the effect that all the threads registered on the Event Source will be signaled with an events mask.
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-Data Structures

struct  EventListener
 Event Listener structure. More...
struct  EventSource
 Event Source structure. More...

-Defines

#define _EVENTSOURCE_DATA(name)   {(void *)(&name)}
 Data part of a static event source initializer.
#define EVENTSOURCE_DECL(name)   EventSource name = _EVENTSOURCE_DATA(name)
 Static event source initializer.
#define ALL_EVENTS   ((eventmask_t)-1)
#define EVENT_MASK(eid)   ((eventmask_t)(1 << (eid)))
#define chEvtRegister(esp, elp, eid)   chEvtRegisterMask(esp, elp, EVENT_MASK(eid))
 Registers an Event Listener on an Event Source.
#define chEvtInit(esp)   ((esp)->es_next = (EventListener *)(void *)(esp))
 Initializes an Event Source.
#define chEvtIsListening(esp)   ((void *)(esp) != (void *)(esp)->es_next)
 Verifies if there is at least one EventListener registered.

-Typedefs

typedef struct EventSource EventSource
 Event Source structure.
typedef void(* evhandler_t )(eventid_t)
 Event Handler callback function.

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void chEvtRegisterMask (EventSource *esp, EventListener *elp, eventmask_t mask)
 Registers an Event Listener on an Event Source.
void chEvtUnregister (EventSource *esp, EventListener *elp)
 Unregisters an Event Listener from its Event Source.
eventmask_t chEvtClear (eventmask_t mask)
 Clears the pending events specified in the mask.
eventmask_t chEvtPend (eventmask_t mask)
 Pends a set of event flags on the current thread, this is much faster than using chEvtBroadcast() or chEvtSignal().
void chEvtSignal (Thread *tp, eventmask_t mask)
 Pends a set of event flags on the specified Thread.
void chEvtSignalI (Thread *tp, eventmask_t mask)
 Pends a set of event flags on the specified Thread.
void chEvtBroadcast (EventSource *esp)
 Signals all the Event Listeners registered on the specified Event Source.
void chEvtBroadcastI (EventSource *esp)
 Signals all the Event Listeners registered on the specified Event Source.
void chEvtDispatch (const evhandler_t *handlers, eventmask_t mask)
 Invokes the event handlers associated to an event flags mask.
eventmask_t chEvtWaitOneTimeout (eventmask_t mask, systime_t time)
 Waits for exactly one of the specified events.
eventmask_t chEvtWaitAnyTimeout (eventmask_t mask, systime_t time)
 Waits for any of the specified events.
eventmask_t chEvtWaitAllTimeout (eventmask_t mask, systime_t time)
 Waits for all the specified events.
eventmask_t chEvtWaitOne (eventmask_t mask)
 Waits for exactly one of the specified events.
eventmask_t chEvtWaitAny (eventmask_t mask)
 Waits for any of the specified events.
eventmask_t chEvtWaitAll (eventmask_t mask)
 Waits for all the specified events.
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Define Documentation

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#define _EVENTSOURCE_DATA( name )    {(void *)(&name)}
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Data part of a static event source initializer.

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Definition at line 71 of file chevents.h.

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Static event source initializer.

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Definition at line 80 of file chevents.h.

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All events allowed mask.

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Definition at line 83 of file chevents.h.

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Definition at line 86 of file chevents.h.

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Referenced by chEvtDispatch().

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#define chEvtRegister( esp,
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[in] esp pointer to the EventSource structure
[out] elp pointer to the EventListener structure
[in] eid numeric identifier assigned to the Event Listener. The identifier is used as index for the event callback function. The value must range between zero and the size, in bit, of the eventid_t type minus one.
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Definition at line 101 of file chevents.h.

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Initializes an Event Source.

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Definition at line 109 of file chevents.h.

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Definition at line 118 of file chevents.h.

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Event Source structure.

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Event Handler callback function.

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Definition at line 124 of file chevents.h.

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void chEvtRegisterMask (EventSource *  esp,
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Registers an Event Listener on an Event Source.

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Definition at line 74 of file chevents.c.

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References chDbgCheck, chSysLock, chSysUnlock, EventListener::el_listener, EventListener::el_mask, EventListener::el_next, and EventSource::es_next.

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Referenced by chibios_rt::Event::RegisterMask().

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Unregisters an Event Listener from its Event Source.

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Definition at line 97 of file chevents.c.

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Referenced by chibios_rt::Event::Unregister().

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Definition at line 120 of file chevents.c.

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Definition at line 139 of file chevents.c.

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Definition at line 155 of file chevents.c.

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Definition at line 171 of file chevents.c.

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Definition at line 190 of file chevents.c.

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Definition at line 204 of file chevents.c.

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Definition at line 223 of file chevents.c.

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Definition at line 345 of file chevents.c.

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Referenced by chibios_rt::Event::WaitOneTimeout().

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eventmask_t chEvtWaitAnyTimeout (eventmask_t  mask,
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Waits for any of the specified events.

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Definition at line 386 of file chevents.c.

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Referenced by chibios_rt::Event::WaitAnyTimeout().

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Waits for all the specified events.

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Definition at line 424 of file chevents.c.

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References chSchGoSleepTimeoutS(), chSysLock, chSysUnlock, Thread::ewmask, Thread::p_epending, Thread::p_u, RDY_OK, THD_STATE_WTANDEVT, and TIME_IMMEDIATE.

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Referenced by chibios_rt::Event::WaitAllTimeout().

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eventmask_t chEvtWaitOne (eventmask_t  mask ) 
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The function waits for one event among those specified in mask to become pending then the event is cleared and returned.

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Definition at line 256 of file chevents.c.

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References chSchGoSleepS(), chSysLock, chSysUnlock, Thread::ewmask, Thread::p_epending, Thread::p_u, and THD_STATE_WTOREVT.

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Referenced by chibios_rt::Event::WaitOne().

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Definition at line 283 of file chevents.c.

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Waits for all the specified events.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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External Components

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ChibiOS/RT supports several external libraries through support interfaces and/or demos. Credit should be given to the original authors for making available such useful code.
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  • uIP, by Adam Dunkels at the Swedish Institute of Computer Science, link.
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  • lwIP, many authors, link.
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External components and libraries are not directly supported and are used "as is" or with minor integration patching.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Heaps
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Description

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Heap Allocator related APIs.

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Operation mode

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The heap allocator implements a first-fit strategy and its APIs are functionally equivalent to the usual malloc() and free() library functions. The main difference is that the OS heap APIs are guaranteed to be thread safe.
- By enabling the CH_USE_MALLOC_HEAP option the heap manager will use the runtime-provided malloc() and free() as backend for the heap APIs instead of the system provided allocator.
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-Data Structures

union  heap_header
 Memory heap block header. More...
struct  memory_heap
 Structure describing a memory heap. More...

-Functions

void heap_init (void)
 Initializes the default heap.
void chHeapInit (MemoryHeap *heapp, void *buf, size_t size)
 Initializes a memory heap from a static memory area.
void * chHeapAlloc (MemoryHeap *heapp, size_t size)
 Allocates a block of memory from the heap by using the first-fit algorithm.
void chHeapFree (void *p)
 Frees a previously allocated memory block.
size_t chHeapStatus (MemoryHeap *heapp, size_t *sizep)
 Reports the heap status.
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Function Documentation

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void heap_init (void  ) 
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Initializes the default heap.

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Definition at line 73 of file chheap.c.

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void chHeapInit (MemoryHeap *  heapp,
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Initializes a memory heap from a static memory area.

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[out] heapp pointer to the memory heap descriptor to be initialized
[in] buf heap buffer base
[in] size heap size
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Definition at line 93 of file chheap.c.

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void * chHeapAlloc (MemoryHeap *  heapp,
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Allocates a block of memory from the heap by using the first-fit algorithm.

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[in] size the size of the block to be allocated. Note that the allocated block may be a bit bigger than the requested size for alignment and fragmentation reasons.
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Definition at line 124 of file chheap.c.

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void chHeapFree (void *  p ) 
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size_t chHeapStatus (MemoryHeap *  heapp,
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Reports the heap status.

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[in] sizep pointer to a variable that will receive the total fragmented free space
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Internals
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Description

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All the functions present in this module, while public, are not an OS API and should not be directly used in the user applications code.

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struct  ThreadsQueue
 Generic threads bidirectional linked list header and element. More...
struct  ThreadsList
 Generic threads single link list, it works like a stack. More...

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#define queue_init(tqp)   ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp));
 Threads queue initialization.
#define list_init(tlp)   ((tlp)->p_next = (Thread *)(tlp))
 Threads list initialization.
#define isempty(p)   ((p)->p_next == (Thread *)(p))
 Evaluates to TRUE if the specified threads queue or list is empty.
#define notempty(p)   ((p)->p_next != (Thread *)(p))
 Evaluates to TRUE if the specified threads queue or list is not empty.
#define _THREADSQUEUE_DATA(name)   {(Thread *)&name, (Thread *)&name}
 Data part of a static threads queue initializer.
#define THREADSQUEUE_DECL(name)   ThreadsQueue name = _THREADSQUEUE_DATA(name)
 Static threads queue initializer.

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void prio_insert (Thread *tp, ThreadsQueue *tqp)
 Inserts a thread into a priority ordered queue.
void queue_insert (Thread *tp, ThreadsQueue *tqp)
 Inserts a Thread into a queue.
Thread * fifo_remove (ThreadsQueue *tqp)
 Removes the first-out Thread from a queue and returns it.
Thread * lifo_remove (ThreadsQueue *tqp)
 Removes the last-out Thread from a queue and returns it.
Thread * dequeue (Thread *tp)
 Removes a Thread from a queue and returns it.
void list_insert (Thread *tp, ThreadsList *tlp)
 Pushes a Thread on top of a stack list.
Thread * list_remove (ThreadsList *tlp)
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Define Documentation

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Threads queue initialization.

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Definition at line 46 of file chlists.h.

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Referenced by chCondBroadcastI(), chCondSignal(), chCondSignalI(), chMsgRelease(), chMtxUnlock(), chMtxUnlockAll(), chMtxUnlockS(), chSchDoRescheduleI(), chSchGoSleepS(), chSemSignal(), chSemSignalI(), and chSemSignalWait().

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines
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I/O Channels
- -[I/O Support] -

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-Collaboration diagram for I/O Channels:
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Description

-

This module defines an abstract interface for I/O channels by extending the BaseSequentialStream interface. Note that no code is present, I/O channels are just abstract interface like structures, you should look at the systems as to a set of abstract C++ classes (even if written in C). Specific device drivers can use/extend the interface and implement them.
- This system has the advantage to make the access to channels independent from the implementation logic.

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-Data Structures

struct  BaseChannelVMT
 BaseChannel virtual methods table. More...
struct  BaseChannel
 Base channel class. More...
struct  BaseAsynchronousChannelVMT
 BaseAsynchronousChannel virtual methods table. More...
struct  BaseAsynchronousChannel
 Base asynchronous channel class. More...

-Defines

#define _base_channel_methods
 BaseChannel specific methods.
#define _base_channel_data   _base_sequential_stream_data
 BaseChannel specific data.
#define chIOPutWouldBlock(ip)   ((ip)->vmt->putwouldblock(ip))
 Channel output check.
#define chIOGetWouldBlock(ip)   ((ip)->vmt->getwouldblock(ip))
 Channel input check.
#define chIOPut(ip, b)   ((ip)->vmt->put(ip, b, TIME_INFINITE))
 Channel blocking byte write.
#define chIOPutTimeout(ip, b, time)   ((ip)->vmt->put(ip, b, time))
 Channel blocking byte write with timeout.
#define chIOGet(ip)   ((ip)->vmt->get(ip, TIME_INFINITE))
 Channel blocking byte read.
#define chIOGetTimeout(ip, time)   ((ip)->vmt->get(ip, time))
 Channel blocking byte read with timeout.
#define chIOWriteTimeout(ip, bp, n, time)   ((ip)->vmt->writet(ip, bp, n, time))
 Channel blocking write with timeout.
#define chIOReadTimeout(ip, bp, n, time)   ((ip)->vmt->readt(ip, bp, n, time))
 Channel blocking read with timeout.
#define _base_asynchronous_channel_methods   _base_channel_methods
 BaseAsynchronousChannel specific methods.
#define _base_asynchronous_channel_data
 BaseAsynchronousChannel specific data.
#define chIOGetWriteEventSource(ip)   (&((ip)->vmt->oevent))
 Returns the write event source.
#define chIOGetReadEventSource(ip)   (&((ip)->vmt->ievent))
 Returns the read event source.
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Define Documentation

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#define _base_channel_methods
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_base_sequential_stream_methods                                           \
-  /* Channel output check.*/                                                \
-  bool_t (*putwouldblock)(void *instance);                                  \
-  /* Channel input check.*/                                                 \
-  bool_t (*getwouldblock)(void *instance);                                  \
-  /* Channel put method with timeout specification.*/                       \
-  msg_t (*put)(void *instance, uint8_t b, systime_t time);                  \
-  /* Channel get method with timeout specification.*/                       \
-  msg_t (*get)(void *instance, systime_t time);                             \
-  /* Channel write method with timeout specification.*/                     \
-  size_t (*writet)(void *instance, const uint8_t *bp,                       \
-                  size_t n, systime_t time);                                \
-  /* Channel read method with timeout specification.*/                      \
-  size_t (*readt)(void *instance, uint8_t *bp, size_t n, systime_t time);
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BaseChannel specific methods.

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Definition at line 51 of file chioch.h.

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#define _base_channel_data   _base_sequential_stream_data
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BaseChannel specific data.

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Definition at line 72 of file chioch.h.

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#define chIOPutWouldBlock( ip )    ((ip)->vmt->putwouldblock(ip))
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Channel output check.

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This function verifies if a subsequent put/write operation would block.

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[in] ip pointer to a BaseChannel or derived class
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The output queue status:
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FALSE if the output queue has space and would not block a write operation.
TRUE if the output queue is full and would block a write operation.
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Definition at line 107 of file chioch.h.

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#define chIOGetWouldBlock( ip )    ((ip)->vmt->getwouldblock(ip))
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Channel input check.

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This function verifies if a subsequent get/read operation would block.

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[in] ip pointer to a BaseChannel or derived class
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The input queue status:
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FALSE if the input queue contains data and would not block a read operation.
TRUE if the input queue is empty and would block a read operation.
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Definition at line 121 of file chioch.h.

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#define chIOPut( ip,
 b 
)   ((ip)->vmt->put(ip, b, TIME_INFINITE))
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Channel blocking byte write.

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This function writes a byte value to a channel. If the channel is not ready to accept data then the calling thread is suspended.

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[in] ip pointer to a BaseChannel or derived class
[in] b the byte value to be written to the channel
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The operation status:
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Q_OK if the operation succeeded.
Q_RESET if the channel associated queue (if any) was reset.
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Definition at line 134 of file chioch.h.

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#define chIOPutTimeout( ip,
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)   ((ip)->vmt->put(ip, b, time))
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Channel blocking byte write with timeout.

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This function writes a byte value to a channel. If the channel is not ready to accept data then the calling thread is suspended.

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[in] ip pointer to a BaseChannel or derived class
[in] b the byte value to be written to the channel
[in] time the number of ticks before the operation timeouts, the following special values are allowed:

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The operation status:
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Q_OK if the operation succeeded.
Q_TIMEOUT if the specified time expired.
Q_RESET if the channel associated queue (if any) was reset.
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Definition at line 153 of file chioch.h.

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#define chIOGet( ip )    ((ip)->vmt->get(ip, TIME_INFINITE))
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Channel blocking byte read.

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This function reads a byte value from a channel. If the data is not available then the calling thread is suspended.

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[in] ip pointer to a BaseChannel or derived class
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A byte value from the queue or:
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Q_RESET if the channel associated queue (if any) was reset.
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Definition at line 164 of file chioch.h.

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#define chIOGetTimeout( ip,
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)   ((ip)->vmt->get(ip, time))
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Channel blocking byte read with timeout.

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This function reads a byte value from a channel. If the data is not available then the calling thread is suspended.

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[in] ip pointer to a BaseChannel or derived class
[in] time the number of ticks before the operation timeouts, the following special values are allowed:

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A byte value from the queue or:
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Q_TIMEOUT if the specified time expired.
Q_RESET if the channel associated queue (if any) was reset.
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Definition at line 181 of file chioch.h.

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#define chIOWriteTimeout( ip,
 bp,
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)   ((ip)->vmt->writet(ip, bp, n, time))
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Channel blocking write with timeout.

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The function writes data from a buffer to a channel. If the channel is not ready to accept data then the calling thread is suspended.

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[in] ip pointer to a BaseChannel or derived class
[out] bp pointer to the data buffer
[in] n the maximum amount of data to be transferred
[in] time the number of ticks before the operation timeouts, the following special values are allowed:

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The number of bytes transferred.
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Definition at line 198 of file chioch.h.

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#define chIOReadTimeout( ip,
 bp,
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 time 
)   ((ip)->vmt->readt(ip, bp, n, time))
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Channel blocking read with timeout.

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The function reads data from a channel into a buffer. If the data is not available then the calling thread is suspended.

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[in] ip pointer to a BaseChannel or derived class
[in] bp pointer to the data buffer
[in] n the maximum amount of data to be transferred
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Definition at line 216 of file chioch.h.

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#define _base_asynchronous_channel_methods   _base_channel_methods
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BaseAsynchronousChannel specific methods.

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Definition at line 223 of file chioch.h.

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#define _base_asynchronous_channel_data
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_base_channel_data                                                        \
-  /* Data Available EventSource.*/                                          \
-  EventSource           ievent;                                             \
-  /* Data Transmitted EventSource.*/                                        \
-  EventSource           oevent;
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BaseAsynchronousChannel specific data.

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Definition at line 229 of file chioch.h.

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#define chIOGetWriteEventSource( ip )    (&((ip)->vmt->oevent))
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Returns the write event source.

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The write event source is broadcasted when the channel is ready for write operations. This usually happens when the internal output queue becomes empty.

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[in] ip pointer to a BaseAsynchronousChannel or derived class
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Definition at line 266 of file chioch.h.

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#define chIOGetReadEventSource( ip )    (&((ip)->vmt->ievent))
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Returns the read event source.

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The read event source is broadcasted when the channel is ready for read operations. This usually happens when the internal input queue becomes non-empty.

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Definition at line 278 of file chioch.h.

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-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/group__io__channels.png b/ChibiOS_2.0.8/docs/html/group__io__channels.png deleted file mode 100644 index 1e1039e..0000000 Binary files a/ChibiOS_2.0.8/docs/html/group__io__channels.png and /dev/null differ diff --git a/ChibiOS_2.0.8/docs/html/group__io__queues.html b/ChibiOS_2.0.8/docs/html/group__io__queues.html deleted file mode 100644 index 689d315..0000000 --- a/ChibiOS_2.0.8/docs/html/group__io__queues.html +++ /dev/null @@ -1,1344 +0,0 @@ - - -ChibiOS/RT: I/O Queues - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions
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I/O Queues
- -[I/O Support] -

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-Collaboration diagram for I/O Queues:
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Description

-

ChibiOS/RT queues are mostly used in serial-like device drivers. The device drivers are usually designed to have a lower side (lower driver, it is usually an interrupt service routine) and an upper side (upper driver, accessed by the application threads).
- There are several kind of queues:
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  • Input queue, unidirectional queue where the writer is the lower side and the reader is the upper side.
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  • Output queue, unidirectional queue where the writer is the upper side and the reader is the lower side.
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  • Full duplex queue, bidirectional queue. Full duplex queues are implemented by pairing an input queue and an output queue together.
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In order to use the I/O queues the CH_USE_QUEUES option must be enabled in chconf.h.
- I/O queues are usually used as an implementation layer for the I/O channels interface, also see I/O Channels.

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-Data Structures

struct  GenericQueue
 Generic I/O queue structure. More...

-Defines

#define Q_OK   RDY_OK
 Returned by the queue functions if the operation is successful.
#define Q_TIMEOUT   RDY_TIMEOUT
 Returned by the queue functions if a timeout occurs.
#define Q_RESET   RDY_RESET
 Returned by the queue functions if the queue is reset.
#define Q_EMPTY   -3
 Returned by the queue functions if the queue is empty.
#define Q_FULL   -4
 Returned by the queue functions if the queue is full.
#define chQSize(q)   ((q)->q_top - (q)->q_buffer)
 Returns the queue's buffer size.
#define chQSpace(q)   chSemGetCounterI(&(q)->q_sem)
 Queue space.
#define chIQIsEmpty(q)   ((bool_t)(chQSpace(q) <= 0))
 Evaluates to TRUE if the specified Input Queue is empty.
#define chIQIsFull(q)   ((bool_t)(chQSpace(q) >= chQSize(q)))
 Evaluates to TRUE if the specified Input Queue is full.
#define chIQGet(iqp)   chIQGetTimeout(iqp, TIME_INFINITE)
 Input queue read.
#define _INPUTQUEUE_DATA(name, buffer, size, inotify)
 Data part of a static input queue initializer.
#define INPUTQUEUE_DECL(name, buffer, size, inotify)   InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify)
 Static input queue initializer.
#define chOQIsEmpty(q)   ((bool_t)(chQSpace(q) >= chQSize(q)))
 Evaluates to TRUE if the specified Output Queue is empty.
#define chOQIsFull(q)   ((bool_t)(chQSpace(q) <= 0))
 Evaluates to TRUE if the specified Output Queue is full.
#define chOQPut(oqp, b)   chOQPutTimeout(oqp, b, TIME_INFINITE)
 Output queue write.
#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify)
 Data part of a static output queue initializer.
#define OUTPUTQUEUE_DECL(name, buffer, size, onotify)   InputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify)
 Static output queue initializer.

-Typedefs

typedef void(* qnotify_t )(void)
 Queue notification callback type.
typedef GenericQueue InputQueue
 Input queue structure.
typedef GenericQueue OutputQueue
 Output queue structure.

-Functions

void chIQInit (InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy)
 Initializes an input queue.
void chIQResetI (InputQueue *iqp)
 Resets an input queue.
msg_t chIQPutI (InputQueue *iqp, uint8_t b)
 Input queue write.
msg_t chIQGetTimeout (InputQueue *iqp, systime_t time)
 Input queue read with timeout.
size_t chIQReadTimeout (InputQueue *iqp, uint8_t *bp, size_t n, systime_t time)
 Input queue read with timeout.
void chOQInit (OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy)
 Initializes an output queue.
void chOQResetI (OutputQueue *oqp)
 Resets an output queue.
msg_t chOQPutTimeout (OutputQueue *oqp, uint8_t b, systime_t time)
 Output queue write with timeout.
msg_t chOQGetI (OutputQueue *oqp)
 Output queue read.
size_t chOQWriteTimeout (OutputQueue *oqp, const uint8_t *bp, size_t n, systime_t time)
 Output queue write with timeout.
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Define Documentation

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#define Q_OK   RDY_OK
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Returned by the queue functions if the operation is successful.

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Definition at line 51 of file chqueues.h.

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Referenced by sdIncomingDataI(), and sdRequestDataI().

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Returned by the queue functions if a timeout occurs.

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Definition at line 53 of file chqueues.h.

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Returned by the queue functions if the queue is reset.

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Definition at line 55 of file chqueues.h.

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Returned by the queue functions if the queue is empty.

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Definition at line 57 of file chqueues.h.

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Returned by the queue functions if the queue is full.

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Definition at line 59 of file chqueues.h.

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#define chQSize( q )    ((q)->q_top - (q)->q_buffer)
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Returns the queue's buffer size.

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Definition at line 83 of file chqueues.h.

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#define chQSpace( q )    chSemGetCounterI(&(q)->q_sem)
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Queue space.

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Returns the used space if used on an Input Queue and the empty space if used on an Output Queue.

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Definition at line 92 of file chqueues.h.

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#define chIQIsEmpty( q )    ((bool_t)(chQSpace(q) <= 0))
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Evaluates to TRUE if the specified Input Queue is empty.

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Definition at line 108 of file chqueues.h.

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Referenced by chIQReadTimeout(), and sdIncomingDataI().

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#define chIQIsFull( q )    ((bool_t)(chQSpace(q) >= chQSize(q)))
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Definition at line 111 of file chqueues.h.

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Referenced by chIQPutI().

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#define chIQGet( iqp )    chIQGetTimeout(iqp, TIME_INFINITE)
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Input queue read.

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This function reads a byte value from an input queue. If the queue is empty then the calling thread is suspended until a byte arrives in the queue.

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A byte value from the queue or:
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Q_RESET if the queue was reset.
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Definition at line 123 of file chqueues.h.

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#define _INPUTQUEUE_DATA( name,
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{                 \
-  (uint8_t *)(buffer),                                                  \
-  (uint8_t *)(buffer) + size,                                           \
-  (uint8_t *)(buffer),                                                  \
-  (uint8_t *)(buffer),                                                  \
-  _SEMAPHORE_DATA(name.q_sem, 0),                                       \
-  inotify                                                               \
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Data part of a static input queue initializer.

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This macro should be used when statically initializing an input queue that is part of a bigger structure.

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[in] name the name of the input queue variable
[in] buffer pointer to the queue buffer area
[in] size size of the queue buffer area
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Definition at line 135 of file chqueues.h.

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#define INPUTQUEUE_DECL( name,
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Static input queue initializer.

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Statically initialized input queues require no explicit initialization using chIQInit().

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[in] buffer pointer to the queue buffer area
[in] size size of the queue buffer area
[in] inotify input notification callback pointer
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Definition at line 154 of file chqueues.h.

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#define chOQIsEmpty( q )    ((bool_t)(chQSpace(q) >= chQSize(q)))
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Definition at line 173 of file chqueues.h.

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Referenced by chOQGetI().

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Definition at line 178 of file chqueues.h.

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#define chOQPut( oqp,
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Output queue write.

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This function writes a byte value to an output queue. If the queue is full then the calling thread is suspended until there is space in the queue.

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[in] b the byte value to be written in the queue
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Definition at line 192 of file chqueues.h.

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#define _OUTPUTQUEUE_DATA( name,
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{                \
-  (uint8_t *)(buffer),                                                  \
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-  (uint8_t *)(buffer),                                                  \
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-  onotify                                                               \
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Data part of a static output queue initializer.

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[in] buffer pointer to the queue buffer area
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[in] onotify output notification callback pointer
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Static output queue initializer.

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Statically initialized output queues require no explicit initialization using chOQInit().

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[in] name the name of the output queue variable
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[in] onotify output notification callback pointer
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Definition at line 223 of file chqueues.h.

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typedef void(* qnotify_t)(void)
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Queue notification callback type.

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Definition at line 48 of file chqueues.h.

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Input queue structure.

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Definition at line 105 of file chqueues.h.

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Output queue structure.

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Definition at line 168 of file chqueues.h.

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void chIQInit (InputQueue *  iqp,
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qnotify_t  infy 
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Initializes an input queue.

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[out] iqp pointer to an InputQueue structure
[in] bp pointer to a memory area allocated as queue buffer
[in] size size of the queue buffer
[in] infy pointer to a callback function that is invoked when data is read from the queue. The value can be NULL.
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Definition at line 69 of file chqueues.c.

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void chIQResetI (InputQueue *  iqp ) 
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Definition at line 86 of file chqueues.c.

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Referenced by sdStop().

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msg_t chIQPutI (InputQueue *  iqp,
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Input queue write.

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A byte value is written into the low end of an input queue.

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Q_OK if the operation has been completed with success.
Q_FULL if the queue is full and the operation cannot be completed.
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Definition at line 103 of file chqueues.c.

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msg_t chIQGetTimeout (InputQueue *  iqp,
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Input queue read with timeout.

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This function reads a byte value from an input queue. If the queue is empty then the calling thread is suspended until a byte arrives in the queue or a timeout occurs.

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Q_TIMEOUT if the specified time expired.
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Definition at line 131 of file chqueues.c.

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size_t chIQReadTimeout (InputQueue *  iqp,
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systime_t  time 
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Input queue read with timeout.

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The function reads data from an input queue into a buffer. The operation completes when the specified amount of data has been transferred or after the specified timeout or if the queue has been reset.

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Definition at line 174 of file chqueues.c.

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void chOQInit (OutputQueue *  oqp,
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Initializes an output queue.

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[in] size size of the queue buffer
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Definition at line 224 of file chqueues.c.

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Referenced by sdObjectInit().

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void chOQResetI (OutputQueue *  oqp ) 
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Definition at line 241 of file chqueues.c.

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Referenced by sdStop().

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msg_t chOQPutTimeout (OutputQueue *  oqp,
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Output queue write with timeout.

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This function writes a byte value to an output queue. If the queue is full then the calling thread is suspended until there is space in the queue or a timeout occurs.

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Definition at line 265 of file chqueues.c.

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msg_t chOQGetI (OutputQueue *  oqp ) 
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Output queue read.

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A byte value is read from the low end of an output queue.

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Definition at line 292 of file chqueues.c.

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Referenced by sdRequestDataI().

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Output queue write with timeout.

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Definition at line 327 of file chqueues.c.

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#define _CHIBIOS_RT_
 ChibiOS/RT identification macro.
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Description

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Asynchronous messages.

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Operation mode

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A mailbox is an asynchronous communication mechanism.
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A message is a variable of type msg_t that is guaranteed to have the same size of and be compatible with (data) pointers (anyway an explicit cast is needed). If larger messages need to be exchanged then a pointer to a structure can be posted in the mailbox but the posting side has no predefined way to know when the message has been processed. A possible approach is to allocate memory (from a memory pool as example) from the posting side and free it on the fetching side. Another approach is to set a "done" flag into the structure pointed by the message.
- In order to use the mailboxes APIs the CH_USE_MAILBOXES option must be enabled in chconf.h.

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-Defines

#define chMBSize(mbp)   ((mbp)->mb_top - (mbp)->mb_buffer)
 Returns the mailbox buffer size.
#define chMBGetEmpty(mbp)   chSemGetCounterI(&(mbp)->mb_emptysem)
 Returns the free space into the mailbox.
#define chMBGetFull(mbp)   chSemGetCounterI(&(mbp)->mb_fullsem)
 Returns the number of messages into the mailbox.
#define chMBPeek(mbp)   (*(mbp)->mb_rdptr)
 Returns the next message in the queue without removing it.
#define _MAILBOX_DATA(name, buffer, size)
 Data part of a static mailbox initializer.
#define MAILBOX_DECL(name, buffer, size)   Mailbox name = _MAILBOX_DATA(name, buffer, size)
 Static mailbox initializer.

-Functions

void chMBInit (Mailbox *mbp, msg_t *buf, cnt_t n)
 Initializes a Mailbox object.
void chMBReset (Mailbox *mbp)
 Resets a Mailbox object.
msg_t chMBPost (Mailbox *mbp, msg_t msg, systime_t time)
 Posts a message into a mailbox.
msg_t chMBPostS (Mailbox *mbp, msg_t msg, systime_t time)
 Posts a message into a mailbox.
msg_t chMBPostAhead (Mailbox *mbp, msg_t msg, systime_t time)
 Posts an high priority message into a mailbox.
msg_t chMBPostAheadS (Mailbox *mbp, msg_t msg, systime_t time)
 Posts an high priority message into a mailbox.
msg_t chMBFetch (Mailbox *mbp, msg_t *msgp, systime_t time)
 Retrieves a message from a mailbox.
msg_t chMBFetchS (Mailbox *mbp, msg_t *msgp, systime_t time)
 Retrieves a message from a mailbox.
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Define Documentation

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#define chMBSize( mbp )    ((mbp)->mb_top - (mbp)->mb_buffer)
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Returns the mailbox buffer size.

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Definition at line 80 of file chmboxes.h.

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#define chMBGetEmpty( mbp )    chSemGetCounterI(&(mbp)->mb_emptysem)
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Returns the free space into the mailbox.

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[in] mbp the pointer to an initialized Mailbox object
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Definition at line 93 of file chmboxes.h.

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#define chMBGetFull( mbp )    chSemGetCounterI(&(mbp)->mb_fullsem)
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Returns the number of messages into the mailbox.

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Definition at line 105 of file chmboxes.h.

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Returns the next message in the queue without removing it.

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Definition at line 114 of file chmboxes.h.

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#define _MAILBOX_DATA( name,
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{                             \
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Data part of a static mailbox initializer.

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This macro should be used when statically initializing a mailbox that is part of a bigger structure.

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[in] name the name of the mailbox variable
[in] buffer pointer to the mailbox buffer area
[in] size size of the mailbox buffer area
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Definition at line 125 of file chmboxes.h.

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Static mailbox initializer.

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Statically initialized mailboxes require no explicit initialization using chMBInit().

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[in] name the name of the mailbox variable
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[in] size size of the mailbox buffer area
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Definition at line 143 of file chmboxes.h.

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void chMBInit (Mailbox *  mbp,
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cnt_t  n 
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Initializes a Mailbox object.

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[out] mbp the pointer to the Mailbox structure to be initialized
[in] buf the circular messages buffer
[in] n the buffer size as number of msg_t
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Definition at line 69 of file chmboxes.c.

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void chMBReset (Mailbox *  mbp ) 
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Resets a Mailbox object.

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All the waiting threads are resumed with status RDY_RESET and the queued messages are lost.

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[in] mbp the pointer to an initialized Mailbox object
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Definition at line 86 of file chmboxes.c.

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msg_t chMBPost (Mailbox *  mbp,
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Posts a message into a mailbox.

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The invoking thread waits until a empty slot in the mailbox becomes available or the specified time runs out.

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[in] mbp the pointer to an initialized Mailbox object
[in] msg the message to be posted on the mailbox
[in] time the number of ticks before the operation timeouts, the following special values are allowed:

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The operation status.
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RDY_OK if the message was correctly posted.
RDY_RESET if the mailbox was reset while waiting.
RDY_TIMEOUT if the operation timed out.
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Definition at line 115 of file chmboxes.c.

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References chMBPostS(), chSysLock, and chSysUnlock.

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msg_t chMBPostS (Mailbox *  mbp,
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Posts a message into a mailbox.

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The invoking thread waits until a empty slot in the mailbox becomes available or the specified time runs out.

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[in] mbp the pointer to an initialized Mailbox object
[in] msg the message to be posted on the mailbox
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The operation status.
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RDY_OK if the message was correctly posted.
RDY_RESET if the mailbox was reset while waiting.
RDY_TIMEOUT if the operation timed out.
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Definition at line 141 of file chmboxes.c.

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References chDbgCheck, chSchRescheduleS(), chSemSignalI(), chSemWaitTimeoutS(), and RDY_OK.

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Referenced by chMBPost().

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msg_t chMBPostAhead (Mailbox *  mbp,
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Posts an high priority message into a mailbox.

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The invoking thread waits until a empty slot in the mailbox becomes available or the specified time runs out.

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[in] msg the message to be posted on the mailbox
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RDY_OK if the message was correctly posted.
RDY_RESET if the mailbox was reset while waiting.
RDY_TIMEOUT if the operation timed out.
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Definition at line 174 of file chmboxes.c.

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msg_t chMBPostAheadS (Mailbox *  mbp,
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RDY_OK if the message was correctly posted.
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Definition at line 200 of file chmboxes.c.

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msg_t chMBFetch (Mailbox *  mbp,
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Retrieves a message from a mailbox.

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The invoking thread waits until a message is posted in the mailbox or the specified time runs out.

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[out] msgp pointer to a message variable for the received message
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Definition at line 233 of file chmboxes.c.

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msg_t chMBFetchS (Mailbox *  mbp,
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[out] msgp pointer to a message variable for the received message
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Definition at line 259 of file chmboxes.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Defines | -Typedefs | -Functions
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Core Memory Manager
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Description

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Core Memory Manager related APIs and services.

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Operation mode

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The core memory manager is a simplified allocator that only allows to allocate memory blocks without the possibility to free them.
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By having a centralized memory provider the various allocators can coexist and share the main memory.
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- In order to use the core memory manager APIs the CH_USE_MEMCORE option must be enabled in chconf.h.

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-Defines

#define MEM_ALIGN_MASK   (sizeof(stkalign_t) - 1)
 Alignment mask constant.
#define MEM_ALIGN_SIZE(p)   (((size_t)(p) + MEM_ALIGN_MASK) & ~MEM_ALIGN_MASK)
 Alignment helper macro.
#define MEM_IS_ALIGNED(p)   (((size_t)(p) & MEM_ALIGN_MASK) == 0)
 Returns whatever a pointer or memory size is aligned to the type align_t.

-Typedefs

typedef void *(* memgetfunc_t )(size_t size)
 Memory get function.

-Functions

void core_init (void)
 Low level memory manager initialization.
void * chCoreAlloc (size_t size)
 Allocates a memory block.
void * chCoreAllocI (size_t size)
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size_t chCoreStatus (void)
 Core memory status.
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#define MEM_ALIGN_MASK   (sizeof(stkalign_t) - 1)
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Alignment mask constant.

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Definition at line 48 of file chmemcore.h.

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Definition at line 53 of file chmemcore.h.

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Definition at line 59 of file chmemcore.h.

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typedef void*(* memgetfunc_t)(size_t size)
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Memory get function.

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void core_init (void  ) 
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Definition at line 62 of file chmemcore.c.

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void * chCoreAlloc (size_t  size ) 
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Definition at line 88 of file chmemcore.c.

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void * chCoreAllocI (size_t  size ) 
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Memory Management
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Memory Management services.

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Memory Streams.

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This module allows to use a memory area (RAM or ROM) using a Data Streams interface.

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struct  MemStreamVMT
 MemStream virtual methods table. More...
struct  MemoryStream
 Memory stream object. More...

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#define _memory_stream_data
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void msObjectInit (MemoryStream *msp, uint8_t *buffer, size_t size, size_t eos)
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ChibiOS/RT LogoChibiOS/RT

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Synchronous inter-thread messages APIs and services.

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Operation Mode

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Synchronous messages are an easy to use and fast IPC mechanism, threads can both act as message servers and/or message clients, the mechanism allows data to be carried in both directions. Note that messages are not copied between the client and server threads but just a pointer passed so the exchange is very time efficient.
- Messages are usually processed in FIFO order but it is possible to process them in priority order by enabling the CH_USE_MESSAGES_PRIORITY option in chconf.h.
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#define chMsgIsPendingI(tp)   ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue)
 Evaluates to TRUE if the thread has pending messages.
#define chMsgGetI(tp)   ((tp)->p_msgqueue.p_next->p_msg)
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msg_t chMsgSend (Thread *tp, msg_t msg)
 Sends a message to the specified thread.
msg_t chMsgWait (void)
 Suspends the thread and waits for an incoming message.
msg_t chMsgGet (void)
 Returns the next message in the queue.
void chMsgRelease (msg_t msg)
 Releases the thread waiting on top of the messages queue.
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#define chMsgIsPendingI( tp )    ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue)
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msg_t chMsgSend (Thread *  tp,
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The sender is stopped until the receiver executes a chMsgRelease()after receiving the message.

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Definition at line 70 of file chmsg.c.

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References chDbgCheck, chSchGoSleepS(), chSchReadyI(), chSysLock, chSysUnlock, Thread::p_msg, Thread::p_msgqueue, Thread::p_state, Thread::p_u, Thread::rdymsg, THD_STATE_SNDMSG, THD_STATE_WTMSG, and Thread::wtobjp.

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The pointer to the message structure. Note, it is always the message associated to the thread on the top of the messages queue.
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Definition at line 97 of file chmsg.c.

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Mutexes related APIs and services.

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A mutex is a threads synchronization object that can be in two distinct states:

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Constraints

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In ChibiOS/RT the Unlock operations are always performed in lock-reverse order. The unlock API does not even have a parameter, the mutex to unlock is selected from an internal, per-thread, stack of owned mutexes. This both improves the performance and is required for an efficient implementation of the priority inheritance mechanism.

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The priority inversion problem

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The mutexes in ChibiOS/RT implements the full priority inheritance mechanism in order handle the priority inversion problem.
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struct  Mutex
 Mutex structure. More...

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#define _MUTEX_DATA(name)   {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL}
 Data part of a static mutex initializer.
#define MUTEX_DECL(name)   Mutex name = _MUTEX_DATA(name)
 Static mutex initializer.
#define chMtxQueueNotEmptyS(mp)   notempty(&(mp)->m_queue)
 Returns TRUE if the mutex queue contains at least a waiting thread.

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typedef struct Mutex Mutex
 Mutex structure.

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void chMtxInit (Mutex *mp)
 Initializes s Mutex structure.
void chMtxLock (Mutex *mp)
 Locks the specified mutex.
void chMtxLockS (Mutex *mp)
 Locks the specified mutex.
bool_t chMtxTryLock (Mutex *mp)
 Tries to lock a mutex.
bool_t chMtxTryLockS (Mutex *mp)
 Tries to lock a mutex.
Mutex * chMtxUnlock (void)
 Unlocks the next owned mutex in reverse lock order.
Mutex * chMtxUnlockS (void)
 Unlocks the next owned mutex in reverse lock order.
void chMtxUnlockAll (void)
 Unlocks all the mutexes owned by the invoking thread.
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#define _MUTEX_DATA( name )    {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL}
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Definition at line 108 of file chmtx.c.

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bool_t chMtxTryLockS (Mutex *  mp ) 
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Definition at line 199 of file chmtx.c.

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Definition at line 216 of file chmtx.c.

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Mutex * chMtxUnlockS (void  ) 
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Definition at line 270 of file chmtx.c.

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Definition at line 322 of file chmtx.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Memory Pools
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Description

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Memory Pools related APIs and services.

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Operation mode

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The Memory Pools APIs allow to allocate/free fixed size objects in constant time and reliably without memory fragmentation problems.
- In order to use the memory pools APIs the CH_USE_MEMPOOLS option must be enabled in chconf.h.

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-Data Structures

struct  pool_header
 Memory pool free object header. More...
struct  MemoryPool
 Memory pool descriptor. More...

-Defines

#define _MEMORYPOOL_DATA(name, size, provider)   {NULL, MEM_ALIGN_SIZE(size), provider}
 Data part of a static memory pool initializer.
#define MEMORYPOOL_DECL(name, size, provider)   MemoryPool name = _MEMORYPOOL_DATA(name, size, provider)
 Static memory pool initializer in hungry mode.

-Functions

void chPoolInit (MemoryPool *mp, size_t size, memgetfunc_t provider)
 Initializes an empty memory pool.
void * chPoolAllocI (MemoryPool *mp)
 Allocates an object from a memory pool.
void * chPoolAlloc (MemoryPool *mp)
 Allocates an object from a memory pool.
void chPoolFreeI (MemoryPool *mp, void *objp)
 Releases (or adds) an object into (to) a memory pool.
void chPoolFree (MemoryPool *mp, void *objp)
 Releases (or adds) an object into (to) a memory pool.
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#define _MEMORYPOOL_DATA( name,
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Data part of a static memory pool initializer.

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This macro should be used when statically initializing a memory pool that is part of a bigger structure.

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[in] name the name of the memory pool variable
[in] size size of the memory pool contained objects
[in] provider memory provider function for the memory pool
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Definition at line 68 of file chmempools.h.

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#define MEMORYPOOL_DECL( name,
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Static memory pool initializer in hungry mode.

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Statically initialized memory pools require no explicit initialization using chPoolInit().

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[in] name the name of the memory pool variable
[in] size size of the memory pool contained objects
[in] provider memory provider function for the memory pool or NULL if the pool is not allowed to grow automatically
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Definition at line 81 of file chmempools.h.

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Function Documentation

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void chPoolInit (MemoryPool *  mp,
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memgetfunc_t  provider 
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Initializes an empty memory pool.

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The size is internally aligned to be a multiple of the align_t type size.
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[out] mp pointer to a MemoryPool structure
[in] size the size of the objects contained in this memory pool, the minimum accepted size is the size of a pointer to void.
[in] provider memory provider function for the memory pool or NULL if the pool is not allowed to grow automatically
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Definition at line 58 of file chmempools.c.

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References chDbgCheck, MEM_ALIGN_SIZE, MemoryPool::mp_next, MemoryPool::mp_object_size, and MemoryPool::mp_provider.

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void * chPoolAllocI (MemoryPool *  mp ) 
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Allocates an object from a memory pool.

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The pointer to the allocated object.
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Definition at line 74 of file chmempools.c.

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References chDbgCheck, MemoryPool::mp_next, MemoryPool::mp_object_size, MemoryPool::mp_provider, and pool_header::ph_next.

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Referenced by chPoolAlloc().

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void * chPoolAlloc (MemoryPool *  mp ) 
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Allocates an object from a memory pool.

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The pointer to the allocated object.
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NULL if pool is empty.
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Definition at line 95 of file chmempools.c.

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References chPoolAllocI(), chSysLock, and chSysUnlock.

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Referenced by chThdCreateFromMemoryPool().

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void chPoolFreeI (MemoryPool *  mp,
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Releases (or adds) an object into (to) a memory pool.

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[in] objp the pointer to the object to be released or added
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Definition at line 114 of file chmempools.c.

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References chDbgCheck, MEM_IS_ALIGNED, MemoryPool::mp_next, and pool_header::ph_next.

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Referenced by chPoolFree().

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void chPoolFree (MemoryPool *  mp,
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Releases (or adds) an object into (to) a memory pool.

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[in] mp pointer to a MemoryPool structure
[in] objp the pointer to the object to be released or added
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Definition at line 132 of file chmempools.c.

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References chPoolFreeI(), chSysLock, and chSysUnlock.

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Referenced by chThdRelease().

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ChibiOS/RT LogoChibiOS/RT

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Ports

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Description

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This section describes the technical details of the various supported ChibiOS/RT ports.

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-Modules

 MegaAVR
 ARM7TDMI
 ARM Cortex-Mx
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 MSP430
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Registry
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Description

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Threads Registry related APIs and services.

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Operation mode

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The Threads Registry is a double linked list that holds all the active threads in the system.
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The registry is meant to be mainly a debug feature, as example, using the registry a debugger can enumerate the active threads in any given moment or the shell can print the active threads and their state.
- Another possible use is for centralized threads memory management, terminating threads can pulse an event source and an event handler can perform a scansion of the registry in order to recover the memory.
- In order to use the threads registry the CH_USE_REGISTRY option must be enabled in chconf.h.

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-Defines

#define REG_REMOVE(tp)
 Removes a thread from the registry list.
#define REG_INSERT(tp)
 Adds a thread to the registry list.

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Thread * chRegFirstThread (void)
 Returns the first thread in the system.
Thread * chRegNextThread (Thread *tp)
 Returns the thread next to the specified one.
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#define REG_REMOVE( tp ) 
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Removes a thread from the registry list.

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Returns the first thread in the system.

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Returns the most ancient thread in the system, usually this is the main thread unless it terminated.

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The reference counter of the specified thread is decremented and the reference counter of the returned thread is incremented.

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Definition at line 91 of file chregistry.c.

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Architecture - Reference Manual - Guides
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Scheduler
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This module provides the default portable scheduler code, scheduler functions can be individually captured by the port layer in order to provide architecture optimized equivalents. When a function is captured its default code is not built into the OS image, the optimized version is included instead.

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struct  ReadyList
 Ready list header. More...

-Defines

#define RDY_OK   0
 Default thread wakeup low level message.
#define RDY_TIMEOUT   -1
 Low level message sent to a thread awakened by a timeout.
#define RDY_RESET   -2
 Low level message sent to a thread awakened by a reset operation.
#define NOPRIO   0
 Ready list header priority.
#define IDLEPRIO   1
 Idle thread priority.
#define LOWPRIO   2
 Lowest user priority.
#define NORMALPRIO   64
 Normal user priority.
#define HIGHPRIO   127
 Highest user priority.
#define ABSPRIO   255
 Greatest possible priority.
#define TIME_IMMEDIATE   ((systime_t)-1)
 Zero time specification for some syscalls with a timeout specification.
#define TIME_INFINITE   ((systime_t)0)
 Infinite time specification for all the syscalls with a timeout specification.
#define firstprio(rlp)   ((rlp)->p_next->p_prio)
 Returns the priority of the first thread on the given ready list.
#define currp   rlist.r_current
 Current thread pointer access macro.
#define setcurrp(tp)   (currp = (tp))
 Current thread pointer change macro.
#define chSchIsRescRequiredI()   (firstprio(&rlist.r_queue) > currp->p_prio)
 Determines if the current thread must reschedule.
#define chSchCanYieldS()   (firstprio(&rlist.r_queue) >= currp->p_prio)
 Determines if yielding is possible.
#define chSchDoYieldS()
 Yields the time slot.

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void scheduler_init (void)
 Scheduler initialization.
Thread * chSchReadyI (Thread *tp)
 Inserts a thread in the Ready List.
void chSchGoSleepS (tstate_t newstate)
 Puts the current thread to sleep into the specified state.
msg_t chSchGoSleepTimeoutS (tstate_t newstate, systime_t time)
 Puts the current thread to sleep into the specified state with timeout specification.
void chSchWakeupS (Thread *ntp, msg_t msg)
 Wakes up a thread.
void chSchDoRescheduleI (void)
 Switches to the first thread on the runnable queue.
void chSchRescheduleS (void)
 Performs a reschedule if a higher priority thread is runnable.
bool_t chSchIsRescRequiredExI (void)
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Default thread wakeup low level message.

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Definition at line 39 of file chschd.h.

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Infinite time specification for all the syscalls with a timeout specification.

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Definition at line 64 of file chschd.h.

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Definition at line 69 of file chschd.h.

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Current thread pointer access macro.

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Definition at line 111 of file chschd.h.

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Referenced by chCondWaitTimeoutS(), chDbgTrace(), chEvtClear(), chEvtPend(), chMsgGet(), chMsgRelease(), chMsgWait(), chMtxTryLockS(), chSchDoRescheduleI(), chSchGoSleepS(), chSchGoSleepTimeoutS(), chSchIsRescRequiredExI(), chSchWakeupS(), chSemWaitS(), chSemWaitTimeoutS(), chSysInit(), chSysTimerHandlerI(), chThdSetPriority(), chThdWait(), and chibios_rt::BaseThread::IsPendingMessage().

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Definition at line 123 of file chschd.h.

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Definition at line 164 of file chschd.h.

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Yields the time slot.

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void scheduler_init (void  ) 
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Scheduler initialization.

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Definition at line 53 of file chschd.c.

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Definition at line 78 of file chschd.c.

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References Thread::p_next, Thread::p_state, and ReadyList::r_queue.

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Referenced by chCondBroadcastI(), chCondSignalI(), chEvtSignalI(), chMsgSend(), chMtxLockS(), chMtxUnlockAll(), chMtxUnlockS(), chSchDoRescheduleI(), chSchWakeupS(), chSemResetI(), chSemSignalI(), chSemSignalWait(), and chThdExit().

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Definition at line 103 of file chschd.c.

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References chDbgTrace(), chSysSwitchI, currp, fifo_remove(), ReadyList::r_queue, and setcurrp.

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Referenced by chCondWaitS(), chEvtWaitAll(), chEvtWaitAny(), chEvtWaitOne(), chMsgSend(), chMsgWait(), chMtxLockS(), chSchGoSleepTimeoutS(), chSemSignalWait(), chSemWaitS(), chThdExit(), and chThdWait().

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msg_t chSchGoSleepTimeoutS (tstate_t  newstate,
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The thread goes into a sleeping state, if it is not awakened explicitly within the specified timeout then it is forcibly awakened with a RDY_TIMEOUT low level message. The Threads States are described into threads.h.

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Definition at line 167 of file chschd.c.

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Definition at line 197 of file chschd.c.

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Definition at line 225 of file chschd.c.

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Definition at line 247 of file chschd.c.

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References chSchDoRescheduleI(), and chSchIsRescRequiredI.

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Referenced by adcStopConversion(), canSleep(), canStop(), canWakeup(), chCondBroadcast(), chEvtBroadcast(), chEvtSignal(), chMBFetchS(), chMBPostAheadS(), chMBPostS(), chMBReset(), chMtxUnlockAll(), chSemReset(), chSemSignalWait(), chThdSetPriority(), and sdStop().

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bool_t chSchIsRescRequiredExI (void  ) 
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Evaluates if a reschedule is required.

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Definition at line 265 of file chschd.c.

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Variable Documentation

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ReadyList rlist
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Ready list header.

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Definition at line 46 of file chschd.c.

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Referenced by chRegFirstThread(), chRegNextThread(), and chSysTimerHandlerI().

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions
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Semaphores
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Description

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Semaphores related APIs and services.

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Operation mode

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Semaphores are a flexible synchronization primitive, ChibiOS/RT implements semaphores in their "counting semaphores" variant as defined by Edsger Dijkstra plus several enhancements like:

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  • Return message from the wait operation (OK, RESET, TIMEOUT).
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The binary semaphores variant can be easily implemented using counting semaphores.
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  • Signal: The semaphore counter is increased and if the result is non-positive then a waiting thread is removed from the semaphore queue and made ready for execution.
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  • Wait: The semaphore counter is decreased and if the result becomes negative the thread is queued in the semaphore and suspended.
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  • Reset: The semaphore counter is reset to a non-negative value and all the threads in the queue are released.
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Semaphores can be used as guards for mutual exclusion zones (note that mutexes are recommended for this kind of use) but also have other uses, queues guards and counters as example.
- Semaphores usually use a FIFO queuing strategy but it is possible to make them order threads by priority by enabling CH_USE_SEMAPHORES_PRIORITY in chconf.h.
- In order to use the Semaphores APIs the CH_USE_SEMAPHORES option must be enabled in chconf.h.

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-Data Structures

struct  Semaphore
 Semaphore structure. More...

-Defines

#define _SEMAPHORE_DATA(name, n)   {_THREADSQUEUE_DATA(name.s_queue), n}
 Data part of a static semaphore initializer.
#define SEMAPHORE_DECL(name, n)   Semaphore name = _SEMAPHORE_DATA(name, n)
 Static semaphore initializer.
#define chSemFastWaitI(sp)   ((sp)->s_cnt--)
 Decreases the semaphore counter.
#define chSemFastSignalI(sp)   ((sp)->s_cnt++)
 Increases the semaphore counter.
#define chSemGetCounterI(sp)   ((sp)->s_cnt)
 Returns the semaphore counter current value.

-Typedefs

typedef struct Semaphore Semaphore
 Semaphore structure.

-Functions

void chSemInit (Semaphore *sp, cnt_t n)
 Initializes a semaphore with the specified counter value.
void chSemReset (Semaphore *sp, cnt_t n)
 Performs a reset operation on the semaphore.
void chSemResetI (Semaphore *sp, cnt_t n)
 Performs a reset operation on the semaphore.
msg_t chSemWait (Semaphore *sp)
 Performs a wait operation on a semaphore.
msg_t chSemWaitS (Semaphore *sp)
 Performs a wait operation on a semaphore.
msg_t chSemWaitTimeout (Semaphore *sp, systime_t time)
 Performs a wait operation on a semaphore with timeout specification.
msg_t chSemWaitTimeoutS (Semaphore *sp, systime_t time)
 Performs a wait operation on a semaphore with timeout specification.
void chSemSignal (Semaphore *sp)
 Performs a signal operation on a semaphore.
void chSemSignalI (Semaphore *sp)
 Performs a signal operation on a semaphore.
msg_t chSemSignalWait (Semaphore *sps, Semaphore *spw)
 Performs atomic signal and wait operations on two semaphores.
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Define Documentation

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#define _SEMAPHORE_DATA( name,
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Data part of a static semaphore initializer.

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This macro should be used when statically initializing a semaphore that is part of a bigger structure.

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Definition at line 77 of file chsem.h.

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#define SEMAPHORE_DECL( name,
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Static semaphore initializer.

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Statically initialized semaphores require no explicit initialization using chSemInit().

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Definition at line 88 of file chsem.h.

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#define chSemFastWaitI( sp )    ((sp)->s_cnt--)
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Decreases the semaphore counter.

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Definition at line 94 of file chsem.h.

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Referenced by chIQReadTimeout(), and chOQWriteTimeout().

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#define chSemFastSignalI( sp )    ((sp)->s_cnt++)
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Increases the semaphore counter.

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Definition at line 100 of file chsem.h.

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Definition at line 105 of file chsem.h.

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typedef struct Semaphore Semaphore
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Semaphore structure.

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Function Documentation

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void chSemInit (Semaphore *  sp,
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Initializes a semaphore with the specified counter value.

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[in] n initial value of the semaphore counter. Must be non-negative.
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Definition at line 83 of file chsem.c.

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References chDbgCheck, queue_init, Semaphore::s_cnt, and Semaphore::s_queue.

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Referenced by adcObjectInit(), canObjectInit(), chHeapInit(), chIQInit(), chMBInit(), chOQInit(), heap_init(), macObjectInit(), chibios_rt::Semaphore::Semaphore(), and spiObjectInit().

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void chSemReset (Semaphore *  sp,
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Performs a reset operation on the semaphore.

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[in] sp pointer to a Semaphore structure
[in] n the new value of the semaphore counter. The value must be non-negative.
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Definition at line 101 of file chsem.c.

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References chSchRescheduleS(), chSemResetI(), chSysLock, and chSysUnlock.

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Referenced by chibios_rt::Semaphore::Reset().

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void chSemResetI (Semaphore *  sp,
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Performs a reset operation on the semaphore.

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[in] sp pointer to a Semaphore structure
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Definition at line 120 of file chsem.c.

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References chDbgCheck, chSchReadyI(), lifo_remove(), Thread::p_u, Thread::rdymsg, Semaphore::s_cnt, and Semaphore::s_queue.

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Referenced by adcStopConversion(), canStop(), CH_IRQ_HANDLER(), chIQResetI(), chMBReset(), chOQResetI(), and chSemReset().

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msg_t chSemWait (Semaphore *  sp ) 
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Performs a wait operation on a semaphore.

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RDY_RESET if the semaphore was reset using chSemReset().
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Definition at line 138 of file chsem.c.

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References chSemWaitS(), chSysLock, and chSysUnlock.

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Referenced by spiAcquireBus(), and chibios_rt::Semaphore::Wait().

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msg_t chSemWaitS (Semaphore *  sp ) 
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RDY_RESET if the semaphore was reset using chSemReset().
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Definition at line 154 of file chsem.c.

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References chDbgCheck, chSchGoSleepS(), currp, Semaphore::s_cnt, Semaphore::s_queue, and THD_STATE_WTSEM.

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Referenced by chSemWait().

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msg_t chSemWaitTimeout (Semaphore *  sp,
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[in] time the number of ticks before the operation timeouts, the following special values are allowed:

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RDY_RESET if the semaphore was reset using chSemReset().
RDY_TIMEOUT if the semaphore was not signaled or reset within the specified timeout.
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Definition at line 181 of file chsem.c.

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References chSemWaitTimeoutS(), chSysLock, and chSysUnlock.

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Referenced by chibios_rt::Semaphore::WaitTimeout().

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Referenced by adcWaitConversion(), canReceive(), canTransmit(), chIQGetTimeout(), chIQReadTimeout(), chMBFetchS(), chMBPostAheadS(), chMBPostS(), chOQPutTimeout(), chOQWriteTimeout(), chSemWaitTimeout(), macWaitReceiveDescriptor(), and macWaitTransmitDescriptor().

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Definition at line 265 of file chsem.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Synchronization services.

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 Semaphores
 Mutexes
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ChibiOS/RT LogoChibiOS/RT

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System Management
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System related APIs and services:

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#define chSysHalt()   port_halt()
 Halts the system.
#define chSysSwitchI(ntp, otp)   port_switch(ntp, otp)
 Performs a context switch.
#define chSysDisable()   port_disable()
 Raises the system interrupt priority mask to the maximum level.
#define chSysSuspend()   port_suspend()
 Raises the system interrupt priority mask to system level.
#define chSysEnable()   port_enable()
 Lowers the system interrupt priority mask to user level.
#define chSysLock()
 Enters the kernel lock mode.
#define chSysUnlock()
 Leaves the kernel lock mode.
#define chSysLockFromIsr()   port_lock_from_isr()
 Enters the kernel lock mode from within an interrupt handler.
#define chSysUnlockFromIsr()   port_unlock_from_isr()
 Leaves the kernel lock mode from within an interrupt handler.
#define CH_IRQ_PROLOGUE()   PORT_IRQ_PROLOGUE()
 IRQ handler enter code.
#define CH_IRQ_EPILOGUE()   PORT_IRQ_EPILOGUE()
 IRQ handler exit code.
#define CH_IRQ_HANDLER(id)   PORT_IRQ_HANDLER(id)
 Standard normal IRQ handler declaration.
#define CH_FAST_IRQ_HANDLER(id)   PORT_FAST_IRQ_HANDLER(id)
 Standard fast IRQ handler declaration.

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void chSysInit (void)
 ChibiOS/RT initialization.
void chSysTimerHandlerI (void)
 Handles time ticks for round robin preemption and timer increments.
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Define Documentation

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#define chSysHalt( )    port_halt()
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Halts the system.

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This function is invoked by the operating system when an unrecoverable error is detected, as example because a programming error in the application code that triggers an assertion while in debug mode.

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Definition at line 45 of file chsys.h.

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Definition at line 53 of file chsys.h.

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Definition at line 63 of file chsys.h.

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Definition at line 76 of file chsys.h.

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Definition at line 87 of file chsys.h.

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Enters the kernel lock mode.

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Definition at line 97 of file chsys.h.

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Referenced by adcStart(), adcStartConversion(), adcStop(), adcStopConversion(), adcWaitConversion(), canGetAndClearFlags(), canReceive(), canSleep(), canStart(), canStop(), canTransmit(), canWakeup(), chCondBroadcast(), chCondSignal(), chCondWait(), chCondWaitTimeout(), chCoreAlloc(), chEvtBroadcast(), chEvtClear(), chEvtPend(), chEvtRegisterMask(), chEvtSignal(), chEvtUnregister(), chEvtWaitAll(), chEvtWaitAllTimeout(), chEvtWaitAny(), chEvtWaitAnyTimeout(), chEvtWaitOne(), chEvtWaitOneTimeout(), chIQGetTimeout(), chIQReadTimeout(), chMBFetch(), chMBPost(), chMBPostAhead(), chMBReset(), chMsgGet(), chMsgRelease(), chMsgSend(), chMsgWait(), chMtxLock(), chMtxTryLock(), chMtxUnlock(), chMtxUnlockAll(), chOQPutTimeout(), chOQWriteTimeout(), chPoolAlloc(), chPoolFree(), chRegFirstThread(), chRegNextThread(), chSemReset(), chSemSignal(), chSemSignalWait(), chSemWait(), chSemWaitTimeout(), chThdAddRef(), chThdCreateFromHeap(), chThdCreateFromMemoryPool(), chThdCreateStatic(), chThdExit(), chThdRelease(), chThdResume(), chThdSetPriority(), chThdSleep(), chThdSleepUntil(), chThdTerminate(), chThdWait(), chThdYield(), chibios_rt::System::Lock(), macWaitReceiveDescriptor(), macWaitTransmitDescriptor(), mmcConnect(), mmcDisconnect(), mmcSequentialRead(), mmcSequentialWrite(), mmcStart(), mmcStartSequentialRead(), mmcStartSequentialWrite(), mmcStop(), mmcStopSequentialRead(), mmcStopSequentialWrite(), pwmDisableChannel(), pwmEnableChannel(), pwmStart(), pwmStop(), sdGetAndClearFlags(), sdStart(), sdStop(), spiSelect(), spiStart(), spiStop(), and spiUnselect().

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Leaves the kernel lock mode.

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Definition at line 114 of file chsys.h.

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Referenced by adcStart(), adcStartConversion(), adcStop(), adcStopConversion(), adcWaitConversion(), canGetAndClearFlags(), canReceive(), canSleep(), canStart(), canStop(), canTransmit(), canWakeup(), chCondBroadcast(), chCondSignal(), chCondWait(), chCondWaitTimeout(), chCoreAlloc(), chEvtBroadcast(), chEvtClear(), chEvtPend(), chEvtRegisterMask(), chEvtSignal(), chEvtUnregister(), chEvtWaitAll(), chEvtWaitAllTimeout(), chEvtWaitAny(), chEvtWaitAnyTimeout(), chEvtWaitOne(), chEvtWaitOneTimeout(), chIQGetTimeout(), chIQReadTimeout(), chMBFetch(), chMBPost(), chMBPostAhead(), chMBReset(), chMsgGet(), chMsgRelease(), chMsgSend(), chMsgWait(), chMtxLock(), chMtxTryLock(), chMtxUnlock(), chMtxUnlockAll(), chOQPutTimeout(), chOQWriteTimeout(), chPoolAlloc(), chPoolFree(), chRegFirstThread(), chRegNextThread(), chSemReset(), chSemSignal(), chSemSignalWait(), chSemWait(), chSemWaitTimeout(), chThdAddRef(), chThdCreateFromHeap(), chThdCreateFromMemoryPool(), chThdCreateStatic(), chThdRelease(), chThdResume(), chThdSetPriority(), chThdSleep(), chThdSleepUntil(), chThdTerminate(), chThdWait(), chThdYield(), macWaitReceiveDescriptor(), macWaitTransmitDescriptor(), mmcConnect(), mmcDisconnect(), mmcSequentialRead(), mmcSequentialWrite(), mmcStart(), mmcStartSequentialRead(), mmcStartSequentialWrite(), mmcStop(), mmcStopSequentialRead(), mmcStopSequentialWrite(), pwmDisableChannel(), pwmEnableChannel(), pwmStart(), pwmStop(), sdGetAndClearFlags(), sdStart(), sdStop(), spiSelect(), spiStart(), spiStop(), spiUnselect(), and chibios_rt::System::Unlock().

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#define chSysLockFromIsr( )    port_lock_from_isr()
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Definition at line 133 of file chsys.h.

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Definition at line 146 of file chsys.h.

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Definition at line 153 of file chsys.h.

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Definition at line 161 of file chsys.h.

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Definition at line 168 of file chsys.h.

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Definition at line 176 of file chsys.h.

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ChibiOS/RT initialization.

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Definition at line 73 of file chsys.c.

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Decrements the remaining time quantum of the running thread and preempts it when the quantum is used up. Increments system time and manages the timers.

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Definition at line 111 of file chsys.c.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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Test Runtime

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Description

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Runtime code for the test suite execution, this code is not part of the OS and should not be included in user applications.

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-Data Structures

struct  testcase
 Structure representing a test case. More...

-Defines

#define DELAY_BETWEEN_TESTS   200
 Delay inserted between test cases.
#define TEST_NO_BENCHMARKS   FALSE
 If TRUE then benchmarks are not included.
#define test_fail(point)
 Test failure enforcement.
#define test_assert(point, condition, msg)
 Test assertion.
#define test_assert_sequence(point, expected)
 Test sequence assertion.
#define test_assert_time_window(point, start, end)
 Test time window assertion.

-Functions

void test_printn (uint32_t n)
 Prints a decimal unsigned number.
void test_print (char *msgp)
 Prints a line without final end-of-line.
void test_println (char *msgp)
 Prints a line.
void test_emit_token (char token)
 Emits a token into the tokens buffer.
void test_terminate_threads (void)
 Pends a termination request in all the test-spawned threads.
void test_wait_threads (void)
 Waits for the completion of all the test-spawned threads.
void test_cpu_pulse (unsigned duration)
 CPU pulse.
systime_t test_wait_tick (void)
 Delays execution until next system time tick.
void test_start_timer (unsigned ms)
 Starts the test timer.
msg_t TestThread (void *p)
 Test execution thread function.

-Variables

bool_t test_timer_done
 Set to TRUE when the test timer reaches its deadline.
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Define Documentation

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#define DELAY_BETWEEN_TESTS   200
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Delay inserted between test cases.

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Definition at line 42 of file test.h.

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#define TEST_NO_BENCHMARKS   FALSE
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If TRUE then benchmarks are not included.

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Definition at line 49 of file test.h.

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#define test_fail( point ) 
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Test failure enforcement.

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Definition at line 118 of file test.h.

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#define test_assert( point,
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Test assertion.

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[in] point numeric assertion identifier
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[in] msg failure message
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Definition at line 130 of file test.h.

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#define test_assert_sequence( point,
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Test sequence assertion.

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[in] expected string to be matched with the tokens buffer
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Definition at line 141 of file test.h.

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#define test_assert_time_window( point,
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Test time window assertion.

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[in] point numeric assertion identifier
[in] start initial time in the window (included)
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Definition at line 153 of file test.h.

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Function Documentation

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void test_printn (uint32_t  n ) 
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Prints a decimal unsigned number.

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void test_print (char *  msgp ) 
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Prints a line without final end-of-line.

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Pends a termination request in all the test-spawned threads.

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Waits for the completion of all the test-spawned threads.

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void test_cpu_pulse (unsigned  duration ) 
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CPU pulse.

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systime_t test_wait_tick (void  ) 
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Delays execution until next system time tick.

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Starts the test timer.

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msg_t TestThread (void *  p ) 
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Test execution thread function.

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Variable Documentation

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bool_t test_timer_done
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Set to TRUE when the test timer reaches its deadline.

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Definition at line 265 of file test.c.

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-Generated on Sun Nov 28 2010 14:09:59 for ChibiOS/RT by doxygen 1.7.1
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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions
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Threads
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-Collaboration diagram for Threads:
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Description

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Threads related APIs and services.

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Operation mode

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A thread is an abstraction of an independent instructions flow. In ChibiOS/RT a thread is represented by a "C" function owning a processor context, state informations and a dedicated stack area. In this scenario static variables are shared among all threads while automatic variables are local to the thread.
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The threads subsystem is implicitly included in kernel however some of its part may be excluded by disabling them in chconf.h, see the CH_USE_WAITEXIT and CH_USE_DYNAMIC configuration options.

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-Data Structures

struct  Thread
 Structure representing a thread. More...

-Defines

#define THD_STATE_READY   0
 Thread state: Ready to run, waiting on the ready list.
#define THD_STATE_CURRENT   1
 Thread state: Currently running.
#define THD_STATE_SUSPENDED   2
 Thread state: Thread created in suspended state.
#define THD_STATE_WTSEM   3
 Thread state: Waiting on a semaphore.
#define THD_STATE_WTMTX   4
 Thread state: Waiting on a mutex.
#define THD_STATE_WTCOND   5
 Thread state: Waiting in chCondWait().
#define THD_STATE_SLEEPING   6
 Thread state: Waiting in chThdSleep() or chThdSleepUntil().
#define THD_STATE_WTEXIT   7
 Thread state: Waiting in chThdWait().
#define THD_STATE_WTOREVT   8
 Thread state: Waiting in chEvtWaitXXX().
#define THD_STATE_WTANDEVT   9
 Thread state: Waiting in chEvtWaitAllTimeout().
#define THD_STATE_SNDMSG   10
 Thread state: Waiting in chMsgSend().
#define THD_STATE_WTMSG   11
 Thread state: Waiting in chMsgWait().
#define THD_STATE_FINAL   12
 Thread state: After termination.
#define THD_MEM_MODE_MASK   3
 Thread memory mode mask.
#define THD_MEM_MODE_STATIC   0
 Thread memory mode: static.
#define THD_MEM_MODE_HEAP   1
 Thread memory mode: heap.
#define THD_MEM_MODE_MEMPOOL   2
 Thread memory mode: pool.
#define THD_TERMINATE   4
 Termination requested.
#define chThdSelf()   currp
 Returns a pointer to the current Thread.
#define chThdGetPriority()   (currp->p_prio)
 Returns the current thread priority.
#define chThdLS()   (void *)(currp + 1)
 Returns the pointer to the Thread local storage area, if any.
#define chThdTerminated(tp)   ((tp)->p_state == THD_STATE_FINAL)
 Verifies if the specified thread is in the THD_STATE_FINAL state.
#define chThdShouldTerminate()   (currp->p_flags & THD_TERMINATE)
 Verifies if the current thread has a termination request pending.
#define chThdResumeI(tp)   chSchReadyI(tp)
 Resumes a thread created with chThdInit().
#define chThdSleepS(time)   chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time)
 Suspends the invoking thread for the specified time.
#define chThdSleepSeconds(sec)   chThdSleep(S2ST(sec))
 Delays the invoking thread for the specified number of seconds.
#define chThdSleepMilliseconds(msec)   chThdSleep(MS2ST(msec))
 Delays the invoking thread for the specified number of milliseconds.
#define chThdSleepMicroseconds(usec)   chThdSleep(US2ST(usec))
 Delays the invoking thread for the specified number of microseconds.

-Typedefs

typedef msg_t(* tfunc_t )(void *)
 Thread function.

-Functions

Thread * init_thread (Thread *tp, tprio_t prio)
 Initializes a thread structure.
Thread * chThdCreateI (void *wsp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread into a static memory area.
Thread * chThdCreateStatic (void *wsp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread into a static memory area.
Thread * chThdCreateFromHeap (MemoryHeap *heapp, size_t size, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread allocating the memory from the heap.
Thread * chThdCreateFromMemoryPool (MemoryPool *mp, tprio_t prio, tfunc_t pf, void *arg)
 Creates a new thread allocating the memory from the specified memory pool.
tprio_t chThdSetPriority (tprio_t newprio)
 Changes the running thread priority level then reschedules if necessary.
Thread * chThdResume (Thread *tp)
 Resumes a suspended thread.
void chThdTerminate (Thread *tp)
 Requests a thread termination.
void chThdSleep (systime_t time)
 Suspends the invoking thread for the specified time.
void chThdSleepUntil (systime_t time)
 Suspends the invoking thread until the system time arrives to the specified value.
void chThdYield (void)
 Yields the time slot.
void chThdExit (msg_t msg)
 Terminates the current thread by specifying an exit status code.
Thread * chThdAddRef (Thread *tp)
 Adds a reference to a thread object.
void chThdRelease (Thread *tp)
 Releases a reference to a thread object.
msg_t chThdWait (Thread *tp)
 Blocks the execution of the invoking thread until the specified thread terminates then the exit code is returned.
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Define Documentation

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#define THD_STATE_READY   0
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Thread state: Ready to run, waiting on the ready list.

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Definition at line 175 of file chthreads.h.

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Thread state: Currently running.

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Definition at line 177 of file chthreads.h.

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Thread state: Thread created in suspended state.

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Definition at line 179 of file chthreads.h.

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Referenced by chThdResume().

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Thread state: Waiting on a semaphore.

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Definition at line 181 of file chthreads.h.

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Referenced by chMtxLockS(), chSemSignalWait(), chSemWaitS(), and chSemWaitTimeoutS().

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Thread state: Waiting on a mutex.

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Definition at line 183 of file chthreads.h.

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Referenced by chMtxLockS().

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Thread state: Waiting in chCondWait().

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Definition at line 185 of file chthreads.h.

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Thread state: Waiting in chThdSleep() or chThdSleepUntil().

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Definition at line 187 of file chthreads.h.

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Thread state: Waiting in chThdWait().

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Definition at line 189 of file chthreads.h.

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Thread state: Waiting in chEvtWaitXXX().

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Definition at line 191 of file chthreads.h.

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Thread state: Waiting in chEvtWaitAllTimeout().

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Definition at line 193 of file chthreads.h.

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Thread state: Waiting in chMsgSend().

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Definition at line 195 of file chthreads.h.

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Thread state: Waiting in chMsgWait().

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Definition at line 197 of file chthreads.h.

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Thread state: After termination.

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Definition at line 199 of file chthreads.h.

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Thread memory mode mask.

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Definition at line 204 of file chthreads.h.

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Thread memory mode: static.

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Definition at line 205 of file chthreads.h.

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Thread memory mode: heap.

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Definition at line 206 of file chthreads.h.

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Thread memory mode: pool.

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Definition at line 207 of file chthreads.h.

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Termination requested.

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Definition at line 208 of file chthreads.h.

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Returns a pointer to the current Thread.

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Definition at line 253 of file chthreads.h.

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Returns the current thread priority.

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Definition at line 258 of file chthreads.h.

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Definition at line 263 of file chthreads.h.

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Verifies if the specified thread is in the THD_STATE_FINAL state.

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Definition at line 272 of file chthreads.h.

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Definition at line 280 of file chthreads.h.

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Definition at line 287 of file chthreads.h.

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Definition at line 301 of file chthreads.h.

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Definition at line 311 of file chthreads.h.

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Definition at line 322 of file chthreads.h.

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Definition at line 333 of file chthreads.h.

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Definition at line 211 of file chthreads.h.

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Thread * init_thread (Thread *  tp,
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Definition at line 74 of file chthreads.c.

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References list_init, Thread::p_epending, Thread::p_flags, Thread::p_msgqueue, Thread::p_mtxlist, Thread::p_prio, Thread::p_realprio, Thread::p_refs, Thread::p_state, Thread::p_time, Thread::p_waiting, queue_init, REG_INSERT, and THREAD_EXT_INIT.

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Thread * chThdCreateI (void *  wsp,
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Creates a new thread into a static memory area.

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The new thread is initialized but not inserted in the ready list, the initial state is THD_STATE_SUSPENDED.

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[out] wsp pointer to a working area dedicated to the thread stack
[in] size size of the working area
[in] prio the priority level for the new thread
[in] pf the thread function
[in] arg an argument passed to the thread function. It can be NULL.
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The pointer to the Thread structure allocated for the thread into the working space area.
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Definition at line 137 of file chthreads.c.

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References chDbgCheck, HIGHPRIO, init_thread(), SETUP_CONTEXT, and THD_WA_SIZE.

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Referenced by chThdCreateFromHeap(), chThdCreateFromMemoryPool(), and chThdCreateStatic().

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Thread * chThdCreateStatic (void *  wsp,
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Creates a new thread into a static memory area.

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A thread can terminate by calling chThdExit() or by simply returning from its main function.
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[out] wsp pointer to a working area dedicated to the thread stack
[in] size size of the working area
[in] prio the priority level for the new thread
[in] pf the thread function
[in] arg an argument passed to the thread function. It can be NULL.
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The pointer to the Thread structure allocated for the thread into the working space area.
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Definition at line 163 of file chthreads.c.

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References chSchWakeupS(), chSysLock, chSysUnlock, chThdCreateI(), RDY_OK, STACK_FILL_VALUE, and THREAD_FILL_VALUE.

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Referenced by chibios_rt::BaseThread::BaseThread(), and chSysInit().

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Thread * chThdCreateFromHeap (MemoryHeap *  heapp,
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void *  arg 
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Creates a new thread allocating the memory from the heap.

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A thread can terminate by calling chThdExit() or by simply returning from its main function.
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[in] heapp heap from which allocate the memory or NULL for the default heap
[in] size size of the working area to be allocated
[in] prio the priority level for the new thread
[in] pf the thread function
[in] arg an argument passed to the thread function. It can be NULL.
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The pointer to the Thread structure allocated for the thread into the working space area.
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Definition at line 200 of file chthreads.c.

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References chHeapAlloc(), chSchWakeupS(), chSysLock, chSysUnlock, chThdCreateI(), Thread::p_flags, RDY_OK, STACK_FILL_VALUE, and THREAD_FILL_VALUE.

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Thread * chThdCreateFromMemoryPool (MemoryPool *  mp,
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void *  arg 
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Creates a new thread allocating the memory from the specified memory pool.

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A thread can terminate by calling chThdExit() or by simply returning from its main function.
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[in] mp pointer to the memory pool object
[in] prio the priority level for the new thread
[in] pf the thread function
[in] arg an argument passed to the thread function. It can be NULL.
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The pointer to the Thread structure allocated for the thread into the working space area.
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Definition at line 245 of file chthreads.c.

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References chDbgCheck, chPoolAlloc(), chSchWakeupS(), chSysLock, chSysUnlock, chThdCreateI(), MemoryPool::mp_object_size, Thread::p_flags, Thread::p_mpool, RDY_OK, STACK_FILL_VALUE, and THREAD_FILL_VALUE.

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tprio_t chThdSetPriority (tprio_t  newprio ) 
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Changes the running thread priority level then reschedules if necessary.

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[in] newprio the new priority level of the running thread
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The old priority level.
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Definition at line 282 of file chthreads.c.

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References chDbgCheck, chSchRescheduleS(), chSysLock, chSysUnlock, currp, HIGHPRIO, and LOWPRIO.

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Referenced by chibios_rt::BaseThread::SetPriority().

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Thread * chThdResume (Thread *  tp ) 
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Resumes a suspended thread.

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Definition at line 310 of file chthreads.c.

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References chDbgAssert, chSchWakeupS(), chSysLock, chSysUnlock, Thread::p_state, RDY_OK, and THD_STATE_SUSPENDED.

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Referenced by chibios_rt::BaseThread::Resume().

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void chThdTerminate (Thread *  tp ) 
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Requests a thread termination.

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Definition at line 329 of file chthreads.c.

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References chSysLock, chSysUnlock, and Thread::p_flags.

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Referenced by chibios_rt::BaseThread::Terminate().

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Suspends the invoking thread for the specified time.

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Definition at line 348 of file chthreads.c.

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References chDbgCheck, chSysLock, chSysUnlock, chThdSleepS, and TIME_INFINITE.

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Referenced by chibios_rt::BaseThread::Sleep().

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Suspends the invoking thread until the system time arrives to the specified value.

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Definition at line 363 of file chthreads.c.

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References chSysLock, chSysUnlock, chThdSleepS, and chTimeNow.

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Referenced by chibios_rt::BaseThread::SleepUntil().

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Yields the time slot.

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Yields the CPU control to the next thread in the ready list with equal priority, if any.

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Definition at line 376 of file chthreads.c.

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Terminates the current thread by specifying an exit status code.

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[in] msg thread exit code. The code can be retrieved by using chThdWait().
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Definition at line 389 of file chthreads.c.

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References chSchGoSleepS(), chSchReadyI(), chSysLock, Thread::exitcode, list_remove(), notempty, Thread::p_flags, Thread::p_u, Thread::p_waiting, REG_REMOVE, THD_MEM_MODE_MASK, THD_MEM_MODE_STATIC, THD_STATE_FINAL, and THREAD_EXT_EXIT.

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Thread * chThdAddRef (Thread *  tp ) 
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Adds a reference to a thread object.

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Definition at line 418 of file chthreads.c.

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void chThdRelease (Thread *  tp ) 
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Releases a reference to a thread object.

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If the references counter reaches zero and the thread is in the THD_STATE_FINAL state then the thread's memory is returned to the proper allocator.

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Definition at line 436 of file chthreads.c.

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References chDbgAssert, chHeapFree(), chPoolFree(), chSysLock, chSysUnlock, Thread::p_flags, Thread::p_mpool, Thread::p_refs, Thread::p_state, REG_REMOVE, THD_MEM_MODE_HEAP, THD_MEM_MODE_MASK, THD_MEM_MODE_MEMPOOL, and THD_STATE_FINAL.

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msg_t chThdWait (Thread *  tp ) 
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Blocks the execution of the invoking thread until the specified thread terminates then the exit code is returned.

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Definition at line 499 of file chthreads.c.

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References chDbgAssert, chDbgCheck, chSchGoSleepS(), chSysLock, chSysUnlock, chThdRelease(), currp, Thread::exitcode, list_insert(), Thread::p_refs, Thread::p_state, Thread::p_u, Thread::p_waiting, THD_STATE_FINAL, and THD_STATE_WTEXIT.

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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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-Data Structures | -Defines | -Typedefs | -Functions | -Variables
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Time and Virtual Timers
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Description

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Time and Virtual Timers related APIs and services.

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-Data Structures

struct  VirtualTimer
 Virtual Timer descriptor structure. More...
struct  VTList
 Virtual timers list header. More...

-Defines

#define S2ST(sec)   ((systime_t)((sec) * CH_FREQUENCY))
 Time conversion utility.
#define MS2ST(msec)   ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L))
 Time conversion utility.
#define US2ST(usec)   ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L))
 Time conversion utility.
#define chVTDoTickI()
 Virtual timers ticker.
#define chVTIsArmedI(vtp)   ((vtp)->vt_func != NULL)
 Returns TRUE if the speciified timer is armed.
#define chTimeNow()   (vtlist.vt_systime)
 Current system time.

-Typedefs

typedef void(* vtfunc_t )(void *)
 Virtual Timer callback function.
typedef struct VirtualTimer VirtualTimer
 Virtual Timer structure type.

-Functions

void vt_init (void)
 Virtual Timers initialization.
void chVTSetI (VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par)
 Enables a virtual timer.
void chVTResetI (VirtualTimer *vtp)
 Disables a Virtual Timer.
bool_t chTimeIsWithin (systime_t start, systime_t end)
 Checks if the current system time is within the specified time window.

-Variables

VTList vtlist
 Virtual timers delta list header.
VTList vtlist
 Virtual timers delta list header.
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Define Documentation

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#define S2ST( sec )    ((systime_t)((sec) * CH_FREQUENCY))
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Time conversion utility.

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Converts from seconds to system ticks number.

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Definition at line 43 of file chvt.h.

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#define MS2ST( msec )    ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L))
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Time conversion utility.

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Converts from milliseconds to system ticks number.

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Definition at line 50 of file chvt.h.

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Referenced by mmcStart(), and tmrfunc().

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#define US2ST( usec )    ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L))
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Time conversion utility.

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Converts from microseconds to system ticks number.

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Definition at line 57 of file chvt.h.

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#define chVTDoTickI( ) 
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{                                                 \
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-  if (&vtlist != (VTList *)vtlist.vt_next) {                            \
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-    --vtlist.vt_next->vt_time;                                          \
-    while (!(vtp = vtlist.vt_next)->vt_time) {                          \
-      vtfunc_t fn = vtp->vt_func;                                       \
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-      vtp->vt_next->vt_prev = (void *)&vtlist;                          \
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-      fn(vtp->vt_par);                                                  \
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Virtual timers ticker.

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Definition at line 106 of file chvt.h.

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Referenced by chSysTimerHandlerI().

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#define chVTIsArmedI( vtp )    ((vtp)->vt_func != NULL)
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Definition at line 139 of file chvt.h.

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Referenced by chSchGoSleepTimeoutS(), and chibios_rt::Timer::IsArmed().

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#define chTimeNow( )    (vtlist.vt_systime)
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Current system time.

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Returns the number of system ticks since the chSysInit() invocation.

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Definition at line 150 of file chvt.h.

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Referenced by chDbgTrace(), chThdSleepUntil(), chTimeIsWithin(), chibios_rt::System::GetTime(), macWaitReceiveDescriptor(), and macWaitTransmitDescriptor().

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Typedef Documentation

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typedef void(* vtfunc_t)(void *)
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Virtual Timer callback function.

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Definition at line 62 of file chvt.h.

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typedef struct VirtualTimer VirtualTimer
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Virtual Timer structure type.

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Definition at line 67 of file chvt.h.

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Function Documentation

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void vt_init (void  ) 
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Virtual Timers initialization.

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Definition at line 47 of file chvt.c.

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References VTList::vt_next, VTList::vt_prev, VTList::vt_systime, and VTList::vt_time.

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Referenced by chSysInit().

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void chVTSetI (VirtualTimer *  vtp,
systime_t  time,
vtfunc_t  vtfunc,
void *  par 
)
-
-
- -

Enables a virtual timer.

-
Note:
The associated function is invoked by an interrupt handler within the I-Locked state, see System States.
-
Parameters:
- - - - - -
[out] vtp the VirtualTimer structure pointer
[in] time the number of time ticks, the value TIME_INFINITE is notallowed. The value TIME_IMMEDIATE is allowed but interpreted as a normal time specification not as an immediate timeout specification.
[in] vtfunc the timer callback function. After invoking the callback the timer is disabled and the structure can be disposed or reused.
[in] par a parameter that will be passed to the callback function
-
-
- -

Definition at line 70 of file chvt.c.

- -

References chDbgCheck, TIME_INFINITE, VirtualTimer::vt_func, VirtualTimer::vt_next, VTList::vt_next, VirtualTimer::vt_par, VirtualTimer::vt_prev, and VirtualTimer::vt_time.

- -

Referenced by chSchGoSleepTimeoutS(), mmcStart(), chibios_rt::Timer::Set(), and tmrfunc().

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void chVTResetI (VirtualTimer *  vtp ) 
-
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Disables a Virtual Timer.

-
Note:
The timer MUST be active when this function is invoked.
-
Parameters:
- - -
[in] vtp the VirtualTimer structure pointer
-
-
- -

Definition at line 97 of file chvt.c.

- -

References chDbgAssert, chDbgCheck, VirtualTimer::vt_func, VirtualTimer::vt_next, VirtualTimer::vt_prev, and VirtualTimer::vt_time.

- -

Referenced by chSchGoSleepTimeoutS(), mmcStop(), and chibios_rt::Timer::Reset().

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bool_t chTimeIsWithin (systime_t  start,
systime_t  end 
)
-
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Checks if the current system time is within the specified time window.

-
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When start==end then the function returns always true because the whole time range is specified.
-
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[in] start the start of the time window (inclusive)
[in] end the end of the time window (non inclusive)
-
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TRUE current time within the specified time window.
FALSE current time not within the specified time window.
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Definition at line 122 of file chvt.c.

- -

References chTimeNow.

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-
-

Variable Documentation

- -
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VTList vtlist
-
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Virtual timers delta list header.

- -

Definition at line 41 of file chvt.c.

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VTList vtlist
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Virtual timers delta list header.

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Definition at line 41 of file chvt.c.

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Description

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System types and macros.

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-Defines

#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef int32_t bool_t
 Boolean, recommended the fastest signed.
typedef uint8_t tmode_t
 Thread mode flags, uint8_t is ok.
typedef uint8_t tstate_t
 Thread state, uint8_t is ok.
typedef uint8_t trefs_t
 Thread references counter, uint8_t is ok.
typedef uint32_t tprio_t
 Priority, use the fastest unsigned type.
typedef int32_t msg_t
 Message, use signed pointer equivalent.
typedef int32_t eventid_t
 Event Id, use fastest signed.
typedef uint32_t eventmask_t
 Event Mask, recommended fastest unsigned.
typedef uint32_t systime_t
 System Time, recommended fastest unsigned.
typedef int32_t cnt_t
 Counter, recommended fastest signed.
-

Define Documentation

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#define INLINE   inline
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Inline function modifier.

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Definition at line 104 of file kernel/templates/chtypes.h.

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ROM constant modifier.

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Note:
This is required because some compilers require a custom keyword, usually this macro is just set to "const" for the GCC compiler.
-
-This macro is not used to place constants in different address spaces (like AVR requires as example) because it is assumed that a pointer to a ROMCONST constant is compatible with a pointer to a normal variable. It is just like the "const" keyword but requires that the constant is placed in ROM if the architecture supports it.
- -

Definition at line 117 of file kernel/templates/chtypes.h.

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Packed structure modifier (within).

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Definition at line 122 of file kernel/templates/chtypes.h.

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Packed structure modifier (before).

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Definition at line 127 of file kernel/templates/chtypes.h.

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#define PACK_STRUCT_END
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Packed structure modifier (after).

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Definition at line 132 of file kernel/templates/chtypes.h.

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Typedef Documentation

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typedef int32_t bool_t
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Boolean, recommended the fastest signed.

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Definition at line 54 of file kernel/templates/chtypes.h.

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Thread mode flags, uint8_t is ok.

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Definition at line 59 of file kernel/templates/chtypes.h.

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typedef uint8_t tstate_t
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Thread state, uint8_t is ok.

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Definition at line 64 of file kernel/templates/chtypes.h.

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typedef uint8_t trefs_t
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Thread references counter, uint8_t is ok.

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Definition at line 69 of file kernel/templates/chtypes.h.

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typedef uint32_t tprio_t
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Priority, use the fastest unsigned type.

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Definition at line 74 of file kernel/templates/chtypes.h.

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typedef int32_t msg_t
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Message, use signed pointer equivalent.

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Definition at line 79 of file kernel/templates/chtypes.h.

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typedef int32_t eventid_t
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Event Id, use fastest signed.

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Definition at line 84 of file kernel/templates/chtypes.h.

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typedef uint32_t eventmask_t
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Event Mask, recommended fastest unsigned.

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Definition at line 89 of file kernel/templates/chtypes.h.

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typedef uint32_t systime_t
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System Time, recommended fastest unsigned.

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Definition at line 94 of file kernel/templates/chtypes.h.

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typedef int32_t cnt_t
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Counter, recommended fastest signed.

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Definition at line 99 of file kernel/templates/chtypes.h.

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Utilities Library.

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This is a collection of useful library code that is not part of the base kernel services.

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Notes

-

The library code does not follow the same naming convention of the system APIs in order to make very clear that it is not "core" code.
- The main difference is that library code is not formally tested in the test suite but through usage in the various demo applications.

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-Modules

 C++ Wrapper
 

C++ wrapper module.

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Memory Streams.

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Periodic Event Timer.

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Small extendible command line shell.

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void halInit (void)
 HAL initialization.
-

Detailed Description

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HAL subsystem code.

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Definition in file hal.c.

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HAL subsystem header. -More...

-#include "board.h"
-#include "halconf.h"
-#include "hal_lld.h"
-#include "pal.h"
-#include "adc.h"
-#include "can.h"
-#include "mac.h"
-#include "pwm.h"
-#include "serial.h"
-#include "spi.h"
-#include "mmc_spi.h"
- -

Go to the source code of this file.

- - - - -

-Functions

void halInit (void)
 HAL initialization.
-

Detailed Description

-

HAL subsystem header.

- -

Definition in file hal.h.

-
-
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STM32F103 HAL subsystem low level driver header. -More...

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Go to the source code of this file.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-Defines

#define STM32_HSICLK   8000000
#define STM32_LSICLK   40000
#define STM32_SW_HSI   (0 << 0)
#define STM32_SW_HSE   (1 << 0)
#define STM32_SW_PLL   (2 << 0)
#define STM32_HPRE_DIV1   (0 << 4)
#define STM32_HPRE_DIV2   (8 << 4)
#define STM32_HPRE_DIV4   (9 << 4)
#define STM32_HPRE_DIV8   (10 << 4)
#define STM32_HPRE_DIV16   (11 << 4)
#define STM32_HPRE_DIV64   (12 << 4)
#define STM32_HPRE_DIV128   (13 << 4)
#define STM32_HPRE_DIV256   (14 << 4)
#define STM32_HPRE_DIV512   (15 << 4)
#define STM32_PPRE1_DIV1   (0 << 8)
#define STM32_PPRE1_DIV2   (4 << 8)
#define STM32_PPRE1_DIV4   (5 << 8)
#define STM32_PPRE1_DIV8   (6 << 8)
#define STM32_PPRE1_DIV16   (7 << 8)
#define STM32_PPRE2_DIV1   (0 << 11)
#define STM32_PPRE2_DIV2   (4 << 11)
#define STM32_PPRE2_DIV4   (5 << 11)
#define STM32_PPRE2_DIV8   (6 << 11)
#define STM32_PPRE2_DIV16   (7 << 11)
#define STM32_ADCPRE_DIV2   (0 << 14)
#define STM32_ADCPRE_DIV4   (1 << 14)
#define STM32_ADCPRE_DIV6   (2 << 14)
#define STM32_ADCPRE_DIV8   (3 << 14)
#define STM32_PLLSRC_HSI   (0 << 16)
#define STM32_PLLSRC_HSE   (1 << 16)
#define STM32_PLLXTPRE_DIV1   (0 << 17)
#define STM32_PLLXTPRE_DIV2   (1 << 17)
#define STM32_MCO_NOCLOCK   (0 << 24)
#define STM32_MCO_SYSCLK   (4 << 24)
#define STM32_MCO_HSI   (5 << 24)
#define STM32_MCO_HSE   (6 << 24)
#define STM32_MCO_PLLDIV2   (7 << 24)
#define WWDG_IRQHandler   Vector40
#define PVD_IRQHandler   Vector44
#define TAMPER_IRQHandler   Vector48
#define RTC_IRQHandler   Vector4C
#define FLASH_IRQHandler   Vector50
#define RCC_IRQHandler   Vector54
#define EXTI0_IRQHandler   Vector58
#define EXTI1_IRQHandler   Vector5C
#define EXTI2_IRQHandler   Vector60
#define EXTI3_IRQHandler   Vector64
#define EXTI4_IRQHandler   Vector68
#define DMA1_Ch1_IRQHandler   Vector6C
#define DMA1_Ch2_IRQHandler   Vector70
#define DMA1_Ch3_IRQHandler   Vector74
#define DMA1_Ch4_IRQHandler   Vector78
#define DMA1_Ch5_IRQHandler   Vector7C
#define DMA1_Ch6_IRQHandler   Vector80
#define DMA1_Ch7_IRQHandler   Vector84
#define ADC1_2_IRQHandler   Vector88
#define CAN1_TX_IRQHandler   Vector8C
#define USB_HP_IRQHandler   Vector8C
#define CAN1_RX0_IRQHandler   Vector90
#define USB_LP_IRQHandler   Vector90
#define CAN1_RX1_IRQHandler   Vector94
#define CAN1_SCE_IRQHandler   Vector98
#define EXTI9_5_IRQHandler   Vector9C
#define TIM1_BRK_IRQHandler   VectorA0
#define TIM1_UP_IRQHandler   VectorA4
#define TIM1_TRG_COM_IRQHandler   VectorA8
#define TIM1_CC_IRQHandler   VectorAC
#define TIM2_IRQHandler   VectorB0
#define TIM3_IRQHandler   VectorB4
#define TIM4_IRQHandler   VectorB8
#define I2C1_EV_IRQHandler   VectorBC
#define I2C1_ER_IRQHandler   VectorC0
#define I2C2_EV_IRQHandler   VectorC4
#define I2C2_ER_IRQHandler   VectorC8
#define SPI1_IRQHandler   VectorCC
#define SPI2_IRQHandler   VectorD0
#define USART1_IRQHandler   VectorD4
#define USART2_IRQHandler   VectorD8
#define USART3_IRQHandler   VectorDC
#define EXTI15_10_IRQHandler   VectorE0
#define RTCAlarm_IRQHandler   VectorE4
#define USBWakeUp_IRQHandler   VectorE8
#define TIM8_BRK_IRQHandler   VectorEC
#define TIM8_UP_IRQHandler   VectorF0
#define TIM8_TRG_COM_IRQHandler   VectorF4
#define TIM8_CC_IRQHandler   VectorF8
#define ADC3_IRQHandler   VectorFC
#define FSMC_IRQHandler   Vector100
#define SDIO_IRQHandler   Vector104
#define TIM5_IRQHandler   Vector108
#define SPI3_IRQHandler   Vector10C
#define UART4_IRQHandler   Vector110
#define UART5_IRQHandler   Vector114
#define TIM6_IRQHandler   Vector118
#define TIM7_IRQHandler   Vector11C
#define DMA2_Ch1_IRQHandler   Vector120
#define DMA2_Ch2_IRQHandler   Vector124
#define DMA2_Ch3_IRQHandler   Vector128
#define DMA2_Ch4_5_IRQHandler   Vector12C
#define STM32_SW   STM32_SW_PLL
 Main clock source selection.
#define STM32_PLLSRC   STM32_PLLSRC_HSE
 Clock source for the PLL.
#define STM32_PLLXTPRE   STM32_PLLXTPRE_DIV1
 Crystal PLL pre-divider.
#define STM32_PLLMUL_VALUE   9
 PLL multiplier value.
#define STM32_HPRE   STM32_HPRE_DIV1
 AHB prescaler value.
#define STM32_PPRE1   STM32_PPRE1_DIV2
 APB1 prescaler value.
#define STM32_PPRE2   STM32_PPRE2_DIV2
 APB2 prescaler value.
#define STM32_ADCPRE   STM32_ADCPRE_DIV4
 ADC prescaler value.
#define STM32_MCO   STM32_MCO_NOCLOCK
 MCO pin setting.
#define STM32_PLLMUL   ((STM32_PLLMUL_VALUE - 2) << 18)
 PLLMUL field.
#define STM32_PLLCLKIN   (STM32_HSECLK / 1)
 PLL input clock frequency.
#define STM32_PLLCLKOUT   (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
 PLL output clock frequency.
#define STM32_SYSCLK   STM32_PLLCLKOUT
 System clock source.
#define STM32_HCLK   (STM32_SYSCLK / 1)
 AHB frequency.
#define STM32_PCLK1   (STM32_HCLK / 1)
 APB1 frequency.
#define STM32_PCLK2   (STM32_HCLK / 1)
 APB2 frequency.
#define STM32_ADCCLK   (STM32_PCLK2 / 2)
 ADC frequency.
#define STM32_TIMCLK1   (STM32_PCLK1 * 1)
 Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
#define STM32_TIMCLK2   (STM32_PCLK2 * 1)
 Timers 1, 8, 9, 10 and 11 clock.
#define STM32_FLASHBITS   0x00000010
 Flash settings.
-

Detailed Description

-

STM32F103 HAL subsystem low level driver header.

- -

Definition in file hal_lld_f103.h.

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-Defines

#define STM32_HSICLK   8000000
#define STM32_LSICLK   40000
#define STM32_SW_HSI   (0 << 0)
#define STM32_SW_HSE   (1 << 0)
#define STM32_SW_PLL   (2 << 0)
#define STM32_HPRE_DIV1   (0 << 4)
#define STM32_HPRE_DIV2   (8 << 4)
#define STM32_HPRE_DIV4   (9 << 4)
#define STM32_HPRE_DIV8   (10 << 4)
#define STM32_HPRE_DIV16   (11 << 4)
#define STM32_HPRE_DIV64   (12 << 4)
#define STM32_HPRE_DIV128   (13 << 4)
#define STM32_HPRE_DIV256   (14 << 4)
#define STM32_HPRE_DIV512   (15 << 4)
#define STM32_PPRE1_DIV1   (0 << 8)
#define STM32_PPRE1_DIV2   (4 << 8)
#define STM32_PPRE1_DIV4   (5 << 8)
#define STM32_PPRE1_DIV8   (6 << 8)
#define STM32_PPRE1_DIV16   (7 << 8)
#define STM32_PPRE2_DIV1   (0 << 11)
#define STM32_PPRE2_DIV2   (4 << 11)
#define STM32_PPRE2_DIV4   (5 << 11)
#define STM32_PPRE2_DIV8   (6 << 11)
#define STM32_PPRE2_DIV16   (7 << 11)
#define STM32_ADCPRE_DIV2   (0 << 14)
#define STM32_ADCPRE_DIV4   (1 << 14)
#define STM32_ADCPRE_DIV6   (2 << 14)
#define STM32_ADCPRE_DIV8   (3 << 14)
#define STM32_PLLSRC_HSI   (0 << 16)
#define STM32_PLLSRC_PREDIV1   (1 << 16)
#define STM32_OTGFSPRE_DIV2   (1 << 22)
#define STM32_OTGFSPRE_DIV3   (0 << 22)
#define STM32_MCO_NOCLOCK   (0 << 24)
#define STM32_MCO_SYSCLK   (4 << 24)
#define STM32_MCO_HSI   (5 << 24)
#define STM32_MCO_HSE   (6 << 24)
#define STM32_MCO_PLLDIV2   (7 << 24)
#define STM32_MCO_PLL2   (8 << 24)
#define STM32_MCO_PLL3DIV2   (9 << 24)
#define STM32_MCO_XT1   (10 << 24)
#define STM32_MCO_PLL3   (11 << 24)
#define STM32_PREDIV1SRC_HSE   (0 << 16)
#define STM32_PREDIV1SRC_PLL2   (1 << 16)
#define WWDG_IRQHandler   Vector40
#define PVD_IRQHandler   Vector44
#define TAMPER_IRQHandler   Vector48
#define RTC_IRQHandler   Vector4C
#define FLASH_IRQHandler   Vector50
#define RCC_IRQHandler   Vector54
#define EXTI0_IRQHandler   Vector58
#define EXTI1_IRQHandler   Vector5C
#define EXTI2_IRQHandler   Vector60
#define EXTI3_IRQHandler   Vector64
#define EXTI4_IRQHandler   Vector68
#define DMA1_Ch1_IRQHandler   Vector6C
#define DMA1_Ch2_IRQHandler   Vector70
#define DMA1_Ch3_IRQHandler   Vector74
#define DMA1_Ch4_IRQHandler   Vector78
#define DMA1_Ch5_IRQHandler   Vector7C
#define DMA1_Ch6_IRQHandler   Vector80
#define DMA1_Ch7_IRQHandler   Vector84
#define ADC1_2_IRQHandler   Vector88
#define CAN1_TX_IRQHandler   Vector8C
#define CAN1_RX0_IRQHandler   Vector90
#define CAN1_RX1_IRQHandler   Vector94
#define CAN1_SCE_IRQHandler   Vector98
#define EXTI9_5_IRQHandler   Vector9C
#define TIM1_BRK_IRQHandler   VectorA0
#define TIM1_UP_IRQHandler   VectorA4
#define TIM1_TRG_COM_IRQHandler   VectorA8
#define TIM1_CC_IRQHandler   VectorAC
#define TIM2_IRQHandler   VectorB0
#define TIM3_IRQHandler   VectorB4
#define TIM4_IRQHandler   VectorB8
#define I2C1_EV_IRQHandler   VectorBC
#define I2C1_ER_IRQHandler   VectorC0
#define I2C2_EV_IRQHandler   VectorC4
#define I2C2_ER_IRQHandler   VectorC8
#define SPI1_IRQHandler   VectorCC
#define SPI2_IRQHandler   VectorD0
#define USART1_IRQHandler   VectorD4
#define USART2_IRQHandler   VectorD8
#define USART3_IRQHandler   VectorDC
#define EXTI15_10_IRQHandler   VectorE0
#define RTCAlarm_IRQHandler   VectorE4
#define OTG_FS_WKUP_IRQHandler   VectorE8
#define TIM5_IRQHandler   Vector108
#define SPI3_IRQHandler   Vector10C
#define UART4_IRQHandler   Vector110
#define UART5_IRQHandler   Vector114
#define TIM6_IRQHandler   Vector118
#define TIM7_IRQHandler   Vector11C
#define DMA2_Ch1_IRQHandler   Vector120
#define DMA2_Ch2_IRQHandler   Vector124
#define DMA2_Ch3_IRQHandler   Vector128
#define DMA2_Ch4_IRQHandler   Vector12C
#define DMA2_Ch5_IRQHandler   Vector130
#define ETH_IRQHandler   Vector134
#define ETH_WKUP_IRQHandler   Vector138
#define CAN2_TX_IRQHandler   Vector13C
#define CAN2_RX0_IRQHandler   Vector140
#define CAN2_RX1_IRQHandler   Vector144
#define CAN2_SCE_IRQHandler   Vector148
#define OTG_FS_IRQHandler   Vector14C
#define STM32_SW   STM32_SW_PLL
 Main clock source selection.
#define STM32_PLLSRC   STM32_PLLSRC_PREDIV1
 Clock source for the PLL.
#define STM32_PREDIV1SRC   STM32_PREDIV1SRC_PLL2
 PREDIV1 clock source.
#define STM32_PREDIV1_VALUE   5
 PREDIV1 division factor.
#define STM32_PLLMUL_VALUE   9
 PLL multiplier value.
#define STM32_PREDIV2_VALUE   5
 PREDIV2 division factor.
#define STM32_PLL2MUL_VALUE   8
 PLL2 multiplier value.
#define STM32_HPRE   STM32_HPRE_DIV1
 AHB prescaler value.
#define STM32_PPRE1   STM32_PPRE1_DIV2
 APB1 prescaler value.
#define STM32_PPRE2   STM32_PPRE2_DIV2
 APB2 prescaler value.
#define STM32_ADCPRE   STM32_ADCPRE_DIV4
 ADC prescaler value.
#define STM32_MCO   STM32_MCO_NOCLOCK
 MCO pin setting.
#define STM32_PREDIV1   ((STM32_PREDIV1_VALUE - 1) << 0)
 PREDIV1 field.
#define STM32_PREDIV2   ((STM32_PREDIV2_VALUE - 1) << 4)
 PREDIV2 field.
#define STM32_PLLMUL   ((STM32_PLLMUL_VALUE - 2) << 18)
 PLLMUL field.
#define STM32_PLL2MUL   ((STM32_PLL2MUL_VALUE - 2) << 8)
 PLL2MUL field.
#define STM32_PLL2CLKIN   (STM32_HSECLK / STM32_PREDIV2_VALUE)
 PLL2 input frequency.
#define STM32_PLL2CLKOUT   (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)
 PLL2 output clock frequency.
#define STM32_PREDIV1CLK   STM32_PLL2CLKOUT
 PREDIV1 input frequency.
#define STM32_PLLCLKIN   (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
 PLL input clock frequency.
#define STM32_PLLCLKOUT   (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
 PLL output clock frequency.
#define STM32_SYSCLK   STM32_PLLCLKOUT
 System clock source.
#define STM32_HCLK   (STM32_SYSCLK / 1)
 AHB frequency.
#define STM32_PCLK1   (STM32_HCLK / 1)
 APB1 frequency.
#define STM32_PCLK2   (STM32_HCLK / 1)
 APB2 frequency.
#define STM32_ADCCLK   (STM32_PCLK2 / 2)
 ADC frequency.
#define STM32_TIMCLK1   (STM32_PCLK1 * 1)
 Timers 2, 3, 4, 5, 6, 7 clock.
#define STM32_TIMCLK2   (STM32_PCLK2 * 1)
 Timer 1 clock.
#define STM32_FLASHBITS   0x00000010
 Flash settings.
-

Detailed Description

-

STM32F10x Connectivity Line HAL subsystem low level driver header.

- -

Definition in file hal_lld_f105_f107.h.

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halconf.h File Reference

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HAL configuration header. -More...

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Go to the source code of this file.

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-Defines

#define CH_HAL_USE_PAL   TRUE
 Enables the PAL subsystem.
#define CH_HAL_USE_ADC   TRUE
 Enables the ADC subsystem.
#define CH_HAL_USE_CAN   TRUE
 Enables the CAN subsystem.
#define CH_HAL_USE_MAC   TRUE
 Enables the MAC subsystem.
#define CH_HAL_USE_PWM   TRUE
 Enables the PWM subsystem.
#define CH_HAL_USE_SERIAL   TRUE
 Enables the SERIAL subsystem.
#define CH_HAL_USE_SPI   TRUE
 Enables the SPI subsystem.
#define CH_HAL_USE_MMC_SPI   TRUE
 Enables the MMC_SPI subsystem.
-

Detailed Description

-

HAL configuration header.

-

HAL configuration file, this file allows to enable or disable the various device drivers from your application. You may also use this file in order to override the device drivers default settings.

- -

Definition in file halconf.h.

-
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-#include "ch.h"
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-Functions

void port_init (void)
 Port-related initialization code.
void port_lock (void)
 Kernel-lock action.
void port_unlock (void)
 Kernel-unlock action.
void port_lock_from_isr (void)
 Kernel-lock action from an interrupt handler.
void port_unlock_from_isr (void)
 Kernel-unlock action from an interrupt handler.
void port_disable (void)
 Disables all the interrupt sources.
void port_suspend (void)
 Disables the interrupt sources below kernel-level priority.
void port_enable (void)
 Enables all the interrupt sources.
void port_wait_for_interrupt (void)
 Enters an architecture-dependent IRQ-waiting mode.
void port_halt (void)
 Halts the system.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
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Detailed Description

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Port related template code.

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This file is a template of the system driver functions provided by a port. Some of the following functions may be implemented as macros in chcore.h if the implementer decides that there is an advantage in doing so, as example because performance concerns.

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Definition in file kernel/templates/chcore.c.

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-Data Structures

struct  extctx
 Interrupt saved context. More...
struct  intctx
 System saved context. More...
struct  context
 Platform dependent part of the Thread structure. More...

-Defines

#define CH_ARCHITECTURE_XXX
 Unique macro for the implemented architecture.
#define CH_ARCHITECTURE_NAME   ""
 Name of the implemented architecture.
#define CH_ARCHITECTURE_VARIANT_NAME   ""
 Name of the architecture variant (optional).
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   0
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   0
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void id(void)
 IRQ handler function declaration.
#define PORT_FAST_IRQ_HANDLER(id)   void id(void)
 Fast IRQ handler function declaration.

-Typedefs

typedef uint8_t stkalign_t
 Base type for stack and memory alignment.

-Functions

void port_init (void)
 Port-related initialization code.
void port_lock (void)
 Kernel-lock action.
void port_unlock (void)
 Kernel-unlock action.
void port_lock_from_isr (void)
 Kernel-lock action from an interrupt handler.
void port_unlock_from_isr (void)
 Kernel-unlock action from an interrupt handler.
void port_disable (void)
 Disables all the interrupt sources.
void port_suspend (void)
 Disables the interrupt sources below kernel-level priority.
void port_enable (void)
 Enables all the interrupt sources.
void port_wait_for_interrupt (void)
 Enters an architecture-dependent IRQ-waiting mode.
void port_halt (void)
 Halts the system.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
-

Detailed Description

-

Port related template macros and structures.

-

This file is a template of the system driver macros provided by a port.

- -

Definition in file kernel/templates/chcore.h.

-
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chtypes.h File Reference

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System types template. -More...

-#include <stddef.h>
-#include <stdint.h>
- -

Go to the source code of this file.

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-Defines

#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef int32_t bool_t
 Boolean, recommended the fastest signed.
typedef uint8_t tmode_t
 Thread mode flags, uint8_t is ok.
typedef uint8_t tstate_t
 Thread state, uint8_t is ok.
typedef uint8_t trefs_t
 Thread references counter, uint8_t is ok.
typedef uint32_t tprio_t
 Priority, use the fastest unsigned type.
typedef int32_t msg_t
 Message, use signed pointer equivalent.
typedef int32_t eventid_t
 Event Id, use fastest signed.
typedef uint32_t eventmask_t
 Event Mask, recommended fastest unsigned.
typedef uint32_t systime_t
 System Time, recommended fastest unsigned.
typedef int32_t cnt_t
 Counter, recommended fastest signed.
-

Detailed Description

-

System types template.

-

The types defined in this file may change depending on the target architecture. You may also try to optimize the size of the various types in order to privilege size or performance, be careful in doing so.

- -

Definition in file kernel/templates/chtypes.h.

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License and F.A.Q.

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ChibiOS/RT is a GPL3-licensed product but it offers a linking exception in its stable releases.
- This article contains some answers about the exception.

-

-Frequently Asked Questions

-
    -
  • Is ChibiOS/RT free ?
    - Yes, free as both in free beer and freedom.
    • -
  • Can I use it in my commercial embedded product?
    - Yes, you just have to advertise that you are using ChibiOS/RT by putting a link to the project somewhere on your web site or documentation.
    • -
  • Am I forced to release the source code of my product?
    - The exception to the GPL allows you to use ChibiOS/RT in your commercial application without have to release your source code under certains conditions. See the GPL Exception Text under "Approved Interfaces" for details.
    • -
  • What I have to contribute back?
    - In general you have to offer changes done on existing files (where allowed) or new developments done using the OS template files. As example:
      -
    • Ports to new architectures because a new port uses copyrighted OS template files.
      • -
    • New, HAL-style, device drivers because device drivers use copyrighted template files.
      • -
    • Improvements on modifiable OS code as described in the "approved interfaces" section of the GPL Exception Text.
      • -
    -
    • -
  • Is the exception applicable to any ChibiOS/RT version ?
    - The exception is valid only for ChibiOS/RT releases marked as stable. Beta, unstable or development versions are covered by the GPL3 alone because are meant for testing only.
    • -
  • I don't want to be bound by any of the above restriction, is this possible?
    - You may contact us about a commercial license.
    • -
-

-GPL Exception Text

-
GPL Exception Text for ChibiOS/RT 1.4.x

In addition, as a special exception, the copyright holder of ChibiOS/RT, gives You the additional right to link the unmodified code of this Program with code not covered under the GNU General Public License ("Non-GPL Code") and to distribute linked combinations including the two, subject to the limitations in this paragraph.

-
    -
  1. Non-GPL Code permitted under this exception must only link to the unmodified code of this Program through those well defined interfaces identified as "Approved Interfaces".
    2. -
  2. Every copy of the combined work is accompanied by a written statement that details to the recipient the version of ChibiOS/RT used and an offer by yourself to provide the ChibiOS/RT source code should the recipient request it.
    3. -
  3. The combined work is not itself an RTOS, scheduler, kernel or related product.
    4. -
  4. The combined work is not itself a binary library intended for linking into other software applications.
    5. -
-
The Approved Interfaces
    -
  1. The files of Non-GPL Code may include the unmodified ChibiOS/RT distribution header files contained under:
      -
    • ./os/kernel/include
      • -
    • ./os/hal/include
      • -
    • ./os/hal/platforms
      • -
    • ./os/various
      • -
    -without causing the resulting work to be covered by the GNU General Public License.
    2. -
  2. The files of Non-GPL Code may link to the unmodified ChibiOS/RT distribution files contained under:
      -
    • ./os/kernel/src
      • -
    • ./os/hal/src
      • -
    • ./os/hal/platforms
      • -
    • ./os/various
      • -
    -without causing the resulting work to be covered by the GNU General Public License.
    3. -
  3. The files of Non-GPL Code may link to, or include, the modified or unmodified ChibiOS/RT distribution files contained under:
      -
    • ./os/kernel/templates
      • -
    • ./os/hal/templates
      • -
    • ./os/ports
      • -
    • ./boards
      • -
    • ./demos
      • -
    -without causing the resulting work to be covered by the GNU General Public License.
    4. -
-

Only the copyright holder of ChibiOS/RT may make changes or additions to the list of Approved Interfaces.

-

You must obey the GNU General Public License in all respects for all of the Program code and other code used in conjunction with the Program except the Non-GPL Code covered by this exception.

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LPC214x register definitions. -More...

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Detailed Description

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LPC214x register definitions.

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Definition in file lpc214x.h.

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mac.c File Reference

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MAC Driver code. -More...

-#include "ch.h"
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-Functions

void macInit (void)
 MAC Driver initialization.
void macObjectInit (MACDriver *macp)
 Initialize the standard part of a MACDriver structure.
void macSetAddress (MACDriver *macp, const uint8_t *p)
 MAC address setup.
msg_t macWaitTransmitDescriptor (MACDriver *macp, MACTransmitDescriptor *tdp, systime_t time)
 Allocates a transmission descriptor.
void macReleaseTransmitDescriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t macWaitReceiveDescriptor (MACDriver *macp, MACReceiveDescriptor *rdp, systime_t time)
 Waits for a received frame.
void macReleaseReceiveDescriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t macPollLinkStatus (MACDriver *macp)
 Updates and returns the link status.
-

Detailed Description

-

MAC Driver code.

- -

Definition in file mac.c.

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mac.h File Reference

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MAC Driver macros and structures. -More...

-#include "mac_lld.h"
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-Defines

#define macGetReceiveEventSource(macp)   (&(macp)->md_rdevent)
 Returns the received frames event source.
#define macWriteTransmitDescriptor(tdp, buf, size)   mac_lld_write_transmit_descriptor(tdp, buf, size)
 Writes to a transmit descriptor's stream.
#define macReadReceiveDescriptor(rdp, buf, size)   mac_lld_read_receive_descriptor(rdp, buf, size)
 Reads from a receive descriptor's stream.

-Functions

void macInit (void)
 MAC Driver initialization.
void macObjectInit (MACDriver *macp)
 Initialize the standard part of a MACDriver structure.
void macSetAddress (MACDriver *macp, const uint8_t *p)
 MAC address setup.
msg_t macWaitTransmitDescriptor (MACDriver *macp, MACTransmitDescriptor *tdp, systime_t time)
 Allocates a transmission descriptor.
void macReleaseTransmitDescriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t macWaitReceiveDescriptor (MACDriver *macp, MACReceiveDescriptor *rdp, systime_t time)
 Waits for a received frame.
void macReleaseReceiveDescriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t macPollLinkStatus (MACDriver *macp)
 Updates and returns the link status.
-

Detailed Description

-

MAC Driver macros and structures.

- -

Definition in file mac.h.

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ChibiOS/RT

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2.0.8

Author:
Giovanni Di Sirio (gdisirio@users.sourceforge.net).
-

Chibi ?

-

I didn't want a serious name for this project. It is the Japanese word for small as in small child. So ChibiOS/RT (ちびOS/RT) means small Real Time Operating System. Source Wikipedia.

-

Features

-
    -
  • Free software, GPL3 licensed. Stable releases include a exception clause to the GPL.
    • -
  • Designed for realtime applications.
    • -
  • Easily portable.
    • -
  • Preemptive scheduling.
    • -
  • 128 priority levels. Multiple threads at the same priority level allowed.
    • -
  • Round robin scheduling for threads at the same priority level.
    • -
  • Offers threads, virtual timers, semaphores, mutexes, condvars, event flags, messages, mailboxes, I/O queues.
    • -
  • No static setup at compile time, there is no need to configure a maximum number of all the above objects.
    • -
  • PC simulator target included, the development can be done on a PC under Linux or Windows.
    - Timers, I/O channels and other HW resources are simulated in a guest OS process and the application code does not need to be aware of it.
    • -
  • No *need* for a memory allocator, all the kernel structures are static and declaratively allocated.
    • -
  • Optional, thread safe, Heap Allocator subsystem.
    • -
  • Optional, thread safe, Memory Pools Allocator subsystem.
    • -
  • Blocking and non blocking I/O channels with timeout and events generation capability.
    • -
  • Minimal system requirements: about 6KiB ROM with all options enabled and speed optimizations on. The size can shrink under 2KiB by disabling the the unused subsystems and optimizing for size.
    • -
  • Almost totally written in C with little ASM code required for ports.
    • -
  • Optional Hardware Abstraction Layer (HAL) with support for many device driver models and device driver implementations.
    • -
-

Related pages

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void msObjectInit (MemoryStream *msp, uint8_t *buffer, size_t size, size_t eos)
 Memory stream object initialization.
-

Detailed Description

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Memory streams code.

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Definition in file memstreams.c.

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struct  MemStreamVMT
 MemStream virtual methods table. More...
struct  MemoryStream
 Memory stream object. More...

-Defines

#define _memory_stream_data
 RamStream specific data.

-Functions

void msObjectInit (MemoryStream *msp, uint8_t *buffer, size_t size, size_t eos)
 Memory stream object initialization.
-

Detailed Description

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Memory streams structures and macros.

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Definition in file memstreams.h.

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mmc_spi.c File Reference

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MMC over SPI driver code. -More...

-#include "ch.h"
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-Functions

void tmrfunc (void *p)
 Inserion monitor timer callback function.
void mmcInit (void)
 MMC over SPI driver initialization.
void mmcObjectInit (MMCDriver *mmcp, SPIDriver *spip, const SPIConfig *lscfg, const SPIConfig *hscfg, mmcquery_t is_protected, mmcquery_t is_inserted)
 Initializes an instance.
void mmcStart (MMCDriver *mmcp, const MMCConfig *config)
 Configures and activates the MMC peripheral.
void mmcStop (MMCDriver *mmcp)
 Disables the MMC peripheral.
bool_t mmcConnect (MMCDriver *mmcp)
 Performs the initialization procedure on the inserted card.
bool_t mmcDisconnect (MMCDriver *mmcp)
 Brings the driver in a state safe for card removal.
bool_t mmcStartSequentialRead (MMCDriver *mmcp, uint32_t startblk)
 Starts a sequential read.
bool_t mmcSequentialRead (MMCDriver *mmcp, uint8_t *buffer)
 Reads a block within a sequential read operation.
bool_t mmcStopSequentialRead (MMCDriver *mmcp)
 Stops a sequential read gracefully.
bool_t mmcStartSequentialWrite (MMCDriver *mmcp, uint32_t startblk)
 Starts a sequential write.
bool_t mmcSequentialWrite (MMCDriver *mmcp, const uint8_t *buffer)
 Writes a block within a sequential write operation.
bool_t mmcStopSequentialWrite (MMCDriver *mmcp)
 Stops a sequential write gracefully.
-

Detailed Description

-

MMC over SPI driver code.

- -

Definition in file mmc_spi.c.

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-Data Structures

struct  MMCConfig
 Driver configuration structure. More...
struct  MMCDriver
 Structure representing a MMC driver. More...

-Defines

#define MMC_SECTOR_SIZE   512
 Block size for MMC transfers.
#define MMC_NICE_WAITING   TRUE
 Delays insertions.
#define MMC_POLLING_INTERVAL   10
 Number of positive insertion queries before generating the insertion event.
#define MMC_POLLING_DELAY   10
 Interval, in milliseconds, between insertion queries.
#define mmcGetDriverState(mmcp)   ((mmcp)->mmc_state)
 Returns the driver state.
#define mmcIsWriteProtected(mmcp)   ((mmcp)->mmc_is_protected())
 Returns the write protect status.

-Typedefs

typedef bool_t(* mmcquery_t )(void)
 Function used to query some hardware status bits.

-Enumerations

enum  mmcstate_t {
-  MMC_UNINIT = 0, -MMC_STOP = 1, -MMC_WAIT = 2, -MMC_INSERTED = 3, -
-  MMC_READY = 4, -MMC_READING = 5, -MMC_WRITING = 6 -
- }
 

Driver state machine possible states.

- More...

-Functions

void mmcInit (void)
 MMC over SPI driver initialization.
void mmcObjectInit (MMCDriver *mmcp, SPIDriver *spip, const SPIConfig *lscfg, const SPIConfig *hscfg, mmcquery_t is_protected, mmcquery_t is_inserted)
 Initializes an instance.
void mmcStart (MMCDriver *mmcp, const MMCConfig *config)
 Configures and activates the MMC peripheral.
void mmcStop (MMCDriver *mmcp)
 Disables the MMC peripheral.
bool_t mmcConnect (MMCDriver *mmcp)
 Performs the initialization procedure on the inserted card.
bool_t mmcDisconnect (MMCDriver *mmcp)
 Brings the driver in a state safe for card removal.
bool_t mmcStartSequentialRead (MMCDriver *mmcp, uint32_t startblk)
 Starts a sequential read.
bool_t mmcSequentialRead (MMCDriver *mmcp, uint8_t *buffer)
 Reads a block within a sequential read operation.
bool_t mmcStopSequentialRead (MMCDriver *mmcp)
 Stops a sequential read gracefully.
bool_t mmcStartSequentialWrite (MMCDriver *mmcp, uint32_t startblk)
 Starts a sequential write.
bool_t mmcSequentialWrite (MMCDriver *mmcp, const uint8_t *buffer)
 Writes a block within a sequential write operation.
bool_t mmcStopSequentialWrite (MMCDriver *mmcp)
 Stops a sequential write gracefully.
-

Detailed Description

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MMC over SPI driver header.

- -

Definition in file mmc_spi.h.

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void NVICEnableVector (uint32_t n, uint32_t prio)
 Sets the priority of an interrupt handler and enables it.
void NVICDisableVector (uint32_t n)
 Disables an interrupt handler.
void NVICSetSystemHandlerPriority (uint32_t handler, uint32_t prio)
 Changes the priority of a system handler.
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Cortex-Mx NVIC support code.

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struct  CM3_ST
 Structure representing the SYSTICK I/O space. More...
struct  CM3_NVIC
 Structure representing the NVIC I/O space. More...
struct  CM3_SCB
 Structure representing the System Control Block I/O space. More...

-Defines

#define HANDLER_MEM_MANAGE   0
#define HANDLER_BUS_FAULT   1
#define HANDLER_USAGE_FAULT   2
#define HANDLER_SVCALL   7
#define HANDLER_DEBUG_MONITOR   8
#define HANDLER_PENDSV   10
#define HANDLER_SYSTICK   11
#define NVIC_ITCR   (*((IOREG32 *)0xE000E004))
 NVIC ITCR register.
#define NVIC_STIR   (*((IOREG32 *)0xE000EF00))
 NVIC STIR register.
#define STBase   ((CM3_ST *)0xE000E010)
 SYSTICK peripheral base address.
#define NVICBase   ((CM3_NVIC *)0xE000E100)
 NVIC peripheral base address.
#define SCBBase   ((CM3_SCB *)0xE000ED00)
 SCB peripheral base address.

-Typedefs

typedef volatile uint8_t IOREG8
typedef volatile uint32_t IOREG32

-Functions

void NVICEnableVector (uint32_t n, uint32_t prio)
 Sets the priority of an interrupt handler and enables it.
void NVICDisableVector (uint32_t n)
 Disables an interrupt handler.
void NVICSetSystemHandlerPriority (uint32_t handler, uint32_t prio)
 Changes the priority of a system handler.
-

Detailed Description

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Cortex-Mx NVIC support macros and structures.

- -

Definition in file nvic.h.

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-Functions

ioportmask_t palReadBus (IOBus *bus)
 Read from an I/O bus.
void palWriteBus (IOBus *bus, ioportmask_t bits)
 Write to an I/O bus.
void palSetBusMode (IOBus *bus, uint_fast8_t mode)
 Programs a bus with the specified mode.
-

Detailed Description

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I/O Ports Abstraction Layer code.

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Definition in file pal.c.

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-Data Structures

struct  IOBus
 I/O bus descriptor. More...

-Defines

#define PAL_MODE_MASK   0xF
 Bits in a mode word dedicated as mode selector.
#define PAL_MODE_RESET   0
 After reset state.
#define PAL_MODE_UNCONNECTED   1
 Safe state for unconnected pads.
#define PAL_MODE_INPUT   2
 Regular input high-Z pad.
#define PAL_MODE_INPUT_PULLUP   3
 Input pad with weak pull up resistor.
#define PAL_MODE_INPUT_PULLDOWN   4
 Input pad with weak pull down resistor.
#define PAL_MODE_INPUT_ANALOG   5
 Analog input mode.
#define PAL_MODE_OUTPUT_PUSHPULL   6
 Push-pull output pad.
#define PAL_MODE_OUTPUT_OPENDRAIN   7
 Open-drain output pad.
#define PAL_LOW   0
 Logical low state.
#define PAL_HIGH   1
 Logical high state.
#define PAL_PORT_BIT(n)   ((ioportmask_t)(1 << (n)))
 Port bit helper macro.
#define PAL_GROUP_MASK(width)   ((ioportmask_t)(1 << (width)) - 1)
 Bits group mask helper.
#define _IOBUS_DATA(name, port, width, offset)   {port, PAL_GROUP_MASK(width), offset}
 Data part of a static I/O bus initializer.
#define IOBUS_DECL(name, port, width, offset)   IOBus name = _IOBUS_DATA(name, port, width, offset)
 Static I/O bus initializer.
#define palInit(config)   pal_lld_init(config)
 PAL subsystem initialization.
#define palReadPort(port)   ((void)(port), 0)
 Reads the physical I/O port states.
#define palReadLatch(port)   ((void)(port), 0)
 Reads the output latch.
#define palWritePort(port, bits)   ((void)(port), (void)(bits))
 Writes a bits mask on a I/O port.
#define palSetPort(port, bits)
 Sets a bits mask on a I/O port.
#define palClearPort(port, bits)
 Clears a bits mask on a I/O port.
#define palTogglePort(port, bits)
 Toggles a bits mask on a I/O port.
#define palReadGroup(port, mask, offset)   ((palReadPort(port) >> (offset)) & (mask))
 Reads a group of bits.
#define palWriteGroup(port, mask, offset, bits)
 Writes a group of bits.
#define palSetGroupMode(port, mask, mode)
 Pads group mode setup.
#define palReadPad(port, pad)   ((palReadPort(port) >> (pad)) & 1)
 Reads an input pad logical state.
#define palWritePad(port, pad, bit)
 Writes a logical state on an output pad.
#define palSetPad(port, pad)   palSetPort(port, PAL_PORT_BIT(pad))
 Sets a pad logical state to PAL_HIGH.
#define palClearPad(port, pad)   palClearPort(port, PAL_PORT_BIT(pad))
 Clears a pad logical state to PAL_LOW.
#define palTogglePad(port, pad)   palTogglePort(port, PAL_PORT_BIT(pad))
 Toggles a pad logical state.
#define palSetPadMode(port, pad, mode)   palSetGroupMode(port, PAL_PORT_BIT(pad), mode)
 Pad mode setup.

-Functions

ioportmask_t palReadBus (IOBus *bus)
 Read from an I/O bus.
void palWriteBus (IOBus *bus, ioportmask_t bits)
 Write to an I/O bus.
void palSetBusMode (IOBus *bus, uint_fast8_t mode)
 Programs a bus with the specified mode.
-

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I/O Ports Abstraction Layer macros, types and structures.

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Definition in file pal.h.

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void hal_lld_init (void)
 Low level HAL driver initialization.
void at91sam7_clock_init (void)
 AT91SAM7 clocks and PLL initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

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AT91SAM7 HAL subsystem low level driver source.

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hal_lld.h File Reference

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AT91SAM7 HAL subsystem low level driver header. -More...

-#include "at91sam7.h"
-#include "at91lib/aic.h"
- -

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-Defines

#define PLATFORM_NAME   "AT91SAM7x"
 Platform name.
#define AT91SAM7_SPURIOUS_HANDLER_HOOK()
 Default action for the spurious handler, nothing.
#define AT91SAM7_USBDIV   AT91C_CKGR_USBDIV_1
 Default divider for the USB clock - half the PLL clock.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void at91sam7_clock_init (void)
 AT91SAM7 clocks and PLL initialization.
-

Detailed Description

-

AT91SAM7 HAL subsystem low level driver header.

- -

Definition in file platforms/AT91SAM7/hal_lld.h.

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mac_lld.c File Reference

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AT91SAM7 low level MAC driver code. -More...

-#include <string.h>
-#include "ch.h"
-#include "hal.h"
-#include "mii.h"
-#include "at91sam7_mii.h"
- -

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-Functions

 CH_IRQ_HANDLER (irq_handler)
 EMAC IRQ veneer handler.
void mac_lld_init (void)
 Low level MAC initialization.
void mac_lld_set_address (MACDriver *macp, const uint8_t *p)
 Low level MAC address setup.
msg_t max_lld_get_transmit_descriptor (MACDriver *macp, MACTransmitDescriptor *tdp)
 Returns a transmission descriptor.
size_t mac_lld_write_transmit_descriptor (MACTransmitDescriptor *tdp, uint8_t *buf, size_t size)
 Writes to a transmit descriptor's stream.
void mac_lld_release_transmit_descriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t max_lld_get_receive_descriptor (MACDriver *macp, MACReceiveDescriptor *rdp)
 Returns a receive descriptor.
size_t mac_lld_read_receive_descriptor (MACReceiveDescriptor *rdp, uint8_t *buf, size_t size)
 Reads from a receive descriptor's stream.
void mac_lld_release_receive_descriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t mac_lld_poll_link_status (MACDriver *macp)
 Updates and returns the link status.

-Variables

MACDriver ETH1
 Ethernet driver 1.
-

Detailed Description

-

AT91SAM7 low level MAC driver code.

- -

Definition in file platforms/AT91SAM7/mac_lld.c.

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mac_lld.h File Reference

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AT91SAM7 low level MAC driver header. -More...

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-Data Structures

struct  EMACDescriptor
 Structure representing a buffer physical descriptor. More...
struct  MACDriver
 Structure representing a MAC driver. More...
struct  MACTransmitDescriptor
 Structure representing a transmit descriptor. More...
struct  MACReceiveDescriptor
 Structure representing a receive descriptor. More...

-Defines

#define MAC_TRANSMIT_BUFFERS   2
 Number of available transmit buffers.
#define MAC_RECEIVE_BUFFERS   2
 Number of available receive buffers.
#define MAC_BUFFERS_SIZE   1518
 Maximum supported frame size.
#define EMAC_INTERRUPT_PRIORITY   (AT91C_AIC_PRIOR_HIGHEST - 3)
 Interrupt priority level for the EMAC device.

-Functions

void mac_lld_init (void)
 Low level MAC initialization.
void mac_lld_set_address (MACDriver *macp, const uint8_t *p)
 Low level MAC address setup.
msg_t max_lld_get_transmit_descriptor (MACDriver *macp, MACTransmitDescriptor *tdp)
 Returns a transmission descriptor.
size_t mac_lld_write_transmit_descriptor (MACTransmitDescriptor *tdp, uint8_t *buf, size_t size)
 Writes to a transmit descriptor's stream.
void mac_lld_release_transmit_descriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t max_lld_get_receive_descriptor (MACDriver *macp, MACReceiveDescriptor *rdp)
 Returns a receive descriptor.
size_t mac_lld_read_receive_descriptor (MACReceiveDescriptor *rdp, uint8_t *buf, size_t size)
 Reads from a receive descriptor's stream.
void mac_lld_release_receive_descriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t mac_lld_poll_link_status (MACDriver *macp)
 Updates and returns the link status.
-

Detailed Description

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AT91SAM7 low level MAC driver header.

- -

Definition in file platforms/AT91SAM7/mac_lld.h.

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pal_lld.c File Reference

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AT91SAM7 PIO low level driver code. -More...

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void _pal_lld_init (const PALConfig *config)
 AT91SAM7 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
-

Detailed Description

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AT91SAM7 PIO low level driver code.

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Definition in file platforms/AT91SAM7/pal_lld.c.

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-Data Structures

struct  at91sam7_pio_setup_t
 PIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define IOPORT1   AT91C_BASE_PIOA
 PIO port A identifier.
#define IOPORT2   AT91C_BASE_PIOB
 PIO port B identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->PIO_PDSR)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->PIO_ODSR)
 Reads the output latch.
#define pal_lld_writeport(port, bits)
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)
 Clears a bits mask on a I/O port.
#define pal_lld_writegroup(port, mask, offset, bits)
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   pal_lld_writegroup(port, 1, pad, bit)
 Writes a logical state on an output pad.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef AT91PS_PIO ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 AT91SAM7 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Detailed Description

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AT91SAM7 PIO low level driver header.

- -

Definition in file platforms/AT91SAM7/pal_lld.h.

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serial_lld.c File Reference

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AT91SAM7 low level serial driver code. -More...

-#include "ch.h"
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-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 USART0 serial driver identifier.
SerialDriver SD2
 USART1 serial driver identifier.
SerialDriver SD3
 DBGU_UART serial driver identifier.
-

Detailed Description

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AT91SAM7 low level serial driver code.

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Definition in file platforms/AT91SAM7/serial_lld.c.

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AT91SAM7 low level serial driver header. -More...

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_SAM7_USART0   TRUE
 UART0 driver enable switch.
#define USE_SAM7_USART1   TRUE
 UART1 driver enable switch.
#define USE_SAM7_DBGU_UART   TRUE
 DBGU UART driver enable switch.
#define SAM7_USART0_PRIORITY   (AT91C_AIC_PRIOR_HIGHEST - 2)
 UART1 interrupt priority level setting.
#define SAM7_USART1_PRIORITY   (AT91C_AIC_PRIOR_HIGHEST - 2)
 UART2 interrupt priority level setting.
#define SAM7_DBGU_UART_PRIORITY   (AT91C_AIC_PRIOR_HIGHEST - 2)
 DBGU_UART interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
-

Detailed Description

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AT91SAM7 low level serial driver header.

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Definition in file platforms/AT91SAM7/serial_lld.h.

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void hal_lld_init (void)
 Low level HAL driver initialization.
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Detailed Description

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AVR HAL subsystem low level driver code.

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Definition in file platforms/AVR/hal_lld.c.

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#define PLATFORM_NAME   "ATmega128"
 Platform name.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
-

Detailed Description

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AVR HAL subsystem low level driver header.

- -

Definition in file platforms/AVR/hal_lld.h.

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serial_lld.c File Reference

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AVR low level serial driver code. -More...

-#include "ch.h"
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-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 USART0 serial driver identifier.
SerialDriver SD2
 USART1 serial driver identifier.
-

Detailed Description

-

AVR low level serial driver code.

- -

Definition in file platforms/AVR/serial_lld.c.

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serial_lld.h File Reference

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AVR low level serial driver header. -More...

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Go to the source code of this file.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_AVR_USART0   TRUE
 USART0 driver enable switch.
#define USE_AVR_USART1   TRUE
 USART1 driver enable switch.
#define _serial_driver_data
 SerialDriver specific data.
#define UBRR(b)   ((F_CPU / (b << 4)) - 1)
 Macro for baud rate computation.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
-

Detailed Description

-

AVR low level serial driver header.

- -

Definition in file platforms/AVR/serial_lld.h.

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hal_lld.c File Reference

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LPC11xx HAL subsystem low level driver source. -More...

-#include "ch.h"
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-Defines

#define FLASHCFG   (*((volatile uint32_t *)0x4003C010))
 Register missing in NXP header file.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void lpc111x_clock_init (void)
 LPC11xx clocks and PLL initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Detailed Description

-

LPC11xx HAL subsystem low level driver source.

- -

Definition in file platforms/LPC11xx/hal_lld.c.

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hal_lld.h File Reference

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HAL subsystem low level driver header template. -More...

-#include "LPC11xx.h"
-#include "nvic.h"
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-Defines

#define PLATFORM_NAME   "LPC11xx"
 Platform name.
#define IRCOSCCLK   12000000
#define WDGOSCCLK   1600000
#define SYSPLLCLKSEL_IRCOSC   0
#define SYSPLLCLKSEL_SYSOSC   1
#define SYSMAINCLKSEL_IRCOSC   0
#define SYSMAINCLKSEL_PLLIN   1
#define SYSMAINCLKSEL_WDGOSC   2
#define SYSMAINCLKSEL_PLLOUT   3
#define LPC11xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC
 System PLL clock source.
#define LPC11xx_SYSPLL_MUL   4
 System PLL multiplier.
#define LPC11xx_SYSPLL_DIV   4
 System PLL divider.
#define LPC11xx_MAINCLK_SOURCE   SYSMAINCLKSEL_PLLOUT
 System main clock source.
#define LPC11xx_SYSABHCLK_DIV   1
 AHB clock divider.
#define LPC11xx_UART_PCLK_DIV   1
 UART clock divider.
#define LPC11xx_SYSOSCCTRL   0
 Calculated SYSOSCCTRL setting.
#define LPC11xx_SYSPLLCLKIN   SYSOSCCLK
 PLL input clock frequency.
#define LPC11xx_SYSPLLCTRL_MSEL   (LPC11xx_SYSPLL_MUL - 1)
 MSEL mask in SYSPLLCTRL register.
#define LPC11xx_SYSPLLCTRL_PSEL   (0 << 5)
 PSEL mask in SYSPLLCTRL register.
#define LPC11xx_SYSPLLCCO
 CCP frequency.
#define LPC11xx_SYSPLLCLKOUT   (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)
 PLL output clock frequency.
#define LPC11xx_SYSCLK   (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV)
 AHB clock.
#define LPC11xx_FLASHCFG_FLASHTIM   0
 Flash wait states.
#define LPC11xx_UART_PCLK   (LPC11xx_MAINCLK / LPC11xx_UART_PCLK_DIV)
 UART clock.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void lpc111x_clock_init (void)
 LPC11xx clocks and PLL initialization.
-

Detailed Description

-

HAL subsystem low level driver header template.

- -

Definition in file platforms/LPC11xx/hal_lld.h.

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pal_lld.c File Reference

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LPC11xx GPIO low level driver code. -More...

-#include "ch.h"
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void _pal_lld_init (const PALConfig *config)
 LPC11xx I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
-

Detailed Description

-

LPC11xx GPIO low level driver code.

- -

Definition in file platforms/LPC11xx/pal_lld.c.

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LPC11xx GPIO low level driver header. -More...

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-Data Structures

struct  lpc111x_gpio_setup_t
 GPIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFF)
 Whole port mask.
#define IOPORT1   LPC_GPIO0
 GPIO0 port identifier.
#define IOPORT2   LPC_GPIO1
 GPIO1 port identifier.
#define IOPORT3   LPC_GPIO2
 GPIO2 port identifier.
#define IOPORT4   LPC_GPIO3
 GPIO3 port identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->DATA)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->DATA)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->DATA = (bits))
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0)
 Clears a bits mask on a I/O port.
#define pal_lld_readgroup(port, mask, offset)   ((port)->MASKED_ACCESS[(mask) << (offset)])
 Reads a group of bits.
#define pal_lld_writegroup(port, mask, offset, bits)   ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad))
 Writes a logical state on an output pad.
#define pal_lld_setpad(port, pad)   ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
 Sets a pad logical state to PAL_HIGH.
#define pal_lld_clearpad(port, pad)   ((port)->MASKED_ACCESS[1 << (pad)] = 0)
 Clears a pad logical state to PAL_LOW.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef LPC_GPIO_TypeDef * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 LPC11xx I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
-

Detailed Description

-

LPC11xx GPIO low level driver header.

- -

Definition in file platforms/LPC11xx/pal_lld.h.

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LPC11xx low level serial driver code. -More...

-#include "ch.h"
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-Functions

 CH_IRQ_HANDLER (Vector94)
 UART0 IRQ handler.
void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 UART0 serial driver identifier.
-

Detailed Description

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LPC11xx low level serial driver code.

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Definition in file platforms/LPC11xx/serial_lld.c.

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LPC11xx low level serial driver header. -More...

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_LPC11xx_UART0   TRUE
 UART0 driver enable switch.
#define LPC11xx_UART_FIFO_PRELOAD   16
 FIFO preload parameter.
#define LPC11xx_UART0_PRIORITY   3
 UART0 interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
-

Detailed Description

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LPC11xx low level serial driver header.

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Definition in file platforms/LPC11xx/serial_lld.h.

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hal_lld.c File Reference

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LPC13xx HAL subsystem low level driver source. -More...

-#include "ch.h"
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-Defines

#define FLASHCFG   (*((volatile uint32_t *)0x4003C010))
 Register missing in NXP header file.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void LPC13xx_clock_init (void)
 LPC13xx clocks and PLL initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Detailed Description

-

LPC13xx HAL subsystem low level driver source.

- -

Definition in file platforms/LPC13xx/hal_lld.c.

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hal_lld.h File Reference

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HAL subsystem low level driver header template. -More...

-#include "LPC13xx.h"
-#include "nvic.h"
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-Defines

#define PLATFORM_NAME   "LPC13xx"
 Platform name.
#define IRCOSCCLK   12000000
#define WDGOSCCLK   1600000
#define SYSPLLCLKSEL_IRCOSC   0
#define SYSPLLCLKSEL_SYSOSC   1
#define SYSMAINCLKSEL_IRCOSC   0
#define SYSMAINCLKSEL_PLLIN   1
#define SYSMAINCLKSEL_WDGOSC   2
#define SYSMAINCLKSEL_PLLOUT   3
#define LPC13xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC
 System PLL clock source.
#define LPC13xx_SYSPLL_MUL   6
 System PLL multiplier.
#define LPC13xx_SYSPLL_DIV   4
 System PLL divider.
#define LPC13xx_MAINCLK_SOURCE   SYSMAINCLKSEL_PLLOUT
 System main clock source.
#define LPC13xx_SYSABHCLK_DIV   1
 AHB clock divider.
#define LPC13xx_UART_PCLK_DIV   1
 UART clock divider.
#define LPC13xx_SYSOSCCTRL   0
 Calculated SYSOSCCTRL setting.
#define LPC13xx_SYSPLLCLKIN   SYSOSCCLK
 PLL input clock frequency.
#define LPC13xx_SYSPLLCTRL_MSEL   (LPC13xx_SYSPLL_MUL - 1)
 MSEL mask in SYSPLLCTRL register.
#define LPC13xx_SYSPLLCTRL_PSEL   (0 << 5)
 PSEL mask in SYSPLLCTRL register.
#define LPC13xx_SYSPLLCCO
 CCP frequency.
#define LPC13xx_SYSPLLCLKOUT   (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV)
 PLL output clock frequency.
#define LPC13xx_SYSCLK   (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV)
 AHB clock.
#define LPC13xx_FLASHCFG_FLASHTIM   0
 Flash wait states.
#define LPC13xx_UART_PCLK   (LPC13xx_MAINCLK / LPC13xx_UART_PCLK_DIV)
 UART clock.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void LPC13xx_clock_init (void)
 LPC13xx clocks and PLL initialization.
-

Detailed Description

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HAL subsystem low level driver header template.

- -

Definition in file platforms/LPC13xx/hal_lld.h.

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pal_lld.c File Reference

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LPC13xx GPIO low level driver code. -More...

-#include "ch.h"
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void _pal_lld_init (const PALConfig *config)
 LPC13xx I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
-

Detailed Description

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LPC13xx GPIO low level driver code.

- -

Definition in file platforms/LPC13xx/pal_lld.c.

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LPC13xx GPIO low level driver header. -More...

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-Data Structures

struct  LPC13xx_gpio_setup_t
 GPIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFF)
 Whole port mask.
#define IOPORT1   LPC_GPIO0
 GPIO0 port identifier.
#define IOPORT2   LPC_GPIO1
 GPIO1 port identifier.
#define IOPORT3   LPC_GPIO2
 GPIO2 port identifier.
#define IOPORT4   LPC_GPIO3
 GPIO3 port identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->DATA)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->DATA)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->DATA = (bits))
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0)
 Clears a bits mask on a I/O port.
#define pal_lld_readgroup(port, mask, offset)   ((port)->MASKED_ACCESS[(mask) << (offset)])
 Reads a group of bits.
#define pal_lld_writegroup(port, mask, offset, bits)   ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad))
 Writes a logical state on an output pad.
#define pal_lld_setpad(port, pad)   ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
 Sets a pad logical state to PAL_HIGH.
#define pal_lld_clearpad(port, pad)   ((port)->MASKED_ACCESS[1 << (pad)] = 0)
 Clears a pad logical state to PAL_LOW.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef LPC_GPIO_TypeDef * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 LPC13xx I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
-

Detailed Description

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LPC13xx GPIO low level driver header.

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Definition in file platforms/LPC13xx/pal_lld.h.

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serial_lld.c File Reference

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LPC13xx low level serial driver code. -More...

-#include "ch.h"
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-Functions

 CH_IRQ_HANDLER (VectorF8)
 UART0 IRQ handler.
void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 UART0 serial driver identifier.
-

Detailed Description

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LPC13xx low level serial driver code.

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Definition in file platforms/LPC13xx/serial_lld.c.

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struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_LPC13xx_UART0   TRUE
 UART0 driver enable switch.
#define LPC13xx_UART_FIFO_PRELOAD   16
 FIFO preload parameter.
#define LPC13xx_UART0_PRIORITY   3
 UART0 interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
-

Detailed Description

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LPC13xx low level serial driver header.

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Definition in file platforms/LPC13xx/serial_lld.h.

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void hal_lld_init (void)
 Low level HAL driver initialization.
void lpc214x_clock_init (void)
 LPC214x clocks and PLL initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
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Detailed Description

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LPC214x HAL subsystem low level driver source.

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Definition in file platforms/LPC214x/hal_lld.c.

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-Defines

#define PLATFORM_NAME   "LPC214x"
 Platform name.
#define LPC214x_NON_VECTORED_IRQ_HOOK()
 Default action for the non vectored IRQ handler, nothing.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void lpc214x_clock_init (void)
 LPC214x clocks and PLL initialization.
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Detailed Description

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LPC214x HAL subsystem low level driver header.

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Definition in file platforms/LPC214x/hal_lld.h.

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LPC214x FIO low level driver code. -More...

-#include "ch.h"
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void _pal_lld_init (const PALConfig *config)
 LPC214x I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
-

Detailed Description

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LPC214x FIO low level driver code.

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Definition in file platforms/LPC214x/pal_lld.c.

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pal_lld.h File Reference

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LPC214x FIO low level driver header. -More...

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-Data Structures

struct  lpc214x_fio_setup_t
 FIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define IOPORT1   FIO0Base
 FIO port 0 identifier.
#define IOPORT2   FIO1Base
 FIO port 1 identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 FIO subsystem initialization.
#define pal_lld_readport(port)   ((port)->FIO_PIN)
 Reads an I/O port.
#define pal_lld_readlatch(port)   ((port)->FIO_SET)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->FIO_PIN = (bits))
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)   ((port)->FIO_SET = (bits))
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)   ((port)->FIO_CLR = (bits))
 Clears a bits mask on a I/O port.
#define pal_lld_writegroup(port, mask, offset, bits)
 Writes a value on an I/O bus.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   pal_lld_writegroup(port, 1, pad, bit)
 Writes a logical state on an output pad.
#define pal_lld_lpc214x_set_direction(port, dir)
 FIO port setup.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef FIO * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 LPC214x I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Detailed Description

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LPC214x FIO low level driver header.

- -

Definition in file platforms/LPC214x/pal_lld.h.

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serial_lld.c File Reference

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LPC214x low level serial driver code. -More...

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-Functions

 CH_IRQ_HANDLER (UART0IrqHandler)
 UART0 IRQ handler.
 CH_IRQ_HANDLER (UART1IrqHandler)
 UART1 IRQ handler.
void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 UART0 serial driver identifier.
SerialDriver SD2
 UART1 serial driver identifier.
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Detailed Description

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LPC214x low level serial driver code.

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Definition in file platforms/LPC214x/serial_lld.c.

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LPC214x low level serial driver header. -More...

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_LPC214x_UART0   TRUE
 UART0 driver enable switch.
#define USE_LPC214x_UART1   TRUE
 UART1 driver enable switch.
#define LPC214x_UART_FIFO_PRELOAD   16
 FIFO preload parameter.
#define LPC214x_UART0_PRIORITY   1
 UART0 interrupt priority level setting.
#define LPC214x_UART1_PRIORITY   2
 UART1 interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
-

Detailed Description

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LPC214x low level serial driver header.

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Definition in file platforms/LPC214x/serial_lld.h.

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spi_lld.c File Reference

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LPC214x low level SPI driver code. -More...

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void rw8 (size_t n, const uint8_t *txbuf, uint8_t *rxbuf)
 Synchronous SSP transfer.
void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.

-Variables

SPIDriver SPID1
 SPI1 driver identifier.
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Detailed Description

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LPC214x low level SPI driver code.

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Definition in file platforms/LPC214x/spi_lld.c.

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LPC214x low level SPI driver header. -More...

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-Data Structures

struct  SPIConfig
 Driver configuration structure. More...
struct  SPIDriver
 Structure representing a SPI driver. More...

-Defines

#define USE_LPC214x_SPI1   TRUE
 SPI1 (SSP) driver enable switch.

-Functions

void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.
-

Detailed Description

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LPC214x low level SPI driver header.

- -

Definition in file platforms/LPC214x/spi_lld.h.

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MSP430 HAL subsystem low level driver source. -More...

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void hal_lld_init (void)
 Low level HAL driver initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Detailed Description

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MSP430 HAL subsystem low level driver source.

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Definition in file platforms/MSP430/hal_lld.c.

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#define PLATFORM_NAME   "MSP430x16x"
 Platform name.
#define MSP430_USE_CLOCK   MSP430_CLOCK_SOURCE_XT2CLK
 Clock source.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
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Detailed Description

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MSP430 HAL subsystem low level driver header.

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Definition in file platforms/MSP430/hal_lld.h.

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MSP430 Digital I/O low level driver code. -More...

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void _pal_lld_init (const PALConfig *config)
 MSP430 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
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Detailed Description

-

MSP430 Digital I/O low level driver code.

- -

Definition in file platforms/MSP430/pal_lld.c.

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struct  port_common_t
 Simplified MSP430 I/O port representation. More...
union  __ioport
 Generic MSP430 I/O port. More...
struct  msp430_dio_setup_t
 Setup registers common to all the MSP430 ports. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   8
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFF)
 Whole port mask.
#define IOPORT1   ((ioportid_t)0x0020)
 I/O port A identifier.
#define IOPORT2   ((ioportid_t)0x0028)
 I/O port B identifier.
#define IOPORT3   ((ioportid_t)0x0018)
 I/O port C identifier.
#define IOPORT4   ((ioportid_t)0x001c)
 I/O port D identifier.
#define IOPORT5   ((ioportid_t)0x0030)
 I/O port E identifier.
#define IOPORT6   ((ioportid_t)0x0034)
 I/O port F identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->iop_common.in.reg_p)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->iop_common.out.reg_p)
 Reads the output latch.
#define pal_lld_writeport(port, bits)
 Writes a bits mask on a I/O port.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.

-Typedefs

typedef uint8_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef union __ioport * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 MSP430 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Detailed Description

-

MSP430 Digital I/O low level driver header.

- -

Definition in file platforms/MSP430/pal_lld.h.

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serial_lld.c File Reference

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MSP430 low level serial driver code. -More...

-#include <signal.h>
-#include "ch.h"
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-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 USART0 serial driver identifier.
SerialDriver SD2
 USART1 serial driver identifier.
-

Detailed Description

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MSP430 low level serial driver code.

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Definition in file platforms/MSP430/serial_lld.c.

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MSP430 low level serial driver header. -More...

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_MSP430_USART0   TRUE
 USART0 driver enable switch.
#define USE_MSP430_USART1   TRUE
 USART1 driver enable switch.
#define _serial_driver_data
 SerialDriver specific data.
#define UBR(b)   (SMCLK / (b))
 Macro for baud rate computation.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
-

Detailed Description

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MSP430 low level serial driver header.

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Definition in file platforms/MSP430/serial_lld.h.

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void hal_lld_init (void)
 Low level HAL driver initialization.
void spc563_clock_init (void)
 SPC563 clocks and PLL initialization.
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Detailed Description

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SPC563 HAL subsystem low level driver source.

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Definition in file platforms/SPC56x/hal_lld.c.

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-Defines

#define PLATFORM_NAME   "SPC563M64"
 Platform name.
#define RFD_DIV2   0
#define RFD_DIV4   1
#define RFD_DIV8   2
#define RFD_DIV16   3
#define BIUCR_BANK1_TOO   0x01000000
#define BIUCR_MASTER7_PREFETCH   0x00800000
#define BIUCR_MASTER6_PREFETCH   0x00400000
#define BIUCR_MASTER5_PREFETCH   0x00200000
#define BIUCR_MASTER4_PREFETCH   0x00100000
#define BIUCR_MASTER3_PREFETCH   0x00080000
#define BIUCR_MASTER2_PREFETCH   0x00040000
#define BIUCR_MASTER1_PREFETCH   0x00020000
#define BIUCR_MASTER0_PREFETCH   0x00010000
#define BIUCR_APC_MASK   0x0000E000
#define BIUCR_APC_0   (0 << 13)
#define BIUCR_APC_1   (1 << 13)
#define BIUCR_APC_2   (2 << 13)
#define BIUCR_APC_3   (3 << 13)
#define BIUCR_APC_4   (4 << 13)
#define BIUCR_APC_5   (5 << 13)
#define BIUCR_APC_6   (6 << 13)
#define BIUCR_WWSC_MASK   0x00001800
#define BIUCR_WWSC_0   (0 << 11)
#define BIUCR_WWSC_1   (1 << 11)
#define BIUCR_WWSC_2   (2 << 11)
#define BIUCR_WWSC_3   (3 << 11)
#define BIUCR_RWSC_MASK   0x00001800
#define BIUCR_RWSC_0   (0 << 8)
#define BIUCR_RWSC_1   (1 << 8)
#define BIUCR_RWSC_2   (2 << 8)
#define BIUCR_RWSC_3   (3 << 8)
#define BIUCR_RWSC_4   (4 << 8)
#define BIUCR_RWSC_5   (5 << 8)
#define BIUCR_RWSC_6   (6 << 8)
#define BIUCR_RWSC_7   (7 << 8)
#define BIUCR_DPFEN   0x00000040
#define BIUCR_IPFEN   0x00000010
#define BIUCR_PFLIM_MASK   0x00000060
#define BIUCR_PFLIM_NO   (0 << 1)
#define BIUCR_PFLIM_ON_MISS   (1 << 1)
#define BIUCR_PFLIM_ON_HITMISS   (2 << 1)
#define BIUCR_BFEN   0x00000001
#define SPC563_CLK_BYPASS   FALSE
 Clock bypass.
#define SPC563_ALLOW_OVERCLOCK   FALSE
 Disables the overclock checks.
#define SPC563_CLK_PREDIV   0
 External clock pre-divider.
#define SPC563_CLK_MFD   40
 Multiplication factor divider.
#define SPC563_CLK_RFD   RFD_DIV4
 Reduced frequency divider.
#define SPC563_FLASH_BIUCR
 Flash buffer and prefetching settings.
#define SPC563_PLLCLK   ((EXTCLK / (SPC563_CLK_PREDIV + 1)) * SPC563_CLK_MFD)
 PLL output clock.
#define SPC563_SYSCLK   (SPC563_PLLCLK / (1 << (SPC563_CLK_RFD + 1)))
 PLL output clock.
#define SPC563_FLASH_WS   (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1)
 Flash wait states are a function of the system clock.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void spc563_clock_init (void)
 SPC563 clocks and PLL initialization.
-

Detailed Description

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SPC563 HAL subsystem low level driver header.

- -

Definition in file platforms/SPC56x/hal_lld.h.

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-#include "ch.h"
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-Functions

 CH_IRQ_HANDLER (vector146)
 eSCI-A interrupt handler.
 CH_IRQ_HANDLER (vector149)
 eSCI-B interrupt handler.
void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 eSCI-A serial driver identifier.
SerialDriver SD2
 eSCI-B serial driver identifier.
-

Detailed Description

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SPC563 low level serial driver code.

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Definition in file platforms/SPC56x/serial_lld.c.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define SD_MODE_PARITY   0x03
 Parity field mask.
#define SD_MODE_PARITY_NONE   0x00
 No parity.
#define SD_MODE_PARITY_EVEN   0x01
 Even parity.
#define SD_MODE_PARITY_ODD   0x02
 Odd parity.
#define SD_MODE_NORMAL   0x00
 Normal operations.
#define SD_MODE_LOOPBACK   0x80
 Internal loopback.
#define USE_SPC563_ESCIA   TRUE
 eSCI-A driver enable switch.
#define USE_SPC563_ESCIB   TRUE
 eSCI-B driver enable switch.
#define SPC563_ESCIA_PRIORITY   8
 eSCI-A interrupt priority level setting.
#define SPC563_ESCIB_PRIORITY   8
 eSCI-B interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
-

Detailed Description

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SPC563 low level serial driver header.

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Definition in file platforms/SPC56x/serial_lld.h.

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 CH_IRQ_HANDLER (Vector6C)
 ADC1 DMA interrupt handler (channel 1).
void adc_lld_init (void)
 Low level ADC driver initialization.
void adc_lld_start (ADCDriver *adcp)
 Configures and activates the ADC peripheral.
void adc_lld_stop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
void adc_lld_start_conversion (ADCDriver *adcp)
 Starts an ADC conversion.
void adc_lld_stop_conversion (ADCDriver *adcp)
 Stops an ongoing conversion.

-Variables

ADCDriver ADCD1
 ADC1 driver identifier.
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Detailed Description

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STM32 ADC subsystem low level driver source.

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Definition in file platforms/STM32/adc_lld.c.

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-Data Structures

struct  ADCConversionGroup
 Conversion group configuration structure. More...
struct  ADCConfig
 Driver configuration structure. More...
struct  ADCDriver
 Structure representing an ADC driver. More...

-Defines

#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 17)
 Trigger source.
#define ADC_CR2_EXTSEL_SWSTART   (7 << 17)
 Software trigger.
#define ADC_CHANNEL_IN0   0
 External analog input 0.
#define ADC_CHANNEL_IN1   1
 External analog input 1.
#define ADC_CHANNEL_IN2   2
 External analog input 2.
#define ADC_CHANNEL_IN3   3
 External analog input 3.
#define ADC_CHANNEL_IN4   4
 External analog input 4.
#define ADC_CHANNEL_IN5   5
 External analog input 5.
#define ADC_CHANNEL_IN6   6
 External analog input 6.
#define ADC_CHANNEL_IN7   7
 External analog input 7.
#define ADC_CHANNEL_IN8   8
 External analog input 8.
#define ADC_CHANNEL_IN9   9
 External analog input 9.
#define ADC_CHANNEL_IN10   10
 External analog input 10.
#define ADC_CHANNEL_IN11   11
 External analog input 11.
#define ADC_CHANNEL_IN12   12
 External analog input 12.
#define ADC_CHANNEL_IN13   13
 External analog input 13.
#define ADC_CHANNEL_IN14   14
 External analog input 14.
#define ADC_CHANNEL_IN15   15
 External analog input 15.
#define ADC_CHANNEL_SENSOR   16
 Internal temperature sensor.
#define ADC_CHANNEL_VREFINT   17
 Internal reference.
#define USE_STM32_ADC1   TRUE
 ADC1 driver enable switch.
#define STM32_ADC1_DMA_PRIORITY   3
 ADC1 DMA priority (0..3|lowest..highest).
#define STM32_ADC1_IRQ_PRIORITY   5
 ADC1 interrupt priority level setting.
#define STM32_ADC1_DMA_ERROR_HOOK()   chSysHalt()
 ADC1 DMA error hook.

-Typedefs

typedef uint16_t adcsample_t
 ADC sample data type.
typedef uint16_t adc_channels_num_t
 Channels number in a conversion group.
typedef void(* adccallback_t )(adcsample_t *buffer, size_t n)
 ADC notification callback type.

-Functions

void adc_lld_init (void)
 Low level ADC driver initialization.
void adc_lld_start (ADCDriver *adcp)
 Configures and activates the ADC peripheral.
void adc_lld_stop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
void adc_lld_start_conversion (ADCDriver *adcp)
 Starts an ADC conversion.
void adc_lld_stop_conversion (ADCDriver *adcp)
 Stops an ongoing conversion.
-

Detailed Description

-

STM32 ADC subsystem low level driver header.

- -

Definition in file platforms/STM32/adc_lld.h.

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can_lld.c File Reference

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STM32 CAN subsystem low level driver source. -More...

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-Functions

void can_lld_init (void)
 Low level CAN driver initialization.
void can_lld_start (CANDriver *canp)
 Configures and activates the CAN peripheral.
void can_lld_stop (CANDriver *canp)
 Deactivates the CAN peripheral.
bool_t can_lld_can_transmit (CANDriver *canp)
 Determines whether a frame can be transmitted.
void can_lld_transmit (CANDriver *canp, const CANTxFrame *ctfp)
 Inserts a frame into the transmit queue.
bool_t can_lld_can_receive (CANDriver *canp)
 Determines whether a frame has been received.
void can_lld_receive (CANDriver *canp, CANRxFrame *crfp)
 Receives a frame from the input queue.
void can_lld_sleep (CANDriver *canp)
 Enters the sleep mode.
void can_lld_wakeup (CANDriver *canp)
 Enforces leaving the sleep mode.

-Variables

CANDriver CAND1
 ADC1 driver identifier.
-

Detailed Description

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STM32 CAN subsystem low level driver source.

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Definition in file platforms/STM32/can_lld.c.

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can_lld.h File Reference

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STM32 CAN subsystem low level driver header. -More...

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-Data Structures

struct  CANTxFrame
 CAN transmission frame. More...
struct  CANRxFrame
 CAN received frame. More...
struct  CANFilter
 CAN filter. More...
struct  CANConfig
 Driver configuration structure. More...
struct  CANDriver
 Structure representing an CAN driver. More...

-Defines

#define CAN_SUPPORTS_SLEEP   TRUE
 This switch defines whether the driver implementation supports a low power switch mode with automatic an wakeup feature.
#define CAN_MAX_FILTERS   28
 Minimum number of CAN filters.
#define CAN_BTR_BRP(n)   (n)
 BRP field macro.
#define CAN_BTR_TS1(n)   ((n) << 16)
 TS1 field macro.
#define CAN_BTR_TS2(n)   ((n) << 20)
 TS2 field macro.
#define CAN_BTR_SJW(n)   ((n) << 24)
 SJW field macro.
#define CAN_IDE_STD   0
 Standard id.
#define CAN_IDE_EXT   1
 Extended id.
#define CAN_RTR_DATA   0
 Data frame.
#define CAN_RTR_REMOTE   1
 Remote frame.
#define USE_STM32_CAN1   TRUE
 CAN1 driver enable switch.
#define STM32_CAN1_IRQ_PRIORITY   11
 CAN1 interrupt priority level setting.

-Typedefs

typedef uint32_t canstatus_t
 CAN status flags.

-Functions

void can_lld_init (void)
 Low level CAN driver initialization.
void can_lld_start (CANDriver *canp)
 Configures and activates the CAN peripheral.
void can_lld_stop (CANDriver *canp)
 Deactivates the CAN peripheral.
bool_t can_lld_can_transmit (CANDriver *canp)
 Determines whether a frame can be transmitted.
void can_lld_transmit (CANDriver *canp, const CANTxFrame *ctfp)
 Inserts a frame into the transmit queue.
bool_t can_lld_can_receive (CANDriver *canp)
 Determines whether a frame has been received.
void can_lld_receive (CANDriver *canp, CANRxFrame *crfp)
 Receives a frame from the input queue.
-

Detailed Description

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STM32 CAN subsystem low level driver header.

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Definition in file platforms/STM32/can_lld.h.

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hal_lld.c File Reference

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STM32 HAL subsystem low level driver source. -More...

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-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void stm32_clock_init (void)
 STM32 clocks and PLL initialization.

-Variables

const PALConfig pal_default_config
 PAL setup.
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Detailed Description

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STM32 HAL subsystem low level driver source.

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Definition in file platforms/STM32/hal_lld.c.

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hal_lld.h File Reference

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STM32 HAL subsystem low level driver header. -More...

-#include "stm32f10x.h"
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-Defines

#define PLATFORM_NAME   "STM32 MD"
 Platform name.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
void stm32_clock_init (void)
 STM32 clocks and PLL initialization.
-

Detailed Description

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STM32 HAL subsystem low level driver header.

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Definition in file platforms/STM32/hal_lld.h.

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pal_lld.c File Reference

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STM32 GPIO low level driver code. -More...

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void _pal_lld_init (const PALConfig *config)
 STM32 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
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Detailed Description

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STM32 GPIO low level driver code.

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Definition in file platforms/STM32/pal_lld.c.

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STM32 GPIO low level driver header. -More...

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-Data Structures

struct  stm32_gpio_setup_t
 GPIO port setup info. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_MODE_STM32_ALTERNATE_PUSHPULL   16
 STM32 specific alternate push-pull output mode.
#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN   17
 STM32 specific alternate open-drain output mode.
#define PAL_IOPORTS_WIDTH   16
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFFF)
 Whole port mask.
#define IOPORT1   GPIOA
 GPIO port A identifier.
#define IOPORT2   GPIOB
 GPIO port B identifier.
#define IOPORT3   GPIOC
 GPIO port C identifier.
#define IOPORT4   GPIOD
 GPIO port D identifier.
#define IOPORT5   GPIOE
 GPIO port E identifier.
#define IOPORT6   GPIOF
 GPIO port F identifier.
#define IOPORT7   GPIOG
 GPIO port G identifier.
#define pal_lld_init(config)   _pal_lld_init(config)
 GPIO ports subsystem initialization.
#define pal_lld_readport(port)   ((port)->IDR)
 Reads an I/O port.
#define pal_lld_readlatch(port)   ((port)->ODR)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->ODR = (bits))
 Writes on a I/O port.
#define pal_lld_setport(port, bits)   ((port)->BSRR = (bits))
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)   ((port)->BRR = (bits))
 Clears a bits mask on a I/O port.
#define pal_lld_writegroup(port, mask, offset, bits)
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_writepad(port, pad, bit)   pal_lld_writegroup(port, 1, pad, bit)
 Writes a logical state on an output pad.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef GPIO_TypeDef * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_init (const PALConfig *config)
 STM32 I/O ports configuration.
void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

const PALConfig pal_default_config
 PAL setup.
-

Detailed Description

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STM32 GPIO low level driver header.

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Definition in file platforms/STM32/pal_lld.h.

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pwm_lld.c File Reference

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STM32 PWM subsystem low level driver header. -More...

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-Functions

void pwm_lld_init (void)
 Low level PWM driver initialization.
void pwm_lld_start (PWMDriver *pwmp)
 Configures and activates the PWM peripheral.
void pwm_lld_stop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
void pwm_lld_enable_channel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwm_lld_disable_channel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.

-Variables

PWMDriver PWMD1
 PWM1 driver identifier.
PWMDriver PWMD2
 PWM2 driver identifier.
PWMDriver PWMD3
 PWM3 driver identifier.
PWMDriver PWMD4
 PWM4 driver identifier.
-

Detailed Description

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STM32 PWM subsystem low level driver header.

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Definition in file platforms/STM32/pwm_lld.c.

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pwm_lld.h File Reference

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STM32 PWM subsystem low level driver header. -More...

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-Data Structures

struct  PWMChannelConfig
 PWM driver channel configuration structure. More...
struct  PWMConfig
 Driver configuration structure. More...
struct  PWMDriver
 Structure representing an PWM driver. More...

-Defines

#define PWM_CHANNELS   4
 Number of PWM channels per PWM driver.
#define USE_STM32_PWM1   TRUE
 PWM1 driver enable switch.
#define USE_STM32_PWM2   TRUE
 PWM2 driver enable switch.
#define USE_STM32_PWM3   TRUE
 PWM3 driver enable switch.
#define USE_STM32_PWM4   TRUE
 PWM4 driver enable switch.
#define STM32_PWM1_IRQ_PRIORITY   7
 PWM1 interrupt priority level setting.
#define STM32_PWM2_IRQ_PRIORITY   7
 PWM2 interrupt priority level setting.
#define STM32_PWM3_IRQ_PRIORITY   7
 PWM3 interrupt priority level setting.
#define STM32_PWM4_IRQ_PRIORITY   7
 PWM4 interrupt priority level setting.
#define PWM_COMPUTE_PSC(clksrc, pwmclk)   ((uint16_t)(((clksrc) / (pwmclk)) - 1))
 PWM clock prescaler initialization utility.
#define PWM_COMPUTE_ARR(pwmclk, pwmperiod)   ((uint16_t)(((pwmclk) / (1000000000 / (pwmperiod))) - 1))
 PWM cycle period initialization utility.
#define PWM_FRACTION_TO_WIDTH(pwmp, numerator, denominator)
 Converts from fraction to pulse width.
#define PWM_DEGREES_TO_WIDTH(pwmp, degrees)   PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees)
 Converts from degrees to pulse width.
#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage)   PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage)
 Converts from percentage to pulse width.

-Typedefs

typedef uint8_t pwmchannel_t
 PWM channel type.
typedef uint16_t pwmcnt_t
 PWM counter type.
typedef struct PWMDriver PWMDriver
 Type of a structure representing an PWM driver.
typedef void(* pwmcallback_t )(PWMDriver *pwmp)
 PWM notification callback type.

-Functions

void pwm_lld_init (void)
 Low level PWM driver initialization.
void pwm_lld_start (PWMDriver *pwmp)
 Configures and activates the PWM peripheral.
void pwm_lld_stop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
void pwm_lld_enable_channel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwm_lld_disable_channel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.
-

Detailed Description

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STM32 PWM subsystem low level driver header.

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Definition in file platforms/STM32/pwm_lld.h.

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serial_lld.c File Reference

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STM32 low level serial driver code. -More...

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-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 USART1 serial driver identifier.
SerialDriver SD2
 USART2 serial driver identifier.
SerialDriver SD3
 USART3 serial driver identifier.
SerialDriver SD4
 UART4 serial driver identifier.
SerialDriver SD5
 UART5 serial driver identifier.
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Detailed Description

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STM32 low level serial driver code.

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Definition in file platforms/STM32/serial_lld.c.

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serial_lld.h File Reference

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STM32 low level serial driver header. -More...

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define USE_STM32_USART1   TRUE
 USART1 driver enable switch.
#define USE_STM32_USART2   TRUE
 USART2 driver enable switch.
#define USE_STM32_USART3   TRUE
 USART3 driver enable switch.
#define USE_STM32_UART4   TRUE
 UART4 driver enable switch.
#define USE_STM32_UART5   TRUE
 UART5 driver enable switch.
#define STM32_USART1_PRIORITY   12
 USART1 interrupt priority level setting.
#define STM32_USART2_PRIORITY   12)
 USART2 interrupt priority level setting.
#define STM32_USART3_PRIORITY   12
 USART3 interrupt priority level setting.
#define STM32_UART4_PRIORITY   12
 UART4 interrupt priority level setting.
#define STM32_UART5_PRIORITY   12
 UART5 interrupt priority level setting.
#define _serial_driver_data
 SerialDriver specific data.
#define USART_CR2_STOP1_BITS   (0 << 12)
 CR2 1 stop bit value.
#define USART_CR2_STOP0P5_BITS   (1 << 12)
 CR2 0.5 stop bit value.
#define USART_CR2_STOP2_BITS   (2 << 12)
 CR2 2 stop bit value.
#define USART_CR2_STOP1P5_BITS   (3 << 12)
 CR2 1.5 stop bit value.

-Typedefs

typedef uint32_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
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Detailed Description

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STM32 low level serial driver header.

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Definition in file platforms/STM32/serial_lld.h.

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spi_lld.c File Reference

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STM32 SPI subsystem low level driver source. -More...

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 CH_IRQ_HANDLER (Vector70)
 SPI1 RX DMA interrupt handler (channel 2).
 CH_IRQ_HANDLER (Vector74)
 SPI1 TX DMA interrupt handler (channel 3).
 CH_IRQ_HANDLER (Vector78)
 SPI2 RX DMA interrupt handler (channel 4).
 CH_IRQ_HANDLER (Vector7C)
 SPI2 TX DMA interrupt handler (channel 5).
void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.

-Variables

SPIDriver SPID1
 SPI1 driver identifier.
SPIDriver SPID2
 SPI2 driver identifier.
-

Detailed Description

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STM32 SPI subsystem low level driver source.

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Definition in file platforms/STM32/spi_lld.c.

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-Data Structures

struct  SPIConfig
 Driver configuration structure. More...
struct  SPIDriver
 Structure representing a SPI driver. More...

-Defines

#define USE_STM32_SPI1   TRUE
 SPI1 driver enable switch.
#define USE_STM32_SPI2   TRUE
 SPI2 driver enable switch.
#define STM32_SPI1_DMA_PRIORITY   2
 SPI1 DMA priority (0..3|lowest..highest).
#define STM32_SPI2_DMA_PRIORITY   2
 SPI2 DMA priority (0..3|lowest..highest).
#define STM32_SPI1_IRQ_PRIORITY   10
 SPI1 interrupt priority level setting.
#define STM32_SPI2_IRQ_PRIORITY   10
 SPI2 interrupt priority level setting.
#define STM32_SPI1_DMA_ERROR_HOOK()   chSysHalt()
 SPI1 DMA error hook.
#define STM32_SPI2_DMA_ERROR_HOOK()   chSysHalt()
 SPI2 DMA error hook.

-Functions

void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.
-

Detailed Description

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STM32 SPI subsystem low level driver header.

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Definition in file platforms/STM32/spi_lld.h.

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hal_lld.c File Reference

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STM8 HAL subsystem low level driver source. -More...

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void hal_lld_init (void)
 Low level HAL driver initialization.

-Variables

ROMCONST PALConfig pal_default_config
 PAL setup.
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Detailed Description

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STM8 HAL subsystem low level driver source.

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Definition in file platforms/STM8/hal_lld.c.

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-Defines

#define PLATFORM_NAME   "STM8x"
 Platform name.
#define LSICLK   128000
#define HSICLK   16000000
#define CLK_SOURCE_DEFAULT   0
#define CLK_SOURCE_HSI   0xE1
#define CLK_SOURCE_LSI   0xD2
#define CLK_SOURCE_HSE   0xB4
#define CLK_HSI_DIV1   0
#define CLK_HSI_DIV2   1
#define CLK_HSI_DIV4   2
#define CLK_HSI_DIV8   3
#define CLK_CPU_DIV1   0
#define CLK_CPU_DIV2   1
#define CLK_CPU_DIV4   2
#define CLK_CPU_DIV8   3
#define CLK_CPU_DIV16   4
#define CLK_CPU_DIV32   5
#define CLK_CPU_DIV64   6
#define CLK_CPU_DIV128   7
#define STM8_CLOCK_SOURCE   CLK_SOURCE_DEFAULT
 Clock source setting.
#define STM8_HSI_DIVIDER   CLK_HSI_DIV8
 HSI clock divider.
#define STM8_CPU_DIVIDER   CLK_CPU_DIV1
 CPU clock divider.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
-

Detailed Description

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STM8 HAL subsystem low level driver source.

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Definition in file platforms/STM8/hal_lld.h.

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pal_lld.c File Reference

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STM8 GPIO low level driver code. -More...

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void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.
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Detailed Description

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STM8 GPIO low level driver code.

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Definition in file platforms/STM8/pal_lld.c.

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pal_lld.h File Reference

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STM8 GPIO low level driver header. -More...

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-Data Structures

struct  gpio_t
 GPIO port representation. More...
struct  PALConfig
 AT91SAM7 PIO static initializer. More...

-Defines

#define PAL_MODE_OUTPUT_PUSHPULL_SLOW   16
 STM8 specific alternate push-pull slow output mode.
#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW   17
 STM8 specific alternate open-drain slow output mode.
#define PAL_IOPORTS_WIDTH   8
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFF)
 Whole port mask.
#define IOPORTS   ((PALConfig *)0x5000)
 GPIO ports as a whole.
#define IOPORT1   ((gpio_t *)0x5000)
 GPIO port A identifier.
#define IOPORT2   ((gpio_t *)0x5005)
 GPIO port B identifier.
#define IOPORT3   ((gpio_t *)0x500A)
 GPIO port C identifier.
#define IOPORT4   ((gpio_t *)0x500F)
 GPIO port D identifier.
#define IOPORT5   ((gpio_t *)0x5014)
 GPIO port E identifier.
#define IOPORT6   ((gpio_t *)0x5019)
 GPIO port F identifier.
#define IOPORT7   ((gpio_t *)0x501E)
 GPIO port G identifier.
#define IOPORT8   ((gpio_t *)0x5023)
 GPIO port H identifier.
#define IOPORT9   ((gpio_t *)0x5028)
 GPIO port I identifier.
#define pal_lld_init(config)   *IOPORTS = *(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)   ((port)->IDR)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)   ((port)->ODR)
 Reads the output latch.
#define pal_lld_writeport(port, bits)   ((port)->ODR = (bits))
 Writes a bits mask on a I/O port.
#define pal_lld_setgroupmode(port, mask, mode)   _pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.

-Typedefs

typedef uint8_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef gpio_t * ioportid_t
 Port Identifier.

-Functions

void _pal_lld_setgroupmode (ioportid_t port, ioportmask_t mask, uint_fast8_t mode)
 Pads mode setup.

-Variables

ROMCONST PALConfig pal_default_config
 PAL setup.
-

Detailed Description

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STM8 GPIO low level driver header.

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Definition in file platforms/STM8/pal_lld.h.

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serial_lld.c File Reference

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STM8 low level serial driver code. -More...

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-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.

-Variables

SerialDriver SD1
 UART1 serial driver identifier.
SerialDriver SD3
 UART3 serial driver identifier.
-

Detailed Description

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STM8 low level serial driver code.

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Definition in file platforms/STM8/serial_lld.c.

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define SD_MODE_PARITY   0x07
 Parity field mask.
#define SD_MODE_PARITY_NONE   0x00
 No parity.
#define SD_MODE_PARITY_EVEN   0x05
 Even parity.
#define SD_MODE_PARITY_ODD   0x07
 Odd parity.
#define SD_MODE_STOP   0x30
 Stop bits mask.
#define SD_MODE_STOP_1   0x00
 One stop bit.
#define SD_MODE_STOP_2   0x20
 Two stop bits.
#define SD_MODE_STOP_1P5   0x30
 1.5 stop bits.
#define USE_STM8_UART1   TRUE
 UART1 driver enable switch.
#define USE_STM8_UART3   TRUE
 UART3 driver enable switch.
#define _serial_driver_data
 SerialDriver specific data.
#define BBR(b)   (SYSCLK / (b))
 Macro for baud rate computation.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
-

Detailed Description

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STM8 low level serial driver header.

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Definition in file platforms/STM8/serial_lld.h.

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void port_halt (void)
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ARM7 architecture port code.

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Port related code.

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Definition in file ports/GCC/ARM7/chcore.c.

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-Defines

#define ENABLE_WFI_IDLE   0
 If enabled allows the idle thread to enter a low power mode.
#define CH_ARCHITECTURE_ARM7
 Macro defining the ARM7 architecture.
#define CH_ARCHITECTURE_NAME   "ARM"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "ARM7TDMI"
 Name of the architecture variant (optional).
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   4
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   0x10
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   __attribute__((naked)) void id(void)
 IRQ handler function declaration.
#define PORT_FAST_IRQ_HANDLER(id)   __attribute__((interrupt("FIQ"))) void id(void)
 Fast IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   asm volatile ("msr CPSR_c, #0x9F" : : : "memory")
 Kernel-lock action.
#define port_unlock()   asm volatile ("msr CPSR_c, #0x1F" : : : "memory")
 Kernel-unlock action.
#define port_lock_from_isr()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()
 Kernel-unlock action from an interrupt handler.
#define port_disable()
 Disables all the interrupt sources.
#define port_suspend()   asm volatile ("msr CPSR_c, #0x9F" : : : "memory")
 Disables the interrupt sources below kernel-level priority.
#define port_enable()   asm volatile ("msr CPSR_c, #0x1F" : : : "memory")
 Enables all the interrupt sources.
#define port_switch(ntp, otp)
 Performs a context switch between two threads.

-Typedefs

typedef uint32_t stkalign_t
 32 bits stack and memory alignment enforcement.
typedef void * regarm_t
 Generic ARM register.

-Functions

void port_halt (void)
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

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ARM7 architecture port macros and structures.

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Port related structures and macros.

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Definition in file ports/GCC/ARM7/chcore.h.

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#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef int32_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint32_t tprio_t
typedef int32_t msg_t
typedef int32_t eventid_t
typedef uint32_t eventmask_t
typedef uint32_t systime_t
typedef int32_t cnt_t
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ARM7 architecture port system types.

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Port types.

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Definition in file ports/GCC/ARM7/chtypes.h.

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 Halts the system.
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-Defines

#define CORTEX_M0   0
 Cortex-M0 variant.
#define CORTEX_M1   1
 Cortex-M1 variant.
#define CORTEX_M3   3
 Cortex-M3 variant.
#define CORTEX_M4   4
 Cortex-M4 variant.
#define CORTEX_PRIORITY_LEVELS   (1 << CORTEX_PRIORITY_BITS)
 Total priority levels.
#define CORTEX_MINIMUM_PRIORITY   (CORTEX_PRIORITY_LEVELS - 1)
 Minimum priority level.
#define CORTEX_MAXIMUM_PRIORITY   0
 Maximum priority level.
#define CORTEX_BASEPRI_DISABLED   0
 Disabled value for BASEPRI register.
#define CORTEX_IS_VALID_PRIORITY(n)   (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
 Priority level verification macro.
#define CORTEX_PRIORITY_MASK(n)   ((n) << (8 - CORTEX_PRIORITY_BITS))
 Priority level to priority mask conversion macro.
#define CORTEX_ENABLE_WFI_IDLE   FALSE
 Enables the use of the WFI instruction in the idle thread loop.
#define CORTEX_PRIORITY_SYSTICK   (CORTEX_PRIORITY_LEVELS >> 1)
 SYSTICK handler priority.
#define CORTEX_PRIORITY_SVCALL   (CORTEX_MAXIMUM_PRIORITY + 1)
 SVCALL handler priority.
#define CORTEX_PRIORITY_PENDSV   CORTEX_MINIMUM_PRIORITY
 PENDSV handler priority.
#define CORTEX_BASEPRI_KERNEL   CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
 BASEPRI level within kernel lock.
#define CORTEX_STACK_ALIGNMENT   64
 Stack alignment enforcement.
#define CH_ARCHITECTURE_ARM
 Macro defining a generic ARM architecture.
#define CH_ARCHITECTURE_ARM_vxm
 Macro defining the specific ARM architecture.
#define CH_ARCHITECTURE_NAME   "ARMvx-M"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "Cortex-Mx"
 Name of the architecture variant (optional).
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.

-Typedefs

typedef uint64_t stkalign_t __attribute__ ((aligned(8)))
 Stack and memory alignment enforcement.
typedef void * regarm_t
 Generic ARM register.
-

Detailed Description

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ARM Cortex-Mx port macros and structures.

- -

Definition in file ports/GCC/ARMCMx/chcore.h.

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-Defines

#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef int32_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint32_t tprio_t
typedef int32_t msg_t
typedef int32_t eventid_t
typedef uint32_t eventmask_t
typedef uint32_t systime_t
typedef int32_t cnt_t
-

Detailed Description

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ARM Cortex-Mx port system types.

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Definition in file ports/GCC/ARMCMx/chtypes.h.

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void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void port_halt (void)
 Halts the system.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

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AVR architecture port code.

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Port related code.

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Definition in file ports/GCC/AVR/chcore.c.

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-Defines

#define ENABLE_WFI_IDLE   0
 If enabled allows the idle thread to enter a low power mode.
#define CH_ARCHITECTURE_AVR
 Macro defining the AVR architecture.
#define CH_ARCHITECTURE_NAME   "AVR"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "MegaAVR"
 Name of the architecture variant (optional).
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   8
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   32
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   ISR(id)
 IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   asm volatile ("cli" : : : "memory")
 Kernel-lock action.
#define port_unlock()   asm volatile ("sei" : : : "memory")
 Kernel-unlock action.
#define port_lock_from_isr()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   asm volatile ("cli" : : : "memory")
 Disables all the interrupt sources.
#define port_suspend()   asm volatile ("cli" : : : "memory")
 Disables the interrupt sources below kernel-level priority.
#define port_enable()   asm volatile ("sei" : : : "memory")
 Enables all the interrupt sources.
#define port_wait_for_interrupt()
 Enters an architecture-dependent IRQ-waiting mode.

-Typedefs

typedef uint8_t stkalign_t
 8 bits stack and memory alignment enforcement.

-Functions

void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void port_halt (void)
 Halts the system.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

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AVR architecture port macros and structures.

-

Port related structures and macros.

- -

Definition in file ports/GCC/AVR/chcore.h.

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-Defines

#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef int8_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint8_t tprio_t
typedef int16_t msg_t
typedef uint8_t eventid_t
typedef uint8_t eventmask_t
typedef uint16_t systime_t
typedef int8_t cnt_t
-

Detailed Description

-

AVR architecture port system types.

-

Port types.

- -

Definition in file ports/GCC/AVR/chtypes.h.

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void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void port_halt (void)
 Halts the system.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

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MSP430 architecture port code.

-

Port related code.

- -

Definition in file ports/GCC/MSP430/chcore.c.

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-#include <iomacros.h>
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-Defines

#define ENABLE_WFI_IDLE   0
 Enables the use of a wait state in the idle thread loop.
#define CH_ARCHITECTURE_MSP430
 Macro defining the MSP430 architecture.
#define CH_ARCHITECTURE_NAME   "MSP430"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "MSP430"
 Name of the architecture variant (optional).
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   0
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   32
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   interrupt(id) _vect_##id(void)
 IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   asm volatile ("dint" : : : "memory")
 Kernel-lock action.
#define port_unlock()   asm volatile ("eint" : : : "memory")
 Kernel-unlock action.
#define port_lock_from_isr()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   asm volatile ("dint" : : : "memory")
 Disables all the interrupt sources.
#define port_suspend()   asm volatile ("dint" : : : "memory")
 Disables the interrupt sources below kernel-level priority.
#define port_enable()   asm volatile ("eint" : : : "memory")
 Enables all the interrupt sources.
#define port_wait_for_interrupt()
 Enters an architecture-dependent IRQ-waiting mode.

-Typedefs

typedef uint16_t stkalign_t
 16 bits stack and memory alignment enforcement.
typedef void * regmsp_t
 Generic MSP430 register.

-Functions

void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void port_halt (void)
 Halts the system.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

-

MSP430 architecture port macros and structures.

-

Port related structures and macros.

- -

Definition in file ports/GCC/MSP430/chcore.h.

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-#include <stddef.h>
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-Defines

#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef int16_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint16_t tprio_t
typedef int16_t msg_t
typedef int16_t eventid_t
typedef uint16_t eventmask_t
typedef uint16_t systime_t
typedef int16_t cnt_t
-

Detailed Description

-

MSP430 architecture port system types.

-

Port types.

- -

Definition in file ports/GCC/MSP430/chtypes.h.

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PowerPC architecture port code. -More...

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-Functions

void port_halt (void)
 Halts the system.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Start a thread by invoking its work function.
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Detailed Description

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PowerPC architecture port code.

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Definition in file ports/GCC/PPC/chcore.c.

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-Data Structures

struct  stkalign_t
 Base type for stack and memory alignment. More...
struct  eabi_frame
 Mandatory part of a stack frame. More...

-Defines

#define ENABLE_WFI_IDLE   0
 Enables the use of the WFI instruction.
#define PPC_VARIANT_e200z3   3
#define PPC_VARIANT_e200z4   4
#define PPC_VARIANT   PPC_VARIANT_e200z3
 Core variant selector.
#define CH_ARCHITECTURE_PPC
 Unique macro for the implemented architecture.
#define CH_ARCHITECTURE_NAME   "PowerPC"
 Name of the implemented architecture.
#define CH_CORE_VARIANT_NAME   "e200z3"
 Name of the architecture variant.
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   0
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   128
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void id(void)
 IRQ handler function declaration.
#define port_init()
 Kernel port layer initialization.
#define port_lock()   asm volatile ("wrteei 0" : : : "memory")
#define port_unlock()   asm volatile("wrteei 1" : : : "memory")
#define port_lock_from_isr()
#define port_unlock_from_isr()
#define port_disable()   asm volatile ("wrteei 0" : : : "memory")
#define port_suspend()   asm volatile ("wrteei 0" : : : "memory")
#define port_enable()   asm volatile ("wrteei 1" : : : "memory")
#define port_wait_for_interrupt()

-Typedefs

typedef void * regppc_t
 Generic PPC register.

-Functions

void port_halt (void)
 Halts the system.
void port_switch (Thread *ntp, Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Start a thread by invoking its work function.
-

Detailed Description

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PowerPC architecture port macros and structures.

- -

Definition in file ports/GCC/PPC/chcore.h.

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-Defines

#define INLINE   inline
 Inline function modifier.
#define ROMCONST   const
 ROM constant modifier.
#define PACK_STRUCT_STRUCT   __attribute__((packed))
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef volatile int8_t vint8_t
typedef volatile uint8_t vuint8_t
typedef volatile int16_t vint16_t
typedef volatile uint16_t vuint16_t
typedef volatile int32_t vint32_t
typedef volatile uint32_t vuint32_t
typedef int32_t bool_t
typedef uint8_t tmode_t
typedef uint8_t tstate_t
typedef uint8_t trefs_t
typedef uint32_t tprio_t
typedef int32_t msg_t
typedef int32_t eventid_t
typedef uint32_t eventmask_t
typedef uint32_t systime_t
typedef int32_t cnt_t
-

Detailed Description

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PowerPC architecture port system types.

- -

Definition in file ports/GCC/PPC/chtypes.h.

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-Functions

void _port_switch (Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Thread start code.
void port_halt (void)
 Halts the system.

-Variables

page0 ReadyList rlist
 Ready list header.
-

Detailed Description

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STM8 architecture port code.

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Port related code.

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Definition in file ports/RC/STM8/chcore.c.

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struct  stm8_startctx
 Start context. More...
struct  ReadyList
 Ready list header. More...

-Defines

#define STM8_ENABLE_WFI_IDLE   FALSE
 Enables the use of the WFI instruction in the idle thread loop.
#define CH_ARCHITECTURE_STM8
 Unique macro for the implemented architecture.
#define CH_ARCHITECTURE_NAME   "STM8"
 Name of the implemented architecture.
#define SETUP_CONTEXT(workspace, wsize, pf, arg)
 Platform dependent part of the chThdInit() API.
#define IDLE_THREAD_STACK_SIZE   0
 Stack size for the system idle thread.
#define INT_REQUIRED_STACK   32
 Per-thread stack overhead for interrupts servicing.
#define STACK_ALIGN(n)   ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
 Enforces a correct alignment for a stack area size value.
#define THD_WA_SIZE(n)
 Computes the thread working area global size.
#define WORKING_AREA(s, n)   stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
 Static working area allocation.
#define PORT_IRQ_PROLOGUE()
 IRQ prologue code.
#define PORT_IRQ_EPILOGUE()
 IRQ epilogue code.
#define PORT_IRQ_HANDLER(id)   void irq##id(void) interrupt id
 IRQ handler function declaration.
#define port_init()
 Port-related initialization code.
#define port_lock()   _sim_()
 Kernel-lock action.
#define port_unlock()   _rim_()
 Kernel-unlock action.
#define port_lock_from_isr()
 Kernel-lock action from an interrupt handler.
#define port_unlock_from_isr()
 Kernel-unlock action from an interrupt handler.
#define port_disable()   _sim_()
 Disables all the interrupt sources.
#define port_suspend()   _sim_()
 Disables the interrupt sources that are not supposed to preempt the kernel.
#define port_enable()   _rim_()
 Enables all the interrupt sources.
#define port_wait_for_interrupt()   _wfi_()
 Enters an architecture-dependent halt mode.
#define port_switch(ntp, otp)   _port_switch(otp)
 Performs a context switch between two threads.

-Typedefs

typedef uint8_t stkalign_t
 Base type for stack alignment.
typedef void(* stm8func_t )(void)
 Generic STM8 function pointer.

-Functions

void port_halt (void)
 Halts the system.
void _port_switch (Thread *otp)
 Performs a context switch between two threads.
void _port_thread_start (void)
 Thread start code.

-Variables

page0 ReadyList rlist
 Ready list header.
-

Detailed Description

-

STM8 architecture port macros and structures.

-

Port related structures and macros.

- -

Definition in file ports/RC/STM8/chcore.h.

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-Defines

#define INLINE   inline
 Inline function modifier.
#define ROMCONST   code
 ROM constant modifier.
#define PACK_STRUCT_STRUCT
 Packed structure modifier (within).
#define PACK_STRUCT_BEGIN
 Packed structure modifier (before).
#define PACK_STRUCT_END
 Packed structure modifier (after).

-Typedefs

typedef unsigned char uint8_t
typedef signed char int8_t
typedef unsigned int uint16_t
typedef signed int int16_t
typedef unsigned long uint32_t
typedef signed long int32_t
typedef uint8_t uint_fast8_t
typedef uint16_t uint_fast16_t
typedef uint32_t uint_fast32_t
typedef int8_t bool_t
 Boolean, recommended the fastest signed.
typedef uint8_t tmode_t
 Thread mode flags, uint8_t is ok.
typedef uint8_t tstate_t
 Thread state, uint8_t is ok.
typedef uint8_t trefs_t
 Thread references counter, uint8_t is ok.
typedef uint8_t tprio_t
 Priority, use the fastest unsigned type.
typedef int16_t msg_t
 Message, use signed pointer equivalent.
typedef int8_t eventid_t
 Event Id, use fastest signed.
typedef uint8_t eventmask_t
 Event Mask, recommended fastest unsigned.
typedef uint16_t systime_t
 System Time, recommended fastest unsigned.
typedef int16_t cnt_t
 Counter, recommended fastest signed.
-

Detailed Description

-

STM8 port system types.

-

Port types.

- -

Definition in file ports/RC/STM8/chtypes.h.

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void pwmInit (void)
 PWM Driver initialization.
void pwmObjectInit (PWMDriver *pwmp)
 Initializes the standard part of a PWMDriver structure.
void pwmStart (PWMDriver *pwmp, const PWMConfig *config)
 Configures and activates the PWM peripheral.
void pwmStop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
void pwmEnableChannel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwmDisableChannel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.
-

Detailed Description

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PWM Driver code.

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Definition in file pwm.c.

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pwm.h File Reference

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PWM Driver macros and structures. -More...

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-Defines

#define pwmEnableChannelI(pwmp, channel, width)   pwm_lld_enable_channel(pwmp, channel, width)
 Enables a PWM channel.
#define pwmDisableChannelI(pwmp, channel)   pwm_lld_disable_channel(pwmp, channel)
 Disables a PWM channel.

-Enumerations

enum  pwmstate_t { PWM_UNINIT = 0, -PWM_STOP = 1, -PWM_READY = 2 - }
 

Driver state machine possible states.

- More...
enum  pwmmode_t { PWM_OUTPUT_DISABLED = 0, -PWM_OUTPUT_ACTIVE_HIGH = 1, -PWM_OUTPUT_ACTIVE_LOW = 2 - }
 

PWM logic mode.

- More...

-Functions

void pwmInit (void)
 PWM Driver initialization.
void pwmObjectInit (PWMDriver *pwmp)
 Initializes the standard part of a PWMDriver structure.
void pwmStart (PWMDriver *pwmp, const PWMConfig *config)
 Configures and activates the PWM peripheral.
void pwmStop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
void pwmEnableChannel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwmDisableChannel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.
-

Detailed Description

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PWM Driver macros and structures.

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Definition in file pwm.h.

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serial.c File Reference

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Serial Driver code. -More...

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-Functions

void sdInit (void)
 Serial Driver initialization.
void sdObjectInit (SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify)
 Initializes a generic full duplex driver object.
void sdStart (SerialDriver *sdp, const SerialConfig *config)
 Configures and starts the driver.
void sdStop (SerialDriver *sdp)
 Stops the driver.
void sdIncomingDataI (SerialDriver *sdp, uint8_t b)
 Handles incoming data.
msg_t sdRequestDataI (SerialDriver *sdp)
 Handles outgoing data.
void sdAddFlagsI (SerialDriver *sdp, sdflags_t mask)
 Handles communication events/errors.
sdflags_t sdGetAndClearFlags (SerialDriver *sdp)
 Returns and clears the errors mask associated to the driver.
-

Detailed Description

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Serial Driver code.

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Definition in file serial.c.

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serial.h File Reference

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Serial Driver macros and structures. -More...

-#include "serial_lld.h"
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-Data Structures

struct  SerialDriverVMT
 SerialDriver virtual methods table. More...
struct  _SerialDriver
 Full duplex serial driver class. More...

-Defines

#define SD_NO_ERROR   0
 No pending conditions.
#define SD_CONNECTED   1
 Connection happened.
#define SD_DISCONNECTED   2
 Disconnection happened.
#define SD_PARITY_ERROR   4
 Parity error happened.
#define SD_FRAMING_ERROR   8
 Framing error happened.
#define SD_OVERRUN_ERROR   16
 Overflow happened.
#define SD_NOISE_ERROR   32
 Noise on the line.
#define SD_BREAK_DETECTED   64
 Break detected.
#define SERIAL_DEFAULT_BITRATE   38400
 Default bit rate.
#define SERIAL_BUFFERS_SIZE   64
 Serial buffers size.
#define _serial_driver_methods   _base_asynchronous_channel_methods
 SerialDriver specific methods.
#define sdPutWouldBlock(sdp)   chOQIsFull(&(sdp)->oqueue)
 Direct output check on a SerialDriver.
#define sdGetWouldBlock(sdp)   chIQIsEmpty(&(sdp)->iqueue)
 Direct input check on a SerialDriver.
#define sdPut(sdp, b)   chOQPut(&(sdp)->oqueue, b)
 Direct write to a SerialDriver.
#define sdPutTimeout(sdp, b, t)   chOQPutTimeout(&(sdp)->iqueue, b, t)
 Direct write to a SerialDriver with timeout specification.
#define sdGet(sdp)   chIQGet(&(sdp)->iqueue)
 Direct read from a SerialDriver.
#define sdGetTimeout(sdp, t)   chIQGetTimeout(&(sdp)->iqueue, t)
 Direct read from a SerialDriver with timeout specification.
#define sdWrite(sdp, b, n)   chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE)
 Direct blocking write to a SerialDriver.
#define sdWriteTimeout(sdp, b, n, t)   chOQWriteTimeout(&(sdp)->oqueue, b, n, t)
 Direct blocking write to a SerialDriver with timeout specification.
#define sdAsynchronousWrite(sdp, b, n)   chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE)
 Direct non-blocking write to a SerialDriver.
#define sdRead(sdp, b, n)   chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE)
 Direct blocking read from a SerialDriver.
#define sdReadTimeout(sdp, b, n, t)   chIQReadTimeout(&(sdp)->iqueue, b, n, t)
 Direct blocking read from a SerialDriver with timeout specification.
#define sdAsynchronousRead(sdp, b, n)   chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE)
 Direct non-blocking read from a SerialDriver.
#define sdGetStatusChangeEventSource(ip)   (&((ip)->vmt->sevent))
 Returns the status change event source.

-Typedefs

typedef struct _SerialDriver SerialDriver
 Structure representing a serial driver.

-Enumerations

enum  sdstate_t { SD_UNINIT = 0, -SD_STOP = 1, -SD_READY = 2 - }
 

Driver state machine possible states.

- More...

-Functions

void sdInit (void)
 Serial Driver initialization.
void sdObjectInit (SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify)
 Initializes a generic full duplex driver object.
void sdStart (SerialDriver *sdp, const SerialConfig *config)
 Configures and starts the driver.
void sdStop (SerialDriver *sdp)
 Stops the driver.
void sdIncomingDataI (SerialDriver *sdp, uint8_t b)
 Handles incoming data.
msg_t sdRequestDataI (SerialDriver *sdp)
 Handles outgoing data.
void sdAddFlagsI (SerialDriver *sdp, sdflags_t mask)
 Handles communication events/errors.
sdflags_t sdGetAndClearFlags (SerialDriver *sdp)
 Returns and clears the errors mask associated to the driver.
-

Detailed Description

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Serial Driver macros and structures.

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Definition in file serial.h.

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shell.c File Reference

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-#include "hal.h"
-#include "shell.h"
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-Functions

void shellInit (void)
 Shell manager initialization.
Thread * shellCreate (const ShellConfig *scp, size_t size, tprio_t prio)
 Spawns a new shell.
void shellPrint (BaseChannel *chp, const char *msg)
 Prints a string.
void shellPrintLine (BaseChannel *chp, const char *msg)
 Prints a string with a final newline.
bool_t shellGetLine (BaseChannel *chp, char *line, unsigned size)
 Reads a whole line from the input channel.

-Variables

EventSource shell_terminated
 Shell termination event source.
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Detailed Description

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Simple CLI shell code.

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Definition in file shell.c.

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Simple CLI shell header. -More...

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-Data Structures

struct  ShellCommand
 Custom command entry type. More...
struct  ShellConfig
 Shell descriptor type. More...

-Defines

#define SHELL_MAX_LINE_LENGTH   64
 Shell maximum input line length.
#define SHELL_MAX_ARGUMENTS   4
 Shell maximum arguments per command.
#define SHELL_USE_IPRINTF   TRUE
 Enforces the use of iprintf() on newlib.

-Typedefs

typedef void(* shellcmd_t )(BaseChannel *chp, int argc, char *argv[])
 Command handler function type.

-Functions

void shellInit (void)
 Shell manager initialization.
Thread * shellCreate (const ShellConfig *scp, size_t size, tprio_t prio)
 Spawns a new shell.
void shellPrint (BaseChannel *chp, const char *msg)
 Prints a string.
void shellPrintLine (BaseChannel *chp, const char *msg)
 Prints a string with a final newline.
bool_t shellGetLine (BaseChannel *chp, char *line, unsigned size)
 Reads a whole line from the input channel.

-Variables

EventSource shell_terminated
 Shell termination event source.
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Detailed Description

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Simple CLI shell header.

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Definition in file shell.h.

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SPI Driver code. -More...

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void spiInit (void)
 SPI Driver initialization.
void spiObjectInit (SPIDriver *spip)
 Initializes the standard part of a SPIDriver structure.
void spiStart (SPIDriver *spip, const SPIConfig *config)
 Configures and activates the SPI peripheral.
void spiStop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spiSelect (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spiUnselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spiIgnore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spiExchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spiSend (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data over the SPI bus.
void spiReceive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.
void spiAcquireBus (SPIDriver *spip)
 Gains exclusive access to the SPI bus.
void spiReleaseBus (SPIDriver *spip)
 Releases exclusive access to the SPI bus.
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Detailed Description

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SPI Driver code.

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Definition in file spi.c.

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#define SPI_USE_MUTUAL_EXCLUSION   TRUE
 Enables the mutual exclusion APIs on the SPI bus.

-Enumerations

enum  spistate_t { SPI_UNINIT = 0, -SPI_STOP = 1, -SPI_READY = 2, -SPI_ACTIVE = 3 - }
 

Driver state machine possible states.

- More...

-Functions

void spiInit (void)
 SPI Driver initialization.
void spiObjectInit (SPIDriver *spip)
 Initializes the standard part of a SPIDriver structure.
void spiStart (SPIDriver *spip, const SPIConfig *config)
 Configures and activates the SPI peripheral.
void spiStop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spiSelect (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spiUnselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spiIgnore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spiExchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spiSend (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data over the SPI bus.
void spiReceive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.
-

Detailed Description

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SPI Driver macros and structures.

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Definition in file spi.h.

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void dmaInit (void)
 STM32 DMA helper initialization.
void dmaEnable (uint32_t dma)
 Enables the specified DMA controller clock.
void dmaDisable (uint32_t dma)
 Disables the specified DMA controller clock.
-

Detailed Description

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STM32 DMA helper driver code.

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Definition in file stm32_dma.c.

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#define DMA1_ID   0
 DMA1 identifier.
#define DMA2_ID   1
 DMA2 identifier.

-Functions

void dmaInit (void)
 STM32 DMA helper initialization.
void dmaEnable (uint32_t dma)
 Enables the specified DMA controller clock.
void dmaDisable (uint32_t dma)
 Disables the specified DMA controller clock.
-

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STM32 DMA helper driver header.

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Definition in file stm32_dma.h.

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_SerialDriver Struct Reference
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Full duplex serial driver class. -More...

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#include <serial.h>

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Inherits BaseAsynchronousChannel.

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struct SerialDriverVMT * vmt
 Virtual Methods Table.
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Detailed Description

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Full duplex serial driver class.

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This class extends BaseAsynchronousChannel by adding physical I/O queues.

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Definition at line 133 of file serial.h.

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Field Documentation

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struct SerialDriverVMT* _SerialDriver::vmt
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Virtual Methods Table.

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Reimplemented from BaseAsynchronousChannel.

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Definition at line 135 of file serial.h.

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Referenced by sdObjectInit().

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Driver configuration structure.

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Definition at line 99 of file templates/adc_lld.h.

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bool_t acg_circular
 Enables the circular buffer mode for the group.
adc_channels_num_t acg_num_channels
 Number of the analog channels belonging to the conversion group.
uint32_t acg_cr1
 ADC CR1 register initialization data.
uint32_t acg_cr2
 ADC CR2 register initialization data.
uint32_t acg_smpr1
 ADC SMPR1 register initialization data.
uint32_t acg_smpr2
 ADC SMPR2 register initialization data.
uint32_t acg_sqr1
 ADC SQR1 register initialization data.
uint32_t acg_sqr2
 ADC SQR2 register initialization data.
uint32_t acg_sqr3
 ADC SQR3 register initialization data.
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Conversion group configuration structure.

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This implementation-dependent structure describes a conversion operation.

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Number of the analog channels belonging to the conversion group.

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Definition at line 91 of file templates/adc_lld.h.

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ADC CR1 register initialization data.

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ADC CR2 register initialization data.

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ADC SMPR1 register initialization data.

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ADC SMPR2 register initialization data.

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ADC SQR1 register initialization data.

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ADC SQR2 register initialization data.

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ADCDriver Struct Reference
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adcstate_t ad_state
 Driver state.
const ADCConfig * ad_config
 Current configuration data.
Semaphore ad_sem
 Synchronization semaphore.
adccallback_t ad_callback
 Current callback function or NULL.
adcsample_t * ad_samples
 Current samples buffer pointer or NULL.
size_t ad_depth
 Current samples buffer depth or 0.
const ADCConversionGroup * ad_grpp
 Current conversion group pointer or NULL.
ADC_TypeDef * ad_adc
 Pointer to the ADCx registers block.
DMA_Channel_TypeDef * ad_dma
 Pointer to the DMA channel registers block.
uint32_t ad_dmaprio
 DMA priority bit mask.
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Structure representing an ADC driver.

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adcstate_t ADCDriver::ad_state
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Driver state.

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Definition at line 110 of file templates/adc_lld.h.

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Current configuration data.

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Definition at line 114 of file templates/adc_lld.h.

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Synchronization semaphore.

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Definition at line 118 of file templates/adc_lld.h.

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Current callback function or NULL.

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Current samples buffer pointer or NULL.

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Current samples buffer depth or 0.

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Current conversion group pointer or NULL.

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Definition at line 134 of file templates/adc_lld.h.

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Pointer to the ADCx registers block.

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Definition at line 226 of file platforms/STM32/adc_lld.h.

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Pointer to the DMA channel registers block.

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Definition at line 230 of file platforms/STM32/adc_lld.h.

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DMA priority bit mask.

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Definition at line 234 of file platforms/STM32/adc_lld.h.

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BaseAsynchronousChannel Struct Reference
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struct BaseAsynchronousChannelVMT * vmt
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Base asynchronous channel class.

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This class extends BaseChannel by adding event sources fields for asynchronous I/O for use in an event-driven environment.

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Definition at line 250 of file chioch.h.

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Virtual Methods Table.

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BaseAsynchronousChannel virtual methods table.

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struct BaseChannelVMT * vmt
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Base channel class.

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This class represents a generic, byte-wide, I/O channel. This class introduces generic I/O primitives with timeout specification.

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Definition at line 89 of file chioch.h.

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Virtual Methods Table.

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Definition at line 91 of file chioch.h.

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BaseChannel virtual methods table.

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Base stream class.

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This class represents a generic blocking unbuffered sequential data stream.

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BaseSequentialStream virtual methods table.

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uint32_t cc_mcr
 CAN MCR register initialization data.
uint32_t cc_btr
 CAN BTR register initialization data.
uint32_t cc_num
 Number of elements into the filters array.
const CANFilter * cc_filters
 Pointer to an array of CANFilter structures.
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Driver configuration structure.

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CAN MCR register initialization data.

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Definition at line 231 of file platforms/STM32/can_lld.h.

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canstate_t cd_state
 Driver state.
const CANConfig * cd_config
 Current configuration data.
Semaphore cd_txsem
 Transmission queue semaphore.
Semaphore cd_rxsem
 Receive queue semaphore.
EventSource cd_rxfull_event
 One or more frames become available.
EventSource cd_txempty_event
 One or more transmission slots become available.
EventSource cd_error_event
 A CAN bus error happened.
canstatus_t cd_status
 Error flags set when an error event is broadcasted.
EventSource cd_sleep_event
 Entering sleep state event.
EventSource cd_wakeup_event
 Exiting sleep state event.
CAN_TypeDef * cd_can
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Structure representing an CAN driver.

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Driver state.

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Definition at line 159 of file templates/can_lld.h.

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Current configuration data.

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Transmission queue semaphore.

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Receive queue semaphore.

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One or more frames become available.

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Definition at line 181 of file templates/can_lld.h.

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One or more transmission slots become available.

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Definition at line 185 of file templates/can_lld.h.

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A CAN bus error happened.

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Definition at line 189 of file templates/can_lld.h.

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Error flags set when an error event is broadcasted.

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Definition at line 193 of file templates/can_lld.h.

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Entering sleep state event.

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Definition at line 198 of file templates/can_lld.h.

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Exiting sleep state event.

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Definition at line 202 of file templates/can_lld.h.

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Pointer to the CAN registers.

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Definition at line 290 of file platforms/STM32/can_lld.h.

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CANFilter Struct Reference
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CAN filter. -More...

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uint32_t cf_mode:1
 Filter mode.
uint32_t cf_scale:1
 Filter sclae.
uint32_t cf_assignment:1
 Filter mode.
uint32_t cf_register1
 Filter register 1 (identifier).
uint32_t cf_register2
 Filter register 2 (mask/identifier depending on cf_mode=0/1).
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Detailed Description

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CAN filter.

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It could not be present on some architectures.
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Definition at line 142 of file templates/can_lld.h.

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uint32_t CANFilter::cf_mode
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Filter mode.

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Definition at line 181 of file platforms/STM32/can_lld.h.

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Filter sclae.

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Definition at line 187 of file platforms/STM32/can_lld.h.

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Filter mode.

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Definition at line 193 of file platforms/STM32/can_lld.h.

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Filter register 1 (identifier).

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Definition at line 197 of file platforms/STM32/can_lld.h.

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Filter register 2 (mask/identifier depending on cf_mode=0/1).

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Definition at line 201 of file platforms/STM32/can_lld.h.

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CANRxFrame Struct Reference
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CAN received frame. -More...

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#include <can_lld.h>

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Detailed Description

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CAN received frame.

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Definition at line 117 of file templates/can_lld.h.

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uint8_t CANRxFrame::cf_DLC
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Data length.

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Definition at line 119 of file templates/can_lld.h.

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Frame type.

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Definition at line 120 of file templates/can_lld.h.

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Identifier type.

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Definition at line 121 of file templates/can_lld.h.

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Standard identifier.

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Definition at line 125 of file templates/can_lld.h.

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Extended identifier.

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Definition at line 128 of file templates/can_lld.h.

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uint8_t CANRxFrame::cf_data8[8]
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Frame data.

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Definition at line 132 of file templates/can_lld.h.

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Frame data.

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Definition at line 133 of file templates/can_lld.h.

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Frame data.

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Definition at line 134 of file templates/can_lld.h.

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uint8_t CANRxFrame::cf_FMI
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Filter id.

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Definition at line 148 of file platforms/STM32/can_lld.h.

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Time stamp.

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Definition at line 149 of file platforms/STM32/can_lld.h.

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CANTxFrame Struct Reference
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CAN transmission frame. -More...

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#include <can_lld.h>

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Detailed Description

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CAN transmission frame.

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Definition at line 90 of file templates/can_lld.h.

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uint8_t CANTxFrame::cf_DLC
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Data length.

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Definition at line 92 of file templates/can_lld.h.

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Frame type.

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Definition at line 93 of file templates/can_lld.h.

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Identifier type.

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Definition at line 94 of file templates/can_lld.h.

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Standard identifier.

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Extended identifier.

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Definition at line 101 of file templates/can_lld.h.

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Frame data.

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Definition at line 105 of file templates/can_lld.h.

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Frame data.

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Definition at line 106 of file templates/can_lld.h.

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Frame data.

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Definition at line 107 of file templates/can_lld.h.

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Structure representing the NVIC I/O space.

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Definition at line 108 of file nvic.h.

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Structure representing the System Control Block I/O space.

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Definition at line 136 of file nvic.h.

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Structure representing the SYSTICK I/O space.

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Definition at line 70 of file nvic.h.

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CondVar Struct Reference
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ThreadsQueue c_queue
 CondVar threads queue.
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CondVar structure.

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Definition at line 54 of file chcond.h.

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CondVar threads queue.

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Definition at line 55 of file chcond.h.

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CtxSwcEvent Struct Reference
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void * cse_wtobjp
 Object where going to sleep.
systime_t cse_time
 Time of the switch event.
uint16_t cse_state: 4
 Switched out thread state.
uint16_t cse_tid: 12
 Switched in thread id.
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Trace buffer record.

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Definition at line 67 of file chdebug.h.

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Object where going to sleep.

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Definition at line 68 of file chdebug.h.

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Time of the switch event.

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Switched out thread state.

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Definition at line 72 of file chdebug.h.

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Switched in thread id.

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Definition at line 74 of file chdebug.h.

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EMACDescriptor Struct Reference
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Structure representing a buffer physical descriptor.

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Definition at line 130 of file platforms/AT91SAM7/mac_lld.h.

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EventListener * el_next
 Next Event Listener registered on the Event Source.
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 Thread interested in the Event Source.
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Event Listener structure.

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Definition at line 45 of file chevents.h.

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Next Event Listener registered on the Event Source.

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Definition at line 46 of file chevents.h.

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Thread interested in the Event Source.

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Definition at line 49 of file chevents.h.

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Event flags mask associated by the thread to the Event Source.

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Definition at line 51 of file chevents.h.

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EventSource Struct Reference
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Event Source structure. -More...

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#include <chevents.h>

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EventListener * es_next
 First Event Listener registered on the Event Source.
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Event Source structure.

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Definition at line 59 of file chevents.h.

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First Event Listener registered on the Event Source.

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Definition at line 60 of file chevents.h.

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Referenced by chEvtBroadcastI(), and chEvtRegisterMask().

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GenericConfig Struct Reference
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Generic I/O ports static initializer. -More...

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#include <pal_lld.h>

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Detailed Description

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Generic I/O ports static initializer.

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An instance of this structure must be passed to palInit() at system startup time in order to initialized the digital I/O subsystem. This represents only the initial setup, specific pads or whole ports can be reprogrammed at later time.

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Definition at line 63 of file templates/pal_lld.h.

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GenericQueue Struct Reference
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#include <chqueues.h>

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uint8_t * q_buffer
 Pointer to the queue buffer.
uint8_t * q_top
 Pointer to the first location after the buffer.
uint8_t * q_wrptr
 Write pointer.
uint8_t * q_rdptr
 Read pointer.
Semaphore q_sem
 Counter Semaphore.
qnotify_t q_notify
 Data notification callback.
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Generic I/O queue structure.

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This structure represents a generic Input or Output asymmetrical queue. The queue is asymmetrical because one end is meant to be accessed from a thread context, and thus can be blocking, the other end is accessible from interrupt handlers or from within a kernel lock zone (see I-Locked and S-Locked states in System States) and is non-blocking.

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Definition at line 70 of file chqueues.h.

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Pointer to the queue buffer.

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Definition at line 71 of file chqueues.h.

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Pointer to the first location after the buffer.

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Definition at line 72 of file chqueues.h.

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Write pointer.

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Definition at line 74 of file chqueues.h.

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Read pointer.

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Definition at line 75 of file chqueues.h.

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Counter Semaphore.

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Definition at line 76 of file chqueues.h.

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Referenced by chIQGetTimeout(), chIQInit(), chIQPutI(), chIQReadTimeout(), chIQResetI(), chOQGetI(), chOQInit(), chOQPutTimeout(), chOQResetI(), and chOQWriteTimeout().

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Data notification callback.

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Definition at line 77 of file chqueues.h.

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Referenced by chIQGetTimeout(), chIQInit(), chIQReadTimeout(), chOQInit(), chOQPutTimeout(), and chOQWriteTimeout().

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IOBus Struct Reference
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ioportid_t bus_portid
 Port identifier.
ioportmask_t bus_mask
 Bus mask aligned to port bit 0.
uint_fast8_t bus_offset
 Offset, within the port, of the least significant bit of the bus.
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Detailed Description

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I/O bus descriptor.

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Definition at line 129 of file pal.h.

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ioportid_t IOBus::bus_portid
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Port identifier.

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Definition at line 133 of file pal.h.

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Referenced by palReadBus(), palSetBusMode(), and palWriteBus().

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Bus mask aligned to port bit 0.

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Definition at line 139 of file pal.h.

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Referenced by palReadBus(), palSetBusMode(), and palWriteBus().

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Offset, within the port, of the least significant bit of the bus.

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Definition at line 143 of file pal.h.

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Referenced by palReadBus(), palSetBusMode(), and palWriteBus().

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LPC13xx_gpio_setup_t Struct Reference
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GPIO port setup info. -More...

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#include <pal_lld.h>

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uint32_t data
uint32_t dir
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GPIO port setup info.

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Definition at line 56 of file platforms/LPC13xx/pal_lld.h.

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uint32_t LPC13xx_gpio_setup_t::data
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Initial value for FIO_PIN register.

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Definition at line 58 of file platforms/LPC13xx/pal_lld.h.

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Initial value for FIO_DIR register.

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MACDriver Struct Reference
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Semaphore md_tdsem
Semaphore md_rdsem
EventSource md_rdevent
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Structure representing a MAC driver.

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Definition at line 80 of file templates/mac_lld.h.

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Transmit semaphore.

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Definition at line 81 of file templates/mac_lld.h.

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Receive semaphore.

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Definition at line 82 of file templates/mac_lld.h.

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Receive event source.

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Definition at line 84 of file templates/mac_lld.h.

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MACReceiveDescriptor Struct Reference
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size_t rd_offset
size_t rd_size
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Structure representing a receive descriptor.

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Definition at line 101 of file templates/mac_lld.h.

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Current read offset.

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Available data size.

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Pointer to the first descriptor of the buffers chain.

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Definition at line 165 of file platforms/AT91SAM7/mac_lld.h.

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MACTransmitDescriptor Struct Reference
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size_t td_offset
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Structure representing a transmit descriptor.

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Definition at line 92 of file templates/mac_lld.h.

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Current write offset.

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Available space size.

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Pointer to the physical descriptor.

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Driver configuration structure.

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Definition at line 131 of file mmc_spi.h.

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mmcstate_t mmc_state
 Driver state.
const MMCConfig * mmc_config
 Current configuration data.
SPIDriver * mmc_spip
 SPI driver associated to this MMC driver.
const SPIConfig * mmc_lscfg
 SPI low speed configuration used during initialization.
const SPIConfig * mmc_hscfg
 SPI high speed configuration used during transfers.
mmcquery_t mmc_is_protected
 Write protect status query function.
mmcquery_t mmc_is_inserted
 Insertion status query function.
EventSource mmc_inserted_event
 Card insertion event source.
EventSource mmc_removed_event
 Card removal event source.
VirtualTimer mmc_vt
 MMC insertion polling timer.
uint_fast8_t mmc_cnt
 Insertion counter.
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Structure representing a MMC driver.

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Definition at line 138 of file mmc_spi.h.

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Driver state.

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Definition at line 142 of file mmc_spi.h.

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Current configuration data.

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Definition at line 146 of file mmc_spi.h.

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SPI driver associated to this MMC driver.

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Definition at line 150 of file mmc_spi.h.

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SPI low speed configuration used during initialization.

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Definition at line 154 of file mmc_spi.h.

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SPI high speed configuration used during transfers.

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Definition at line 158 of file mmc_spi.h.

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Write protect status query function.

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Definition at line 162 of file mmc_spi.h.

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Insertion status query function.

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Definition at line 166 of file mmc_spi.h.

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Card insertion event source.

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Definition at line 170 of file mmc_spi.h.

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Card removal event source.

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Definition at line 174 of file mmc_spi.h.

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MMC insertion polling timer.

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Definition at line 178 of file mmc_spi.h.

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Insertion counter.

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Definition at line 182 of file mmc_spi.h.

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MemStream virtual methods table.

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Definition at line 55 of file memstreams.h.

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MemoryPool Struct Reference
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struct pool_header * mp_next
 Pointer to the header.
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 Memory pool objects size.
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Memory pool descriptor.

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Memory pool objects size.

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Memory blocks provider for this pool.

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Inherits BaseSequentialStream.

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Memory stream object.

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Virtual Methods Table.

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ThreadsQueue m_queue
 Queue of the threads sleeping on this Mutex.
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Mutex structure.

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Definition at line 43 of file chmtx.h.

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Queue of the threads sleeping on this Mutex.

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Definition at line 44 of file chmtx.h.

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Owner Thread pointer or NULL.

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Definition at line 46 of file chmtx.h.

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Next Mutex into an owner-list or NULL.

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Definition at line 48 of file chmtx.h.

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PALConfig Struct Reference
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#include <pal_lld.h>

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at91sam7_pio_setup_t P0Data
 Port 0 setup data.
at91sam7_pio_setup_t P1Data
 Port 1 setup data.
lpc111x_gpio_setup_t P0
 GPIO 0 setup data.
lpc111x_gpio_setup_t P1
 GPIO 1 setup data.
lpc111x_gpio_setup_t P2
 GPIO 2 setup data.
lpc111x_gpio_setup_t P3
 GPIO 3 setup data.
LPC13xx_gpio_setup_t P0
 GPIO 0 setup data.
LPC13xx_gpio_setup_t P1
 GPIO 1 setup data.
LPC13xx_gpio_setup_t P2
 GPIO 2 setup data.
LPC13xx_gpio_setup_t P3
 GPIO 3 setup data.
uint32_t pinsel0
 PINSEL0 initial value.
uint32_t pinsel1
 PINSEL1 initial value.
uint32_t pinsel2
 PINSEL2 initial value.
lpc214x_fio_setup_t P0Data
 Port 0 setup data.
lpc214x_fio_setup_t P1Data
 Port 1 setup data.
msp430_dio_setup_t P1Data
 Port 1 setup data.
msp430_dio_setup_t P2Data
 Port 2 setup data.
msp430_dio_setup_t P3Data
 Port 3 setup data.
msp430_dio_setup_t P4Data
 Port 4 setup data.
msp430_dio_setup_t P5Data
 Port 5 setup data.
msp430_dio_setup_t P6Data
 Port 6 setup data.
stm32_gpio_setup_t PAData
 Port A setup data.
stm32_gpio_setup_t PBData
 Port B setup data.
stm32_gpio_setup_t PCData
 Port C setup data.
stm32_gpio_setup_t PDData
 Port D setup data.
stm32_gpio_setup_t PEData
 Port E setup data.
stm32_gpio_setup_t PFData
 Port F setup data.
stm32_gpio_setup_t PGData
 Port G setup data.
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AT91SAM7 PIO static initializer.

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Generic I/O ports static initializer.

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STM32 GPIO static initializer.

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MSP430 I/O ports static initializer.

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LPC214x FIO static initializer.

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GPIO static initializer.

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An instance of this structure must be passed to palInit() at system startup time in order to initialize the digital I/O subsystem. This represents only the initial setup, specific pads or whole ports can be reprogrammed at later time.

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An instance of this structure must be passed to palInit() at system startup time in order to initialized the digital I/O subsystem. This represents only the initial setup, specific pads or whole ports can be reprogrammed at later time.

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An instance of this structure must be passed to palInit() at system startup time in order to initialized the digital I/O subsystem. This represents only the initial setup, specific pads or whole ports can be reprogrammed at later time.

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Definition at line 68 of file platforms/AT91SAM7/pal_lld.h.

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at91sam7_pio_setup_t PALConfig::P0Data
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Port 0 setup data.

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Definition at line 70 of file platforms/AT91SAM7/pal_lld.h.

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Port 1 setup data.

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Definition at line 74 of file platforms/AT91SAM7/pal_lld.h.

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lpc111x_gpio_setup_t PALConfig::P0
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GPIO 0 setup data.

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Definition at line 77 of file platforms/LPC11xx/pal_lld.h.

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GPIO 1 setup data.

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Definition at line 79 of file platforms/LPC11xx/pal_lld.h.

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GPIO 2 setup data.

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Definition at line 81 of file platforms/LPC11xx/pal_lld.h.

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GPIO 3 setup data.

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Definition at line 83 of file platforms/LPC11xx/pal_lld.h.

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LPC13xx_gpio_setup_t PALConfig::P0
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GPIO 0 setup data.

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Definition at line 77 of file platforms/LPC13xx/pal_lld.h.

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GPIO 1 setup data.

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Definition at line 79 of file platforms/LPC13xx/pal_lld.h.

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GPIO 2 setup data.

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Definition at line 81 of file platforms/LPC13xx/pal_lld.h.

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GPIO 3 setup data.

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Definition at line 83 of file platforms/LPC13xx/pal_lld.h.

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uint32_t PALConfig::pinsel0
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PINSEL0 initial value.

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Definition at line 70 of file platforms/LPC214x/pal_lld.h.

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PINSEL1 initial value.

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Definition at line 72 of file platforms/LPC214x/pal_lld.h.

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PINSEL2 initial value.

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Definition at line 74 of file platforms/LPC214x/pal_lld.h.

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Port 0 setup data.

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Definition at line 76 of file platforms/LPC214x/pal_lld.h.

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Port 1 setup data.

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Definition at line 78 of file platforms/LPC214x/pal_lld.h.

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Port 1 setup data.

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Definition at line 92 of file platforms/MSP430/pal_lld.h.

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Port 2 setup data.

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Definition at line 98 of file platforms/MSP430/pal_lld.h.

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Port 3 setup data.

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Definition at line 104 of file platforms/MSP430/pal_lld.h.

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Port 4 setup data.

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Definition at line 110 of file platforms/MSP430/pal_lld.h.

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Port 5 setup data.

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Definition at line 116 of file platforms/MSP430/pal_lld.h.

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Port 6 setup data.

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Definition at line 122 of file platforms/MSP430/pal_lld.h.

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Port A setup data.

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Definition at line 79 of file platforms/STM32/pal_lld.h.

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Definition at line 81 of file platforms/STM32/pal_lld.h.

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Port C setup data.

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Definition at line 83 of file platforms/STM32/pal_lld.h.

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Port D setup data.

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Definition at line 85 of file platforms/STM32/pal_lld.h.

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Definition at line 88 of file platforms/STM32/pal_lld.h.

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Definition at line 92 of file platforms/STM32/pal_lld.h.

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Port G setup data.

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Definition at line 94 of file platforms/STM32/pal_lld.h.

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pwmmode_t pcc_mode
 Channel active logic level.
pwmcallback_t pcc_callback
 Channel callback pointer.
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PWM driver channel configuration structure.

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Definition at line 90 of file templates/pwm_lld.h.

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Channel active logic level.

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Definition at line 94 of file templates/pwm_lld.h.

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Definition at line 100 of file templates/pwm_lld.h.

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Referenced by pwm_lld_enable_channel().

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pwmcallback_t pc_callback
 Periodic callback pointer.
PWMChannelConfig pc_channels [PWM_CHANNELS]
 Channels configurations.
uint16_t pc_psc
 TIM PSC (pre-scaler) register initialization data.
uint16_t pc_arr
 TIM ARR (auto-reload) register initialization data.
uint16_t pc_cr2
 TIM CR2 register initialization data.
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Driver configuration structure.

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PWM driver configuration structure.

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Definition at line 109 of file templates/pwm_lld.h.

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Periodic callback pointer.

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Definition at line 115 of file templates/pwm_lld.h.

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Referenced by pwm_lld_start().

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Channels configurations.

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Definition at line 119 of file templates/pwm_lld.h.

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Referenced by pwm_lld_enable_channel(), and pwm_lld_start().

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uint16_t PWMConfig::pc_psc
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TIM PSC (pre-scaler) register initialization data.

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Definition at line 184 of file platforms/STM32/pwm_lld.h.

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Referenced by pwm_lld_start().

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TIM ARR (auto-reload) register initialization data.

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Definition at line 188 of file platforms/STM32/pwm_lld.h.

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Referenced by pwm_lld_start().

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TIM CR2 register initialization data.

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Definition at line 193 of file platforms/STM32/pwm_lld.h.

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Referenced by pwm_lld_start().

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PWMDriver Struct Reference
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pwmstate_t pd_state
 Driver state.
const PWMConfig * pd_config
 Current configuration data.
uint32_t pd_enabled_channels
 Bit mask of the enabled channels.
TIM_TypeDef * pd_tim
 Pointer to the TIMx registers block.
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Structure representing an PWM driver.

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Structure representing a PWM driver.

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Definition at line 128 of file templates/pwm_lld.h.

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Driver state.

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Definition at line 132 of file templates/pwm_lld.h.

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Current configuration data.

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Current driver configuration data.

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Definition at line 136 of file templates/pwm_lld.h.

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Bit mask of the enabled channels.

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Definition at line 215 of file platforms/STM32/pwm_lld.h.

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Referenced by pwm_lld_disable_channel(), pwm_lld_enable_channel(), pwm_lld_init(), pwm_lld_start(), and pwm_lld_stop().

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Pointer to the TIMx registers block.

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Definition at line 219 of file platforms/STM32/pwm_lld.h.

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ReadyList Struct Reference
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#include <chschd.h>

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Inherits ThreadsQueue.

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ThreadsQueue r_queue
 Threads queue.
tprio_t r_prio
 This field must be initialized to zero.
struct context r_ctx
 Not used, present because offsets.
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 Newer registry element.
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 Older registry element.
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 The currently running thread.
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Ready list header.

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Definition at line 77 of file chschd.h.

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Field Documentation

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Threads queue.

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Definition at line 78 of file chschd.h.

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Definition at line 79 of file chschd.h.

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Newer registry element.

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The currently running thread.

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ChibiOS/RT LogoChibiOS/RT

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SPIConfig Struct Reference
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Driver configuration structure. -More...

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#include <spi_lld.h>

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ioportid_t spc_ssport
 The chip select line port.
uint16_t spc_sspad
 The chip select line pad number.
uint16_t spc_cr0
 SSP CR0 initialization data.
uint16_t spc_cr1
 SSP CR1 initialization data.
uint32_t spc_cpsr
 SSP CPSR initialization data.
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Detailed Description

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Driver configuration structure.

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Definition at line 59 of file templates/spi_lld.h.

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ioportid_t SPIConfig::spc_ssport
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The chip select line port.

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Definition at line 71 of file platforms/LPC214x/spi_lld.h.

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The chip select line pad number.

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Definition at line 75 of file platforms/LPC214x/spi_lld.h.

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SSP CR0 initialization data.

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Definition at line 79 of file platforms/LPC214x/spi_lld.h.

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SSP CR1 initialization data.

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SPI initialization data.

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Definition at line 83 of file platforms/LPC214x/spi_lld.h.

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SSP CPSR initialization data.

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Definition at line 87 of file platforms/LPC214x/spi_lld.h.

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SPIDriver Struct Reference
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spistate_t spd_state
 Driver state.
Mutex spd_mutex
 Mutex protecting the bus.
const SPIConfig * spd_config
 Current configuration data.
Thread * spd_thread
 Thread waiting for I/O completion.
SPI_TypeDef * spd_spi
 Pointer to the SPIx registers block.
DMA_Channel_TypeDef * spd_dmarx
 Pointer to the receive DMA channel registers block.
DMA_Channel_TypeDef * spd_dmatx
 Pointer to the transmit DMA channel registers block.
uint32_t spd_dmaprio
 DMA priority bit mask.
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Detailed Description

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Structure representing a SPI driver.

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Definition at line 66 of file templates/spi_lld.h.

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spistate_t SPIDriver::spd_state
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Driver state.

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Definition at line 70 of file templates/spi_lld.h.

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Referenced by spiExchange(), spiIgnore(), spiObjectInit(), spiReceive(), spiSelect(), spiSend(), spiStart(), spiStop(), and spiUnselect().

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Mutex protecting the bus.

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Definition at line 76 of file templates/spi_lld.h.

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Current configuration data.

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Definition at line 84 of file templates/spi_lld.h.

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Referenced by spiObjectInit(), and spiStart().

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Thread waiting for I/O completion.

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Definition at line 170 of file platforms/STM32/spi_lld.h.

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Pointer to the SPIx registers block.

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Definition at line 174 of file platforms/STM32/spi_lld.h.

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Pointer to the receive DMA channel registers block.

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Definition at line 178 of file platforms/STM32/spi_lld.h.

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Pointer to the transmit DMA channel registers block.

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Definition at line 182 of file platforms/STM32/spi_lld.h.

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DMA priority bit mask.

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Definition at line 186 of file platforms/STM32/spi_lld.h.

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ThreadsQueue s_queue
 Queue of the threads sleeping on this semaphore.
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Semaphore structure.

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Definition at line 43 of file chsem.h.

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Queue of the threads sleeping on this semaphore.

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SerialConfig Struct Reference
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Generic Serial Driver configuration structure. -More...

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uint32_t sc_speed
 Bit rate.
uint32_t sc_mr
 Initialization value for the MR register.
uint16_t sc_brr
 Initialization value for the BRR register.
uint8_t sc_csrc
 Initialization value for the CSRC register.
uint32_t sc_lcr
 Initialization value for the LCR register.
uint32_t sc_fcr
 Initialization value for the FCR register.
uint16_t sc_div
 Initialization value for the UBRx registers.
uint8_t sc_mod
 Initialization value for the MOD register.
uint8_t sc_ctl
 Initialization value for the CTL register.
uint8_t sc_mode
 Mode flags.
uint16_t sc_cr1
 Initialization value for the CR1 register.
uint16_t sc_cr2
 Initialization value for the CR2 register.
uint16_t sc_cr3
 Initialization value for the CR3 register.
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Detailed Description

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Generic Serial Driver configuration structure.

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STM32 Serial Driver configuration structure.

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MSP430 Serial Driver configuration structure.

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LPC214x Serial Driver configuration structure.

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LPC13xx Serial Driver configuration structure.

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LPC11xx Serial Driver configuration structure.

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AVR Serial Driver configuration structure.

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AT91SAM7 Serial Driver configuration structure.

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An instance of this structure must be passed to sdStart() in order to configure and start a serial driver operations.

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An instance of this structure must be passed to sdStart() in order to configure and start a serial driver operations.

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Definition at line 69 of file templates/serial_lld.h.

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Field Documentation

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Bit rate.

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Initialization value for the MR register.

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Bit rate register.

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Initialization value for the CSRC register.

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Initialization value for the LCR register.

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Initialization value for the FCR register.

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Initialization value for the UBRx registers.

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Initialization value for the MOD register.

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Initialization value for the CTL register.

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Mode flags.

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Initialization value for the CR1 register.

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Initialization value for the CR2 register.

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Initialization value for the CR3 register.

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Definition at line 170 of file platforms/STM32/serial_lld.h.

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Detailed Description

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SerialDriver virtual methods table.

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Definition at line 122 of file serial.h.

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const char * sc_name
 Command name.
shellcmd_t sc_function
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Custom command entry type.

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Field Documentation

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Command name.

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Command function.

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ShellConfig Struct Reference
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Shell descriptor type. -More...

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#include <shell.h>

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BaseChannel * sc_channel
 I/O channel associated to the shell.
const ShellCommand * sc_commands
 Shell extra commands table.
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Shell descriptor type.

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Definition at line 74 of file shell.h.

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I/O channel associated to the shell.

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Definition at line 75 of file shell.h.

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Definition at line 77 of file shell.h.

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Thread Struct Reference
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Structure representing a thread. -More...

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Thread * p_next
 Next in the list/queue.
Thread * p_prev
 Previous in the queue.
tprio_t p_prio
 Thread priority.
struct context p_ctx
 Processor context.
Thread * p_newer
 Newer registry element.
Thread * p_older
 Older registry element.
tstate_t p_state
 Current thread state.
tmode_t p_flags
 Various thread flags.
trefs_t p_refs
 References to this thread.
volatile systime_t p_time
 Thread consumed time in ticks.
union {
   msg_t   rdymsg
 Thread wakeup code.
   msg_t   exitcode
 Thread exit code.
   void *   wtobjp
 Pointer to a generic "wait" object.
   eventmask_t   ewmask
 Enabled events mask.
} p_u
 State-specific fields.
ThreadsList p_waiting
 Termination waiting list.
ThreadsQueue p_msgqueue
 Messages queue.
msg_t p_msg
 Thread message.
eventmask_t p_epending
 Pending events mask.
Mutex * p_mtxlist
 List of the mutexes owned by this thread.
tprio_t p_realprio
 Thread's own, non-inherited, priority.
void * p_mpool
 Memory Pool where the thread workspace is returned.
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Structure representing a thread.

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Definition at line 56 of file chthreads.h.

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Next in the list/queue.

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Definition at line 57 of file chthreads.h.

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Previous in the queue.

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Definition at line 59 of file chthreads.h.

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Thread priority.

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Definition at line 61 of file chthreads.h.

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Processor context.

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Newer registry element.

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Older registry element.

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Definition at line 65 of file chthreads.h.

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Current thread state.

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Definition at line 71 of file chthreads.h.

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Various thread flags.

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Definition at line 75 of file chthreads.h.

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References to this thread.

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Definition at line 80 of file chthreads.h.

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Thread consumed time in ticks.

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Definition at line 93 of file chthreads.h.

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Thread wakeup code.

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Definition at line 107 of file chthreads.h.

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Referenced by chCondBroadcastI(), chCondSignalI(), chCondWaitS(), chEvtSignalI(), chMsgSend(), chSchWakeupS(), chSemResetI(), chSemSignalI(), and chSemSignalWait().

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Thread exit code.

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Definition at line 114 of file chthreads.h.

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Pointer to a generic "wait" object.

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Definition at line 121 of file chthreads.h.

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Enabled events mask.

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Definition at line 128 of file chthreads.h.

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State-specific fields.

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Termination waiting list.

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Definition at line 135 of file chthreads.h.

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Messages queue.

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Definition at line 141 of file chthreads.h.

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Thread message.

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Definition at line 145 of file chthreads.h.

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Pending events mask.

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Definition at line 151 of file chthreads.h.

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List of the mutexes owned by this thread.

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Definition at line 158 of file chthreads.h.

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Thread's own, non-inherited, priority.

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Definition at line 162 of file chthreads.h.

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Definition at line 168 of file chthreads.h.

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Thread * p_next
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Generic threads single link list, it works like a stack.

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Definition at line 98 of file chlists.h.

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Last pushed Thread on the stack list, or pointer to itself if empty.

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Generic threads bidirectional linked list header and element.

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First Thread in the queue, or ThreadQueue when empty.

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Last Thread in the queue, or ThreadQueue when empty.

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TraceBuffer Struct Reference
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unsigned tb_size
 Trace buffer size (entries).
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Trace buffer header.

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Trace buffer size (entries).

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Ring buffer.

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VirtualTimer * vt_next
 Next timer in the delta list.
VirtualTimer * vt_prev
 Last timer in the delta list.
systime_t vt_time
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 System Time counter.
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Virtual timers list header.

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Next timer in the delta list.

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System Time counter.

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VirtualTimer * vt_next
 Next timer in the delta list.
VirtualTimer * vt_prev
 Previous timer in the delta list.
systime_t vt_time
 Time delta before timeout.
vtfunc_t vt_func
 Timer callback function pointer.
void * vt_par
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Virtual Timer descriptor structure.

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at91sam7_pio_setup_t Struct Reference
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PIO port setup info. -More...

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#include <pal_lld.h>

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uint32_t odsr
uint32_t osr
uint32_t pusr
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PIO port setup info.

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Definition at line 52 of file platforms/AT91SAM7/pal_lld.h.

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Initial value for ODSR register (data).

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Initial value for OSR register (direction).

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Initial value for PUSR register (Pull-ups).

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Cortex-Mx exception context.

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context Struct Reference
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Platform dependent part of the Thread structure.

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eabi_frame Struct Reference
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regppc_t slink
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Mandatory part of a stack frame.

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Stack back link.

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Stack hole for LR storage.

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Interrupt saved context.

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This structure represents the stack frame saved during a preemption-capable interrupt handler.

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Definition at line 65 of file kernel/templates/chcore.h.

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gpio_t Struct Reference
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GPIO port representation. -More...

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Detailed Description

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GPIO port representation.

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Definition at line 63 of file platforms/STM8/pal_lld.h.

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System saved context.

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lpc111x_gpio_setup_t Struct Reference
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uint32_t data
uint32_t dir
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GPIO port setup info.

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Definition at line 56 of file platforms/LPC11xx/pal_lld.h.

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Initial value for FIO_PIN register.

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Initial value for FIO_DIR register.

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FIO port setup info.

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Definition at line 54 of file platforms/LPC214x/pal_lld.h.

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Initial value for FIO_PIN register.

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Initial value for FIO_DIR register.

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memgetfunc_t h_provider
 Memory blocks provider for this heap.
union heap_header h_free
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Structure describing a memory heap.

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Memory blocks provider for this heap.

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Free blocks list header.

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Heap access mutex.

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Definition at line 75 of file chheap.h.

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msp430_dio_setup_t Struct Reference
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Setup registers common to all the MSP430 ports. -More...

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Setup registers common to all the MSP430 ports.

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Definition at line 75 of file platforms/MSP430/pal_lld.h.

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Memory pool free object header.

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port_common_t Struct Reference
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Simplified MSP430 I/O port representation. -More...

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Simplified MSP430 I/O port representation.

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Base type for stack and memory alignment.

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uint32_t crl
uint32_t crh
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GPIO port setup info.

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Definition at line 61 of file platforms/STM32/pal_lld.h.

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Initial value for ODR register.

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Initial value for CRL register.

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Initial value for CRH register.

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Start context.

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This context is the stack organization for the trampoline code _port_thread_start().

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Definition at line 134 of file ports/RC/STM8/chcore.h.

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char *(* gettest )(void)
 Test case name get function.
void(* setup )(void)
 Test case preparation function.
void(* teardown )(void)
 Test case clean up function.
void(* execute )(void)
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Structure representing a test case.

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Test case name get function.

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Test case clean up function.

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Test case execution function.

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Application Range

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ChibiOS/RT Application Range.

- -

-Application Scenarios

-

ChibiOS/RT is usable in many applicative areas, as example and not limited to:

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    -
  • Automotive.
    • -
  • Robotic Applications.
    • -
  • Consumer Electronics.
    • -
  • Energy Management.
    • -
  • Teaching and Learning.
    • -
  • Hobby.
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-Absolute Minimum Requirements

-

A certain set of minimum system requirements must be satisfied in order to use ChibiOS/RT on a new architecture:

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    -
  • 8bits architecture minimum.
    • -
  • A "real" stack pointer that can be positioned anywhere in the data address space. The OS could be ported to architectures with an hardware stack but I wouldn't recommend it because the context switch would become ridiculously inefficient.
    • -
  • Support for maskable interrupt sources and at least an OS-dedicated timer.
    • -
  • Support for standard C89 (C99 supported) language with no architecture-related non-standard restrictions. Non standard mandatory language extensions or restrictions may result in reduced functionality or impossibility of use.
    • -
  • 256/512bytes RAM permanently allocated to the kernel and its two mandatory threads "idle" and "main", the exact amount depends on the architecture. This figure is not inclusive of the HAL and device drivers (non mandatory components).
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  • 8KiB of program space for a full featured kernel scalable down to about 1.2KiB for reduced configurations. This figure is not inclusive of the HAL and device drivers (non mandatory components).
    • -
-

-Desirable Features

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  • Efficient instruction set for linked lists traversal. The kernel makes extensive use of simple and bidirectional linked lists so the performance is directly affected by the supported addressing modes, number of registers etc.
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  • Uniformly sized C pointers.
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  • 2KiB RAM.
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  • 16KiB ROM/Flash.
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-Upper Recommended Limit

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The application range of ChibiOS/RT ends when one or more of the following features are required:

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    -
  • Separation between user code space and kernel space, both just logical or using a Memory Management/Protection Unit. Applications in ChibiOS/RT are supposed to be monolithic and trusted. The kernel and the application share the same address space.
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  • Multiple applications. ChibiOS/RT supports the single multithreaded application model.
    • -
  • Multicore SMP architectures. Currently ChibiOS/RT only supports a single core unless running multiple distinct and separate OS instances. A true multicore kernel is planned for when multicore MCUs will become commonly available.
    • -
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adc_lld.c File Reference

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ADC Driver subsystem low level driver source template. -More...

-#include "ch.h"
-#include "hal.h"
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- - - - - - - - - - - - -

-Functions

void adc_lld_init (void)
 Low level ADC driver initialization.
void adc_lld_start (ADCDriver *adcp)
 Configures and activates the ADC peripheral.
void adc_lld_stop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
void adc_lld_start_conversion (ADCDriver *adcp)
 Starts an ADC conversion.
void adc_lld_stop_conversion (ADCDriver *adcp)
 Stops an ongoing conversion.
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Detailed Description

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ADC Driver subsystem low level driver source template.

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Definition in file templates/adc_lld.c.

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adc_lld.h File Reference

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ADC Driver subsystem low level driver header template. -More...

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Go to the source code of this file.

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-Data Structures

struct  ADCConversionGroup
 Conversion group configuration structure. More...
struct  ADCConfig
 Driver configuration structure. More...
struct  ADCDriver
 Structure representing an ADC driver. More...

-Typedefs

typedef uint16_t adcsample_t
 ADC sample data type.
typedef uint16_t adc_channels_num_t
 Channels number in a conversion group.
typedef void(* adccallback_t )(adcsample_t *buffer, size_t n)
 ADC notification callback type.

-Functions

void adc_lld_init (void)
 Low level ADC driver initialization.
void adc_lld_start (ADCDriver *adcp)
 Configures and activates the ADC peripheral.
void adc_lld_stop (ADCDriver *adcp)
 Deactivates the ADC peripheral.
void adc_lld_start_conversion (ADCDriver *adcp)
 Starts an ADC conversion.
void adc_lld_stop_conversion (ADCDriver *adcp)
 Stops an ongoing conversion.
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Detailed Description

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ADC Driver subsystem low level driver header template.

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Definition in file templates/adc_lld.h.

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can_lld.c File Reference

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CAN Driver subsystem low level driver source template. -More...

-#include "ch.h"
-#include "hal.h"
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-Functions

void can_lld_init (void)
 Low level CAN driver initialization.
void can_lld_start (CANDriver *canp)
 Configures and activates the CAN peripheral.
void can_lld_stop (CANDriver *canp)
 Deactivates the CAN peripheral.
bool_t can_lld_can_transmit (CANDriver *canp)
 Determines whether a frame can be transmitted.
void can_lld_transmit (CANDriver *canp, const CANTxFrame *ctfp)
 Inserts a frame into the transmit queue.
bool_t can_lld_can_receive (CANDriver *canp)
 Determines whether a frame has been received.
void can_lld_receive (CANDriver *canp, CANRxFrame *crfp)
 Receives a frame from the input queue.
void can_lld_sleep (CANDriver *canp)
 Enters the sleep mode.
void can_lld_wakeup (CANDriver *canp)
 Enforces leaving the sleep mode.
-

Detailed Description

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CAN Driver subsystem low level driver source template.

- -

Definition in file templates/can_lld.c.

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can_lld.h File Reference

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CAN Driver subsystem low level driver header template. -More...

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Go to the source code of this file.

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-Data Structures

struct  CANTxFrame
 CAN transmission frame. More...
struct  CANRxFrame
 CAN received frame. More...
struct  CANFilter
 CAN filter. More...
struct  CANConfig
 Driver configuration structure. More...
struct  CANDriver
 Structure representing an CAN driver. More...

-Defines

#define CAN_SUPPORTS_SLEEP   TRUE
 This switch defines whether the driver implementation supports a low power switch mode with automatic an wakeup feature.
#define CAN_USE_SLEEP_MODE   TRUE
 Sleep mode related APIs inclusion switch.

-Typedefs

typedef uint32_t canstatus_t
 CAN status flags.

-Functions

void can_lld_init (void)
 Low level CAN driver initialization.
void can_lld_start (CANDriver *canp)
 Configures and activates the CAN peripheral.
void can_lld_stop (CANDriver *canp)
 Deactivates the CAN peripheral.
bool_t can_lld_can_transmit (CANDriver *canp)
 Determines whether a frame can be transmitted.
void can_lld_transmit (CANDriver *canp, const CANTxFrame *ctfp)
 Inserts a frame into the transmit queue.
bool_t can_lld_can_receive (CANDriver *canp)
 Determines whether a frame has been received.
void can_lld_receive (CANDriver *canp, CANRxFrame *crfp)
 Receives a frame from the input queue.
-

Detailed Description

-

CAN Driver subsystem low level driver header template.

- -

Definition in file templates/can_lld.h.

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hal_lld.c File Reference

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HAL Driver subsystem low level driver source template. -More...

-#include "ch.h"
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void hal_lld_init (void)
 Low level HAL driver initialization.
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Detailed Description

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HAL Driver subsystem low level driver source template.

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Definition in file templates/hal_lld.c.

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#define PLATFORM_NAME   ""
 Platform name.

-Functions

void hal_lld_init (void)
 Low level HAL driver initialization.
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Detailed Description

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HAL subsystem low level driver header template.

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Definition in file templates/hal_lld.h.

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MAC Driver subsystem low level driver source template. -More...

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-Functions

void mac_lld_init (void)
 Low level MAC initialization.
void mac_lld_set_address (MACDriver *macp, const uint8_t *p)
 Low level MAC address setup.
msg_t max_lld_get_transmit_descriptor (MACDriver *macp, MACTransmitDescriptor *tdp)
 Returns a transmission descriptor.
size_t mac_lld_write_transmit_descriptor (MACTransmitDescriptor *tdp, uint8_t *buf, size_t size)
 Writes to a transmit descriptor's stream.
void mac_lld_release_transmit_descriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t max_lld_get_receive_descriptor (MACDriver *macp, MACReceiveDescriptor *rdp)
 Returns a receive descriptor.
size_t mac_lld_read_receive_descriptor (MACReceiveDescriptor *rdp, uint8_t *buf, size_t size)
 Reads from a receive descriptor's stream.
void mac_lld_release_receive_descriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t mac_lld_poll_link_status (MACDriver *macp)
 Updates and returns the link status.
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Detailed Description

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MAC Driver subsystem low level driver source template.

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Definition in file templates/mac_lld.c.

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mac_lld.h File Reference

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MAC Driver subsystem low level driver header template. -More...

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Go to the source code of this file.

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-Data Structures

struct  MACDriver
 Structure representing a MAC driver. More...
struct  MACTransmitDescriptor
 Structure representing a transmit descriptor. More...
struct  MACReceiveDescriptor
 Structure representing a receive descriptor. More...

-Defines

#define MAC_TRANSMIT_BUFFERS   2
 Number of available transmit buffers.
#define MAC_RECEIVE_BUFFERS   2
 Number of available receive buffers.
#define MAC_BUFFERS_SIZE   1518
 Maximum supported frame size.

-Functions

void mac_lld_init (void)
 Low level MAC initialization.
void mac_lld_set_address (MACDriver *macp, const uint8_t *p)
 Low level MAC address setup.
msg_t max_lld_get_transmit_descriptor (MACDriver *macp, MACTransmitDescriptor *tdp)
 Returns a transmission descriptor.
size_t mac_lld_write_transmit_descriptor (MACTransmitDescriptor *tdp, uint8_t *buf, size_t size)
 Writes to a transmit descriptor's stream.
void mac_lld_release_transmit_descriptor (MACTransmitDescriptor *tdp)
 Releases a transmit descriptor and starts the transmission of the enqueued data as a single frame.
msg_t max_lld_get_receive_descriptor (MACDriver *macp, MACReceiveDescriptor *rdp)
 Returns a receive descriptor.
size_t mac_lld_read_receive_descriptor (MACReceiveDescriptor *rdp, uint8_t *buf, size_t size)
 Reads from a receive descriptor's stream.
void mac_lld_release_receive_descriptor (MACReceiveDescriptor *rdp)
 Releases a receive descriptor.
bool_t mac_lld_poll_link_status (MACDriver *macp)
 Updates and returns the link status.
-

Detailed Description

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MAC Driver subsystem low level driver header template.

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Definition in file templates/mac_lld.h.

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pal_lld.c File Reference

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PAL subsystem low level driver template. -More...

-#include "ch.h"
-#include "hal.h"
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PAL subsystem low level driver template.

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Definition in file templates/pal_lld.c.

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-Data Structures

struct  GenericConfig
 Generic I/O ports static initializer. More...

-Defines

#define PAL_IOPORTS_WIDTH   32
 Width, in bits, of an I/O port.
#define PAL_WHOLE_PORT   ((ioportmask_t)0xFFFFFFFF)
 Whole port mask.
#define IOPORT1   0
 First I/O port identifier.
#define pal_lld_init(config)
 Low level PAL subsystem initialization.
#define pal_lld_readport(port)
 Reads the physical I/O port states.
#define pal_lld_readlatch(port)
 Reads the output latch.
#define pal_lld_writeport(port, bits)
 Writes a bits mask on a I/O port.
#define pal_lld_setport(port, bits)
 Sets a bits mask on a I/O port.
#define pal_lld_clearport(port, bits)
 Clears a bits mask on a I/O port.
#define pal_lld_toggleport(port, bits)
 Toggles a bits mask on a I/O port.
#define pal_lld_readgroup(port, mask, offset)
 Reads a group of bits.
#define pal_lld_writegroup(port, mask, offset, bits)
 Writes a group of bits.
#define pal_lld_setgroupmode(port, mask, mode)
 Pads group mode setup.
#define pal_lld_readpad(port, pad)
 Reads a logical state from an I/O pad.
#define pal_lld_writepad(port, pad, bit)
 Writes a logical state on an output pad.
#define pal_lld_setpad(port, pad)
 Sets a pad logical state to PAL_HIGH.
#define pal_lld_clearpad(port, pad)
 Clears a pad logical state to PAL_LOW.
#define pal_lld_togglepad(port, pad)
 Toggles a pad logical state.
#define pal_lld_setpadmode(port, pad, mode)
 Pad mode setup.

-Typedefs

typedef uint32_t ioportmask_t
 Digital I/O port sized unsigned type.
typedef uint32_t ioportid_t
 Port Identifier.
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Detailed Description

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PAL subsystem low level driver header template.

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Definition in file templates/pal_lld.h.

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pwm_lld.c File Reference

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PWM Driver subsystem low level driver source template. -More...

-#include "ch.h"
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-Functions

void pwm_lld_init (void)
 Low level PWM driver initialization.
void pwm_lld_start (PWMDriver *pwmp)
 Configures and activates the PWM peripheral.
void pwm_lld_stop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
bool_t pwm_lld_is_enabled (PWMDriver *pwmp, pwmchannel_t channel)
 Determines whatever the PWM channel is already enabled.
void pwm_lld_enable_channel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwm_lld_disable_channel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.
-

Detailed Description

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PWM Driver subsystem low level driver source template.

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Definition in file templates/pwm_lld.c.

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pwm_lld.h File Reference

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PWM Driver subsystem low level driver header template. -More...

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-Data Structures

struct  PWMChannelConfig
 PWM driver channel configuration structure. More...
struct  PWMConfig
 Driver configuration structure. More...
struct  PWMDriver
 Structure representing an PWM driver. More...

-Defines

#define PWM_CHANNELS   1
 Number of PWM channels per PWM driver.
#define PWM_FRACTION_TO_WIDTH(pwmp, numerator, denominator)   0
 Converts from fraction to pulse width.
#define PWM_DEGREES_TO_WIDTH(pwmp, degrees)   PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees)
 Converts from degrees to pulse width.
#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage)   PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage)
 Converts from percentage to pulse width.

-Typedefs

typedef uint8_t pwmchannel_t
 PWM channel type.
typedef uint16_t pwmcnt_t
 PWM counter type.
typedef struct PWMDriver PWMDriver
 Type of a structure representing an PWM driver.
typedef void(* pwmcallback_t )(PWMDriver *pwmp)
 PWM notification callback type.

-Functions

void pwm_lld_init (void)
 Low level PWM driver initialization.
void pwm_lld_start (PWMDriver *pwmp)
 Configures and activates the PWM peripheral.
void pwm_lld_stop (PWMDriver *pwmp)
 Deactivates the PWM peripheral.
bool_t pwm_lld_is_enabled (PWMDriver *pwmp, pwmchannel_t channel)
 Determines whatever the PWM channel is already enabled.
void pwm_lld_enable_channel (PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width)
 Enables a PWM channel.
void pwm_lld_disable_channel (PWMDriver *pwmp, pwmchannel_t channel)
 Disables a PWM channel.
-

Detailed Description

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PWM Driver subsystem low level driver header template.

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Definition in file templates/pwm_lld.h.

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serial_lld.c File Reference

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Serial Driver subsystem low level driver source template. -More...

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void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
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Detailed Description

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Serial Driver subsystem low level driver source template.

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Definition in file templates/serial_lld.c.

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Serial Driver subsystem low level driver header template. -More...

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-Data Structures

struct  SerialConfig
 Generic Serial Driver configuration structure. More...

-Defines

#define _serial_driver_data
 SerialDriver specific data.

-Typedefs

typedef uint8_t sdflags_t
 Serial Driver condition flags type.

-Functions

void sd_lld_init (void)
 Low level serial driver initialization.
void sd_lld_start (SerialDriver *sdp, const SerialConfig *config)
 Low level serial driver configuration and (re)start.
void sd_lld_stop (SerialDriver *sdp)
 Low level serial driver stop.
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Detailed Description

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Serial Driver subsystem low level driver header template.

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Definition in file templates/serial_lld.h.

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spi_lld.c File Reference

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SPI Driver subsystem low level driver source template. -More...

-#include "ch.h"
-#include "hal.h"
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-Functions

void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.
-

Detailed Description

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SPI Driver subsystem low level driver source template.

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Definition in file templates/spi_lld.c.

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spi_lld.h File Reference

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SPI Driver subsystem low level driver header template. -More...

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Go to the source code of this file.

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-Data Structures

struct  SPIConfig
 Driver configuration structure. More...
struct  SPIDriver
 Structure representing a SPI driver. More...

-Functions

void spi_lld_init (void)
 Low level SPI driver initialization.
void spi_lld_start (SPIDriver *spip)
 Configures and activates the SPI peripheral.
void spi_lld_stop (SPIDriver *spip)
 Deactivates the SPI peripheral.
void spi_lld_select (SPIDriver *spip)
 Asserts the slave select signal and prepares for transfers.
void spi_lld_unselect (SPIDriver *spip)
 Deasserts the slave select signal.
void spi_lld_ignore (SPIDriver *spip, size_t n)
 Ignores data on the SPI bus.
void spi_lld_exchange (SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
 Exchanges data on the SPI bus.
void spi_lld_send (SPIDriver *spip, size_t n, const void *txbuf)
 Sends data ever the SPI bus.
void spi_lld_receive (SPIDriver *spip, size_t n, void *rxbuf)
 Receives data from the SPI bus.
-

Detailed Description

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SPI Driver subsystem low level driver header template.

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Definition in file templates/spi_lld.h.

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test.c File Reference

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Tests support code. -More...

-#include "ch.h"
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-#include "test.h"
-#include "testthd.h"
-#include "testsem.h"
-#include "testmtx.h"
-#include "testmsg.h"
-#include "testmbox.h"
-#include "testevt.h"
-#include "testheap.h"
-#include "testpools.h"
-#include "testdyn.h"
-#include "testqueues.h"
-#include "testbmk.h"
- -

Go to the source code of this file.

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-Functions

void test_printn (uint32_t n)
 Prints a decimal unsigned number.
void test_print (char *msgp)
 Prints a line without final end-of-line.
void test_println (char *msgp)
 Prints a line.
void test_emit_token (char token)
 Emits a token into the tokens buffer.
void test_terminate_threads (void)
 Pends a termination request in all the test-spawned threads.
void test_wait_threads (void)
 Waits for the completion of all the test-spawned threads.
void test_cpu_pulse (unsigned duration)
 CPU pulse.
systime_t test_wait_tick (void)
 Delays execution until next system time tick.
void test_start_timer (unsigned ms)
 Starts the test timer.
msg_t TestThread (void *p)
 Test execution thread function.

-Variables

bool_t test_timer_done
 Set to TRUE when the test timer reaches its deadline.
-

Detailed Description

-

Tests support code.

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Definition in file test.c.

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test.h File Reference

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Tests support header. -More...

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Go to the source code of this file.

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-Data Structures

struct  testcase
 Structure representing a test case. More...

-Defines

#define DELAY_BETWEEN_TESTS   200
 Delay inserted between test cases.
#define TEST_NO_BENCHMARKS   FALSE
 If TRUE then benchmarks are not included.
#define test_fail(point)
 Test failure enforcement.
#define test_assert(point, condition, msg)
 Test assertion.
#define test_assert_sequence(point, expected)
 Test sequence assertion.
#define test_assert_time_window(point, start, end)
 Test time window assertion.

-Functions

msg_t TestThread (void *p)
 Test execution thread function.
void test_printn (uint32_t n)
 Prints a decimal unsigned number.
void test_print (char *msgp)
 Prints a line without final end-of-line.
void test_println (char *msgp)
 Prints a line.
void test_emit_token (char token)
 Emits a token into the tokens buffer.
void test_terminate_threads (void)
 Pends a termination request in all the test-spawned threads.
void test_wait_threads (void)
 Waits for the completion of all the test-spawned threads.
systime_t test_wait_tick (void)
 Delays execution until next system time tick.
void test_start_timer (unsigned ms)
 Starts the test timer.
void test_cpu_pulse (unsigned duration)
 CPU pulse.
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Detailed Description

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Tests support header.

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Definition in file test.h.

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Kernel Benchmarks

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File: testbmk.c

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Description

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This module implements a series of system benchmarks. The benchmarks are useful as a stress test and as a reference when comparing ChibiOS/RT with similar systems.

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Objective

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Objective of the test module is to provide a performance index for the most critical system subsystems. The performance numbers allow to discover performance regressions between successive ChibiOS/RT releases.

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Preconditions

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None.

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Test Cases

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Messages performance #1

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Description

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A message server thread is created with a lower priority than the client thread, the messages throughput per second is measured and the result printed in the output log.

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Messages performance #2

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Description

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A message server thread is created with an higher priority than the client thread, the messages throughput per second is measured and the result printed in the output log.

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Messages performance #3

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Description

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A message server thread is created with an higher priority than the client thread, four lower priority threads crowd the ready list, the messages throughput per second is measured while the ready list and the result printed in the output log.

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Context Switch performance

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Description

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A thread is created that just performs a chSchGoSleepS() into a loop, the thread is awakened as fast is possible by the tester thread.
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Threads performance, full cycle

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Description

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Threads are continuously created and terminated into a loop. A full chThdCreateStatic() / chThdExit() / chThdWait() cycle is performed in each iteration.
- The performance is calculated by measuring the number of iterations after a second of continuous operations.

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Threads performance, create/exit only

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Description

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Threads are continuously created and terminated into a loop. A partial chThdCreateStatic() / chThdExit() cycle is performed in each iteration, the chThdWait() is not necessary because the thread is created at an higher priority so there is no need to wait for it to terminate.
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Mass reschedule performance

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Description

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Five threads are created and atomically rescheduled by resetting the semaphore where they are waiting on. The operation is performed into a continuous loop.
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I/O Round-Robin voluntary reschedule.

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Description

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Five threads are created at equal priority, each thread just increases a variable and yields.
- The performance is calculated by measuring the number of iterations after a second of continuous operations.

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I/O Queues throughput

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Description

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Four bytes are written and then read from an InputQueue into a continuous loop.
- The performance is calculated by measuring the number of iterations after a second of continuous operations.

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Virtual Timers set/reset performance

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Description

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A virtual timer is set and immediately reset into a continuous loop.
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Semaphores wait/signal performance

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Description

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A counting semaphore is taken/released into a continuous loop, no Context Switch happens because the counter is always non negative.
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Mutexes lock/unlock performance

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Description

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A mutex is locked/unlocked into a continuous loop, no Context Switch happens because there are no other threads asking for the mutex.
- The performance is calculated by measuring the number of iterations after a second of continuous operations.

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RAM Footprint

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Description

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The memory size of the various kernel objects is printed.

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Dynamic APIs test

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File: testdyn.c

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Description

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This module implements the test sequence for the dynamic thread creation APIs.

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Objective

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Objective of the test module is to cover 100% of the dynamic APIs code.

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Preconditions

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The module requires the following kernel options:

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In case some of the required options are not enabled then some or all tests may be skipped.

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Test Cases

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Threads creation from Memory Heap

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Description

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Two threads are started by allocating the memory from the Memory Heap then the remaining heap space is arbitrarily allocated and a third tread startup is attempted.
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Threads creation from Memory Pool

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Description

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Five thread creation are attempted from a pool containing only four elements.
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Registry and References test

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Registry and Thread References APIs are tested for functionality and coverage.

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Events test

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File: testevt.c

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This module implements the test sequence for the Event Flags subsystem.

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Objective

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Objective of the test module is to cover 100% of the Event Flags subsystem.

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Preconditions

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Test Cases

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Events registration and dispatch

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Description

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Two event listeners are registered on an event source and then unregistered in the same order.
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Events wait and broadcast

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Description

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In this test the following APIs are indipently tested by starting threads that signal/broadcast events after fixed delays:

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After each test phase the test verifies that the events have been served at the expected time and that there are no stuck event flags.

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Events timeout

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Description

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In this test the following APIs are let to timeout twice: immediatly and after 10ms: In this test the following APIs are indipently tested by starting threads that broadcast events after fixed delays:

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After each test phase the test verifies that there are no stuck event flags.

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Memory Heap test

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File: testheap.c

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Description

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This module implements the test sequence for the Heaps subsystem.

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Objective

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Objective of the test module is to cover 100% of the Heaps subsystem.

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Preconditions

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The module requires the following kernel options:

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In case some of the required options are not enabled then some or all tests may be skipped.

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Test Cases

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Allocation and fragmentation test

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Description

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Series of allocations/deallocations are performed in carefully designed sequences in order to stimulate all the possible code paths inside the allocator.
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- - diff --git a/ChibiOS_2.0.8/docs/html/test_mbox.html b/ChibiOS_2.0.8/docs/html/test_mbox.html deleted file mode 100644 index 5ed80fe..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mbox.html +++ /dev/null @@ -1,60 +0,0 @@ - - -ChibiOS/RT: Mailboxes test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Mailboxes test

-
-
-

File: testmbox.c

-

Description

-

This module implements the test sequence for the Mailboxes subsystem.

-

Objective

-

Objective of the test module is to cover 100% of the Mailboxes subsystem code.
- Note that the Mailboxes subsystem depends on the Semaphores subsystem that has to met its testing objectives as well.

-

Preconditions

-

The module requires the following kernel options:

-
    -
  • CH_USE_MAILBOXES
    • -
-

In case some of the required options are not enabled then some or all tests may be skipped.

-

Test Cases

- -
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mbox_001.html b/ChibiOS_2.0.8/docs/html/test_mbox_001.html deleted file mode 100644 index 2d677a9..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mbox_001.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Queuing and timeouts - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Queuing and timeouts

-
-
-

Description

-

Messages are posted/fetched from a mailbox in carefully designed sequences in order to stimulate all the possible code paths inside the mailbox.
- The test expects to find a consistent mailbox status after each operation.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_msg.html b/ChibiOS_2.0.8/docs/html/test_msg.html deleted file mode 100644 index a65af05..0000000 --- a/ChibiOS_2.0.8/docs/html/test_msg.html +++ /dev/null @@ -1,59 +0,0 @@ - - -ChibiOS/RT: Messages test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Messages test

-
-
-

File: testmsg.c

-

Description

-

This module implements the test sequence for the Synchronous Messages subsystem.

-

Objective

-

Objective of the test module is to cover 100% of the Synchronous Messages subsystem code.

-

Preconditions

-

The module requires the following kernel options:

-
    -
  • CH_USE_MESSAGES
    • -
-

In case some of the required options are not enabled then some or all tests may be skipped.

-

Test Cases

- -
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_msg_001.html b/ChibiOS_2.0.8/docs/html/test_msg_001.html deleted file mode 100644 index b0f3553..0000000 --- a/ChibiOS_2.0.8/docs/html/test_msg_001.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Messages Server loop - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Messages Server loop

-
-
-

Description

-

A thread is spawned that sends four messages back to the tester thread.
- The test expect to receive the messages in the correct sequence and to not find a fifth message waiting.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx.html b/ChibiOS_2.0.8/docs/html/test_mtx.html deleted file mode 100644 index 75304fc..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx.html +++ /dev/null @@ -1,69 +0,0 @@ - - -ChibiOS/RT: Mutexes test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Mutexes test

-
-
-

File: testmtx.c

-

Description

-

This module implements the test sequence for the Mutexes and Condition Variables subsystems.
- Tests on those subsystems are particularly critical because the system-wide implications of the Priority Inheritance mechanism.

-

Objective

-

Objective of the test module is to cover 100% of the subsystems code.

-

Preconditions

-

The module requires the following kernel options:

-
    -
  • CH_USE_MUTEXES
    • -
  • CH_USE_CONDVARS
    • -
  • CH_DBG_THREADS_PROFILING
    • -
-

In case some of the required options are not enabled then some or all tests may be skipped.

-

Test Cases

- -
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx_001.html b/ChibiOS_2.0.8/docs/html/test_mtx_001.html deleted file mode 100644 index 6e9ed6c..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx_001.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Priority enqueuing test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Priority enqueuing test

-
-
-

Description

-

Five threads, with increasing priority, are enqueued on a locked mutex then the mutex is unlocked.
- The test expects the threads to perform their operations in increasing priority order regardless of the initial order.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx_002.html b/ChibiOS_2.0.8/docs/html/test_mtx_002.html deleted file mode 100644 index c227311..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx_002.html +++ /dev/null @@ -1,64 +0,0 @@ - - -ChibiOS/RT: Priority inheritance, simple case - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Priority inheritance, simple case

-
-
-

Description

-

Three threads are involved in the classic priority inversion scenario, a medium priority thread tries to starve an high priority thread by blocking a low priority thread into a mutex lock zone.
- The test expects the threads to reach their goal in increasing priority order by rearranging their priorities in order to avoid the priority inversion trap.

-

Scenario

-

This weird looking diagram should explain what happens in the test case:

-
 Time ----> 0     10    20    30    40    50    60    70    80    90    100
-    0 ......AL++++++++++............2+++++++++++AU0---------------++++++G...
-    1 ..................++++++++++++------------------++++++++++++G.........
-    2  .............................AL..........++++++AUG...................
-                                    ^           ^
- Legend:
-   0..2 - Priority levels
-   +++  - Running
-   ---  - Ready
-   ...  - Waiting or Terminated
-   xL   - Lock operation on mutex 'x'
-   xUn  - Unlock operation on mutex 'x' with priority returning to level 'n'
-   G    - Goal
-   ^    - Priority transition (boost or return).
-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx_003.html b/ChibiOS_2.0.8/docs/html/test_mtx_003.html deleted file mode 100644 index 59ca17b..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx_003.html +++ /dev/null @@ -1,65 +0,0 @@ - - -ChibiOS/RT: Priority inheritance, complex case - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Priority inheritance, complex case

-
-
-

Description

-

Five threads are involved in the complex priority inversion scenario, please refer to the diagram below for the complete scenario.
- The test expects the threads to perform their operations in increasing priority order by rearranging their priorities in order to avoid the priority inversion trap.

-

Scenario

-

This weird looking diagram should explain what happens in the test case:

-
 Time ----> 0     10    20    30    40    50    60    70    80    90    100   110
-    0 ......BL++++------------2+++++------4+++++BU0---------------------------G.....
-    1 ............AL++++2+++++BL----------4-----++++++BU4+++AU1---------------G.....
-    2 ..................AL----------------------------------------------++++++AUG...
-    3 ..............................+++++++-----------------------++++++G...........
-    4 ....................................AL................++++++AUG...............
-                        ^     ^           ^     ^     ^     ^
- Legend:
-   0..4 - Priority levels
-   +++  - Running
-   ---  - Ready
-   ...  - Waiting or Terminated
-   xL   - Lock operation on mutex 'x'
-   xUn  - Unlock operation on mutex 'x' with priority returning to level 'n'
-   ^    - Priority transition (boost or return).
-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx_004.html b/ChibiOS_2.0.8/docs/html/test_mtx_004.html deleted file mode 100644 index ab6d9ec..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx_004.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Priority return verification - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Priority return verification

-
-
-

Description

-

Two threads are spawned that try to lock the mutexes locked by the tester thread with precise timing.
- The test expects that the priority changes caused by the priority inheritance algorithm happen at the right moment and with the right values.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx_005.html b/ChibiOS_2.0.8/docs/html/test_mtx_005.html deleted file mode 100644 index 4885130..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx_005.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Mutex status - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Mutex status

-
-
-

Description

-

Various tests on the mutex structure status after performing some lock and unlock operations.
- The test expects that the internal mutex status is consistent after each operation.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx_006.html b/ChibiOS_2.0.8/docs/html/test_mtx_006.html deleted file mode 100644 index eed2556..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx_006.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Condition Variable signal test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Condition Variable signal test

-
-
-

Description

-

Five threads take a mutex and then enter a conditional variable queue, the tester thread then proceeds to signal the conditional variable five times atomically.
- The test expects the threads to reach their goal in increasing priority order regardless of the initial order.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx_007.html b/ChibiOS_2.0.8/docs/html/test_mtx_007.html deleted file mode 100644 index 983f663..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx_007.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Condition Variable broadcast test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Condition Variable broadcast test

-
-
-

Description

-

Five threads take a mutex and then enter a conditional variable queue, the tester thread then proceeds to broadcast the conditional variable.
- The test expects the threads to reach their goal in increasing priority order regardless of the initial order.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_mtx_008.html b/ChibiOS_2.0.8/docs/html/test_mtx_008.html deleted file mode 100644 index 94c6d27..0000000 --- a/ChibiOS_2.0.8/docs/html/test_mtx_008.html +++ /dev/null @@ -1,47 +0,0 @@ - - -ChibiOS/RT: Condition Variable priority boost test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Condition Variable priority boost test

-
-
-

Description

-

This test case verifies the priority boost of a thread waiting on a conditional variable queue. It tests this very specific situation in order to complete the code coverage.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_pools.html b/ChibiOS_2.0.8/docs/html/test_pools.html deleted file mode 100644 index db81999..0000000 --- a/ChibiOS_2.0.8/docs/html/test_pools.html +++ /dev/null @@ -1,59 +0,0 @@ - - -ChibiOS/RT: Memory Pools test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Memory Pools test

-
-
-

File: testpools.c

-

Description

-

This module implements the test sequence for the Memory Pools subsystem.

-

Objective

-

Objective of the test module is to cover 100% of the Memory Pools code.

-

Preconditions

-

The module requires the following kernel options:

-
    -
  • CH_USE_MEMPOOLS
    • -
-

In case some of the required options are not enabled then some or all tests may be skipped.

-

Test Cases

- -
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_pools_001.html b/ChibiOS_2.0.8/docs/html/test_pools_001.html deleted file mode 100644 index 41b8f75..0000000 --- a/ChibiOS_2.0.8/docs/html/test_pools_001.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Allocation and enqueuing test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Allocation and enqueuing test

-
-
-

Description

-

Five memory blocks are added to a memory pool then removed.
- The test expects to find the pool queue in the proper status after each operation.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_queues.html b/ChibiOS_2.0.8/docs/html/test_queues.html deleted file mode 100644 index 2b3d5a5..0000000 --- a/ChibiOS_2.0.8/docs/html/test_queues.html +++ /dev/null @@ -1,61 +0,0 @@ - - -ChibiOS/RT: I/O Queues test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

I/O Queues test

-
-
-

File: testqueues.c

-

Description

-

This module implements the test sequence for the I/O Queues subsystem. The tests are performed by inserting and removing data from queues and by checking both the queues status and the correct sequence of the extracted data.

-

Objective

-

Objective of the test module is to cover 100% of the I/O Queues code.
- Note that the I/O Queues subsystem depends on the Semaphores subsystem that has to met its testing objectives as well.

-

Preconditions

-

The module requires the following kernel options:

-
    -
  • CH_USE_QUEUES (and dependent options)
    • -
-

In case some of the required options are not enabled then some or all tests may be skipped.

-

Test Cases

- -
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_queues_001.html b/ChibiOS_2.0.8/docs/html/test_queues_001.html deleted file mode 100644 index 611c56e..0000000 --- a/ChibiOS_2.0.8/docs/html/test_queues_001.html +++ /dev/null @@ -1,47 +0,0 @@ - - -ChibiOS/RT: Input Queues functionality and APIs - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Input Queues functionality and APIs

-
-
-

Description

-

This test case tests sysnchronos and asynchronous operations on an InputQueue object including timeouts. The queue state must remain consistent through the whole test.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_queues_002.html b/ChibiOS_2.0.8/docs/html/test_queues_002.html deleted file mode 100644 index 67bf137..0000000 --- a/ChibiOS_2.0.8/docs/html/test_queues_002.html +++ /dev/null @@ -1,47 +0,0 @@ - - -ChibiOS/RT: Output Queues functionality and APIs - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Output Queues functionality and APIs

-
-
-

Description

-

This test case tests sysnchronos and asynchronous operations on an OutputQueue object including timeouts. The queue state must remain consistent through the whole test.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_sem.html b/ChibiOS_2.0.8/docs/html/test_sem.html deleted file mode 100644 index a2ca401..0000000 --- a/ChibiOS_2.0.8/docs/html/test_sem.html +++ /dev/null @@ -1,61 +0,0 @@ - - -ChibiOS/RT: Semaphores test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Semaphores test

-
-
-

File: testsem.c

-

Description

-

This module implements the test sequence for the Semaphores subsystem.

-

Objective

-

Objective of the test module is to cover 100% of the Semaphores code.

-

Preconditions

-

The module requires the following kernel options:

-
    -
  • CH_USE_SEMAPHORES
    • -
-

In case some of the required options are not enabled then some or all tests may be skipped.

-

Test Cases

- -
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_sem_001.html b/ChibiOS_2.0.8/docs/html/test_sem_001.html deleted file mode 100644 index eb39bfe..0000000 --- a/ChibiOS_2.0.8/docs/html/test_sem_001.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Enqueuing test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Enqueuing test

-
-
-

Description

-

Five threads with randomized priorities are enqueued to a semaphore then awakened one at time.
- The test expects that the threads reach their goal in FIFO order or priority order depending on the CH_USE_SEMAPHORES_PRIORITY configuration setting.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_sem_002.html b/ChibiOS_2.0.8/docs/html/test_sem_002.html deleted file mode 100644 index f6f0e43..0000000 --- a/ChibiOS_2.0.8/docs/html/test_sem_002.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Timeout test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Timeout test

-
-
-

Description

-

The three possible semaphore waiting modes (do not wait, wait with timeout, wait without timeout) are explored.
- The test expects that the semaphore wait function returns the correct value in each of the above scenario and that the semaphore structure status is correct after each operation.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_sem_003.html b/ChibiOS_2.0.8/docs/html/test_sem_003.html deleted file mode 100644 index 26878d8..0000000 --- a/ChibiOS_2.0.8/docs/html/test_sem_003.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Atomic signal-wait test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Atomic signal-wait test

-
-
-

Description

-

This test case explicitly address the chSemWaitSignal() function. A thread is created that performs a wait and a signal operations. The tester thread is awakened from an atomic wait/signal operation.
- The test expects that the semaphore wait function returns the correct value in each of the above scenario and that the semaphore structure status is correct after each operation.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_threads.html b/ChibiOS_2.0.8/docs/html/test_threads.html deleted file mode 100644 index 1dcf5c3..0000000 --- a/ChibiOS_2.0.8/docs/html/test_threads.html +++ /dev/null @@ -1,59 +0,0 @@ - - -ChibiOS/RT: Threads and Scheduler test - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Threads and Scheduler test

-
-
-

File: testthd.c

-

Description

-

This module implements the test sequence for the Scheduler, Threads and Time and Virtual Timers subsystems.
- Note that the tests on those subsystems are formally required but most of their functionality is already demonstrated because the test suite itself depends on them, anyway double check is good.

-

Objective

-

Objective of the test module is to cover 100% of the subsystems code.

-

Preconditions

-

None.

-

Test Cases

- -
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_threads_001.html b/ChibiOS_2.0.8/docs/html/test_threads_001.html deleted file mode 100644 index e7a1d57..0000000 --- a/ChibiOS_2.0.8/docs/html/test_threads_001.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Ready List functionality #1 - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Ready List functionality #1

-
-
-

Description

-

Five threads, with increasing priority, are enqueued in the ready list and atomically executed.
- The test expects the threads to perform their operations in increasing priority order regardless of the initial order.

-
-
-Generated on Sun Nov 28 2010 14:09:56 for ChibiOS/RT by doxygen 1.7.1
- - diff --git a/ChibiOS_2.0.8/docs/html/test_threads_002.html b/ChibiOS_2.0.8/docs/html/test_threads_002.html deleted file mode 100644 index 34db5db..0000000 --- a/ChibiOS_2.0.8/docs/html/test_threads_002.html +++ /dev/null @@ -1,48 +0,0 @@ - - -ChibiOS/RT: Ready List functionality #2 - - - - - - - - - - - -
ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
-
- - -
-
-

Ready List functionality #2

-
-
-

Description

-

Five threads, with pseudo-random priority, are enqueued in the ready list and atomically executed.
- The test expects the threads to perform their operations in increasing priority order regardless of the initial order.

-
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A series of priority changes are performed on the current thread in order to verify that the priority change happens as expected.
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Threads delays test

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Delay APIs and associated macros are tested, the invoking thread is verified to wake up at the exact expected time.

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Kernel Benchmarks header file.

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Definition in file testbmk.h.

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typedefs.h File Reference

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Dummy typedefs file. -More...

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Detailed Description

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Dummy typedefs file.

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Definition in file typedefs.h.

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__ioport Union Reference
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#include <pal_lld.h>

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Generic MSP430 I/O port.

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heap_header Union Reference
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Memory heap block header.

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Field Documentation

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Next block in free list.

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Block owner heap.

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Size of the memory block.

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LPC214x VIC peripheral support code. -More...

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void vic_init (void)
 VIC Initialization.
void SetVICVector (void *handler, int vector, int source)
 Initializes a VIC vector.
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Detailed Description

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LPC214x VIC peripheral support code.

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Definition in file vic.c.

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LPC214x VIC peripheral support header. -More...

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void vic_init (void)
 VIC Initialization.
void SetVICVector (void *handler, int vector, int source)
 Initializes a VIC vector.
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Detailed Description

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LPC214x VIC peripheral support header.

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Definition in file vic.h.

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- - diff --git a/ChibiOS_2.0.8/docs/html/vic_8h_source.html b/ChibiOS_2.0.8/docs/html/vic_8h_source.html deleted file mode 100644 index 0d4cfa6..0000000 --- a/ChibiOS_2.0.8/docs/html/vic_8h_source.html +++ /dev/null @@ -1,93 +0,0 @@ - - -ChibiOS/RT: vic.h Source File - - - - - - - - - - - -
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The ./bin directory must be specified in the path in - order to make Graphviz accessible by Doxygen. - -Build procedure: -- Run Doxywizard. -- Load ./docs/Doxyfile from Doxywizard. -- Start. - -*** Doxygen usage rules *** -- The JavaDoc style is recommended (@ instad of \, /** instead of /*!). -- Params descriptions must not begin with a capital letter and must not be - terminated with a dot unless it is composed of multiple paragraphs. -- Retvals descriptions must not begin with a capital letter but must be - terminated by a dot. -- Normal paragraphs, return rescriptions and notes must start with a capital - letter and must be terminated with a dot. -- Multiple return values should be listed using the @retval command. -- Parameters direction must be specified. - -Examples: -@note This is a note. -@retval RDY_OK is a possible return value. -@return The pointer to the created thread is returned. -@param[in] n the number of bytes to be written -@param[in] n the number of bytes to be written. This value can be zero. diff --git a/ChibiOS_2.0.8/docs/reports/AT91SAM7X-48-ARM.txt b/ChibiOS_2.0.8/docs/reports/AT91SAM7X-48-ARM.txt deleted file mode 100644 index c8366c3..0000000 --- a/ChibiOS_2.0.8/docs/reports/AT91SAM7X-48-ARM.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -Settings: MCK=48.054857, MC_FMR = AT91C_MC_FWS_1FWS (1 wait state) -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 4.5.1 -*** Architecture: ARM -*** Core Variant: ARM7TDMI -*** Platform: AT91SAM7x -*** Test Board: Olimex SAM7-EX256 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 114671 msgs/S, 229342 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 89883 msgs/S, 179766 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 89883 msgs/S, 179766 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 380272 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 67349 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 96994 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 27231 reschedules/S, 163386 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 211348 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 239264 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 264214 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 449036 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 322036 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 356 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/AT91SAM7X-48-THUMB.txt b/ChibiOS_2.0.8/docs/reports/AT91SAM7X-48-THUMB.txt deleted file mode 100644 index dad364a..0000000 --- a/ChibiOS_2.0.8/docs/reports/AT91SAM7X-48-THUMB.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -Settings: MCK=48.054857, MC_FMR = AT91C_MC_FWS_1FWS (1 wait state) -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 4.5.1 -*** Architecture: ARM -*** Core Variant: ARM7TDMI -*** Platform: AT91SAM7x -*** Test Board: Olimex SAM7-EX256 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 106525 msgs/S, 213050 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 87601 msgs/S, 175202 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 87601 msgs/S, 175202 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 405776 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 70339 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 105584 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 28624 reschedules/S, 171744 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 212116 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 258636 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 323178 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 364428 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 256808 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 356 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/ATmega128-16.txt b/ChibiOS_2.0.8/docs/reports/ATmega128-16.txt deleted file mode 100644 index 3cf7136..0000000 --- a/ChibiOS_2.0.8/docs/reports/ATmega128-16.txt +++ /dev/null @@ -1,150 +0,0 @@ -*************************************************************************** -Options: -O2 -Settings: F_CPU=16000000 -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 4.3.0 -*** Architecture: AVR -*** Core Variant: MegaAVR -*** Platform: ATmega128 -*** Test Board: Olimex AVR-MT-128 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 31125 msgs/S, 62250 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 24979 msgs/S, 49958 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 24979 msgs/S, 49958 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 89904 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 21253 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 27451 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 7970 reschedules/S, 47820 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 60760 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 80180 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 81522 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 227560 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 116720 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 230 bytes ---- Thread: 29 bytes ---- Timer : 10 bytes ---- Semaph: 5 bytes ---- EventS: 2 bytes ---- EventL: 5 bytes ---- Mutex : 8 bytes ---- CondV.: 4 bytes ---- Queue : 15 bytes ---- MailB.: 18 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/LPC1114-48.txt b/ChibiOS_2.0.8/docs/reports/LPC1114-48.txt deleted file mode 100644 index dc6d4b1..0000000 --- a/ChibiOS_2.0.8/docs/reports/LPC1114-48.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu -Settings: CLK=48, (3 wait states) -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 4.3.3 -*** Architecture: ARMv6-M -*** Core Variant: Cortex-M0 -*** Platform: LPC11xx -*** Test Board: Embedded Artists LPCXpresso Base Board + LPC1114 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 124136 msgs/S, 248272 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 99992 msgs/S, 199984 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 99992 msgs/S, 199984 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 380432 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 80188 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 111404 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 31034 reschedules/S, 186204 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 253200 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 298992 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 350196 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 591948 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 334860 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 360 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/LPC1343-72.txt b/ChibiOS_2.0.8/docs/reports/LPC1343-72.txt deleted file mode 100644 index 8c57533..0000000 --- a/ChibiOS_2.0.8/docs/reports/LPC1343-72.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu -Settings: CLK=72, (3 wait states) -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 4.3.3 -*** Architecture: ARMv7-M -*** Core Variant: Cortex-M3 -*** Platform: LPC13xx -*** Test Board: Embedded Artists LPCXpresso Base Board + LPC1343 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 241880 msgs/S, 483760 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 196281 msgs/S, 392562 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 196281 msgs/S, 392562 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 806072 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 155163 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 219028 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 63239 reschedules/S, 379434 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 473392 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 482836 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 707908 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 909504 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 588968 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 360 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/LPC2148-48-ARM.txt b/ChibiOS_2.0.8/docs/reports/LPC2148-48-ARM.txt deleted file mode 100644 index ff11fc2..0000000 --- a/ChibiOS_2.0.8/docs/reports/LPC2148-48-ARM.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -falign-functions=16 -Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states) -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 4.5.1 -*** Architecture: ARM -*** Core Variant: ARM7TDMI -*** Platform: LPC214x -*** Test Board: Olimex LCP-P2148 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 145386 msgs/S, 290772 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 113890 msgs/S, 227780 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 113890 msgs/S, 227780 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 493760 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 89745 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 128237 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 35380 reschedules/S, 212280 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 276080 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 341980 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 333360 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 607412 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 380408 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 356 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/LPC2148-48-THUMB.txt b/ChibiOS_2.0.8/docs/reports/LPC2148-48-THUMB.txt deleted file mode 100644 index 1fb66d2..0000000 --- a/ChibiOS_2.0.8/docs/reports/LPC2148-48-THUMB.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -falign-functions=16 -Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states) -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 4.5.1 -*** Architecture: ARM -*** Core Variant: ARM7TDMI -*** Platform: LPC214x -*** Test Board: Olimex LCP-P2148 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 106224 msgs/S, 212448 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 88032 msgs/S, 176064 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 88032 msgs/S, 176064 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 412536 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 71990 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 110394 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 29290 reschedules/S, 175740 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 221560 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 261396 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 326304 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 350836 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 244200 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 356 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/MSP430F1611-0.75.txt b/ChibiOS_2.0.8/docs/reports/MSP430F1611-0.75.txt deleted file mode 100644 index 035644f..0000000 --- a/ChibiOS_2.0.8/docs/reports/MSP430F1611-0.75.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -Settings: MCLK=DCOCLK 750KHz -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 3.2.3 -*** Architecture: MSP430 -*** Core Variant: MSP430 -*** Platform: MSP430x16x -*** Test Board: Olimex MSP430-P1611 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 1971 msgs/S, 3942 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 1624 msgs/S, 3248 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 1624 msgs/S, 3248 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 5912 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 1145 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 1545 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 494 reschedules/S, 2964 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 3820 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 4920 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 5644 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 13908 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 7524 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 220 bytes ---- Thread: 36 bytes ---- Timer : 10 bytes ---- Semaph: 6 bytes ---- EventS: 2 bytes ---- EventL: 6 bytes ---- Mutex : 8 bytes ---- CondV.: 4 bytes ---- Queue : 16 bytes ---- MailB.: 20 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/MSP430F1611-8.txt b/ChibiOS_2.0.8/docs/reports/MSP430F1611-8.txt deleted file mode 100644 index 9f9009b..0000000 --- a/ChibiOS_2.0.8/docs/reports/MSP430F1611-8.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -Settings: MCLK=XT2CLK 8MHz -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** GCC Version: 3.2.3 -*** Architecture: MSP430 -*** Core Variant: MSP430 -*** Platform: MSP430x16x -*** Test Board: Olimex MSP430-P1611 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 21356 msgs/S, 42712 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 17593 msgs/S, 35186 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 17593 msgs/S, 35186 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 64024 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 12402 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 16745 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 5350 reschedules/S, 32100 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 41336 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 53292 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 60970 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 150700 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 81504 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 220 bytes ---- Thread: 36 bytes ---- Timer : 10 bytes ---- Semaph: 6 bytes ---- EventS: 2 bytes ---- EventL: 6 bytes ---- Mutex : 8 bytes ---- CondV.: 4 bytes ---- Queue : 16 bytes ---- MailB.: 20 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/SPC563M64-80.txt b/ChibiOS_2.0.8/docs/reports/SPC563M64-80.txt deleted file mode 100644 index 9ad1888..0000000 --- a/ChibiOS_2.0.8/docs/reports/SPC563M64-80.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -msdata=none -falign-functions=16 -Settings: SYSCLK=80, optimal wait states, prefetching enabled -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.0 -*** GCC Version: 4.4.1 -*** Architecture: PowerPC -*** Core Variant: e200z3 -*** Platform: SPC563M64 -*** Test Board: Generic SPC563 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 281168 msgs/S, 562336 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 226208 msgs/S, 452416 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 226208 msgs/S, 452416 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 907432 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 182729 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 263538 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 74067 reschedules/S, 444402 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 614140 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 618384 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 1093664 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 1027008 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 871856 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 760 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/STM32F103-48.txt b/ChibiOS_2.0.8/docs/reports/STM32F103-48.txt deleted file mode 100644 index c3bb59b..0000000 --- a/ChibiOS_2.0.8/docs/reports/STM32F103-48.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -falign-functions=16 -Settings: SYSCLK=48, ACR=0x11 (1 wait state) -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.8 -*** GCC Version: 4.5.1 -*** Architecture: ARMv7-M -*** Core Variant: Cortex-M3 -*** Platform: STM32 MD -*** Test Board: Olimex STM32-P103 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 186215 msgs/S, 372430 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 152411 msgs/S, 304822 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 152411 msgs/S, 304822 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 613592 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 117593 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 173405 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 46508 reschedules/S, 279048 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 357804 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 355212 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 514688 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 640320 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 475080 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 360 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/STM32F103-72.txt b/ChibiOS_2.0.8/docs/reports/STM32F103-72.txt deleted file mode 100644 index 5c1ff5d..0000000 --- a/ChibiOS_2.0.8/docs/reports/STM32F103-72.txt +++ /dev/null @@ -1,159 +0,0 @@ -*************************************************************************** -Options: -O2 -fomit-frame-pointer -falign-functions=16 -Settings: SYSCLK=72, ACR=0x12 (2 wait states) -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.8 -*** GCC Version: 4.5.1 -*** Architecture: ARMv7-M -*** Core Variant: Cortex-M3 -*** Platform: STM32 MD -*** Test Board: Olimex STM32-P103 - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.1 (Mutexes, priority enqueuing test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.2 (Mutexes, priority inheritance, simple case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.3 (Mutexes, priority inheritance, complex case) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.4 (Mutexes, priority return) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.5 (Mutexes, status) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.6 (CondVar, signal test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.7 (CondVar, broadcast test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 3.8 (CondVar, boost test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 5.1 (Mailboxes, queuing and timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 248573 msgs/S, 497146 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 201227 msgs/S, 402454 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 201227 msgs/S, 402454 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 839008 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 156856 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 235543 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 61138 reschedules/S, 366828 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 478120 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 465772 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 647262 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 787368 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 586492 lock+unlock/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 360 bytes ---- Thread: 68 bytes ---- Timer : 20 bytes ---- Semaph: 12 bytes ---- EventS: 4 bytes ---- EventL: 12 bytes ---- Mutex : 16 bytes ---- CondV.: 8 bytes ---- Queue : 32 bytes ---- MailB.: 40 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/STM8S208-16.txt b/ChibiOS_2.0.8/docs/reports/STM8S208-16.txt deleted file mode 100644 index 0ff71dc..0000000 --- a/ChibiOS_2.0.8/docs/reports/STM8S208-16.txt +++ /dev/null @@ -1,124 +0,0 @@ -*************************************************************************** -Options: Optimized for speed (3) -Settings: CPUCLK=16MHz (HSI) -Compiler: Raisonance RKit-STM8_2.30.10.0175 -*************************************************************************** - -*** ChibiOS/RT test suite -*** -*** Kernel: 2.0.6 -*** Architecture: STM8 -*** Platform: STM8x -*** Test Board: Raisonance REva V3 + STM8S208RB - ----------------------------------------------------------------------------- ---- Test Case 1.1 (Threads, enqueuing test #1) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.2 (Threads, enqueuing test #2) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.3 (Threads, priority change) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 1.4 (Threads, delays) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.1 (Semaphores, enqueuing) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.2 (Semaphores, timeout) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 2.3 (Semaphores, atomic signal-wait) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 4.1 (Messages, loop) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.1 (Events, registration and dispatch) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.2 (Events, wait and broadcast) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 6.3 (Events, timeouts) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 7.1 (Heap, allocation and fragmentation test) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 8.1 (Memory Pools, queue/dequeue) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.1 (Dynamic APIs, threads creation from heap) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 9.3 (Dynamic APIs, registry and references) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.1 (Queues, input queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 10.2 (Queues, output queues) ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.1 (Benchmark, messages #1) ---- Score : 31402 msgs/S, 62804 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.2 (Benchmark, messages #2) ---- Score : 24108 msgs/S, 48216 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.3 (Benchmark, messages #3) ---- Score : 24108 msgs/S, 48216 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.4 (Benchmark, context switch) ---- Score : 108184 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 18102 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 28190 threads/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 6956 reschedules/S, 41736 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 54180 ctxswc/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 62808 bytes/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 57788 timers/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 211004 wait+signal/S ---- Result: SUCCESS ----------------------------------------------------------------------------- ---- Test Case 11.12 (Benchmark, RAM footprint) ---- System: 177 bytes ---- Thread: 29 bytes ---- Timer : 10 bytes ---- Semaph: 6 bytes ---- EventS: 2 bytes ---- EventL: 5 bytes ---- Queue : 16 bytes ---- Result: SUCCESS ----------------------------------------------------------------------------- - -Final result: SUCCESS diff --git a/ChibiOS_2.0.8/docs/reports/build.txt b/ChibiOS_2.0.8/docs/reports/build.txt deleted file mode 100644 index c530404..0000000 --- a/ChibiOS_2.0.8/docs/reports/build.txt +++ /dev/null @@ -1,48 +0,0 @@ -Default maximum settings - * Building...OK - * Testing...OK -CH_OPTIMIZE_SPEED=FALSE - * Building...OK - * Testing...OK -CH_USE_NESTED_LOCKS=TRUE - * Building...OK - * Testing...OK -CH_TIME_QUANTUM=0 - * Building...OK - * Testing...OK -CH_USE_REGISTRY=FALSE - * Building...OK - * Testing...OK -CH_USE_SEMAPHORES_PRIORITY=TRUE - * Building...OK - * Testing...OK -CH_USE_CONDVARS_TIMEOUT=FALSE - * Building...OK - * Testing...OK -CH_USE_EVENTS_TIMEOUT=FALSE - * Building...OK - * Testing...OK -CH_USE_MESSAGES_PRIORITY=TRUE - * Building...OK - * Testing...OK -CH_USE_DYNAMIC=FALSE - * Building...OK - * Testing...OK -CH_DBG_ENABLE_CHECKS=TRUE - * Building...OK - * Testing...OK -CH_DBG_ENABLE_ASSERTS=TRUE - * Building...OK - * Testing...OK -CH_DBG_ENABLE_TRACE=TRUE - * Building...OK - * Testing...OK -CH_DBG_ENABLE_STACK_CHECK=TRUE - * Building...OK - * Testing...OK -CH_DBG_FILL_THREADS=TRUE - * Building...OK - * Testing...OK -CH_DBG_THREADS_PROFILING=FALSE - * Building...OK - * Testing...OK diff --git a/ChibiOS_2.0.8/docs/reports/coverage.txt b/ChibiOS_2.0.8/docs/reports/coverage.txt deleted file mode 100644 index b8a1eee..0000000 --- a/ChibiOS_2.0.8/docs/reports/coverage.txt +++ /dev/null @@ -1,71 +0,0 @@ -mkdir gcov -gcov -u ..\..\os\kernel\src\chsys.c ..\..\os\kernel\src\chdebug.c ..\..\os\kernel\src\chlists.c ..\..\os\kernel\src\chvt.c ..\..\os\kernel\src\chschd.c ..\..\os\kernel\src\chthreads.c ..\..\os\kernel\src\chregistry.c ..\..\os\kernel\src\chsem.c ..\..\os\kernel\src\chmtx.c ..\..\os\kernel\src\chcond.c ..\..\os\kernel\src\chevents.c ..\..\os\kernel\src\chmsg.c ..\..\os\kernel\src\chmboxes.c ..\..\os\kernel\src\chqueues.c ..\..\os\kernel\src\chmemcore.c ..\..\os\kernel\src\chheap.c ..\..\os\kernel\src\chmempools.c -File `../../os/kernel/src/chsys.c' -Lines executed:100.00% of 27 -../../os/kernel/src/chsys.c:creating `chsys.c.gcov' - -File `../../os/kernel/src/chdebug.c' -Lines executed:76.92% of 13 -../../os/kernel/src/chdebug.c:creating `chdebug.c.gcov' - -File `../../os/kernel/src/chlists.c' -Lines executed:100.00% of 31 -../../os/kernel/src/chlists.c:creating `chlists.c.gcov' - -File `../../os/kernel/src/chvt.c' -Lines executed:100.00% of 29 -../../os/kernel/src/chvt.c:creating `chvt.c.gcov' - -File `../../os/kernel/src/chschd.c' -Lines executed:100.00% of 67 -../../os/kernel/src/chschd.c:creating `chschd.c.gcov' - -File `../../os/kernel/src/chthreads.c' -Lines executed:95.62% of 137 -../../os/kernel/src/chthreads.c:creating `chthreads.c.gcov' - -File `../../os/kernel/src/chregistry.c' -Lines executed:100.00% of 18 -../../os/kernel/src/chregistry.c:creating `chregistry.c.gcov' - -File `../../os/kernel/src/chsem.c' -Lines executed:100.00% of 74 -../../os/kernel/src/chsem.c:creating `chsem.c.gcov' - -File `../../os/kernel/src/chmtx.c' -Lines executed:99.10% of 111 -../../os/kernel/src/chmtx.c:creating `chmtx.c.gcov' - -File `../../os/kernel/src/chcond.c' -Lines executed:100.00% of 59 -../../os/kernel/src/chcond.c:creating `chcond.c.gcov' - -File `../../os/kernel/src/chevents.c' -Lines executed:100.00% of 111 -../../os/kernel/src/chevents.c:creating `chevents.c.gcov' - -File `../../os/kernel/src/chmsg.c' -Lines executed:100.00% of 32 -../../os/kernel/src/chmsg.c:creating `chmsg.c.gcov' - -File `../../os/kernel/src/chmboxes.c' -Lines executed:100.00% of 65 -../../os/kernel/src/chmboxes.c:creating `chmboxes.c.gcov' - -File `../../os/kernel/src/chqueues.c' -Lines executed:100.00% of 112 -../../os/kernel/src/chqueues.c:creating `chqueues.c.gcov' - -File `../../os/kernel/src/chmemcore.c' -Lines executed:100.00% of 20 -../../os/kernel/src/chmemcore.c:creating `chmemcore.c.gcov' - -File `../../os/kernel/src/chheap.c' -Lines executed:100.00% of 79 -../../os/kernel/src/chheap.c:creating `chheap.c.gcov' - -File `../../os/kernel/src/chmempools.c' -Lines executed:100.00% of 28 -../../os/kernel/src/chmempools.c:creating `chmempools.c.gcov' - -mv -f *.gcov ./gcov diff --git a/ChibiOS_2.0.8/docs/reports/kernel.txt b/ChibiOS_2.0.8/docs/reports/kernel.txt deleted file mode 100644 index 664d2dd..0000000 --- a/ChibiOS_2.0.8/docs/reports/kernel.txt +++ /dev/null @@ -1,306 +0,0 @@ -Platform : PowerPC -OS Setup : Full kernel -Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 -Options : -O2 -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 11240 - -Platform : PowerPC -OS Setup : Full kernel -Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 -Options : -O2 -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 10800 - -Platform : PowerPC -OS Setup : Minimal kernel -Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 -Options : -O2 -Kernel Size = 2076 - -Platform : PowerPC -OS Setup : Full kernel -Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 -Options : -Os -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 9788 - -Platform : PowerPC -OS Setup : Full kernel -Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 -Options : -Os -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 9304 - -Platform : PowerPC -OS Setup : Minimal kernel -Compiler : powerpc-eabi-gcc (Sourcery G++ Lite 4.4-79) 4.4.1 -Options : -Os -Kernel Size = 2092 - -Platform : ARM Cortex-M3 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 5932 - -Platform : ARM Cortex-M3 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 5440 - -Platform : ARM Cortex-M3 -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -Kernel Size = 1424 - -Platform : ARM Cortex-M3 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 5364 - -Platform : ARM Cortex-M3 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 4956 - -Platform : ARM Cortex-M3 -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -Kernel Size = 1244 - -Platform : ARM Cortex-M3 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 5144 - -Platform : ARM Cortex-M3 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 4764 - -Platform : ARM Cortex-M3 -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -Kernel Size = 1196 - -Platform : ARM Cortex-M0 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 5184 - -Platform : ARM Cortex-M0 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 4992 - -Platform : ARM Cortex-M0 -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -Kernel Size = 1300 - -Platform : ARM Cortex-M0 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 4784 - -Platform : ARM Cortex-M0 -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 4624 - -Platform : ARM Cortex-M0 -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -Kernel Size = 1180 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 8620 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 8168 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -Kernel Size = 1820 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 7980 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 7632 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -Kernel Size = 1568 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 8336 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 7900 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -Kernel Size = 1752 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 7688 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 7360 - -Platform : ARM7TDMI (ARM mode) -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -Kernel Size = 1500 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=TRUE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 5748 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -DCH_OPTIMIZE_SPEED=FALSE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 5544 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 1300 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=TRUE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 5356 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -DCH_OPTIMIZE_SPEED=FALSE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 5176 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 1188 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=TRUE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 5604 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=FALSE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 5412 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -O2 -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 1252 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=TRUE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 5144 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Full kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DCH_OPTIMIZE_SPEED=FALSE -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 4984 - -Platform : ARM7TDMI (THUMB mode) -OS Setup : Minimal kernel -Compiler : arm-none-eabi-gcc (GCC) 4.5.1 -Options : -Os -mthumb -ffixed-r7 -DCH_CURRP_REGISTER_CACHE=\"r7\" -DTHUMB -DTHUMB_PRESENT -DTHUMB_NO_INTERWORKING -Kernel Size = 1136 - -Platform : MSP430 -OS Setup : Full kernel -Compiler : msp430-gcc (GCC) 3.2.3 -Options : -O2 -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 5728 - -Platform : MSP430 -OS Setup : Full kernel -Compiler : msp430-gcc (GCC) 3.2.3 -Options : -O2 -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 5208 - -Platform : MSP430 -OS Setup : Minimal kernel -Compiler : msp430-gcc (GCC) 3.2.3 -Options : -O2 -Kernel Size = 1120 - -Platform : MSP430 -OS Setup : Full kernel -Compiler : msp430-gcc (GCC) 3.2.3 -Options : -Os -DCH_OPTIMIZE_SPEED=TRUE -Kernel Size = 5668 - -Platform : MSP430 -OS Setup : Full kernel -Compiler : msp430-gcc (GCC) 3.2.3 -Options : -Os -DCH_OPTIMIZE_SPEED=FALSE -Kernel Size = 5168 - -Platform : MSP430 -OS Setup : Minimal kernel -Compiler : msp430-gcc (GCC) 3.2.3 -Options : -Os -Kernel Size = 1120 - diff --git a/ChibiOS_2.0.8/docs/rsc/custom.css b/ChibiOS_2.0.8/docs/rsc/custom.css deleted file mode 100644 index 9c847c6..0000000 --- a/ChibiOS_2.0.8/docs/rsc/custom.css +++ /dev/null @@ -1,441 +0,0 @@ -body, table, div, p, dl { - font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; - font-size: 12px; -} - -/* @group Heading Levels */ - -h1 { - text-align: center; - font-size: 150%; -} - -h2 { - font-size: 120%; -} - -h3 { - font-size: 100%; -} - -/* @end */ - -caption { - font-weight: bold; -} - -div.qindex, div.navpath, div.navtab{ - background-color: #e8eef2; - border: 1px solid #84b0c7; - text-align: center; - margin: 2px; - padding: 2px; -} - -div.qindex, div.navpath { - width: 100%; - line-height: 140%; -} - -div.navtab { - margin-right: 15px; -} - -/* @group Link Styling */ - -a { - color: #153788; - font-weight: normal; - text-decoration: none; -} - -.contents a:visited { - color: #1b77c5; -} - -a:hover { - text-decoration: underline; -} - -a.qindex { - font-weight: bold; -} - -a.qindexHL { - font-weight: bold; - background-color: #6666cc; - color: #ffffff; - border: 1px double #9295C2; -} - -a.el { - font-weight: bold; -} - -a.elRef { -} - -a.code { -} - -a.codeRef { -} - -/* @end */ - -dl.el { - margin-left: -1cm; -} - -.fragment { - font-family: monospace, fixed; - font-size: 105%; -} - -pre.fragment { - border: 1px solid #CCCCCC; - background-color: #f5f5f5; - padding: 4px 6px; - margin: 4px 8px 4px 2px; -} - -div.ah { - background-color: black; - font-weight: bold; - color: #ffffff; - margin-bottom: 3px; - margin-top: 3px -} - -div.groupHeader { - margin-left: 16px; - margin-top: 12px; - margin-bottom: 6px; - font-weight: bold; -} - -div.groupText { - margin-left: 16px; - font-style: italic; -} - -body { - background: white; - color: black; - margin-right: 20px; - margin-left: 20px; -} - -td.indexkey { - background-color: #e8eef2; - font-weight: bold; - border: 1px solid #CCCCCC; - margin: 2px 0px 2px 0; - padding: 2px 10px; -} - -td.indexvalue { - background-color: #e8eef2; - border: 1px solid #CCCCCC; - padding: 2px 10px; - margin: 2px 0px; -} - -tr.memlist { - background-color: #f0f0f0; -} - -p.formulaDsp { - text-align: center; -} - -img.formulaDsp { - -} - -img.formulaInl { - vertical-align: middle; -} - -/* @group Code Colorization */ - -span.keyword { - color: #008000 -} - -span.keywordtype { - color: #604020 -} - -span.keywordflow { - color: #e08000 -} - -span.comment { - color: #800000 -} - -span.preprocessor { - color: #806020 -} - -span.stringliteral { - color: #002080 -} - -span.charliteral { - color: #008080 -} - -span.vhdldigit { - color: #ff00ff -} - -span.vhdlchar { - color: #000000 -} - -span.vhdlkeyword { - color: #700070 -} - -span.vhdllogic { - color: #ff0000 -} - -/* @end */ - -.search { - color: #003399; - font-weight: bold; -} - -form.search { - margin-bottom: 0px; - margin-top: 0px; -} - -input.search { - font-size: 75%; - color: #000080; - font-weight: normal; - background-color: #e8eef2; -} - -td.tiny { - font-size: 75%; -} - -.dirtab { - padding: 4px; - border-collapse: collapse; - border: 1px solid #84b0c7; -} - -th.dirtab { - background: #e8eef2; - font-weight: bold; -} - -hr { - height: 0; - border: none; - border-top: 1px solid #666; -} - -/* @group Member Descriptions */ - -.mdescLeft, .mdescRight, -.memItemLeft, .memItemRight, -.memTemplItemLeft, .memTemplItemRight, .memTemplParams { - background-color: #FAFAFA; - border: none; - margin: 4px; - padding: 1px 0 0 8px; -} - -.mdescLeft, .mdescRight { - padding: 0px 8px 4px 8px; - color: #555; -} - -.memItemLeft, .memItemRight, .memTemplParams { - border-top: 1px solid #ccc; -} - -.memTemplParams { - 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ChibiOS/RT LogoChibiOS/RT

Architecture - Reference Manual - Guides
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See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page architecture Architecture - * @brief ChibiOS/RT General Architecture - * - @ref components - * - @ref dependencies - * - @ref kernel_arch - * - @ref hal_arch - * . - * @section components Components - * ChibiOS/RT is composed of several major components, each component can be - * composed of one of more subsystems. The main components are: - * - Kernel, this is the platform independent part of the OS kernel. - * - HAL, this component contains a set of abstract device drivers - * that offer a common I/O API to the application across all the support - * platforms. The HAL code is totally portable across platforms. - * - Port, this is the platform dependent part of the OS kernel. This - * component is responsible of the system startup, interrupts abstraction, - * lock/unlock primitives, context switch related structures and code.
- * The component usually contains very little code because the OS is very - * portable but the quality of the implementation of the Port component - * affects heavily the performance of the ported OS. It is probably the - * most critical part of the whole OS. - * - Platform, this component contains a set of device drivers - * implementations. - * - Various, a library of various extra components that do not belong - * to any particular component but can make life easier while developing an - * embedded application. - * . - * @section dependencies Dependencies - * The following diagram shows the relationships among the various components - * that compose the system:

- * @dot - digraph example { - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1.0", height="0.25"]; - edge [fontname=Helvetica, fontsize=8]; - - Application [label="Application"]; - HAL [label="HAL"]; - Platform [label="Platform"]; - Kernel [label="Kernel"]; - Port [label="Port"]; - HW [label="Hardware", style="filled", width="3.0", height="0.3"]; - - Application -> Kernel; - Application -> HAL; - Application -> HW [label=" (not recommended)"]; - HAL -> Platform; - HAL -> Kernel; - Platform -> Kernel; - Platform -> HW; - Kernel -> Port; - Port -> HW; - } - * @enddot - * - * @section kernel_arch Kernel Architecture - * The kernel itself is very modular and is composed of several subsystems, - * most subsystems are optional and can be switched of in the kernel - * configuration file @p chconf.h.
- * The current kernel subsystems are divided in five categories: - * - @ref base, this category contains the mandatory kernel - * subsystems: - * - @ref system, low level locks, initialization. - * - @ref time, virtual timers and time APIs. - * - @ref scheduler, scheduler APIs, all the higher level synchronization - * mechanism are implemented through this subsystem, it is very flexible - * but not recommended for direct use in user code. - * - @ref threads, thread-related APIs. - * . - * Base services diagram:

- * @dot - digraph example { - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1.0", height="0.25"]; - edge [fontname=Helvetica, fontsize=8]; - - Threads -> Scheduler; - Scheduler-> System; - Scheduler-> Timers; - System-> Timers; - } - * @enddot - * - @ref synchronization, this category contains the synchronization-related - * subsystems, each one of the provided mechanism can be configured out of - * the kernel if not needed. - * - @ref semaphores, counter semaphores subsystem. - * - @ref mutexes, mutexes subsystem with support to the priority inheritance - * algorithm (fully implemented, any depht). - * - @ref condvars, condition variables, together with mutexes the condition - * variables allow the implementation of monitor constructs. - * - @ref events, event sources and event flags with flexible support for - * and/or conditions and automatic dispatching to handler functions. - * - @ref messages, lightweight synchronous messages. - * - @ref mailboxes, asynchronous messages queues. - * . - * All the synchronization mechanisms are built on top of the Scheduler APIs - * except Mailboxes that are build on top of Semaphores and Condition - * Variables that implicitly refer to Mutexes:

- * @dot - digraph example { - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1.0", height="0.25"]; - edge [fontname=Helvetica, fontsize=8]; - - Semaphores -> Scheduler; - Mutexes -> Scheduler; - Condvars -> Scheduler; - Condvars -> Mutexes; - Events -> Scheduler; - Messages -> Scheduler; - Mailboxes -> Semaphores; - } - * @enddot - * - @ref memory, memory management, multiple non-alternative schemes are - * available: - * - @ref memcore, centralized core memory manager, this subsystems is used - * by the other allocators in order to get chunks of memory in a consistent - * way. - * - @ref heaps, central heap manager using a first fit strategy, it also - * allow the creation of multiple heaps in order to handle non uniform - * memory areas. - * - @ref pools, very fast fixed size objects allocator. - * - @ref threads (dynamic), usually threads are static objects in ChibiOS/RT - * but there is the option for dynamic threads management, please see the - * article @ref article_lifecycle. - * . - * The various allocators follow a precise hierarchy:

- * @dot - digraph example { - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1.0", height="0.25"]; - edge [fontname=Helvetica, fontsize=8]; - - Core [label="Core Allocator"]; - Dynamic [label="Dynamic Threads"]; - Heaps [label="Dynamic Heaps"]; - Pools [label="Memory Pools"]; - C [label="C-runtime"]; - - Dynamic -> Heaps; - Dynamic -> Pools; - Heaps -> Core; - Pools -> Core; - C -> Core; - } - * @enddot - * Please also see the article @ref article_manage_memory. - * - @ref io_support, the kernel also provides mechanisms and abstract data - * interfaces that can be used by non-kernel components, the HAL as example. - * - @ref data_streams, abstract streams interface. - * - @ref io_channels, abstract I/O channels that inherits from the abstract - * stream interface. - * - @ref io_queues, generic, byte wide, I/O queues APIs. - * . - * - @ref debug, debug services and APIs. The @ref registry susystem can be - * seen as part of the debug category even if it finds use in non-debug - * roles. - * . - * @section hal_arch HAL Architecture - * The HAL is a collection of abstract device drivers, it relies on the - * Platform component for the low level implementation on specific - * hardware.
- * The current internal HAL organization is the following:

- * @dot - digraph example { - rankdir="LR"; - - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1.0", height="0.25"]; - edge [fontname=Helvetica, fontsize=8]; - - subgraph cluster_HAL { - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="0.6", height="0.25"]; - ADC [label="ADC"]; - CAN [label="CAN"]; - HAL [label="HAL"]; - MAC [label="MAC"]; - PAL [label="PAL"]; - PWM [label="PWM"]; - SER [label="SER"]; - SPI [label="SPI"]; - MMC_SD [label="MMC/SD"]; - color = blue; - label = "HAL"; - } - - subgraph cluster_Platform { - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="0.6", height="0.25"]; - ADC_LLD [label="ADC_LLD"]; - CAN_LLD [label="CAN_LLD"]; - HAL_LLD [label="HAL_LLD"]; - MAC_LLD [label="MAC_LLD"]; - PAL_LLD [label="PAL_LLD"]; - PWM_LLD [label="PWM_LLD"]; - SER_LLD [label="SER_LLD"]; - SPI_LLD [label="SPI_LLD"]; - color = blue; - label = "Platform"; - } - - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1", height="0.5"]; - edge [fontname=Helvetica, fontsize=8]; - - Application [label="Application"]; - HW [label="Hardware", style="filled"]; - - ADC -> ADC_LLD; - CAN -> CAN_LLD; - HAL -> HAL_LLD; - MAC -> MAC_LLD; - PAL -> PAL_LLD; - PWM -> PWM_LLD; - SER -> SER_LLD; - SPI -> SPI_LLD; - MMC_SD -> SPI [constraint=false]; - - Application -> ADC; - Application -> CAN; - Application -> HAL; - Application -> MAC; - Application -> PAL; - Application -> PWM; - Application -> SER; - Application -> SPI; - Application -> MMC_SD; - ADC_LLD -> HW; - CAN_LLD -> HW; - HAL_LLD -> HW; - MAC_LLD -> HW; - PAL_LLD -> HW; - PWM_LLD -> HW; - SER_LLD -> HW; - SPI_LLD -> HW; - } - * @enddot - *
- * See @ref IO for details about the various HAL subsystems. - */ diff --git a/ChibiOS_2.0.8/docs/src/articles.dox b/ChibiOS_2.0.8/docs/src/articles.dox deleted file mode 100644 index 88990b4..0000000 --- a/ChibiOS_2.0.8/docs/src/articles.dox +++ /dev/null @@ -1,73 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page articles Articles and Code Samples - * ChibiOS/RT Articles and Code Samples: - * - @subpage page_general - * - @subpage page_kb - * - @subpage page_howtos - * . - */ - -/** - * @page page_general General - * Articles and guides not necessarily related to ChibiOS/RT. - * - @subpage article_eclipse - * - @subpage article_eclipse2 - * - @subpage article_jitter - * . - */ - -/** - * @page page_kb Knowledge Base - * Articles and guides about ChibiOS/RT. - * - @subpage article_integrationguide - * - @subpage article_portguide - * - @subpage article_events - * - @subpage article_debug - * - @subpage article_stacks - * - @subpage article_roundrobin - * - @subpage article_lifecycle - * - @subpage article_mutual_exclusion - * - @subpage article_atomic - * - @subpage article_saveram - * - @subpage article_timing - * - @subpage article_design - * . - */ - -/** - * @page page_howtos How To's - * Articles describing how to implement specific tasks using ChibiOS/RT. - * - @subpage article_create_thread - * - @subpage article_interrupts - * - @subpage article_wakeup - * - @subpage article_manage_memory - * - @subpage article_stop_os - * . - */ - diff --git a/ChibiOS_2.0.8/docs/src/atomic.dox b/ChibiOS_2.0.8/docs/src/atomic.dox deleted file mode 100644 index 6919b3e..0000000 --- a/ChibiOS_2.0.8/docs/src/atomic.dox +++ /dev/null @@ -1,64 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_atomic Invoking multiple primitives as a single atomic operation - * It is often necessary to invoke multiple operations involving a - * reschedule as a single atomic operation.
- * ChibiOS/RT already implements APIs that perform complex operations, as - * example the API @p chSemSignalWait() performs two operations atomically.
- * If more complex operations are required in your application then it is - * possible to build macro-operations, see the following example: - * @code - chSysLock(); - - chSemSignalI(&sem1); - chSemSignalI(&sem2); - chMtxUnlockS(); - chSchRescheduleS(); - - chSysUnlock(); - * @endcode - * The above example performs a signal operation on two semaphores, unlocks the - * last acquired mutex and finally performs a reschedule. All the operations - * are performed atomically.
- * An hypothetical @p chSemSignalSignalWait() operation could be implemented as - * follow: - * @code - chSysLock(); - - chSemSignalI(&sem1); - chSemSignalI(&sem2); - chSemWaitS(&Sem3); /* May reschedule or not. */ - chSchRescheduleS(); /* This one reschedules if necessary. */ - - chSysUnlock(); - * @endcode - * In general multiple @ref I-Class and (non rescheduling) @ref S-Class APIs - * can be included and the block is terminated by a rescheduling @ref S-Class - * API. An extra @p chSchRescheduleS() can be present at the very end of the - * block, it only reschedules if a reschedule is still required. - */ diff --git a/ChibiOS_2.0.8/docs/src/concepts.dox b/ChibiOS_2.0.8/docs/src/concepts.dox deleted file mode 100644 index 71bafbf..0000000 --- a/ChibiOS_2.0.8/docs/src/concepts.dox +++ /dev/null @@ -1,290 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page concepts Kernel Concepts - * @brief ChibiOS/RT Kernel Concepts - * - @ref naming - * - @ref api_suffixes - * - @ref interrupt_classes - * - @ref system_states - * - @ref scheduling - * - @ref thread_states - * - @ref priority - * - @ref warea - * . - * @section naming Naming Conventions - * ChibiOS/RT APIs are all named following this convention: - * @a ch\\\(). - * The possible groups are: @a Sys, @a Sch, @a Time, @a VT, @a Thd, @a Sem, - * @a Mtx, @a Cond, @a Evt, @a Msg, @a SequentialStream, @a IO, @a IQ, @a OQ, - * @a Dbg, @a Core, @a Heap, @a Pool. - * - * @section api_suffixes API Names Suffixes - * The suffix can be one of the following: - * - None, APIs without any suffix can be invoked only from the user - * code in the Normal state unless differently specified. See - * @ref system_states. - * - @anchor I-Class "I", I-Class APIs are invokable only from the - * I-Locked or S-Locked states. See @ref system_states. - * - @anchor S-Class "S", S-Class APIs are invokable only from the - * S-Locked state. See @ref system_states. - * . - * Examples: @p chThdCreateStatic(), @p chSemSignalI(), @p chIQGetTimeout(). - * - * @section interrupt_classes Interrupt Classes - * In ChibiOS/RT there are three logical interrupt classes: - * - Regular Interrupts. Maskable interrupt sources that cannot - * preempt (small parts of) the kernel code and are thus able to invoke - * operating system APIs from within their handlers. The interrupt handlers - * belonging to this class must be written following some rules. See the - * @ref system APIs group and @ref article_interrupts. - * - Fast Interrupts. Maskable interrupt sources with the ability - * to preempt the kernel code and thus have a lower latency and are less - * subject to jitter, see @ref article_jitter. Such sources are not - * supported on all the architectures.
- * Fast interrupts are not allowed to invoke any operating system API from - * within their handlers. Fast interrupt sources may, however, pend a lower - * priority regular interrupt where access to the operating system is - * possible. - * - Non Maskable Interrupts. Non maskable interrupt sources are - * totally out of the operating system control and have the lowest latency. - * Such sources are not supported on all the architectures. - * . - * The mapping of the above logical classes into physical interrupts priorities - * is, of course, port dependent. See the documentation of the various ports - * for details. - * - * @section system_states System States - * When using ChibiOS/RT the system can be in one of the following logical - * operating states: - * - Init. When the system is in this state all the maskable - * interrupt sources are disabled. In this state it is not possible to use - * any system API except @p chSysInit(). This state is entered after a - * physical reset. - * - Normal. All the interrupt sources are enabled and the system APIs - * are accessible, threads are running. - * - Suspended. In this state the fast interrupt sources are enabled but - * the regular interrupt sources are not. In this state it is not possible - * to use any system API except @p chSysDisable() or @p chSysEnable() in - * order to change state. - * - Disabled. When the system is in this state both the maskable - * regular and fast interrupt sources are disabled. In this state it is not - * possible to use any system API except @p chSysSuspend() or - * @p chSysEnable() in order to change state. - * - Sleep. Architecture-dependent low power mode, the idle thread - * goes in this state and waits for interrupts, after servicing the interrupt - * the Normal state is restored and the scheduler has a chance to reschedule. - * - S-Locked. Kernel locked and regular interrupt sources disabled. - * Fast interrupt sources are enabled. @ref S-Class and @ref I-Class APIs are - * invokable in this state. - * - I-Locked. Kernel locked and regular interrupt sources disabled. - * @ref I-Class APIs are invokable from this state. - * - Serving Regular Interrupt. No system APIs are accessible but it is - * possible to switch to the I-Locked state using @p chSysLockFromIsr() and - * then invoke any @ref I-Class API. Interrupt handlers can be preemptable on - * some architectures thus is important to switch to I-Locked state before - * invoking system APIs. - * - Serving Fast Interrupt. System APIs are not accessible. - * - Serving Non-Maskable Interrupt. System APIs are not accessible. - * - Halted. All interrupt sources are disabled and system stopped into - * an infinite loop. This state can be reached if the debug mode is activated - * and an error is detected or after explicitly invoking - * @p chSysHalt(). - * . - * Note that the above states are just Logical States that may have no - * real associated machine state on some architectures. The following diagram - * shows the possible transitions between the states: - * - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; - edge [fontname=Helvetica, fontsize=8]; - init [label="Init", style="bold"]; - norm [label="Normal", shape=doublecircle]; - susp [label="Suspended"]; - disab [label="Disabled"]; - slock [label="S-Locked"]; - ilock [label="I-Locked"]; - slock [label="S-Locked"]; - sleep [label="Sleep"]; - sri [label="SRI"]; - init -> norm [label="chSysInit()"]; - norm -> slock [label="chSysLock()", constraint=false]; - slock -> norm [label="chSysUnlock()"]; - norm -> susp [label="chSysSuspend()"]; - susp -> disab [label="chSysDisable()"]; - norm -> disab [label="chSysDisable()"]; - susp -> norm [label="chSysEnable()"]; - disab -> norm [label="chSysEnable()"]; - slock -> ilock [label="Context Switch", dir="both"]; - norm -> sri [label="Regular IRQ", style="dotted"]; - sri -> norm [label="Regular IRQ return", fontname=Helvetica, fontsize=8]; - sri -> ilock [label="chSysLockFromIsr()", constraint=false]; - ilock -> sri [label="chSysUnlockFromIsr()", fontsize=8]; - norm -> sleep [label="Idle Thread"]; - sleep -> sri [label="Regular IRQ", style="dotted"]; - } - * @enddot - * Note, the SFI, Halted and SNMI states were not shown - * because those are reachable from most states: - * - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; - edge [fontname=Helvetica, fontsize=8]; - any1 [label="Any State\nexcept *"]; - any2 [label="Any State"]; - sfi [label="SFI"]; - halt [label="Halted"]; - SNMI [label="SNMI"]; - any1 -> sfi [style="dotted", label="Fast IRQ"]; - sfi -> any1 [label="Fast IRQ return"]; - any2 -> halt [label="chSysHalt()"]; - any2 -> SNMI [label="Synchronous NMI"]; - any2 -> SNMI [label="Asynchronous NMI", style="dotted"]; - SNMI -> any2 [label="NMI return"]; - halt -> SNMI [label="Asynchronous NMI", style="dotted"]; - SNMI -> halt [label="NMI return"]; - } - * @enddot - * @attention * except: Init, Halt, SNMI, Disabled. - * - * @section scheduling Scheduling - * The strategy is very simple the currently ready thread with the highest - * priority is executed. If more than one thread with equal priority are - * eligible for execution then they are executed in a round-robin way, the - * CPU time slice constant is configurable. The ready list is a double linked - * list of threads ordered by priority.

- * @dot - digraph example { - rankdir="LR"; - - node [shape=square, fontname=Helvetica, fontsize=8, - fixedsize="true", width="0.6", height="0.5"]; - edge [fontname=Helvetica, fontsize=8]; - - subgraph cluster_running { - node [shape=square, fontname=Helvetica, fontsize=8, - fixedsize="true", width="0.6", height="0.5"]; - currp [label="'currp'\npointer", style="bold"]; - T4 [label="Tuser(4)\nprio=100"]; - label = "Currently Running Thread"; - penwidth = 0; - } - - subgraph cluster_rlist { - node [shape=square, fontname=Helvetica, fontsize=8, - fixedsize="true", width="0.6", height="0.5"]; - rh [label="ready list\nheader\nprio=0", style="bold"]; - Ti [label="Tidle\nprio=1"]; - Tm [label="Tmain\nprio=64"]; - T1 [label="Tuser(1)\nprio=32"]; - T2 [label="Tuser(2)\nprio=32"]; - T3 [label="Tuser(3)\nprio=80"]; - label = "Threads Ready for Execution"; - penwidth = 0; - } - - currp -> T4 - rh -> Ti -> T1 -> T2 -> Tm -> T3 -> rh [label="p_next"]; - rh -> T3 -> Tm -> T2 -> T1 -> Ti -> rh [label="p_prev"]; - } - * @enddot - *
- * Note that the currently running thread is not in the ready list, the list - * only contains the threads ready to be executed but still actually waiting. - * - * @section thread_states Threads States - * The image shows how threads can change their state in ChibiOS/RT.
- * @dot - digraph example { - /*rankdir="LR";*/ - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; - edge [fontname=Helvetica, fontsize=8]; - start [label="Start", style="bold"]; - run [label="Running"]; - ready [label="Ready"]; - suspend [label="Suspended"]; - sleep [label="Sleeping"]; - stop [label="Stop", style="bold"]; - start -> suspend [label="chThdInit()", constraint=false]; - start -> run [label="chThdCreate()"]; - start -> ready [label="chThdCreate()"]; - run -> ready [label="Reschedule", dir="both"]; - suspend -> run [label="chThdResume()"]; - suspend -> ready [label="chThdResume()"]; - run -> sleep [label="chSchGoSleepS()"]; - sleep -> run [label="chSchWakepS()"]; - sleep -> ready [label="chSchWakepS()"]; - run -> stop [label="chThdExit()"]; - } - * @enddot - * - * @section priority Priority Levels - * Priorities in ChibiOS/RT are a contiguous numerical range but the initial - * and final values are not enforced.
- * The following table describes the various priority boundaries (from lowest - * to highest): - * - @p IDLEPRIO, this is the lowest priority level and is reserved for the - * idle thread, no other threads should share this priority level. This is - * the lowest numerical value of the priorities space. - * - @p LOWPRIO, the lowest priority level that can be assigned to an user - * thread. - * - @p NORMALPRIO, this is the central priority level for user threads. It is - * advisable to assign priorities to threads as values relative to - * @p NORMALPRIO, as example NORMALPRIO-1 or NORMALPRIO+4, this ensures the - * portability of code should the numerical range change in future - * implementations. - * - @p HIGHPRIO, the highest priority level that can be assigned to an user - * thread. - * - @p ABSPRO, absolute maximum software priority level, it can be higher than - * @p HIGHPRIO but the numerical values above @p HIGHPRIO up to @p ABSPRIO - * (inclusive) are reserved. This is the highest numerical value of the - * priorities space. - * . - * @section warea Threads Working Area - * Each thread has its own stack, a Thread structure and some preemption - * areas. All the structures are allocated into a "Thread Working Area", - * a thread private heap, usually statically declared in your code. - * Threads do not use any memory outside the allocated working area - * except when accessing static shared data.

- * @image html workspace.png - *
- * Note that the preemption area is only present when the thread is not - * running (switched out), the context switching is done by pushing the - * registers on the stack of the switched-out thread and popping the registers - * of the switched-in thread from its stack. - * The preemption area can be divided in up to three structures: - * - External Context. - * - Interrupt Stack. - * - Internal Context. - * . - * See the @ref core documentation for details, the area may change on - * the various ports and some structures may not be present (or be zero-sized). - */ diff --git a/ChibiOS_2.0.8/docs/src/createthread.dox b/ChibiOS_2.0.8/docs/src/createthread.dox deleted file mode 100644 index ae1a19a..0000000 --- a/ChibiOS_2.0.8/docs/src/createthread.dox +++ /dev/null @@ -1,194 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_create_thread How to create a thread - * At the system startup there are already two active threads: - * - Idle thread. This thread has the lowest priority in the system so - * it runs only when the other threads in the system are sleeping. This - * threads usually switches the system in a low power mode and does nothing - * else. - * - Main thread. This thread executes your @p main() function at - * startup. The main thread is created at the @p NORMALPRIO level but it - * can change its own priority if required. It is from the main thread - * that the other threads are usually created. - * . - * There are two kind of threads in ChibiOS/RT: - * - Static Threads. This kind of threads are statically allocated in - * memory. The memory used by the thread cannot reused except for restarting - * the threads. - * - Dynamic Threads. Threads created by allocating memory from a memory - * heap or a memory pool. - * . - *

Creating a static thread

- * In order to create a static thread a working area must be declared using - * the macro @p WORKING_AREA as shown: - * @code -static WORKING_AREA(myThreadWorkingArea, 128); - * @endcode - * This macro reserves 128 bytes of stack for the thread and space for all - * the required thread related structures. The total size and the alignment - * problems are handled inside the macro, you only need to specify the pure - * stack size.
- * A thread can be started by invoking @p chThdCreateStatic() as shown in this - * example: - * @code - Thread *tp = chThdCreateStatic(myThreadWorkingArea, - sizeof(myThreadWorkingArea), - NORMALPRIO, /* Initial priority. */ - myThread, /* Thread function. */ - NULL); /* Thread parameter. */ - * @endcode - * The variable tp receives the pointer to the thread object, it is taken - * by other APIs as parameter.
- * Now a complete example: - * @code -/* -* * My simple application. - */ - -#include - -/* -* * Working area for the LED flashing thread. - */ -static WORKING_AREA(myThreadWorkingArea, 128); - -/* -* * LED flashing thread. - */ -static msg_t myThread(void *arg) { - - while (TRUE) { - LED_ON(); - chThdSleepMilliseconds(500); - LED_OFF(); - chThdSleepMilliseconds(500); - } -} - -int main(int argc, char *argv[]) { - - /* Starting the flashing LEDs thread.*/ - (void)chThdCreateStatic(myThreadWorkingArea, sizeof(myThreadWorkingArea), - NORMALPRIO, myThread, NULL); - . - . - . -} - * @endcode - * Note that the memory allocated to myThread() is statically defined and - * cannot be reused. Static threads are ideal for safety applications because - * there is no risk of a memory allocation failure because progressive heap - * fragmentation. - * - *

Creating a dynamic thread using the heap allocator

- * In order to create a thread from a memory heap is very easy: - * @code - Thread *tp = chThdCreateFromHeap(NULL, /* NULL = Default heap. */ - THD_WA_SIZE(128),/* Stack size. */ - NORMALPRIO, /* Initial priority. */ - myThread, /* Thread function. */ - NULL); /* Thread parameter. */ - * @endcode - * The memory is allocated from the spawned heap and the thread is started. - * Note that the memory is not freed when the thread terminates but when the - * thread final status (its return value) is collected by the spawning thread. - * As example: - * @code -static msg_t myThread(void *arg) { - - unsigned i = 10; - while (i > 0) { - LED_ON(); - chThdSleepMilliseconds(500); - LED_OFF(); - chThdSleepMilliseconds(500); - i--; - } - return (msg_t)i; -} - -int main(int argc, char *argv[]) { - - Thread *tp = chThdCreateFromHeap(NULL, THD_WA_SIZE(128), NORMALPRIO+1, - myThread, NULL); - if (tp == NULL) - chSysHalt(); /* Memory exausted. */ - - /* The main thread continues its normal execution.*/ - . - . - /* -* * Now waits for the spawned thread to terminate (if it has not terminated -* * already) then gets the thread exit message (msg) and returns the -* * terminated thread memory to the heap (default system heap in this -* * example). - */ - msg_t msg = chThdWait(tp); - . - . -} - * @endcode - * - *

Creating a dynamic thread using the heap allocator

- * A pool is a collection of equally sized memory blocks, creating a thread from - * a memry pool is very similar to the previous example but the memory of - * terminated threads is returned to the memory pool rather than to a heap: - * @code -static msg_t myThread(void *arg) { - - unsigned i = 10; - while (i > 0) { - LED_ON(); - chThdSleepMilliseconds(500); - LED_OFF(); - chThdSleepMilliseconds(500); - i--; - } - return (msg_t)i; -} - -int main(int argc, char *argv[]) { - - Thread *tp = chThdCreateFromMemoryPool(myPool, NORMALPRIO+1, myThread, NULL); - if (tp == NULL) - chSysHalt(); /* Pool empty. */ - - /* The main thread continues its normal execution.*/ - . - . - /* -* * Now waits for the spawned thread to terminate (if it has not terminated -* * already) then gets the thread exit message (msg) and returns the -* * terminated thread memory to the original memory pool. - */ - msg_t msg = chThdWait(tp); - . - . -} - * @endcode - */ diff --git a/ChibiOS_2.0.8/docs/src/credits.dox b/ChibiOS_2.0.8/docs/src/credits.dox deleted file mode 100644 index 0ba4d8b..0000000 --- a/ChibiOS_2.0.8/docs/src/credits.dox +++ /dev/null @@ -1,104 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page credits Copyright and Credits - * @brief Copyright and Credits - * - *

Copyright Statement

-@verbatim - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. -@endverbatim - * - *

Contributions and Copyright Assignment

- * If you plan to contribute code to the ChibiOS/RT project then there is a - * requirement you should be aware of: contributing code for inclusion in - * the ChibiOS/RT main line requires assigning the copyright on the - * contributed code to me (Giovanni Di Sirio).
- * This may sound a bit strange but is pretty standard for this kind of - * projects, there are several reasons for this requirement: - * - ChibiOS/RT will probably also become a commercial product and it would - * not be possible to re-license the code without ownership. Note that the - * commercial product would not be a different or better product, just the - * same GPL product made available, on request, under a different license. - * The code will always be available to you under the current licensing - * terms. - * - Ownership is required when changing the licensing terms and this happens - * each time the project goes from development/unstable to stable and - * back because the addition/removal of the GPL linking exception. - * - It will be easier for the project adopters to have a single ownership - * point in case of licensing issues (both GPL or commercial). - * - Losing the ownership on the code could preclude me the opportunity to - * make this project a full time job as I hope. - * - I definitely don't want to have to sort out copyright related issues - * in the future so better be clear than sorry. - * . - * Note that contributions will always be welcome even without such copyright - * assignment, the difference is that the contributed code would not be - * merged into the main line, it will still made available as contributed - * code with the contributor(s) copyright notice intact.
- * Submissions of code with copyright notice should only happen through - * email, please do not commit code with copyright notices directly on - * the repository.
- * When submitting code please state clearly your intention to keep the - * copyright on your work by adding your own copyright notice within the - * source code and by clearly mentioning your intentions in the message. Code - * contributed without copyright notice will be considered donated.
- * If in doubt with licensing issues please don't hesitate to contact me - * in order to sort out any problem you may have.
- * Of course the copyright assignment does not mean you would not be - * recognized for your hard work, see the following section. - * - *

Credits

- * I want to thank all the people that directly or indirectly contributed - * to the project, I beg pardon if someone is missing: - * - Adamo Reggiani, working on the Fujitsu port. - * - Alexander Kozaruk, AT91SAM7S256 demo and description files for - * the Olimex SAM7-P256 board. - * - Brian Weaver, STM8 port, STM8 and STM32 testing and improvements. - * - Egon Carusi, STM32 port improvements, testing and bug fixes. - * - Enrico Cavazza, working on the Fujitsu port and a GUI subsystem. - * - Eric Weddington, because his work on WinAVR and helping me sorting - * out issues with the ChibiOS/RT license. - * - Isidoro Orabona, co-developer of the ChibiOS/RT grandfather back - * in 1988, it is a long long story involving a 6502 and a Z80... - * - Jacek, Ride7 demo for STM32 Primer. - * - Leon Woestenberg, CondVars idea and implementation, documentation - * improvements and a lot of other ideas, he also helped with the lwIP port - * (he is one of the developers of that project too). - * - Leszek Bednarz, H8S and ColdFire ports and drivers maintainer. - * - Liam Staskawicz, Posix simulator, AT91SAM7x and STM32 related - * contributions, general improvements, many bug fixes and excellent - * suggestions. - * - Michael Fischer, because the work on YAGARTO and the excellent - * feedback. - * - Riccardo Scanu, another long story, this time involving reverse - * engineering and giant robots... - * - Vladimir, first tested and fixed the AVR port, I don't know the - * surname but he has been the first contributor. - * - Walter Goossens, several fixes to the LPC21xx support. - * . - */ diff --git a/ChibiOS_2.0.8/docs/src/debug.dox b/ChibiOS_2.0.8/docs/src/debug.dox deleted file mode 100644 index d80defa..0000000 --- a/ChibiOS_2.0.8/docs/src/debug.dox +++ /dev/null @@ -1,145 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_debug Debugging ChibiOS/RT applications - * ChibiOS/RT offers several mechanisms that can help in the debug phase of - * the development cycle. - * - *

What this guide does not cover

- * This guide assumes knowledge in following areas: - * - General knowledge of embedded development. - * - RTOS concepts. - * - Setup of your specific target hardware and toolchain. - * - Knowledge of your toolchain. The guide will explain what you need to do, - * not how it is done using you specific debugger, compiler, JTAG probe and - * target hardware. - * . - *

Helpful debugging configuration settings

- * There are several settings in your kernel configuration file - * (see @ref templates/chconf.h) that you may want to enable during - * debugging and in general during the whole development process. - * - @p CH_OPTIMIZE_SPEED=FALSE, this disables inlining into the kernel code - * and makes it easier to debug using your debugger, you may also want - * to reduce or disable compiler optimizations (-O0 using GCC). - * - @p CH_DBG_ENABLE_CHECKS=TRUE, this setting enables the checks on the - * API parameters, useful to understand if you are passing wrong parameters - * to the OS functions. - * - @p CH_DBG_ENABLE_ASSERTS=TRUE, this setting enables the OS internal - * consistency checks, this can trap several kind of errors in the user - * code (or in the kernel itself). - * - @p CH_DBG_ENABLE_STACK_CHECK=TRUE, this setting enables checks on - * threads stack overflow. Note that this option is not available in - * all ports, check your port documentation. If not supported then it - * is silently ignored, see also the article @ref article_stacks. - * - @p CH_DBG_FILL_THREADS=TRUE, this setting enables the threads workspace - * filling, this can help examining the stack usage from your debugger. - * . - * Note that all the failed checks lock the kernel into the @p port_halt() - * function. In order to assess what triggered the lock the global variable - * @p panic_msg must be inspected using the debugger, the variable is a - * pointer to an error message (a zero terminated string), the pointer may - * contain @p NULL if the lock was triggered by a stack overflow. - * - *

Common errors and symptoms

- * There are some common errors while using an RTOS, use the following - * table as a check list, if your problem is not a generic programming error - * then probably it is one of the following common RTOS/embedded related - * mistakes: - * - Insufficient stack allocated to one or more threads.
- * Common symptoms: - * - Target instability. - * - Target locked into the @p port_halt() function. - * - Target trapped into an exception handler (architecture dependent). - * - Target apparent self reset (not real resets usually). - * . - * - Insufficient stack allocated to the IRQ stack (in those architectures - * that have a separate IRQ stack, ARM as example).
- * Common symptoms: - * - Target instability. - * - Target trapped into an exception handler (architecture dependent). - * - Target apparent self reset (not real resets usually). - * . - * - Use of a non reentrant function from within an interrupt handler, as - * example most C runtime functions.
- * Common symptoms: - * - Target instability. - * - Unexpected application behavior. - * . - * - Missing use of a mutual exclusion mechanism to protect data - * (or non reentrant code) shared among multiple threads and/or - * threads and interrupt handlers, see also the article - * @ref article_mutual_exclusion.
- * Common symptoms: - * - Target instability. - * - Unexpected application behavior. - * . - * - Use of S-class or I-class APIs outside a proper lock state, see the - * @ref concepts article, specifically the @ref api_suffixes and - * @ref system_states sections.
- * Common symptoms: - * - Target instability. - * - Target trapped into an exception handler (architecture dependent). - * - Target apparent self reset (not real resets usually). - * . - * - Use of a non I-class API from an interrupt handler, see the - * @ref concepts article, specifically the @ref api_suffixes and - * @ref system_states sections.
- * Common symptoms: - * - Target instability. - * - Target trapped into an exception handler (architecture dependent). - * - Target apparent self reset (not real resets usually). - * . - * - Wrong threads priority assignment. One of the most critical things - * to do when designing an RTOS based application is to assign correct - * priorities to the threads in the system.
- * Common symptoms: - * - Excessive or unpredictable response times. - * - Threads that appear to be never executed (CPU intensive threads at - * higher priority). - * . - * . - *

General suggestions

- * For the less expert users, there are several things you may do in order - * to minimize the need for debugging: - * - Read carefully the documentation first. - * - Try to find a code examples for things are you going to do, good sources - * are: the documentation, the test code, under "./test" you will - * find examples for almost any API in the ChibiOS/RT kernel and most - * common RTOS related tasks, under "./testhal" there are examples - * regarding the various device drivers, the various demos contain - * good code samples too). - * - Start your application from an existing demo, add things one at a - * time and test often, if you add too many things at once then finding a - * small problem can become a debugging nightmare. Follow the cycle: think, - * implement, test, repeat. - * - If you are stuck for too much time then consider asking for advice. - * - Report bugs and problems, bugs can be fixed, problems can become new - * articles in the documentation (this and other documentation articles - * spawned from questions in the forum or in the tracker). - * - Never give up :-) - * . - */ diff --git a/ChibiOS_2.0.8/docs/src/design.dox b/ChibiOS_2.0.8/docs/src/design.dox deleted file mode 100644 index c395411..0000000 --- a/ChibiOS_2.0.8/docs/src/design.dox +++ /dev/null @@ -1,117 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_design Designing an embedded application - * ChibiOS/RT offers a variety of mechanisms and primitives, often it is - * better to focus on a single approach for the system design and use only - * part of the available subsystems.
- * When designing your application you may choose among several design - * alternatives: - * - @ref nothreads - * - @ref messpass - * - @ref thdshared - * - @ref thdmixed - * . - * @section nothreads Single threaded superloop - * Correct, single thread, it is not mandatory to use the multithreading - * features of the OS. You may choose to implements everything as a complex - * state machine handled in the main thread alone. In this scenario the OS - * still offers a variety of useful mechanisms: - * - Interrupt handling. - * - Virtual Timers, very useful in state machines in order to handle time - * triggered state transitions. - * - Power management. - * - Event Flags and/or Semaphores as communication mechanism between - * interrupt handlers and the main. - * - I/O queues. - * - Memory allocation. - * - System time. - * . - * In this configuration the kernel size is really minimal, everything else - * is disabled and takes no space. You always have the option to use more - * threads at a later time in order to perform separate tasks. - * - * @section messpass Message Passing - * In this scenario there are multiple threads in the system that never - * share data, everything is done by exchanging messages. Each thread - * represents a service, the other threads can request the service by sending - * a message.
- * In this scenario the following subsystems can be used: - * - Synchronous Messages. - * - Mailboxes (asynchronous message queues). - * . - * The advantage of this approach is to not have to deal with mutual exclusion, - * each functionality is encapsulated into a server thread that sequentially - * serves all the requests. As example, you can have the following scenario: - * - A buffers allocator server. - * - A disk driver server. - * - A file system server. - * - One or more client threads. - * . - * Example: - *

- * @dot - digraph example { - rankdir="RL"; - node [shape=rectangle, fontname=Helvetica, fontsize=8, fixedsize="true", - width="1.2", height="0.75"]; - edge [fontname=Helvetica, fontsize=8]; - disk [label="Server Thread\nDisk Driver"]; - buf [label="Server Thread\nBuffers Allocator"]; - fs [label="Client&Server Thread\nFile System"]; - cl1 [label="Client Thread"]; - cl2 [label="Client Thread"]; - cl3 [label="Client Thread"]; - fs -> disk [label="I/O request", constraint=false]; - disk -> fs [label="status", style="dotted", constraint=false]; - fs -> buf [label="buffer request"]; - buf -> fs [label="buffer", style="dotted"]; - cl1 -> fs [label="FS transaction"]; - fs -> cl1 [label="result", style="dotted"]; - cl2 -> fs [label="FS transaction"]; - fs -> cl2 [label="result", style="dotted"]; - cl3 -> fs [label="FS transaction"]; - fs -> cl3 [label="result", style="dotted"]; - } - * @enddot - *

- * Note that the threads should not exchange complex messages but just - * pointers to data structures in order to optimize the performance. - * Also note that a thread can be both client and server at the same - * time, the FS service in the previous scenario as example. - * - * @section thdshared Threads sharing data - * This is the most common scenario, several threads have access to both their - * private data and shared data. Synchronization happens with one of the - * mechanisms described in the @ref article_mutual_exclusion article.
- * - * @section thdmixed Mixed - * All the above approaches can be freely mixed in a single application but - * usually I prefer to choose a way and consistently design the system around - * it. The OS is a toolbox that offers a lot of tools but you don't have - * to use them all necessarily. - */ diff --git a/ChibiOS_2.0.8/docs/src/eclipse.dox b/ChibiOS_2.0.8/docs/src/eclipse.dox deleted file mode 100644 index fd43cc1..0000000 --- a/ChibiOS_2.0.8/docs/src/eclipse.dox +++ /dev/null @@ -1,176 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_eclipse Setting up a free embedded IDE - * @brief Free advanced embedded IDE for ChibiOS/RT. - * details This article will explain how to setup a free toolchain for use with - * ChibiOS/RT and general embedded development.
- * The guide is meant mainly for Windows users but notes about Linux and - * MAC OSX are present where the setup differs, mostly the toolchain is - * exactly the same. - * - *

What this guide does not cover

- * We will not enter in details of common system tasks like and not limited to: - * - Installing applications (unless a special procedure is required). - * - Creating desktop shortcuts. - * - Adding paths to the PATH variable. - * - Creating environment variables. - * - Any other normal PC usage task. - * - Use of the toolchain, the use is covered by the @ref article_eclipse2 - * article. - * . - * - *

Article Index

- * - @ref required_components - * - @ref install_chibios - * - @ref install_compiler - * - @ref install_eclipse - * - @ref install_zylin - * - @ref install_openocd - * - @ref install_doxygen - * - @ref install_graphviz - * - @ref install_eclox - * . - * - * @section required_components Required Components - * The first thing to do is to download all the required components, beginners - * should avoid the optional components initially: - * - A JTAG probe supporting GDB and OpenOCD, a list of compatible devices is - * available on the - * OpenOCD home page, more exactly - * here. - * - - * ChibiOS/RT latest stable release. - * - Java runtime, you - * probably already have this installed. - * - Eclipse IDE - * for C/C++ Developers - * - YAGARTO ARM toolchain - * for Windows, note that you need both the compiler and the tools (make - * and binutils). - * - Zylin plugin for on-board debugging, see @ref install_zylin section. - * - OpenOCD binaries for Windows, YAGARTO does not provide those anymore but - * you can download them from here. Linux users can try - * here. - * - Optional, MinGW compiler, needed if you want to compile, debug - * and run the simulator from within Eclipse. Linux users do not need this - * one because all Linux distributions include the native GCC. - * - Optional, Doxygen, it is only required if you want to - * generate documentation from source files. - * - Optional, - * Graphwiz, it is only required if you want to generate diagrams - * within documentation from source files. - * - Optional, - * Eclox, it is only required if you want to generate documentation - * from source files from within Eclipse. - * . - * - * @section install_chibios ChibiOS/RT Installation - * Just unzip it into a directory in your home folder, Windows users may - * consider c:@\projects@\chibios. It is strongly suggested to not put version - * numbers into the ChibiOS/RT directory name because Eclipse workspaces - * have absolute paths inside and you don't want to setup everything again - * each time a new ChibiOS/RT version is released, use plain "chibios". - * - * @section install_compiler GCC ARM Compiler Installation - * Simply follow the YAGARTO installation guide. Linux/MACOS users have several - * other options: - * - Download the latest CodeSourcery free Linux package. - * - Build it yourself, Liam recommended a build script - * - * here, it looks interesting. - * . - * Make sure that the compiler binaries directory is listed in the PATH - * variable or Eclipse would not be able to locate it. - * - * @section install_eclipse Eclipse Installation - * Eclipse is distributed into a compressed archive, there is no installation - * procedure: - * - Verify if you have Java installed, if not install the runtime. You may - * verify this using the command: "java -version". Make sure you have at - * least version 1.6. - * - Create an eclipse directory in your home and unpack the archive there. - * Windows users may unpack it into c:@\program files@\eclipse. - * - Create a desktop shortcut or other way to launch the Eclipse executable - * easily. - * - Launch Eclipse. - * - Eclipse will ask you a directory for its initial workspace, make it point - * to the ChibiOS/RT root directory (you may have as many workspaces you - * want, keep this for later), make sure to select the check box or it will - * ask you again each time. - *

- * @image html tool001.jpg - *
- * - Now you should see the welcome screen, close it and you will be in the - * normal C/C++ perspective. - * - Unselect "Project->Build Automatically" unless you like insanity. - * - Disable the "usage collector" in - * "Window->Preferences->Usage_Data_Collector" by unselecting "Enable - * capture". - * - If you are behind a proxy or firewall (corporate users usually are) - * configure the correct parameters in - * "Window->Preferences->General->Network_Connections". - * - Let Eclipse auto update to the latest version "Help->Check_for_Updates". - * . - * - * @section install_zylin Zylin Plugin Installation - * Eclipse requires an hardware debugger component in order to perform on board - * execution and debug. - * - Open Eclipse, then "Help->Install_New_Software...". - * - Press the "Add..." button and put http://opensource.zylin.com/zylincdt - * into the location field, then press OK. The Zylin plugin will appear in the - * available plugins view, select and install it. - *

- * @image html tool002.jpg - * . - * - * @section install_openocd OpenOCD Installation - * Windows users just have to use the installer. Linux user should follow the - * normal installation procedure for deb or rpm packages, of course it is also - * possible to build it from the source code. - * - * @section install_doxygen Doxygen Installation - * Just use the installer, Linux users probably have Doxygen already available - * from the repositories. Make sure that the Doxygen binaries directory - * is listed in the PATH variable or Eclipse would not be able to locate it. - * - * @section install_graphviz Graphviz Installation - * Just use the installer, Linux users probably have Graphviz already available - * from the repositories. Make sure that the Graphviz binaries directory - * is listed in the PATH variable or Doxygen would not be able to locate it. - * - * @section install_eclox Eclox Installation - * Use the same installation steps used for the Zylin plugin except use - * http://download.gna.org/eclox/update as URL. Install "Eclox" not "Eclox - * Hot". - * After installing Eclox you will be able to compile Doxygen documentation - * using the button with the blue @@ inside. - */ diff --git a/ChibiOS_2.0.8/docs/src/eclipse2.dox b/ChibiOS_2.0.8/docs/src/eclipse2.dox deleted file mode 100644 index fe657b4..0000000 --- a/ChibiOS_2.0.8/docs/src/eclipse2.dox +++ /dev/null @@ -1,256 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_eclipse2 Embedded development using Eclipse - * @brief Compiling and debugging ChibiOS/RT applications using Eclipse. - * @details This article will explain how to use an Eclipse based toolchain - * (see @ref article_eclipse) to develop ChibiOS/RT based applications. - * This guide will allow you to: - * - Importing ChibiOS/RT demos into the Eclipse environment. - * - Edit and reformat your source code. - * - Compile and examine errors and warnings. - * - Upload your program on the target board. - * - Debug your code on the target board both in high level language and - * assembler. - * - Develop embedded applications with or without ChibiOS/RT. - * . - * - *

What this guide does not cover

- * This guide assumes knowledge in following areas: - * - OpenOCD setup is not covered by this guide because the setup changes - * depending on the JTAG probe used, the target MCU and also the target - * board. The guide will show the setup for a specific JTAG probe and a - * specific target, a valuable source for the OpenOCD setup is the - * - * dedicated forum, most questions you may have about OpenOCD have - * most likely already been answered there. - * - Hardware setup. - * . - * In general this guide is not a replacement for the Eclipse, GCC, Make, - * binutils, newlib, GDB, OpenOCD user manuals, the guide simply aims to - * give you a faster start. - * - *

Article Index

- * - @ref eclipse2_requirements - * - @ref eclipse2_importing - * - @ref eclipse2_creating - * - @ref eclipse2_compiling - * - @ref eclipse2_configuring - * - @ref eclipse2_configuring_gdb - * - @ref eclipse2_configuring_openocd - * . - * - @ref eclipse2_debugging - * - @ref eclipse2_debugging_start - * - @ref eclipse2_debugging_stop - * . - * . - * - * @section eclipse2_requirements Required Components - * This guide requires: - * - An Eclipse/GCC/OpenOCD based toolchain, as example the one described in - * the article @ref article_eclipse. - * - An Olimex ARM-USB-OCD JTAG probe, this guide applies to any other ARM - * JTAG probe as long it is supported by OpenOCD. - * - An Olimex STM32-P103 target board, this guide applies to any other ARM - * target except for the OpenOCD setup part. - * - A terminal emulator for capturing the board serial output, Windows users - * may use Hyper Terminal, Linux and MAC OS-X users may use - * CuteCom. - * All ChibiOS/RT demos generate on the serial port a test report when a - * button on the target board is pressed, other demos may activate a command - * shell on the serial port, in both cases a terminal emulator is required. - * . - * - * @section eclipse2_importing Importing existing ChibiOS/RT demos into Eclipse - * The first step is to import a project into the Eclipse environment. - * ChibiOS/RT demos do not include Eclipse project files but just a normal - * Makefile. Eclipse is able to import a Makefile project and create - * its own project file so this is not a problem. This is how it is done: - * - Open you Eclipse environment and select the workspace created into the - * ChibiOS/RT project directory. - * - From within Eclipse select "File->New->C_Project", a dialog box will show. - * - Select "Makefile_project->Empty_Project" in the "Project type:" box. - * - Select "-- Other Toolchain --" in the "Toolchains:" box. - * - Unselect the "Use default location" check box. - * - Select the demo directory using the "Browse..." button. Something like - * "C:\Projects\ChibiOS-RT\demos\ARMCM3-STM32F103-GCC" will appear in the - * "Location:" box. - * - In the project name box put the same name of the directory containing - * the demo, ARMCM3-STM32F103-GCC in this example. - *

- * @image html eclipse003.jpg - *
- * - Press the "Finish" button and the project will be created and shown in - * the "Project Explorer". - * - Right click on the imported project and select "Index->Rebuild", this - * will make Eclipse build its internal symbols database. - * - Repeat the above steps for each ChibiOS/RT demo you want to import in - * Eclipse, all the demos that have a makefile can be imported. - * . - * - * @section eclipse2_creating Creating a new ChibiOS/RT application - * If you want to create a new application it is recommended that you create - * a Makefile project first then you can import it into eclipse using the above - * procedure. Makefile projects have the advantage that can be compiled - * everywhere even without Eclipse. Creation steps: - * - Create your own development directory under the ChibiOS/RT installation - * directory, as example "chibios/myprojects". - * - Copy an existing demo, of course choose a demo using your same target, - * under the new directory and rename it, as example - * "chibios/myprojects/myapplication". - * - Customize the Makefile if needed, usually you just need to do this if - * your application is composed by more than one source file. You may also - * want to remove the ChibiOS/RT test code from your application. - * - Once your makefile is ready, import the project under the Eclipse - * workspace using the procedure described in @ref eclipse2_importing. - * . - * - * @section eclipse2_compiling Compiling and Cleaning applications - * Once imported, an application can be compiled by using the "Build All" in - * the toolbar or by right clicking on the project and selecting "Build - * Project". In order to clean a project (removing all the temporary and binary - * files) right click on the project and select "Clean Project". - *

- * @image html eclipse004.jpg - *
- * The compilation result is visible as a complete log in the "Console" window, - * the detail of all errors an warnings is available in the "Problems" window. - *

- * @image html eclipse005.jpg - *
- * The build process produces the binary files specified in the Makefile, all - * the ChibiOS/RT demos produce binary files named ch.elf, ch.bin and/or - * ch.hex. The image must be loaded on the target board in order to execute - * it. The build process usually creates also some other useful files - * containing details about the built application (usually named ch.map and - * ch.dmp). - * - * @section eclipse2_configuring Preparing for Debug - * In order to debug your application a debug configuration must be created. - * The configuration instructs GDB (the source debugger used by Eclipse) on - * how to load the image, load the symbols and place the initial breakpoint - * in the make function. Note that GDB performs its function by connecting - * to a "GDB server", the DGB server implements the low level communication - * with the target device through the JTAG probe. In our scenario the GDB - * server functionality is performed by OpenOCD, this mean that OpenOCD must - * be running while performing a debug session within Eclipse. - * - * @subsection eclipse2_configuring_gdb Creating a GDB Debug Configuration - * A target specific debug configuration is required in order to: - * - Establish a connection with the GDB server. - * - Stop and reset the target. - * - Upload the binary code in Flash or RAM. - * - Set an initial breakpoint in the main function. - * - Start the target (which will immediately stop on the breakpoint). - * . - * The first thing to do is to open the "Debug Configurations..." dialog: - *

- * @image html eclipse006.jpg - *
- * The configuration dialog will appear, we must create a native Zylin - * configuration: - *

- * @image html eclipse007.jpg - *
- * Now we must give the configuration a name, "ARMCM3-STM32F103-GCC (flash and - * run)" in this example, then setup the various configuration pages as follow: - *

- * The "Main" tab: - * @image html eclipse008.jpg - *

- * The "Debugger" tab: - * @image html eclipse009.jpg - *

- * The "Commands" tab: - * @image html eclipse010.jpg - *
- * Note that the "Commands" tab contains the part that changes depending on - * the target. The complete commands sequence (it is not fully visible in the - * image) for STM32 is: - * @code - * monitor soft_reset_halt - * monitor wait_halt - * monitor poll - * monitor flash probe 0 - * monitor stm32x mass_erase 0 - * monitor flash write_bank 0 ch.bin 0 - * monitor soft_reset_halt - * symbol-file ch.elf - * thbreak main - * continue - * @endcode - *

- * The "Common" tab: - * @image html eclipse011.jpg - *
- * Now the debug configuration is complete. - * - * @subsection eclipse2_configuring_openocd Configuring and running OpenOCD - * OpenOCD must be run, with appropriate parameters, before starting your - * debug session. Please refer to the OpenOCD documentation in order to - * properly launch it for your target. - *
**To be completed** - * - * @section eclipse2_debugging Debugging - * Now we are ready to debug an application on the target. Note that Eclipse - * have a mechanism called "Perspectives", you edit and compile your source - * code while you are in the "C/C++ perspective" while the debugging is - * performed in the "Debug perspective". You can switch perspective at any - * time, even while there is an active debug session. If you install more of - * the many Eclipse extension plugins (there are thousands) you may have even - * more perspectives available. - * - * @subsection eclipse2_debugging_start Starting a Debug Session - * In order to start a debugging session first make sure that OpenOCD is - * running then press the drop down menu on the right side of the - * debug icon in the toolbar (the small green bug) and select your - * debug configuration (we created just one but you may have multiple - * debug configurations in your project, as example I usually create - * another debug configuration that just starts the target without - * uploading the code). - *

- * @image html eclipse012.jpg - *
- * The debugger will be initialized, you will see the operation in progress on - * the console then Eclipse will switch to the debug perspective and you will - * see your program stopped on the default breakpoint in the main function. - *

- * @image html eclipse013.jpg - *
- * From there you can perform all the usual debugging tasks, set breakpoints, - * single step execution, variables, memory and registers inspection etc. - * Please refer to the Eclipse documentation about those "normal" operations. - * Note that if the debugging start procedure hangs then there is probably - * an error in your configuration or problems with the target, read the - * console log and/or the OpenOCD output in order to understand where the - * problem is. - * - * @subsection eclipse2_debugging_stop Stopping a Debug Session - * From the debug perspective press the stop button (small red square) in the - * debug window, the target will be stopped and you may both return to the - * C/C++ perspective or start it again. - */ diff --git a/ChibiOS_2.0.8/docs/src/events.dox b/ChibiOS_2.0.8/docs/src/events.dox deleted file mode 100644 index 0f40c33..0000000 --- a/ChibiOS_2.0.8/docs/src/events.dox +++ /dev/null @@ -1,130 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_events Events Explained - * Events are an important feature in ChibiOS/RT, most device drivers generate - * events in order to notify the application that something happened at the - * I/O level.
- * While event flags are not something unknown in other operating systems, - * their peculiar implementation in ChibiOS/RT requires a more in depth - * explanation.
- * Lets start with the events related terminology: - * - Event Source, an @p EventSource is a system object that can be - * @a broadcasted asynchronously in response of a system event, as example, - * when the CAN driver receives a packet from the CAN bus it @a broadcasts - * an event source in order to inform the registered threads that a packet - * has just arrived. - * - Broadcast, the operation performed on an event source in order - * to inform the @a registered threads that an event just occurred. - * Broadcasting can happened both in interrupt handlers and in threads. - * - Event Listener, a system object that associates a @p Thread object - * to an event source. The process of associating a @p Thread to an - * @p EventSource using an @p EventListener is called @a registration. - * - Registration, action performed by a thread in order to be informed - * of events from a specific event source. Of course a thread can be - * @a registered on more than one event source by using multiple - * @p EventListener objects. Threads can also @a unregister from an event - * source. - * - Pend, each thread has a mask of @a pending events. The @a broadcast - * operation @a pends an event mask on all the @a registered threads. - * - Wait, synchronous operation performed by a thread in order to - * @a wait a specific combination of events. The API offers a variety of - * @a wait functions, please refer to the events API documentation. - * . - * Note that events are asynchronously generated, as example in an interrupt - * handler, but are synchronously served. - * - *

Events related data structures

- * The following diagram explains the relationship between an event source, - * its list of event listeners and the @a registered threads. - * @dot - digraph example { - rankdir="LR"; - - node [shape=rectangle, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1.0", height="0.5"]; - edge [fontname=Helvetica, fontsize=8, sep=3.0]; - - es [shape=record, label="EventSource | es_next", style="bold"]; - - subgraph cluster_0 { - fontname=Helvetica; - label = "Listeners List"; - color = blue; - node [shape=record, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1.5", height="1.0"]; - el4 [label="EventListener 4 | el_mask: 0x0001 | el_listener | el_next"]; - el3 [label="EventListener 3 | el_mask: 0x0C00 | el_listener | el_next"]; - el2 [label="EventListener 2 | el_mask: 0x0001 | el_listener | el_next"]; - el1 [label="EventListener 1 | el_mask: 0x0004 | el_listener | el_next"]; - el1 -> el2 -> el3 -> el4 [label=" el_next", constraint=false]; - } - - subgraph cluster_1 { - fontname=Helvetica; - label = "Registered Threads"; - color = blue; - node [shape=record, fontname=Helvetica, fontsize=8, - fixedsize="true", width="1.5", height="0.8"]; - t1 [label="Thread 1 | p_epending:0x0000 | p_ewmask:0xFFFF"]; - t2 [label="Thread 2 | p_epending:0x000F | p_ewmask:0x0C01"]; - t3 [label="Thread 3 | p_epending:0x0008 | p_ewmask:0x0001"]; - t4 [label="Thread 4 | p_epending:0x0000 | p_ewmask:0xFFFF"]; - } - - es -> el1 [label=" es_next"]; - el4 -> es [label=" el_next"]; - el1 -> t1 [label="el_listener"]; - el2 -> t2 [label="el_listener"]; - el3 -> t3 [label="el_listener"]; - el4 -> t4 [label="el_listener"]; - } - * @enddot - * Note that each event listener has a different bit mask to be @a pended on - * its associated thread when the event source is @a broadcasted, this means - * that each thread can define its own event identifiers independently. A - * @a broadcast operation can also @a pend more than one bit on the - * @a registered threads.
- * The threads have a variety of @a wait primitives, they can @a wait for one - * or more event flags to become @a pending, and can also specify AND/OR - * conditions, as example a thread can @a wait for any event to become - * @a pending or @a wait for all the specified events to become @a pending.
- * The field @p p_epending is the mask of the currently pending events, - * the field @p p_ewmask is the mask of the events the thread is interested - * on in that moment (AND or OR condition depending on the invoked - * @a wait API). - * - *

Use Scenarios

- * Events are best used when one of more of the following conditions are - * required: - * - Having to wait on multiple conditions, Events are the only mechanism - * that easily allow that. - * - Synchronous response to one or more asynchronous events. - * - Single threaded applications working in a event driver environment (but - * events are not limited to single threaded applications). - * . - */ diff --git a/ChibiOS_2.0.8/docs/src/goals.dox b/ChibiOS_2.0.8/docs/src/goals.dox deleted file mode 100644 index cf5acb6..0000000 --- a/ChibiOS_2.0.8/docs/src/goals.dox +++ /dev/null @@ -1,95 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page goals Project Goals - *

Another RTOS?

- * The first question to be answered is: there was really the need for YET - * ANOTHER RTOS?
- * There are several reasons: - * - The ChibiOS/RT ancestor was created more than 15 years ago and while it - * had far less features than the current product it was complete and - * functioning. ChibiOS/RT is just a new (and silly) name given to - * something created when there were not many free RTOSes around (actually - * none, at least none in my knowledge, there was no widespread Internet - * at that time). - * - When, after a while, I needed a RTOS again, none of the existing FOSS - * projects met my expectations or my ideas of how a RTOS should be, not - * even close (see below). I decided that work on that old project was - * a better idea than contribute to, or fork, something else. - * - I wanted another toy. - * . - *

Why is it different?

- * Well, there are some design choices that should be explained and contribute - * to make ChibiOS/RT a peculiar design. Nothing really new in itself but - * the whole is interesting: - * - *

Static design

- * Everything in the kernel is static, nowhere memory is allocated or freed, - * there are three allocator subsystems but those are options and not part of - * core OS. Safety is something you design in, not something you can add later. - * - *

No tables, arrays or other fixed structures

- * The kernel has no internal tables, there is nothing that must be configured - * at compile time or that can overflow at run time. No upper bounds, the - * internal structures are all dynamic even if all the objects are statically - * allocated. - * - *

No error conditions and no error checks

- * All the system APIs have no error conditions, all the previous points are - * finalized to this objective. Everything you can invoke in the kernel is - * designed to not fail unless you pass garbage as parameters, stray pointers - * as examples. The APIs are not slowed down by parameter checks, - * parameter checks (and consistency checks) do exist but only when the - * debug switch is activated.
- * All the static core APIs always succeed if correct parameters are passed. - * Exception to this are the optional allocators APIs that, of course, - * can report memory exhausted. - * - *

Very simple APIs

- * Each API should have the parameters you would expect for that function and - * do just one thing with no options. - * - *

Fast and compact

- * Note, first "fast" then "compact", the focus is on speed and execution - * efficiency and then on code size. This does not mean that the OS is large, - * the kernel size with all the subsystems activated weighs around 5.3KiB - * and can shrink down around to 1.2Kib in a minimal configuration - * (STM32, Cortex-M3). It would be possible to make something even smaller but: - * -# It would be pointless, it is already @a really small. - * -# I would not trade efficiency or features in order to save few bytes. - * . - * About the "fast" part, the kernel is able to start/exit over - * 220,000 threads per second on a 72MHz STM32. - * The Context Switch takes 1.2 microseconds on the same STM32. - * - *

Tests and metrics

- * I think it is nice to know how an OS is tested and how it performs before - * committing to use it. Test results on all the supported platforms and - * performance metrics are included in each ChibiOS/RT release. The test - * code is released as well, all the included demos are capable of executing - * the test suite and the OS benchmarks, see @ref testsuite. - */ diff --git a/ChibiOS_2.0.8/docs/src/integrationguide.dox b/ChibiOS_2.0.8/docs/src/integrationguide.dox deleted file mode 100644 index c2ae611..0000000 --- a/ChibiOS_2.0.8/docs/src/integrationguide.dox +++ /dev/null @@ -1,102 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_integrationguide Integration Guide - * All the delivered ChibiOS/RT demos are stand alone applications so if - * you just start your application from an existing demo there isn't any - * integration effort, you are simply using the existing makefiles, the - * default startup files etc, minimal effort.
- * The matter is very different if you are going to integrate the OS into - * a different runtime framework or if you want to use a different build - * system, in that case you have the problem to integrate the OS source - * code into your application. - * - *

What this guide does not cover

- * This guide has a limited scope, the following topics are handled elsewhere: - * - Porting the OS to different architectures or different compilers is - * not covered in this guide, see @ref article_portguide instead. - * - This guide does not describe any specific environment or development - * tool, it is assumed you already know in detail the environment you - * want to work with. - * . - * - *

Article Index

- * - @ref integrationguide_kernel - * - @ref integrationguide_hal - * . - * @section integrationguide_kernel Integrating the Kernel - * This section covers the scenario where you want to use the ChibiOS/RT - * kernel into an existing application. In order to accomplish this you need - * to import in your project two components: - * - The portable kernel. - * - The port layer for your microcontroller. - * . - * See the @ref architecture for more details. - * You need to add the following files to your build process: - * - All the source files contained under ./os/kernel/src, note that - * you should add all of them even if you don't plan to use some of the - * subsystems. Unused subsystems can be excluded from the kernel - * configuration file @p chconf.h. - * - All the source files contained under - * ./os/ports/@/@. - * Note that those could be both C source files and assembler source files - * and that some architectures have an extra directories layer containing - * files required for a specific platform. - * . - * You also need to add to the compiler options the following paths for - * searching header files: - * - The portable kernel headers ./os/kernel/include. - * - The port layer headers - * ./os/ports/@/@. - * . - * @section integrationguide_hal Integrating the HAL - * If, in addition to the kernel as described in the previous section, you also - * need to integrate the HAL into your application you also need to import - * the following components: - * - HAL portable files. - * - Platform specific files. - * . - * See the @ref architecture for more details. - * You need to add the following files to your build process: - * - All the source files contained under ./os/hal/src, note that - * you should add all of them even if you don't plan to use some of the - * subsystems. Unused drivers can be excluded from the HAL configuration - * file @p halconf.h. - * - All the source files contained under - * ./os/hal/platforms/@. - * - All the source files contained under - * ./boards/@. - * . - * You also need to add to the compiler options the following paths for - * searching header files: - * - The portable HAL headers ./os/hal/include. - * - The platform layer headers - * ./os/hal/platforms/@. - * - The board description headers - * ./boards/@. - * . - */ diff --git a/ChibiOS_2.0.8/docs/src/interrupts.dox b/ChibiOS_2.0.8/docs/src/interrupts.dox deleted file mode 100644 index bb2c660..0000000 --- a/ChibiOS_2.0.8/docs/src/interrupts.dox +++ /dev/null @@ -1,76 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_interrupts How to write interrupt handlers - * Since version 1.1.0 ChibiOS/RT offers a cross-platform method for writing - * interrupt handlers. Port-related and compiler-related details are - * encapsulated within standard system macros. - * - *

Writing Regular Interrupt handlers

- * A Regular Interrupts handler (see @ref interrupt_classes) must be written - * using the following general form: - * @code -CH_IRQ_HANDLER(myIRQ) { - CH_IRQ_PROLOGUE(); - - // IRQ handling code, preemptable if the architecture supports it. - - chSysLockFromIsr(); - // Invocation of some I-Class system APIs, never preemptable. - chSysUnlockFromIsr(); - - // More IRQ handling code, again preemptable. - - CH_IRQ_EPILOGUE(); -} - * @endcode - * - *

Writing Fast Interrupt handlers

- * In those architectures (@ref ARM7 and @ref ARMCMx) supporting Fast - * Interrupts (see @ref interrupt_classes) handlers must be written - * using the following general form: - * @code -CH_FAST_IRQ_HANDLER(myIRQ) { - - // Fast IRQ handling code, preemptable if the architecture supports it. - // The invocation of any API is forbidden here because fast interrupt - // handlers can preempt the kernel even within its critical zones in - // order to minimize latency. -} - * @endcode - * - *

Handlers naming

- * A note about the handler name "myIRQ", in some ports it must be a - * vector number rather than a function name, it could also be a name from - * within a predefined set, see the notes about the various ports. - * - *

Important Notes

- * - There is an important application note about ARM7 interrupt handlers, - * please read about it in the ARM7 port section: @ref ARM7_IH - * . - */ - diff --git a/ChibiOS_2.0.8/docs/src/jitter.dox b/ChibiOS_2.0.8/docs/src/jitter.dox deleted file mode 100644 index 77b488e..0000000 --- a/ChibiOS_2.0.8/docs/src/jitter.dox +++ /dev/null @@ -1,142 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_jitter Response Time and Jitter - * Response time jitter is one of the most sneaky source of problems when - * designing a real time system. When using a RTOS like ChibiOS/RT one must - * be aware of what the jitter is and how it can affect the performance of the - * system. A good place to start is this - * Wikipedia - * article. - * - *

Interrupt handlers execution time

- * The total execution time of an interrupt handler includes: - * - Hardware interrupts latency, this parameter is pretty much fixed and - * characteristic of the system. - * - Fixed handler overhead, as example registers stacking/unstacking. - * - Interrupt specific handler code execution time, as example, in a serial - * driver, this is the time used by the handler to transfer data from/to - * the UART. - * - OS overhead. Any operating system requires to run some extra code - * in interrupt handlers in order to handle correct preemption and Context - * Switching. - * . - *

Interrupt Response Time

- * The Interrupt Response Time is the time from an interrupt event and the - * execution of the handler code. Unfortunately this time is not constant - * in most cases, see the following graph: - * - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; - edge [fontname=Helvetica, fontsize=8]; - int [label="Interrupt"]; - busy [label="Busy"]; - served [label="Interrupt\nServed"]; - int -> served [label="Not Busy (minimum latency)"]; - int -> busy [label="Not Ready"]; - busy -> busy [label="Still Busy\n(added latency)"]; - busy -> served [label="Finally Ready"]; - } - * @enddot - * - * In this scenario the jitter (busy state) is represented by the sum of: - * - Higher or equal priority interrupt handlers execution time combined. - * This time can go from zero to the maximum randomly. This value can be - * guaranteed to be zero only if the interrupt has the highest priority in - * the system. - * - Highest execution time among lower priority handlers. This value is zero - * on those architectures (Cortex-M3 as example) where interrupt handlers - * can be preempted by higher priority sources. - * - Longest time in a kernel lock zone that can delay interrupt servicing. - * This value is zero for fast interrupt sources, see @ref system_states. - * . - *

Threads Flyback Time

- * This is the time between an event, as example an interrupt, and the - * execution of the thread that will process it. Imagine the following - * graph as the continuation of the previous one. - * - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; - edge [fontname=Helvetica, fontsize=8]; - served [label="Interrupt\nServed"]; - busy [label="Busy"]; - thread [label="Thread\nAwakened"]; - served -> busy [label="Not highest Priority"]; - busy -> busy [label="Higher priority Threads\n(added latency)"]; - busy -> thread [label="Highest Priority"]; - served -> thread [label="Highest Priority (minimum latency)"]; - } - * @enddot - * - * In this scenario all the jitter sources previously discussed are also - * present and there is the added jitter caused by the activity of the - * higher priority threads. - * - *

Jitter Mitigation

- * For each of the previously described jitter sources there are possible - * mitigation actions. - * - *

Interrupt handlers optimization

- * An obvious mitigation action is to optimize the interrupt handler code as - * much as possible for speed.
- * Complex actions should never be performed in interrupt handlers. - * An handler should just serve the interrupt and wakeup a dedicated thread in - * order to handle the bulk of the work.
- * Another possible mitigation action is to evaluate if a specific interrupt - * handler really needs to interact with the OS, if the handler uses full - * stand-alone code then it is possible to remove the OS related overhead.
- * - *

Kernel lock zones

- * The OS kernel protects some critical internal data structure by disabling - * (fully in simple architecture, to some extent in more advanced - * microcontrollers) the interrupt sources. Because of this the kernel itself - * is a jitter cause, a good OS design minimizes the jitter generated by the - * kernel by using adequate data structures, algorithms and coding - * practices.
- * A good OS design is not the whole story, some OS primitives may generate - * more or less jitter depending on the system state, as example the maximum - * number of threads on a certain queue, the maximum number of nested mutexes - * and so on. Some algorithms employed internally can have constant execution - * time but others may have linear execution time or be even more complex. - * - *

Higher priority threads activity

- * At thread level, the response time is affected by the interrupt-related - * jitter but mainly by the activity of the higher priority threads and - * contention on protected resources.
- * It is possible to improve the system overall response time and reduce jitter - * by carefully assigning priorities to the various threads and carefully - * designing mutual exclusion zones.
- * The use of the proper synchronization mechanism (semaphores, mutexes, events, - * messages and so on) also helps to improve the overall system performance. - * The use of the Priority Inheritance algorithm implemented in the mutexes - * subsystem can improve the overall response time and reduce jitter but it is - * not a magic wand, a proper system design comes first. - */ diff --git a/ChibiOS_2.0.8/docs/src/licfaq.dox b/ChibiOS_2.0.8/docs/src/licfaq.dox deleted file mode 100644 index 13c4759..0000000 --- a/ChibiOS_2.0.8/docs/src/licfaq.dox +++ /dev/null @@ -1,126 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page lic_faq License and F.A.Q. - * ChibiOS/RT is a - * GPL3-licensed product but it offers a linking exception in its stable - * releases.
- * This article contains some answers about the exception. - * - * @section faq Frequently Asked Questions - * - Is ChibiOS/RT free ?
- * Yes, free as both in free beer and freedom. - * - Can I use it in my commercial embedded product?
- * Yes, you just have to advertise that you are using ChibiOS/RT by putting - * a link to the project somewhere on your web site or documentation. - * - Am I forced to release the source code of my product?
- * The exception to the GPL allows you to use ChibiOS/RT in your commercial - * application without have to release your source code under certains - * conditions. See the @ref exception_text under "Approved Interfaces" for - * details. - * - What I have to contribute back?
- * In general you have to offer changes done on existing files (where - * allowed) or new developments done using the OS template files. As example: - * - Ports to new architectures because a new port uses copyrighted OS - * template files. - * - New, HAL-style, device drivers because device drivers use copyrighted - * template files. - * - Improvements on modifiable OS code as described in the - * "approved interfaces" section of the @ref exception_text. - * . - * - Is the exception applicable to any ChibiOS/RT version ?
- * The exception is valid only for ChibiOS/RT releases marked as @e stable. - * Beta, unstable or development versions are covered by the GPL3 alone - * because are meant for testing only. - * - I don't want to be bound by any of the above restriction, is this - * possible?
- * You may contact us about a commercial license. - * . - * @section exception_text GPL Exception Text - -
GPL Exception Text for ChibiOS/RT 1.4.x
- - In addition, as a special exception, the copyright holder of ChibiOS/RT, -gives You the additional right to link the unmodified code of this Program with -code not covered under the GNU General Public License ("Non-GPL Code") and to -distribute linked combinations including the two, subject to the limitations -in this paragraph. - - -# Non-GPL Code permitted under this exception must only link to the - unmodified code of this Program through those well defined interfaces - identified as "Approved Interfaces". - -# Every copy of the combined work is accompanied by a written statement - that details to the recipient the version of ChibiOS/RT used and an - offer by yourself to provide the ChibiOS/RT source code should the - recipient request it. - -# The combined work is not itself an RTOS, scheduler, kernel or related - product. - -# The combined work is not itself a binary library intended for linking - into other software applications. - . - -
The Approved Interfaces
- - -# The files of Non-GPL Code may include the unmodified ChibiOS/RT - distribution header files contained under: - - ./os/kernel/include - - ./os/hal/include - - ./os/hal/platforms - - ./os/various - . - without causing the resulting work to be covered by the GNU General - Public License. - -# The files of Non-GPL Code may link to the unmodified ChibiOS/RT - distribution files contained under: - - ./os/kernel/src - - ./os/hal/src - - ./os/hal/platforms - - ./os/various - . - without causing the resulting work to be covered by the GNU General - Public License. - -# The files of Non-GPL Code may link to, or include, the modified or - unmodified ChibiOS/RT distribution files contained under: - - ./os/kernel/templates - - ./os/hal/templates - - ./os/ports - - ./boards - - ./demos - . - without causing the resulting work to be covered by the GNU General - Public License. - . - - Only the copyright holder of ChibiOS/RT may make changes or additions to the -list of Approved Interfaces. - - You must obey the GNU General Public License in all respects for all of the -Program code and other code used in conjunction with the Program except the -Non-GPL Code covered by this exception. - * - */ - diff --git a/ChibiOS_2.0.8/docs/src/lifecycle.dox b/ChibiOS_2.0.8/docs/src/lifecycle.dox deleted file mode 100644 index 5126485..0000000 --- a/ChibiOS_2.0.8/docs/src/lifecycle.dox +++ /dev/null @@ -1,75 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_lifecycle Threads Lifecycle - * In ChibiOS/RT threads are divided in two categories: - * - Static threads. The memory used for static threads is allocated at - * compile time so static threads are always there, there is no management - * to be done. - * - Dynamic threads. Dynamic threads are allocated at runtime from one - * of the available allocators (see @ref heaps, @ref pools). - * . - * Dynamic threads create the problem of who is responsible of releasing - * their memory because a thread cannot dispose its own memory.
- * This is handled in ChibiOS/RT through the mechanism of "thread references", - * When the @p CH_USE_DYNAMIC option is enabled the threads become objects - * with a reference counter. The memory of a thread, if dynamic, is freed - * when the last reference to the thread is released while the thread is in - * its @p THD_STATE_FINAL state.
- * The following diagram explains the mechanism: - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; - edge [fontname=Helvetica, fontsize=8]; - - init [label="No thread", style="bold"]; - alive [label="Alive"]; - final [label="Terminated"]; - detached [label="Detached", style="bold"]; - - init -> alive [label="chThdCreateX()"]; - alive -> alive [label="chThdAddRef()"]; - alive -> alive [label="chThdRelease()\n[ref > 0]"]; - alive -> detached [label="chThdRelease()\n[ref == 0]"]; - alive -> init [label="chThdWait()\n[ref == 0]"]; - alive -> final [label="chThdExit()\nreturn"]; - final -> final [label="chThdAddRef()"]; - final -> final [label="chThdRelease()\nchThdWait()\n[ref > 0]"]; - final -> init [label="chThdRelease()\nchThdWait()\n[ref == 0]"]; - } - * @enddot - *
- * As you can see the easiest way to ensure that the memory is released is - * to make another thread perform a @p chThdWait() on the dynamic thread.
- * If all the references to the threads are released while the thread is - * still alive then the thread goes in a "detached" state and its memory - * cannot be recovered unless there is a dedicated task in the system that - * scans the threads through the @ref registry subsystem, scanning the registry - * has the side effect to release the zombies (detached and then terminated - * threads). - */ diff --git a/ChibiOS_2.0.8/docs/src/main.dox b/ChibiOS_2.0.8/docs/src/main.dox deleted file mode 100644 index 887cd4b..0000000 --- a/ChibiOS_2.0.8/docs/src/main.dox +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @mainpage ChibiOS/RT - * @author Giovanni Di Sirio (gdisirio@users.sourceforge.net). - * - *

Chibi ?

- * I didn't want a serious name for this project. It is the Japanese word for - * small as in small child. So ChibiOS/RT - * @htmlonly (ちびOS/RT) @endhtmlonly - * means small Real Time Operating System. - * Source Wikipedia. - * - *

Features

- * - Free software, GPL3 licensed. Stable releases include a exception clause - * to the GPL. - * - Designed for realtime applications. - * - Easily portable. - * - Preemptive scheduling. - * - 128 priority levels. Multiple threads at the same priority level allowed. - * - Round robin scheduling for threads at the same priority level. - * - Offers threads, virtual timers, semaphores, mutexes, condvars, - * event flags, messages, mailboxes, I/O queues. - * - No static setup at compile time, there is no need to configure a maximum - * number of all the above objects. - * - PC simulator target included, the development can be done on a PC - * under Linux or Windows.
- * Timers, I/O channels and other HW resources are simulated in a guest OS - * process and the application code does not need to be aware of it. - * - No *need* for a memory allocator, all the kernel structures are static - * and declaratively allocated. - * - Optional, thread safe, Heap Allocator subsystem. - * - Optional, thread safe, Memory Pools Allocator subsystem. - * - Blocking and non blocking I/O channels with timeout and events generation - * capability. - * - Minimal system requirements: about 6KiB ROM with all options enabled and - * speed optimizations on. The size can shrink under 2KiB by disabling the - * the unused subsystems and optimizing for size. - * - Almost totally written in C with little ASM code required for ports. - * - Optional Hardware Abstraction Layer (HAL) with support for many device - * driver models and device driver implementations. - * . - *

Related pages

- * - @subpage credits - * - @subpage lic_faq - * - @subpage goals - * - @subpage target - * - @subpage architecture - * - @subpage concepts - * - @subpage articles - * - @subpage testsuite - * . - */ diff --git a/ChibiOS_2.0.8/docs/src/memory.dox b/ChibiOS_2.0.8/docs/src/memory.dox deleted file mode 100644 index e4c8e2e..0000000 --- a/ChibiOS_2.0.8/docs/src/memory.dox +++ /dev/null @@ -1,145 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_manage_memory How to manage memory - * ChibiOS/RT is a static kernel so you don't need to manage memory at all - * if your application doesn't really require it. This doesn't mean that - * the OS is unable to manage memory but just that memory management is an - * optional part of the whole.
- * The OS offers three distinct ways to manage memory, each one with its - * weaknesses and strengths: - * - Core Memory Manager. See @ref memcore. - * - Heap Allocator. See @ref heaps. - * - Memory Pools. See @ref pools. - * . - * The three mechanisms are able to coexist and are well integrated, as example - * the heap allocator uses the core memory manager in order to get more - * memory blocks, memory pools can optionally do the same thing. - * - *

The three subsystems

- * This is a small comparison table regarding the three subsystems, C-runtime - * and static objects are thrown in there for comparison:

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- * Subsystem - * - * Free capable - * - * Constant time - * - * Safe - * - * From IRQ - * - * Notes - *
- * Static Objects - * N/AN/AYESYES - * Preferred solution for safety applications. - *
- * Core Memory Manager - * NOYESYESYES - * Fast and safe but unable to free allocated memory. - *
- * Heap Allocator - * YESNONONO - * Unsafe because fragmentation and not constant time, cannot be used - * from IRQ handlers. - *
- * Memory Pools - * YESYESYESYES - * Fast and safe but it can handle fixed size objects only, you may have - * multiple memory pools however. - *
- * C-Runtime - * YESNONONO - * Unsafe because fragmentation, not constant time, cannot be used - * from IRQ handlers and not thread safe. The C runtime must also be - * modified in order to work with the other allocators. - *
- *
- * When designing a system it is recommended to proceed as follow: - * -# Use static objects and initializers whenever possible. - * -# Where dynamic allocation is required without have to free the allocated - * memory then use the Core Memory Manager allocation APIs. - * -# Where dynamic allocation is required evaluate if one or more memory - * pools can be used. - * -# If all the above points do not satisfy your requirements then use the - * heap allocator. - * -# Consider the C-runtime allocator only for legacy code. - * . - */ - diff --git a/ChibiOS_2.0.8/docs/src/mutualexcl.dox b/ChibiOS_2.0.8/docs/src/mutualexcl.dox deleted file mode 100644 index cb8d0e9..0000000 --- a/ChibiOS_2.0.8/docs/src/mutualexcl.dox +++ /dev/null @@ -1,217 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_mutual_exclusion Mutual Exclusion guide - * The most common problem when writing multithreaded code is the - * synchronization on the shared resources/services.
- * ChibiOS/RT offers a rich variety of mechanisms that apparently solve the - * same problem. I wrote apparently because each mechanism has its pro and - * cons. - * This article will introduce the various mechanisms and the explain the - * right scenarios for each one. - * - *

Basics

- * Some of the concepts mentioned in this article can be found in the - * following Wikipedia articles: - * - - * Mutual Exclusion - * - - * Priority Inversion - * - Priority Inheritance - * - - * Priority Ceiling - * . - *

Mutual exclusion by System Locks

- * This is the lowest level mechanism, the system is locked by invoking the - * @p chSysLock() API and then unlocked by invoking @p chSysUnlock().
- * The implementation is architecture dependent but it is guaranteed to, at - * least, disable the interrupt sources with hardware priority below or equal - * the kernel level. - * - *

Advantages

- * - It is the lightest as execution time, often a lock or unlock becomes just a - * single inlined assembler instruction. - * - It ensures mutual exclusion among threads but also interrupt handling code. - * - The implementation would ensure mutual exclusion even on multicore - * architectures where multiple hardware threads are present. - * . - *

Disadvantages

- * - Disabling interrupts for a long period of time can deteriorate the overall - * system response time and/or introduce jitter. - * . - *

When use Locks

- * - When mutual exclusion with interrupt handlers is required. - * - When the operation within the lock zone is very simple and has finite - * time. - * . - *

Example

- * @code - * ... - * chSysLock(); - * /* Protected code */ - * chSysUnlock(); - * ... - * @endcode - * - *

Mutual exclusion by Semaphores

- * In ChibiOS/RT the counting semaphores are mainly meant as a - * synchronization mechanism between interrupt handlers and high level code - * running at thread level. Usually a thread waits on a semaphore that is - * signaled asynchronously by an interrupt handler.
- * The semaphores can, however, be used as simple mutexes by initializing - * the semaphore counter to one. - * - *

Advantages

- * - The semaphores code is "already there" if you use the I/O queues or - * mailboxes and you don't want to enable the mutexes too in order to save - * space. - * - Semaphores are lighter than mutexes because their queues are FIFO - * ordered and do not have any overhead caused by the priority inheritance - * algorithm. - * - A semaphore takes less RAM than a mutex (12 vs 16 bytes on 32 bit - * architectures). - * . - *

Disadvantages

- * - Semaphore queues are FIFO ordered by default, an option exist to make - * them priority ordered but this can impact I/O performance because - * semaphores are used in I/O queues. - * - Semaphores do not implement the Priority Inheritance algorithm. - * . - *

When use Semaphores

- * - When you don't need queuing by priority nor the Priority Inheritance - * algorithm. - * - When RAM/ROM space is scarce. - * . - *

Example

- * @code - * static Semaphore sem; /* Semaphore declaration */ - * ... - * chSemInit(&sem, 1); /* Semaphore initialization before use */ - * ... - * chSemWait(&sem); - * /* Protected code */ - * chSemSignal(&sem); - * ... - * @endcode - * - *

Mutual exclusion by Mutexes

- * The mutexes are the mechanism intended as the most general solution for - * Mutual Exclusion. - * - *

Advantages

- * - Mutexes implement the Priority Inheritance algorithm that is an important - * tool in reducing jitter and improve overall system response time (it is - * not a magic solution, just another tool for the system designer). - * . - *

Disadvantages

- * - Heaviest among all the possible choices. The Priority Inheritance method - * is efficiently implemented but nothing is more efficient than no code at - * all. - * . - *

When use Mutexes

- * - When you are designing a very complex system with hard realtime - * requirements. - * . - *

Example

- * @code - * static Mutex mtx; /* Mutex declaration */ - * ... - * chMtxInit(&mtx); /* Mutex initialization before use */ - * ... - * chMtxLock(&mtx); - * /* Protected code */ - * chMtxUnlock(); - * ... - * @endcode - * - *

Mutual exclusion by priority boost

- * Another way to implement mutual exclusion is to boost the thread priority - * to a level higher than all of the threads competing for a certain resource. - * This solution effectively implements an Immediate Priority Ceiling - * algorithm. - * - *

Advantages

- * - Almost free as code size, you need no semaphores nor mutexes. - * - No RAM overhead. - * - Fast execution, priority change is a quick operation under ChibiOS/RT. - * - The Priority Ceiling protocol can help mitigate potential Priority - * Inversion problems. - * . - *

Disadvantages

- * - Makes the design more complicated because priorities must be assigned to - * not just threads but also assigned to the resources to be protected. - * - Locking a resource affects all the threads with lower priority even if - * not interested to the resource. - * - All the threads that can access the resource must have lower priority - * than the resource itself. - * - The mechanism is not easy to understand in the code unless it is clearly - * documented. - * - This method does not work in on multicore architectures where multiple - * hardware threads are present. - * - Only useful in very simple applications. - * . - *

Example

- * @code - * /* Priority assigned to the resource, threads must have lower - * priority than this.*/ - * #define AAA_RESOURCE_PRIORITY NORMALPRIO+10 - * ... - * /* Locks the resources AAA.*/ - * tprio_t aaa_old_prio = chThdSetPriority(AAA_RESOURCE_PRIORITY); - * /* Accessing resource AAA */ - * chThdSetPriority(aaa_old_prio); /* Unlocks AAA.*/ - * ... - * @endcode - * - *

Mutual exclusion by message passing

- * Another method is to make a single dedicated thread execute the critical - * code and make it work as a messages server. The other threads can request - * the service to the server by sending a properly formatted message and - * then wait for the answer with the result.
- * This method is very useful when integrating into the system components not - * designed to be reentrant or to be executed in a multithreaded environment, - * as example a 3rd part file system or a networking protocol stack. - * - *

Advantages

- * - It is possible to encapsulate very complex logic without worry about - * about concurrent accesses. - * - If the encapsulate code uses a large stack area only the server thread - * have to allocate enough RAM, the client threads save RAM by just - * requesting the service to the server. - * - Clean system architecture. - * - This method also implements a form of Priority Ceiling. The ceiling is - * the priority of the server thread itself. - * . - *

Disadvantages

- * - More complex implementation, a protocol must be created between clients - * and server. - * - Two context switches are required for each request to the server (but - * ChibiOSRT is very efficient at that). - * - Requires a dedicated thread as server. - * . - */ diff --git a/ChibiOS_2.0.8/docs/src/portguide.dox b/ChibiOS_2.0.8/docs/src/portguide.dox deleted file mode 100644 index c475bfd..0000000 --- a/ChibiOS_2.0.8/docs/src/portguide.dox +++ /dev/null @@ -1,127 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_portguide Porting ChibiOS/RT for Dummies - * Porting the operating system on a new platform is one of the most common - * tasks. The difficulty can range from easy to very difficult depending - * on several factors.
- * We can divide in problem in several classes of progressively increasing - * difficulty: - * - @ref port_board - * - @ref port_family - * - @ref port_chip - * - @ref port_core - * . - * Another kind of port type is porting to another compiler and this is an - * added complexity level on the above classes. The kernel itself is portable - * but the port-specific code usually contains compiler specific extensions to - * the C language and the asm files syntax is almost never compatible. - * - * @section port_board Porting the OS to a new board - * This is the easiest port type, the scenario is that the specific - * microcontroller is already supported and a demo exists. This scenario also - * applies when porting the OS on a custom hardware using a supported - * microcontroller. This task can be easily performed with the following - * steps: - * -# Create a new directory under ./boards and copy inside the board files - * from another board using the same microcontroller. - * -# Customize the board files: - * - @p board.h This file contains the I/O pins setup for the uC, it - * may also contain other board-dependent settings, as example, the clock - * frequency. Customize this file depending on your target hardware. - * - @p board.c This file contains the initialization code, it is possible - * you just need to customize @p board.h and not this file. If you have - * some hardware specific initialization code then put it here. - * . - * -# Create a new directory under the ChibiOS/RT installation directory: - * ./projects/@ - * -# Copy an existing demo code under the newly created directory. - * -# Customize the demo: - * - @p Makefile You may edit this file in order to remove the test related - * sources and/or add you application source files. - * - @p main.c It contains the demo simple code, clean it and write your - * own @p main() function here, use this file just as a template. - * -# Compile your application and debug. - * . - * @section port_family Porting the OS to a closely related microcontroller - * In this scenario all the above steps are required but an analysis must - * be performed to evaluate the differences between from the supported micro - * and the target micro. Often the micros just differ for the memory area - * sizes and a change to the linker script is enough (the file is usually - * named @p ch.ld). Chips having more or less peripherals, everything else - * being the same or compatible are not a problem also as long the timer and - * the serial peripherals used by the port do not change.
- * If there are differences in the internal peripherals, as example non - * compatible interrupt controllers (this happens in the LPC2000 family) - * or differences in UARTS, timers etc then the port falls in the following - * category. - * - * @section port_chip Porting the OS to another microcontroller using the same core - * This kind of port is required when a target microcontroller has the same - * core (a common example: ARM7) of a supported microcontroller but has - * differences in the internal peripherals.
- * If this is your case proceed as follow: - * -# Create a new directory under @p ./os/io/platforms and - * name it with the microcontroller name (or family name).
- * In case of the ARM-based microcontroller you also need to create a - * equally named directory under - * @p ./os/ports/@/@ and - * put there the microcontroller related files such as the vectors table, - * see the existing ports as example. - * -# Copy into the newly created directory the most closely related existing - * chip port or the naked template files from - * @p ./os/io/templates. - * -# Work out the differences in the drivers or implement them if you started - * from the templates. - * -# Edit/create the documentation file @p platform.dox, this - * is required if you want to regenerate this documentation including - * your work. - * . - * Usually this kind of port just requires a serial driver (and those are very - * similar each other) and some code for the interrupt controller (this one - * can be part of the core port, as example the Cortex-M3 has this as standard - * part of the core).
- * When the chip port is completed created your application as seen in the - * previous sections. - * - * @section port_core Porting the OS to a whole new architecture - * This is the hardest scenario, the time required by core ports depends - * strongly by the target architecture complexity and the level of support you - * need for the architecture specific features.
- * As a reference, the MSP430 port took me 2 hours and it worked at the first - * run, it can be a reference for simple architectures, the ARM Cortex-M3 was - * painful instead, the architecture enforces you to implement things in a very - * specific way and I spent 2 week to go through all the documentation and - * figure out the correct way to implement the port (you can see that the - * preemption context switch is done in a very peculiar way because the - * exceptions architecture).
- * One thing is sure, port an OS to a new architecture is not an easy task and - * if you have the required experience for such an effort then probably you - * don't need any advice from me. Just follow the directory patterns and fill - * the OS template files, the hardest part is decide the correct and efficient - * way to implement the context switching. - */ diff --git a/ChibiOS_2.0.8/docs/src/roundrobin.dox b/ChibiOS_2.0.8/docs/src/roundrobin.dox deleted file mode 100644 index abe416f..0000000 --- a/ChibiOS_2.0.8/docs/src/roundrobin.dox +++ /dev/null @@ -1,57 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_roundrobin Round Robin scheduling explained - * Unlike many other RTOSes, ChibiOS/RT supports multiple threads at the - * same priority level and schedules them using an aggressive - * round-robin strategy.
- * The strategy is defined as aggressive because any scheduling event - * causes the round-robin threads to rotate.
- * A round-robin rotation can happen because of the following events: - * - The currently executed thread voluntarily invokes the @p chThdYield() - * API in order to allow the execution of another thread at the same - * priority level, if any. - * - The currently executed thread voluntarily goes into a sleep state - * (see @ref thread_states), when the thread is awakened it goes behind - * any other thread at the same priority level. - * - The currently executed thread is preempted by an higher priority - * thread, the thread is reinserted in the ready list (see @ref scheduling) - * behind any other thread at the same priority level. - * - If the @p CH_TIME_QUANTUM configuration constant is set to a value - * greater than zero and if the specified time quantum expired and if - * a thread with equal priority is ready then the currently executing - * thread is automatically reinserted in the ready list behind any - * other thread at the same priority level. - * . - * As you can see the @p CH_TIME_QUANTUM setting is really useful only if - * there are threads at the same priority level that can run not preempted - * for long periods of time and that do not explicitly yield using - * @p chThdYield(). Because of this you should consider setting - * @p CH_TIME_QUANTUM to zero in your configuration file, this makes the - * kernel much faster and smaller and does not forbid the use of - * multiple threads at the same priority level. - */ diff --git a/ChibiOS_2.0.8/docs/src/saveram.dox b/ChibiOS_2.0.8/docs/src/saveram.dox deleted file mode 100644 index f69df46..0000000 --- a/ChibiOS_2.0.8/docs/src/saveram.dox +++ /dev/null @@ -1,88 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_saveram Saving RAM by declaring thread functions "noreturn" - * One of the problems, when writing embedded multi-threaded applications, - * is that the thread functions do save the registers in the function - * entry code even if the system does not require it, exiting such - * a function would terminate the thread so there is no need to preserve - * the register values. This can waste tens of bytes for each thread.
- * Consider the following code: - * @code -#include - -static WORKING_AREA(waMyThread, 64); - -static t_msg MyThread(void *arg) { - while (!chThdShoudTerminate()) { - /* Do thread inner work */ - } - return 1; -} - -main() { - chSysInit(); - ... - chThdCreateStatic(waMyThread, sizeof(waMyThread), NORMALPRIO, MyThread, NULL); - ... -} - * @endcode - * The resulting ASM code for the thread function would be something like this: - * @code -MyThread: - stmfd sp!, {r4, r5, r6, lr} - ... - ldmfd sp!, {r4, r5, r6, pc} - * @endcode - * Being that function a thread there is no need to save those registers, in - * embedded applications often the RAM is a scarce resource. That space can be - * saved by modifying the code as follow, using some advanced GCC extensions: - * @code -#include - -static WORKING_AREA(waMyThread, 64); - -__attribute__((noreturn)) -static void MyThread(void *arg) { - while (!chThdShoudTerminate()) { - /* Do thread inner work */ - } - chThdExit(1); -} - -main() { - chSysInit(); - ... - chThdCreateStatic(waMyThread, sizeof(waMyThread), NORMALPRIO, - (tfunc_t)MyThread, NULL); - ... -} - * @endcode - * This will make GCC believe that the function cannot return and there is no - * need to save registers. The code will be a bit less readable and less - * portable on other compilers however. - */ diff --git a/ChibiOS_2.0.8/docs/src/stacks.dox b/ChibiOS_2.0.8/docs/src/stacks.dox deleted file mode 100644 index 0dff8cd..0000000 --- a/ChibiOS_2.0.8/docs/src/stacks.dox +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_stacks Stacks and stack sizes - * In an RTOS like ChibiOS/RT there are several dedicated stacks, each stack - * has a dedicated RAM space that must have a correctly sized assigned area. - *

The stacks

- * There are several stacks in the systems, some are always present, some - * others are present only in some architectures: - * - Main stack, this stack is used by the @p main() function and the - * thread that execute it. It is not a normal thread stack because it is - * initialized in the startup code and its size is defined in a port - * dependent way. Details are in the various ports documentation. - * - Interrupt Stack, some architectures have a dedicated interrupt - * stack. This is an important feature in a multithreaded environment, - * without a dedicated interrupt stack each thread has to reserve - * enough space, for interrupts servicing, within its own stack. This space, - * multiplied by the total threads number, can amount to a significant RAM - * overhead. - * - Thread Stack, each thread has a dedicated stack for its own - * execution and context switch. - * - Other Stacks, some architectures (ARM) can have other stacks but - * the OS does not directly use any of them. - * . - *

Risks

- * The most critical thing when writing an embedded multithreaded application - * is to determine the correct stack size for main, threads and, when present, - * interrupts.
- * Assigning too much space to a stack is a waste of RAM, assigning too little - * space leads to crashes or, worst scenario, hard to track instability. - * - *

Assigning the correct size

- * You may try to examine the asm listings in order to calculate the exact - * stack requirements but this requires much time, experience and patience.
- * An alternative way is to use an interactive method. Follow this procedure - * for each thread in the system: - * - Enable the following debug options in the kernel: - * - @p CH_DBG_ENABLE_STACK_CHECK, this enables a stack check before any - * context switch. This option halts the system in @p chSysHalt() just - * before a stack overflow happens. The halt condition is caused by - * a stack overflow when the global variable @p panic_msg is set to - * @p NULL, normally it would point to a panic message. - * - @p CH_DBG_FILL_THREADS, this option fills the threads working area - * with an easily recognizable pattern (0x55). - * - Assign a large and safe size to the thread stack, as example 256 bytes - * on 32 MCUs, 128 bytes on 8/16 bit MCUs. This is almost always too much - * for simple threads. - * - Run the application, if the application crashes or halts then increase - * the stack size and repeat (you know how to use the debugger right?). - * - Let the application run and make sure to trigger the thread in a way to - * make it follow most or all its code paths. If the application crashes or - * halts then increase the stack size and repeat. - * - Stop the application using the debugger and examine the thread working - * area (you know what a map file is, right?). You can see that the thread - * stack overwrote the fill pattern (0x55) from the top of the working area - * downward. You can estimate the excess stack by counting the untouched - * locations. - * - Trim down the stack size and repeat until the application still runs - * correctly and you have a decent margin in the stack. - * - Repeat for all the thread classes in the system. - * - Turn off the debug options. - * - Done. - * . - *

Final Notes

- * Some useful info: - * - Stack overflows are the most common problems source during development, - * when in trouble with crashes or anomalous behaviors always first verify - * stack sizes. - * - The required stack size can, and very often does change when changing - * compiler vendor, compiler version, compiler options, code type (ARM - * or THUMB as example). - * - Code compiled in THUMB mode uses more stack space compared to the - * same code compiled in ARM mode. In GCC this is related to lack of tail - * calls optimizations in THUMB mode, this is probably true also in other - * compilers. - * - Speed optimized code often requires less stack space compared to space - * optimized code. Be careful when changing optimizations. - * - The interrupts space overhead on the thread stacks (@p INT_REQUIRED_STACK - * defined in @p chcore.h) is included in the total working area size - * by the system macros @p THD_WA_SIZE() and @p WORKING_AREA().
- * The correct way to reserve space into the thread stacks for interrupts - * processing is to override the @p INT_REQUIRED_STACK default value. - * Architectures with a dedicated interrupt stack do not require changes - * to this value. Resizing of the global interrupt stack may be required - * instead. - * - Often is a good idea to have some extra space in stacks unless you - * are really starved on RAM. Anyway, it is best to optimize stack space - * at the very end of your development cycle. - * . - */ diff --git a/ChibiOS_2.0.8/docs/src/stop_os.dox b/ChibiOS_2.0.8/docs/src/stop_os.dox deleted file mode 100644 index bc74b03..0000000 --- a/ChibiOS_2.0.8/docs/src/stop_os.dox +++ /dev/null @@ -1,140 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_stop_os How to cleanly stop the OS - * Stopping the OS should not be normally required but there are scenarios - * where one might want the complete control over the system again. - * As example entering into a bootload mode, or invoking some flashing - * algorithm locked in ROM.
- * ChibiOS/RT does not have a shutdown API and there is a reason for this, - * stopping the kernel would not be enough, a well defined operations sequence - * is required.
- * The shutdown operation should always be implemented into the @p main() - * function because in that context the stack pointer is guaranteed to be - * in the area allocated by the startup code. Stopping from a thread would - * leave the stack pointer "somewhere".
- * The shutdown sequence should include the following steps, some steps - * are optional and depend on the application: - * - Safely stop critical threads. As example a thread that uses a File System - * should flush all the modified buffers to the persistent storage before - * terminating.
- * The system should be designed to request the thread termination using - * @p chThdTerminate() and then wait its termination using @p chThdWait(). - * This phase can be skipped for non-critical threads. - * - Invoke the xxxStop() method on all the active device drivers, this - * disables the interrupt sources used by the various peripherals. This - * is required in order to not have interrupts after the shutdown that - * may invoke OS primitives. - * - Invoke chSysDisable(). - * - Stop the system timer whose service routine invokes - * @p chSysTimerHandlerI(). - * - Disable any other interrupt source that may invoke OS APIs. In general - * all the interrupt sources that have handlers declared by using the - * @p CH_IRQ_HANDLER() macro. - * - Perform any application related de-initialization. - * - Invoke chSysEnable(). - * . - * Now the OS is stopped and you can safely assume there are nothing going on - * under the hood. From here you can also restart the OS after finishing your - * critical operations using the following sequence: - * - Invoke chSysDisable(). - * - Restart the system timer. - * - Reinitialize the OS by invoking @p chSysInit(). - * - Restart your device drivers using the @p xxxStart() methods. - * - Restart all your threads. - * . - *

Example

- * This is an example of an hypothetical application that have to shutdown - * the OS when a certain event is generated. - * @code -#include "ch.h" -#include "hal.h" - -/* A shutdown flag.*/ -bool_t shutdown_required; - -/* Critical thread.*/ -static void my_thread(void *p) { - - while (!chThdShouldTerminate()) { - /* Normal thread activity code.*/ - } - /* Thread de-initialization before terminating, here you put the critical - thread finalization code.*/ - return 0; -} - -/* Main program, it is entered with interrupts disabled.*/ -void main(void) { - - /* HAL initialization, you need to do this just once.*/ - halInit(); - - /* Main loop, the main() function never exits.*/ - while (TRUE) { - Thread *tp; - - shutdown_required = FALSE; - - /* ChibiOS/RT initialization. This function becomes an OS thread.*/ - chSysInit(); - - /* Starting a device driver, SD2 in this case.*/ - sdStart(&SD2, NULL); - - /* Starting our critical thread.*/ - tp = chThdCreateFromHeap(NULL, THD_WA_SIZE(256), - NORMALPRIO, my_thread, &SD2); - - /* Main thread activity into a loop.*/ - while (!shutdown_required) { - /* Main activity, OS active until a shutdown becomes necessary.*/ - } - - /* Starting the shutdown sequence.*/ - chThdTerminate(tp); /* Requesting termination. */ - chThdWait(tp); /* Waiting for the actual termination. */ - sdStop(&SD2); /* Stopping serial port 2. */ - chSysDisable(); - stop_system_timer(); - stop_any_other_interrupt(); - chSysEnable(); - - /* Now the main function is again a normal function, no more a - OS thread.*/ - do_funny_stuff(); - - /* Restarting the OS but you could also stop the system or trigger a - reset instead.*/ - chSysDisable(); - } -} - * @endcode - * As you can see it is possible to jump in and out of the "OS mode" quite - * easily. Note that this is just an example, the real code could be very - * different depending on your requirements. - */ diff --git a/ChibiOS_2.0.8/docs/src/target.dox b/ChibiOS_2.0.8/docs/src/target.dox deleted file mode 100644 index 677c567..0000000 --- a/ChibiOS_2.0.8/docs/src/target.dox +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page target Application Range - * @brief ChibiOS/RT Application Range. - * - @ref applications - * - @ref min_requirements - * - @ref desirable_features - * - @ref upper_limit - * . - * @section applications Application Scenarios - * ChibiOS/RT is usable in many applicative areas, as example and not limited - * to: - * - Automotive. - * - Robotic Applications. - * - Consumer Electronics. - * - Energy Management. - * - Teaching and Learning. - * - Hobby. - * . - * @section min_requirements Absolute Minimum Requirements - * A certain set of minimum system requirements must be satisfied in order to - * use ChibiOS/RT on a new architecture: - * - 8bits architecture minimum. - * - A "real" stack pointer that can be positioned anywhere in the data address - * space. The OS could be ported to architectures with an hardware stack but - * I wouldn't recommend it because the context switch would become - * ridiculously inefficient. - * - Support for maskable interrupt sources and at least an OS-dedicated timer. - * - Support for standard C89 (C99 supported) language with no - * architecture-related non-standard restrictions. Non standard mandatory - * language extensions or restrictions may result in reduced functionality - * or impossibility of use. - * - 256/512bytes RAM permanently allocated to the kernel and its two mandatory - * threads "idle" and "main", the exact amount depends on the architecture. - * This figure is not inclusive of the HAL and device drivers (non mandatory - * components). - * - 8KiB of program space for a full featured kernel scalable down to about - * 1.2KiB for reduced configurations. This figure is not inclusive of the - * HAL and device drivers (non mandatory components). - * . - * @section desirable_features Desirable Features - * - Efficient instruction set for linked lists traversal. The kernel makes - * extensive use of simple and bidirectional linked lists so the performance - * is directly affected by the supported addressing modes, number of - * registers etc. - * - Uniformly sized C pointers. - * - 2KiB RAM. - * - 16KiB ROM/Flash. - * . - * @section upper_limit Upper Recommended Limit - * The application range of ChibiOS/RT ends when one or more of the following - * features are required: - * - Separation between user code space and kernel space, both just logical or - * using a Memory Management/Protection Unit. Applications in ChibiOS/RT are - * supposed to be monolithic and trusted. The kernel and the application - * share the same address space. - * - Multiple applications. ChibiOS/RT supports the single multithreaded - * application model. - * - Multicore SMP architectures. Currently ChibiOS/RT only supports a single - * core unless running multiple distinct and separate OS instances. - * A true multicore kernel is planned for when multicore MCUs will become - * commonly available. - * . - */ diff --git a/ChibiOS_2.0.8/docs/src/timing.dox b/ChibiOS_2.0.8/docs/src/timing.dox deleted file mode 100644 index 721b164..0000000 --- a/ChibiOS_2.0.8/docs/src/timing.dox +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_timing Reliable timings using Threads - * One common task is to have threads do something at regular, scheduled, - * intervals. - * An obvious solution is to write something like this: - * @code -msg_t my_thread(void *param) { - - while (TRUE) { - do_something(); - chThdSleepMilliseconds(1000); // Fixed interval - } -} - * @endcode - * This example works well assuming that the @p do_something() execution time - * is well below the system tick period and that @p my_thread() is not - * preempted by other threads that could insert long intervals.
- * If the above conditions are not satisfied you may have @p do_something() - * executed at irregular intervals, as example:

- * T0...T0+1000...T0+2002...T0+3002...T0+4005...etc.

- * Also note that the error increases over time and this kind of behavior can - * lead to anomalies really hard to debug. - *

A better solution

- * It is possible to rewrite the above code using absolute deadlines rather - * than fixed intervals: - * @code -msg_t my_thread(void *param) { - - systick_t time = chTimeNow(); // T0 - while (TRUE) { - time += MS2ST(1000); // Next deadline - do_something(); - chThdSleepUntil(time); - } -} - * @endcode - * Using this code @p do_something() will always be executed at an absolute - * deadline time and the error will not accumulate over time regardless of - * the execution time and delays inserted by other threads.
- * Note that this solution requires that the @p do_something() execution - * time must not exceed the deadline or the thread would stay sleeping into - * @p chThdSleepUntil(). - * - *

A different way

- * Another way to perform activities at regular intervals is the use of a - * virtual timer. Virtual timers are able to generate callbacks at scheduled - * intervals. Virtual timers are one shot timers so you need to restart them - * from within the callback if you need a periodic timer like in this case. - * @code -VirtualTimer vt; - -void do_something(void *p) { - - chVTSetI(&vt, MS2ST(1000), do_something, p); // Restarts the timer. - // Periodic code here. -} - -int main(int argc, char **argv) { - - chSysLock(); - chVTSetI(&vt, MS2ST(1000), do_something, NULL); // Starts the timer. - chSysUnlock(); - ... -} - * @endcode - * Note that the callback code is executed from within the I-Locked state (see - * @ref system_states) so you can only execute I-Class APIs from there (see - * @ref api_suffixes).
- * This solution has the advantage to not require a dedicated thread and - * thus uses much less RAM but the periodic code must have a very short - * execution time or it would degrade the overall system response time. - */ diff --git a/ChibiOS_2.0.8/docs/src/wakeup.dox b/ChibiOS_2.0.8/docs/src/wakeup.dox deleted file mode 100644 index 42777cc..0000000 --- a/ChibiOS_2.0.8/docs/src/wakeup.dox +++ /dev/null @@ -1,155 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @page article_wakeup How to wake up a thread from an interrupt handler - * Waking up a thread after an hardware event is one of the most common tasks - * that an RTOS must be able to perform efficiently. In ChibiOS/RT there are - * several mechanisms that can be used, often each mechanism is best suited - * in a specific scenario. - * - *

Synchronously waking up a specific thread

- * A common situation is to have to synchronously wake up a specific thread. - * This can be accomplished without the use of any specific synchronization - * primitive, it uses the very efficient low level scheduler APIs, note that - * you can also optionally send a simple message from the IRQ handler to - * the thread. - * @code -static Thread *tp = NULL; - -void mythread(void *p) { - - while (TRUE) { - msg_t msg; - - // Waiting for the IRQ to happen. - chSysLock(); - tp = chThdSelf(); - chSchGoSleepS(PRSUSPENDED); - msg = chThdSelf()->p_rdymsg; // Retrieving the message, optional - chSysUnlock(); - // Perform processing here. - } -} - -CH_IRQ_HANDLER(myIRQ) { - CH_IRQ_PROLOGUE(); - - // Wakes up the thread. - chSysLockFromIsr(); - if (tp != NULL) { - tp->p_rdymsg = (msg_t)55; // Sending the message, optional - chSchReadyI(tp); - tp = NULL; - } - chSysUnlockFromIsr(). - - CH_IRQ_EPILOGUE(); -} - * @endcode - * - *

Synchronously waking up one of the waiting threads

- * Lets assume you have a queue of waiting threads, you want to wake up - * the threads one by one in FIFO order, if there are no waiting threads - * then nothing happens.
- * This can be accomplished using a @p Semaphore object initialized to zero: - * @code -CH_IRQ_HANDLER(myIRQ) { - CH_IRQ_PROLOGUE(); - - // If there is at least one waiting thread then signal it. - chSysLockFromIsr(); - if (chSemGetCounterI(&mysem) < 0) - chSemSignalI(&mysem); - chSysUnlockFromIsr(). - - CH_IRQ_EPILOGUE(); -} - * @endcode - * - *

Synchronously waking up all the waiting threads

- * In this scenario you want to synchronously wake up all the waiting threads, - * if there are no waiting threads then nothing happens.
- * This can be accomplished using a @p Semaphore object initialized to zero: - * @code -CH_IRQ_HANDLER(myIRQ) { - CH_IRQ_PROLOGUE(); - - // Wakes up all the threads waiting on the semaphore. - chSysLockFromIsr(); - chSemResetI(&mysem); - chSysUnlockFromIsr(). - - CH_IRQ_EPILOGUE(); -} - * @endcode - * - *

Asynchronously waking up a specific thread

- * If you have to asynchronously wake up a specific thread then a simple - * event flags can be used. - * @code -static Thread *tp; - -void mythread(void *p) { - - tp = chThdSelf(); - while (TRUE) { - // Checks if an IRQ happened else wait. - chEvtWaitAny((eventmask_t)1); - // Perform processing here. - } -} - -CH_IRQ_HANDLER(myIRQ) { - CH_IRQ_PROLOGUE(); - - // Wakes up the thread. - chSysLockFromIsr(); - chEvtSignalI(tp, (eventmask_t)1); - chSysUnlockFromIsr(). - - CH_IRQ_EPILOGUE(); -} - * @endcode - * - *

Asynchronously waking up one or more threads

- * By using event sources it is possible to asynchronously wake up one or more - * listener threads. The mechanism requires a single initialized - * @p EventSource object, all the threads registered as listeners on the - * event source will be broadcasted. - * @code -CH_IRQ_HANDLER(myIRQ) { - CH_IRQ_PROLOGUE(); - - // Pends an event flag on all the listening threads. - chSysLockFromIsr(); - chEvtBroadcastI(&my_event_source); - chSysUnlockFromIsr(). - - CH_IRQ_EPILOGUE(); -} - * @endcode - */ diff --git a/ChibiOS_2.0.8/exception.txt b/ChibiOS_2.0.8/exception.txt deleted file mode 100644 index 30ce186..0000000 --- a/ChibiOS_2.0.8/exception.txt +++ /dev/null @@ -1,54 +0,0 @@ - GPL Exception Text - - In addition, as a special exception, the copyright holder of ChibiOS/RT, -gives You the additional right to link the unmodified code of this Program with -code not covered under the GNU General Public License ("Non-GPL Code") and to -distribute linked combinations including the two, subject to the limitations -in this paragraph. - - 1. Non-GPL Code permitted under this exception must only link to the - unmodified code of this Program through those well defined interfaces - identified as "Approved Interfaces". - 2. Every copy of the combined work is accompanied by a written statement - that details to the recipient the version of ChibiOS/RT used and an - offer by yourself to provide the ChibiOS/RT source code should the - recipient request it. - 3. The combined work is not itself an RTOS, scheduler, kernel or related - product. - 4. The combined work is not itself a binary library intended for linking - into other software applications. - - The Approved Interfaces - - 1. The files of Non-GPL Code may include the unmodified ChibiOS/RT - distribution header files contained under: - ./os/kernel/include - ./os/hal/include - ./os/hal/platforms - ./os/various - without causing the resulting work to be covered by the GNU General - Public License. - 2. The files of Non-GPL Code may link to the unmodified ChibiOS/RT - distribution files contained under: - ./os/kernel/src - ./os/hal/src - ./os/hal/platforms - ./os/various - without causing the resulting work to be covered by the GNU General - Public License. - 3. The files of Non-GPL Code may link to, or include, the modified or - unmodified ChibiOS/RT distribution files contained under: - ./os/kernel/templates - ./os/hal/templates - ./os/ports - ./boards - ./demos - without causing the resulting work to be covered by the GNU General - Public License. - - Only the copyright holder of ChibiOS/RT may make changes or additions to the -list of Approved Interfaces. - - You must obey the GNU General Public License in all respects for all of the -Program code and other code used in conjunction with the Program except the -Non-GPL Code covered by this exception. diff --git a/ChibiOS_2.0.8/ext/ext.dox b/ChibiOS_2.0.8/ext/ext.dox deleted file mode 100644 index 6e07d87..0000000 --- a/ChibiOS_2.0.8/ext/ext.dox +++ /dev/null @@ -1,45 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup external External Components - * ChibiOS/RT supports several external libraries through support interfaces - * and/or demos. Credit should be given to the original authors for making - * available such useful code.
- * The current list of supported component is: - * - uIP, by Adam Dunkels at the Swedish Institute of Computer Science, - * link. - * - lwIP, many authors, - * link. - * - FatFs, by "ChaN", - * link. - * . - * External components and libraries are not directly supported and are used - * "as is" or with minor integration patching. - */ diff --git a/ChibiOS_2.0.8/ext/ff007e-patched.zip b/ChibiOS_2.0.8/ext/ff007e-patched.zip deleted file mode 100644 index e6aab7a..0000000 Binary files a/ChibiOS_2.0.8/ext/ff007e-patched.zip and /dev/null differ diff --git a/ChibiOS_2.0.8/ext/lwip-1.3.1.zip b/ChibiOS_2.0.8/ext/lwip-1.3.1.zip deleted file mode 100644 index 00a18df..0000000 Binary files a/ChibiOS_2.0.8/ext/lwip-1.3.1.zip and /dev/null differ diff --git a/ChibiOS_2.0.8/ext/readme.txt b/ChibiOS_2.0.8/ext/readme.txt deleted file mode 100644 index d9573d8..0000000 --- a/ChibiOS_2.0.8/ext/readme.txt +++ /dev/null @@ -1,32 +0,0 @@ -***************************************************************************** -** External Libraries. ** -***************************************************************************** - -The libraries under this directory are not part of ChibiOS/RT but are used by -some of the demo applications. -Please note that each item is covered by its own license, please read the -instructions contained in the various distributions. - -The currently included items are: - -1. uip-1.0, a minimal TCP/IP implementation: http://www.sics.se/~adam/uip/ -2. lwip-1.3.1, lightweight TCP/IP stack: http://savannah.nongnu.org/projects/lwip/ -3. STM32 firmware library 3.3.0 (partial, library only) the full download is - available from http://www.st.com -4. FatFS 0.7e (patched), the original version is available from - http://elm-chan.org/fsw/ff/00index_e.html - -The above files are included packed as downloaded from the original repository -and without any modification, in order to use the libraries unpack them -under ./ext as: - -./ext/uip-1.0 -./ext/lwip -./ext/stm32lib -./ext/fatfs - -Some patches are also present: - -1. uip-1.0 patches, small fixes to the uIP required to make it work with - ChibiOS/RT, unpack the archive over the uIP distribution and replace the - files. diff --git a/ChibiOS_2.0.8/ext/stm32lib-3.3.0.zip b/ChibiOS_2.0.8/ext/stm32lib-3.3.0.zip deleted file mode 100644 index e920c27..0000000 Binary files a/ChibiOS_2.0.8/ext/stm32lib-3.3.0.zip and /dev/null differ diff --git a/ChibiOS_2.0.8/ext/uip-1.0.patches.zip b/ChibiOS_2.0.8/ext/uip-1.0.patches.zip deleted file mode 100644 index bdff1db..0000000 Binary files a/ChibiOS_2.0.8/ext/uip-1.0.patches.zip and /dev/null differ diff --git a/ChibiOS_2.0.8/ext/uip-1.0.tar.gz b/ChibiOS_2.0.8/ext/uip-1.0.tar.gz deleted file mode 100644 index d5530ec..0000000 Binary files a/ChibiOS_2.0.8/ext/uip-1.0.tar.gz and /dev/null differ diff --git a/ChibiOS_2.0.8/license.txt b/ChibiOS_2.0.8/license.txt deleted file mode 100644 index 94a9ed0..0000000 --- a/ChibiOS_2.0.8/license.txt +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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If not, see . - -Also add information on how to contact you by electronic and paper mail. - - If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - - Copyright (C) - This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an "about box". - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU GPL, see -. - - The GNU General Public License does not permit incorporating your program -into proprietary programs. If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/ChibiOS_2.0.8/os/hal/hal.dox b/ChibiOS_2.0.8/os/hal/hal.dox deleted file mode 100644 index 03df8d8..0000000 --- a/ChibiOS_2.0.8/os/hal/hal.dox +++ /dev/null @@ -1,404 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup IO HAL - * @brief Hardware Abstraction Layer. - * @details Under ChibiOS/RT the set of the various device driver interfaces - * is called the HAL subsystem: Hardware Abstraction Layer.
- * A device driver is usually split in two layers: - * - High Level Device Driver (HLD). This layer contains the definitions - * of the driver's APIs and the platform independent part of the driver.
- * An HLD is composed by two files: - * - @.c, the HLD implementation file. This file must be - * included in the Makefile in order to use the driver. - * - @.h, the HLD header file. This file is implicitly - * included by the HAL header file @p hal.h. - * . - * - Low Level Device Driver (LLD). This layer contains the platform - * dependent part of the driver.
- * A LLD is composed by two files: - * - @_lld.c, the LLD implementation file. This file must be - * included in the Makefile in order to use the driver. - * - @_lld.h, the LLD header file. This file is implicitly - * included by the HLD header file. - * . - * The LLD may be not present in those drivers that do not access the - * hardware directly but through other device drivers, as example the - * @ref MMC_SPI driver uses the @ref SPI and @ref PAL drivers in order - * to implement its functionalities. - * . - *

Available Device Drivers

- * The I/O subsystem currently includes support for: - * - @ref HAL. - * - @ref PAL. - * - @ref SERIAL. - * - @ref ADC. - * - @ref CAN. - * - @ref MAC. - * - @ref MMC_SPI. - * - @ref SPI. - * . - */ - -/** - * @defgroup HAL HAL Driver - * @brief Hardware Abstraction Layer. - * @details The HAL driver performs the system initialization and includes - * the platform support code shared by the other drivers. - * - * @ingroup IO - */ - -/** - * @defgroup HAL_LLD HAL Low Level Driver - * @brief @ref HAL low level driver template. - * - * @ingroup HAL - */ - -/** - * @defgroup HAL_CONF Configuration - * @brief @ref HAL Configuration. - * - * @ingroup HAL - */ - -/** - * @defgroup PAL PAL Driver - * @brief I/O Ports Abstraction Layer - * @details This module defines an abstract interface for digital I/O ports. - * Note that most I/O ports functions are just macros. The macros - * have default software implementations that can be redefined in a - * @ref PAL_LLD if the target hardware supports special features like, as - * example, atomic bit set/reset/masking. Please refer to the ports specific - * documentation for details.
- * The @ref PAL has the advantage to make the access to the I/O ports platform - * independent and still be optimized for the specific architectures.
- * Note that the @ref PAL_LLD may also offer non standard macro and functions - * in order to support specific features but, of course, the use of such - * interfaces would not be portable. Such interfaces shall be marked with - * the architecture name inside the function names. - * - *

Implementation Rules

- * In implementing an @ref PAL_LLD there are some rules/behaviors that - * should be respected. - * - *

Writing on input pads

- * The behavior is not specified but there are implementations better than - * others, this is the list of possible implementations, preferred options - * are on top: - * -# The written value is not actually output but latched, should the pads - * be reprogrammed as outputs the value would be in effect. - * -# The write operation is ignored. - * -# The write operation has side effects, as example disabling/enabling - * pull up/down resistors or changing the pad direction. This scenario is - * discouraged, please try to avoid this scenario. - * . - *

Reading from output pads

- * The behavior is not specified but there are implementations better than - * others, this is the list of possible implementations, preferred options - * are on top: - * -# The actual pads states are read (not the output latch). - * -# The output latch value is read (regardless of the actual pads states). - * -# Unspecified, please try to avoid this scenario. - * . - *

Writing unused or unimplemented port bits

- * The behavior is not specified. - * - *

Reading from unused or unimplemented port bits

- * The behavior is not specified. - * - *

Reading or writing on pins associated to other functionalities

- * The behavior is not specified. - * - *

Usage

- * The use of I/O ports requires the inclusion of the header file @p pal.h, - * this file is not automatically included @p ch.h like the other header - * files. - * - * @ingroup IO - */ - -/** - * @defgroup PAL_LLD PAL Low Level Driver - * @brief @ref PAL low level driver template. - * @details This file is a template for an I/O port low level driver. - * - * @ingroup PAL - */ - -/** - * @defgroup SERIAL Serial Driver - * @brief Generic Serial Driver. - * @details This module implements a generic full duplex serial driver. The - * driver implements a @p SerialDriver interface and uses I/O Queues for - * communication between the upper and the lower driver. Event flags are used - * to notify the application about incoming data, outgoing data and other I/O - * events.
- * The module also contains functions that make the implementation of the - * interrupt service routines much easier. - * - * @ingroup IO - */ - -/** - * @defgroup SERIAL_LLD Serial Low Level Driver - * @brief @ref SERIAL low level driver template. - * @details This file is a template for a serial low level driver. - * - * @ingroup SERIAL - */ - -/** - * @defgroup SPI SPI Driver - * @brief Generic SPI Driver. - * @details This module implements a generic SPI driver. The driver implements - * a state machine internally: - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.8", height="0.8"]; - edge [fontname=Helvetica, fontsize=8]; - uninit [label="SPI_UNINIT", style="bold"]; - stop [label="SPI_STOP\nLow Power"]; - ready [label="SPI_READY\nClock Enabled"]; - active [label="SPI_ACTIVE\nBus Active"]; - uninit -> stop [label="spiInit()"]; - stop -> ready [label="spiStart()"]; - ready -> ready [label="spiStart()"]; - ready -> ready [label="spiIgnore()"]; - ready -> stop [label="spiStop()"]; - stop -> stop [label="spiStop()"]; - ready -> active [label="spiSelect()"]; - active -> active [label="spiSelect()"]; - active -> ready [label="spiUnselect()"]; - ready -> ready [label="spiUnselect()"]; - active -> active [label="spiIgnore()\nspiExchange()\nspiSend()\nspiReceive()"]; - } - * @enddot - * - * The driver is not thread safe for performance reasons, if you need to access - * the SPI bus from multiple thread then use the @p spiAcquireBus() and - * @p spiReleaseBus() APIs in order to gain exclusive access. - * - * @ingroup IO - */ - -/** - * @defgroup SPI_LLD SPI Low Level Driver - * @brief @ref SPI low level driver template. - * @details This file is a template for a SPI low level driver. - * - * @ingroup SPI - */ - -/** - * @defgroup ADC ADC Driver - * @brief Generic ADC Driver. - * @details This module implements a generic ADC driver. The driver implements - * a state machine internally: - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.8", height="0.8"]; - edge [fontname=Helvetica, fontsize=8]; - uninit [label="ADC_UNINIT", style="bold"]; - stop [label="ADC_STOP\nLow Power"]; - ready [label="ADC_READY\nClock Enabled"]; - running [label="ADC_RUNNING"]; - complete [label="ADC_COMPLETE"]; - uninit -> stop [label="adcInit()"]; - stop -> ready [label="adcStart()"]; - ready -> ready [label="adcStart()"]; - ready -> ready [label="adcWaitConversion()"]; - ready -> stop [label="adcStop()"]; - stop -> stop [label="adcStop()"]; - ready -> running [label="adcStartConversion()"]; - running -> ready [label="adcStopConversion()"]; - running -> complete [label="End of Conversion"]; - complete -> running [label="adcStartConversion()"]; - complete -> ready [label="adcStopConversion()"]; - complete -> ready [label="adcWaitConversion()"]; - complete -> stop [label="adcStop()"]; - } - * @enddot - * - * The driver supports a continuous conversion mode with circular buffer, - * callback functions allow to process the converted data in real time. - * Please refer to the documentation of the function @p adcStartConversion(). - * - * @ingroup IO - */ - -/** - * @defgroup ADC_LLD ADC Low Level Driver - * @brief @ref ADC low level driver template. - * @details This file is a template for a ADC low level driver. - * - * @ingroup ADC - */ - -/** - * @defgroup CAN CAN Driver - * @brief Generic CAN Driver. - * @details This module implements a generic ADC driver. The driver implements - * a state machine internally: - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.8", height="0.8"]; - edge [fontname=Helvetica, fontsize=8]; - uninit [label="CAN_UNINIT", style="bold"]; - stop [label="CAN_STOP\nLow Power"]; - ready [label="CAN_READY\nClock Enabled"]; - sleep [label="CAN_SLEEP\nLow Power"]; - uninit -> stop [label="canInit()"]; - stop -> stop [label="canStop()"]; - stop -> ready [label="canStart()"]; - ready -> stop [label="canStop()"]; - ready -> ready [label="canReceive()\ncanTransmit()"]; - ready -> ready [label="canStart()"]; - ready -> sleep [label="canSleep()"]; - sleep -> sleep [label="canSleep()"]; - sleep -> ready [label="canWakeup()"]; - sleep -> ready [label="wakeup event"]; - } - * @enddot - * - * @ingroup IO - */ - -/** - * @defgroup CAN_LLD CAN Low Level Driver - * @brief @ref CAN low level driver template. - * - * @ingroup CAN - */ - -/** - * @defgroup PWM PWM Driver - * @brief Generic PWM Driver. - * @details This module implements a generic PWM driver. The driver implements - * a state machine internally: - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.8", height="0.8"]; - edge [fontname=Helvetica, fontsize=8]; - uninit [label="PWM_UNINIT", style="bold"]; - stop [label="PWM_STOP\nLow Power"]; - ready [label="PWM_READY\nClock Enabled"]; - uninit -> stop [label="pwmInit()"]; - stop -> stop [label="pwmStop()"]; - stop -> ready [label="pwmStart()"]; - ready -> stop [label="pwmStop()"]; - ready -> ready [label="pwmEnableChannel()\npwmDisableChannel()"]; - } - * @enddot - * - * @ingroup IO - */ - -/** - * @defgroup PWM_LLD PWM Low Level Driver - * @brief @ref PWM low level driver template. - * - * @ingroup PWM - */ - -/** - * @defgroup MAC MAC Driver - * @brief Generic MAC driver. - * @details This module implements a generic interface for MAC (Media - * Access Control) drivers, as example Ethernet controllers. - * - * @ingroup IO - */ - -/** - * @defgroup MAC_LLD MAC Low Level Driver - * @brief @ref MAC low level driver template. - * @details This file is a template for a MAC low level driver. - * - * @ingroup MAC - */ - -/** - * @defgroup MMC_SPI MMC over SPI Driver - * @brief Generic MMC driver. - * @details This module implements a portable MMC driver that uses a SPI - * driver as physical layer.
- * The driver implements the following state machine: - * @dot - digraph example { - rankdir="LR"; - node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.8", height="0.8"]; - edge [fontname=Helvetica, fontsize=8]; - - any [label="Any State"]; - stop2 [label="MMC_STOP\nLow Power"]; - uninit [label="MMC_UNINIT", style="bold"]; - stop [label="MMC_STOP\nLow Power"]; - wait [label="MMC_WAIT\nWaiting Card"]; - inserted [label="MMC_INSERTED\nCard Inserted"]; - ready [label="MMC_READY\nCard Ready"]; - reading [label="MMC_READING\nReading"]; - writing [label="MMC_WRITING\nWriting"]; - - uninit -> stop [label="mmcInit()"]; - stop -> wait [label="mmcStart()", constraint=false]; - wait -> inserted [label="insertion (inserted event)"]; - inserted -> inserted [label="mmcDisconnect()"]; - inserted -> ready [label="mmcConnect()"]; - ready -> ready [label="mmcConnect()"]; - ready -> inserted [label="mmcDisconnect()"]; - ready -> reading [label="mmcStartSequentialRead()"]; - reading -> reading [label="mmcSequentialRead()"]; - reading -> ready [label="mmcStopSequentialRead()"]; - reading -> ready [label="read error"]; - ready -> writing [label="mmcStartSequentialWrite()"]; - writing -> writing [label="mmcSequentialWrite()"]; - writing -> ready [label="mmcStopSequentialWrite()"]; - writing -> ready [label="write error"]; - - inserted -> wait [label="removal (removed event)"]; - ready -> wait [label="removal (removed event)"]; - reading -> wait [label="removal (removed event)"]; - writing -> wait [label="removal (removed event)"]; - - any -> stop2 [label="mmcStop()"]; - } - * @enddot - * - * The MMC drivers currently supports only cards with capacity up to 2GB - * and does not implement CRC checking. Hot plugging and removal are supported - * through kernel events. - * - * @ingroup IO - */ - - diff --git a/ChibiOS_2.0.8/os/hal/hal.mk b/ChibiOS_2.0.8/os/hal/hal.mk deleted file mode 100644 index 4ff7e83..0000000 --- a/ChibiOS_2.0.8/os/hal/hal.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of all the ChibiOS/RT HAL files, there is no need to remove the files -# from this list, you can disable parts of the kernel by editing halconf.h. -HALSRC = ${CHIBIOS}/os/hal/src/hal.c \ - ${CHIBIOS}/os/hal/src/adc.c \ - ${CHIBIOS}/os/hal/src/can.c \ - ${CHIBIOS}/os/hal/src/mac.c \ - ${CHIBIOS}/os/hal/src/pal.c \ - ${CHIBIOS}/os/hal/src/pwm.c \ - ${CHIBIOS}/os/hal/src/serial.c \ - ${CHIBIOS}/os/hal/src/spi.c \ - ${CHIBIOS}/os/hal/src/mmc_spi.c - -# Required include directories -HALINC = ${CHIBIOS}/os/hal/include diff --git a/ChibiOS_2.0.8/os/hal/include/adc.h b/ChibiOS_2.0.8/os/hal/include/adc.h deleted file mode 100644 index 127b546..0000000 --- a/ChibiOS_2.0.8/os/hal/include/adc.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file adc.h - * @brief ADC Driver macros and structures. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_H_ -#define _ADC_H_ - -#if CH_HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_USE_SEMAPHORES -#error "ADC driver requires CH_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - ADC_UNINIT = 0, /**< @brief Not initialized. */ - ADC_STOP = 1, /**< @brief Stopped. */ - ADC_READY = 2, /**< @brief Ready. */ - ADC_RUNNING = 3, /**< @brief Conversion running. */ - ADC_COMPLETE = 4 /**< @brief Conversion complete.*/ -} adcstate_t; - -#include "adc_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void adcInit(void); - void adcObjectInit(ADCDriver *adcp); - void adcStart(ADCDriver *adcp, const ADCConfig *config); - void adcStop(ADCDriver *adcp); - bool_t adcStartConversion(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth, - adccallback_t callback); - void adcStopConversion(ADCDriver *adcp); - msg_t adcWaitConversion(ADCDriver *adcp, systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_ADC */ - -#endif /* _ADC_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/can.h b/ChibiOS_2.0.8/os/hal/include/can.h deleted file mode 100644 index 6041615..0000000 --- a/ChibiOS_2.0.8/os/hal/include/can.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file can.h - * @brief CAN Driver macros and structures. - * - * @addtogroup CAN - * @{ - */ - -#ifndef _CAN_H_ -#define _CAN_H_ - -#if CH_HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Errors rate warning. - */ -#define CAN_LIMIT_WARNING 1 -/** - * @brief Errors rate error. - */ -#define CAN_LIMIT_ERROR 2 -/** - * @brief Bus off condition reached. - */ -#define CAN_BUS_OFF_ERROR 4 -/** - * @brief Framing error of some kind on the CAN bus. - */ -#define CAN_FRAMING_ERROR 8 -/** - * @brief Overflow in receive queue. - */ -#define CAN_OVERFLOW_ERROR 16 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS -#error "CAN driver requires CH_USE_SEMAPHORES and CH_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - CAN_UNINIT = 0, /**< @brief Not initialized. */ - CAN_STOP = 1, /**< @brief Stopped. */ - CAN_STARTING = 2, /**< @brief Starting. */ - CAN_READY = 3, /**< @brief Ready. */ - CAN_SLEEP = 4 /**< @brief Sleep state. */ -} canstate_t; - -#include "can_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Adds some flags to the CAN status mask. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] mask flags to be added to the status mask - */ -#define canAddFlagsI(canp, mask) ((canp)->cd_status |= (mask)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void canInit(void); - void canObjectInit(CANDriver *canp); - void canStart(CANDriver *canp, const CANConfig *config); - void canStop(CANDriver *canp); - msg_t canTransmit(CANDriver *canp, const CANTxFrame *ctfp, systime_t timeout); - msg_t canReceive(CANDriver *canp, CANRxFrame *crfp, systime_t timeout); - canstatus_t canGetAndClearFlags(CANDriver *canp); -#if CAN_USE_SLEEP_MODE - void canSleep(CANDriver *canp); - void canWakeup(CANDriver *canp); -#endif /* CAN_USE_SLEEP_MODE */ -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_CAN */ - -#endif /* _CAN_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/hal.h b/ChibiOS_2.0.8/os/hal/include/hal.h deleted file mode 100644 index c912ab0..0000000 --- a/ChibiOS_2.0.8/os/hal/include/hal.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file hal.h - * @brief HAL subsystem header. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_H_ -#define _HAL_H_ - -#include "board.h" -#include "halconf.h" - -#include "hal_lld.h" - -#include "pal.h" -#include "adc.h" -#include "can.h" -#include "mac.h" -#include "pwm.h" -#include "serial.h" -#include "spi.h" -#include "mmc_spi.h" - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void halInit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/mac.h b/ChibiOS_2.0.8/os/hal/include/mac.h deleted file mode 100644 index d6942ee..0000000 --- a/ChibiOS_2.0.8/os/hal/include/mac.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mac.h - * @brief MAC Driver macros and structures. - * @addtogroup MAC - * @{ - */ - -#ifndef _MAC_H_ -#define _MAC_H_ - -#if CH_HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS -#error "the MAC driver requires CH_USE_SEMAPHORES and CH_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -#include "mac_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the received frames event source. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The pointer to the @p EventSource structure. - */ -#if CH_USE_EVENTS || defined(__DOXYGEN__) -#define macGetReceiveEventSource(macp) (&(macp)->md_rdevent) -#endif - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum frame - * size is reached. - */ -#define macWriteTransmitDescriptor(tdp, buf, size) \ - mac_lld_write_transmit_descriptor(tdp, buf, size) - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's stream, this - * value can be less than the amount specified in the - * parameter @p size if there are no more bytes to read. - */ -#define macReadReceiveDescriptor(rdp, buf, size) \ - mac_lld_read_receive_descriptor(rdp, buf, size) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void macInit(void); - void macObjectInit(MACDriver *macp); - void macSetAddress(MACDriver *macp, const uint8_t *p); - msg_t macWaitTransmitDescriptor(MACDriver *macp, - MACTransmitDescriptor *tdp, - systime_t time); - void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp); - msg_t macWaitReceiveDescriptor(MACDriver *macp, - MACReceiveDescriptor *rdp, - systime_t time); - void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp); - bool_t macPollLinkStatus(MACDriver *macp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_MAC */ - -#endif /* _MAC_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/mii.h b/ChibiOS_2.0.8/os/hal/include/mii.h deleted file mode 100644 index c6824b7..0000000 --- a/ChibiOS_2.0.8/os/hal/include/mii.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * Parts of this file are borrowed by the Linux include file linux/mii.h: - * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) - */ - -/*-* - * @file mii.h - * @brief MII Driver macros and structures. - * - * @addtogroup MII - * @{ - */ - -#ifndef _MII_H_ -#define _MII_H_ - -/* - * Generic MII registers. Note, not all registers are present on all PHY - * devices and some extra registers may be present. - */ -#define MII_BMCR 0x00 /**< Basic mode control register. */ -#define MII_BMSR 0x01 /**< Basic mode status register. */ -#define MII_PHYSID1 0x02 /**< PHYS ID 1. */ -#define MII_PHYSID2 0x03 /**< PHYS ID 2. */ -#define MII_ADVERTISE 0x04 /**< Advertisement control reg. */ -#define MII_LPA 0x05 /**< Link partner ability reg. */ -#define MII_EXPANSION 0x06 /**< Expansion register. */ -#define MII_CTRL1000 0x09 /**< 1000BASE-T control. */ -#define MII_STAT1000 0x0a /**< 1000BASE-T status. */ -#define MII_ESTATUS 0x0f /**< Extended Status. */ -#define MII_DCOUNTER 0x12 /**< Disconnect counter. */ -#define MII_FCSCOUNTER 0x13 /**< False carrier counter. */ -#define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */ -#define MII_RERRCOUNTER 0x15 /**< Receive error counter. */ -#define MII_SREVISION 0x16 /**< Silicon revision. */ -#define MII_RESV1 0x17 /**< Reserved. */ -#define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */ -#define MII_PHYADDR 0x19 /**< PHY address. */ -#define MII_RESV2 0x1a /**< Reserved. */ -#define MII_TPISTATUS 0x1b /**< TPI status for 10mbps. */ -#define MII_NCONFIG 0x1c /**< Network interface config. */ - -/* - * Basic mode control register. - */ -#define BMCR_RESV 0x003f /**< Unused. */ -#define BMCR_SPEED1000 0x0040 /**< MSB of Speed (1000). */ -#define BMCR_CTST 0x0080 /**< Collision test. */ -#define BMCR_FULLDPLX 0x0100 /**< Full duplex. */ -#define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */ -#define BMCR_ISOLATE 0x0400 /**< Disconnect DP83840 from MII. */ -#define BMCR_PDOWN 0x0800 /**< Powerdown. */ -#define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */ -#define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */ -#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bits. */ -#define BMCR_RESET 0x8000 /**< Reset. */ - -/* - * Basic mode status register. - */ -#define BMSR_ERCAP 0x0001 /**< Ext-reg capability. */ -#define BMSR_JCD 0x0002 /**< Jabber detected. */ -#define BMSR_LSTATUS 0x0004 /**< Link status. */ -#define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */ -#define BMSR_RFAULT 0x0010 /**< Remote fault detected. */ -#define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */ -#define BMSR_RESV 0x00c0 /**< Unused. */ -#define BMSR_ESTATEN 0x0100 /**< Extended Status in R15. */ -#define BMSR_100HALF2 0x0200 /**< Can do 100BASE-T2 HDX. */ -#define BMSR_100FULL2 0x0400 /**< Can do 100BASE-T2 FDX. */ -#define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */ -#define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */ -#define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */ -#define BMSR_100FULL 0x4000 /**< Can do 100mbps, full-duplex. */ -#define BMSR_100BASE4 0x8000 /**< Can do 100mbps, 4k packets. */ - -/* - * Advertisement control register. - */ -#define ADVERTISE_SLCT 0x001f /**< Selector bits. */ -#define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */ -#define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */ -#define ADVERTISE_1000XFULL 0x0020 /**< Try for 1000BASE-X full-duplex.*/ -#define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */ -#define ADVERTISE_1000XHALF 0x0040 /**< Try for 1000BASE-X half-duplex.*/ -#define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */ -#define ADVERTISE_1000XPAUSE 0x0080 /**< Try for 1000BASE-X pause. */ -#define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */ -#define ADVERTISE_1000XPSE_ASYM 0x0100 /**< Try for 1000BASE-X asym pause. */ -#define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */ -#define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */ -#define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */ -#define ADVERTISE_RESV 0x1000 /**< Unused. */ -#define ADVERTISE_RFAULT 0x2000 /**< Say we can detect faults. */ -#define ADVERTISE_LPACK 0x4000 /**< Ack link partners response. */ -#define ADVERTISE_NPAGE 0x8000 /**< Next page bit. */ - -#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) -#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) - -/* - * Link partner ability register. - */ -#define LPA_SLCT 0x001f /**< Same as advertise selector. */ -#define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */ -#define LPA_1000XFULL 0x0020 /**< Can do 1000BASE-X full-duplex. */ -#define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */ -#define LPA_1000XHALF 0x0040 /**< Can do 1000BASE-X half-duplex. */ -#define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */ -#define LPA_1000XPAUSE 0x0080 /**< Can do 1000BASE-X pause. */ -#define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */ -#define LPA_1000XPAUSE_ASYM 0x0100 /**< Can do 1000BASE-X pause asym. */ -#define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */ -#define LPA_PAUSE_CAP 0x0400 /**< Can pause. */ -#define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */ -#define LPA_RESV 0x1000 /**< Unused. */ -#define LPA_RFAULT 0x2000 /**< Link partner faulted. */ -#define LPA_LPACK 0x4000 /**< Link partner acked us. */ -#define LPA_NPAGE 0x8000 /**< Next page bit. */ - -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) - -/* - * Expansion register for auto-negotiation. - */ -#define EXPANSION_NWAY 0x0001 /**< Can do N-way auto-nego. */ -#define EXPANSION_LCWP 0x0002 /**< Got new RX page code word. */ -#define EXPANSION_ENABLENPAGE 0x0004 /**< This enables npage words. */ -#define EXPANSION_NPCAPABLE 0x0008 /**< Link partner supports npage. */ -#define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */ -#define EXPANSION_RESV 0xffe0 /**< Unused. */ - -#define ESTATUS_1000_TFULL 0x2000 /**< Can do 1000BT Full. */ -#define ESTATUS_1000_THALF 0x1000 /**< Can do 1000BT Half. */ - -/* - * N-way test register. - */ -#define NWAYTEST_RESV1 0x00ff /**< Unused. */ -#define NWAYTEST_LOOPBACK 0x0100 /**< Enable loopback for N-way. */ -#define NWAYTEST_RESV2 0xfe00 /**< Unused. */ - -/* - * 1000BASE-T Control register. - */ -#define ADVERTISE_1000FULL 0x0200 /**< Advertise 1000BASE-T full duplex.*/ -#define ADVERTISE_1000HALF 0x0100 /**< Advertise 1000BASE-T half duplex.*/ - -/* - * 1000BASE-T Status register. - */ -#define LPA_1000LOCALRXOK 0x2000 /**< Link partner local receiver status.*/ -#define LPA_1000REMRXOK 0x1000 /**< Link partner remote receiver status.*/ -#define LPA_1000FULL 0x0800 /**< Link partner 1000BASE-T full duplex.*/ -#define LPA_1000HALF 0x0400 /**< Link partner 1000BASE-T half duplex.*/ - -/* - * PHY identifiers. - */ -#define MII_DM9161_ID 0x0181b8a0 -#define MII_AM79C875_ID 0x00225540 -#define MII_KS8721_ID 0x00221610 - -#endif /* _MII_H_ */ - -/*-* @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/mmc_spi.h b/ChibiOS_2.0.8/os/hal/include/mmc_spi.h deleted file mode 100644 index 64723d6..0000000 --- a/ChibiOS_2.0.8/os/hal/include/mmc_spi.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mmc_spi.h - * @brief MMC over SPI driver header. - * - * @addtogroup MMC_SPI - * @{ - */ - -#ifndef _MMC_SPI_H_ -#define _MMC_SPI_H_ - -#if CH_HAL_USE_MMC_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define MMC_CMD0_RETRY 10 -#define MMC_CMD1_RETRY 100 -#define MMC_WAIT_DATA 10000 - -#define MMC_CMDGOIDLE 0 -#define MMC_CMDINIT 1 -#define MMC_CMDREADCSD 9 -#define MMC_CMDSTOP 12 -#define MMC_CMDSETBLOCKLEN 16 -#define MMC_CMDREAD 17 -#define MMC_CMDREADMULTIPLE 18 -#define MMC_CMDWRITE 24 -#define MMC_CMDWRITEMULTIPLE 25 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Block size for MMC transfers. - */ -#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) -#define MMC_SECTOR_SIZE 512 -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/** - * @brief Number of positive insertion queries before generating the - * insertion event. - */ -#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) -#define MMC_POLLING_INTERVAL 10 -#endif - -/** - * @brief Interval, in milliseconds, between insertion queries. - */ -#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) -#define MMC_POLLING_DELAY 10 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_HAL_USE_SPI || !CH_USE_EVENTS -#error "MMC_SPI driver requires CH_HAL_USE_SPI and CH_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - MMC_UNINIT = 0, /**< @brief Not initialized. */ - MMC_STOP = 1, /**< @brief Stopped. */ - MMC_WAIT = 2, /**< @brief Waiting card. */ - MMC_INSERTED = 3, /**< @brief Card inserted. */ - MMC_READY = 4, /**< @brief Card ready. */ - MMC_READING = 5, /**< @brief Reading. */ - MMC_WRITING = 6 /**< @brief Writing. */ -} mmcstate_t; - -/** - * @brief Function used to query some hardware status bits. - * - * @return The status. - */ -typedef bool_t (*mmcquery_t)(void); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - -} MMCConfig; - -/** - * @brief Structure representing a MMC driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - mmcstate_t mmc_state; - /** - * @brief Current configuration data. - */ - const MMCConfig *mmc_config; - /** - * @brief SPI driver associated to this MMC driver. - */ - SPIDriver *mmc_spip; - /** - * @brief SPI low speed configuration used during initialization. - */ - const SPIConfig *mmc_lscfg; - /** - * @brief SPI high speed configuration used during transfers. - */ - const SPIConfig *mmc_hscfg; - /** - * @brief Write protect status query function. - */ - mmcquery_t mmc_is_protected; - /** - * @brief Insertion status query function. - */ - mmcquery_t mmc_is_inserted; - /** - * @brief Card insertion event source. - */ - EventSource mmc_inserted_event; - /** - * @brief Card removal event source. - */ - EventSource mmc_removed_event; - /** - * @brief MMC insertion polling timer. - */ - VirtualTimer mmc_vt; - /** - * @brief Insertion counter. - */ - uint_fast8_t mmc_cnt; -} MMCDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Returns the driver state. - */ -#define mmcGetDriverState(mmcp) ((mmcp)->mmc_state) - -/** - * @brief Returns the write protect status. - */ -#define mmcIsWriteProtected(mmcp) ((mmcp)->mmc_is_protected()) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void mmcInit(void); - void mmcObjectInit(MMCDriver *mmcp, SPIDriver *spip, - const SPIConfig *lscfg, const SPIConfig *hscfg, - mmcquery_t is_protected, mmcquery_t is_inserted); - void mmcStart(MMCDriver *mmcp, const MMCConfig *config); - void mmcStop(MMCDriver *mmcp); - bool_t mmcConnect(MMCDriver *mmcp); - bool_t mmcDisconnect(MMCDriver *mmcp); - bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk); - bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer); - bool_t mmcStopSequentialRead(MMCDriver *mmcp); - bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk); - bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer); - bool_t mmcStopSequentialWrite(MMCDriver *mmcp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_MMC_SPI */ - -#endif /* _MMC_SPI_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/pal.h b/ChibiOS_2.0.8/os/hal/include/pal.h deleted file mode 100644 index 05cb4aa..0000000 --- a/ChibiOS_2.0.8/os/hal/include/pal.h +++ /dev/null @@ -1,508 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file pal.h - * @brief I/O Ports Abstraction Layer macros, types and structures. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_H_ -#define _PAL_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Bits in a mode word dedicated as mode selector. - * @details The other bits are not defined and may be used as device-specific - * option bits. - */ -#define PAL_MODE_MASK 0xF - -/** - * @brief After reset state. - * @details The state itself is not specified and is architecture dependent, - * it is guaranteed to be equal to the after-reset state. It is - * usually an input state. - */ -#define PAL_MODE_RESET 0 - -/** - * @brief Safe state for unconnected pads. - * @details The state itself is not specified and is architecture dependent, - * it may be mapped on @p PAL_MODE_INPUT_PULLUP, - * @p PAL_MODE_INPUT_PULLDOWN or @p PAL_MODE_OUTPUT_PUSHPULL as - * example. - */ -#define PAL_MODE_UNCONNECTED 1 - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT 2 - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP 3 - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN 4 - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG 5 - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL 6 - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN 7 - -/** - * @brief Logical low state. - */ -#define PAL_LOW 0 - -/** - * @brief Logical high state. - */ -#define PAL_HIGH 1 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -#include "pal_lld.h" - -/** - * @brief I/O bus descriptor. - * @details This structure describes a group of contiguous digital I/O lines - * that have to be handled as bus. - * @note I/O operations on a bus do not affect I/O lines on the same port but - * not belonging to the bus. - */ -typedef struct { - /** - * @brief Port identifier. - */ - ioportid_t bus_portid; - /** - * @brief Bus mask aligned to port bit 0. - * @note The bus mask implicitly define the bus width. A logical AND is - * performed on the bus data. - */ - ioportmask_t bus_mask; - /** - * @brief Offset, within the port, of the least significant bit of the bus. - */ - uint_fast8_t bus_offset; -} IOBus; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Port bit helper macro. - * @details This macro calculates the mask of a bit within a port. - * - * @param[in] n bit position within the port - * @return The bit mask. - */ -#define PAL_PORT_BIT(n) ((ioportmask_t)(1 << (n))) - - -/** - * @brief Bits group mask helper. - * @details This macro calculates the mask of a bits group. - * - * @param[in] width group width - * @return The group mask. - */ -#define PAL_GROUP_MASK(width) ((ioportmask_t)(1 << (width)) - 1) - -/** - * @brief Data part of a static I/O bus initializer. - * @details This macro should be used when statically initializing an I/O bus - * that is part of a bigger structure. - * - * @param[in] name name of the IOBus variable - * @param[in] port I/O port descriptor - * @param[in] width bus width in bits - * @param[in] offset bus bit offset within the port - */ -#define _IOBUS_DATA(name, port, width, offset) \ - {port, PAL_GROUP_MASK(width), offset} - -/** - * @brief Static I/O bus initializer. - * - * @param[in] name name of the IOBus variable - * @param[in] port I/O port descriptor - * @param[in] width bus width in bits - * @param[in] offset bus bit offset within the port - */ -#define IOBUS_DECL(name, port, width, offset) \ - IOBus name = _IOBUS_DATA(name, port, width, offset) - -/** - * @brief PAL subsystem initialization. - * - * @param[in] config pointer to an architecture specific configuration - * structure. This structure is defined in the low level driver - * header. - */ -#define palInit(config) pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * @note The default implementation always return zero and computes the - * parameter eventual side effects. - * - * @param[in] port port identifier - * @return The port logical states. - */ -#if !defined(pal_lld_readport) || defined(__DOXYGEN__) -#define palReadPort(port) ((void)(port), 0) -#else -#define palReadPort(port) pal_lld_readport(port) -#endif - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note The default implementation always return zero and computes the - * parameter eventual side effects. - * - * @param[in] port port identifier - * @return The latched logical states. - */ -#if !defined(pal_lld_readlatch) || defined(__DOXYGEN__) -#define palReadLatch(port) ((void)(port), 0) -#else -#define palReadLatch(port) pal_lld_readlatch(port) -#endif - -/** - * @brief Writes a bits mask on a I/O port. - * @note The default implementation does nothing except computing the - * parameters eventual side effects. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - */ -#if !defined(pal_lld_writeport) || defined(__DOXYGEN__) -#define palWritePort(port, bits) ((void)(port), (void)(bits)) -#else -#define palWritePort(port, bits) pal_lld_writeport(port, bits) -#endif - -/** - * @brief Sets a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - */ -#if !defined(pal_lld_setport) || defined(__DOXYGEN__) -#define palSetPort(port, bits) { \ - palWritePort(port, palReadLatch(port) | (bits)); \ -} -#else -#define palSetPort(port, bits) pal_lld_setport(port, bits) -#endif - -/** - * @brief Clears a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - */ -#if !defined(pal_lld_clearport) || defined(__DOXYGEN__) -#define palClearPort(port, bits) { \ - palWritePort(port, palReadLatch(port) & ~(bits)); \ -} -#else -#define palClearPort(port, bits) pal_lld_clearport(port, bits) -#endif - -/** - * @brief Toggles a bits mask on a I/O port. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be XORed on the specified port - */ -#if !defined(pal_lld_toggleport) || defined(__DOXYGEN__) -#define palTogglePort(port, bits) { \ - palWritePort(port, palReadLatch(port) ^ (bits)); \ -} -#else -#define palTogglePort(port, bits) pal_lld_toggleport(port, bits) -#endif - -/** - * @brief Reads a group of bits. - * - * @param[in] port port identifier - * @param[in] mask group mask, a logical AND is performed on the input - * data - * @param[in] offset group bit offset within the port - * @return The group logical states. - */ -#if !defined(pal_lld_readgroup) || defined(__DOXYGEN__) -#define palReadGroup(port, mask, offset) \ - ((palReadPort(port) >> (offset)) & (mask)) -#else -#define palReadGroup(port, mask, offset) pal_lld_readgroup(port, mask, offset) -#endif - -/** - * @brief Writes a group of bits. - * - * @param[in] port port identifier - * @param[in] mask group mask, a logical AND is performed on the - * output data - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group - * width are masked. - */ -#if !defined(pal_lld_writegroup) || defined(__DOXYGEN__) -#define palWriteGroup(port, mask, offset, bits) { \ - palWritePort(port, (palReadLatch(port) & ~((mask) << (offset))) | \ - (((bits) & (mask)) << (offset))); \ -} -#else -#define palWriteGroup(port, mask, offset, bits) \ - pal_lld_writegroup(port, mask, offset, bits) -#endif - - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] mode group mode - * - */ -#if !defined(pal_lld_setgroupmode) || defined(__DOXYGEN__) -#define palSetGroupMode(port, mask, mode) -#else -#define palSetGroupMode(port, mask, mode) pal_lld_setgroupmode(port, mask, mode) -#endif - -/** - * @brief Reads an input pad logical state. - * @note The default implementation not necessarily optimal. Low level - * drivers may optimize the function by using specific hardware - * or coding. - * @note The default implementation internally uses the @p palReadPort(). - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - * - */ -#if !defined(pal_lld_readpad) || defined(__DOXYGEN__) -#define palReadPad(port, pad) ((palReadPort(port) >> (pad)) & 1) -#else -#define palReadPad(port, pad) pal_lld_readpad(port, pad) -#endif - -/** - * @brief Writes a logical state on an output pad. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palReadLatch() - * and @p palWritePort(). - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - */ -#if !defined(pal_lld_writepad) || defined(__DOXYGEN__) -#define palWritePad(port, pad, bit) { \ - palWritePort(port, (palReadLatch(port) & ~PAL_PORT_BIT(pad)) | \ - (((bit) & 1) << pad)); \ -} -#else -#define palWritePad(port, pad, bit) pal_lld_writepad(port, pad, bit) -#endif - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palSetPort(). - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#if !defined(pal_lld_setpad) || defined(__DOXYGEN__) -#define palSetPad(port, pad) palSetPort(port, PAL_PORT_BIT(pad)) -#else -#define palSetPad(port, pad) pal_lld_setpad(port, pad) -#endif - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palClearPort(). - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#if !defined(pal_lld_clearpad) || defined(__DOXYGEN__) -#define palClearPad(port, pad) palClearPort(port, PAL_PORT_BIT(pad)) -#else -#define palClearPad(port, pad) pal_lld_clearpad(port, pad) -#endif - -/** - * @brief Toggles a pad logical state. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * @note The default implementation internally uses the @p palTogglePort(). - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#if !defined(pal_lld_togglepad) || defined(__DOXYGEN__) -#define palTogglePad(port, pad) palTogglePort(port, PAL_PORT_BIT(pad)) -#else -#define palTogglePad(port, pad) pal_lld_togglepad(port, pad) -#endif - - -/** - * @brief Pad mode setup. - * @details This function programs a pad with the specified mode. - * @note The default implementation not necessarily optimal. Low level - * drivers may optimize the function by using specific hardware - * or coding. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] mode pad mode - */ -#if !defined(pal_lld_setpadmode) || defined(__DOXYGEN__) -#define palSetPadMode(port, pad, mode) \ - palSetGroupMode(port, PAL_PORT_BIT(pad), mode) -#else -#define palSetPadMode(port, pad, mode) pal_lld_setpadmode(port, pad, mode) -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - ioportmask_t palReadBus(IOBus *bus); - void palWriteBus(IOBus *bus, ioportmask_t bits); - void palSetBusMode(IOBus *bus, uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* _PAL_H_ */ - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/pwm.h b/ChibiOS_2.0.8/os/hal/include/pwm.h deleted file mode 100644 index 6b4f511..0000000 --- a/ChibiOS_2.0.8/os/hal/include/pwm.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file pwm.h - * @brief PWM Driver macros and structures. - * - * @addtogroup PWM - * @{ - */ - -#ifndef _PWM_H_ -#define _PWM_H_ - -#if CH_HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - PWM_UNINIT = 0, /**< Not initialized. */ - PWM_STOP = 1, /**< Stopped. */ - PWM_READY = 2, /**< Ready. */ -} pwmstate_t; - -/** - * @brief PWM logic mode. - */ -typedef enum { - PWM_OUTPUT_DISABLED = 0, /**< Output not driven, callback only. */ - PWM_OUTPUT_ACTIVE_HIGH = 1, /**< Idle is logic level 0. */ - PWM_OUTPUT_ACTIVE_LOW = 2 /**< Idle is logic level 1. */ -} pwmmode_t; - -#include "pwm_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Enables a PWM channel. - * @details Programs (or reprograms) a PWM channel. - * @note This function has to be invoked from a lock zone. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier - * @param[in] width PWM pulse width as clock pulses number - */ -#define pwmEnableChannelI(pwmp, channel, width) \ - pwm_lld_enable_channel(pwmp, channel, width) - -/** - * @brief Disables a PWM channel. - * @details The channel is disabled and its output line returned to the - * idle state. - * @note This function has to be invoked from a lock zone. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier - */ -#define pwmDisableChannelI(pwmp, channel) \ - pwm_lld_disable_channel(pwmp, channel) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void pwmInit(void); - void pwmObjectInit(PWMDriver *pwmp); - void pwmStart(PWMDriver *pwmp, const PWMConfig *config); - void pwmStop(PWMDriver *pwmp); - void pwmEnableChannel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PWM */ - -#endif /* _PWM_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/serial.h b/ChibiOS_2.0.8/os/hal/include/serial.h deleted file mode 100644 index 5a78a33..0000000 --- a/ChibiOS_2.0.8/os/hal/include/serial.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file serial.h - * @brief Serial Driver macros and structures. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_H_ -#define _SERIAL_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** @brief No pending conditions.*/ -#define SD_NO_ERROR 0 -/** @brief Connection happened.*/ -#define SD_CONNECTED 1 -/** @brief Disconnection happened.*/ -#define SD_DISCONNECTED 2 -/** @brief Parity error happened.*/ -#define SD_PARITY_ERROR 4 -/** @brief Framing error happened.*/ -#define SD_FRAMING_ERROR 8 -/** @brief Overflow happened.*/ -#define SD_OVERRUN_ERROR 16 -/** @brief Noise on the line.*/ -#define SD_NOISE_ERROR 32 -/** @brief Break detected.*/ -#define SD_BREAK_DETECTED 64 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 38400 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 64 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 64 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_USE_QUEUES && !CH_USE_EVENTS -#error "Serial Driver requires CH_USE_QUEUES and CH_USE_EVENTS" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SD_UNINIT = 0, /**< @brief Not initialized. */ - SD_STOP = 1, /**< @brief Stopped. */ - SD_READY = 2 /**< @brief Ready. */ -} sdstate_t; - -/** - * @brief Structure representing a serial driver. - */ -typedef struct _SerialDriver SerialDriver; - -#include "serial_lld.h" - -/** - * @brief @p SerialDriver specific methods. - */ -#define _serial_driver_methods \ - _base_asynchronous_channel_methods - -/** - * @brief @p SerialDriver virtual methods table. - */ -struct SerialDriverVMT { - _serial_driver_methods -}; - -/** - * @extends BaseAsynchronousChannel - * - * @brief Full duplex serial driver class. - * @details This class extends @p BaseAsynchronousChannel by adding physical - * I/O queues. - */ -struct _SerialDriver { - /** @brief Virtual Methods Table.*/ - const struct SerialDriverVMT *vmt; - _serial_driver_data -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Direct output check on a @p SerialDriver. - * @details This function bypasses the indirect access to the channel and - * checks directly the output queue. This is faster but cannot - * be used to check different channels implementations. - * - * @see chIOPutWouldBlock() - */ -#define sdPutWouldBlock(sdp) chOQIsFull(&(sdp)->oqueue) - -/** - * @brief Direct input check on a @p SerialDriver. - * @details This function bypasses the indirect access to the channel and - * checks directly the input queue. This is faster but cannot - * be used to check different channels implementations. - * - * @see chIOGetWouldBlock() - */ -#define sdGetWouldBlock(sdp) chIQIsEmpty(&(sdp)->iqueue) - -/** - * @brief Direct write to a @p SerialDriver. - * @details This function bypasses the indirect access to the channel and - * writes directly on the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chIOPut() - */ -#define sdPut(sdp, b) chOQPut(&(sdp)->oqueue, b) - -/** - * @brief Direct write to a @p SerialDriver with timeout specification. - * @details This function bypasses the indirect access to the channel and - * writes directly on the output queue. This is faster but cannot - * be used to write to different channels implementations. - * - * @see chIOPutTimeout() - */ -#define sdPutTimeout(sdp, b, t) chOQPutTimeout(&(sdp)->iqueue, b, t) - -/** - * @brief Direct read from a @p SerialDriver. - * @details This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chIOGet() - */ -#define sdGet(sdp) chIQGet(&(sdp)->iqueue) - -/** - * @brief Direct read from a @p SerialDriver with timeout specification. - * @details This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chIOGetTimeout() - */ -#define sdGetTimeout(sdp, t) chIQGetTimeout(&(sdp)->iqueue, t) - -/** - * @brief Direct blocking write to a @p SerialDriver. - * @details This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write from different channels implementations. - * - * @see chIOWriteTimeout() - */ -#define sdWrite(sdp, b, n) \ - chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE) - -/** - * @brief Direct blocking write to a @p SerialDriver with timeout - * specification. - * @details This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write from different channels implementations. - * - * @see chIOWriteTimeout() - */ -#define sdWriteTimeout(sdp, b, n, t) \ - chOQWriteTimeout(&(sdp)->oqueue, b, n, t) - -/** - * @brief Direct non-blocking write to a @p SerialDriver. - * @details This function bypasses the indirect access to the channel and - * writes directly to the output queue. This is faster but cannot - * be used to write from different channels implementations. - * - * @see chIOWriteTimeout() - */ -#define sdAsynchronousWrite(sdp, b, n) \ - chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE) - -/** - * @brief Direct blocking read from a @p SerialDriver. - * @details This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chIOReadTimeout() - */ -#define sdRead(sdp, b, n) \ - chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE) - -/** - * @brief Direct blocking read from a @p SerialDriver with timeout - * specification. - * @details This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chIOReadTimeout() - */ -#define sdReadTimeout(sdp, b, n, t) \ - chIQReadTimeout(&(sdp)->iqueue, b, n, t) - -/** - * @brief Direct non-blocking read from a @p SerialDriver. - * @details This function bypasses the indirect access to the channel and - * reads directly from the input queue. This is faster but cannot - * be used to read from different channels implementations. - * - * @see chIOReadTimeout() - */ -#define sdAsynchronousRead(sdp, b, n) \ - chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE) - -/** - * @brief Returns the status change event source. - * @details The status change event source is broadcasted when the channel - * status is updated, the status flags can then be fetched and - * cheared by using @p sdGetAndClearFlags(). - * - * @param[in] ip pointer to a @p SerialDriver object - * @return A pointer to an @p EventSource object. - */ -#define sdGetStatusChangeEventSource(ip) (&((ip)->vmt->sevent)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void sdInit(void); - void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify); - void sdStart(SerialDriver *sdp, const SerialConfig *config); - void sdStop(SerialDriver *sdp); - void sdIncomingDataI(SerialDriver *sdp, uint8_t b); - msg_t sdRequestDataI(SerialDriver *sdp); - void sdAddFlagsI(SerialDriver *sdp, sdflags_t mask); - sdflags_t sdGetAndClearFlags(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/include/spi.h b/ChibiOS_2.0.8/os/hal/include/spi.h deleted file mode 100644 index 0e6d732..0000000 --- a/ChibiOS_2.0.8/os/hal/include/spi.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file spi.h - * @brief SPI Driver macros and structures. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_H_ -#define _SPI_H_ - -#if CH_HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the SPI bus. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if SPI_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES -#error "SPI_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SPI_UNINIT = 0, /**< @brief Not initialized. */ - SPI_STOP = 1, /**< @brief Stopped. */ - SPI_READY = 2, /**< @brief Ready. */ - SPI_ACTIVE = 3 /**< @brief Slave selected. */ -} spistate_t; - -#include "spi_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void spiInit(void); - void spiObjectInit(SPIDriver *spip); - void spiStart(SPIDriver *spip, const SPIConfig *config); - void spiStop(SPIDriver *spip); - void spiSelect(SPIDriver *spip); - void spiUnselect(SPIDriver *spip); - void spiIgnore(SPIDriver *spip, size_t n); - void spiExchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf); - void spiSend(SPIDriver *spip, size_t n, const void *txbuf); - void spiReceive(SPIDriver *spip, size_t n, void *rxbuf); -#if SPI_USE_MUTUAL_EXCLUSION - void spiAcquireBus(SPIDriver *spip); - void spiReleaseBus(SPIDriver *spip); -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SPI */ - -#endif /* _SPI_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h deleted file mode 100644 index 5eb3450..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S128.h -// Object : AT91SAM7S128 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:12:49) -// -// CVS Reference : /AT91SAM7S128.pl/1.12/Wed Aug 30 14:08:34 2006// -// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// -// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S128_H -#define AT91SAM7S128_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S128 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S128 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S128 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S128 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S128 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes - -#endif diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h deleted file mode 100644 index 812f3fa..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S256.h -// Object : AT91SAM7S256 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:12:57) -// -// CVS Reference : /AT91SAM7S256.pl/1.12/Wed Aug 30 14:08:39 2006// -// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// -// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S256_H -#define AT91SAM7S256_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h deleted file mode 100644 index 2b8841d..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h +++ /dev/null @@ -1,2303 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S512.h -// Object : AT91SAM7S512 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:13:20) -// -// CVS Reference : /AT91SAM7S512.pl/1.6/Wed Aug 30 14:08:44 2006// -// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// -// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005// -// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005// -// CVS Reference : /SDRC_SAM7SE512.pl/1.7/Fri Jul 8 07:50:18 2005// -// CVS Reference : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S512_H -#define AT91SAM7S512_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_EFC { - AT91_REG EFC_FMR; // MC Flash Mode Register - AT91_REG EFC_FCR; // MC Flash Command Register - AT91_REG EFC_FSR; // MC Flash Status Register - AT91_REG EFC_VR; // MC Flash Version Register -} AT91S_EFC, *AT91PS_EFC; -#else -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register -#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register - -#endif -// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number -// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key -// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status -// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- -#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number -#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[1]; // - AT91_REG MC_PUIA[16]; // MC Protection Unit Area - AT91_REG MC_PUP; // MC Protection Unit Peripherals - AT91_REG MC_PUER; // MC Protection Unit Enable Register - AT91_REG Reserved1[2]; // - AT91_REG MC0_FMR; // MC Flash Mode Register - AT91_REG MC0_FCR; // MC Flash Command Register - AT91_REG MC0_FSR; // MC Flash Status Register - AT91_REG MC0_VR; // MC Flash Version Register - AT91_REG MC1_FMR; // MC Flash Mode Register - AT91_REG MC1_FCR; // MC Flash Command Register - AT91_REG MC1_FSR; // MC Flash Status Register - AT91_REG MC1_VR; // MC Flash Version Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area -#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals -#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection -#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access -#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access -#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only -#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write -#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size -#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte -#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte -#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte -#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte -#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte -#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte -#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte -#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte -#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte -#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte -#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte -#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte -#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte -#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte -#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte -#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte -#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S512 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for EFC0 peripheral ========== -#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register -#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register -#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register -#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register -// ========== Register definition for EFC1 peripheral ========== -#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register -#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register -#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register -#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals -#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S512 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S512 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S512 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address -#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S512 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes - -#endif diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h deleted file mode 100644 index af386a7..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S64.h -// Object : AT91SAM7S64 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:13:29) -// -// CVS Reference : /AT91SAM7S64.pl/1.23/Wed Aug 30 14:08:51 2006// -// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// -// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S64_H -#define AT91SAM7S64_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00010000) // Internal FLASH size in byte (64 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (128) // Internal FLASH Page Size: 128 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (4096) // Internal FLASH Lock Region Size: 4 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h deleted file mode 100644 index 458b252..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h +++ /dev/null @@ -1,2914 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X128.h -// Object : AT91SAM7X128 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:15:23) -// -// CVS Reference : /AT91SAM7X128.pl/1.19/Wed Aug 30 14:09:08 2006// -// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// -// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X128_H -#define AT91SAM7X128_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; -#else -#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register -#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register -#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register -#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register -#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register -#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register -#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register -#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register - -#endif -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; -#else -#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register -#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register -#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register -#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register -#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register -#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register -#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register -#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register -#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register -#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register -#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register -#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register - -#endif -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; -#else -#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register -#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register -#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register -#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register -#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer -#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer -#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register -#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register -#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register -#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register -#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register -#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register -#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register -#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register -#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register -#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register -#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register -#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register -#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register -#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register -#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register -#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register -#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register -#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register -#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register -#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register -#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register -#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register -#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register -#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register -#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register -#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register -#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register -#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register -#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] -#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] -#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register -#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register -#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register -#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register -#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register - -#endif -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes - -#endif diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h deleted file mode 100644 index 4366bad..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h +++ /dev/null @@ -1,2918 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// - Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the disclaimer below in the documentation and/or -// other materials provided with the distribution. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 06/19/2007 (15:41:06) -// -// CVS Reference : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006// -// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// -// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; -#else -#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register -#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register -#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register -#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register -#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register -#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register -#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register -#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register - -#endif -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; -#else -#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register -#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register -#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register -#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register -#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register -#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register -#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register -#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register -#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register -#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register -#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register -#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register - -#endif -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; -#else -#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register -#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register -#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register -#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register -#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer -#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer -#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register -#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register -#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register -#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register -#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register -#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register -#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register -#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register -#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register -#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register -#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register -#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register -#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register -#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register -#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register -#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register -#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register -#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register -#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register -#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register -#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register -#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register -#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register -#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register -#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register -#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register -#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register -#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register -#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] -#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] -#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register -#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register -#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register -#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register -#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register - -#endif -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h deleted file mode 100644 index ea0fcb6..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h +++ /dev/null @@ -1,2984 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X512.h -// Object : AT91SAM7X512 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:15:41) -// -// CVS Reference : /AT91SAM7X512.pl/1.7/Wed Aug 30 14:09:17 2006// -// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// -// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// -// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X512_H -#define AT91SAM7X512_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_EFC { - AT91_REG EFC_FMR; // MC Flash Mode Register - AT91_REG EFC_FCR; // MC Flash Command Register - AT91_REG EFC_FSR; // MC Flash Status Register - AT91_REG EFC_VR; // MC Flash Version Register -} AT91S_EFC, *AT91PS_EFC; -#else -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register -#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register - -#endif -// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number -// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key -// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status -// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- -#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number -#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[1]; // - AT91_REG MC_PUIA[16]; // MC Protection Unit Area - AT91_REG MC_PUP; // MC Protection Unit Peripherals - AT91_REG MC_PUER; // MC Protection Unit Enable Register - AT91_REG Reserved1[2]; // - AT91_REG MC0_FMR; // MC Flash Mode Register - AT91_REG MC0_FCR; // MC Flash Command Register - AT91_REG MC0_FSR; // MC Flash Status Register - AT91_REG MC0_VR; // MC Flash Version Register - AT91_REG MC1_FMR; // MC Flash Mode Register - AT91_REG MC1_FCR; // MC Flash Command Register - AT91_REG MC1_FSR; // MC Flash Status Register - AT91_REG MC1_VR; // MC Flash Version Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area -#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals -#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection -#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access -#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access -#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only -#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write -#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size -#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte -#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte -#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte -#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte -#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte -#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte -#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte -#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte -#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte -#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte -#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte -#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte -#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte -#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte -#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte -#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte -#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; -#else -#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register -#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register -#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register -#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register -#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register -#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register -#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register -#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register - -#endif -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; -#else -#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register -#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register -#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register -#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register -#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register -#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register -#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register -#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register -#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register -#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register -#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register -#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register - -#endif -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; -#else -#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register -#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register -#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register -#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register -#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer -#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer -#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register -#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register -#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register -#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register -#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register -#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register -#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register -#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register -#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register -#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register -#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register -#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register -#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register -#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register -#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register -#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register -#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register -#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register -#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register -#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register -#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register -#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register -#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register -#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register -#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register -#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register -#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register -#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register -#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] -#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] -#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register -#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register -#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register -#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register -#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register - -#endif -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X512 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for EFC0 peripheral ========== -#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register -#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register -#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register -#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register -// ========== Register definition for EFC1 peripheral ========== -#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register -#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register -#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register -#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals -#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X512 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X512 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X512 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address -#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X512 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00020000) // Internal SRAM size in byte (128 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes - -#endif diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/aic.c b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/aic.c deleted file mode 100644 index f71ee09..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/aic.c +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - * ---------------------------------------------------------------------------- - * Copyright (c) 2006, Atmel Corporation - - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaiimer below. - * - * - Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the disclaimer below in the documentation and/or - * other materials provided with the distribution. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "aic.h" -#include - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures the interrupt associated with the given source, using the -/// specified mode and interrupt handler. -/// \param source Interrupt source to configure. -/// \param mode Triggering mode of the interrupt. -/// \param handler Interrupt handler function. -//------------------------------------------------------------------------------ -void AIC_ConfigureIT(unsigned int source, - unsigned int mode, - void (*handler)( void )) -{ - // Disable the interrupt first - AT91C_BASE_AIC->AIC_IDCR = 1 << source; - - // Configure mode and handler - AT91C_BASE_AIC->AIC_SMR[source] = mode; - AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; - - // Clear interrupt - AT91C_BASE_AIC->AIC_ICCR = 1 << source; -} - -//------------------------------------------------------------------------------ -/// Enables interrupts coming from the given (unique) source. -/// \param source Interrupt source to enable. -//------------------------------------------------------------------------------ -void AIC_EnableIT(unsigned int source) -{ - AT91C_BASE_AIC->AIC_IECR = 1 << source; -} - -//------------------------------------------------------------------------------ -/// Disables interrupts coming from the given (unique) source. -/// \param source Interrupt source to enable. -//------------------------------------------------------------------------------ -void AIC_DisableIT(unsigned int source) -{ - AT91C_BASE_AIC->AIC_IDCR = 1 << source; -} - diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/aic.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/aic.h deleted file mode 100644 index ab7fd6d..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91lib/aic.h +++ /dev/null @@ -1,78 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - * ---------------------------------------------------------------------------- - * Copyright (c) 2006, Atmel Corporation - - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaiimer below. - * - * - Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the disclaimer below in the documentation and/or - * other materials provided with the distribution. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \dir -/// !Purpose -/// -/// Methods and definitions for configuring interrupts using the Advanced -/// Interrupt Controller (AIC). -/// -/// !Usage -/// -# Configure an interrupt source using AIC_ConfigureIT -/// -# Enable or disable interrupt generation of a particular source with -/// AIC_EnableIT and AIC_DisableIT. -//------------------------------------------------------------------------------ - -#ifndef AIC_H -#define AIC_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL - /// Redefinition of missing constant. - #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE -#endif - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -extern void AIC_ConfigureIT(unsigned int source, - unsigned int mode, - void (*handler)( void )); - -extern void AIC_EnableIT(unsigned int source); - -extern void AIC_DisableIT(unsigned int source); - -#endif //#ifndef AIC_H - diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7.h deleted file mode 100644 index 66c1e20..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _AT91SAM7_H_ -#define _AT91SAM7_H_ - -/* - * Supported platforms. - */ -#define SAM7S64 0 -#define SAM7S128 1 -#define SAM7S256 2 -#define SAM7S512 3 -#define SAM7X128 4 -#define SAM7X256 5 -#define SAM7X512 6 - -#ifndef SAM7_PLATFORM -#error "SAM7 platform not defined" -#endif - -#if SAM7_PLATFORM == SAM7S64 -#include "at91lib/AT91SAM7S64.h" -#elif SAM7_PLATFORM == SAM7S128 -#include "at91lib/AT91SAM7S128.h" -#elif SAM7_PLATFORM == SAM7S256 -#include "at91lib/AT91SAM7S256.h" -#elif SAM7_PLATFORM == SAM7S512 -#include "at91lib/AT91SAM7S512.h" -#elif SAM7_PLATFORM == SAM7X128 -#include "at91lib/AT91SAM7X128.h" -#elif SAM7_PLATFORM == SAM7X256 -#include "at91lib/AT91SAM7X256.h" -#elif SAM7_PLATFORM == SAM7X512 -#include "at91lib/AT91SAM7X512.h" -#else -#error "SAM7 platform not supported" -#endif - -#endif /* _AT91SAM7_H_ */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7_mii.c b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7_mii.c deleted file mode 100644 index 95cc0e9..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7_mii.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/at91sam7_mii.c - * @brief AT91SAM7 low level MII driver code. - * @addtogroup AT91SAM7_MII - * @{ - */ - -#include "ch.h" -#include "hal.h" -#include "at91sam7_mii.h" - -#if CH_HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level MII driver initialization. - */ -void miiInit(void) { - -} - -/** - * @brief Resets a PHY device. - * - * @param[in] macp pointer to the @p MACDriver object - */ -void miiReset(MACDriver *macp) { - - (void)macp; - - /* - * Disables the pullups on all the pins that are latched on reset by the PHY. - */ - AT91C_BASE_PIOB->PIO_PPUDR = PHY_LATCHED_PINS; - -#ifdef PIOB_PHY_PD_MASK - /* - * PHY power control. - */ - AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK; // Becomes an output. - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK; // Default pullup disabled. -#if (PHY_HARDWARE == PHY_DAVICOM_9161) - AT91C_BASE_PIOB->PIO_CODR = PIOB_PHY_PD_MASK; // Output to low level. -#else - AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK; // Output to high level. -#endif -#endif // PIOB_PHY_PD_MASK - - /* - * PHY reset by pulsing the NRST pin. - */ - AT91C_BASE_RSTC->RSTC_RMR = 0xA5000100; - AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST; - while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)) - ; -} - -/** - * @brief Reads a PHY register through the MII interface. - * - * @param[in] macp pointer to the @p MACDriver object - * @param addr the register address - * @return The register value. - */ -phyreg_t miiGet(MACDriver *macp, phyaddr_t addr) { - - (void)macp; - AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) | /* SOF */ - (0b10 << 28) | /* RW */ - (PHY_ADDRESS << 23) | /* PHYA */ - (addr << 18) | /* REGA */ - (0b10 << 16); /* CODE */ - while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE)) - ; - return (phyreg_t)(AT91C_BASE_EMAC->EMAC_MAN & 0xFFFF); -} - -/** - * @brief Writes a PHY register through the MII interface. - * - * @param[in] macp pointer to the @p MACDriver object - * @param addr the register address - * @param value the new register value - */ -void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value) { - - (void)macp; - AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) | /* SOF */ - (0b01 << 28) | /* RW */ - (PHY_ADDRESS << 23) | /* PHYA */ - (addr << 18) | /* REGA */ - (0b10 << 16) | /* CODE */ - value; - while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE)) - ; -} - -#endif /* CH_HAL_USE_MAC */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7_mii.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7_mii.h deleted file mode 100644 index d329bb2..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/at91sam7_mii.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/at91sam7_mii.h - * @brief AT91SAM7 low level MII driver header. - * @addtogroup AT91SAM7_MII - * @{ - */ - -#ifndef _AT91SAM7_MII_H_ -#define _AT91SAM7_MII_H_ - -#if CH_HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define PHY_MICREL_KS8721 0 -#define PHY_DAVICOM_9161 1 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief PHY manufacturer and model. - */ -#if !defined(PHY_HARDWARE) || defined(__DOXYGEN__) -#define PHY_HARDWARE PHY_MICREL_KS8721 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief Pins latched by the PHY at reset. - */ -#if PHY_HARDWARE == PHY_MICREL_KS8721 -#define PHY_ADDRESS 1 -#define PHY_ID MII_KS8721_ID -#define PHY_LATCHED_PINS (AT91C_PB4_ECRS | AT91C_PB5_ERX0 | \ - AT91C_PB6_ERX1 | AT91C_PB7_ERXER | \ - AT91C_PB13_ERX2 | AT91C_PB14_ERX3 | \ - AT91C_PB15_ERXDV_ECRSDV | AT91C_PB16_ECOL | \ - AT91C_PIO_PB26) - -#elif PHY_HARDWARE == PHY_DAVICOM_9161 -#define PHY_ADDRESS 0 -#define PHY_ID MII_DM9161_ID -#define PHY_LATCHED_PINS (AT91C_PB0_ETXCK_EREFCK | AT91C_PB4_ECRS | \ - AT91C_PB5_ERX0 | AT91C_PB6_ERX1 | \ - AT91C_PB7_ERXER | AT91C_PB13_ERX2 | \ - AT91C_PB14_ERX3 | AT91C_PB15_ERXDV_ECRSDV | \ - AT91C_PB16_ECOL | AT91C_PB17_ERXCK) -#endif /* PHY_HARDWARE */ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a PHY register value. - */ -typedef uint16_t phyreg_t; - -/** - * @brief Type of a PHY register address. - */ -typedef uint8_t phyaddr_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void miiInit(void); - void miiReset(MACDriver *macp); - phyreg_t miiGet(MACDriver *macp, phyaddr_t addr); - void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_MAC */ - -#endif /* _AT91SAM7_MII_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/hal_lld.c deleted file mode 100644 index a7473c8..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/hal_lld.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/hal_lld.c - * @brief AT91SAM7 HAL subsystem low level driver source. - * @addtogroup AT91SAM7_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -const PALConfig pal_default_config = -{ - {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, -#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ - (SAM7_PLATFORM == SAM7X512) - {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -static CH_IRQ_HANDLER(spurious_handler) { - - CH_IRQ_PROLOGUE(); - - AT91SAM7_SPURIOUS_HANDLER_HOOK(); - - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - unsigned i; - - /* FIQ Handler weak symbol defined in vectors.s.*/ - void FiqHandler(void); - - /* Default AIC setup, the device drivers will modify it as needed.*/ - AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; - for (i = 1; i < 31; i++) { - AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; - AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; - } - AT91C_BASE_AIC->AIC_SPU = (AT91_REG)spurious_handler; - -} - -/** - * @brief AT91SAM7 clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - */ -void at91sam7_clock_init(void) { - - /* wait for reset */ - while((AT91C_BASE_RSTC->RSTC_RSR & (AT91C_RSTC_SRCMP | AT91C_RSTC_NRSTL)) != AT91C_RSTC_NRSTL) - ; - /* enable reset */ - AT91C_BASE_RSTC->RSTC_RMR = ((0xA5 << 24) | AT91C_RSTC_URSTEN); - - /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/ -#if SAM7_PLATFORM == SAM7X512 - AT91C_BASE_MC->MC0_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; - AT91C_BASE_MC->MC1_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; -#else - AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; -#endif - - /* Enables the main oscillator and waits 56 slow cycles as startup time.*/ - AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) - ; - - /* PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 - PLLfreq = 96109714 Hz (rounded).*/ - AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | - (AT91C_CKGR_PLLCOUNT & (10 << 8)) | - (AT91SAM7_USBDIV) | - (AT91C_CKGR_MUL & (72 << 16)); - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) - ; - - /* Master clock = PLLfreq / 2 = 48054858 Hz (rounded).*/ - AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) - ; - - AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) - ; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/hal_lld.h deleted file mode 100644 index bee0f72..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/hal_lld.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/hal_lld.h - * @brief AT91SAM7 HAL subsystem low level driver header. - * @addtogroup AT91SAM7_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "at91sam7.h" -#include "at91lib/aic.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "AT91SAM7x" - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Default action for the spurious handler, nothing. - */ -#if !defined(AT91SAM7_SPURIOUS_HANDLER_HOOK) || defined(__DOXYGEN__) -#define AT91SAM7_SPURIOUS_HANDLER_HOOK() -#endif - -/** - * @brief Default divider for the USB clock - half the PLL clock. - */ -#if !defined(AT91SAM7_USBDIV) || defined(__DOXYGEN__) -#define AT91SAM7_USBDIV AT91C_CKGR_USBDIV_1 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void at91sam7_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/mac_lld.c b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/mac_lld.c deleted file mode 100644 index 45ecf0b..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/mac_lld.c +++ /dev/null @@ -1,514 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/mac_lld.c - * @brief AT91SAM7 low level MAC driver code. - * @addtogroup AT91SAM7_MAC - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" -#include "mii.h" -#include "at91sam7_mii.h" - -#if CH_HAL_USE_MAC || defined(__DOXYGEN__) - -#define EMAC_PIN_MASK (AT91C_PB0_ETXCK_EREFCK | AT91C_PB1_ETXEN | \ - AT91C_PB2_ETX0 | AT91C_PB3_ETX1 | \ - AT91C_PB4_ECRS | AT91C_PB5_ERX0 | \ - AT91C_PB6_ERX1 | AT91C_PB7_ERXER | \ - AT91C_PB8_EMDC | AT91C_PB9_EMDIO | \ - AT91C_PB10_ETX2 | AT91C_PB11_ETX3 | \ - AT91C_PB12_ETXER | AT91C_PB13_ERX2 | \ - AT91C_PB14_ERX3 | AT91C_PB15_ERXDV_ECRSDV | \ - AT91C_PB16_ECOL | AT91C_PB17_ERXCK) - -#define RSR_BITS (AT91C_EMAC_BNA | AT91C_EMAC_REC | AT91C_EMAC_OVR) - -#define TSR_BITS (AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES | \ - AT91C_EMAC_BEX | AT91C_EMAC_COMP | AT91C_EMAC_UND) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Ethernet driver 1. - */ -MACDriver ETH1; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -#ifndef __DOXYGEN__ -static bool_t link_up; - -static uint8_t default_mac[] = {0xAA, 0x55, 0x13, 0x37, 0x01, 0x10}; - -static EMACDescriptor *rxptr; -static EMACDescriptor *txptr; -static EMACDescriptor rd[EMAC_RECEIVE_DESCRIPTORS] - __attribute__((aligned(8))); -static EMACDescriptor td[EMAC_TRANSMIT_DESCRIPTORS] - __attribute__((aligned(8))); -static uint8_t rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE] - __attribute__((aligned(8))); -static uint8_t tb[EMAC_TRANSMIT_DESCRIPTORS * EMAC_TRANSMIT_BUFFERS_SIZE] - __attribute__((aligned(8))); -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief IRQ handler. - */ -/** @cond never*/ -__attribute__((noinline)) -/** @endcond*/ -static void serve_interrupt(void) { - uint32_t isr, rsr, tsr; - - /* Fix for the EMAC errata */ - isr = AT91C_BASE_EMAC->EMAC_ISR; - rsr = AT91C_BASE_EMAC->EMAC_RSR; - tsr = AT91C_BASE_EMAC->EMAC_TSR; - - if ((isr & AT91C_EMAC_RCOMP) || (rsr & RSR_BITS)) { - if (rsr & AT91C_EMAC_REC) { - chSysLockFromIsr(); - chSemResetI(Ð1.md_rdsem, 0); -#if CH_USE_EVENTS - chEvtBroadcastI(Ð1.md_rdevent); -#endif - chSysUnlockFromIsr(); - } - AT91C_BASE_EMAC->EMAC_RSR = RSR_BITS; - } - - if ((isr & AT91C_EMAC_TCOMP) || (tsr & TSR_BITS)) { - if (tsr & AT91C_EMAC_COMP) { - chSysLockFromIsr(); - chSemResetI(Ð1.md_tdsem, 0); - chSysUnlockFromIsr(); - } - AT91C_BASE_EMAC->EMAC_TSR = TSR_BITS; - } - AT91C_BASE_AIC->AIC_EOICR = 0; -} - -/** - * @brief Cleans an incomplete frame. - * @param from the start position of the incomplete frame - */ -static void cleanup(EMACDescriptor *from) { - - while (from != rxptr) { - from->w1 &= ~W1_R_OWNERSHIP; - if (++from >= &rd[EMAC_RECEIVE_DESCRIPTORS]) - from = rd; - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EMAC IRQ veneer handler. - */ -CH_IRQ_HANDLER(irq_handler) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(); - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level MAC initialization. - */ -void mac_lld_init(void) { - unsigned i; - - miiInit(); - macObjectInit(Ð1); - - /* - * Buffers initialization. - */ - for (i = 0; i < EMAC_RECEIVE_DESCRIPTORS; i++) { - rd[i].w1 = (uint32_t)&rb[i * EMAC_RECEIVE_BUFFERS_SIZE]; - rd[i].w2 = 0; - } - rd[EMAC_RECEIVE_DESCRIPTORS - 1].w1 |= W1_R_WRAP; - rxptr = rd; - for (i = 0; i < EMAC_TRANSMIT_DESCRIPTORS; i++) { - td[i].w1 = (uint32_t)&tb[i * EMAC_TRANSMIT_BUFFERS_SIZE]; - td[i].w2 = EMAC_TRANSMIT_BUFFERS_SIZE | W2_T_LAST_BUFFER | W2_T_USED; - } - td[EMAC_TRANSMIT_DESCRIPTORS - 1].w2 |= W2_T_WRAP; - txptr = td; - - /* - * Associated PHY initialization. - */ - miiReset(Ð1); - - /* - * EMAC pins setup and clock enable. Note, PB18 is not included because it is - * used as #PD control and not as EF100. - */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; - AT91C_BASE_PIOB->PIO_ASR = EMAC_PIN_MASK; - AT91C_BASE_PIOB->PIO_PDR = EMAC_PIN_MASK; - AT91C_BASE_PIOB->PIO_PPUDR = EMAC_PIN_MASK; - - /* - * EMAC Initial setup. - */ - AT91C_BASE_EMAC->EMAC_NCR = 0; /* Stopped but MCE active.*/ - AT91C_BASE_EMAC->EMAC_NCFGR = 2 << 10; /* MDC-CLK = MCK / 32 */ - AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;/* Enable EMAC in MII mode.*/ - AT91C_BASE_EMAC->EMAC_RBQP = (AT91_REG)rd; /* RX descriptors list.*/ - AT91C_BASE_EMAC->EMAC_TBQP = (AT91_REG)td; /* TX descriptors list.*/ - AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | - AT91C_EMAC_REC | - AT91C_EMAC_BNA; /* Clears RSR.*/ - AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_DRFCS;/* Initial NCFGR settings.*/ - AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | - AT91C_EMAC_RE | - AT91C_EMAC_CLRSTAT;/* Initial NCR settings.*/ - mac_lld_set_address(Ð1, default_mac); - - /* - * PHY device identification. - */ - AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; - if ((miiGet(Ð1, MII_PHYSID1) != (PHY_ID >> 16)) || - ((miiGet(Ð1, MII_PHYSID2) & 0xFFF0) != (PHY_ID & 0xFFF0))) - chSysHalt(); - AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; - - /* - * Interrupt configuration. - */ - AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP; - AIC_ConfigureIT(AT91C_ID_EMAC, - AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | EMAC_INTERRUPT_PRIORITY, - irq_handler); - AIC_EnableIT(AT91C_ID_EMAC); -} - -/** - * @brief Low level MAC address setup. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] p pointer to a six bytes buffer containing the MAC address. If - * this parameter is set to @p NULL then a system default MAC is - * used. The MAC address must be aligned with the most significant - * byte first. - */ -void mac_lld_set_address(MACDriver *macp, const uint8_t *p) { - - (void)macp; - AT91C_BASE_EMAC->EMAC_SA1L = (AT91_REG)((p[3] << 24) | (p[2] << 16) | - (p[1] << 8) | p[0]); - AT91C_BASE_EMAC->EMAC_SA1H = (AT91_REG)((p[5] << 8) | p[4]); -} - -/** - * @brief Returns a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @return The operation status. - * @retval RDY_OK the descriptor was obtained. - * @retval RDY_TIMEOUT descriptor not available. - */ -msg_t max_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp) { - EMACDescriptor *edp; - - (void)macp; - - if (!link_up) - return RDY_TIMEOUT; - - chSysLock(); - edp = txptr; - if (!(edp->w2 & W2_T_USED) || (edp->w2 & W2_T_LOCKED)) { - chSysUnlock(); - return RDY_TIMEOUT; - } - /* - * Set the buffer size and configuration, the buffer is also marked - * as locked. - */ - if (++txptr >= &td[EMAC_TRANSMIT_DESCRIPTORS]) { - edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER | W2_T_WRAP; - txptr = td; - } - else - edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER; - chSysUnlock(); - tdp->td_offset = 0; - tdp->td_size = EMAC_TRANSMIT_BUFFERS_SIZE; - tdp->td_physdesc = edp; - return RDY_OK; -} - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer cointaining the data to be written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's stream, this - * value can be less than the amount specified in the parameter - * @p size if the maximum frame size is reached. - */ -size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size) { - - if (size > tdp->td_size - tdp->td_offset) - size = tdp->td_size - tdp->td_offset; - if (size > 0) { - memcpy((uint8_t *)(tdp->td_physdesc->w1 & W1_T_ADDRESS_MASK) + - tdp->td_offset, - buf, size); - tdp->td_offset += size; - } - return size; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - */ -void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { - - chSysLock(); - tdp->td_physdesc->w2 = (tdp->td_physdesc->w2 & - ~(W2_T_LOCKED | W2_T_USED | W2_T_LENGTH_MASK)) | - tdp->td_offset; - AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART; - chSysUnlock(); -} - -/** - * @brief Returns a receive descriptor. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @return The operation status. - * @retval RDY_OK the descriptor was obtained. - * @retval RDY_TIMEOUT descriptor not available. - */ -msg_t max_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp) { - unsigned n; - EMACDescriptor *edp; - - (void)macp; - n = EMAC_RECEIVE_DESCRIPTORS; - - /* - * Skips unused buffers, if any. - */ -skip: - while ((n > 0) && !(rxptr->w1 & W1_R_OWNERSHIP)) { - if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) - rxptr = rd; - n--; - } - - /* - * Skips fragments, if any, cleaning them up. - */ - while ((n > 0) && (rxptr->w1 & W1_R_OWNERSHIP) && - !(rxptr->w2 & W2_R_FRAME_START)) { - rxptr->w1 &= ~W1_R_OWNERSHIP; - if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) - rxptr = rd; - n--; - } - - /* - * Now compute the total frame size skipping eventual incomplete frames - * or holes... - */ -restart: - edp = rxptr; - while (n > 0) { - if (!(rxptr->w1 & W1_R_OWNERSHIP)) { - /* Empty buffer for some reason... cleaning up the incomplete frame.*/ - cleanup(edp); - goto skip; - } - /* - * End Of Frame found. - */ - if (rxptr->w2 & W2_R_FRAME_END) { - rdp->rd_offset = 0; - rdp->rd_size = rxptr->w2 & W2_T_LENGTH_MASK; - rdp->rd_physdesc = edp; - return RDY_OK; - } - - if ((edp != rxptr) && (rxptr->w2 & W2_R_FRAME_START)) { - /* Found another start... cleaning up the incomplete frame.*/ - cleanup(edp); - goto restart; /* Another start buffer for some reason... */ - } - - if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS]) - rxptr = rd; - n--; - } - return RDY_TIMEOUT; -} - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's stream, this - * value can be less than the amount specified in the parameter - * @p size if there are no more bytes to read. - */ -size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size) { - if (size > rdp->rd_size - rdp->rd_offset) - size = rdp->rd_size - rdp->rd_offset; - if (size > 0) { - uint8_t *src = (uint8_t *)(rdp->rd_physdesc->w1 & W1_R_ADDRESS_MASK) + - rdp->rd_offset; - uint8_t *limit = &rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE]; - if (src >= limit) - src -= EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE; - if (src + size > limit ) { - memcpy(buf, src, (size_t)(limit - src)); - memcpy(buf + (size_t)(limit - src), rb, size - (size_t)(limit - src)); - } - else - memcpy(buf, src, size); - rdp->rd_offset += size; - } - return size; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - */ -void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { - bool_t done; - EMACDescriptor *edp = rdp->rd_physdesc; - - unsigned n = EMAC_RECEIVE_DESCRIPTORS; - do { - done = ((edp->w2 & W2_R_FRAME_END) != 0); - chDbgAssert(edp->w1 & W1_R_OWNERSHIP, - "mac_lld_release_receive_descriptor(), #1", - "found not owned descriptor"); - edp->w1 &= ~(W1_R_OWNERSHIP | W2_R_FRAME_START | W2_R_FRAME_END); - if (++edp >= &rd[EMAC_RECEIVE_DESCRIPTORS]) - edp = rd; - n--; - } - while ((n > 0) && !done); - /* - * Make rxptr point to the descriptor where the next frame will most - * likely appear. - */ - rxptr = edp; -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval TRUE if the link is active. - * @retval FALSE if the link is down. - */ -bool_t mac_lld_poll_link_status(MACDriver *macp) { - uint32_t ncfgr, bmsr, bmcr, lpa; - - AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; - (void)miiGet(macp, MII_BMSR); - bmsr = miiGet(macp, MII_BMSR); - if (!(bmsr & BMSR_LSTATUS)) { - AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; - return link_up = FALSE; - } - - ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); - bmcr = miiGet(macp, MII_BMCR); - if (bmcr & BMCR_ANENABLE) { - lpa = miiGet(macp, MII_LPA); - if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) - ncfgr |= AT91C_EMAC_SPD; - if (lpa & (LPA_10FULL | LPA_100FULL)) - ncfgr |= AT91C_EMAC_FD; - } - else { - if (bmcr & BMCR_SPEED100) - ncfgr |= AT91C_EMAC_SPD; - if (bmcr & BMCR_FULLDPLX) - ncfgr |= AT91C_EMAC_FD; - } - AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr; - AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; - return link_up = TRUE; -} - -#endif /* CH_HAL_USE_MAC */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/mac_lld.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/mac_lld.h deleted file mode 100644 index 741c066..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/mac_lld.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/mac_lld.h - * @brief AT91SAM7 low level MAC driver header. - * @addtogroup AT91SAM7_MAC - * @{ - */ - -#ifndef _MAC_LLD_H_ -#define _MAC_LLD_H_ - -#if CH_HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define EMAC_RECEIVE_BUFFERS_SIZE 128 /* Do not modify */ -#define EMAC_TRANSMIT_BUFFERS_SIZE MAC_BUFFERS_SIZE -#define EMAC_RECEIVE_DESCRIPTORS \ - (((((MAC_BUFFERS_SIZE - 1) | (EMAC_RECEIVE_BUFFERS_SIZE - 1)) + 1) \ - / EMAC_RECEIVE_BUFFERS_SIZE) * MAC_RECEIVE_BUFFERS) -#define EMAC_TRANSMIT_DESCRIPTORS MAC_TRANSMIT_BUFFERS - -#define W1_R_OWNERSHIP 0x00000001 -#define W1_R_WRAP 0x00000002 -#define W1_R_ADDRESS_MASK 0xFFFFFFFC - -#define W2_R_LENGTH_MASK 0x00000FFF -#define W2_R_FRAME_START 0x00004000 -#define W2_R_FRAME_END 0x00008000 -#define W2_R_CFI 0x00010000 -#define W2_R_VLAN_PRIO_MASK 0x000E0000 -#define W2_R_PRIO_TAG_DETECTED 0x00100000 -#define W2_R_VLAN_TAG_DETECTED 0x00200000 -#define W2_R_TYPE_ID_MATCH 0x00400000 -#define W2_R_ADDR4_MATCH 0x00800000 -#define W2_R_ADDR3_MATCH 0x01000000 -#define W2_R_ADDR2_MATCH 0x02000000 -#define W2_R_ADDR1_MATCH 0x04000000 -#define W2_R_RFU1 0x08000000 -#define W2_R_ADDR_EXT_MATCH 0x10000000 -#define W2_R_UNICAST_MATCH 0x20000000 -#define W2_R_MULTICAST_MATCH 0x40000000 -#define W2_R_BROADCAST_DETECTED 0x80000000 - -#define W1_T_ADDRESS_MASK 0xFFFFFFFF - -#define W2_T_LENGTH_MASK 0x000007FF -#define W2_T_LOCKED 0x00000800 /* Not an EMAC flag, used by the driver */ -#define W2_T_RFU1 0x00003000 -#define W2_T_LAST_BUFFER 0x00008000 -#define W2_T_NO_CRC 0x00010000 -#define W2_T_RFU2 0x07FE0000 -#define W2_T_BUFFERS_EXHAUSTED 0x08000000 -#define W2_T_TRANSMIT_UNDERRUN 0x10000000 -#define W2_T_RETRY_LIMIT_EXC 0x20000000 -#define W2_T_WRAP 0x40000000 -#define W2_T_USED 0x80000000 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Number of available transmit buffers. - */ -#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) -#define MAC_TRANSMIT_BUFFERS 2 -#endif - -/** - * @brief Number of available receive buffers. - */ -#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) -#define MAC_RECEIVE_BUFFERS 2 -#endif - -/** - * @brief Maximum supported frame size. - */ -#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define MAC_BUFFERS_SIZE 1518 -#endif - -/** - * @brief Interrupt priority level for the EMAC device. - */ -#if !defined(EMAC_INTERRUPT_PRIORITY) || defined(__DOXYGEN__) -#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Structure representing a buffer physical descriptor. - * @note It represents both descriptor types. - */ -typedef struct { - uint32_t w1; - uint32_t w2; -} EMACDescriptor; - -/** - * @brief Structure representing a MAC driver. - */ -typedef struct { - Semaphore md_tdsem; /**< Transmit semaphore. */ - Semaphore md_rdsem; /**< Receive semaphore. */ -#if CH_USE_EVENTS - EventSource md_rdevent; /**< Receive event source. */ -#endif - /* End of the mandatory fields.*/ -} MACDriver; - -/** - * @brief Structure representing a transmit descriptor. - */ -typedef struct { - size_t td_offset; /**< Current write offset. */ - size_t td_size; /**< Available space size. */ - /* End of the mandatory fields.*/ - EMACDescriptor *td_physdesc; /**< Pointer to the physical - descriptor. */ -} MACTransmitDescriptor; - -/** - * @brief Structure representing a receive descriptor. - */ -typedef struct { - size_t rd_offset; /**< Current read offset. */ - size_t rd_size; /**< Available data size. */ - /* End of the mandatory fields.*/ - EMACDescriptor *rd_physdesc; /**< Pointer to the first descriptor - of the buffers chain. */ -} MACReceiveDescriptor; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern MACDriver ETH1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void mac_lld_init(void); - void mac_lld_set_address(MACDriver *macp, const uint8_t *p); - msg_t max_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp); - size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size); - void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); - msg_t max_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp); - size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size); - void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); - bool_t mac_lld_poll_link_status(MACDriver *macp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_MAC */ - -#endif /* _MAC_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/pal_lld.c deleted file mode 100644 index 92ab5b8..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/pal_lld.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/pal_lld.c - * @brief AT91SAM7 PIO low level driver code. - * @addtogroup AT91SAM7_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief AT91SAM7 I/O ports configuration. - * @details PIO registers initialization. - * - * @param[in] config the AT91SAM7 ports configuration - */ -void _pal_lld_init(const PALConfig *config) { - - uint32_t ports = (1 << AT91C_ID_PIOA); -#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ - (SAM7_PLATFORM == SAM7X512) - ports |= (1 << AT91C_ID_PIOB); -#endif - AT91C_BASE_PMC->PMC_PCER = ports; - - /* - * PIOA setup. - */ - AT91C_BASE_PIOA->PIO_PPUER = config->P0Data.pusr; /* Pull-up as spec.*/ - AT91C_BASE_PIOA->PIO_PPUDR = ~config->P0Data.pusr; - AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; /* PIO enabled.*/ - AT91C_BASE_PIOA->PIO_ODSR = config->P0Data.odsr; /* Data as specified.*/ - AT91C_BASE_PIOA->PIO_OER = config->P0Data.osr; /* Dir. as specified.*/ - AT91C_BASE_PIOA->PIO_ODR = ~config->P0Data.osr; - AT91C_BASE_PIOA->PIO_IFDR = 0xFFFFFFFF; /* Filter disabled.*/ - AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; /* Int. disabled.*/ - AT91C_BASE_PIOA->PIO_MDDR = 0xFFFFFFFF; /* Push Pull drive.*/ - AT91C_BASE_PIOA->PIO_ASR = 0xFFFFFFFF; /* Peripheral A.*/ - AT91C_BASE_PIOA->PIO_OWER = 0xFFFFFFFF; /* Write enabled.*/ - - /* - * PIOB setup. - */ -#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ - (SAM7_PLATFORM == SAM7X512) - AT91C_BASE_PIOB->PIO_PPUER = config->P1Data.pusr; /* Pull-up as spec.*/ - AT91C_BASE_PIOB->PIO_PPUDR = ~config->P1Data.pusr; - AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; /* PIO enabled.*/ - AT91C_BASE_PIOB->PIO_ODSR = config->P1Data.odsr; /* Data as specified.*/ - AT91C_BASE_PIOB->PIO_OER = config->P1Data.osr; /* Dir. as specified.*/ - AT91C_BASE_PIOB->PIO_ODR = ~config->P1Data.osr; - AT91C_BASE_PIOB->PIO_IFDR = 0xFFFFFFFF; /* Filter disabled.*/ - AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF; /* Int. disabled.*/ - AT91C_BASE_PIOB->PIO_MDDR = 0xFFFFFFFF; /* Push Pull drive.*/ - AT91C_BASE_PIOB->PIO_ASR = 0xFFFFFFFF; /* Peripheral A.*/ - AT91C_BASE_PIOB->PIO_OWER = 0xFFFFFFFF; /* Write enabled.*/ -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_RESET is implemented as input with pull-up. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note @p PAL_MODE_OUTPUT_OPENDRAIN also enables the pull-up resistor. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - - switch (mode & PAL_MODE_MASK) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT_PULLUP: - port->PIO_PPUER = mask; - port->PIO_ODR = mask; - break; - case PAL_MODE_INPUT: - case PAL_MODE_INPUT_ANALOG: - port->PIO_PPUDR = mask; - port->PIO_ODR = mask; - break; - case PAL_MODE_UNCONNECTED: - port->PIO_SODR = mask; - /* Falls in */ - case PAL_MODE_OUTPUT_PUSHPULL: - port->PIO_PPUDR = mask; - port->PIO_OER = mask; - port->PIO_MDDR = mask; - break; - case PAL_MODE_OUTPUT_OPENDRAIN: - port->PIO_PPUER = mask; - port->PIO_OER = mask; - port->PIO_MDER = mask; - } -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/pal_lld.h deleted file mode 100644 index 63b389e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/pal_lld.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/pal_lld.h - * @brief AT91SAM7 PIO low level driver header. - * @addtogroup AT91SAM7_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLDOWN - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief PIO port setup info. - */ -typedef struct { - /** Initial value for ODSR register (data).*/ - uint32_t odsr; - /** Initial value for OSR register (direction).*/ - uint32_t osr; - /** Initial value for PUSR register (Pull-ups).*/ - uint32_t pusr; -} at91sam7_pio_setup_t; - -/** - * @brief AT91SAM7 PIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** @brief Port 0 setup data.*/ - at91sam7_pio_setup_t P0Data; -#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ - (SAM7_PLATFORM == SAM7X512) || defined(__DOXYGEN__) - /** @brief Port 1 setup data.*/ - at91sam7_pio_setup_t P1Data; -#endif -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef AT91PS_PIO ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief PIO port A identifier. - */ -#define IOPORT1 AT91C_BASE_PIOA - -/** - * @brief PIO port B identifier. - */ -#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ - (SAM7_PLATFORM == SAM7X512) || defined(__DOXYGEN__) -#define IOPORT2 AT91C_BASE_PIOB -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in a file named pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * @details This function is implemented by reading the PIO_PDSR register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @return The port bits. - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_readport(port) ((port)->PIO_PDSR) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the PIO_ODSR register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @return The latched logical states. - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_readlatch(port) ((port)->PIO_ODSR) - -/** - * @brief Writes a bits mask on a I/O port. - * @details This function is implemented by writing the PIO_ODSR register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be written on the specified port - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_writeport(port, bits) { \ - (port)->PIO_ODSR = (bits); \ -} - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the PIO_SODR register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be ORed on the specified port - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_setport(port, bits) { \ - (port)->PIO_SODR = (bits); \ -} - - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the PIO_CODR register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be cleared on the specified port - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_clearport(port, bits) { \ - (port)->PIO_CODR = (bits); \ -} - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the PIO_OWER, PIO_ODSR and - * PIO_OWDR registers, the implementation is not atomic because the - * multiple accesses. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits the bits to be written. Values exceeding the group width - * are masked. - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_writegroup(port, mask, offset, bits) { \ - (port)->PIO_OWER = (mask) << (offset); \ - (port)->PIO_ODSR = (bits) << (offset); \ - (port)->PIO_OWDR = (mask) << (offset); \ -} - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -/** - * @brief Writes a logical state on an output pad. - * - * @param[in] port the port identifier - * @param[in] pad the pad number within the port - * @param[out] bit the logical value, the value must be @p 0 or @p 1 - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/platform.dox deleted file mode 100644 index 485e132..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/platform.dox +++ /dev/null @@ -1,100 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup AT91SAM7 AT91SAM7 Support - * @brief AT91SAM7 specific support. - * @details The AT91SAM7 support includes: - * - Buffered, interrupt driven, serial driver. - * - EMAC driver with MII support. - * - A demo supporting the kernel test suite. - * - A Web server demo using the uIP TCP/IP stack. - * - A Web server demo using the lwIP TCP/IP stack. - * . - * @ingroup ARM7 - */ - -/** - * @defgroup AT91SAM7_HAL AT91SAM7 HAL Support - * @brief HAL support. - * - * @ingroup AT91SAM7 - */ - -/** - * @defgroup AT91SAM7_PAL AT91SAM7 I/O Ports Support - * @brief I/O Ports peripherals support. - * @details This module supports the AT91SAM7 PIO controller. The controller - * supports the following features (see @ref PAL): - * - 32 bits wide ports. - * - Atomic set/reset functions. - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - *

Supported Setup Modes

- * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT). - * - @p PAL_MODE_INPUT_PULLUP. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * . - * Any attempt to setup an invalid mode is ignored. - * - *

Suboptimal Behavior

- * Some PIO features are less than optimal: - * - Pad/port toggling operations are not atomic. - * - Pad/group mode setup is not atomic. - * . - * @ingroup AT91SAM7 - */ - -/** - * @defgroup AT91SAM7_SERIAL AT91SAM7 USART Support - * @brief USART peripherals support. - * @details The serial driver supports the AT91SAM7 USART peripherals. - * - * @ingroup AT91SAM7 - */ - -/** - * @defgroup AT91SAM7_MAC AT91SAM7 EMAC Support - * @brief EMAC peripheral support. - * @details the @ref MAC supports the AT91SAM7 EMAC peripheral. - * - * @ingroup AT91SAM7 - */ - -/** - * @defgroup AT91SAM7_MII AT91SAM7 MII Support - * @brief EMAC+PHY peripheral support. - * @details This driver supports the AT91SAM7 EMAC peripheral communicating - * with an external PHY transceiver. The driver currently supports - * the Micrel KS8721 PHY and the Davicom DV9161 modules. - * - * @ingroup AT91SAM7 - */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/platform.mk deleted file mode 100644 index d72b4a1..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/platform.mk +++ /dev/null @@ -1,10 +0,0 @@ -# List of all the AT91SAM7 platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AT91SAM7/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/AT91SAM7/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/AT91SAM7/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/AT91SAM7/mac_lld.c \ - ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91sam7_mii.c \ - ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91lib/aic.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AT91SAM7 diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/serial_lld.c deleted file mode 100644 index 6c2d4b9..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/serial_lld.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/serial_lld.c - * @brief AT91SAM7 low level serial driver code. - * - * @addtogroup AT91SAM7_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -#if SAM7_PLATFORM == SAM7S256 - -#define SAM7_USART0_RX AT91C_PA5_RXD0 -#define SAM7_USART0_TX AT91C_PA6_TXD0 -#define SAM7_USART1_RX AT91C_PA21_RXD1 -#define SAM7_USART1_TX AT91C_PA22_TXD1 -#define SAM7_DBGU_RX AT91C_PA9_DRXD -#define SAM7_DBGU_TX AT91C_PA10_DTXD - -#elif SAM7_PLATFORM == SAM7X256 - -#define SAM7_USART0_RX AT91C_PA0_RXD0 -#define SAM7_USART0_TX AT91C_PA1_TXD0 -#define SAM7_USART1_RX AT91C_PA5_RXD1 -#define SAM7_USART1_TX AT91C_PA6_TXD1 -#define SAM7_DBGU_RX AT91C_PA27_DRXD -#define SAM7_DBGU_TX AT91C_PA28_DTXD - -#else -#error "serial lines not defined for this SAM7 version" -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if USE_SAM7_USART0 || defined(__DOXYGEN__) -/** @brief USART0 serial driver identifier.*/ -SerialDriver SD1; -#endif - -#if USE_SAM7_USART1 || defined(__DOXYGEN__) -/** @brief USART1 serial driver identifier.*/ -SerialDriver SD2; -#endif - -#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__) -/** @brief DBGU_UART serial driver identifier.*/ -SerialDriver SD3; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { - SERIAL_DEFAULT_BITRATE, - AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | - AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief USART initialization. - * - * @param[in] sdp communication channel associated to the USART - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config) { - AT91PS_USART u = sdp->usart; - - /* Disables IRQ sources and stop operations.*/ - u->US_IDR = 0xFFFFFFFF; - u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA; - - /* New parameters setup.*/ - if (config->sc_mr & AT91C_US_OVER) - u->US_BRGR = MCK / (config->sc_speed * 8); - else - u->US_BRGR = MCK / (config->sc_speed * 16); - u->US_MR = config->sc_mr; - u->US_RTOR = 0; - u->US_TTGR = 0; - - /* Enables operations and IRQ sources.*/ - u->US_CR = AT91C_US_RXEN | AT91C_US_TXEN | AT91C_US_DTREN | AT91C_US_RTSEN; - u->US_IER = AT91C_US_RXRDY | AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | - AT91C_US_RXBRK; -} - -/** - * @brief USART de-initialization. - * - * @param[in] u pointer to an USART I/O block - */ -static void usart_deinit(AT91PS_USART u) { - - /* Disables IRQ sources and stop operations.*/ - u->US_IDR = 0xFFFFFFFF; - u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA; - u->US_MR = 0; - u->US_RTOR = 0; - u->US_TTGR = 0; -} - -/** - * @brief Error handling routine. - * - * @param[in] err USART CSR register value - * @param[in] sdp communication channel associated to the USART - */ -static void set_error(SerialDriver *sdp, AT91_REG csr) { - sdflags_t sts = 0; - - if (csr & AT91C_US_OVRE) - sts |= SD_OVERRUN_ERROR; - if (csr & AT91C_US_PARE) - sts |= SD_PARITY_ERROR; - if (csr & AT91C_US_FRAME) - sts |= SD_FRAMING_ERROR; - if (csr & AT91C_US_RXBRK) - sts |= SD_BREAK_DETECTED; - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -#if defined(__GNUC__) -__attribute__((noinline)) -#endif -#if !USE_SAM7_DBGU_UART -static -#endif -/** - * @brief Common IRQ handler. - * - * @param[in] sdp communication channel associated to the USART - */ -void sd_lld_serve_interrupt(SerialDriver *sdp) { - uint32_t csr; - AT91PS_USART u = sdp->usart; - - csr = u->US_CSR; - if (csr & AT91C_US_RXRDY) { - chSysLockFromIsr(); - sdIncomingDataI(sdp, u->US_RHR); - chSysUnlockFromIsr(); - } - if ((u->US_IMR & AT91C_US_TXRDY) && (csr & AT91C_US_TXRDY)) { - msg_t b; - - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chEvtBroadcastI(&sdp->oevent); - u->US_IDR = AT91C_US_TXRDY; - } - else - u->US_THR = b; - chSysUnlockFromIsr(); - } - csr &= (AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | AT91C_US_RXBRK); - if (csr != 0) { - set_error(sdp, csr); - u->US_CR = AT91C_US_RSTSTA; - } - AT91C_BASE_AIC->AIC_EOICR = 0; -} - -#if USE_SAM7_USART0 || defined(__DOXYGEN__) -static void notify1(void) { - - AT91C_BASE_US0->US_IER = AT91C_US_TXRDY; -} -#endif - -#if USE_SAM7_USART1 || defined(__DOXYGEN__) -static void notify2(void) { - - AT91C_BASE_US1->US_IER = AT91C_US_TXRDY; -} -#endif - -#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__) -static void notify3(void) { - - AT91C_BASE_DBGU->DBGU_IER = AT91C_US_TXRDY; -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_SAM7_USART0 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(USART0IrqHandler) { - - CH_IRQ_PROLOGUE(); - sd_lld_serve_interrupt(&SD1); - AT91C_BASE_AIC->AIC_EOICR = 0; - CH_IRQ_EPILOGUE(); -} -#endif - -#if USE_SAM7_USART1 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(USART1IrqHandler) { - - CH_IRQ_PROLOGUE(); - sd_lld_serve_interrupt(&SD2); - AT91C_BASE_AIC->AIC_EOICR = 0; - CH_IRQ_EPILOGUE(); -} -#endif - -// note - DBGU_UART IRQ is the SysIrq in board.c -// since it's not vectored separately by the AIC - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_SAM7_USART0 - sdObjectInit(&SD1, NULL, notify1); - SD1.usart = AT91C_BASE_US0; - AT91C_BASE_PIOA->PIO_PDR = SAM7_USART0_RX | SAM7_USART0_TX; - AT91C_BASE_PIOA->PIO_ASR = SAM7_USART0_RX | SAM7_USART0_TX; - AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART0_RX | SAM7_USART0_TX; - AIC_ConfigureIT(AT91C_ID_US0, - AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART0_PRIORITY, - USART0IrqHandler); -#endif - -#if USE_SAM7_USART1 - sdObjectInit(&SD2, NULL, notify2); - SD2.usart = AT91C_BASE_US1; - AT91C_BASE_PIOA->PIO_PDR = SAM7_USART1_RX | SAM7_USART1_TX; - AT91C_BASE_PIOA->PIO_ASR = SAM7_USART1_RX | SAM7_USART1_TX; - AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART1_RX | SAM7_USART1_TX; - AIC_ConfigureIT(AT91C_ID_US1, - AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART1_PRIORITY, - USART1IrqHandler); -#endif - -#if USE_SAM7_DBGU_UART - sdObjectInit(&SD3, NULL, notify3); - // this is a little cheap, but OK for now since there's enough overlap - // between dbgu and usart register maps. it means we can reuse all the - // same usart interrupt handling and config that already exists - SD3.usart = (AT91PS_USART)AT91C_BASE_DBGU; - AT91C_BASE_PIOA->PIO_PDR = SAM7_DBGU_RX | SAM7_DBGU_TX; - AT91C_BASE_PIOA->PIO_ASR = SAM7_DBGU_RX | SAM7_DBGU_TX; - AT91C_BASE_PIOA->PIO_PPUDR = SAM7_DBGU_RX | SAM7_DBGU_TX; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if USE_SAM7_USART0 - if (&SD1 == sdp) { - /* Starts the clock and clears possible sources of immediate interrupts.*/ - AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US0); - /* Enables associated interrupt vector.*/ - AIC_EnableIT(AT91C_ID_US0); - } -#endif -#if USE_SAM7_USART1 - if (&SD2 == sdp) { - /* Starts the clock and clears possible sources of immediate interrupts.*/ - AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US1); - /* Enables associated interrupt vector.*/ - AIC_EnableIT(AT91C_ID_US1); - } -#endif - // note - no explicit start for SD3 (DBGU_UART) since it's not included in the AIC or PMC - } - usart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - usart_deinit(sdp->usart); -#if USE_SAM7_USART0 - if (&SD1 == sdp) { - AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US0); - AIC_DisableIT(AT91C_ID_US0); - return; - } -#endif -#if USE_SAM7_USART1 - if (&SD2 == sdp) { - AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US1); - AIC_DisableIT(AT91C_ID_US1); - return; - } -#endif -#if USE_SAM7_DBGU_UART - if (&SD3 == sdp) { - AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF; - return; - } -#endif - } -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/serial_lld.h deleted file mode 100644 index 190b3f6..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AT91SAM7/serial_lld.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AT91SAM7/serial_lld.h - * @brief AT91SAM7 low level serial driver header. - * - * @addtogroup AT91SAM7_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UART0 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SAM7_USART0) || defined(__DOXYGEN__) -#define USE_SAM7_USART0 TRUE -#endif - -/** - * @brief UART1 driver enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SAM7_USART1) || defined(__DOXYGEN__) -#define USE_SAM7_USART1 TRUE -#endif - -/** - * @brief DBGU UART driver enable switch. - * @details If set to @p TRUE the support for the DBGU UART is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SAM7_DBGU_UART) || defined(__DOXYGEN__) -#define USE_SAM7_DBGU_UART TRUE -#endif - -/** - * @brief UART1 interrupt priority level setting. - */ -#if !defined(SAM7_USART0_PRIORITY) || defined(__DOXYGEN__) -#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) -#endif - -/** - * @brief UART2 interrupt priority level setting. - */ -#if !defined(SAM7_USART1_PRIORITY) || defined(__DOXYGEN__) -#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) -#endif - -/** - * @brief DBGU_UART interrupt priority level setting. - */ -#if !defined(SAM7_DBGU_UART_PRIORITY) || defined(__DOXYGEN__) -#define SAM7_DBGU_UART_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint32_t sdflags_t; - -/** - * @brief AT91SAM7 Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Bit rate. - * @details This is written to the US_BRGR register of the appropriate AT91S_USART - */ - uint32_t sc_speed; - /** - * @brief Initialization value for the MR register. - * @details This is written to the US_MR register of the appropriate AT91S_USART - */ - uint32_t sc_mr; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - AT91PS_USART usart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_SAM7_USART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_SAM7_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif -#if USE_SAM7_DBGU_UART -extern SerialDriver SD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#if USE_SAM7_DBGU_UART - void sd_lld_serve_interrupt(SerialDriver *sdp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AVR/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/AVR/hal_lld.c deleted file mode 100644 index fb753af..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AVR/hal_lld.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AVR/hal_lld.c - * @brief AVR HAL subsystem low level driver code. - * @addtogroup AVR_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AVR/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/AVR/hal_lld.h deleted file mode 100644 index 8da810e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AVR/hal_lld.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AVR/hal_lld.h - * @brief AVR HAL subsystem low level driver header. - * @addtogroup AVR_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "ATmega128" - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AVR/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/AVR/platform.dox deleted file mode 100644 index 46c9c2a..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AVR/platform.dox +++ /dev/null @@ -1,48 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup AVR_DRIVERS AVR Drivers - * @brief Device drivers included in the AVR support. - * - * @ingroup AVR - */ - -/** - * @defgroup AVR_HAL AVR HAL Support - * @brief HAL support. - * - * @ingroup AVR_DRIVERS - */ - -/** - * @defgroup AVR_SERIAL AVR USART Support - * @brief USART support. - * @details The serial driver supports both the AVR USARTs in asynchronous - * mode. - * - * @ingroup AVR_DRIVERS - */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AVR/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/AVR/platform.mk deleted file mode 100644 index f9d8120..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AVR/platform.mk +++ /dev/null @@ -1,6 +0,0 @@ -# List of all the AVR platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AVR/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/AVR/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AVR diff --git a/ChibiOS_2.0.8/os/hal/platforms/AVR/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/AVR/serial_lld.c deleted file mode 100644 index 40d27aa..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AVR/serial_lld.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AVR/serial_lld.c - * @brief AVR low level serial driver code. - * - * @addtogroup AVR_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief USART0 serial driver identifier. - * @note The name does not follow the convention used in the other ports - * (COMn) because a name conflict with the AVR headers. - */ -#if USE_AVR_USART0 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** - * @brief USART1 serial driver identifier. - * @note The name does not follow the convention used in the other ports - * (COMn) because a name conflict with the AVR headers. - */ -#if USE_AVR_USART1 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static const SerialConfig default_config = { - UBRR(SERIAL_DEFAULT_BITRATE), - (1 << UCSZ1) | (1 << UCSZ0) -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void set_error(uint8_t sra, SerialDriver *sdp) { - sdflags_t sts = 0; - - if (sra & (1 << DOR)) - sts |= SD_OVERRUN_ERROR; - if (sra & (1 << UPE)) - sts |= SD_PARITY_ERROR; - if (sra & (1 << FE)) - sts |= SD_FRAMING_ERROR; - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -#if USE_AVR_USART0 || defined(__DOXYGEN__) -static void notify1(void) { - - UCSR0B |= (1 << UDRIE); -} - -/** - * @brief USART0 initialization. - * - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart0_init(const SerialConfig *config) { - - UBRR0L = config->sc_brr; - UBRR0H = config->sc_brr >> 8; - UCSR0A = 0; - UCSR0B = (1 << RXEN) | (1 << TXEN) | (1 << RXCIE); - UCSR0C = config->sc_csrc; -} - -/** - * @brief USART0 de-initialization. - */ -static void usart0_deinit(void) { - - UCSR0A = 0; - UCSR0B = 0; - UCSR0C = 0; -} -#endif - -#if USE_AVR_USART1 || defined(__DOXYGEN__) -static void notify2(void) { - - UCSR1B |= (1 << UDRIE); -} - -/** - * @brief USART1 initialization. - * - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart1_init(const SerialConfig *config) { - - UBRR1L = config->sc_brr; - UBRR1H = config->sc_brr >> 8; - UCSR1A = 0; - UCSR1B = (1 << RXEN) | (1 << TXEN) | (1 << RXCIE); - UCSR1C = config->sc_csrc; -} - -/** - * @brief USART1 de-initialization. - */ -static void usart1_deinit(void) { - - UCSR1A = 0; - UCSR1B = 0; - UCSR1C = 0; -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_AVR_USART0 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(USART0_RX_vect) { - uint8_t sra; - - CH_IRQ_PROLOGUE(); - - sra = UCSR0A; - if (sra & ((1 << DOR) | (1 << UPE) | (1 << FE))) - set_error(sra, &SD1); - chSysLockFromIsr(); - sdIncomingDataI(&SD1, UDR0); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -CH_IRQ_HANDLER(USART0_UDRE_vect) { - msg_t b; - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - b = sdRequestDataI(&SER1); - chSysUnlockFromIsr(); - if (b < Q_OK) - UCSR0B &= ~(1 << UDRIE); - else - UDR0 = b; - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_AVR_USART0 */ - -#if USE_AVR_USART1 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(USART1_RX_vect) { - uint8_t sra; - - CH_IRQ_PROLOGUE(); - - sra = UCSR1A; - if (sra & ((1 << DOR) | (1 << UPE) | (1 << FE))) - set_error(sra, &SD2); - chSysLockFromIsr(); - sdIncomingDataI(&SD2, UDR1); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -CH_IRQ_HANDLER(USART1_UDRE_vect) { - msg_t b; - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - b = sdRequestDataI(&SD2); - chSysUnlockFromIsr(); - if (b < Q_OK) - UCSR1B &= ~(1 << UDRIE); - else - UDR1 = b; - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_AVR_USART1 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_AVR_USART0 - sdObjectInit(&SD1, NULL, notify1); -#endif -#if USE_AVR_USART1 - sdObjectInit(&SD2, NULL, notify2); -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -#if USE_AVR_USART0 - if (&SD1 == sdp) { - usart0_init(config); - return; - } -#endif -#if USE_AVR_USART1 - if (&SD2 == sdp) { - usart1_init(config); - return; - } -#endif -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - -#if USE_AVR_USART0 - if (&SD1 == sdp) - usart0_deinit(); -#endif -#if USE_AVR_USART1 - if (&SD2 == sdp) - usart1_deinit(); -#endif -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/AVR/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/AVR/serial_lld.h deleted file mode 100644 index 2f74324..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/AVR/serial_lld.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AVR/serial_lld.h - * @brief AVR low level serial driver header. - * - * @addtogroup AVR_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief USART0 driver enable switch. - * @details If set to @p TRUE the support for USART0 is included. - * @note The default is @p FALSE. - */ -#if !defined(USE_AVR_USART0) || defined(__DOXYGEN__) -#define USE_AVR_USART0 TRUE -#endif - -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_AVR_USART1) || defined(__DOXYGEN__) -#define USE_AVR_USART1 TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint8_t sdflags_t; - -/** - * @brief AVR Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Initialization value for the BRR register. - */ - uint16_t sc_brr; - /** - * @brief Initialization value for the CSRC register. - */ - uint8_t sc_csrc; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Macro for baud rate computation. - * @note Make sure the final baud rate is within tolerance. - */ -#define UBRR(b) ((F_CPU / (b << 4)) - 1) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_AVR_USART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_AVR_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/LPC11xx.h b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/LPC11xx.h deleted file mode 100644 index 6a6061a..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/LPC11xx.h +++ /dev/null @@ -1,499 +0,0 @@ -/**************************************************************************//** - * @file LPC11xx.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for - * NXP LPC11xx Device Series - * @version V1.00 - * @date 17. November 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __LPC11xx_H__ -#define __LPC11xx_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup LPC11xx_Definitions LPC11xx Definitions - This file defines all structures and symbols for LPC11xx: - - Registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions - @{ -*/ - - -/******************************************************************************/ -/* Processor and Core Peripherals */ -/******************************************************************************/ -/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions - Configuration of the Cortex-M0 Processor and Core Peripherals - @{ -*/ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** LPC13xx Specific Interrupt Numbers *******************************************************/ - WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ - WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */ - WAKEUP2_IRQn = 2, - WAKEUP3_IRQn = 3, - WAKEUP4_IRQn = 4, - WAKEUP5_IRQn = 5, - WAKEUP6_IRQn = 6, - WAKEUP7_IRQn = 7, - WAKEUP8_IRQn = 8, - WAKEUP9_IRQn = 9, - WAKEUP10_IRQn = 10, - WAKEUP11_IRQn = 11, - WAKEUP12_IRQn = 12, - SSP1_IRQn = 14, /*!< SSP1 Interrupt */ - I2C_IRQn = 15, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ - SSP0_IRQn = 20, /*!< SSP0 Interrupt */ - UART_IRQn = 21, /*!< UART Interrupt */ - ADC_IRQn = 24, /*!< A/D Converter Interrupt */ - WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ - EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */ - EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */ - EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */ - EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*@}*/ /* end of group LPC11xx_CMSIS */ - - -#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ -#include "system_LPC11xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SYSCON) --------------------------------------*/ -/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block - @{ -*/ -typedef struct -{ - __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ - __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ - __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ - __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */ - uint32_t RESERVED0[4]; - - __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ - __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ - __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */ - uint32_t RESERVED1[1]; - __IO uint32_t SYSRESSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ - __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ - uint32_t RESERVED3[10]; - - __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ - __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ - __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ - uint32_t RESERVED4[1]; - - __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ - uint32_t RESERVED5[4]; - __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */ - __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */ - __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */ - uint32_t RESERVED6[4]; - - __IO uint32_t SYSTICKCLKDIV; /*!< Offset: 0x0B0 SYSTICK clock divider (R/W) */ - uint32_t RESERVED7[7]; - - __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */ - __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */ - __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */ - uint32_t RESERVED8[1]; - __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ - __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ - __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ - uint32_t RESERVED9[5]; - - __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ - __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */ - uint32_t RESERVED10[18]; - - __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ - uint32_t RESERVED11[1]; - __IO uint32_t SYSTCKCAL; /*!< Offset: 0x158 System tick counter calibration (R/W) */ - uint32_t RESERVED12[41]; - - __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */ - __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ - __IO uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */ - __IO uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/W) */ - uint32_t RESERVED14[8]; - - __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ - __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ - __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ - uint32_t RESERVED15[110]; - __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ -} LPC_SYSCON_TypeDef; -/*@}*/ /* end of group LPC11xx_SYSCON */ - - -/*------------- Pin Connect Block (IOCON) --------------------------------*/ -/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block - @{ -*/ -typedef struct -{ - __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */ - uint32_t RESERVED0[1]; - __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */ - __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */ - __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */ - __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */ - uint32_t RESERVED1[1]; - __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */ - - __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */ - __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */ - __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */ - __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */ - __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */ - __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */ - __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */ - __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */ - - __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */ - __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */ - __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */ - __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */ - __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */ - __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */ - __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */ - __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */ - - __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */ - __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */ - __IO uint32_t JTAG_TCK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */ - __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */ - __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */ - __IO uint32_t JTAG_TDI_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */ - __IO uint32_t JTAG_TMS_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */ - __IO uint32_t JTAG_TDO_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */ - - __IO uint32_t JTAG_nTRST_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */ - __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */ - __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */ - __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */ - __IO uint32_t ARM_SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */ - __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */ - __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */ - __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */ - - __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */ - __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */ - __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */ - __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */ - __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */ - __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */ - __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */ - __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */ -} LPC_IOCON_TypeDef; -/*@}*/ /* end of group LPC11xx_IOCON */ - - -/*------------- Power Management Unit (PMU) --------------------------*/ -/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit - @{ -*/ -typedef struct -{ - __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ - __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ - __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ - __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ - __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ - __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */ -} LPC_PMU_TypeDef; -/*@}*/ /* end of group LPC11xx_PMU */ - - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output - @{ -*/ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */ - struct { - uint32_t RESERVED0[4095]; - __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */ - }; - }; - uint32_t RESERVED1[4096]; - __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */ - __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */ - __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */ - __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */ - __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */ - __IO uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */ - __IO uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */ - __IO uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (R/W) */ -} LPC_GPIO_TypeDef; -/*@}*/ /* end of group LPC11xx_GPIO */ - - -/*------------- Timer (TMR) --------------------------------------------------*/ -/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer - @{ -*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - uint32_t RESERVED1[3]; - __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ - uint32_t RESERVED2[12]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ - __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */ -} LPC_TMR_TypeDef; -/*@}*/ /* end of group LPC11xx_TMR */ - - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter - @{ -*/ -typedef struct -{ - union { - __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ - __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ - __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ - }; - union { - __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ - __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ - }; - union { - __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ - __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ - }; - __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ - __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ - __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ - __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ - __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ - uint32_t RESERVED1; - __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ - uint32_t RESERVED2[6]; - __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ - __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ - __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ - __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R/ ) */ -} LPC_UART_TypeDef; -/*@}*/ /* end of group LPC11xx_UART */ - - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port - @{ -*/ -typedef struct -{ - __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ - __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ - __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ - __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ - __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ - __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ - __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ - __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ - __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ -} LPC_SSP_TypeDef; -/*@}*/ /* end of group LPC11xx_SSP */ - - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface - @{ -*/ -typedef struct -{ - __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ - __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ - __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ - __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ - __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ - __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ - __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ - __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ - __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ - __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ - __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ - __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ - __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ - __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ - __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ -} LPC_I2C_TypeDef; -/*@}*/ /* end of group LPC11xx_I2C */ - - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer - @{ -*/ -typedef struct -{ - __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ - __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register ( /W) */ - __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R/ ) */ -} LPC_WDT_TypeDef; -/*@}*/ /* end of group LPC11xx_WDT */ - - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter - @{ -*/ -typedef struct -{ - __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ - __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ - __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ -} LPC_ADC_TypeDef; -/*@}*/ /* end of group LPC11xx_ADC */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000) - -/* AHB peripherals */ -#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) -#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) -#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) -#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) -#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC11xx_H__ */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/hal_lld.c deleted file mode 100644 index 0c47b99..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/hal_lld.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC11xx/hal_lld.c - * @brief LPC11xx HAL subsystem low level driver source. - * - * @addtogroup LPC11xx_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/** - * @brief Register missing in NXP header file. - */ -#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -const PALConfig pal_default_config = { - {VAL_GPIO0DATA, VAL_GPIO0DIR}, - {VAL_GPIO1DATA, VAL_GPIO1DIR}, - {VAL_GPIO2DATA, VAL_GPIO2DIR}, - {VAL_GPIO3DATA, VAL_GPIO3DIR}, -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - - /* SysTick initialization using the system clock.*/ - NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); - SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief LPC11xx clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - */ -void lpc111x_clock_init(void) { - unsigned i; - - /* Flash wait states setting, the code takes care to not touch TBD bits.*/ - FLASHCFG = (FLASHCFG & ~3) | LPC11xx_FLASHCFG_FLASHTIM; - - /* System oscillator initialization if required.*/ -#if LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT -#if LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC - LPC_SYSCON->SYSOSCCTRL = LPC11xx_SYSOSCCTRL; - LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ - for (i = 0; i < 200; i++) - __NOP(); /* Stabilization delay. */ -#endif /* LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ - - /* PLL initialization if required.*/ - LPC_SYSCON->SYSPLLCLKSEL = LPC11xx_PLLCLK_SOURCE; - LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ - LPC_SYSCON->SYSPLLCLKUEN = 0; - LPC_SYSCON->SYSPLLCLKUEN = 1; - LPC_SYSCON->SYSPLLCTRL = LPC11xx_SYSPLLCTRL_MSEL | LPC11xx_SYSPLLCTRL_PSEL; - LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ - while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ - ; -#endif /* LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ - - /* Main clock source selection.*/ - LPC_SYSCON->MAINCLKSEL = LPC11xx_MAINCLK_SOURCE; - LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ - LPC_SYSCON->MAINCLKUEN = 0; - LPC_SYSCON->MAINCLKUEN = 1; - while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ - ; - - /* ABH divider initialization, peripheral clocks are initially disabled, - the various device drivers will handle their own setup except GPIO and - IOCON that are left enabled.*/ - LPC_SYSCON->SYSAHBCLKDIV = LPC11xx_SYSABHCLK_DIV; - LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; - - /* Peripheral clock dividers initialization.*/ - LPC_SYSCON->UARTCLKDIV = LPC11xx_UART_PCLK_DIV; - - /* Memory remapping, vectors always in ROM.*/ - LPC_SYSCON->SYSMEMREMAP = 2; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/hal_lld.h deleted file mode 100644 index 94f8648..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/hal_lld.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC11xx/hal_lld.h - * @brief HAL subsystem low level driver header template. - * - * @addtogroup LPC11xx_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "LPC11xx.h" -#include "nvic.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "LPC11xx" - -#define IRCOSCCLK 12000000 /**< High speed internal clock. */ -#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ - -#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator - clock source. */ -#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock - source. */ - -#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ -#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ -#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ -#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief System PLL clock source. - */ -#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) -#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC -#endif - -/** - * @brief System PLL multiplier. - * @note The value must be in the 1..32 range and the final frequency - * must not exceed the CCO ratings. - */ -#if !defined(LPC11xx_SYSPLL_MUL) || defined(__DOXYGEN__) -#define LPC11xx_SYSPLL_MUL 4 -#endif - -/** - * @brief System PLL divider. - * @note The value must be chosen between (2, 4, 8, 16). - */ -#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__) -#define LPC11xx_SYSPLL_DIV 4 -#endif - -/** - * @brief System main clock source. - */ -#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) -#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT -#endif - -/** - * @brief AHB clock divider. - * @note The value must be chosen between (1...255). - */ -#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__) -#define LPC11xx_SYSABHCLK_DIV 1 -#endif - -/** - * @brief UART clock divider. - * @note The value must be chosen between (1...255). - */ -#if !defined(LPC11xx_UART_PCLK_DIV) || defined(__DOXYGEN__) -#define LPC11xx_UART_PCLK_DIV 1 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief Calculated SYSOSCCTRL setting. - */ -#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) -#define LPC11xx_SYSOSCCTRL 0 -#else -#define LPC11xx_SYSOSCCTRL 1 -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) -#define LPC11xx_SYSPLLCLKIN SYSOSCCLK -#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS -#define LPC11xx_SYSPLLCLKIN IRCOSCCLK -#else -#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified" -#endif - -/** - * @brief MSEL mask in SYSPLLCTRL register. - */ -#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) || \ - defined(__DOXYGEN__) -#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1) -#else -#error "LPC11xx_SYSPLL_MUL out of range (1...32)" -#endif - -/** - * @brief PSEL mask in SYSPLLCTRL register. - */ -#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) -#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5) -#elif LPC11xx_SYSPLL_DIV == 4 -#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5) -#elif LPC11xx_SYSPLL_DIV == 8 -#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5) -#elif LPC11xx_SYSPLL_DIV == 16 -#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5) -#else -#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)" -#endif - -/** - * @brief CCP frequency. - */ -#define LPC11xx_SYSPLLCCO (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL * \ - LPC11xx_SYSPLL_DIV) - -#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000) -#error "CCO frequency out of the acceptable range (156...320)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define LPC11xx_SYSPLLCLKOUT (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV) - -#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__) -#define LPC11xx_MAINCLK IRCOSCCLK -#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN -#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKIN -#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC -#define LPC11xx_MAINCLK WDGOSCCLK -#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT -#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKOUT -#else -#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified" -#endif - -/** - * @brief AHB clock. - */ -#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV) -#if LPC11xx_SYSCLK > 50000000 -#error "AHB clock frequency out of the acceptable range (50MHz max)" -#endif - -/** - * @brief Flash wait states. - */ -#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) -#define LPC11xx_FLASHCFG_FLASHTIM 0 -#elif LPC11xx_SYSCLK <= 40000000 -#define LPC11xx_FLASHCFG_FLASHTIM 1 -#else -#define LPC11xx_FLASHCFG_FLASHTIM 2 -#endif - -/** - * @brief UART clock. - */ -#define LPC11xx_UART_PCLK (LPC11xx_MAINCLK / LPC11xx_UART_PCLK_DIV) - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void lpc111x_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/pal_lld.c deleted file mode 100644 index d6766e4..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/pal_lld.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC11xx/pal_lld.c - * @brief LPC11xx GPIO low level driver code. - * - * @addtogroup LPC11xx_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ -/** - * @brief LPC11xx I/O ports configuration. - * @details GPIO unit registers initialization. - * - * @param[in] config the LPC11xx ports configuration - */ -void _pal_lld_init(const PALConfig *config) { - - LPC_GPIO0->DIR = config->P0.dir; - LPC_GPIO1->DIR = config->P1.dir; - LPC_GPIO2->DIR = config->P2.dir; - LPC_GPIO3->DIR = config->P3.dir; - LPC_GPIO0->DATA = config->P0.data; - LPC_GPIO1->DATA = config->P1.data; - LPC_GPIO2->DATA = config->P2.data; - LPC_GPIO3->DATA = config->P3.data; -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - - switch (mode & PAL_MODE_MASK) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->DIR &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - palSetPort(port, PAL_WHOLE_PORT); - case PAL_MODE_OUTPUT_PUSHPULL: - port->DIR |= mask; - break; - } -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/pal_lld.h deleted file mode 100644 index 6aecdda..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/pal_lld.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC11xx/pal_lld.h - * @brief LPC11xx GPIO low level driver header. - * - * @addtogroup LPC11xx_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for FIO_PIN register.*/ - uint32_t data; - /** Initial value for FIO_DIR register.*/ - uint32_t dir; -} lpc111x_gpio_setup_t; - -/** - * @brief GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - * @note The @p IOCON block is not configured, initially all pins have - * enabled pullups and are programmed as GPIO. It is responsibility - * of the various drivers to reprogram the pins in the proper mode. - * Pins that are not handled by any driver may be programmed in - * @p board.c. - */ -typedef struct { - /** @brief GPIO 0 setup data.*/ - lpc111x_gpio_setup_t P0; - /** @brief GPIO 1 setup data.*/ - lpc111x_gpio_setup_t P1; - /** @brief GPIO 2 setup data.*/ - lpc111x_gpio_setup_t P2; - /** @brief GPIO 3 setup data.*/ - lpc111x_gpio_setup_t P3; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Port Identifier. - */ -typedef LPC_GPIO_TypeDef *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief GPIO0 port identifier. - */ -#define IOPORT1 LPC_GPIO0 -#define GPIO0 LPC_GPIO0 - -/** - * @brief GPIO1 port identifier. - */ -#define IOPORT2 LPC_GPIO1 -#define GPIO1 LPC_GPIO1 - -/** - * @brief GPIO2 port identifier. - */ -#define IOPORT3 LPC_GPIO2 -#define GPIO2 LPC_GPIO2 - -/** - * @brief GPIO3 port identifier. - */ -#define IOPORT4 LPC_GPIO3 -#define GPIO3 LPC_GPIO3 - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The port bits. - */ -#define pal_lld_readport(port) ((port)->DATA) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The latched logical states. - */ -#define pal_lld_readlatch(port) ((port)->DATA) - -/** - * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - */ -#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF) - -/** - * @brief Clears a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - */ -#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) - -/** - * @brief Reads a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @return The group logical states. - */ -#define pal_lld_readgroup(port, mask, offset) \ - ((port)->MASKED_ACCESS[(mask) << (offset)]) - -/** - * @brief Writes a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group width - * are masked. - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] mode group mode - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[out] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - */ -#define pal_lld_writepad(port, pad, bit) \ - ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad)) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#define pal_lld_setpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#define pal_lld_clearpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 0) - -#if !defined(__DOXYGEN__) -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/platform.dox deleted file mode 100644 index ad9cf0f..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/platform.dox +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup LPC11xx LPC11xx Support - * @brief LPC11xx specific support. - * @details The LPC11xx support includes: - * - I/O ports driver. - * - Buffered, interrupt driven, serial driver. - * - A demo supporting the kernel test suite. - * . - * @ingroup ARMCMx - */ - -/** - * @defgroup LPC11xx_HAL LPC11xx HAL Support - * @brief HAL support. - * - * @ingroup LPC11xx - */ - -/** - * @defgroup LPC11xx_PAL LPC11xx I/O Ports Support - * @brief I/O Ports peripherals support. - * @details This module supports the LPC11xx GPIO controller. The controller - * supports the following features (see @ref PAL): - * - 12 bits wide ports. - * - Atomic set/reset functions. - * - Atomic set+reset function (atomic bus operations). - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - *

Supported Setup Modes

- * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * . - * Any attempt to setup an invalid mode is ignored. - * - *

Suboptimal Behavior

- * Some GPIO features are less than optimal: - * - Pad/port toggling operations are not atomic. - * - Pull-up and Pull-down resistors cannot be programmed through the PAL - * driver and must be programmed separately. - * - Reading of the output latch for pads programmed as input is not possible, - * the input pin value is returned instead. - * . - * @ingroup LPC11xx - */ - -/** - * @defgroup LPC11xx_SERIAL LPC11xx UART Support - * @brief UART peripherals support. - * @details The serial driver supports the LPC11xx UART taking advantage of - * its deep hardware buffers. - * - * @ingroup LPC11xx - */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/platform.mk deleted file mode 100644 index 82875a6..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/platform.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of all the LPC11xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11xx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC11xx/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC11xx/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC11xx diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/serial_lld.c deleted file mode 100644 index 55a5295..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/serial_lld.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC11xx/serial_lld.c - * @brief LPC11xx low level serial driver code. - * - * @addtogroup LPC11xx_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if USE_LPC11xx_UART0 || defined(__DOXYGEN__) -/** @brief UART0 serial driver identifier.*/ -SerialDriver SD1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { - SERIAL_DEFAULT_BITRATE, - LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, - FCR_TRIGGER0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief UART initialization. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] config the architecture-dependent serial driver configuration - */ -static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - LPC_UART_TypeDef *u = sdp->uart; - - uint32_t div = LPC11xx_UART_PCLK / (config->sc_speed << 4); - u->LCR = config->sc_lcr | LCR_DLAB; - u->DLL = div; - u->DLM = div >> 8; - u->LCR = config->sc_lcr; - u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; - u->ACR = 0; - u->FDR = 0x10; - u->TER = TER_ENABLE; - u->IER = IER_RBR | IER_STATUS; -} - -/** - * @brief UART de-initialization. - * - * @param[in] u pointer to an UART I/O block - */ -static void uart_deinit(LPC_UART_TypeDef *u) { - - u->LCR = LCR_DLAB; - u->DLL = 1; - u->DLM = 0; - u->LCR = 0; - u->FDR = 0x10; - u->IER = 0; - u->FCR = FCR_RXRESET | FCR_TXRESET; - u->ACR = 0; - u->TER = TER_ENABLE; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] err UART LSR register value - */ -static void set_error(SerialDriver *sdp, IOREG32 err) { - sdflags_t sts = 0; - - if (err & LSR_OVERRUN) - sts |= SD_OVERRUN_ERROR; - if (err & LSR_PARITY) - sts |= SD_PARITY_ERROR; - if (err & LSR_FRAMING) - sts |= SD_FRAMING_ERROR; - if (err & LSR_BREAK) - sts |= SD_BREAK_DETECTED; - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -/** - * @brief Common IRQ handler. - * @note Tries hard to clear all the pending interrupt sources, we don't - * want to go through the whole ISR and have another interrupt soon - * after. - * - * @param[in] u pointer to an UART I/O block - * @param[in] sdp communication channel associated to the UART - */ -static void serve_interrupt(SerialDriver *sdp) { - LPC_UART_TypeDef *u = sdp->uart; - - while (TRUE) { - switch (u->IIR & IIR_SRC_MASK) { - case IIR_SRC_NONE: - return; - case IIR_SRC_ERROR: - set_error(sdp, u->LSR); - break; - case IIR_SRC_TIMEOUT: - case IIR_SRC_RX: - chSysLockFromIsr(); - if (chIQIsEmpty(&sdp->iqueue)) - chEvtBroadcastI(&sdp->ievent); - chSysUnlockFromIsr(); - while (u->LSR & LSR_RBR_FULL) { - chSysLockFromIsr(); - if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) - sdAddFlagsI(sdp, SD_OVERRUN_ERROR); - chSysUnlockFromIsr(); - } - break; - case IIR_SRC_TX: - { - int i = LPC11xx_UART_FIFO_PRELOAD; - do { - msg_t b; - - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - chSysUnlockFromIsr(); - if (b < Q_OK) { - u->IER &= ~IER_THRE; - chSysLockFromIsr(); - chEvtBroadcastI(&sdp->oevent); - chSysUnlockFromIsr(); - break; - } - u->THR = b; - } while (--i); - } - break; - default: - (void) u->THR; - (void) u->RBR; - } - } -} - -/** - * @brief Attempts a TX FIFO preload. - */ -static void preload(SerialDriver *sdp) { - LPC_UART_TypeDef *u = sdp->uart; - - if (u->LSR & LSR_THRE) { - int i = LPC11xx_UART_FIFO_PRELOAD; - do { - msg_t b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chEvtBroadcastI(&sdp->oevent); - return; - } - u->THR = b; - } while (--i); - } - u->IER |= IER_THRE; -} - -/** - * @brief Driver SD1 output notification. - */ -#if USE_LPC11xx_UART0 || defined(__DOXYGEN__) -static void notify1(void) { - - preload(&SD1); -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief UART0 IRQ handler. - */ -#if USE_LPC11xx_UART0 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(Vector94) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_LPC11xx_UART0 - sdObjectInit(&SD1, NULL, notify1); - SD1.uart = LPC_UART; - LPC_IOCON->PIO1_6 = 0xC1; /* RDX without resistors. */ - LPC_IOCON->PIO1_7 = 0xC1; /* TDX without resistors. */ -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if USE_LPC11xx_UART0 - if (&SD1 == sdp) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); - NVICEnableVector(UART_IRQn, - CORTEX_PRIORITY_MASK(LPC11xx_UART0_PRIORITY)); - } -#endif - } - uart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the UART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - uart_deinit(sdp->uart); -#if USE_LPC11xx_UART0 - if (&SD1 == sdp) { - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); - NVICDisableVector(UART_IRQn); - return; - } -#endif - } -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/serial_lld.h deleted file mode 100644 index 7805118..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/serial_lld.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC11xx/serial_lld.h - * @brief LPC11xx low level serial driver header. - * - * @addtogroup LPC11xx_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define IIR_SRC_MASK 0x0F -#define IIR_SRC_NONE 0x01 -#define IIR_SRC_MODEM 0x00 -#define IIR_SRC_TX 0x02 -#define IIR_SRC_RX 0x04 -#define IIR_SRC_ERROR 0x06 -#define IIR_SRC_TIMEOUT 0x0C - -#define IER_RBR 1 -#define IER_THRE 2 -#define IER_STATUS 4 - -#define LCR_WL5 0 -#define LCR_WL6 1 -#define LCR_WL7 2 -#define LCR_WL8 3 -#define LCR_STOP1 0 -#define LCR_STOP2 4 -#define LCR_NOPARITY 0 -#define LCR_PARITYODD 0x08 -#define LCR_PARITYEVEN 0x18 -#define LCR_PARITYONE 0x28 -#define LCR_PARITYZERO 0x38 -#define LCR_BREAK_ON 0x40 -#define LCR_DLAB 0x80 - -#define FCR_ENABLE 1 -#define FCR_RXRESET 2 -#define FCR_TXRESET 4 -#define FCR_TRIGGER0 0 -#define FCR_TRIGGER1 0x40 -#define FCR_TRIGGER2 0x80 -#define FCR_TRIGGER3 0xC0 - -#define LSR_RBR_FULL 1 -#define LSR_OVERRUN 2 -#define LSR_PARITY 4 -#define LSR_FRAMING 8 -#define LSR_BREAK 0x10 -#define LSR_THRE 0x20 -#define LSR_TEMT 0x40 -#define LSR_RXFE 0x80 - -#define TER_ENABLE 0x80 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UART0 driver enable switch. - * @details If set to @p TRUE the support for UART0 is included. - * @note The default is @p TRUE . - */ -#if !defined(USE_LPC11xx_UART0) || defined(__DOXYGEN__) -#define USE_LPC11xx_UART0 TRUE -#endif - -/** - * @brief FIFO preload parameter. - * @details Configuration parameter, this values defines how many bytes are - * preloaded in the HW transmit FIFO for each interrupt, the maximum - * value is 16 the minimum is 1. - * @note An high value reduces the number of interrupts generated but can - * also increase the worst case interrupt response time because the - * preload loops. - */ -#if !defined(LPC11xx_UART_FIFO_PRELOAD) || defined(__DOXYGEN__) -#define LPC11xx_UART_FIFO_PRELOAD 16 -#endif - -/** - * @brief UART0 interrupt priority level setting. - */ -#if !defined(LPC11xx_UART0_PRIORITY) || defined(__DOXYGEN__) -#define LPC11xx_UART0_PRIORITY 3 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (LPC11xx_UART_FIFO_PRELOAD < 1) || (LPC11xx_UART_FIFO_PRELOAD > 16) -#error "invalid LPC11xx_UART_FIFO_PRELOAD setting" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint32_t sdflags_t; - -/** - * @brief LPC11xx Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /** - * @brief Initialization value for the LCR register. - */ - uint32_t sc_lcr; - /** - * @brief Initialization value for the FCR register. - */ - uint32_t sc_fcr; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - LPC_UART_TypeDef *uart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_LPC11xx_UART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/system_LPC11xx.h b/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/system_LPC11xx.h deleted file mode 100644 index 4186707..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC11xx/system_LPC11xx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_LPC11xx.h - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File - * for the NXP LPC11xx Device Series - * @version V1.00 - * @date 17. November 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC11xx_H -#define __SYSTEM_LPC11xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC11x_H */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/LPC13xx.h b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/LPC13xx.h deleted file mode 100644 index 81a9b5f..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/LPC13xx.h +++ /dev/null @@ -1,493 +0,0 @@ -/**************************************************************************//** - * @file LPC13xx.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * NXP LPC13xx Device Series - * @version V1.01 - * @date 19. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __LPC13xx_H__ -#define __LPC13xx_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC13xx Specific Interrupt Numbers *******************************************************/ - WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ - WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ - WAKEUP2_IRQn = 2, - WAKEUP3_IRQn = 3, - WAKEUP4_IRQn = 4, - WAKEUP5_IRQn = 5, - WAKEUP6_IRQn = 6, - WAKEUP7_IRQn = 7, - WAKEUP8_IRQn = 8, - WAKEUP9_IRQn = 9, - WAKEUP10_IRQn = 10, - WAKEUP11_IRQn = 11, - WAKEUP12_IRQn = 12, - WAKEUP13_IRQn = 13, - WAKEUP14_IRQn = 14, - WAKEUP15_IRQn = 15, - WAKEUP16_IRQn = 16, - WAKEUP17_IRQn = 17, - WAKEUP18_IRQn = 18, - WAKEUP19_IRQn = 19, - WAKEUP20_IRQn = 20, - WAKEUP21_IRQn = 21, - WAKEUP22_IRQn = 22, - WAKEUP23_IRQn = 23, - WAKEUP24_IRQn = 24, - WAKEUP25_IRQn = 25, - WAKEUP26_IRQn = 26, - WAKEUP27_IRQn = 27, - WAKEUP28_IRQn = 28, - WAKEUP29_IRQn = 29, - WAKEUP30_IRQn = 30, - WAKEUP31_IRQn = 31, - WAKEUP32_IRQn = 32, - WAKEUP33_IRQn = 33, - WAKEUP34_IRQn = 34, - WAKEUP35_IRQn = 35, - WAKEUP36_IRQn = 36, - WAKEUP37_IRQn = 37, - WAKEUP38_IRQn = 38, - WAKEUP39_IRQn = 39, - I2C_IRQn = 40, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ - SSP_IRQn = 45, /*!< SSP Interrupt */ - UART_IRQn = 46, /*!< UART Interrupt */ - USB_IRQn = 47, /*!< USB Regular Interrupt */ - USB_FIQn = 48, /*!< USB Fast Interrupt */ - ADC_IRQn = 49, /*!< A/D Converter Interrupt */ - WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ - EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ - EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ - EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ - EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_LPC13xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SYSCON) --------------------------------------*/ -typedef struct -{ - __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ - __IO uint32_t PRESETCTRL; - __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ - __IO uint32_t SYSPLLSTAT; - __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ - __IO uint32_t USBPLLSTAT; - uint32_t RESERVED0[2]; - - __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ - __IO uint32_t WDTOSCCTRL; - __IO uint32_t IRCCTRL; - uint32_t RESERVED1[1]; - __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ - __IO uint32_t SYSPLLCLKUEN; - __IO uint32_t USBPLLCLKSEL; - __IO uint32_t USBPLLCLKUEN; - uint32_t RESERVED3[8]; - - __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ - __IO uint32_t MAINCLKUEN; - __IO uint32_t SYSAHBCLKDIV; - uint32_t RESERVED4[1]; - - __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ - uint32_t RESERVED5[4]; - __IO uint32_t SSPCLKDIV; - __IO uint32_t UARTCLKDIV; - uint32_t RESERVED6[4]; - __IO uint32_t TRACECLKDIV; - - __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ - uint32_t RESERVED7[3]; - - __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ - __IO uint32_t USBCLKUEN; - __IO uint32_t USBCLKDIV; - uint32_t RESERVED8[1]; - __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ - __IO uint32_t WDTCLKUEN; - __IO uint32_t WDTCLKDIV; - uint32_t RESERVED9[1]; - __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ - __IO uint32_t CLKOUTUEN; - __IO uint32_t CLKOUTDIV; - uint32_t RESERVED10[5]; - - __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ - __IO uint32_t PIOPORCAP1; - uint32_t RESERVED11[18]; - - __IO uint32_t BODCTRL; /* Offset 0x150 */ - uint32_t RESERVED12[1]; - __IO uint32_t SYSTCKCAL; - uint32_t RESERVED13[41]; - - __IO uint32_t STARTAPRP0; /* Offset 0x200 */ - __IO uint32_t STARTERP0; - __IO uint32_t STARTRSRP0CLR; - __IO uint32_t STARTSRP0; - __IO uint32_t STARTAPRP1; - __IO uint32_t STARTERP1; - __IO uint32_t STARTRSRP1CLR; - __IO uint32_t STARTSRP1; - uint32_t RESERVED14[4]; - - __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ - __IO uint32_t PDAWAKECFG; - __IO uint32_t PDRUNCFG; - uint32_t RESERVED15[110]; - __I uint32_t DEVICE_ID; -} LPC_SYSCON_TypeDef; - - -/*------------- Pin Connect Block (IOCON) --------------------------------*/ -typedef struct -{ - __IO uint32_t PIO2_6; - uint32_t RESERVED0[1]; - __IO uint32_t PIO2_0; - __IO uint32_t RESET_PIO0_0; - __IO uint32_t PIO0_1; - __IO uint32_t PIO1_8; - uint32_t RESERVED1[1]; - __IO uint32_t PIO0_2; - - __IO uint32_t PIO2_7; - __IO uint32_t PIO2_8; - __IO uint32_t PIO2_1; - __IO uint32_t PIO0_3; - __IO uint32_t PIO0_4; - __IO uint32_t PIO0_5; - __IO uint32_t PIO1_9; - __IO uint32_t PIO3_4; - - __IO uint32_t PIO2_4; - __IO uint32_t PIO2_5; - __IO uint32_t PIO3_5; - __IO uint32_t PIO0_6; - __IO uint32_t PIO0_7; - __IO uint32_t PIO2_9; - __IO uint32_t PIO2_10; - __IO uint32_t PIO2_2; - - __IO uint32_t PIO0_8; - __IO uint32_t PIO0_9; - __IO uint32_t JTAG_TCK_PIO0_10; - __IO uint32_t PIO1_10; - __IO uint32_t PIO2_11; - __IO uint32_t JTAG_TDI_PIO0_11; - __IO uint32_t JTAG_TMS_PIO1_0; - __IO uint32_t JTAG_TDO_PIO1_1; - - __IO uint32_t JTAG_nTRST_PIO1_2; - __IO uint32_t PIO3_0; - __IO uint32_t PIO3_1; - __IO uint32_t PIO2_3; - __IO uint32_t ARM_SWDIO_PIO1_3; - __IO uint32_t PIO1_4; - __IO uint32_t PIO1_11; - __IO uint32_t PIO3_2; - - __IO uint32_t PIO1_5; - __IO uint32_t PIO1_6; - __IO uint32_t PIO1_7; - __IO uint32_t PIO3_3; - __IO uint32_t SCKLOC; /* For HB1 only, new feature */ -} LPC_IOCON_TypeDef; - - -/*------------- Power Management Unit (PMU) --------------------------*/ -typedef struct -{ - __IO uint32_t PCON; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; -} LPC_PMU_TypeDef; - - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[4096]; - struct { - uint32_t RESERVED0[4095]; - __IO uint32_t DATA; - }; - }; - uint32_t RESERVED1[4096]; - __IO uint32_t DIR; - __IO uint32_t IS; - __IO uint32_t IBE; - __IO uint32_t IEV; - __IO uint32_t IE; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t IC; -} LPC_GPIO_TypeDef; - - -/*------------- Timer (TMR) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - uint32_t RESERVED1[3]; - __IO uint32_t EMR; - uint32_t RESERVED2[12]; - __IO uint32_t CTCR; - __IO uint32_t PWMC; -} LPC_TMR_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - union { - __I uint32_t RBR; - __O uint32_t THR; - __IO uint32_t DLL; - }; - union { - __IO uint32_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint32_t FCR; - }; - __IO uint32_t LCR; - __IO uint32_t MCR; - __I uint32_t LSR; - __I uint32_t MSR; - __IO uint32_t SCR; - __IO uint32_t ACR; - __IO uint32_t ICR; - __IO uint32_t FDR; - uint32_t RESERVED0; - __IO uint32_t TER; - uint32_t RESERVED1[6]; - __IO uint32_t RS485CTRL; - __IO uint32_t ADRMATCH; - __IO uint32_t RS485DLY; - __I uint32_t FIFOLVL; -} LPC_UART_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __I uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t CONSET; - __I uint32_t STAT; - __IO uint32_t DAT; - __IO uint32_t ADR0; - __IO uint32_t SCLH; - __IO uint32_t SCLL; - __O uint32_t CONCLR; - __IO uint32_t MMCTRL; - __IO uint32_t ADR1; - __IO uint32_t ADR2; - __IO uint32_t ADR3; - __I uint32_t DATA_BUFFER; - __IO uint32_t MASK0; - __IO uint32_t MASK1; - __IO uint32_t MASK2; - __IO uint32_t MASK3; -} LPC_I2C_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t MOD; - __IO uint32_t TC; - __O uint32_t FEED; - __I uint32_t TV; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t GDR; - uint32_t RESERVED0; - __IO uint32_t INTEN; - __I uint32_t DR0; - __I uint32_t DR1; - __I uint32_t DR2; - __I uint32_t DR3; - __I uint32_t DR4; - __I uint32_t DR5; - __I uint32_t DR6; - __I uint32_t DR7; - __I uint32_t STAT; -} LPC_ADC_TypeDef; - - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t DevIntEn; - __O uint32_t DevIntClr; - __O uint32_t DevIntSet; - - __O uint32_t CmdCode; /* USB Device SIE Command Registers */ - __I uint32_t CmdData; - - __I uint32_t RxData; /* USB Device Transfer Registers */ - __O uint32_t TxData; - __I uint32_t RxPLen; - __O uint32_t TxPLen; - __IO uint32_t Ctrl; - __O uint32_t DevFIQSel; -} LPC_USB_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) - -/* AHB peripherals */ -#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) -#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) -#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) -#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) -#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) -#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) - -#endif // __LPC13xx_H__ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/hal_lld.c deleted file mode 100644 index de8cba9..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/hal_lld.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC13xx/hal_lld.c - * @brief LPC13xx HAL subsystem low level driver source. - * - * @addtogroup LPC13xx_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/** - * @brief Register missing in NXP header file. - */ -#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -const PALConfig pal_default_config = { - {VAL_GPIO0DATA, VAL_GPIO0DIR}, - {VAL_GPIO1DATA, VAL_GPIO1DIR}, - {VAL_GPIO2DATA, VAL_GPIO2DIR}, - {VAL_GPIO3DATA, VAL_GPIO3DIR}, -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - - /* SysTick initialization using the system clock.*/ - NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); - SysTick->LOAD = LPC13xx_SYSCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief LPC13xx clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - */ -void LPC13xx_clock_init(void) { - unsigned i; - - /* Flash wait states setting, the code takes care to not touch TBD bits.*/ - FLASHCFG = (FLASHCFG & ~3) | LPC13xx_FLASHCFG_FLASHTIM; - - /* System oscillator initialization if required.*/ -#if LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT -#if LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC - LPC_SYSCON->SYSOSCCTRL = LPC13xx_SYSOSCCTRL; - LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ - for (i = 0; i < 200; i++) - __NOP(); /* Stabilization delay. */ -#endif /* LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ - - /* PLL initialization if required.*/ - LPC_SYSCON->SYSPLLCLKSEL = LPC13xx_PLLCLK_SOURCE; - LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ - LPC_SYSCON->SYSPLLCLKUEN = 0; - LPC_SYSCON->SYSPLLCLKUEN = 1; - LPC_SYSCON->SYSPLLCTRL = LPC13xx_SYSPLLCTRL_MSEL | LPC13xx_SYSPLLCTRL_PSEL; - LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ - while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ - ; -#endif /* LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ - - /* Main clock source selection.*/ - LPC_SYSCON->MAINCLKSEL = LPC13xx_MAINCLK_SOURCE; - LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ - LPC_SYSCON->MAINCLKUEN = 0; - LPC_SYSCON->MAINCLKUEN = 1; - while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ - ; - - /* ABH divider initialization, peripheral clocks are initially disabled, - the various device drivers will handle their own setup except GPIO and - IOCON that are left enabled.*/ - LPC_SYSCON->SYSAHBCLKDIV = LPC13xx_SYSABHCLK_DIV; - LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; - - /* Peripheral clock dividers initialization.*/ - LPC_SYSCON->UARTCLKDIV = LPC13xx_UART_PCLK_DIV; - - /* Memory remapping, vectors always in ROM.*/ - LPC_SYSCON->SYSMEMREMAP = 2; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/hal_lld.h deleted file mode 100644 index 8af3ce3..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/hal_lld.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC13xx/hal_lld.h - * @brief HAL subsystem low level driver header template. - * - * @addtogroup LPC13xx_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "LPC13xx.h" -#include "nvic.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "LPC13xx" - -#define IRCOSCCLK 12000000 /**< High speed internal clock. */ -#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ - -#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator - clock source. */ -#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock - source. */ - -#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ -#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ -#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ -#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief System PLL clock source. - */ -#if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) -#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC -#endif - -/** - * @brief System PLL multiplier. - * @note The value must be in the 1..32 range and the final frequency - * must not exceed the CCO ratings. - */ -#if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__) -#define LPC13xx_SYSPLL_MUL 6 -#endif - -/** - * @brief System PLL divider. - * @note The value must be chosen between (2, 4, 8, 16). - */ -#if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__) -#define LPC13xx_SYSPLL_DIV 4 -#endif - -/** - * @brief System main clock source. - */ -#if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) -#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT -#endif - -/** - * @brief AHB clock divider. - * @note The value must be chosen between (1...255). - */ -#if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__) -#define LPC13xx_SYSABHCLK_DIV 1 -#endif - -/** - * @brief UART clock divider. - * @note The value must be chosen between (1...255). - */ -#if !defined(LPC13xx_UART_PCLK_DIV) || defined(__DOXYGEN__) -#define LPC13xx_UART_PCLK_DIV 1 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief Calculated SYSOSCCTRL setting. - */ -#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) -#define LPC13xx_SYSOSCCTRL 0 -#else -#define LPC13xx_SYSOSCCTRL 1 -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) -#define LPC13xx_SYSPLLCLKIN SYSOSCCLK -#elif LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS -#define LPC13xx_SYSPLLCLKIN IRCOSCCLK -#else -#error "invalid LPC13xx_PLLCLK_SOURCE clock source specified" -#endif - -/** - * @brief MSEL mask in SYSPLLCTRL register. - */ -#if (LPC13xx_SYSPLL_MUL >= 1) && (LPC13xx_SYSPLL_MUL <= 32) || \ - defined(__DOXYGEN__) -#define LPC13xx_SYSPLLCTRL_MSEL (LPC13xx_SYSPLL_MUL - 1) -#else -#error "LPC13xx_SYSPLL_MUL out of range (1...32)" -#endif - -/** - * @brief PSEL mask in SYSPLLCTRL register. - */ -#if (LPC13xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) -#define LPC13xx_SYSPLLCTRL_PSEL (0 << 5) -#elif LPC13xx_SYSPLL_DIV == 4 -#define LPC13xx_SYSPLLCTRL_PSEL (1 << 5) -#elif LPC13xx_SYSPLL_DIV == 8 -#define LPC13xx_SYSPLLCTRL_PSEL (2 << 5) -#elif LPC13xx_SYSPLL_DIV == 16 -#define LPC13xx_SYSPLLCTRL_PSEL (3 << 5) -#else -#error "invalid LPC13xx_SYSPLL_DIV value (2,4,8,16)" -#endif - -/** - * @brief CCP frequency. - */ -#define LPC13xx_SYSPLLCCO (LPC13xx_SYSPLLCLKIN * LPC13xx_SYSPLL_MUL * \ - LPC13xx_SYSPLL_DIV) - -#if (LPC13xx_SYSPLLCCO < 156000000) || (LPC13xx_SYSPLLCCO > 320000000) -#error "CCO frequency out of the acceptable range (156...320)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define LPC13xx_SYSPLLCLKOUT (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV) - -#if (LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__) -#define LPC13xx_MAINCLK IRCOSCCLK -#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN -#define LPC13xx_MAINCLK LPC13xx_SYSPLLCLKIN -#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC -#define LPC13xx_MAINCLK WDGOSCCLK -#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT -#define LPC13xx_MAINCLK LPC13xx_SYSPLLCLKOUT -#else -#error "invalid LPC13xx_MAINCLK_SOURCE clock source specified" -#endif - -/** - * @brief AHB clock. - */ -#define LPC13xx_SYSCLK (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV) -#if LPC13xx_SYSCLK > 72000000 -#error "AHB clock frequency out of the acceptable range (72MHz max)" -#endif - -/** - * @brief Flash wait states. - */ -#if (LPC13xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) -#define LPC13xx_FLASHCFG_FLASHTIM 0 -#elif LPC13xx_SYSCLK <= 40000000 -#define LPC13xx_FLASHCFG_FLASHTIM 1 -#else -#define LPC13xx_FLASHCFG_FLASHTIM 2 -#endif - -/** - * @brief UART clock. - */ -#define LPC13xx_UART_PCLK (LPC13xx_MAINCLK / LPC13xx_UART_PCLK_DIV) - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void LPC13xx_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/pal_lld.c deleted file mode 100644 index 8644e35..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/pal_lld.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC13xx/pal_lld.c - * @brief LPC13xx GPIO low level driver code. - * - * @addtogroup LPC13xx_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ -/** - * @brief LPC13xx I/O ports configuration. - * @details GPIO unit registers initialization. - * - * @param[in] config the LPC13xx ports configuration - */ -void _pal_lld_init(const PALConfig *config) { - - LPC_GPIO0->DIR = config->P0.dir; - LPC_GPIO1->DIR = config->P1.dir; - LPC_GPIO2->DIR = config->P2.dir; - LPC_GPIO3->DIR = config->P3.dir; - LPC_GPIO0->DATA = config->P0.data; - LPC_GPIO1->DATA = config->P1.data; - LPC_GPIO2->DATA = config->P2.data; - LPC_GPIO3->DATA = config->P3.data; -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - - switch (mode & PAL_MODE_MASK) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->DIR &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - palSetPort(port, PAL_WHOLE_PORT); - case PAL_MODE_OUTPUT_PUSHPULL: - port->DIR |= mask; - break; - } -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/pal_lld.h deleted file mode 100644 index 6034377..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/pal_lld.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC13xx/pal_lld.h - * @brief LPC13xx GPIO low level driver header. - * - * @addtogroup LPC13xx_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for FIO_PIN register.*/ - uint32_t data; - /** Initial value for FIO_DIR register.*/ - uint32_t dir; -} LPC13xx_gpio_setup_t; - -/** - * @brief GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - * @note The @p IOCON block is not configured, initially all pins have - * enabled pullups and are programmed as GPIO. It is responsibility - * of the various drivers to reprogram the pins in the proper mode. - * Pins that are not handled by any driver may be programmed in - * @p board.c. - */ -typedef struct { - /** @brief GPIO 0 setup data.*/ - LPC13xx_gpio_setup_t P0; - /** @brief GPIO 1 setup data.*/ - LPC13xx_gpio_setup_t P1; - /** @brief GPIO 2 setup data.*/ - LPC13xx_gpio_setup_t P2; - /** @brief GPIO 3 setup data.*/ - LPC13xx_gpio_setup_t P3; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Port Identifier. - */ -typedef LPC_GPIO_TypeDef *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief GPIO0 port identifier. - */ -#define IOPORT1 LPC_GPIO0 -#define GPIO0 LPC_GPIO0 - -/** - * @brief GPIO1 port identifier. - */ -#define IOPORT2 LPC_GPIO1 -#define GPIO1 LPC_GPIO1 - -/** - * @brief GPIO2 port identifier. - */ -#define IOPORT3 LPC_GPIO2 -#define GPIO2 LPC_GPIO2 - -/** - * @brief GPIO3 port identifier. - */ -#define IOPORT4 LPC_GPIO3 -#define GPIO3 LPC_GPIO3 - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The port bits. - */ -#define pal_lld_readport(port) ((port)->DATA) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The latched logical states. - */ -#define pal_lld_readlatch(port) ((port)->DATA) - -/** - * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - */ -#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF) - -/** - * @brief Clears a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - */ -#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) - -/** - * @brief Reads a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @return The group logical states. - */ -#define pal_lld_readgroup(port, mask, offset) \ - ((port)->MASKED_ACCESS[(mask) << (offset)]) - -/** - * @brief Writes a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group width - * are masked. - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] mode group mode - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[out] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - */ -#define pal_lld_writepad(port, pad, bit) \ - ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad)) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#define pal_lld_setpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#define pal_lld_clearpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 0) - -#if !defined(__DOXYGEN__) -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/platform.dox deleted file mode 100644 index 1cebb33..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/platform.dox +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup LPC13xx LPC13xx Support - * @brief LPC13xx specific support. - * @details The LPC13xx support includes: - * - I/O ports driver. - * - Buffered, interrupt driven, serial driver. - * - A demo supporting the kernel test suite. - * . - * @ingroup ARMCMx - */ - -/** - * @defgroup LPC13xx_HAL LPC13xx HAL Support - * @brief HAL support. - * - * @ingroup LPC13xx - */ - -/** - * @defgroup LPC13xx_PAL LPC13xx I/O Ports Support - * @brief I/O Ports peripherals support. - * @details This module supports the LPC13xx GPIO controller. The controller - * supports the following features (see @ref PAL): - * - 12 bits wide ports. - * - Atomic set/reset functions. - * - Atomic set+reset function (atomic bus operations). - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - *

Supported Setup Modes

- * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * . - * Any attempt to setup an invalid mode is ignored. - * - *

Suboptimal Behavior

- * Some GPIO features are less than optimal: - * - Pad/port toggling operations are not atomic. - * - Pull-up and Pull-down resistors cannot be programmed through the PAL - * driver and must be programmed separately. - * - Reading of the output latch for pads programmed as input is not possible, - * the input pin value is returned instead. - * . - * @ingroup LPC13xx - */ - -/** - * @defgroup LPC13xx_SERIAL LPC13xx UART Support - * @brief UART peripherals support. - * @details The serial driver supports the LPC13xx UART taking advantage of - * its deep hardware buffers. - * - * @ingroup LPC13xx - */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/platform.mk deleted file mode 100644 index 9966feb..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/platform.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of all the LPC13xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC13xx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC13xx/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC13xx/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC13xx diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/serial_lld.c deleted file mode 100644 index 19c7c63..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/serial_lld.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC13xx/serial_lld.c - * @brief LPC13xx low level serial driver code. - * - * @addtogroup LPC13xx_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if USE_LPC13xx_UART0 || defined(__DOXYGEN__) -/** @brief UART0 serial driver identifier.*/ -SerialDriver SD1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { - SERIAL_DEFAULT_BITRATE, - LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, - FCR_TRIGGER0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief UART initialization. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] config the architecture-dependent serial driver configuration - */ -static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - LPC_UART_TypeDef *u = sdp->uart; - - uint32_t div = LPC13xx_UART_PCLK / (config->sc_speed << 4); - u->LCR = config->sc_lcr | LCR_DLAB; - u->DLL = div; - u->DLM = div >> 8; - u->LCR = config->sc_lcr; - u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; - u->ACR = 0; - u->FDR = 0x10; - u->TER = TER_ENABLE; - u->IER = IER_RBR | IER_STATUS; -} - -/** - * @brief UART de-initialization. - * - * @param[in] u pointer to an UART I/O block - */ -static void uart_deinit(LPC_UART_TypeDef *u) { - - u->LCR = LCR_DLAB; - u->DLL = 1; - u->DLM = 0; - u->LCR = 0; - u->FDR = 0x10; - u->IER = 0; - u->FCR = FCR_RXRESET | FCR_TXRESET; - u->ACR = 0; - u->TER = TER_ENABLE; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] err UART LSR register value - */ -static void set_error(SerialDriver *sdp, IOREG32 err) { - sdflags_t sts = 0; - - if (err & LSR_OVERRUN) - sts |= SD_OVERRUN_ERROR; - if (err & LSR_PARITY) - sts |= SD_PARITY_ERROR; - if (err & LSR_FRAMING) - sts |= SD_FRAMING_ERROR; - if (err & LSR_BREAK) - sts |= SD_BREAK_DETECTED; - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -/** - * @brief Common IRQ handler. - * @note Tries hard to clear all the pending interrupt sources, we don't - * want to go through the whole ISR and have another interrupt soon - * after. - * - * @param[in] u pointer to an UART I/O block - * @param[in] sdp communication channel associated to the UART - */ -static void serve_interrupt(SerialDriver *sdp) { - LPC_UART_TypeDef *u = sdp->uart; - - while (TRUE) { - switch (u->IIR & IIR_SRC_MASK) { - case IIR_SRC_NONE: - return; - case IIR_SRC_ERROR: - set_error(sdp, u->LSR); - break; - case IIR_SRC_TIMEOUT: - case IIR_SRC_RX: - chSysLockFromIsr(); - if (chIQIsEmpty(&sdp->iqueue)) - chEvtBroadcastI(&sdp->ievent); - chSysUnlockFromIsr(); - while (u->LSR & LSR_RBR_FULL) { - chSysLockFromIsr(); - if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) - sdAddFlagsI(sdp, SD_OVERRUN_ERROR); - chSysUnlockFromIsr(); - } - break; - case IIR_SRC_TX: - { - int i = LPC13xx_UART_FIFO_PRELOAD; - do { - msg_t b; - - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - chSysUnlockFromIsr(); - if (b < Q_OK) { - u->IER &= ~IER_THRE; - chSysLockFromIsr(); - chEvtBroadcastI(&sdp->oevent); - chSysUnlockFromIsr(); - break; - } - u->THR = b; - } while (--i); - } - break; - default: - (void) u->THR; - (void) u->RBR; - } - } -} - -/** - * @brief Attempts a TX FIFO preload. - */ -static void preload(SerialDriver *sdp) { - LPC_UART_TypeDef *u = sdp->uart; - - if (u->LSR & LSR_THRE) { - int i = LPC13xx_UART_FIFO_PRELOAD; - do { - msg_t b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chEvtBroadcastI(&sdp->oevent); - return; - } - u->THR = b; - } while (--i); - } - u->IER |= IER_THRE; -} - -/** - * @brief Driver SD1 output notification. - */ -#if USE_LPC13xx_UART0 || defined(__DOXYGEN__) -static void notify1(void) { - - preload(&SD1); -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief UART0 IRQ handler. - */ -#if USE_LPC13xx_UART0 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(VectorF8) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_LPC13xx_UART0 - sdObjectInit(&SD1, NULL, notify1); - SD1.uart = LPC_UART; - LPC_IOCON->PIO1_6 = 0xC1; /* RDX without resistors. */ - LPC_IOCON->PIO1_7 = 0xC1; /* TDX without resistors. */ -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if USE_LPC13xx_UART0 - if (&SD1 == sdp) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); - NVICEnableVector(UART_IRQn, - CORTEX_PRIORITY_MASK(LPC13xx_UART0_PRIORITY)); - } -#endif - } - uart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the UART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - uart_deinit(sdp->uart); -#if USE_LPC13xx_UART0 - if (&SD1 == sdp) { - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); - NVICDisableVector(UART_IRQn); - return; - } -#endif - } -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/serial_lld.h deleted file mode 100644 index 34d00c3..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/serial_lld.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC13xx/serial_lld.h - * @brief LPC13xx low level serial driver header. - * - * @addtogroup LPC13xx_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define IIR_SRC_MASK 0x0F -#define IIR_SRC_NONE 0x01 -#define IIR_SRC_MODEM 0x00 -#define IIR_SRC_TX 0x02 -#define IIR_SRC_RX 0x04 -#define IIR_SRC_ERROR 0x06 -#define IIR_SRC_TIMEOUT 0x0C - -#define IER_RBR 1 -#define IER_THRE 2 -#define IER_STATUS 4 - -#define LCR_WL5 0 -#define LCR_WL6 1 -#define LCR_WL7 2 -#define LCR_WL8 3 -#define LCR_STOP1 0 -#define LCR_STOP2 4 -#define LCR_NOPARITY 0 -#define LCR_PARITYODD 0x08 -#define LCR_PARITYEVEN 0x18 -#define LCR_PARITYONE 0x28 -#define LCR_PARITYZERO 0x38 -#define LCR_BREAK_ON 0x40 -#define LCR_DLAB 0x80 - -#define FCR_ENABLE 1 -#define FCR_RXRESET 2 -#define FCR_TXRESET 4 -#define FCR_TRIGGER0 0 -#define FCR_TRIGGER1 0x40 -#define FCR_TRIGGER2 0x80 -#define FCR_TRIGGER3 0xC0 - -#define LSR_RBR_FULL 1 -#define LSR_OVERRUN 2 -#define LSR_PARITY 4 -#define LSR_FRAMING 8 -#define LSR_BREAK 0x10 -#define LSR_THRE 0x20 -#define LSR_TEMT 0x40 -#define LSR_RXFE 0x80 - -#define TER_ENABLE 0x80 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UART0 driver enable switch. - * @details If set to @p TRUE the support for UART0 is included. - * @note The default is @p TRUE . - */ -#if !defined(USE_LPC13xx_UART0) || defined(__DOXYGEN__) -#define USE_LPC13xx_UART0 TRUE -#endif - -/** - * @brief FIFO preload parameter. - * @details Configuration parameter, this values defines how many bytes are - * preloaded in the HW transmit FIFO for each interrupt, the maximum - * value is 16 the minimum is 1. - * @note An high value reduces the number of interrupts generated but can - * also increase the worst case interrupt response time because the - * preload loops. - */ -#if !defined(LPC13xx_UART_FIFO_PRELOAD) || defined(__DOXYGEN__) -#define LPC13xx_UART_FIFO_PRELOAD 16 -#endif - -/** - * @brief UART0 interrupt priority level setting. - */ -#if !defined(LPC13xx_UART0_PRIORITY) || defined(__DOXYGEN__) -#define LPC13xx_UART0_PRIORITY 3 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (LPC13xx_UART_FIFO_PRELOAD < 1) || (LPC13xx_UART_FIFO_PRELOAD > 16) -#error "invalid LPC13xx_UART_FIFO_PRELOAD setting" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint32_t sdflags_t; - -/** - * @brief LPC13xx Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /** - * @brief Initialization value for the LCR register. - */ - uint32_t sc_lcr; - /** - * @brief Initialization value for the FCR register. - */ - uint32_t sc_fcr; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - LPC_UART_TypeDef *uart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_LPC13xx_UART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/system_LPC13xx.h b/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/system_LPC13xx.h deleted file mode 100644 index 1cb04fa..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC13xx/system_LPC13xx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_LPC13xx.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC13xx Device Series - * @version V1.01 - * @date 19. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC13xx_H -#define __SYSTEM_LPC13xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC13x_H */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/hal_lld.c deleted file mode 100644 index 6d995f3..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/hal_lld.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/hal_lld.c - * @brief LPC214x HAL subsystem low level driver source. - * @addtogroup LPC214x_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -const PALConfig pal_default_config = -{ - VAL_PINSEL0, - VAL_PINSEL1, - VAL_PINSEL2, - {VAL_FIO0PIN, VAL_FIO0DIR}, - {VAL_FIO1PIN, VAL_FIO1DIR} -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/* - * Non-vectored IRQs handler, the default action can be overridden by - * redefining the @p LPC214x_NON_VECTORED_IRQ_HOOK() hook macro. - */ -static CH_IRQ_HANDLER(irq_handler) { - - CH_IRQ_PROLOGUE(); - - LPC214x_NON_VECTORED_IRQ_HOOK(); - - VICVectAddr = 0; - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - - vic_init(); - VICDefVectAddr = (IOREG32)irq_handler; - -} - -/** - * @brief LPC214x clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - */ -void lpc214x_clock_init(void) { - - /* - * All peripherals clock disabled by default in order to save power. - */ - PCONP = PCRTC | PCTIM0; - - /* - * MAM setup. - */ - MAMTIM = 0x3; /* 3 cycles for flash accesses. */ - MAMCR = 0x2; /* MAM fully enabled. */ - - /* - * PLL setup for Fosc=12MHz and CCLK=48MHz. - * P=2 M=3. - */ - PLL *pll = PLL0Base; - pll->PLL_CFG = 0x23; /* P and M values. */ - pll->PLL_CON = 0x1; /* Enables the PLL 0. */ - pll->PLL_FEED = 0xAA; - pll->PLL_FEED = 0x55; - while (!(pll->PLL_STAT & 0x400)) - ; /* Wait for PLL lock. */ - - pll->PLL_CON = 0x3; /* Connects the PLL. */ - pll->PLL_FEED = 0xAA; - pll->PLL_FEED = 0x55; - - /* - * VPB setup. - * PCLK = CCLK / 4. - */ - VPBDIV = VPD_D4; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/hal_lld.h deleted file mode 100644 index 10cd40f..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/hal_lld.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/hal_lld.h - * @brief LPC214x HAL subsystem low level driver header. - * @addtogroup LPC214x_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "lpc214x.h" -#include "vic.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "LPC214x" - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Default action for the non vectored IRQ handler, nothing. - */ -#if !defined(LPC214x_NON_VECTORED_IRQ_HOOK) || defined(__DOXYGEN__) -#define LPC214x_NON_VECTORED_IRQ_HOOK() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void lpc214x_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/lpc214x.h b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/lpc214x.h deleted file mode 100644 index 82c2b0c..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/lpc214x.h +++ /dev/null @@ -1,532 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file lpc214x.h - * @brief LPC214x register definitions. - */ - -#ifndef _LPC214X_H_ -#define _LPC214X_H_ - -typedef volatile uint8_t IOREG8; -typedef volatile uint16_t IOREG16; -typedef volatile uint32_t IOREG32; - -/* - * System. - */ -#define MEMMAP (*((IOREG32 *)0xE01FC040)) -#define PCON (*((IOREG32 *)0xE01FC0C0)) -#define PCONP (*((IOREG32 *)0xE01FC0C4)) -#define VPBDIV (*((IOREG32 *)0xE01FC100)) -#define EXTINT (*((IOREG32 *)0xE01FC140)) -#define INTWAKE (*((IOREG32 *)0xE01FC144)) -#define EXTMODE (*((IOREG32 *)0xE01FC148)) -#define EXTPOLAR (*((IOREG32 *)0xE01FC14C)) -#define RSID (*((IOREG32 *)0xE01FC180)) -#define CSPR (*((IOREG32 *)0xE01FC184)) -#define SCS (*((IOREG32 *)0xE01FC1A0)) - -#define VPD_D4 0 -#define VPD_D1 1 -#define VPD_D2 2 -#define VPD_RESERVED 3 - -#define PCTIM0 (1 << 1) -#define PCTIM1 (1 << 2) -#define PCUART0 (1 << 3) -#define PCUART1 (1 << 4) -#define PCPWM0 (1 << 5) -#define PCI2C0 (1 << 7) -#define PCSPI0 (1 << 8) -#define PCRTC (1 << 9) -#define PCSPI1 (1 << 10) -#define PCAD0 (1 << 12) -#define PCI2C1 (1 << 19) -#define PCAD1 (1 << 20) -#define PCUSB (1 << 31) -#define PCALL (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \ - PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \ - PCAD0 | PCI2C1 | PCAD1 | PCUSB) - -#define EINT0 1 -#define EINT1 2 -#define EINT2 4 -#define EINT3 8 - -#define EXTWAKE0 1 -#define EXTWAKE1 2 -#define EXTWAKE2 4 -#define EXTWAKE3 8 -#define USBWAKE 0x20 -#define BODWAKE 0x4000 -#define RTCWAKE 0x8000 - -#define EXTMODE0 1 -#define EXTMODE1 2 -#define EXTMODE2 4 -#define EXTMODE3 8 - -#define EXTPOLAR0 1 -#define EXTPOLAR1 2 -#define EXTPOLAR2 4 -#define EXTPOLAR3 8 - -typedef struct { - IOREG32 PLL_CON; - IOREG32 PLL_CFG; - IOREG32 PLL_STAT; - IOREG32 PLL_FEED; -} PLL; - -#define PLL0Base ((PLL *)0xE01FC080) -#define PLL1Base ((PLL *)0xE01FC0A0) -#define PLL0CON (PLL0Base->PLL_CON) -#define PLL0CFG (PLL0Base->PLL_CFG) -#define PLL0STAT (PLL0Base->PLL_STAT) -#define PLL0FEED (PLL0Base->PLL_FEED) -#define PLL1CON (PLL1Base->PLL_CON) -#define PLL1CFG (PLL1Base->PLL_CFG) -#define PLL1STAT (PLL1Base->PLL_STAT) -#define PLL1FEED (PLL1Base->PLL_FEED) - -/* - * Pins. - */ -typedef struct { - IOREG32 PS_SEL0; - IOREG32 PS_SEL1; - IOREG32 _dummy[3]; - IOREG32 PS_SEL2; -} PS; - -#define PSBase ((PS *)0xE002C000) -#define PINSEL0 (PSBase->PS_SEL0) -#define PINSEL1 (PSBase->PS_SEL1) -#define PINSEL2 (PSBase->PS_SEL2) - -/* - * VIC - */ -#define SOURCE_WDT 0 -#define SOURCE_ARMCore0 2 -#define SOURCE_ARMCore1 3 -#define SOURCE_Timer0 4 -#define SOURCE_Timer1 5 -#define SOURCE_UART0 6 -#define SOURCE_UART1 7 -#define SOURCE_PWM0 8 -#define SOURCE_I2C0 9 -#define SOURCE_SPI0 10 -#define SOURCE_SPI1 11 -#define SOURCE_PLL 12 -#define SOURCE_RTC 13 -#define SOURCE_EINT0 14 -#define SOURCE_EINT1 15 -#define SOURCE_EINT2 16 -#define SOURCE_EINT3 17 -#define SOURCE_ADC0 18 -#define SOURCE_I2C1 19 -#define SOURCE_BOD 20 -#define SOURCE_ADC1 21 -#define SOURCE_USB 22 - -#define INTMASK(n) (1 << (n)) -#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \ - INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \ - INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \ - INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \ - INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \ - INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \ - INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \ - INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \ - INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \ - INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \ - INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB)) - -typedef struct { - IOREG32 VIC_IRQStatus; - IOREG32 VIC_FIQStatus; - IOREG32 VIC_RawIntr; - IOREG32 VIC_IntSelect; - IOREG32 VIC_IntEnable; - IOREG32 VIC_IntEnClear; - IOREG32 VIC_SoftInt; - IOREG32 VIC_SoftIntClear; - IOREG32 VIC_Protection; - IOREG32 unused1[3]; - IOREG32 VIC_VectAddr; - IOREG32 VIC_DefVectAddr; - IOREG32 unused2[50]; - IOREG32 VIC_VectAddrs[16]; - IOREG32 unused3[48]; - IOREG32 VIC_VectCntls[16]; -} VIC; - -#define VICBase ((VIC *)0xFFFFF000) -#define VICVectorsBase ((IOREG32 *)0xFFFFF100) -#define VICControlsBase ((IOREG32 *)0xFFFFF200) - -#define VICIRQStatus (VICBase->VIC_IRQStatus) -#define VICFIQStatus (VICBase->VIC_FIQStatus) -#define VICRawIntr (VICBase->VIC_RawIntr) -#define VICIntSelect (VICBase->VIC_IntSelect) -#define VICIntEnable (VICBase->VIC_IntEnable) -#define VICIntEnClear (VICBase->VIC_IntEnClear) -#define VICSoftInt (VICBase->VIC_SoftInt) -#define VICSoftIntClear (VICBase->VIC_SoftIntClear) -#define VICProtection (VICBase->VIC_Protection) -#define VICVectAddr (VICBase->VIC_VectAddr) -#define VICDefVectAddr (VICBase->VIC_DefVectAddr) - -#define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n]) -#define VICVectCntls(n) (VICBase->VIC_VectCntls[n]) - -/* - * MAM. - */ -typedef struct { - IOREG32 MAM_Control; - IOREG32 MAM_Timing; -} MAM; - -#define MAMBase ((MAM *)0xE01FC000) -#define MAMCR (MAMBase->MAM_Control) -#define MAMTIM (MAMBase->MAM_Timing) - -/* - * GPIO - FIO. - */ -typedef struct { - IOREG32 IO_PIN; - IOREG32 IO_SET; - IOREG32 IO_DIR; - IOREG32 IO_CLR; -} GPIO; - -#define GPIO0Base ((GPIO *)0xE0028000) -#define IO0PIN (GPIO0Base->IO_PIN) -#define IO0SET (GPIO0Base->IO_SET) -#define IO0DIR (GPIO0Base->IO_DIR) -#define IO0CLR (GPIO0Base->IO_CLR) - -#define GPIO1Base ((GPIO *)0xE0028010) -#define IO1PIN (GPIO1Base->IO_PIN) -#define IO1SET (GPIO1Base->IO_SET) -#define IO1DIR (GPIO1Base->IO_DIR) -#define IO1CLR (GPIO1Base->IO_CLR) - -typedef struct { - IOREG32 FIO_DIR; - IOREG32 unused1; - IOREG32 unused2; - IOREG32 unused3; - IOREG32 FIO_MASK; - IOREG32 FIO_PIN; - IOREG32 FIO_SET; - IOREG32 FIO_CLR; -} FIO; - -#define FIO0Base ((FIO *)0x3FFFC000) -#define FIO0DIR (FIO0Base->FIO_DIR) -#define FIO0MASK (FIO0Base->FIO_MASK) -#define FIO0PIN (FIO0Base->FIO_PIN) -#define FIO0SET (FIO0Base->FIO_SET) -#define FIO0CLR (FIO0Base->FIO_CLR) - -#define FIO1Base ((FIO *)0x3FFFC020) -#define FIO1DIR (FIO1Base->FIO_DIR) -#define FIO1MASK (FIO1Base->FIO_MASK) -#define FIO1PIN (FIO1Base->FIO_PIN) -#define FIO1SET (FIO1Base->FIO_SET) -#define FIO1CLR (FIO1Base->FIO_CLR) - -/* - * UART. - */ -typedef struct { - union { - IOREG32 UART_RBR; - IOREG32 UART_THR; - IOREG32 UART_DLL; - }; - union { - IOREG32 UART_IER; - IOREG32 UART_DLM; - }; - union { - IOREG32 UART_IIR; - IOREG32 UART_FCR; - }; - IOREG32 UART_LCR; - IOREG32 UART_MCR; // UART1 only - IOREG32 UART_LSR; - IOREG32 unused18; - IOREG32 UART_SCR; - IOREG32 UART_ACR; - IOREG32 unused24; - IOREG32 UART_FDR; - IOREG32 unused2C; - IOREG32 UART_TER; -} UART; - -#define U0Base ((UART *)0xE000C000) -#define U0RBR (U0Base->UART_RBR) -#define U0THR (U0Base->UART_THR) -#define U0DLL (U0Base->UART_DLL) -#define U0IER (U0Base->UART_IER) -#define U0DLM (U0Base->UART_DLM) -#define U0IIR (U0Base->UART_IIR) -#define U0FCR (U0Base->UART_FCR) -#define U0LCR (U0Base->UART_LCR) -#define U0LSR (U0Base->UART_LSR) -#define U0SCR (U0Base->UART_SCR) -#define U0ACR (U0Base->UART_ACR) -#define U0FDR (U0Base->UART_FDR) -#define U0TER (U0Base->UART_TER) - -#define U1Base ((UART *)0xE0010000) -#define U1RBR (U1Base->UART_RBR) -#define U1THR (U1Base->UART_THR) -#define U1DLL (U1Base->UART_DLL) -#define U1IER (U1Base->UART_IER) -#define U1DLM (U1Base->UART_DLM) -#define U1IIR (U1Base->UART_IIR) -#define U1FCR (U1Base->UART_FCR) -#define U1MCR (U1Base->UART_MCR) -#define U1LCR (U1Base->UART_LCR) -#define U1LSR (U1Base->UART_LSR) -#define U1SCR (U1Base->UART_SCR) -#define U1ACR (U1Base->UART_ACR) -#define U1FDR (U1Base->UART_FDR) -#define U1TER (U1Base->UART_TER) - -#define IIR_SRC_MASK 0x0F -#define IIR_SRC_NONE 0x01 -#define IIR_SRC_TX 0x02 -#define IIR_SRC_RX 0x04 -#define IIR_SRC_ERROR 0x06 -#define IIR_SRC_TIMEOUT 0x0C - -#define IER_RBR 1 -#define IER_THRE 2 -#define IER_STATUS 4 - -#define IIR_INT_PENDING 1 - -#define LCR_WL5 0 -#define LCR_WL6 1 -#define LCR_WL7 2 -#define LCR_WL8 3 -#define LCR_STOP1 0 -#define LCR_STOP2 4 -#define LCR_NOPARITY 0 -#define LCR_PARITYODD 0x08 -#define LCR_PARITYEVEN 0x18 -#define LCR_PARITYONE 0x28 -#define LCR_PARITYZERO 0x38 -#define LCR_BREAK_ON 0x40 -#define LCR_DLAB 0x80 - -#define FCR_ENABLE 1 -#define FCR_RXRESET 2 -#define FCR_TXRESET 4 -#define FCR_TRIGGER0 0 -#define FCR_TRIGGER1 0x40 -#define FCR_TRIGGER2 0x80 -#define FCR_TRIGGER3 0xC0 - -#define LSR_RBR_FULL 1 -#define LSR_OVERRUN 2 -#define LSR_PARITY 4 -#define LSR_FRAMING 8 -#define LSR_BREAK 0x10 -#define LSR_THRE 0x20 -#define LSR_TEMT 0x40 -#define LSR_RXFE 0x80 - -#define TER_ENABLE 0x80 - -/* - * SSP. - */ -typedef struct { - IOREG32 SSP_CR0; - IOREG32 SSP_CR1; - IOREG32 SSP_DR; - IOREG32 SSP_SR; - IOREG32 SSP_CPSR; - IOREG32 SSP_IMSC; - IOREG32 SSP_RIS; - IOREG32 SSP_MIS; - IOREG32 SSP_ICR; -} SSP; - -#define SSPBase ((SSP *)0xE0068000) -#define SSPCR0 (SSPBase->SSP_CR0) -#define SSPCR1 (SSPBase->SSP_CR1) -#define SSPDR (SSPBase->SSP_DR) -#define SSPSR (SSPBase->SSP_SR) -#define SSPCPSR (SSPBase->SSP_CPSR) -#define SSPIMSC (SSPBase->SSP_IMSC) -#define SSPRIS (SSPBase->SSP_RIS) -#define SSPMIS (SSPBase->SSP_MIS) -#define SSPICR (SSPBase->SSP_ICR) - -#define CR0_DSS4BIT 3 -#define CR0_DSS5BIT 4 -#define CR0_DSS6BIT 5 -#define CR0_DSS7BIT 6 -#define CR0_DSS8BIT 7 -#define CR0_DSS9BIT 8 -#define CR0_DSS10BIT 9 -#define CR0_DSS11BIT 0xA -#define CR0_DSS12BIT 0xB -#define CR0_DSS13BIT 0xC -#define CR0_DSS14BIT 0xD -#define CR0_DSS15BIT 0xE -#define CR0_DSS16BIT 0xF -#define CR0_FRFSPI 0 -#define CR0_FRFSSI 0x10 -#define CR0_FRFMW 0x20 -#define CR0_CPOL 0x40 -#define CR0_CPHA 0x80 -#define CR0_CLOCKRATE(n) ((n) << 8) - -#define CR1_LBM 1 -#define CR1_SSE 2 -#define CR1_MS 4 -#define CR1_SOD 8 - -#define SR_TFE 1 -#define SR_TNF 2 -#define SR_RNE 4 -#define SR_RFF 8 -#define SR_BSY 0x10 - -#define IMSC_ROR 1 -#define IMSC_RT 2 -#define IMSC_RX 4 -#define IMSC_TX 8 - -#define RIS_ROR 1 -#define RIS_RT 2 -#define RIS_RX 4 -#define RIS_TX 8 - -#define MIS_ROR 1 -#define MIS_RT 2 -#define MIS_RX 4 -#define MIS_TX 8 - -#define ICR_ROR 1 -#define ICR_RT 2 - -/* - * Timers/Counters. - */ -typedef struct { - IOREG32 TC_IR; - IOREG32 TC_TCR; - IOREG32 TC_TC; - IOREG32 TC_PR; - IOREG32 TC_PC; - IOREG32 TC_MCR; - IOREG32 TC_MR0; - IOREG32 TC_MR1; - IOREG32 TC_MR2; - IOREG32 TC_MR3; - IOREG32 TC_CCR; - IOREG32 TC_CR0; - IOREG32 TC_CR1; - IOREG32 TC_CR2; - IOREG32 TC_CR3; - IOREG32 TC_EMR; - IOREG32 TC_CTCR; -} TC; - -#define T0Base ((TC *)0xE0004000) -#define T0IR (T0Base->TC_IR) -#define T0TCR (T0Base->TC_TCR) -#define T0TC (T0Base->TC_TC) -#define T0PR (T0Base->TC_PR) -#define T0PC (T0Base->TC_PC) -#define T0MCR (T0Base->TC_MCR) -#define T0MR0 (T0Base->TC_MR0) -#define T0MR1 (T0Base->TC_MR1) -#define T0MR2 (T0Base->TC_MR2) -#define T0MR3 (T0Base->TC_MR3) -#define T0CCR (T0Base->TC_CCR) -#define T0CR0 (T0Base->TC_CR0) -#define T0CR1 (T0Base->TC_CR1) -#define T0CR2 (T0Base->TC_CR2) -#define T0CR3 (T0Base->TC_CR3) -#define T0EMR (T0Base->TC_EMR) -#define T0CTCR (T0Base->TC_CTCR) - -#define T1Base ((TC *)0xE0008000) -#define T1IR (T1Base->TC_IR) -#define T1TCR (T1Base->TC_TCR) -#define T1TC (T1Base->TC_TC) -#define T1PR (T1Base->TC_PR) -#define T1PC (T1Base->TC_PC) -#define T1MCR (T1Base->TC_MCR) -#define T1MR0 (T1Base->TC_MR0) -#define T1MR1 (T1Base->TC_MR1) -#define T1MR2 (T1Base->TC_MR2) -#define T1MR3 (T1Base->TC_MR3) -#define T1CCR (T1Base->TC_CCR) -#define T1CR0 (T1Base->TC_CR0) -#define T1CR1 (T1Base->TC_CR1) -#define T1CR2 (T1Base->TC_CR2) -#define T1CR3 (T1Base->TC_CR3) -#define T1EMR (T1Base->TC_EMR) -#define T1CTCR (T1Base->TC_CTCR) - -/* - * Watchdog. - */ -typedef struct { - IOREG32 WD_MOD; - IOREG32 WD_TC; - IOREG32 WD_FEED; - IOREG32 WD_TV; -} WD; - -#define WDBase ((WD *)0xE0000000) -#define WDMOD (WDBase->WD_MOD) -#define WDTC (WDBase->WD_TC) -#define WDFEED (WDBase->WD_FEED) -#define WDTV (WDBase->WD_TV) - -/* - * DAC. - */ -#define DACR (*((IOREG32 *)0xE006C000)) - -#endif /* _LPC214X_H_ */ - diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/pal_lld.c deleted file mode 100644 index afff9e7..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/pal_lld.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/pal_lld.c - * @brief LPC214x FIO low level driver code. - * @addtogroup LPC214x_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief LPC214x I/O ports configuration. - * @details FIO units and PINSEL registers initialization. - * - * @param[in] config the LPC214x ports configuration - */ -void _pal_lld_init(const PALConfig *config) { - - /* Enables the access through the fast registers.*/ - SCS = 3; - - /* I/O pads initial assignment, device drivers may change this setup at a - * later time.*/ - PINSEL0 = config->pinsel0; - PINSEL1 = config->pinsel1; - PINSEL2 = config->pinsel2; - - /* I/O pads direction initial setting.*/ - FIO0Base->FIO_MASK = 0; - FIO0Base->FIO_PIN = config->P0Data.pin; - FIO0Base->FIO_DIR = config->P0Data.dir; - FIO1Base->FIO_MASK = 0; - FIO1Base->FIO_PIN = config->P1Data.pin; - FIO1Base->FIO_DIR = config->P1Data.dir; -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->FIO_DIR &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - port->FIO_PIN |= mask; - case PAL_MODE_OUTPUT_PUSHPULL: - port->FIO_DIR |= mask; - break; - } -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/pal_lld.h deleted file mode 100644 index 8521534..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/pal_lld.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/pal_lld.h - * @brief LPC214x FIO low level driver header. - * @addtogroup LPC214x_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief FIO port setup info. - */ -typedef struct { - /** Initial value for FIO_PIN register.*/ - uint32_t pin; - /** Initial value for FIO_DIR register.*/ - uint32_t dir; -} lpc214x_fio_setup_t; - -/** - * @brief LPC214x FIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** @brief PINSEL0 initial value.*/ - uint32_t pinsel0; - /** @brief PINSEL1 initial value.*/ - uint32_t pinsel1; - /** @brief PINSEL2 initial value.*/ - uint32_t pinsel2; - /** @brief Port 0 setup data.*/ - lpc214x_fio_setup_t P0Data; - /** @brief Port 1 setup data.*/ - lpc214x_fio_setup_t P1Data; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Port Identifier. - */ -typedef FIO * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief FIO port 0 identifier. - */ -#define IOPORT1 FIO0Base - -/** - * @brief FIO port 1 identifier. - */ -#define IOPORT2 FIO1Base - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, please put them in a file named ioports_lld.c if so. */ -/*===========================================================================*/ - -/** - * @brief FIO subsystem initialization. - * @details Enables the access through the fast registers. - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads an I/O port. - * @details This function is implemented by reading the FIO PIN register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @return the port bits - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_readport(port) ((port)->FIO_PIN) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the FIO SET register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @return The latched logical states. - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_readlatch(port) ((port)->FIO_SET) - -/** - * @brief Writes a bits mask on a I/O port. - * @details This function is implemented by writing the FIO PIN register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be written on the specified port - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_writeport(port, bits) ((port)->FIO_PIN = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the FIO SET register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be ORed on the specified port - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_setport(port, bits) ((port)->FIO_SET = (bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the FIO CLR register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be cleared on the specified port - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_clearport(port, bits) ((port)->FIO_CLR = (bits)) - -/** - * @brief Writes a value on an I/O bus. - * @details This function is implemented by writing the FIO PIN and MASK - * registers, the implementation is not atomic because the multiple - * accesses. - * - * @param[in] port the port identifier - * @param[in] mask the group mask, a logical AND is performed on the output - * data - * @param[in] offset the group bit offset within the port - * @param[in] bits the bits to be written. Values exceeding the group width - * are masked. - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_writegroup(port, mask, offset, bits) { \ - (port)->FIO_MASK = ~((mask) << (offset)); \ - (port)->FIO_PIN = (bits) << (offset); \ - (port)->FIO_MASK = 0; \ -} - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -/** - * @brief Writes a logical state on an output pad. - * - * @param[in] port the port identifier - * @param[in] pad the pad number within the port - * @param[out] bit the logical value, the value must be @p 0 or @p 1 - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -/** - * @brief FIO port setup. - * @details This function programs the pins direction within a port. - */ -#define pal_lld_lpc214x_set_direction(port, dir) { \ - (port)->FIO_DIR = (dir); \ -} - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/platform.dox deleted file mode 100644 index 92d81a1..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/platform.dox +++ /dev/null @@ -1,97 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup LPC214x LPC214x Support - * @brief LPC214x specific support. - * @details The LPC214x support includes: - * - VIC support code. - * - I/O ports driver. - * - Buffered, interrupt driven, serial driver. - * - SPI driver. - * - A demo supporting the kernel test suite. - * - A C++ demo supporting the kernel test suite. - * - A demo integrating ChibiOS/RT with FatFS. - * . - * @ingroup ARM7 - */ - -/** - * @defgroup LPC214x_VIC VIC Support - * @brief VIC peripheral support. - * - * @ingroup LPC214x - */ - -/** - * @defgroup LPC214x_HAL LPC214x HAL Support - * @brief HAL support. - * - * @ingroup LPC214x - */ - -/** - * @defgroup LPC214x_PAL LPC214x I/O Ports Support - * @brief I/O Ports peripherals support. - * @details This module supports the LPC214x FIO controller. The controller - * supports the following features (see @ref PAL): - * - 32 bits wide ports. - * - Atomic set/reset functions. - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - *

Supported Setup Modes

- * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT). - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * . - * Any attempt to setup an invalid mode is ignored. - * - *

Suboptimal Behavior

- * - Pad/port toggling operations are not atomic. - * - Pad/group mode setup is not atomic. - * . - * @ingroup LPC214x - */ - -/** - * @defgroup LPC214x_SERIAL LPC214x UART Support - * @brief UART peripherals support. - * @details The serial driver supports the LPC214x UART peripherals. - * - * @ingroup LPC214x - */ - -/** - * @defgroup LPC214x_SPI LPC214x SPI Support - * @brief SSP peripheral support. - * @details The SPI driver supports the LPC214x SSP, the driver works in - * polling mode. - * - * @ingroup LPC214x - */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/platform.mk deleted file mode 100644 index cec96cc..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/platform.mk +++ /dev/null @@ -1,9 +0,0 @@ -# List of all the LPC214x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC214x/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC214x/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC214x/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC214x/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC214x/vic.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC214x diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/serial_lld.c deleted file mode 100644 index 73004c4..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/serial_lld.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/serial_lld.c - * @brief LPC214x low level serial driver code. - * - * @addtogroup LPC214x_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if USE_LPC214x_UART0 || defined(__DOXYGEN__) -/** @brief UART0 serial driver identifier.*/ -SerialDriver SD1; -#endif - -#if USE_LPC214x_UART1 || defined(__DOXYGEN__) -/** @brief UART1 serial driver identifier.*/ -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { - SERIAL_DEFAULT_BITRATE, - LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, - FCR_TRIGGER0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief UART initialization. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] config the architecture-dependent serial driver configuration - */ -static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - UART *u = sdp->uart; - - uint32_t div = PCLK / (config->sc_speed << 4); - u->UART_LCR = config->sc_lcr | LCR_DLAB; - u->UART_DLL = div; - u->UART_DLM = div >> 8; - u->UART_LCR = config->sc_lcr; - u->UART_FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; - u->UART_ACR = 0; - u->UART_FDR = 0x10; - u->UART_TER = TER_ENABLE; - u->UART_IER = IER_RBR | IER_STATUS; -} - -/** - * @brief UART de-initialization. - * - * @param[in] u pointer to an UART I/O block - */ -static void uart_deinit(UART *u) { - - u->UART_LCR = LCR_DLAB; - u->UART_DLL = 1; - u->UART_DLM = 0; - u->UART_LCR = 0; - u->UART_FDR = 0x10; - u->UART_IER = 0; - u->UART_FCR = FCR_RXRESET | FCR_TXRESET; - u->UART_ACR = 0; - u->UART_TER = TER_ENABLE; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] err UART LSR register value - */ -static void set_error(SerialDriver *sdp, IOREG32 err) { - sdflags_t sts = 0; - - if (err & LSR_OVERRUN) - sts |= SD_OVERRUN_ERROR; - if (err & LSR_PARITY) - sts |= SD_PARITY_ERROR; - if (err & LSR_FRAMING) - sts |= SD_FRAMING_ERROR; - if (err & LSR_BREAK) - sts |= SD_BREAK_DETECTED; - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -#if defined(__GNUC__) -__attribute__((noinline)) -#endif -/** - * @brief Common IRQ handler. - * @note Tries hard to clear all the pending interrupt sources, we dont want - * to go through the whole ISR and have another interrupt soon after. - * - * @param[in] sdp communication channel associated to the UART - */ -static void serve_interrupt(SerialDriver *sdp) { - UART *u = sdp->uart; - - while (TRUE) { - switch (u->UART_IIR & IIR_SRC_MASK) { - case IIR_SRC_NONE: - return; - case IIR_SRC_ERROR: - set_error(sdp, u->UART_LSR); - break; - case IIR_SRC_TIMEOUT: - case IIR_SRC_RX: - chSysLockFromIsr(); - if (chIQIsEmpty(&sdp->iqueue)) - chEvtBroadcastI(&sdp->ievent); - chSysUnlockFromIsr(); - while (u->UART_LSR & LSR_RBR_FULL) { - chSysLockFromIsr(); - if (chIQPutI(&sdp->iqueue, u->UART_RBR) < Q_OK) - sdAddFlagsI(sdp, SD_OVERRUN_ERROR); - chSysUnlockFromIsr(); - } - break; - case IIR_SRC_TX: - { - int i = LPC214x_UART_FIFO_PRELOAD; - do { - msg_t b; - - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - chSysUnlockFromIsr(); - if (b < Q_OK) { - u->UART_IER &= ~IER_THRE; - chSysLockFromIsr(); - chEvtBroadcastI(&sdp->oevent); - chSysUnlockFromIsr(); - break; - } - u->UART_THR = b; - } while (--i); - } - break; - default: - (void) u->UART_THR; - (void) u->UART_RBR; - } - } -} - -/** - * @brief Attempts a TX FIFO preload. - */ -static void preload(SerialDriver *sdp) { - UART *u = sdp->uart; - - if (u->UART_LSR & LSR_THRE) { - int i = LPC214x_UART_FIFO_PRELOAD; - do { - msg_t b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chEvtBroadcastI(&sdp->oevent); - return; - } - u->UART_THR = b; - } while (--i); - } - u->UART_IER |= IER_THRE; -} - -/** - * @brief Driver SD1 output notification. - */ -#if USE_LPC214x_UART0 || defined(__DOXYGEN__) -static void notify1(void) { - - preload(&SD1); -} -#endif - -/** - * @brief Driver SD2 output notification. - */ -#if USE_LPC214x_UART1 || defined(__DOXYGEN__) -static void notify2(void) { - - preload(&SD2); -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief UART0 IRQ handler. - */ -#if USE_LPC214x_UART0 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(UART0IrqHandler) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - VICVectAddr = 0; - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART1 IRQ handler. - */ -#if USE_LPC214x_UART1 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(UART1IrqHandler) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD2); - VICVectAddr = 0; - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_LPC214x_UART0 - sdObjectInit(&SD1, NULL, notify1); - SD1.uart = U0Base; - SetVICVector(UART0IrqHandler, LPC214x_UART0_PRIORITY, SOURCE_UART0); -#endif -#if USE_LPC214x_UART1 - sdObjectInit(&SD2, NULL, notify2); - SD2.uart = U1Base; - SetVICVector(UART1IrqHandler, LPC214x_UART1_PRIORITY, SOURCE_UART1); -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if USE_LPC214x_UART0 - if (&SD1 == sdp) { - PCONP = (PCONP & PCALL) | PCUART0; - VICIntEnable = INTMASK(SOURCE_UART0); - } -#endif -#if USE_LPC214x_UART1 - if (&SD2 == sdp) { - PCONP = (PCONP & PCALL) | PCUART1; - VICIntEnable = INTMASK(SOURCE_UART1); - } -#endif - } - uart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the UART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - uart_deinit(sdp->uart); -#if USE_LPC214x_UART0 - if (&SD1 == sdp) { - PCONP = (PCONP & PCALL) & ~PCUART0; - VICIntEnClear = INTMASK(SOURCE_UART0); - return; - } -#endif -#if USE_LPC214x_UART1 - if (&SD2 == sdp) { - PCONP = (PCONP & PCALL) & ~PCUART1; - VICIntEnClear = INTMASK(SOURCE_UART1); - return; - } -#endif - } -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/serial_lld.h deleted file mode 100644 index 5918fe5..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/serial_lld.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/serial_lld.h - * @brief LPC214x low level serial driver header. - * - * @addtogroup LPC214x_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UART0 driver enable switch. - * @details If set to @p TRUE the support for UART0 is included. - * @note The default is @p TRUE . - */ -#if !defined(USE_LPC214x_UART0) || defined(__DOXYGEN__) -#define USE_LPC214x_UART0 TRUE -#endif - -/** - * @brief UART1 driver enable switch. - * @details If set to @p TRUE the support for UART1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_LPC214x_UART1) || defined(__DOXYGEN__) -#define USE_LPC214x_UART1 TRUE -#endif - -/** - * @brief FIFO preload parameter. - * @details Configuration parameter, this values defines how many bytes are - * preloaded in the HW transmit FIFO for each interrupt, the maximum - * value is 16 the minimum is 1. - * @note An high value reduces the number of interrupts generated but can - * also increase the worst case interrupt response time because the - * preload loops. - */ -#if !defined(LPC214x_UART_FIFO_PRELOAD) || defined(__DOXYGEN__) -#define LPC214x_UART_FIFO_PRELOAD 16 -#endif - -/** - * @brief UART0 interrupt priority level setting. - */ -#if !defined(LPC214x_UART0_PRIORITY) || defined(__DOXYGEN__) -#define LPC214x_UART0_PRIORITY 1 -#endif - -/** - * @brief UART1 interrupt priority level setting. - */ -#if !defined(LPC214x_UART1_PRIORITY) || defined(__DOXYGEN__) -#define LPC214x_UART1_PRIORITY 2 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (LPC214x_UART_FIFO_PRELOAD < 1) || (LPC214x_UART_FIFO_PRELOAD > 16) -#error "invalid LPC214x_UART_FIFO_PRELOAD setting" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint32_t sdflags_t; - -/** - * @brief LPC214x Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /** - * @brief Initialization value for the LCR register. - */ - uint32_t sc_lcr; - /** - * @brief Initialization value for the FCR register. - */ - uint32_t sc_fcr; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - UART *uart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_LPC214x_UART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_LPC214x_UART1 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/spi_lld.c b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/spi_lld.c deleted file mode 100644 index 464a82c..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/spi_lld.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/spi_lld.c - * @brief LPC214x low level SPI driver code. - * @addtogroup LPC214x_SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if USE_LPC214x_SPI1 || defined(__DOXYGEN__) -/** @brief SPI1 driver identifier.*/ -SPIDriver SPID1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Synchronous SSP transfer. - * - * @param[in] n number of bytes to be exchanged - * - * @param[in] txbuf the pointer to the transmit buffer or @p NULL - * @param[out] rxbuf the pointer to the receive buffer or @p NULL - */ -void rw8(size_t n, const uint8_t *txbuf, uint8_t *rxbuf) { - size_t ntx = n; - - while (n > 0) { - uint32_t sr = SSPBase->SSP_SR; - if (sr & SR_RNE) { - uint8_t w = SSPBase->SSP_DR; - if (rxbuf != NULL) - *rxbuf++ = w; - n--; - continue; /* Priority over transmission. */ - } - if ((ntx > 0) && (sr & SR_TNF)) { - if (txbuf != NULL) - SSPBase->SSP_DR = *txbuf++; - else - SSPBase->SSP_DR = 0xFFFFFFFF; - ntx--; - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - */ -void spi_lld_init(void) { - -#if USE_LPC214x_SPI1 - spiObjectInit(&SPID1); -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_start(SPIDriver *spip) { - - if (spip->spd_state == SPI_STOP) { - /* Clock activation.*/ - PCONP = (PCONP & PCALL) | PCSPI1; - } - /* Configuration.*/ - SSPBase->SSP_CR1 = 0; - /* Emptying the receive FIFO, it happens to not be empty while debugging.*/ - while (SSPBase->SSP_SR & SR_RNE) - (void) SSPBase->SSP_DR; - SSPBase->SSP_CR0 = spip->spd_config->spc_cr0; - SSPBase->SSP_CPSR = spip->spd_config->spc_cpsr; - SSPBase->SSP_CR1 = spip->spd_config->spc_cr1 | CR1_SSE; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_stop(SPIDriver *spip) { - - if (spip->spd_state != SPI_STOP) { - SSPBase->SSP_CR1 = 0; - SSPBase->SSP_CR0 = 0; - SSPBase->SSP_CPSR = 0; - PCONP &= ~PCSPI1; - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This function transmits a series of idle words on the SPI bus and - * ignores the received data. This function can be invoked even - * when a slave select signal has not been yet asserted. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - (void)spip; - rw8(n, NULL, NULL); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This function performs a simultaneous transmit/receive operation. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - (void)spip; - rw8(n, txbuf, rxbuf); -} - -/** - * @brief Sends data ever the SPI bus. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - (void)spip; - rw8(n, txbuf, NULL); -} - -/** - * @brief Receives data from the SPI bus. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - (void)spip; - rw8(n, NULL, rxbuf); -} - -#endif /* CH_HAL_USE_SPI */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/spi_lld.h b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/spi_lld.h deleted file mode 100644 index 6e5af75..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/spi_lld.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/spi_lld.h - * @brief LPC214x low level SPI driver header. - * @addtogroup LPC214x_SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if CH_HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief SPI1 (SSP) driver enable switch. - * @details If set to @p TRUE the support for SPI0 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_LPC214x_SPI1) || defined(__DOXYGEN__) -#define USE_LPC214x_SPI1 TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief The chip select line port. - */ - ioportid_t spc_ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t spc_sspad; - /** - * @brief SSP CR0 initialization data. - */ - uint16_t spc_cr0; - /** - * @brief SSP CR1 initialization data. - */ - uint16_t spc_cr1; - /** - * @brief SSP CPSR initialization data. - */ - uint32_t spc_cpsr; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - spistate_t spd_state; -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex spd_mutex; -#elif CH_USE_SEMAPHORES - Semaphore spd_semaphore; -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ - /** - * @brief Current configuration data. - */ - const SPIConfig *spd_config; - /* End of the mandatory fields.*/ -} SPIDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_LPC214x_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/vic.c b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/vic.c deleted file mode 100644 index 44a9175..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/vic.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/vic.c - * @brief LPC214x VIC peripheral support code. - * - * @addtogroup LPC214x_VIC - * @{ - */ - -#include "ch.h" - -/** - * @brief VIC Initialization. - * @note Better reset everything in the VIC, it is a HUGE source of trouble. - */ -void vic_init(void) { - int i; - - VIC *vic = VICBase; - vic->VIC_IntSelect = 0; /* All sources assigned to IRQ. */ - vic->VIC_SoftIntClear = ALLINTMASK; /* No interrupts enforced */ - vic->VIC_IntEnClear = ALLINTMASK; /* All sources disabled. */ - for (i = 0; i < 16; i++) { - vic->VIC_VectCntls[i] = 0; - vic->VIC_VectAddrs[i] = 0; - vic->VIC_VectAddr = 0; - } -} - -/** - * @brief Initializes a VIC vector. - * @details Set a vector for an interrupt source and enables it. - * - * @param[in] handler the pointer to the IRQ service routine - * @param[in] vector the vector number - * @param[in] source the IRQ source to be associated to the vector - */ -void SetVICVector(void *handler, int vector, int source) { - - VIC *vicp = VICBase; - vicp->VIC_VectAddrs[vector] = (IOREG32)handler; - vicp->VIC_VectCntls[vector] = (IOREG32)(source | 0x20); -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/vic.h b/ChibiOS_2.0.8/os/hal/platforms/LPC214x/vic.h deleted file mode 100644 index 5a771c7..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/LPC214x/vic.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file LPC214x/vic.h - * @brief LPC214x VIC peripheral support header. - * - * @addtogroup LPC214x_VIC - * @{ - */ - -#ifndef _VIC_H_ -#define _VIC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - void vic_init(void); - void SetVICVector(void *handler, int vector, int source); -#ifdef __cplusplus -} -#endif - -#endif /* _VIC_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/MSP430/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/MSP430/hal_lld.c deleted file mode 100644 index 88d64a6..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/MSP430/hal_lld.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/hal_lld.c - * @brief MSP430 HAL subsystem low level driver source. - * @addtogroup MSP430_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -const PALConfig pal_default_config = -{ -#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__) - {VAL_P1OUT, VAL_P1DIR}, -#endif -#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__) - {VAL_P2OUT, VAL_P2DIR}, -#endif -#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__) - {VAL_P3OUT, VAL_P3DIR}, -#endif -#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__) - {VAL_P4OUT, VAL_P4DIR}, -#endif -#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__) - {VAL_P5OUT, VAL_P5DIR}, -#endif -#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__) - {VAL_P6OUT, VAL_P6DIR}, -#endif -}; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - - /* - * Clock sources setup. - */ - DCOCTL = VAL_DCOCTL; - BCSCTL1 = VAL_BCSCTL1; -#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK - do { - int i; - IFG1 &= ~OFIFG; - for (i = 255; i > 0; i--) - asm("nop"); - } while (IFG1 & OFIFG); -#endif - BCSCTL2 = VAL_BCSCTL2; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/MSP430/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/MSP430/hal_lld.h deleted file mode 100644 index 2c46bd1..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/MSP430/hal_lld.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/hal_lld.h - * @brief MSP430 HAL subsystem low level driver header. - * @addtogroup MSP430_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "msp430x16x.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "MSP430x16x" - -#define MSP430_CLOCK_SOURCE_XT2CLK 0 /** @brief XT2CLK clock selector. */ -#define MSP430_CLOCK_SOURCE_DCOCLK 1 /** @brief DCOCLK clock selector. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Clock source. - * @details The clock source can be selected from: - * - @p MSP430_CLOCK_SOURCE_XT2CLK. - * - @p MSP430_CLOCK_SOURCE_DCOCLK. - * . - */ -#if !defined(MSP430_USE_CLOCK) || defined(__DOXYGEN__) -#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Calculating the derived clock constants. - */ -#define ACLK LFXT1CLK -#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK -#define MCLK XT2CLK -#define SMCLK (XT2CLK / 8) -#elif MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_DCOCLK -#define MCLK DCOCLK -#define SMCLK DCOCLK -#else -#error "unknown clock source specified" -#endif - -/* - * Calculating the initialization values. - */ -#define VAL_DCOCTL (DCO0 | DCO1) -#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK -#define VAL_BCSCTL1 (RSEL2) -#define VAL_BCSCTL2 (SELM_2 | DIVM_0 | DIVS_3 | SELS) -#endif -#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_DCOCLK -#define VAL_BCSCTL1 (XT2OFF | RSEL2) -#define VAL_BCSCTL2 (SELM_0 | DIVM_0 | DIVS_0) -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/MSP430/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/MSP430/pal_lld.c deleted file mode 100644 index cdf1932..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/MSP430/pal_lld.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/pal_lld.c - * @brief MSP430 Digital I/O low level driver code. - * @addtogroup MSP430_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief MSP430 I/O ports configuration. - * - * @param[in] config the MSP430 ports configuration - * - * @note The @p PxIFG, @p PxIE and @p PxSEL registers are cleared. @p PxOUT - * and @p PxDIR are configured as specified. - */ -void _pal_lld_init(const PALConfig *config) { - -#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__) - IOPORT1->iop_full.ie.reg_p = 0; - IOPORT1->iop_full.ifg.reg_p = 0; - IOPORT1->iop_full.sel.reg_p = 0; - IOPORT1->iop_common.out = config->P1Data.out; - IOPORT1->iop_common.dir = config->P1Data.dir; -#endif - -#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__) - IOPORT2->iop_full.ie.reg_p = 0; - IOPORT2->iop_full.ifg.reg_p = 0; - IOPORT2->iop_full.sel.reg_p = 0; - IOPORT2->iop_common.out = config->P2Data.out; - IOPORT2->iop_common.dir = config->P2Data.dir; -#endif - -#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__) - IOPORT3->iop_simple.sel.reg_p = 0; - IOPORT3->iop_common.out = config->P3Data.out; - IOPORT3->iop_common.dir = config->P3Data.dir; -#endif - -#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__) - IOPORT4->iop_simple.sel.reg_p = 0; - IOPORT4->iop_common.out = config->P4Data.out; - IOPORT4->iop_common.dir = config->P4Data.dir; -#endif - -#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__) - IOPORT5->iop_simple.sel.reg_p = 0; - IOPORT5->iop_common.out = config->P5Data.out; - IOPORT5->iop_common.dir = config->P5Data.dir; -#endif - -#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__) - IOPORT6->iop_simple.sel.reg_p = 0; - IOPORT6->iop_common.out = config->P6Data.out; - IOPORT6->iop_common.dir = config->P6Data.dir; -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by - * the MSP430x1xx Family User's Guide. Unconnected pads are set to - * high logic state by default. - * @note This function does not alter the @p PxSEL registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->iop_common.dir.reg_p &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - port->iop_common.out.reg_p |= mask; - case PAL_MODE_OUTPUT_PUSHPULL: - port->iop_common.dir.reg_p |= mask; - break; - } -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/MSP430/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/MSP430/pal_lld.h deleted file mode 100644 index 1fa2d19..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/MSP430/pal_lld.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/pal_lld.h - * @brief MSP430 Digital I/O low level driver header. - * @addtogroup MSP430_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief Simplified MSP430 I/O port representation. - * @details This structure represents the common part of all the MSP430 I/O - * ports. - */ -struct port_common_t { - ioregister_t in; - ioregister_t out; - ioregister_t dir; -}; - -/** - * @brief Generic MSP430 I/O port. - */ -union __ioport { - struct port_common_t iop_common; - struct port_simple_t iop_simple; - struct port_full_t iop_full; -}; - -/** - * @brief Setup registers common to all the MSP430 ports. - */ -typedef struct { - ioregister_t out; - ioregister_t dir; -} msp430_dio_setup_t; - -/** - * @brief MSP430 I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { -#if defined(__MSP430_HAS_PORT1__) || \ - defined(__MSP430_HAS_PORT1_R__) || \ - defined(__DOXYGEN__) - /** @brief Port 1 setup data.*/ - msp430_dio_setup_t P1Data; -#endif -#if defined(__MSP430_HAS_PORT2__) || \ - defined(__MSP430_HAS_PORT2_R__) || \ - defined(__DOXYGEN__) - /** @brief Port 2 setup data.*/ - msp430_dio_setup_t P2Data; -#endif -#if defined(__MSP430_HAS_PORT3__) || \ - defined(__MSP430_HAS_PORT3_R__) || \ - defined(__DOXYGEN__) - /** @brief Port 3 setup data.*/ - msp430_dio_setup_t P3Data; -#endif -#if defined(__MSP430_HAS_PORT4__) || \ - defined(__MSP430_HAS_PORT4_R__) || \ - defined(__DOXYGEN__) - /** @brief Port 4 setup data.*/ - msp430_dio_setup_t P4Data; -#endif -#if defined(__MSP430_HAS_PORT5__) || \ - defined(__MSP430_HAS_PORT5_R__) || \ - defined(__DOXYGEN__) - /** @brief Port 5 setup data.*/ - msp430_dio_setup_t P5Data; -#endif -#if defined(__MSP430_HAS_PORT6__) || \ - defined(__MSP430_HAS_PORT6_R__) || \ - defined(__DOXYGEN__) - /** @brief Port 6 setup data.*/ - msp430_dio_setup_t P6Data; -#endif -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 8 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint8_t ioportmask_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef union __ioport * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief I/O port A identifier. - * @details This port identifier is mapped on the MSP430 port 1 (P1). - */ -#if defined(__MSP430_HAS_PORT1__) || \ - defined(__MSP430_HAS_PORT1_R__) || \ - defined(__DOXYGEN__) -#define IOPORT1 ((ioportid_t)0x0020) -#endif - -/** - * @brief I/O port B identifier. - * @details This port identifier is mapped on the MSP430 port 2 (P2). - */ -#if defined(__MSP430_HAS_PORT2__) || \ - defined(__MSP430_HAS_PORT2_R__) || \ - defined(__DOXYGEN__) -#define IOPORT2 ((ioportid_t)0x0028) -#endif - -/** - * @brief I/O port C identifier. - * @details This port identifier is mapped on the MSP430 port 3 (P3). - */ -#if defined(__MSP430_HAS_PORT3__) || \ - defined(__MSP430_HAS_PORT3_R__) || \ - defined(__DOXYGEN__) -#define IOPORT3 ((ioportid_t)0x0018) -#endif - -/** - * @brief I/O port D identifier. - * @details This port identifier is mapped on the MSP430 port 4 (P4). - */ -#if defined(__MSP430_HAS_PORT4__) || \ - defined(__MSP430_HAS_PORT4_R__) || \ - defined(__DOXYGEN__) -#define IOPORT4 ((ioportid_t)0x001c) -#endif - -/** - * @brief I/O port E identifier. - * @details This port identifier is mapped on the MSP430 port 5 (P5). - */ -#if defined(__MSP430_HAS_PORT5__) || \ - defined(__MSP430_HAS_PORT5_R__) || \ - defined(__DOXYGEN__) -#define IOPORT5 ((ioportid_t)0x0030) -#endif - -/** - * @brief I/O port F identifier. - * @details This port identifier is mapped on the MSP430 port 6 (P6). - */ -#if defined(__MSP430_HAS_PORT6__) || \ - defined(__MSP430_HAS_PORT6_R__) || \ - defined(__DOXYGEN__) -#define IOPORT6 ((ioportid_t)0x0034) -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in a file named pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * @details In MSP430 programs all the ports as input. - * - * @param[in] config the MSP430 ports configuration - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * @details This function is implemented by reading the PxIN register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @return The port bits. - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_readport(port) ((port)->iop_common.in.reg_p) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the PxOUT register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @return The latched logical states. - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_readlatch(port) ((port)->iop_common.out.reg_p) - -/** - * @brief Writes a bits mask on a I/O port. - * @details This function is implemented by writing the PxOUT register, the - * implementation has no side effects. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be written on the specified port - * - * @note This function is not meant to be invoked directly by the application - * code. - */ -#define pal_lld_writeport(port, bits) { \ - (port)->iop_common.out.reg_p = (bits); \ -} - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by - * the MSP430x1xx Family User's Guide. - * @note This function does not alter the @p PxSEL registers. Alternate - * functions setup must be handled by device-specific code. - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* _PAL_LLD_H_ */ - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/MSP430/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/MSP430/platform.dox deleted file mode 100644 index 2eec40e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/MSP430/platform.dox +++ /dev/null @@ -1,74 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup MSP430_DRIVERS MSP430 Drivers - * @brief Device drivers included in the MSP430 support. - * - * @ingroup MSP430 - */ - -/** - * @defgroup MSP430_HAL MSP430 HAL Support - * @brief HAL support. - * - * @ingroup MSP430_DRIVERS - */ - -/** - * @defgroup MSP430_PAL MSP430 I/O Ports Support - * @brief I/O Ports peripherals support. - * @details This module supports the MSP430 Digital I/O controller. The - * controller supports the following features (see @ref PAL): - * - 8 bits wide ports. - * - Atomic set/reset/toggle functions because special MSP430 instruction set. - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - *

Supported Setup Modes

- * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * . - * Any attempt to setup an invalid mode is ignored. - * - *

Suboptimal Behavior

- * Some MSP430 I/O ports features are less than optimal: - * - Bus/group writing is not atomic. - * - Pad/group mode setup is not atomic. - * . - * @ingroup MSP430_DRIVERS - */ - -/** - * @defgroup MSP430_SERIAL MSP430 USART Support - * @brief USART support. - * @details The serial driver supports both the MSP430 USARTs in asynchronous - * mode. - * - * @ingroup MSP430_DRIVERS - */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/MSP430/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/MSP430/platform.mk deleted file mode 100644 index a31b534..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/MSP430/platform.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of all the MSP430 platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/MSP430/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/MSP430/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/MSP430/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/MSP430 diff --git a/ChibiOS_2.0.8/os/hal/platforms/MSP430/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/MSP430/serial_lld.c deleted file mode 100644 index 09b7826..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/MSP430/serial_lld.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/serial_lld.c - * @brief MSP430 low level serial driver code. - * - * @addtogroup MSP430_SERIAL - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if USE_MSP430_USART0 || defined(__DOXYGEN__) -/** @brief USART0 serial driver identifier.*/ -SerialDriver SD1; -#endif -#if USE_MSP430_USART1 || defined(__DOXYGEN__) -/** @brief USART1 serial driver identifier.*/ -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { - UBR(SERIAL_DEFAULT_BITRATE), - 0, - CHAR -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void set_error(SerialDriver *sdp, uint8_t urctl) { - sdflags_t sts = 0; - - if (urctl & OE) - sts |= SD_OVERRUN_ERROR; - if (urctl & PE) - sts |= SD_PARITY_ERROR; - if (urctl & FE) - sts |= SD_FRAMING_ERROR; - if (urctl & BRK) - sts |= SD_BREAK_DETECTED; - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -#if USE_MSP430_USART0 || defined(__DOXYGEN__) -static void notify1(void) { - - if (!(U0IE & UTXIE0)) { - msg_t b = sdRequestDataI(&SD1); - if (b != Q_EMPTY) { - U0IE |= UTXIE0; - U0TXBUF = (uint8_t)b; - } - } -} - -/** - * @brief USART0 initialization. - * - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart0_init(const SerialConfig *config) { - - U0CTL = SWRST; /* Resets the USART. */ - /* USART init */ - U0TCTL = SSEL0 | SSEL1; /* SMCLK as clock source. */ - U0MCTL = config->sc_mod; /* Modulator. */ - U0BR1 = (uint8_t)(config->sc_div >> 8); /* Divider high. */ - U0BR0 = (uint8_t)(config->sc_div >> 0); /* Divider low. */ - /* Clear USART status.*/ - (void)U0RXBUF; - U0RCTL = 0; - /* USART enable.*/ - U0ME |= UTXE0 + URXE0; /* Enables the USART. */ - U0CTL = config->sc_ctl & ~SWRST; /* Various settings. */ - U0IE |= URXIE0; /* Enables RX interrupt. */ -} - -/** - * @brief USART0 de-initialization. - */ -static void usart0_deinit(void) { - - U0IE &= ~URXIE0; - U0CTL = SWRST; -} -#endif /* USE_MSP430_USART0 */ - -#if USE_MSP430_USART1 || defined(__DOXYGEN__) -static void notify2(void) { - - if (!(U1IE & UTXIE1)) { - msg_t b = sdRequestDataI(&SD2); - if (b != Q_EMPTY) { - U1IE |= UTXIE1; - U1TXBUF = (uint8_t)b; - } - } -} - -/** - * @brief USART1 initialization. - * - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart1_init(const SerialConfig *config) { - - U1CTL = SWRST; /* Resets the USART. */ - /* USART init.*/ - U1TCTL = SSEL0 | SSEL1; /* SMCLK as clock source. */ - U1MCTL = config->sc_mod; /* Modulator. */ - U1BR1 = (uint8_t)(config->sc_div >> 8); /* Divider high. */ - U1BR0 = (uint8_t)(config->sc_div >> 0); /* Divider low. */ - /* Clear USART status.*/ - (void)U0RXBUF; - U1RCTL = 0; - /* USART enable.*/ - U1ME |= UTXE0 + URXE0; /* Enables the USART. */ - U1CTL = config->sc_ctl & ~SWRST; /* Various settings. */ - U1IE |= URXIE0; /* Enables RX interrupt. */ -} - -/** - * @brief USART1 de-initialization. - */ -static void usart1_deinit(void) { - - U1IE &= ~URXIE0; - U1CTL = SWRST; -} -#endif /* USE_MSP430_USART1 */ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_MSP430_USART0 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(USART0TX_VECTOR) { - msg_t b; - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - b = sdRequestDataI(&SD1); - chSysUnlockFromIsr(); - if (b < Q_OK) - U0IE &= ~UTXIE0; - else - U0TXBUF = b; - - CH_IRQ_EPILOGUE(); -} - -CH_IRQ_HANDLER(USART0RX_VECTOR) { - uint8_t urctl; - - CH_IRQ_PROLOGUE(); - - if ((urctl = U0RCTL) & RXERR) - set_error(&SD1, urctl); - chSysLockFromIsr(); - sdIncomingDataI(&SD1, U0RXBUF); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_MSP430_USART0 */ - -#if USE_MSP430_USART1 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(USART1TX_VECTOR) { - msg_t b; - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - b = sdRequestDataI(&SD2); - chSysUnlockFromIsr(); - if (b < Q_OK) - U1IE &= ~UTXIE1; - else - U1TXBUF = b; - - CH_IRQ_EPILOGUE(); -} - -CH_IRQ_HANDLER(USART1RX_VECTOR) { - uint8_t urctl; - - CH_IRQ_PROLOGUE(); - - if ((urctl = U1RCTL) & RXERR) - set_error(&SD2, urctl); - chSysLockFromIsr(); - sdIncomingDataI(&SD2, U1RXBUF); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_MSP430_USART1 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_MSP430_USART0 - sdObjectInit(&SD1, NULL, notify1); - /* I/O pins for USART0.*/ - P3SEL |= BV(4) + BV(5); -#endif - -#if USE_MSP430_USART1 - sdObjectInit(&SD2, NULL, notify2); - /* I/O pins for USART1.*/ - P3SEL |= BV(6) + BV(7); -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -#if USE_MSP430_USART0 - if (&SD1 == sdp) { - usart0_init(config); - return; - } -#endif -#if USE_MSP430_USART1 - if (&SD2 == sdp) { - usart1_init(config); - return; - } -#endif -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - -#if USE_MSP430_USART0 - if (&SD1 == sdp) { - usart0_deinit(); - return; - } -#endif -#if USE_MSP430_USART1 - if (&SD2 == sdp) { - usart1_deinit(); - return; - } -#endif -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/MSP430/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/MSP430/serial_lld.h deleted file mode 100644 index 13927a4..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/MSP430/serial_lld.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/serial_lld.h - * @brief MSP430 low level serial driver header. - * - * @addtogroup MSP430_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief USART0 driver enable switch. - * @details If set to @p TRUE the support for USART0 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_MSP430_USART0) || defined(__DOXYGEN__) -#define USE_MSP430_USART0 TRUE -#endif - -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(USE_MSP430_USART1) || defined(__DOXYGEN__) -#define USE_MSP430_USART1 TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint8_t sdflags_t; - -/** - * @brief MSP430 Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Initialization value for the UBRx registers. - */ - uint16_t sc_div; - /** - * @brief Initialization value for the MOD register. - */ - uint8_t sc_mod; - /** - * @brief Initialization value for the CTL register. - */ - uint8_t sc_ctl; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Macro for baud rate computation. - * @note Make sure the final baud rate is within tolerance. - */ -#define UBR(b) (SMCLK / (b)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_MSP430_USART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_MSP430_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/console.c b/ChibiOS_2.0.8/os/hal/platforms/Posix/console.c deleted file mode 100644 index 2ae2da4..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/console.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file console.c - * @brief Simulator console driver code. - * @{ - */ - -#include - -#include "ch.h" -#include "console.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Console driver 1. - */ -BaseChannel CD1; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - - -static size_t writes(void *ip, const uint8_t *bp, size_t n) { - size_t ret; - - (void)ip; - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t reads(void *ip, uint8_t *bp, size_t n) { - - (void)ip; - return fread(bp, 1, n, stdin); -} - -static bool_t putwouldblock(void *ip) { - - (void)ip; - return FALSE; -} - -static bool_t getwouldblock(void *ip) { - - (void)ip; - return TRUE; -} - -static msg_t putt(void *ip, uint8_t b, systime_t time) { - - (void)ip; - (void)time; - fputc(b, stdout); - fflush(stdout); - return RDY_OK; -} - -static msg_t gett(void *ip, systime_t time) { - - (void)ip; - (void)time; - return fgetc(stdin); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { - size_t ret; - - (void)ip; - (void)time; - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { - - (void)ip; - (void)time; - return fread(bp, 1, n, stdin); -} - -static const struct BaseChannelVMT vmt = { - writes, reads, putwouldblock, getwouldblock, putt, gett, writet, readt -}; - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void conInit(void) { - - CD1.vmt = &vmt; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/console.h b/ChibiOS_2.0.8/os/hal/platforms/Posix/console.h deleted file mode 100644 index 62e4a51..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/console.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file console.h - * @brief Simulator console driver header. - * @{ - */ - -#ifndef _CONSOLE_H_ -#define _CONSOLE_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern BaseChannel CD1; - -#ifdef __cplusplus -extern "C" { -#endif - void conInit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CONSOLE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/Posix/hal_lld.c deleted file mode 100644 index 05a252e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/hal_lld.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Posix/hal_lld.c - * @brief Posix HAL subsystem low level driver code. - * - * @addtogroup POSIX_HAL - * @{ - */ - -#include -#include -#include - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -static struct timeval nextcnt; -static struct timeval tick = {0, 1000000 / CH_FREQUENCY}; - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) -const PALConfig pal_default_config = { - {0, 0, 0}, - {0, 0, 0} -}; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - -#if defined(__APPLE__) - puts("ChibiOS/RT simulator (OS X)\n"); -#else - puts("ChibiOS/RT simulator (Linux)\n"); -#endif - gettimeofday(&nextcnt, NULL); - timeradd(&nextcnt, &tick, &nextcnt); -} - -/** - * @brief Interrupt simulation. - */ -void ChkIntSources(void) { - struct timeval tv; - -#if CH_HAL_USE_SERIAL - if (sd_lld_interrupt_pending()) { - if (chSchIsRescRequiredExI()) - chSchDoRescheduleI(); - return; - } -#endif - - gettimeofday(&tv, NULL); - if (timercmp(&tv, &nextcnt, >=)) { - timeradd(&nextcnt, &tick, &nextcnt); - chSysTimerHandlerI(); - if (chSchIsRescRequiredExI()) - chSchDoRescheduleI(); - } -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/Posix/hal_lld.h deleted file mode 100644 index 4aaab05..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/hal_lld.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Posix/hal_lld.h - * @brief Posix simulator HAL subsystem low level driver header. - * - * @addtogroup POSIX_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include -#include -#include - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "Linux" - -#define SOCKET int -#define INVALID_SOCKET -1 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void ChkIntSources(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/Posix/pal_lld.c deleted file mode 100644 index 82a0b2e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/pal_lld.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Posix/pal_lld.c - * @brief Posix low level simulated PAL driver code. - * - * @addtogroup POSIX_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief VIO1 simulated port. - */ -sim_vio_port_t vio_port_1; - -/** - * @brief VIO2 simulated port. - */ -sim_vio_port_t vio_port_2; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->dir &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - port->latch |= mask; - case PAL_MODE_OUTPUT_PUSHPULL: - port->dir |= mask; - break; - } -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/Posix/pal_lld.h deleted file mode 100644 index 9cac72e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/pal_lld.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Posix/pal_lld.h - * @brief Posix low level simulated PAL driver header. - * - * @addtogroup POSIX_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_OUTPUT_OPENDRAIN -#undef PAL_MODE_INPUT_ANALOG - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief VIO port structure. - */ -typedef struct { - /** - * @brief VIO_LATCH register. - * @details This register represents the output latch of the VIO port. - */ - uint32_t latch; - /** - * @brief VIO_PIN register. - * @details This register represents the logical level at the VIO port - * pin level. - */ - uint32_t pin; - /** - * @brief VIO_DIR register. - * @details Direction of the VIO port bits, 0=input, 1=output. - */ - uint32_t dir; -} sim_vio_port_t; - -/** - * @brief Virtual I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** - * @brief Virtual port 1 setup data. - */ - sim_vio_port_t VP1Data; - /** - * @brief Virtual port 2 setup data. - */ - sim_vio_port_t VP2Data; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Port Identifier. - */ -typedef sim_vio_port_t *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief VIO port 1 identifier. - */ -#define IOPORT1 (&vio_port_1) - -/** - * @brief VIO port 2 identifier. - */ -#define IOPORT2 (&vio_port_2) - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - */ -#define pal_lld_init(config) { \ - vio_port_1 = (config)->VP1Data; \ - vio_port_2 = (config)->VP2Data; \ -} - -/** - * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The port bits. - */ -#define pal_lld_readport(port) ((port)->pin) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The latched logical states. - */ -#define pal_lld_readlatch(port) ((port)->latch) - -/** - * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - */ -#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] mode group mode - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -#if !defined(__DOXYGEN__) -extern sim_vio_port_t vio_port_1; -extern sim_vio_port_t vio_port_2; -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/Posix/platform.mk deleted file mode 100644 index ea0c2e4..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/platform.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of all the Posix platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Posix/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/Posix/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/Posix/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Posix diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/Posix/serial_lld.c deleted file mode 100644 index d953e49..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/serial_lld.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Posix/serial_lld.c - * @brief Posix low level simulated serial driver code. - * - * @addtogroup POSIX_SERIAL - * @{ - */ - -#include -#include -#include -#include -#include -#include - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief Serial driver 1 identifier.*/ -#if USE_SIM_SERIAL1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif -/** @brief Serial driver 2 identifier.*/ -#if USE_SIM_SERIAL2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { -}; - -static u_long nb = 1; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void init(SerialDriver *sdp, uint16_t port) { - struct sockaddr_in sad; - struct protoent *prtp; - - if ((prtp = getprotobyname("tcp")) == NULL) { - printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); - goto abort; - } - - sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); - if (sdp->com_listen == INVALID_SOCKET) { - printf("%s: Error creating simulator socket\n", sdp->com_name); - goto abort; - } - - if (ioctl(sdp->com_listen, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); - goto abort; - } - - memset(&sad, 0, sizeof(sad)); - sad.sin_family = AF_INET; - sad.sin_addr.s_addr = INADDR_ANY; - sad.sin_port = htons(port); - if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { - printf("%s: Error binding socket\n", sdp->com_name); - goto abort; - } - - if (listen(sdp->com_listen, 1) != 0) { - printf("%s: Error listening socket\n", sdp->com_name); - goto abort; - } - printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); - return; - -abort: - if (sdp->com_listen != INVALID_SOCKET) - close(sdp->com_listen); - exit(1); -} - -static bool_t connint(SerialDriver *sdp) { - - if (sdp->com_data == INVALID_SOCKET) { - struct sockaddr addr; - socklen_t addrlen = sizeof(addr); - - if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) - return FALSE; - - if (ioctl(sdp->com_data, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); - goto abort; - } - sdAddFlagsI(sdp, SD_CONNECTED); - return TRUE; - } - return FALSE; -abort: - if (sdp->com_listen != INVALID_SOCKET) - close(sdp->com_listen); - if (sdp->com_data != INVALID_SOCKET) - close(sdp->com_data); - exit(1); -} - -static bool_t inint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int i; - uint8_t data[32]; - - /* - * Input. - */ - int n = recv(sdp->com_data, data, sizeof(data), 0); - switch (n) { - case 0: - close(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - sdAddFlagsI(sdp, SD_DISCONNECTED); - return FALSE; - case INVALID_SOCKET: - if (errno == EWOULDBLOCK) - return FALSE; - close(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - for (i = 0; i < n; i++) - sdIncomingDataI(sdp, data[i]); - return TRUE; - } - return FALSE; -} - -static bool_t outint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int n; - uint8_t data[1]; - - /* - * Input. - */ - n = sdRequestDataI(sdp); - if (n < 0) - return FALSE; - data[0] = (uint8_t)n; - n = send(sdp->com_data, data, sizeof(data), 0); - switch (n) { - case 0: - close(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - sdAddFlagsI(sdp, SD_DISCONNECTED); - return FALSE; - case INVALID_SOCKET: - if (errno == EWOULDBLOCK) - return FALSE; - close(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - return TRUE; - } - return FALSE; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_SIM_SERIAL1 - sdObjectInit(&SD1, NULL, NULL); - SD1.com_listen = INVALID_SOCKET; - SD1.com_data = INVALID_SOCKET; - SD1.com_name = "SD1"; -#endif - -#if USE_SIM_SERIAL2 - sdObjectInit(&SD2, NULL, NULL); - SD2.com_listen = INVALID_SOCKET; - SD2.com_data = INVALID_SOCKET; - SD2.com_name = "SD2"; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -#if USE_SIM_SERIAL1 - if (sdp == &SD1) - init(&SD1, SIM_SD1_PORT); -#endif - -#if USE_SIM_SERIAL2 - if (sdp == &SD2) - init(&SD2, SIM_SD2_PORT); -#endif -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - (void)sdp; -} - -bool_t sd_lld_interrupt_pending(void) { - - return connint(&SD1) || connint(&SD2) || - inint(&SD1) || inint(&SD2) || - outint(&SD1) || outint(&SD2); -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Posix/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/Posix/serial_lld.h deleted file mode 100644 index bbf6a5e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Posix/serial_lld.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Posix/serial_lld.h - * @brief Posix low level simulated serial driver header. - * - * @addtogroup POSIX_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 1024 -#endif - -/** - * @brief SD1 driver enable switch. - * @details If set to @p TRUE the support for SD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SIM_SERIAL1) || defined(__DOXYGEN__) -#define USE_SIM_SERIAL1 TRUE -#endif - -/** - * @brief SD2 driver enable switch. - * @details If set to @p TRUE the support for SD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SIM_SERIAL2) || defined(__DOXYGEN__) -#define USE_SIM_SERIAL2 TRUE -#endif - -/** - * @brief Listen port for SD1. - */ -#if !defined(SD1_PORT) || defined(__DOXYGEN__) -#define SIM_SD1_PORT 29001 -#endif - -/** - * @brief Listen port for SD2. - */ -#if !defined(SD2_PORT) || defined(__DOXYGEN__) -#define SIM_SD2_PORT 29002 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint32_t sdflags_t; - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Listen socket for simulated serial port.*/ \ - SOCKET com_listen; \ - /* Data socket for simulated serial port.*/ \ - SOCKET com_data; \ - /* Port readable name.*/ \ - const char *com_name; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_SIM_SERIAL1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_SIM_SERIAL2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); - bool_t sd_lld_interrupt_pending(void); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/SPC56x/hal_lld.c deleted file mode 100644 index b718210..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/hal_lld.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file SPC56x/hal_lld.c - * @brief SPC563 HAL subsystem low level driver source. - * - * @addtogroup SPC563_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - extern void _vectors(void); - uint32_t n; - - /* Enables the branch prediction, clears and enables the BTB into the - BUCSR special register (1013).*/ - asm volatile ("li %%r3, 0x0201 \t\n" - "mtspr 1013, %%r3": : : "r3"); - - /* FLASH wait states and prefetching setup.*/ - CFLASH0.BIUCR.R = SPC563_FLASH_BIUCR | SPC563_FLASH_WS; - CFLASH0.BIUCR2.R = 0; - CFLASH0.PFCR3.R = 0; - - /* Optimal crossbar settings. The DMA priority is placed above the CPU - priority in order to not starve I/O activities while the CPU is - excuting tight loops (FLASH and SRAM slave ports only). - The SRAM is parked on the load/store port, for some unknown reason it - is defaulted on the instructions port and this kills performance.*/ - XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/ - XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities: - eDMA (1): 0 (highest) - Core Instructions (0): 1 - Undocumented (2): 2 - Core Data (4): 3 */ - XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities: - eDMA (1): 0 (highest) - Core Instructions (0): 1 - Undocumented (2): 2 - Core Data (4): 3 */ - - /* Downcounter timer initialized for system tick use, TB enabled for debug - and measurements.*/ - n = SPC563_SYSCLK / CH_FREQUENCY; - asm volatile ("li %%r3, 0 \t\n" - "mtspr 284, %%r3 \t\n" /* Clear TBL register. */ - "mtspr 285, %%r3 \t\n" /* Clear TBU register. */ - "mtspr 22, %[n] \t\n" /* Init. DEC register. */ - "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ - "li %%r3, 0x4000 \t\n" /* TBEN bit. */ - "mtspr 1008, %%r3 \t\n" /* HID0 register. */ - "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ - "mtspr 340, %%r3" /* TCR register. */ - : : [n] "r" (n) : "r3"); - - /* INTC initialization, software vector mode, 4 bytes vectors, starting - at priority 0.*/ - INTC.MCR.R = 0; - INTC.CPR.R = 0; - INTC.IACKR.R = (uint32_t)_vectors; -} - -/** - * @brief SPC563 clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h and - * @p hal_lld.h - */ -void spc563_clock_init(void) { - - /* PLL activation.*/ - FMPLL.ESYNCR1.B.EMODE = 1; - FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/ - FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */ - FMPLL.ESYNCR1.B.EPREDIV = SPC563_CLK_PREDIV; - FMPLL.ESYNCR1.B.EMFD = SPC563_CLK_MFD; - FMPLL.ESYNCR2.B.ERFD = SPC563_CLK_RFD; - while (!FMPLL.SYNSR.B.LOCK) - ; - FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */ -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/SPC56x/hal_lld.h deleted file mode 100644 index f0857cc..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/hal_lld.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file SPC56x/hal_lld.h - * @brief SPC563 HAL subsystem low level driver header. - * - * @addtogroup SPC563_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "mpc563m.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "SPC563M64" - -#define RFD_DIV2 0 /**< Divide VCO frequency by 2. */ -#define RFD_DIV4 1 /**< Divide VCO frequency by 4. */ -#define RFD_DIV8 2 /**< Divide VCO frequency by 8. */ -#define RFD_DIV16 3 /**< Divide VCO frequency by 16.*/ - -/* The following settings are related to the FLASH controller, performance - and stability depends on them, be careful.*/ -#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/ -#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */ -#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */ -#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */ -#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */ -#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */ -#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */ -#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */ -#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */ -#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */ -#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */ -#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */ -#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */ -#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */ -#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */ -#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */ -#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */ -#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */ -#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */ -#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */ -#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */ -#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */ -#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */ -#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */ -#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */ -#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */ -#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */ -#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */ -#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */ -#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */ -#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */ -#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */ -#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */ -#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */ -#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */ -#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */ -#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */ -#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Clock bypass. - * @note If set to @p TRUE then the PLL is not started and initialized, the - * external clock is used as-is and the other clock-related settings - * are ignored. - */ -#if !defined(SPC563_CLK_BYPASS) || defined(__DOXYGEN__) -#define SPC563_CLK_BYPASS FALSE -#endif - -/** - * @brief Disables the overclock checks. - */ -#if !defined(SPC563_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) -#define SPC563_ALLOW_OVERCLOCK FALSE -#endif - -/** - * @brief External clock pre-divider. - * @note Must be in range 0...14. - * @note The effective divider factor is this value plus one. - */ -#if !defined(SPC563_CLK_PREDIV) || defined(__DOXYGEN__) -#define SPC563_CLK_PREDIV 0 -#endif - -/** - * @brief Multiplication factor divider. - * @note Must be in range 32...96. - */ -#if !defined(SPC563_CLK_MFD) || defined(__DOXYGEN__) -#define SPC563_CLK_MFD 40 -#endif - -/** - * @brief Reduced frequency divider. - */ -#if !defined(SPC563_CLK_RFD) || defined(__DOXYGEN__) -#define SPC563_CLK_RFD RFD_DIV4 -#endif - -/** - * @brief Flash buffer and prefetching settings. - * @note Please refer to the SPC563M64 reference manual about the meaning - * of the following bits, if in doubt DO NOT MODIFY IT. - * @note Do not specify the APC, WWSC, RWSC bits in this value because - * those are calculated from the system clock and ORed with this - * value. - */ -#if !defined(SPC563_FLASH_BIUCR) || defined(__DOXYGEN__) -#define SPC563_FLASH_BIUCR (BIUCR_BANK1_TOO | \ - BIUCR_MASTER4_PREFETCH | \ - BIUCR_MASTER0_PREFETCH | \ - BIUCR_DPFEN | \ - BIUCR_IPFEN | \ - BIUCR_PFLIM_ON_MISS | \ - BIUCR_BFEN) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (SPC563_CLK_PREDIV < 0) || (SPC563_CLK_PREDIV > 14) -#error "invalid SPC563_CLK_PREDIV value specified" -#endif - -#if (SPC563_CLK_MFD < 32) || (SPC563_CLK_MFD > 96) -#error "invalid SPC563_CLK_MFD value specified" -#endif - -#if (SPC563_CLK_RFD != RFD_DIV2) && (SPC563_CLK_RFD != RFD_DIV4) && \ - (SPC563_CLK_RFD != RFD_DIV8) && (SPC563_CLK_RFD != RFD_DIV16) -#error "invalid SPC563_CLK_RFD value specified" -#endif - -/** - * @brief PLL output clock. - */ -#define SPC563_PLLCLK ((EXTCLK / (SPC563_CLK_PREDIV + 1)) * SPC563_CLK_MFD) - -#if (SPC563_PLLCLK < 256000000) || (SPC563_PLLCLK > 512000000) -#error "VCO frequency out of the acceptable range (256...512)" -#endif - -/** - * @brief PLL output clock. - */ -#if !SPC563_CLK_BYPASS || defined(__DOXYGEN__) -#define SPC563_SYSCLK (SPC563_PLLCLK / (1 << (SPC563_CLK_RFD + 1))) -#else -#define SPC563_SYSCLK EXTCLK -#endif - -#if (SPC563_SYSCLK > 80000000) && !SPC563_ALLOW_OVERCLOCK -#error "System clock above maximum rated frequency (80MHz)" -#endif - -/** - * @brief Flash wait states are a function of the system clock. - */ -#if (SPC563_SYSCLK <= 30000000) || defined(__DOXYGEN__) -#define SPC563_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1) -#elif SPC563_SYSCLK <= 60000000 -#define SPC563_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1) -#else -#define SPC563_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1) -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void spc563_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/mpc563m.h b/ChibiOS_2.0.8/os/hal/platforms/SPC56x/mpc563m.h deleted file mode 100644 index e319138..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/mpc563m.h +++ /dev/null @@ -1,4123 +0,0 @@ -/**************************************************************************/ - -/* FILE NAME: mpc563xm.h COPYRIGHT (c) Freescale 2008,2009 */ -/* VERSION: 2.0 All Rights Reserved */ -/* */ -/* DESCRIPTION: */ -/* This file contain all of the register and bit field definitions for */ -/* MPC563xM. This version supports revision 1.0 and later. */ -/*========================================================================*/ -/* UPDATE HISTORY */ -/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ -/* --- ----------- --------- --------------------- */ -/* 1.0 G. Emerson 31/OCT/07 Initial version. */ -/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */ -/* Added ESYNCR1 ESYNCR2 SYNFMMR */ -/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */ -/* 8 channels in the middle of the range */ -/* do not exist */ -/* 1.3 G. Emerson 30/JUL/08 FLEXCAN - Supports FIFO and Buffer. */ -/* RXIMR added */ -/* FMPLL - Added FMPLL.SYNFMMR.B.BSY */ -/* SIU - Added SIU.ISEL0-3 */ -/* EMIOS - Added EMIOS.CH[x].ALTCADR.R */ -/* MCM - Replaced ECSM with MCM */ -/* removing SWT registers as defined at */ -/* seperate memory location. PFLASH */ -/* registers pre-fixed with P*. Added PCT,*/ -/* PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/ -/* PBRIDGE - Removed as no PBRIDGE */ -/* registers. */ -/* INTC - Updated number of PSR from */ -/* 358 to 360. */ -/* mpc5500_spr.h - Added RI to MSR and NMI*/ -/* to MSCR. */ -/* 1.4 G. Emerson 30/SEP/08 Add SIU.MIDR2 */ -/* Changes to SIU.MIDR as per RM. */ -/* 1.5 May 2009 Changes to match documentation, removed*/ -/* Not released */ -/* 1.6 K. Odenthal 03/June/09 Update for 1.5M version of the MPC563xM*/ -/* & R. Dees */ -/* INTC - All Processor 0 regs matched to previous */ -/* version */ -/* INTC - BCR renamed to MCR to match previous */ -/* version */ -/* INTC - VTES_PRC1 and HVEN_PRC1 added to MCR */ -/* INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1 */ -/* registers added */ -/* INTC - 512 PSR registers instead of 364 */ -/* ECSM - (Internal - mcm -> ecsm in the source files*/ -/* for generating the header file */ -/* ECSM - All bits and regs got an additional "p" in */ -/* the name in the user manual for "Platform" */ -/* -> deleted to match */ -/* ECSM - SWTCR, SWTSR and SWTIR don't exist in */ -/* MPC563xM -> deleted */ -/* ECSM - PROTECTION in the URM is one bitfield, */ -/* in mop5534 this are four: PROT1-4 -> */ -/* changed to match */ -/* EMCM - removed undocumented registers */ -/* ECSM - RAM ECC Syndrome is new in MPC563xM -> added */ -/* XBAR - removed AMPR and ASGPCR registers */ -/* XBAR - removed HPE bits for nonexistant masters */ -/* EBI - added: D16_31, AD_MUX and SETA bits */ -/* EBI - Added reserved register at address 0x4. */ -/* EBI - Corrected number of chip selects in for both*/ -/* the EBI_CS and the CAL_EBI_CS */ -/* SIU - corrected number of GPDO registers and */ -/* allowed for maximum PCR registers. */ -/* SWT - add KEY bit to CR, correct WND (from WNO) */ -/* SWT - add SK register */ -/* PMC - moved bits from CFGR to Status Register (SR)*/ -/* PMC - Added SR */ -/* DECFIL - Added new bits DSEL, IBIE, OBIE, EDME, */ -/* TORE, & TRFE to MCR. Added IBIC, OBIC, */ -/* DIVRC, IBIF, OBIF, DIVR to MSR. */ -/* changed OUTTEG to OUTTAG in OB */ -/* Change COEF to TAG in TAG register */ -/* EQADC - removed REDLCCR - not supported */ -/* FLASH - Aligned register and bit names with legacy*/ -/* 1.7 K. Odenthal 10/November/09 */ -/* SIU - changed PCR[n].PA from 3 bit to 4 bit */ -/* eTPU - changed WDTR_A.WDM from 1 bit to 2 bits */ -/* DECFIL - changed COEF.R and TAP.R from 16 bit to */ -/* 32 bit */ -/* 2.0 K. Odenthal 12/February/2010 */ -/* TSENS - Temperature Sensor Module added to */ -/* header file */ -/* ANSI C Compliance - Register structures have a */ -/* Bitfield Tag ('B') tag only if there is */ -/* at least one Bitfiels defined. Empty */ -/* tags like 'vuint32_t:32;' are not */ -/* allowed. */ -/* DECFIL - removed MXCR register. This register is */ -/* not supported on this part */ -/* SIU - SWT_SEL bit added in SIU DIRER register */ -/* EDMA - removed HRSL, HRSH and GPOR registers. */ -/* Those registers are not supported in */ -/* that part. */ -/* ESCI - removed LDBG and DSF bits from LCR */ -/* registers. Those bits are not supported */ -/* in that part. */ -/* Those registers are not supported in */ -/* that part. */ -/**************************************************************************/ -/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ - -#ifndef _MPC563M_H_ -#define _MPC563M_H_ - -#include "typedefs.h" - -#ifdef __cplusplus -extern "C" { - -#endif /* - */ - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif /* - */ - -/****************************************************************************/ -/* MODULE : FMPLL */ -/****************************************************************************/ - struct FMPLL_tag { - union { - vuint32_t R; - struct { - vuint32_t:1; - vuint32_t PREDIV:3; - vuint32_t MFD:5; - vuint32_t:1; - vuint32_t RFD:3; - vuint32_t LOCEN:1; - vuint32_t LOLRE:1; - vuint32_t LOCRE:1; - vuint32_t:1; /* Reserved in MPC563xM - - Deleted for legacy header version [mpc5534.h]: - - */ - vuint32_t LOLIRQ:1; - vuint32_t LOCIRQ:1; - vuint32_t:13; /* Reserved in MPC563xM - - Deleted for legacy header version [mpc5534.h]: - - - - - - */ - } B; - } SYNCR; - union { - vuint32_t R; - struct { - vuint32_t:22; - vuint32_t LOLF:1; - vuint32_t LOC:1; - vuint32_t MODE:1; - vuint32_t PLLSEL:1; - vuint32_t PLLREF:1; - vuint32_t LOCKS:1; - vuint32_t LOCK:1; - vuint32_t LOCF:1; - vuint32_t:2; /* Reserved in MPC563xM - - Deleted for legacy header version [mpc5534.h]: - - - - */ - } B; - } SYNSR; - union { - vuint32_t R; - struct { - vuint32_t EMODE:1; - vuint32_t CLKCFG:3; - vuint32_t:8; - vuint32_t EPREDIV:4; - vuint32_t:9; - vuint32_t EMFD:7; - } B; - } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */ - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t LOCEN:1; - vuint32_t LOLRE:1; - vuint32_t LOCRE:1; - vuint32_t LOLIRQ:1; - vuint32_t LOCIRQ:1; - vuint32_t:17; - vuint32_t ERFD:2; - } B; - } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */ - int32_t FMPLL_reserved0[2]; - union { - vuint32_t R; - struct { - vuint32_t BSY:1; - vuint32_t MODEN:1; - vuint32_t MODSEL:1; - vuint32_t MODPERIOD:13; - vuint32_t:1; - vuint32_t INCSTEP:15; - } B; - } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */ - }; -/****************************************************************************/ -/* MODULE : EBI */ -/****************************************************************************/ - struct CS_tag { - union { - vuint32_t R; - struct { - vuint32_t BA:17; /* */ - vuint32_t:3; /* */ - vuint32_t PS:1; /* */ - vuint32_t:3; /* */ - vuint32_t AD_MUX:1; /* new in MPC563xM */ - vuint32_t BL:1; /* */ - vuint32_t WEBS:1; /* */ - vuint32_t TBDIP:1; /* */ - vuint32_t:1; /* */ - vuint32_t SETA:1; /* new in MPC563xM */ - vuint32_t BI:1; /* */ - vuint32_t V:1; /* */ - } B; - } BR; /* EBI_BR */ - union { - vuint32_t R; - struct { - vuint32_t AM:17; /* */ - vuint32_t:7; /* */ - vuint32_t SCY:4; /* */ - vuint32_t:1; /* */ - vuint32_t BSCY:2; /* */ - vuint32_t:1; /* */ - } B; - } OR; /* EBI_OR */ - }; - struct CAL_CS_tag { - union { - vuint32_t R; - struct { - vuint32_t BA:17; /* */ - vuint32_t:3; /* */ - vuint32_t PS:1; /* */ - vuint32_t:3; /* */ - vuint32_t AD_MUX:1; /* new in MPC563xM */ - vuint32_t BL:1; /* */ - vuint32_t WEBS:1; /* */ - vuint32_t TBDIP:1; /* */ - vuint32_t:1; /* */ - vuint32_t SETA:1; /* new in MPC563xM */ - vuint32_t BI:1; /* */ - vuint32_t V:1; /* */ - } B; - } BR; /* EBI_CAL_BR */ - - union { - vuint32_t R; - struct { - vuint32_t AM:17; /* */ - vuint32_t:7; /* */ - vuint32_t SCY:4; /* */ - vuint32_t:1; /* */ - vuint32_t BSCY:2; /* */ - vuint32_t:1; /* */ - } B; - } OR; /* EBI_CAL_OR */ - - }; - - struct EBI_tag { - union { - vuint32_t R; - struct { - vuint32_t:5; /* */ - vuint32_t SIZEEN:1; /* SIZEN */ - vuint32_t SIZE:2; /* */ - vuint32_t:8; /* */ - vuint32_t ACGE:1; /* */ - vuint32_t EXTM:1; /* */ - vuint32_t EARB:1; /* */ - vuint32_t EARP:2; /* */ - vuint32_t:4; /* */ - vuint32_t MDIS:1; /* */ - vuint32_t:3; /* */ - vuint32_t D16_31:1; /* new in MPC563xM */ - vuint32_t AD_MUX:1; /* new in MPC563xM */ - vuint32_t DBM:1; /* */ - } B; - } MCR; /* EBI Module Configuration Register (MCR) EBI_MCR @baseaddress + 0x00 */ - - uint32_t EBI_reserved1[1]; - - union { - vuint32_t R; - struct { - vuint32_t:30; /* */ - vuint32_t TEAF:1; /* */ - vuint32_t BMTF:1; /* */ - } B; - } TESR; /* EBI Transfer Error Status Register (TESR) EBI_TESR @baseaddress + 0x08 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; /* */ - vuint32_t BMT:8; /* */ - vuint32_t BME:1; /* */ - vuint32_t:7; /* */ - } B; - } BMCR; /* EBI_BMCR @baseaddress + 0x0C */ - - struct CS_tag CS[4]; - - uint32_t EBI_reserved2[4]; - - /* Calibration registers */ - struct CAL_CS_tag CAL_CS[4]; - - }; /* end of EBI_tag */ -/****************************************************************************/ -/* MODULE : FLASH */ -/****************************************************************************/ -/* 3 flash modules implemented. */ -/* HBL and HBS not used in Bank 0 / Array 0 */ -/* LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in */ -/* Bank 1 / Array 1 or Bank 1 / Array 3 */ -/****************************************************************************/ - struct FLASH_tag { - union { /* Module Configuration Register (MCR)@baseaddress + 0x00 */ - vuint32_t R; - struct { - vuint32_t EDC:1; /* ECC Data Correction (Read/Clear) */ - vuint32_t:4; /* Reserved */ - vuint32_t SIZE:3; /* Array Size (Read Only) */ - vuint32_t:1; /* Reserved */ - vuint32_t LAS:3; /* Low Address Space (Read Only) */ - vuint32_t:3; /* Reserved */ - vuint32_t MAS:1; /* Mid Address Space (Read Only) */ - vuint32_t EER:1; /* ECC Event Error (Read/Clear) *//* BBEPE and EPE */ - vuint32_t RWE:1; /* Read While Write Event Error (Read/Clear) */ - vuint32_t:2; /* Reserved */ - vuint32_t PEAS:1; /* Program/Erase Access Space (Read Only) */ - vuint32_t DONE:1; /* Status (Read Only) */ - vuint32_t PEG:1; /* Program/Erase Good (Read Only) */ - vuint32_t:4; /* Reserved *//* RSD PEG STOP RSVD */ - vuint32_t PGM:1; /* Program (Read/Write) */ - vuint32_t PSUS:1; /* Program Suspend (Read/Write) */ - vuint32_t ERS:1; /* Erase (Read/Write) */ - vuint32_t ESUS:1; /* Erase Suspend (Read/Write) */ - vuint32_t EHV:1; /* Enable High Voltage (Read/Write) */ - } B; - } MCR; - - union { /* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */ - vuint32_t R; - struct { - vuint32_t LME:1; /* Low/Mid address space block enable (Read Only) */ - vuint32_t:10; /* Reserved */ - vuint32_t SLOCK:1; /*SLK *//* Shadow address space block lock (Read/Write) */ - vuint32_t:2; /* Reserved */ - vuint32_t MLOCK:2; /*MLK *//* Mid address space block lock (Read/Write) */ - vuint32_t:8; /* Reserved */ - vuint32_t LLOCK:8; /*LLK *//* Low address space block lock (Read/Write) */ - } B; - } LMLR; /*LML */ - - union { /* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */ - vuint32_t R; - struct { - vuint32_t HBE:1; /* High address space Block Enable (Read Only) */ - vuint32_t:27; /* Reserved */ - vuint32_t HBLOCK:4; /* High address space block lock (Read/Write) */ - } B; - } HLR; /*HBL */ - - union { /* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */ - vuint32_t R; - struct { - vuint32_t SLE:1; /* Secondary low/mid address space block enable (Read Only) */ - vuint32_t:10; /* Reserved */ - vuint32_t SSLOCK:1; /*SSLK *//* Secondary shadow address space block lock (Read/Write) */ - vuint32_t:2; /* Reserved */ - vuint32_t SMLOCK:2; /*SMK *//* Secondary mid address space block lock (Read/Write) */ - vuint32_t:8; /* Reserved */ - vuint32_t SLLOCK:8; /*SLK *//* Secondary low address space block lock (Read/Write) */ - } B; - } SLMLR; /*SLL */ - - union { /* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */ - vuint32_t R; - struct { - vuint32_t:14; /* Reserved */ - vuint32_t MSEL:2; /*MSL *//* Mid address space block select (Read/Write) */ - vuint32_t:8; /* Reserved */ - vuint32_t LSEL:8; /*LSL *//* Low address space block select (Read/Write) */ - } B; - } LMSR; /*LMS */ - - union { /* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */ - vuint32_t R; - struct { - vuint32_t:28; /* Reserved */ - vuint32_t HBSEL:4; /*HSL *//* High address space block select (Read/Write) */ - } B; - } HSR; /*HBS */ - - union { /* Address Register (ADR)@baseaddress + 0x18 */ - vuint32_t R; - struct { - vuint32_t SAD:1; /* Shadow address (Read Only) */ - vuint32_t:10; /* Reserved */ - vuint32_t ADDR:18; /*AD *//* Address 20-3 (Read Only) */ - vuint32_t:3; /* Reserved */ - } B; - } AR; /*ADR */ - - union { /* @baseaddress + 0x1C */ - vuint32_t R; - struct { - vuint32_t:7; /* Reserved */ - vuint32_t GCE:1; /* Global Configuration Enable (Read/Write) */ - vuint32_t:4; /* Reserved */ - vuint32_t M3PFE:1; /* Master 3 Prefetch Enable (Read/Write) */ - vuint32_t M2PFE:1; /* Master 2 Prefetch Enable (Read/Write) */ - vuint32_t M1PFE:1; /* Master 1 Prefetch Enable (Read/Write) */ - vuint32_t M0PFE:1; /* Master 0 Prefetch Enable (Read/Write) */ - vuint32_t APC:3; /* Address Pipelining Control (Read/Write) */ - vuint32_t WWSC:2; /* Write Wait State Control (Read/Write) */ - vuint32_t RWSC:3; /* Read Wait State Control (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t DPFEN:1; /*DPFE *//* Data Prefetch Enable (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t IPFEN:1; /*IPFE *//* Instruction Prefetch Enable (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t PFLIM:2; /* Prefetch Limit (Read/Write) */ - vuint32_t BFEN:1; /*BFE *//* Buffer Enable (Read/Write) */ - } B; - } BIUCR; /*PFCR1 */ - - union { /* @baseaddress + 0x20 */ - vuint32_t R; - struct { - vuint32_t:24; /* Reserved */ - vuint32_t M3AP:2; /* Master 3 Access Protection (Read/Write) */ - vuint32_t M2AP:2; /* Master 2 Access Protection (Read/Write) */ - vuint32_t M1AP:2; /* Master 1 Access Protection (Read/Write) */ - vuint32_t M0AP:2; /* Master 0 Access Protection (Read/Write) */ - } B; - } BIUAPR; /*PFAPR */ - - union { /* @baseaddress + 0x24 */ - vuint32_t R; - struct { - vuint32_t LBCFG:2; /* Line Buffer Configuration (Read/Write) */ - vuint32_t:30; /* Reserved */ - } B; - } BIUCR2; - - union { /* @baseaddress + 0x28 */ - vuint32_t R; - struct { - vuint32_t:25; /* Reserved */ - vuint32_t B1_DPFE:1; /* Bank1 Data Prefetch Enable (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t B1_IPFE:1; /* Bank1 Instruction Prefetch Enable (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t B1_PFLIM:2; /* Bank1 Prefetch Limit (Read/Write) */ - vuint32_t B1_BFE:1; /* Bank1 Buffer Enable (Read/Write) */ - } B; - } PFCR3; - - int32_t FLASH_reserverd_89[4]; - - union { /* User Test 0 (UT0) register@baseaddress + 0x3c */ - vuint32_t R; - struct { - vuint32_t UTE:1; /* User test enable (Read/Clear) */ - vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */ - vuint32_t:6; /* Reserved */ - vuint32_t DSI:8; /* Data syndrome input (Read/Write) */ - vuint32_t:9; /* Reserved */ - vuint32_t:1; /* Reserved (Read/Write) */ - vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */ - vuint32_t MRV:1; /* Margin Read Value (Read/Write) */ - vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */ - vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */ - vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */ - vuint32_t AID:1; /* Array Integrity Done (Read Only) */ - } B; - } UT0; - - union { /* User Test 1 (UT1) register@baseaddress + 0x40 */ - vuint32_t R; - struct { - vuint32_t DAI:32; /* Data Array Input (Read/Write) */ - } B; - } UT1; - - union { /* User Test 2 (UT2) register@baseaddress + 0x44 */ - vuint32_t R; - struct { - vuint32_t DAI:32; /* Data Array Input (Read/Write) */ - } B; - } UT2; - - union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */ - vuint32_t R; - struct { - vuint32_t MS:32; /* Multiple input Signature (Read/Write) */ - } B; - } UMISR[5]; - - }; /* end of FLASH_tag */ -/****************************************************************************/ -/* MODULE : SIU */ -/****************************************************************************/ - struct SIU_tag { - union { - vuint32_t R; - struct { - vuint32_t S_F:1; /* Identifies the Manufacturer S/F */ - vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) Flash Size 1 */ - vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity (see Table 15-5 for details) Flash Size 1 */ - vuint32_t TEMP_RANGE:2; /* Define maximum operating range Temp Range */ - vuint32_t:1; /* Reserved for future enhancements */ - vuint32_t MAX_FREQ:2; /* Define maximum device speed Max Freq */ - vuint32_t:1; /* Reserved for future enhancements */ - vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V Supply */ - vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product Part Number */ - vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */ - vuint32_t:2; /* Reserved for future enhancements */ - vuint32_t EE:1; /* Indicates if Data Flash is present */ - vuint32_t:3; /* Reserved for future enhancements */ - vuint32_t FR:1; /* Indicates if Data FlexRay is present */ - } B; - } MIDR2; /* MCU ID Register 2 SIU_MIDR2 @baseaddress + 0x4 */ - - union { - vuint32_t R; - struct { - vuint32_t PARTNUM:16; /* Device part number: 0x5633 */ - vuint32_t CSP:1; /* CSP configuration (new in MPC563xM) */ - vuint32_t PKG:5; /* Indicate the package the die is mounted in. (new in MPC563xM) */ - vuint32_t:2; /* Reserved */ - vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */ - } B; - } MIDR; /* MCU ID Register (MIDR) SIU_MIDR @baseaddress + 0x8 */ - - union { - vuint32_t R; - } TST; /* SIU Test Register (SIU_TST) SIU_TST @baseaddress + 0xC */ - - union { - vuint32_t R; - struct { - vuint32_t PORS:1; /* Power-On Reset Status */ - vuint32_t ERS:1; /* External Reset Status */ - vuint32_t LLRS:1; /* Loss of Lock Reset Status */ - vuint32_t LCRS:1; /* Loss of Clock Reset Status */ - vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */ - vuint32_t CRS:1; /* Checkstop Reset Status */ - vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status (new in MPC563xM) */ - vuint32_t:7; /* */ - vuint32_t SSRS:1; /* Software System Reset Status */ - vuint32_t SERF:1; /* Software External Reset Flag */ - vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */ - vuint32_t:11; /* */ - vuint32_t ABR:1; /* Auto Baud Rate (new in MPC563xM) */ - vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */ - vuint32_t RGF:1; /* RESET Glitch Flag */ - } B; - } RSR; /* Reset Status Register (SIU_RSR) SIU_RSR @baseaddress + 0x10 */ - - union { - vuint32_t R; - struct { - vuint32_t SSR:1; /* Software System Reset */ - vuint32_t SER:1; /* Software External Reset */ - vuint32_t:14; /* */ - vuint32_t CRE:1; /* Checkstop Reset Enable */ - vuint32_t:15; /* */ - } B; - } SRCR; /* System Reset Control Register (SRCR) SIU_SRCR @baseaddress + 0x14 */ - - union { - vuint32_t R; - struct { - vuint32_t NMI:1; /* Non-Maskable Interrupt Flag (new in MPC563xM) */ - vuint32_t:7; /* */ - vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */ - vuint32_t:7; /* */ - vuint32_t EIF15:1; /* External Interrupt Request Flag x */ - vuint32_t EIF14:1; /* External Interrupt Request Flag x */ - vuint32_t EIF13:1; /* External Interrupt Request Flag x */ - vuint32_t EIF12:1; /* External Interrupt Request Flag x */ - vuint32_t EIF11:1; /* External Interrupt Request Flag x */ - vuint32_t EIF10:1; /* External Interrupt Request Flag x */ - vuint32_t EIF9:1; /* External Interrupt Request Flag x */ - vuint32_t EIF8:1; /* External Interrupt Request Flag x */ - vuint32_t:3; /* (reserved in MPC563xM) */ - vuint32_t EIF4:1; /* External Interrupt Request Flag x */ - vuint32_t EIF3:1; /* External Interrupt Request Flag x */ - vuint32_t:2; /* (reserved in MPC563xM) */ - vuint32_t EIF0:1; /* External Interrupt Request Flag x */ - } B; - } EISR; /* SIU External Interrupt Status Register (EISR) SIU_EISR @baseaddress + 0x18 */ - - union { - vuint32_t R; - struct { - vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection (new in MPC563xM) */ - vuint32_t:7; /* */ - vuint32_t SWT_SEL:1; - vuint32_t:7; - vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */ - } B; - } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) SIU_DIRER @baseaddress + 0x1C */ - - union { - vuint32_t R; - struct { - vuint32_t:28; /* */ - vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */ - } B; - } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) SIU_DIRSR @baseaddress + 0x20 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; /* */ - vuint32_t OVF15:1; /* Overrun Flag x */ - vuint32_t OVF14:1; /* Overrun Flag x */ - vuint32_t OVF13:1; /* Overrun Flag x */ - vuint32_t OVF12:1; /* Overrun Flag x */ - vuint32_t OVF11:1; /* Overrun Flag x */ - vuint32_t OVF10:1; /* Overrun Flag x */ - vuint32_t OVF9:1; /* Overrun Flag x */ - vuint32_t OVF8:1; /* Overrun Flag x */ - vuint32_t:3; /* reserved in MPC563xM */ - vuint32_t OVF4:1; /* Overrun Flag x */ - vuint32_t OVF3:1; /* Overrun Flag x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t OVF0:1; /* Overrun Flag x */ - } B; - } OSR; /* Overrun Status Register (OSR) SIU_OSR @baseaddress + 0x24 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; /* */ - vuint32_t ORE15:1; /* Overrun Request Enable x */ - vuint32_t ORE14:1; /* Overrun Request Enable x */ - vuint32_t ORE13:1; /* Overrun Request Enable x */ - vuint32_t ORE12:1; /* Overrun Request Enable x */ - vuint32_t ORE11:1; /* Overrun Request Enable x */ - vuint32_t ORE10:1; /* Overrun Request Enable x */ - vuint32_t ORE9:1; /* Overrun Request Enable x */ - vuint32_t ORE8:1; /* Overrun Request Enable x */ - vuint32_t:3; /* reserved in MPC563xM */ - vuint32_t ORE4:1; /* Overrun Request Enable x */ - vuint32_t ORE3:1; /* Overrun Request Enable x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t ORE0:1; /* Overrun Request Enable x */ - } B; - } ORER; /* Overrun Request Enable Register (ORER) SIU_ORER @baseaddress + 0x28 */ - - union { - vuint32_t R; - struct { - vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x (new in MPC563xM) */ - vuint32_t:15; /* reserved in MPC563xM */ - vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t:3; /* reserved in MPC563xM */ - vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */ - } B; - } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) SIU_IREER @baseaddress + 0x2C */ - - union { - vuint32_t R; - struct { - vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable x (new in MPC563xM) */ - vuint32_t Reserverd:15; /* */ - vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t:3; /* reserved in MPC563xM */ - vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */ - } B; - } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) SIU_IFEER @baseaddress + 0x30 */ - - union { - vuint32_t R; - struct { - vuint32_t:28; /* */ - vuint32_t DFL:4; /* Digital Filter Length */ - } B; - } IDFR; /* External IRQ Digital Filter Register (IDFR) SIU_IDFR @baseaddress + 0x40 */ - - int32_t SIU_reserverd_153[3]; - - union { - vuint16_t R; - struct { - vuint16_t:2; /* */ - vuint16_t PA:4; /* */ - vuint16_t OBE:1; /* */ - vuint16_t IBE:1; /* */ - vuint16_t DSC:2; /* */ - vuint16_t ODE:1; /* */ - vuint16_t HYS:1; /* */ - vuint16_t SRC:2; /* */ - vuint16_t WPE:1; /* */ - vuint16_t WPS:1; /* */ - } B; - } PCR[512]; /* Pad Configuration Register (PCR) SIU_PCR @baseaddress + 0x600 */ - - int32_t SIU_reserverd_164[112]; - - union { - vuint8_t R; - struct { - vuint8_t:7; /* */ - vuint8_t PDO:1; /* */ - } B; - } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) SIU_GDPO @baseaddress + 0x800 */ - - union { - vuint8_t R; - struct { - vuint8_t:7; /* */ - vuint8_t PDI:1; /* */ - } B; - } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) SIU_GDPI @baseaddress + 0x900 */ - - union { - vuint32_t R; - struct { - vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */ - vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */ - vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */ - vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */ - vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */ - vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */ - vuint32_t:20; /* */ - } B; - } ETISR; /* eQADC Trigger Input Select Register (ETISR) SIU_ETISR @baseaddress + 0x904 */ - - union { - vuint32_t R; - struct { - vuint32_t ESEL15:2; /* External IRQ Input Select x */ - vuint32_t ESEL14:2; /* External IRQ Input Select x */ - vuint32_t ESEL13:2; /* External IRQ Input Select x */ - vuint32_t ESEL12:2; /* External IRQ Input Select x */ - vuint32_t ESEL11:2; /* External IRQ Input Select x */ - vuint32_t ESEL10:2; /* External IRQ Input Select x */ - vuint32_t ESEL9:2; /* External IRQ Input Select x */ - vuint32_t ESEL8:2; /* External IRQ Input Select x */ - vuint32_t ESEL7:2; /* External IRQ Input Select x */ - vuint32_t ESEL6:2; /* External IRQ Input Select x */ - vuint32_t ESEL5:2; /* External IRQ Input Select x */ - vuint32_t ESEL4:2; /* External IRQ Input Select x */ - vuint32_t ESEL3:2; /* External IRQ Input Select x */ - vuint32_t ESEL2:2; /* External IRQ Input Select x */ - vuint32_t ESEL1:2; /* External IRQ Input Select x */ - vuint32_t ESEL0:2; /* External IRQ Input Select x */ - } B; - } EIISR; /* External IRQ Input Select Register (EIISR) SIU_EIISR @baseaddress + 0x908 */ - - union { - vuint32_t R; - struct { - vuint32_t:8; /* reserved in MPC563xM */ - vuint32_t SINSELB:2; /* DSPI_B Data Input Select SIN-SELB */ - vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select SS-SELB */ - vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select SCK-SELB */ - vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select TRIG-SELB */ - vuint32_t SINSELC:2; /* DSPI_C Data Input Select SIN-SELC */ - vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select SSSELC */ - vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select SCK-SELC */ - vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select TRIG-SELC */ - vuint32_t:8; /* reserved in MPC563xM */ - } B; - } DISR; /* DSPI Input Select Register (DISR) SIU_DISR @baseaddress + 0x90c */ - - union { - vuint32_t R; - struct { - vuint32_t:2; /* */ - vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection eTSEL5 */ - vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection eTSEL4 */ - vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection eTSEL3 */ - vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection eTSEL2 */ - vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection eTSEL1 */ - vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection eTSEL0 */ - } B; - } ISEL3; /* MUX Select Register 3 (ISEL3) (new in MPC563xM) SIU_ISEL3 @baseaddress + 0x920 */ - - int32_t SIU_reserverd_214[4]; - - union { - vuint32_t R; - struct { - vuint32_t:11; /* */ - vuint32_t ESEL5:1; /* eSEL5 */ - vuint32_t:3; /* */ - vuint32_t ESEL4:1; /* eSEL4 */ - vuint32_t:3; /* */ - vuint32_t ESEL3:1; /* eSEL3 */ - vuint32_t:3; /* */ - vuint32_t ESEL2:1; /* eSEL2 */ - vuint32_t:3; /* */ - vuint32_t ESEL1:1; /* eSEL1 */ - vuint32_t:3; /* */ - vuint32_t ESEL0:1; /* eSEL0 */ - } B; - } ISEL8; /* MUX Select Register 8 (ISEL8) (new in MPC563xM) SIU_ISEL8 @baseaddress + 0x924 */ - - union { - vuint32_t R; - struct { - vuint32_t:27; /* */ - vuint32_t ETSEL0A:5; /* eTSEL0A */ - } B; - } ISEL9; /* MUX Select Register 9(ISEL9) SIU_ISEL9 @baseaddress + 0x980 */ - - int32_t SIU_reserverd_230[22]; - - union { - vuint32_t R; - struct { - vuint32_t:14; /* */ - vuint32_t MATCH:1; /* Compare Register Match */ - vuint32_t DISNEX:1; /* Disable Nexus */ - vuint32_t:14; /* */ - vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable (new in MPC563xM) */ - vuint32_t:1; /* */ - } B; - } CCR; /* Chip Configuration Register (CCR) SIU_CCR @baseaddress + 0x984 */ - - union { - vuint32_t R; - struct { - vuint32_t:28; /* The ENGDIV bit is reserved in MPC563xM */ - vuint32_t EBTS:1; /* External Bus Tap Select */ - vuint32_t:1; /* */ - vuint32_t EBDF:2; /* External Bus Division Factor */ - } B; - } ECCR; /* External Clock Control Register (ECCR) SIU_ECCR @baseaddress + 0x988 */ - - union { - vuint32_t R; - } CARH; /* Compare A High Register (CARH) SIU_CMPAH @baseaddress + 0x98C */ - - union { - vuint32_t R; - } CARL; /* Compare A Low Register (CARL) SIU_CMPAL @baseaddress + 0x990 */ - - union { - vuint32_t R; - } CBRH; /* Compare B High Register (CBRH) SIU_CMPBH @baseaddress + 0x994 */ - - union { - vuint32_t R; - } CBRL; /* Compare B Low Register (CBRL) SIU_CMPBL @baseaddress + 0x9A0 */ - - int32_t SIU_reserverd_250[2]; - - union { - vuint32_t R; - struct { - vuint32_t:27; /* Reserved */ - vuint32_t BYPASS:1; /* Bypass bit BY-PASS */ - vuint32_t SYSCLKDIV:2; /* System Clock Divide SYS-CLKDIV */ - vuint32_t:2; /* Reserved */ - } B; - } SYSDIV; /* System Clock Register (SYSDIV) (new in MPC563xM) SIU_SYSDIV @baseaddress + 0x9A4 */ - - union { - vuint32_t R; - struct { - vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */ - vuint32_t:2; /* Reserved */ - vuint32_t SWTSTP:1; /* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */ - vuint32_t:1; /* Reserved */ - vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */ - vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */ - vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */ - vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */ - vuint32_t:1; /* Reserved */ - vuint32_t MIOSSTP:1; /* Stop mode request */ - vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */ - vuint32_t:1; /* Reserved */ - vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */ - vuint32_t:3; /* Reserved */ - vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */ - vuint32_t:1; /* Reserved */ - vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */ - vuint32_t:1; /* Reserved */ - vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */ - vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */ - vuint32_t:7; /* Reserved */ - vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */ - vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */ - } B; - } HLT; /* Halt Register (HLT) (new in MPC563xM) SIU_HLT @baseaddress + 0x9A8 */ - - union { - vuint32_t R; - struct { - vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:2; /* Reserved */ - vuint32_t SWTACK:1; /* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:1; /* Reserved */ - vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:1; /* Reserved */ - vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */ - vuint32_t:1; /* Reserved */ - vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:3; /* Reserved */ - vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */ - vuint32_t:1; /* Reserved */ - vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */ - vuint32_t:1; /* Reserved */ - vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:7; /* Reserved */ - vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */ - vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */ - } B; - } HLTACK; /* Halt Acknowledge Register (HLTACK) (new in MPC563xM) SIU_HLTACK @baseaddress + 0x9ac */ - - int32_t SIU_reserved3[21]; - - }; /* end of SIU_tag */ -/****************************************************************************/ -/* MODULE : EMIOS */ -/****************************************************************************/ - struct EMIOS_tag { - union { - vuint32_t R; - struct { - vuint32_t DOZEEN:1; /* new in MPC563xM */ - vuint32_t MDIS:1; - vuint32_t FRZ:1; - vuint32_t GTBE:1; - vuint32_t ETB:1; - vuint32_t GPREN:1; - vuint32_t:6; - vuint32_t SRV:4; - vuint32_t GPRE:8; - vuint32_t:8; - } B; - } MCR; /* Module Configuration Register EMIOSMCR */ - - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t F23:1; - vuint32_t F22:1; - vuint32_t F21:1; - vuint32_t F20:1; - vuint32_t F19:1; - vuint32_t F18:1; - vuint32_t F17:1; - vuint32_t F16:1; - vuint32_t F15:1; - vuint32_t F14:1; - vuint32_t F13:1; - vuint32_t F12:1; - vuint32_t F11:1; - vuint32_t F10:1; - vuint32_t F9:1; - vuint32_t F8:1; - vuint32_t F7:1; - vuint32_t F6:1; - vuint32_t F5:1; - vuint32_t F4:1; - vuint32_t F3:1; - vuint32_t F2:1; - vuint32_t F1:1; - vuint32_t F0:1; - } B; - } GFR; /* Global FLAG Register EMIOSGFLAG */ - - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t OU23:1; - vuint32_t OU22:1; - vuint32_t OU21:1; - vuint32_t OU20:1; - vuint32_t OU19:1; - vuint32_t OU18:1; - vuint32_t OU17:1; - vuint32_t OU16:1; - vuint32_t OU15:1; - vuint32_t OU14:1; - vuint32_t OU13:1; - vuint32_t OU12:1; - vuint32_t OU11:1; - vuint32_t OU10:1; - vuint32_t OU9:1; - vuint32_t OU8:1; - vuint32_t OU7:1; - vuint32_t OU6:1; - vuint32_t OU5:1; - vuint32_t OU4:1; - vuint32_t OU3:1; - vuint32_t OU2:1; - vuint32_t OU1:1; - vuint32_t OU0:1; - } B; - } OUDR; /* Output Update Disable Register EMIOSOUDIS */ - - union { - vuint32_t R; - struct { - vuint32_t:8; /* */ - vuint32_t CHDIS23:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS22:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS21:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS20:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS19:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS18:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS17:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS16:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS15:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS14:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS13:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS12:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS11:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS10:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS9:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS8:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS7:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS6:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS5:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS4:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS3:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS2:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS1:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS0:1; /* Enable Channel [n] bit */ - } B; - } UCDIS; /* Disable Channel (EMIOSUCDIS) EMIOSUCDIS (new in MPC563xM) @baseaddress + 0x0C */ - - int32_t EMIOS_reserverd_30[4]; - - struct { - union { - vuint32_t R; /* Channel A Data Register */ - } CADR; /* EMIOSA */ - - union { - vuint32_t R; /* Channel B Data Register */ - } CBDR; /* EMIOSB */ - - union { - vuint32_t R; /* Channel Counter Register */ - } CCNTR; /* EMIOSCNT */ - - union { - vuint32_t R; - struct { - vuint32_t FREN:1; - vuint32_t ODIS:1; - vuint32_t ODISSL:2; - vuint32_t UCPRE:2; - vuint32_t UCPREN:1; - vuint32_t DMA:1; - vuint32_t:1; - vuint32_t IF:4; - vuint32_t FCK:1; - vuint32_t FEN:1; - vuint32_t:3; - vuint32_t FORCMA:1; - vuint32_t FORCMB:1; - vuint32_t:1; - vuint32_t BSL:2; - vuint32_t EDSEL:1; - vuint32_t EDPOL:1; - vuint32_t MODE:7; - } B; - } CCR; /* Channel Control Register EMIOSC */ - - union { - vuint32_t R; - struct { - vuint32_t OVR:1; - vuint32_t:15; - vuint32_t OVFL:1; - vuint32_t:12; - vuint32_t UCIN:1; - vuint32_t UCOUT:1; - vuint32_t FLAG:1; - } B; - } CSR; /* Channel Status Register EMIOSS */ - - union { - vuint32_t R; /* Alternate Channel A Data Register */ - } ALTA; /* new in MPC563xM EMIOSALTA */ - - uint32_t emios_channel_reserved[2]; - - } CH[24]; - - }; /* end of EMIOS_tag */ -/****************************************************************************/ -/* MODULE : ETPU */ -/****************************************************************************/ - struct ETPU_tag { /* offset 0x0000 */ - union { /* eTPU module configuration register@baseaddress + 0x00 */ - vuint32_t R; - struct { - vuint32_t GEC:1; /* Global Exception Clear */ - vuint32_t SDMERR:1; /* */ - vuint32_t WDTOA:1; /* */ - vuint32_t WDTOB:1; /* */ - vuint32_t MGE1:1; /* MGEA */ - vuint32_t MGE2:1; /* MGEB */ - vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. ILFFA */ - vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. ILFFB */ - vuint32_t SCMERR:1; /* . */ - vuint32_t:2; /* */ - vuint32_t SCMSIZE:5; /* Shared Code Memory size */ - vuint32_t:4; /* */ - vuint32_t SCMMISC:1; /* SCM MISC Flag */ - vuint32_t SCMMISF:1; /* SCM MISC Flag */ - vuint32_t SCMMISEN:1; /* SCM MISC Enable */ - vuint32_t:2; /* */ - vuint32_t VIS:1; /* SCM Visability */ - vuint32_t:5; /* */ - vuint32_t GTBE:1; /* Global Time Base Enable */ - } B; - } MCR; /* ETPU_MCR */ - - /* offset 0x0004 */ - union { /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */ - vuint32_t R; - struct { - vuint32_t STS:1; /* Start Status bit */ - vuint32_t CTBASE:5; /* Channel Transfer Base */ - vuint32_t PBASE:10; /* Parameter Buffer Base Address PBBASE */ - vuint32_t PWIDTH:1; /* Parameter Width */ - vuint32_t PARAM0:7; /* Channel Parameter 0 PARM0 */ - vuint32_t WR:1; /* */ - vuint32_t PARAM1:7; /* Channel Parameter 1 PARM1 */ - } B; - } CDCR; /*ETPU_CDCR */ - - vuint32_t ETPU_reserved_0; - - /* offset 0x000C */ - union { /* eTPU MISC Compare Register@baseaddress + 0x0c */ - vuint32_t R; - struct { - vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. EMISCCMP */ - } B; - } MISCCMPR /*ETPU_MISCCMPR */ ; - - /* offset 0x0010 */ - union { /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */ - vuint32_t R; - struct { - vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */ - } B; - } SCMOFFDATAR; /*ETPU_SCMOFFDATAR */ - - /* offset 0x0014 */ - union { /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */ - vuint32_t R; - struct { - vuint32_t FEND:1; /* Force END */ - vuint32_t MDIS:1; /* Low power Stop */ - vuint32_t:1; /* */ - vuint32_t STF:1; /* Stop Flag */ - vuint32_t:4; /* */ - vuint32_t HLTF:1; /* Halt Mode Flag */ - vuint32_t:3; /* */ - vuint32_t FCSS:1; - vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - vuint32_t CDFC:2; /* */ - vuint32_t:1; /* */ - vuint32_t ERBA:5; /* */ - vuint32_t SPPDIS:1; /* */ - vuint32_t:2; /* */ - vuint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_A; /*ETPU_ECR */ - - vuint32_t ETPU_reserved_1[2]; - - /* offset 0x0020 */ - union { /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */ - vuint32_t R; - struct { - vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - vuint32_t AM:2; /* Angle Mode */ - vuint32_t:3; /* */ - vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ - vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - vuint32_t TCR1CS:1; /* */ - vuint32_t:5; /* */ - vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_A; /*ETPU_TBCR */ - - /* offset 0x0024 */ - union { /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */ - vuint32_t R; - struct { - vuint32_t:8; /* */ - vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */ - } B; - } TB1R_A; /*ETPU_TB1R */ - - /* offset 0x0028 */ - union { /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */ - vuint32_t R; - struct { - vuint32_t:8; /* */ - vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */ - } B; - } TB2R_A; /*ETPU_TB2R */ - - /* offset 0x002C */ - union { /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */ - vuint32_t R; - struct { - vuint32_t REN1:1; /* Resource Enable TCR1 */ - vuint32_t RSC1:1; /* Resource Control TCR1 */ - vuint32_t:2; /* */ - vuint32_t SERVER_ID1:4; /* */ - vuint32_t:4; /* */ - vuint32_t SRV1:4; /* Resource Server Slot */ - vuint32_t REN2:1; /* Resource Enable TCR2 */ - vuint32_t RSC2:1; /* Resource Control TCR2 */ - vuint32_t:2; /* */ - vuint32_t SERVER_ID2:4; /* */ - vuint32_t:4; /* */ - vuint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_A; /*ETPU_REDCR */ - - vuint32_t ETPU_reserved_2[12]; - - /* offset 0x0060 */ - union { /* ETPU1 WDTR Register */ - vuint32_t R; - struct { - vuint32_t WDM:2; - vuint32_t:14; - vuint32_t WDCNT:16; - } B; - } WDTR_A; - - vuint32_t ETPU1_reserved_3; - - /* offset 0x0068 */ - union { /* ETPU1 IDLE Register */ - vuint32_t R; - struct { - vuint32_t IDLE_CNT:31; - vuint32_t ICLR:1; - } B; - } IDLE_A; - - vuint32_t ETPU_reserved_4[101]; - - /* offset 0x0200 */ - union { /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */ - vuint32_t R; - struct { - vuint32_t CIS31:1; /* Channel 31 Interrut Status */ - vuint32_t CIS30:1; /* Channel 30 Interrut Status */ - vuint32_t CIS29:1; /* Channel 29 Interrut Status */ - vuint32_t CIS28:1; /* Channel 28 Interrut Status */ - vuint32_t CIS27:1; /* Channel 27 Interrut Status */ - vuint32_t CIS26:1; /* Channel 26 Interrut Status */ - vuint32_t CIS25:1; /* Channel 25 Interrut Status */ - vuint32_t CIS24:1; /* Channel 24 Interrut Status */ - vuint32_t CIS23:1; /* Channel 23 Interrut Status */ - vuint32_t CIS22:1; /* Channel 22 Interrut Status */ - vuint32_t CIS21:1; /* Channel 21 Interrut Status */ - vuint32_t CIS20:1; /* Channel 20 Interrut Status */ - vuint32_t CIS19:1; /* Channel 19 Interrut Status */ - vuint32_t CIS18:1; /* Channel 18 Interrut Status */ - vuint32_t CIS17:1; /* Channel 17 Interrut Status */ - vuint32_t CIS16:1; /* Channel 16 Interrut Status */ - vuint32_t CIS15:1; /* Channel 15 Interrut Status */ - vuint32_t CIS14:1; /* Channel 14 Interrut Status */ - vuint32_t CIS13:1; /* Channel 13 Interrut Status */ - vuint32_t CIS12:1; /* Channel 12 Interrut Status */ - vuint32_t CIS11:1; /* Channel 11 Interrut Status */ - vuint32_t CIS10:1; /* Channel 10 Interrut Status */ - vuint32_t CIS9:1; /* Channel 9 Interrut Status */ - vuint32_t CIS8:1; /* Channel 8 Interrut Status */ - vuint32_t CIS7:1; /* Channel 7 Interrut Status */ - vuint32_t CIS6:1; /* Channel 6 Interrut Status */ - vuint32_t CIS5:1; /* Channel 5 Interrut Status */ - vuint32_t CIS4:1; /* Channel 4 Interrut Status */ - vuint32_t CIS3:1; /* Channel 3 Interrut Status */ - vuint32_t CIS2:1; /* Channel 2 Interrut Status */ - vuint32_t CIS1:1; /* Channel 1 Interrut Status */ - vuint32_t CIS0:1; /* Channel 0 Interrut Status */ - } B; - } CISR_A; /* ETPU_CISR */ - - int32_t ETPU_reserved_5[3]; - - /* offset 0x0210 */ - union { /* @baseaddress + 0x210 */ - vuint32_t R; - struct { - vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_A; /* ETPU_CDTRSR */ - - int32_t ETPU_reserved_6[3]; - - /* offset 0x0220 */ - union { /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */ - vuint32_t R; - struct { - vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_A; /* ETPU_CIOSR */ - - int32_t ETPU_reserved_7[3]; - - /* offset 0x0230 */ - union { /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */ - vuint32_t R; - struct { - vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_A; /* ETPU_CDTROSR */ - - int32_t ETPU_reserved_8[3]; - - /* offset 0x0240 */ - union { /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */ - vuint32_t R; - struct { - vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ - vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ - vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ - vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ - vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ - vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ - vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ - vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ - vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ - vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ - vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ - vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ - vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ - vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ - vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ - vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ - vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ - vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ - vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ - vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ - vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ - vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ - vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ - vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ - vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ - vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ - vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ - vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ - vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ - vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ - vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ - vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_A; /* ETPU_CIER */ - - int32_t ETPU_reserved_9[3]; - - /* offset 0x0250 */ - union { /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */ - vuint32_t R; - struct { - vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_A; /* ETPU_CDTRER */ - - int32_t ETPU_reserved_10[3]; - - /* offset 0x0260 */ - union { /* ETPUWDSR - eTPU Watchdog Status Register */ - vuint32_t R; - struct { - vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } WDSR_A; - - int32_t ETPU_reserved_11[7]; - - /* offset 0x0280 */ - union { /* ETPUCPSSR - eTPU Channel Pending Service Status Register */ - vuint32_t R; - struct { - vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CPSSR_A; /* ETPU_CPSSR */ - - int32_t ETPU_reserved_12[3]; - - /* offset 0x0290 */ - union { /* ETPUCSSR - eTPU Channel Service Status Register */ - vuint32_t R; - struct { - vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CSSR_A; /* ETPU_CSSR */ - - int32_t ETPU_reserved_13[3]; - int32_t ETPU_reserved_14[88]; - -/***************************** Channels ********************************/ -/* Note not all devices implement all channels or even 2 engines */ -/* Each eTPU engine can implement 64 channels, however most devcies */ -/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */ -/* engines per instantiation */ -/***********************************************************************/ - - struct { - union { /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */ - vuint32_t R; - struct { - vuint32_t CIE:1; /* Channel Interruput Enable */ - vuint32_t DTRE:1; /* Data Transfer Request Enable */ - vuint32_t CPR:2; /* Channel Priority */ - vuint32_t:2; /* */ - vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */ - vuint32_t ETCS:1; /* Entry Table Condition Select */ - vuint32_t:3; /* */ - vuint32_t CFS:5; /* Channel Function Select */ - vuint32_t ODIS:1; /* Output disable */ - vuint32_t OPOL:1; /* output polarity */ - vuint32_t:3; /* */ - vuint32_t CPBA:11; /* Channel Parameter Base Address */ - } B; - } CR; /* ETPU_CnCR */ - - union { /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */ - vuint32_t R; - struct { - vuint32_t CIS:1; /* Channel Interruput Status */ - vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ - vuint32_t:6; /* */ - vuint32_t DTRS:1; /* Data Transfer Status */ - vuint32_t DTROS:1; /* Data Transfer Overflow Status */ - vuint32_t:6; /* */ - vuint32_t IPS:1; /* Input Pin State */ - vuint32_t OPS:1; /* Output Pin State */ - vuint32_t OBE:1; /* Output Pin State */ - vuint32_t:11; /* */ - vuint32_t FM1:1; /* Function mode */ - vuint32_t FM0:1; /* Function mode */ - } B; - } SCR; /* ETPU_CnSCR */ - - union { /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */ - vuint32_t R; - struct { - vuint32_t:29; /* Host Service Request */ - vuint32_t HSR:3; /* */ - } B; - } HSRR; /* ETPU_CnHSRR */ - int32_t ETPU_reserved_18; - - } CHAN[127]; - /**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */ - }; /* end of ETPU_tag */ -/****************************************************************************/ -/* MODULE : XBAR */ -/****************************************************************************/ - struct XBAR_tag { - union { - vuint32_t R; - struct { - vuint32_t:4; /* Master 7 Priority - Not implemented */ - vuint32_t:4; /* Master 6 Priority - Not implemented */ - vuint32_t:4; /* Master 5 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ - vuint32_t:4; /* Master 3 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ - vuint32_t:1; /* */ - vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ - vuint32_t:1; /* */ - vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ - } B; - } MPR0; /* Master Priority Register for Slave port 0 @baseaddress + 0x00 - Flash */ - - int32_t XBAR_reserverd_35[3]; - - union { - vuint32_t R; - struct { - vuint32_t RO:1; /* Read Only */ - vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ - vuint32_t:6; /* Slave General Purpose Control Register Reserved */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:6; /* */ - vuint32_t ARB:2; /* Arbitration Mode */ - vuint32_t:2; /* */ - vuint32_t PCTL:2; /* Parking Control */ - vuint32_t:1; /* */ - vuint32_t PARK:3; /* PARK */ - } B; - } SGPCR0; /* Slave General Purpose Control Register 0 @baseaddress + 0x10 */ - - int32_t XBAR_reserverd_71[59]; - - union { - vuint32_t R; - struct { - vuint32_t:4; /* Master 7 Priority - Not implemented */ - vuint32_t:4; /* Master 6 Priority - Not implemented */ - vuint32_t:4; /* Master 5 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ - vuint32_t:4; /* Master 3 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ - vuint32_t:1; /* */ - vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ - vuint32_t:1; /* */ - vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ - } B; - } MPR1; /* Master Priority Register for Slave port 1 @baseaddress + 0x100 */ - - int32_t XBAR_reserverd_105[3]; - - union { - vuint32_t R; - struct { - vuint32_t RO:1; /* Read Only */ - vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ - vuint32_t:6; /* Slave General Purpose Control Register Reserved */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:6; /* */ - vuint32_t ARB:2; /* Arbitration Mode */ - vuint32_t:2; /* */ - vuint32_t PCTL:2; /* Parking Control */ - vuint32_t:1; /* */ - vuint32_t PARK:3; /* PARK */ - } B; - } SGPCR1; /* Slave General Purpose Control Register 1 @baseaddress + 0x110 */ - - int32_t XBAR_reserverd_141[59]; - -/* Slave General Purpose Control Register 2 @baseaddress + 0x210 - not implemented */ - - int32_t XBAR_reserverd_211[64]; - - union { - vuint32_t R; - struct { - vuint32_t:4; /* Master 7 Priority - Not implemented */ - vuint32_t:4; /* Master 6 Priority - Not implemented */ - vuint32_t:4; /* Master 5 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ - vuint32_t:4; /* Master 3 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ - vuint32_t:1; /* */ - vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ - vuint32_t:1; /* */ - vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ - } B; - } MPR3; /* Master Priority Register for Slave port 3 @baseaddress + 0x300 */ - - int32_t XBAR_reserverd_245[3]; - - union { - vuint32_t R; - struct { - vuint32_t RO:1; /* Read Only */ - vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ - vuint32_t:6; /* Slave General Purpose Control Register Reserved */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:6; /* */ - vuint32_t ARB:2; /* Arbitration Mode */ - vuint32_t:2; /* */ - vuint32_t PCTL:2; /* Parking Control */ - vuint32_t:1; /* */ - vuint32_t PARK:3; /* PARK */ - } B; - } SGPCR3; /* Slave General Purpose Control Register 3 @baseaddress + 0x310 */ - - int32_t XBAR_reserverd_281[59]; - - /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */ - - int32_t XBAR_reserverd_351[64]; - - /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */ - - int32_t XBAR_reserverd_421[64]; - - /* Slave Port 6 not implemented @baseaddress + 0x610 */ - - int32_t XBAR_reserverd_491[64]; - - union { - vuint32_t R; - struct { - vuint32_t:4; /* Master 7 Priority - Not implemented */ - vuint32_t:4; /* Master 6 Priority - Not implemented */ - vuint32_t:4; /* Master 5 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ - vuint32_t:4; /* Master 3 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ - vuint32_t:1; /* */ - vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ - vuint32_t:1; /* */ - vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ - } B; - } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */ - - int32_t XBAR_reserverd_525[3]; - - union { - vuint32_t R; - struct { - vuint32_t RO:1; /* Read Only */ - vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ - vuint32_t:6; /* Slave General Purpose Control Register Reserved */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:6; /* */ - vuint32_t ARB:2; /* Arbitration Mode */ - vuint32_t:2; /* */ - vuint32_t PCTL:2; /* Parking Control */ - vuint32_t:1; /* */ - vuint32_t PARK:3; /* PARK */ - } B; - } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */ - - int32_t XBAR_reserverd_561[59]; - - union { - vuint32_t R; - struct { - vuint32_t:29; /* */ - vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MGPCR0; /* Master General Purpose Control Register 0 @baseaddress + 0x800 */ - - int32_t XBAR_reserverd_564[63]; - - union { - vuint32_t R; - struct { - vuint32_t:29; /* */ - vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MGPCR1; /* Master General Purpose Control Register 1 @baseaddress + 0x900 */ - - int32_t XBAR_reserverd_567[63]; - - union { - vuint32_t R; - struct { - vuint32_t:29; /* */ - vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MGPCR2; /* Master General Purpose Control Register 2 @baseaddress + 0xA00 */ - - int32_t XBAR_reserverd_570[63]; - - /* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */ - - int32_t XBAR_reserverd_573[64]; - - union { - vuint32_t R; - struct { - vuint32_t:29; /* */ - vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MGPCR4; /* Master General Purpose Control Register 4 @baseaddress + 0xC00 */ - - int32_t XBAR_reserverd_576[64]; - - /* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */ - - int32_t XBAR_reserverd_579[64]; - - /* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */ - - int32_t XBAR_reserverd_582[64]; - - /* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */ - - }; /* end of XBAR_tag */ -/****************************************************************************/ -/* MODULE : ECSM */ -/****************************************************************************/ - struct ECSM_tag { - /* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */ - uint32_t ecsm_reserved1[16]; - - uint8_t ecsm_reserved3[3]; /* base + 0x40 */ - - union { - vuint8_t R; - struct { - vuint8_t:6; - vuint8_t ERNCR:1; /* EPRNCR */ - vuint8_t EFNCR:1; /* EPFNCR */ - } B; - } ECR; /* ECC Configuration Register */ - - uint8_t ecsm_reserved4[3]; /* base + 0x44 */ - - union { - vuint8_t R; - struct { - vuint8_t:6; - vuint8_t RNCE:1; /* PRNCE */ - vuint8_t FNCE:1; /* PFNCE */ - } B; - } ESR; /* ECC Status Register */ - - /* EEGR don't exist in MPC563xM */ - uint32_t ecsm_reserved4a[2]; - - union { - vuint32_t R; - struct { - vuint32_t FEAR:32; /* PFEAR */ - } B; - } FEAR; /* Flash ECC Address Register PFEAR - 0x50 */ - - uint16_t ecsm_reserved4b; - - union { - vuint8_t R; - struct { - vuint8_t:4; - vuint8_t FEMR:4; /* PFEMR */ - } B; - } FEMR; /* Flash ECC Master Register PFEMR */ - - union { - vuint8_t R; - struct { - vuint8_t WRITE:1; - vuint8_t SIZE:3; - vuint8_t PROT0:1; /* PROTECTION */ - vuint8_t PROT1:1; /* PROTECTION */ - vuint8_t PROT2:1; /* PROTECTION */ - vuint8_t PROT3:1; /* PROTECTION */ - } B; - } FEAT; /* Flash ECC Attributes Register PFEAT */ - - union { - vuint32_t R; - struct { - vuint32_t FEDH:32; /* PFEDR */ - } B; - } FEDRH; /* Flash ECC Data High Register PFEDRH */ - - union { - vuint32_t R; - struct { - vuint32_t FEDL:32; /* PFEDR */ - } B; - } FEDRL; /* Flash ECC Data Low Register PFEDRL */ - - union { - vuint32_t R; - struct { - vuint32_t REAR:32; /* PREAR */ - } B; - } REAR; /* RAM ECC Address PREAR */ - - uint8_t ecsm_reserved5; - - union { - vuint8_t R; - struct { - vuint8_t PRESR:8; - } B; - } PRESR; /* RAM ECC Syndrome (new in MPC563xM) */ - - union { - vuint8_t R; - struct { - vuint8_t:4; - vuint8_t REMR:4; /* PREMR */ - } B; - } REMR; /* RAM ECC Master PREMR */ - - union { - vuint8_t R; - struct { - vuint8_t WRITE:1; - vuint8_t SIZE:3; - vuint8_t PROT0:1; /* PROTECTION */ - vuint8_t PROT1:1; /* PROTECTION */ - vuint8_t PROT2:1; /* PROTECTION */ - vuint8_t PROT3:1; /* PROTECTION */ - } B; - } REAT; /* RAM ECC Attributes Register PREAT */ - - union { - vuint32_t R; - struct { - vuint32_t REDH:32; /* PREDR */ - } B; - } REDRH; /* RAM ECC Data High Register PREDRH */ - - union { - vuint32_t R; - struct { - vuint32_t REDL:32; /* PREDR */ - } B; - } REDRL; /* RAMECC Data Low Register PREDRL */ - - }; -/****************************************************************************/ -/* MODULE : EDMA */ -/****************************************************************************/ - struct EDMA_tag { - union { - vuint32_t R; - struct { - vuint32_t:14; /* Reserved */ - vuint32_t CX:1; /* Cancel Transfer (new in MPC563xM) */ - vuint32_t ECX:1; /* Error Cancel Transfer (new in MPC563xM) */ - vuint32_t GRP3PRI:2; /* Channel Group 3 Priority (new in MPC563xM) */ - vuint32_t GRP2PRI:2; /* Channel Group 2 Priority (new in MPC563xM) */ - vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */ - vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */ - vuint32_t EMLM:1; /* Enable Minor Loop Mapping (new in MPC563xM) */ - vuint32_t CLM:1; /* Continuous Link Mode (new in MPC563xM) */ - vuint32_t HALT:1; /* Halt DMA Operations (new in MPC563xM) */ - vuint32_t HOE:1; /* Halt On Error (new in MPC563xM) */ - vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ - vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ - vuint32_t EDBG:1; /* Enable Debug */ - vuint32_t EBW:1; /* Enable Buffered Writes */ - } B; - } CR; /* DMA Control Register DMACR @baseaddress + 0x0 */ - - union { - vuint32_t R; - struct { - vuint32_t VLD:1; /* Logical OR of all DMAERRH */ - - vuint32_t:14; /* Reserved */ - vuint32_t ECX:1; /* (new in MPC563xM) */ - vuint32_t GPE:1; /* Group Priority Error */ - vuint32_t CPE:1; /* Channel Priority Error */ - vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */ - vuint32_t SAE:1; /* Source Address Error 0 */ - vuint32_t SOE:1; /* Source Offset Error */ - vuint32_t DAE:1; /* Destination Address Error */ - vuint32_t DOE:1; /* Destination Offset Error */ - vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */ - vuint32_t SGE:1; /* Scatter/Gather Configuration Error */ - vuint32_t SBE:1; /* Source Bus Error */ - vuint32_t DBE:1; /* Destination Bus Error */ - - } B; - } ESR; /* DMAES Error Status Register */ - - uint32_t edma_reserved_erqrh; - - union { - vuint32_t R; - struct { - vuint32_t ERQ31:1; - vuint32_t ERQ30:1; - vuint32_t ERQ29:1; - vuint32_t ERQ28:1; - vuint32_t ERQ27:1; - vuint32_t ERQ26:1; - vuint32_t ERQ25:1; - vuint32_t ERQ24:1; - vuint32_t ERQ23:1; - vuint32_t ERQ22:1; - vuint32_t ERQ21:1; - vuint32_t ERQ20:1; - vuint32_t ERQ19:1; - vuint32_t ERQ18:1; - vuint32_t ERQ17:1; - vuint32_t ERQ16:1; - vuint32_t ERQ15:1; - vuint32_t ERQ14:1; - vuint32_t ERQ13:1; - vuint32_t ERQ12:1; - vuint32_t ERQ11:1; - vuint32_t ERQ10:1; - vuint32_t ERQ09:1; - vuint32_t ERQ08:1; - vuint32_t ERQ07:1; - vuint32_t ERQ06:1; - vuint32_t ERQ05:1; - vuint32_t ERQ04:1; - vuint32_t ERQ03:1; - vuint32_t ERQ02:1; - vuint32_t ERQ01:1; - vuint32_t ERQ00:1; - } B; - } ERQRL; /* DMAERQL ,DMA Enable Request Register Low */ - - uint32_t edma_reserved_eeirh; - - union { - vuint32_t R; - struct { - vuint32_t EEI31:1; - vuint32_t EEI30:1; - vuint32_t EEI29:1; - vuint32_t EEI28:1; - vuint32_t EEI27:1; - vuint32_t EEI26:1; - vuint32_t EEI25:1; - vuint32_t EEI24:1; - vuint32_t EEI23:1; - vuint32_t EEI22:1; - vuint32_t EEI21:1; - vuint32_t EEI20:1; - vuint32_t EEI19:1; - vuint32_t EEI18:1; - vuint32_t EEI17:1; - vuint32_t EEI16:1; - vuint32_t EEI15:1; - vuint32_t EEI14:1; - vuint32_t EEI13:1; - vuint32_t EEI12:1; - vuint32_t EEI11:1; - vuint32_t EEI10:1; - vuint32_t EEI09:1; - vuint32_t EEI08:1; - vuint32_t EEI07:1; - vuint32_t EEI06:1; - vuint32_t EEI05:1; - vuint32_t EEI04:1; - vuint32_t EEI03:1; - vuint32_t EEI02:1; - vuint32_t EEI01:1; - vuint32_t EEI00:1; - } B; - } EEIRL; /* DMAEEIL , DMA Enable Error Interrupt Register Low */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 SERQ:7 */ - } SERQR; /* DMASERQ , DMA Set Enable Request Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CERQ:7 */ - } CERQR; /* DMACERQ , DMA Clear Enable Request Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 SEEI:7 */ - } SEEIR; /* DMASEEI , DMA Set Enable Error Interrupt Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CEEI:7 */ - } CEEIR; /* DMACEEI , DMA Clear Enable Error Interrupt Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CINT:7 */ - } CIRQR; /* DMACINT , DMA Clear Interrupt Request Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CERR:7 */ - } CER; /* DMACERR , DMA Clear error Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 SSRT:7 */ - } SSBR; /* DMASSRT , Set Start Bit Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CDNE:7 */ - } CDSBR; /* DMACDNE , Clear Done Status Bit Register */ - - uint32_t edma_reserved_irqrh; - - union { - vuint32_t R; - struct { - vuint32_t INT31:1; - vuint32_t INT30:1; - vuint32_t INT29:1; - vuint32_t INT28:1; - vuint32_t INT27:1; - vuint32_t INT26:1; - vuint32_t INT25:1; - vuint32_t INT24:1; - vuint32_t INT23:1; - vuint32_t INT22:1; - vuint32_t INT21:1; - vuint32_t INT20:1; - vuint32_t INT19:1; - vuint32_t INT18:1; - vuint32_t INT17:1; - vuint32_t INT16:1; - vuint32_t INT15:1; - vuint32_t INT14:1; - vuint32_t INT13:1; - vuint32_t INT12:1; - vuint32_t INT11:1; - vuint32_t INT10:1; - vuint32_t INT09:1; - vuint32_t INT08:1; - vuint32_t INT07:1; - vuint32_t INT06:1; - vuint32_t INT05:1; - vuint32_t INT04:1; - vuint32_t INT03:1; - vuint32_t INT02:1; - vuint32_t INT01:1; - vuint32_t INT00:1; - } B; - } IRQRL; /* DMAINTL , DMA Interrupt Request Low */ - - uint32_t edma_reserved_erh; - - union { - vuint32_t R; - struct { - vuint32_t ERR31:1; - vuint32_t ERR30:1; - vuint32_t ERR29:1; - vuint32_t ERR28:1; - vuint32_t ERR27:1; - vuint32_t ERR26:1; - vuint32_t ERR25:1; - vuint32_t ERR24:1; - vuint32_t ERR23:1; - vuint32_t ERR22:1; - vuint32_t ERR21:1; - vuint32_t ERR20:1; - vuint32_t ERR19:1; - vuint32_t ERR18:1; - vuint32_t ERR17:1; - vuint32_t ERR16:1; - vuint32_t ERR15:1; - vuint32_t ERR14:1; - vuint32_t ERR13:1; - vuint32_t ERR12:1; - vuint32_t ERR11:1; - vuint32_t ERR10:1; - vuint32_t ERR09:1; - vuint32_t ERR08:1; - vuint32_t ERR07:1; - vuint32_t ERR06:1; - vuint32_t ERR05:1; - vuint32_t ERR04:1; - vuint32_t ERR03:1; - vuint32_t ERR02:1; - vuint32_t ERR01:1; - vuint32_t ERR00:1; - } B; - } ERL; /* DMAERRL , DMA Error Low */ - - int32_t edma_reserverd_hrsh[1]; - - int32_t edma_reserverd_hrsl[1]; - - int32_t edma_reserverd_gpor[1]; - - int32_t EDMA_reserverd_223[49]; - - union { - vuint8_t R; - struct { - vuint8_t ECP:1; - vuint8_t DPA:1; - vuint8_t GRPPRI:2; - vuint8_t CHPRI:4; - } B; - } CPR[64]; /* DCHPRI [32] , Channel n Priority */ - - uint32_t edma_reserved2[944]; - -/****************************************************************************/ -/* DMA2 Transfer Control Descriptor */ -/****************************************************************************/ - - struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */ - vuint32_t SADDR; /* source address */ - - vuint16_t SMOD:5; /* source address modulo */ - vuint16_t SSIZE:3; /* source transfer size */ - vuint16_t DMOD:5; /* destination address modulo */ - vuint16_t DSIZE:3; /* destination transfer size */ - vint16_t SOFF; /* signed source address offset */ - vuint32_t NBYTES; /* inner (“minor”) byte count */ - vint32_t SLAST; /* last destination address adjustment, or - - scatter/gather address (if e_sg = 1) */ - vuint32_t DADDR; /* destination address */ - vuint16_t CITERE_LINK:1; - vuint16_t CITER:15; - vint16_t DOFF; /* signed destination address offset */ - vint32_t DLAST_SGA; - vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ - vuint16_t BITER:15; - vuint16_t BWC:2; /* bandwidth control */ - vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ - vuint16_t DONE:1; /* channel done */ - vuint16_t ACTIVE:1; /* channel active */ - vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ - vuint16_t E_SG:1; /* enable scatter/gather descriptor */ - vuint16_t D_REQ:1; /* disable ipd_req when done */ - vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ - vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ - vuint16_t START:1; /* explicit channel start */ - } TCD[64]; /* TCD [32] , transfer_control_descriptor */ - }; - - struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */ - - struct tcd_alt1_t { - vuint32_t SADDR; /* source address */ - - vuint16_t SMOD:5; /* source address modulo */ - vuint16_t SSIZE:3; /* source transfer size */ - vuint16_t DMOD:5; /* destination address modulo */ - vuint16_t DSIZE:3; /* destination transfer size */ - vint16_t SOFF; /* signed source address offset */ - vuint32_t NBYTES; /* inner (“minor”) byte count */ - vint32_t SLAST; /* last destination address adjustment, or - - scatter/gather address (if e_sg = 1) */ - vuint32_t DADDR; /* destination address */ - vuint16_t CITERE_LINK:1; - vuint16_t CITERLINKCH:6; - vuint16_t CITER:9; - vint16_t DOFF; /* signed destination address offset */ - vint32_t DLAST_SGA; - vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */ - vuint16_t BITERLINKCH:6; - vuint16_t BITER:9; - vuint16_t BWC:2; /* bandwidth control */ - vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ - vuint16_t DONE:1; /* channel done */ - vuint16_t ACTIVE:1; /* channel active */ - vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ - vuint16_t E_SG:1; /* enable scatter/gather descriptor */ - vuint16_t D_REQ:1; /* disable ipd_req when done */ - vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ - vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ - vuint16_t START:1; /* explicit channel start */ - } TCD[64]; /* TCD [32] , transfer_control_descriptor */ - }; - -/****************************************************************************/ -/* MODULE : INTC */ -/****************************************************************************/ - struct INTC_tag { - union { - vuint32_t R; - struct { - vuint32_t:18; /* Reserved */ - vuint32_t VTES_PRC1:1; /* Vector Table Entry Size for PRC1 (new in MPC563xM) */ - vuint32_t:4; /* Reserved */ - vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable for PRC1 (new in MPC563xM) */ - vuint32_t:2; /* Reserved */ - vuint32_t VTES:1; /* Vector Table Entry Size for PRC0 VTES_PRC0 */ - vuint32_t:4; /* Reserved */ - vuint32_t HVEN:1; /* Hardware Vector Enable for PRC0 HVEN_PRC0 */ - } B; - } MCR; /* INTC Module Configuration Register (MCR) INTC_BCR @baseaddress + 0x00 */ - int32_t INTC_reserverd_10[1]; - - union { - vuint32_t R; - struct { - vuint32_t:28; /* Reserved */ - vuint32_t PRI:4; /* Priority */ - } B; - } CPR; /* INTC Current Priority Register for Processor 0 (CPR) INTC_CPR_PRC0 @baseaddress + 0x08 */ - - int32_t INTC_reserved_1; /* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) INTC_CPR_PRC1 @baseaddress + 0x0c */ - - union { - vuint32_t R; - struct { - vuint32_t VTBA:21; /* Vector Table Base Address VTBA_PRC0 */ - vuint32_t INTVEC:9; /* Interrupt Vector INTVEC_PRC0 */ - vuint32_t:2; /* Reserved */ - } B; - } IACKR; /* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) INTC_IACKR_PRC0 @baseaddress + 0x10 */ - - int32_t INTC_reserverd_2; /* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) INTC_IACKR_PRC1 @baseaddress + 0x14 */ - - union { - vuint32_t R; - } EOIR; /* INTC End of Interrupt Register for Processor 0 (EOIR) INTC_EOIR_PRC0 @baseaddress + 0x18 */ - - int32_t INTC_reserverd_3; /* EOIR_PRC1 - INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) INTC_EOIR_PRC1 @baseaddress + 0x1C */ - - union { - vuint8_t R; - struct { - vuint8_t:6; /* Reserved */ - vuint8_t SET:1; /* Set Flag bits */ - vuint8_t CLR:1; /* Clear Flag bits */ - } B; - } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) INTC_SSCIRn @baseaddress + 0x20 */ - - int32_t INTC_reserverd_32[6]; - - union { - vuint8_t R; - struct { - vuint8_t PRC_SEL:2; /* Processor Select (new in MPC563xM) */ - vuint8_t:2; /* Reserved */ - vuint8_t PRI:4; /* Priority Select */ - } B; - } PSR[512]; /* INTC Priority Select Registers (PSR) INTC_PSR @baseaddress + 0x40 */ - - }; /* end of INTC_tag */ -/****************************************************************************/ -/* MODULE : EQADC */ -/****************************************************************************/ - struct EQADC_tag { - union { - vuint32_t R; - struct { - vuint32_t:24; - vuint32_t ICEA0:1; - vuint32_t ICEA1:1; - vuint32_t:1; - vuint32_t ESSIE:2; - vuint32_t:1; - vuint32_t DBG:2; - } B; - } MCR; /* Module Configuration Register EQADC_MCR */ - - int32_t EQADC_reserved00; - - union { - vuint32_t R; - struct { - vuint32_t:6; - vuint32_t NMF:26; - } B; - } NMSFR; /* Null Message Send Format Register EQADC_NMSFR */ - - union { - vuint32_t R; - struct { - vuint32_t:28; - vuint32_t DFL:4; - } B; - } ETDFR; /* External Trigger Digital Filter Register EQADC_ETDFR */ - - union { - vuint32_t R; - struct { - vuint32_t CFPUSH:32; /* CF_PUSH */ - } B; - } CFPR[6]; /* CFIFO Push Registers EQADC_CFPR */ - - uint32_t eqadc_reserved1; - - uint32_t eqadc_reserved2; - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t RFPOP:16; /* RF_POP */ - } B; - } RFPR[6]; /* Result FIFO Pop Registers EQADC_RFPR */ - - uint32_t eqadc_reserved3; - - uint32_t eqadc_reserved4; - - union { - vuint16_t R; - struct { - vuint16_t:3; - vuint16_t CFEE0:1; - vuint16_t STRME0:1; - vuint16_t SSE:1; - vuint16_t CFINV:1; - vuint16_t:1; - vuint16_t MODE:4; - vuint16_t AMODE0:4; /* CFIFO0 only */ - } B; - } CFCR[6]; /* CFIFO Control Registers EQADC_CFCR */ - - uint32_t eqadc_reserved5; - - union { - vuint16_t R; - struct { - vuint16_t NCIE:1; - vuint16_t TORIE:1; - vuint16_t PIE:1; - vuint16_t EOQIE:1; - vuint16_t CFUIE:1; - vuint16_t:1; - vuint16_t CFFE:1; - vuint16_t CFFS:1; - vuint16_t:4; - vuint16_t RFOIE:1; - vuint16_t:1; - vuint16_t RFDE:1; - vuint16_t RFDS:1; - } B; - } IDCR[6]; /* Interrupt and DMA Control Registers EQADC_IDCR */ - - uint32_t eqadc_reserved6; - - union { - vuint32_t R; - struct { - vuint32_t NCF:1; - vuint32_t TORF:1; - vuint32_t PF:1; - vuint32_t EOQF:1; - vuint32_t CFUF:1; - vuint32_t SSS:1; - vuint32_t CFFF:1; - vuint32_t:5; - vuint32_t RFOF:1; - vuint32_t:1; - vuint32_t RFDF:1; - vuint32_t:1; - vuint32_t CFCTR:4; - vuint32_t TNXTPTR:4; - vuint32_t RFCTR:4; - vuint32_t POPNXTPTR:4; - } B; - } FISR[6]; /* FIFO and Interrupt Status Registers EQADC_FISR */ - - uint32_t eqadc_reserved7; - - uint32_t eqadc_reserved8; - - union { - vuint16_t R; - struct { - vuint16_t:5; - vuint16_t TCCF:11; /* TC_CF */ - } B; - } CFTCR[6]; /* CFIFO Transfer Counter Registers EQADC_CFTCR */ - - uint32_t eqadc_reserved9; - - union { - vuint32_t R; - struct { - vuint32_t CFS0:2; /* CFS0_TCB0 */ - vuint32_t CFS1:2; /* CFS1_TCB0 */ - vuint32_t CFS2:2; /* CFS2_TCB0 */ - vuint32_t CFS3:2; /* CFS3_TCB0 */ - vuint32_t CFS4:2; /* CFS4_TCB0 */ - vuint32_t CFS5:2; /* CFS5_TCB0 */ - vuint32_t:5; - vuint32_t LCFTCB0:4; - vuint32_t TC_LCFTCB0:11; - } B; - } CFSSR0; /* CFIFO Status Register 0 EQADC_CFSSR0 */ - - union { - vuint32_t R; - struct { - vuint32_t CFS0:2; /* CFS0_TCB1 */ - vuint32_t CFS1:2; /* CFS1_TCB1 */ - vuint32_t CFS2:2; /* CFS2_TCB1 */ - vuint32_t CFS3:2; /* CFS3_TCB1 */ - vuint32_t CFS4:2; /* CFS4_TCB1 */ - vuint32_t CFS5:2; /* CFS5_TCB1 */ - vuint32_t:5; - vuint32_t LCFTCB1:4; - vuint32_t TC_LCFTCB1:11; - } B; - } CFSSR1; /* CFIFO Status Register 1 EQADC_CFSSR1 */ - - union { - vuint32_t R; - struct { - vuint32_t CFS0:2; /* CFS0_TSSI */ - vuint32_t CFS1:2; /* CFS1_TSSI */ - vuint32_t CFS2:2; /* CFS2_TSSI */ - vuint32_t CFS3:2; /* CFS3_TSSI */ - vuint32_t CFS4:2; /* CFS4_TSSI */ - vuint32_t CFS5:2; /* CFS5_TSSI */ - vuint32_t:4; - vuint32_t ECBNI:1; - vuint32_t LCFTSSI:4; - vuint32_t TC_LCFTSSI:11; - } B; - } CFSSR2; /* CFIFO Status Register 2 EQADC_CFSSR2 */ - - union { - vuint32_t R; - struct { - vuint32_t CFS0:2; - vuint32_t CFS1:2; - vuint32_t CFS2:2; - vuint32_t CFS3:2; - vuint32_t CFS4:2; - vuint32_t CFS5:2; - vuint32_t:20; - } B; - } CFSR; /* EQADC_CFSR */ - - uint32_t eqadc_reserved11; - - union { - vuint32_t R; - struct { - vuint32_t:21; - vuint32_t MDT:3; - vuint32_t:4; - vuint32_t BR:4; - } B; - } SSICR; /* SSI Control Register EQADC_SSICR */ - - union { - vuint32_t R; - struct { - vuint32_t RDV:1; - vuint32_t:5; - vuint32_t RDATA:26; - } B; - } SSIRDR; /* SSI Recieve Data Register EQADC_SSIRDR @ baseaddress + 0xB8 */ - - uint32_t eqadc_reserved11b[5]; - - uint32_t eqadc_reserved15; /* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0 */ - /* REDLCCR is not implemented in the MPC563xM */ - - uint32_t eqadc_reserved12[11]; - - struct { - union { - vuint32_t R; - - /*B.CFIFOx_DATAw */ - - } R[4]; /*EQADC_CFxRw */ - - union { - vuint32_t R; - /*B.CFIFOx_EDATAw */ - } EDATA[4]; /*EQADC_CFxERw (new in MPC563xM) */ - - uint32_t eqadc_reserved13[8]; - - } CF[6]; - - uint32_t eqadc_reserved14[32]; - - struct { - union { - vuint32_t R; - /*RFIFOx_DATAw */ - } R[4]; /*EQADC_RFxRw */ - - uint32_t eqadc_reserved15[12]; - - } RF[6]; - - }; - /****************************************************************************/ -/* MODULE : DSPI */ -/****************************************************************************/ - struct DSPI_tag { - union { - vuint32_t R; - struct { - vuint32_t MSTR:1; - vuint32_t CONT_SCKE:1; - vuint32_t DCONF:2; - vuint32_t FRZ:1; - vuint32_t MTFE:1; - vuint32_t PCSSE:1; - vuint32_t ROOE:1; - vuint32_t PCSIS7:1; /* new in MPC563xM */ - vuint32_t PCSIS6:1; /* new in MPC563xM */ - vuint32_t PCSIS5:1; - vuint32_t PCSIS4:1; - vuint32_t PCSIS3:1; - vuint32_t PCSIS2:1; - vuint32_t PCSIS1:1; - vuint32_t PCSIS0:1; - vuint32_t DOZE:1; - vuint32_t MDIS:1; - vuint32_t DIS_TXF:1; - vuint32_t DIS_RXF:1; - vuint32_t CLR_TXF:1; - vuint32_t CLR_RXF:1; - vuint32_t SMPL_PT:2; - vuint32_t:7; - vuint32_t HALT:1; - } B; - } MCR; /* Module Configuration Register DSPI_MCR @baseaddress + 0x00 */ - - uint32_t dspi_reserved1; - - union { - vuint32_t R; - struct { - vuint32_t TCNT:16; /* SPI_TCNT */ - vuint32_t:16; - } B; - } TCR; /* DSPI Transfer Count Register DSPI_TCR @baseaddress + 0x08 */ - - union { - vuint32_t R; - struct { - vuint32_t DBR:1; - vuint32_t FMSZ:4; - vuint32_t CPOL:1; - vuint32_t CPHA:1; - vuint32_t LSBFE:1; - vuint32_t PCSSCK:2; - vuint32_t PASC:2; - vuint32_t PDT:2; - vuint32_t PBR:2; - vuint32_t CSSCK:4; - vuint32_t ASC:4; - vuint32_t DT:4; - vuint32_t BR:4; - } B; - } CTAR[8]; /* Clock and Transfer Attributes Registers DSPI_CTARx @baseaddress + 0x0C - 0x28 */ - - union { - vuint32_t R; - struct { - vuint32_t TCF:1; - vuint32_t TXRXS:1; - vuint32_t:1; - vuint32_t EOQF:1; - vuint32_t TFUF:1; - vuint32_t:1; - vuint32_t TFFF:1; - vuint32_t:5; - vuint32_t RFOF:1; - vuint32_t:1; - vuint32_t RFDF:1; - vuint32_t:1; - vuint32_t TXCTR:4; - vuint32_t TXNXTPTR:4; - vuint32_t RXCTR:4; - vuint32_t POPNXTPTR:4; - } B; - } SR; /* Status Register DSPI_SR @baseaddress + 0x2C */ - - union { - vuint32_t R; - struct { - vuint32_t TCFRE:1; /*TCF_RE */ - vuint32_t:2; - vuint32_t EOQFRE:1; /*EQQF_RE */ - vuint32_t TFUFRE:1; /*TFUF_RE */ - vuint32_t:1; - vuint32_t TFFFRE:1; /*TFFF_RE */ - vuint32_t TFFFDIRS:1; /*TFFF_DIRS */ - vuint32_t:4; - vuint32_t RFOFRE:1; /*RFOF_RE */ - vuint32_t:1; - vuint32_t RFDFRE:1; /*RFDF_RE */ - vuint32_t RFDFDIRS:1; /*RFDF_DIRS */ - vuint32_t:16; - } B; - } RSER; /* DMA/Interrupt Request Select and Enable Register DSPI_RSER @baseaddress + 0x30 */ - - union { - vuint32_t R; - struct { - vuint32_t CONT:1; - vuint32_t CTAS:3; - vuint32_t EOQ:1; - vuint32_t CTCNT:1; - vuint32_t:2; - vuint32_t PCS7:1; /* new in MPC563xM */ - vuint32_t PCS6:1; /* new in MPC563xM */ - vuint32_t PCS5:1; - vuint32_t PCS4:1; - vuint32_t PCS3:1; - vuint32_t PCS2:1; - vuint32_t PCS1:1; - vuint32_t PCS0:1; - vuint32_t TXDATA:16; - } B; - } PUSHR; /* PUSH TX FIFO Register DSPI_PUSHR @baseaddress + 0x34 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t RXDATA:16; - } B; - } POPR; /* POP RX FIFO Register DSPI_POPR @baseaddress + 0x38 */ - - union { - vuint32_t R; - struct { - vuint32_t TXCMD:16; - vuint32_t TXDATA:16; - } B; - } TXFR[4]; /* Transmit FIFO Registers DSPI_TXFRx @baseaddress + 0x3c - 0x78 */ - - vuint32_t DSPI_reserved_txf[12]; - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t RXDATA:16; - } B; - } RXFR[4]; /* Transmit FIFO Registers DSPI_RXFRx @baseaddress + 0x7c - 0xB8 */ - - vuint32_t DSPI_reserved_rxf[12]; - - union { - vuint32_t R; - struct { - vuint32_t MTOE:1; - vuint32_t:1; - vuint32_t MTOCNT:6; - vuint32_t:3; - vuint32_t TSBC:1; - vuint32_t TXSS:1; - vuint32_t TPOL:1; - vuint32_t TRRE:1; - vuint32_t CID:1; - vuint32_t DCONT:1; - vuint32_t DSICTAS:3; - vuint32_t:4; - vuint32_t DPCS7:1; - vuint32_t DPCS6:1; - vuint32_t DPCS5:1; - vuint32_t DPCS4:1; - vuint32_t DPCS3:1; - vuint32_t DPCS2:1; - vuint32_t DPCS1:1; - vuint32_t DPCS0:1; - } B; - } DSICR; /* DSI Configuration Register DSPI_DSICR @baseaddress + 0xBC */ - - union { - vuint32_t R; - struct { - vuint32_t SER_DATA:32; /* 32bit instead of 16 in MPC563xM */ - } B; - } SDR; /* DSI Serialization Data Register DSPI_SDR @baseaddress + 0xC0 */ - - union { - vuint32_t R; - struct { - vuint32_t ASER_DATA:32; /* 32bit instead of 16 in MPC563xM */ - } B; - } ASDR; /* DSI Alternate Serialization Data Register DSPI_ASDR @baseaddress + 0xC4 */ - - union { - vuint32_t R; - struct { - vuint32_t COMP_DATA:32; /* 32bit instead of 16 in MPC563xM */ - } B; - } COMPR; /* DSI Transmit Comparison Register DSPI_COMPR @baseaddress + 0xC8 */ - - union { - vuint32_t R; - struct { - vuint32_t DESER_DATA:32; /* 32bit instead of 16 in MPC563xM */ - } B; - } DDR; /* DSI deserialization Data Register DSPI_DDR @baseaddress + 0xCC */ - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t TSBCNT:5; - vuint32_t:16; - vuint32_t DPCS1_7:1; - vuint32_t DPCS1_6:1; - vuint32_t DPCS1_5:1; - vuint32_t DPCS1_4:1; - vuint32_t DPCS1_3:1; - vuint32_t DPCS1_2:1; - vuint32_t DPCS1_1:1; - vuint32_t DPCS1_0:1; - } B; - } DSICR1; /* DSI Configuration Register 1 DSPI_DSICR1 @baseaddress + 0xD0 */ - - }; -/****************************************************************************/ -/* MODULE : eSCI */ -/****************************************************************************/ - struct ESCI_tag { - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t SBR:13; - vuint32_t LOOPS:1; - vuint32_t:1; /* Reserved in MPC563xM */ - vuint32_t RSRC:1; - vuint32_t M:1; - vuint32_t WAKE:1; - vuint32_t ILT:1; - vuint32_t PE:1; - vuint32_t PT:1; - vuint32_t TIE:1; - vuint32_t TCIE:1; - vuint32_t RIE:1; - vuint32_t ILIE:1; - vuint32_t TE:1; - vuint32_t RE:1; - vuint32_t RWU:1; - vuint32_t SBK:1; - } B; - } CR1; /* Control Register 1 SCIBDH, SCIBDL, SCICR1, SCICR2 @baseaddress + 0x00 */ - - union { - vuint16_t R; - struct { - vuint16_t MDIS:1; - vuint16_t FBR:1; - vuint16_t BSTP:1; - vuint16_t IEBERR:1; /* BERIE */ - vuint16_t RXDMA:1; - vuint16_t TXDMA:1; - vuint16_t BRK13:1; /* BRCL */ - vuint16_t TXDIR:1; - vuint16_t BESM13:1; /* BESM */ - vuint16_t SBSTP:1; /* BESTP */ - vuint16_t RXPOL:1; - vuint16_t PMSK:1; - vuint16_t ORIE:1; - vuint16_t NFIE:1; - vuint16_t FEIE:1; - vuint16_t PFIE:1; - } B; - } CR2; /* Control Register 2 SCICR3, SCICR4 @baseaddress + 0x04 */ - - union { - vuint16_t R; - struct { - vuint16_t R8:1; /* RN */ - vuint16_t T8:1; /* TN */ - vuint16_t ERR:1; - vuint16_t:1; - vuint16_t R:4; - vuint8_t D; - } B; - } DR; /* Data Register SCIDRH, SCIDRL @baseaddress + 0x06 */ - - union { - vuint32_t R; - struct { - vuint32_t TDRE:1; - vuint32_t TC:1; - vuint32_t RDRF:1; - vuint32_t IDLE:1; - vuint32_t OR:1; - vuint32_t NF:1; - vuint32_t FE:1; - vuint32_t PF:1; - vuint32_t:3; - vuint32_t BERR:1; - vuint32_t:2; - vuint32_t TACT:1; - vuint32_t RAF:1; /* RACT */ - vuint32_t RXRDY:1; - vuint32_t TXRDY:1; - vuint32_t LWAKE:1; - vuint32_t STO:1; - vuint32_t PBERR:1; - vuint32_t CERR:1; - vuint32_t CKERR:1; - vuint32_t FRC:1; - vuint32_t:6; - vuint32_t UREQ:1; - vuint32_t OVFL:1; - } B; - } SR; /* Status Register SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 @baseaddress + 0x08 */ - - union { - vuint32_t R; - struct { - vuint32_t LRES:1; - vuint32_t WU:1; - vuint32_t WUD0:1; - vuint32_t WUD1:1; - vuint32_t:2; /* reserved: LDBG and DSF not longer supported */ - vuint32_t PRTY:1; - vuint32_t LIN:1; - vuint32_t RXIE:1; - vuint32_t TXIE:1; - vuint32_t WUIE:1; - vuint32_t STIE:1; - vuint32_t PBIE:1; - vuint32_t CIE:1; - vuint32_t CKIE:1; - vuint32_t FCIE:1; - vuint32_t:6; - vuint32_t UQIE:1; - vuint32_t OFIE:1; - vuint32_t:8; - } B; - } LCR; /* LIN Control Register LINCTRL1, LINCTRL2, LINCTRL3 @baseaddress + 0x0C */ - - union { - vuint32_t R; - } LTR; /* LIN Transmit Register LINTX @baseaddress + 0x10 */ - - union { - vuint32_t R; - } LRR; /* LIN Recieve Register LINRX @baseaddress + 0x14 */ - - union { - vuint32_t R; - struct { - vuint32_t P:16; - vuint32_t:3; - vuint32_t SYNM:1; - vuint32_t EROE:1; - vuint32_t ERFE:1; - vuint32_t ERPE:1; - vuint32_t M2:1; - vuint32_t:8; - } B; - } LPR; /* LIN CRC Polynom Register LINCRCP1, LINCRCP2, SCICR5 @baseaddress + 0x18 */ - - }; -/****************************************************************************/ -/* MODULE : eSCI */ -/****************************************************************************/ - struct ESCI_12_13_bit_tag { - union { - vuint16_t R; - struct { - vuint16_t R8:1; - vuint16_t T8:1; - vuint16_t ERR:1; - vuint16_t:1; - vuint16_t D:12; - } B; - } DR; /* Data Register */ - }; -/****************************************************************************/ -/* MODULE : FlexCAN */ -/****************************************************************************/ - struct FLEXCAN_BUF_t { - union { - vuint32_t R; - struct { - vuint32_t:4; - vuint32_t CODE:4; - vuint32_t:1; - vuint32_t SRR:1; - vuint32_t IDE:1; - vuint32_t RTR:1; - vuint32_t LENGTH:4; - vuint32_t TIMESTAMP:16; - } B; - } CS; - - union { - vuint32_t R; - struct { - vuint32_t PRIO:3; - vuint32_t STD_ID:11; - vuint32_t EXT_ID:18; - } B; - } ID; - - union { - /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ - /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ - vuint32_t W[2]; /* Data buffer in words (32 bits) */ - /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ - } DATA; - - }; /* end of FLEXCAN_BUF_t */ - - struct FLEXCAN_RXFIFO_t { - union { - vuint32_t R; - struct { - vuint32_t:9; - vuint32_t SRR:1; - vuint32_t IDE:1; - vuint32_t RTR:1; - vuint32_t LENGTH:4; - vuint32_t TIMESTAMP:16; - } B; - } CS; - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t STD_ID:11; - vuint32_t EXT_ID:18; - } B; - } ID; - - union { - /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ - /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ - vuint32_t W[2]; /* Data buffer in words (32 bits) */ - /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ - } DATA; - - uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ - - union { - vuint32_t R; - } IDTABLE[8]; - - }; /* end of FLEXCAN_RXFIFO_t */ - - struct FLEXCAN2_tag { - union { - vuint32_t R; - struct { - vuint32_t MDIS:1; - vuint32_t FRZ:1; - vuint32_t FEN:1; /* new in MPC563xM */ - vuint32_t HALT:1; - vuint32_t NOTRDY:1; /* NOT_RDY */ - vuint32_t WAK_MSK:1; /* new in MPC563xM */ - vuint32_t SOFTRST:1; /* SOFT_RST */ - vuint32_t FRZACK:1; /* FRZ_ACK */ - vuint32_t SUPV:1; /* new in MPC563xM */ - vuint32_t SLF_WAK:1; /* new in MPC563xM */ - - vuint32_t WRNEN:1; /* WRN_EN */ - - vuint32_t MDISACK:1; /* LPM_ACK */ - vuint32_t WAK_SRC:1; /* new in MPC563xM */ - vuint32_t DOZE:1; /* new in MPC563xM */ - - vuint32_t SRXDIS:1; /* SRX_DIS */ - vuint32_t MBFEN:1; /* BCC */ - vuint32_t:2; - - vuint32_t LPRIO_EN:1; /* new in MPC563xM */ - vuint32_t AEN:1; /* new in MPC563xM */ - vuint32_t:2; - vuint32_t IDAM:2; /* new in MPC563xM */ - vuint32_t:2; - - vuint32_t MAXMB:6; - } B; - } MCR; /* Module Configuration Register */ - - union { - vuint32_t R; - struct { - vuint32_t PRESDIV:8; - vuint32_t RJW:2; - vuint32_t PSEG1:3; - vuint32_t PSEG2:3; - vuint32_t BOFFMSK:1; /* BOFF_MSK */ - vuint32_t ERRMSK:1; /* ERR_MSK */ - vuint32_t CLKSRC:1; /* CLK_SRC */ - vuint32_t LPB:1; - vuint32_t TWRNMSK:1; /* TWRN_MSK */ - vuint32_t RWRNMSK:1; /* RWRN_MSK */ - vuint32_t:2; - vuint32_t SMP:1; - vuint32_t BOFFREC:1; /* BOFF_REC */ - vuint32_t TSYN:1; - vuint32_t LBUF:1; - vuint32_t LOM:1; - vuint32_t PROPSEG:3; - } B; /* Control Register */ - } CR; /* CTRL */ - - union { - vuint32_t R; - } TIMER; /* Free Running Timer */ - - int32_t FLEXCAN_reserved00; - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t MI:29; - } B; - } RXGMASK; /* RX Global Mask */ - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t MI:29; - } B; - } RX14MASK; /* RX 14 Mask */ - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t MI:29; - } B; - } RX15MASK; /* RX 15 Mask */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t RXECNT:8; - vuint32_t TXECNT:8; - } B; - } ECR; /* Error Counter Register */ - - union { - vuint32_t R; - struct { - vuint32_t:14; - vuint32_t TWRNINT:1; /* TWRN_INT */ - vuint32_t RWRNINT:1; /* RWRN_INT */ - vuint32_t BIT1ERR:1; /* BIT1_ERR */ - vuint32_t BIT0ERR:1; /* BIT0_ERR */ - vuint32_t ACKERR:1; /* ACK_ERR */ - vuint32_t CRCERR:1; /* CRC_ERR */ - vuint32_t FRMERR:1; /* FRM_ERR */ - vuint32_t STFERR:1; /* STF_ERR */ - vuint32_t TXWRN:1; /* TX_WRN */ - vuint32_t RXWRN:1; /* RX_WRN */ - vuint32_t IDLE:1; - vuint32_t TXRX:1; - vuint32_t FLTCONF:2; /* FLT_CONF */ - vuint32_t:1; - vuint32_t BOFFINT:1; /* BOFF_INT */ - vuint32_t ERRINT:1; /* ERR_INT */ - vuint32_t WAK_INT:1; /* new in MPC563xM */ - } B; - } ESR; /* Error and Status Register */ - - union { - vuint32_t R; - struct { - vuint32_t BUF63M:1; - vuint32_t BUF62M:1; - vuint32_t BUF61M:1; - vuint32_t BUF60M:1; - vuint32_t BUF59M:1; - vuint32_t BUF58M:1; - vuint32_t BUF57M:1; - vuint32_t BUF56M:1; - vuint32_t BUF55M:1; - vuint32_t BUF54M:1; - vuint32_t BUF53M:1; - vuint32_t BUF52M:1; - vuint32_t BUF51M:1; - vuint32_t BUF50M:1; - vuint32_t BUF49M:1; - vuint32_t BUF48M:1; - vuint32_t BUF47M:1; - vuint32_t BUF46M:1; - vuint32_t BUF45M:1; - vuint32_t BUF44M:1; - vuint32_t BUF43M:1; - vuint32_t BUF42M:1; - vuint32_t BUF41M:1; - vuint32_t BUF40M:1; - vuint32_t BUF39M:1; - vuint32_t BUF38M:1; - vuint32_t BUF37M:1; - vuint32_t BUF36M:1; - vuint32_t BUF35M:1; - vuint32_t BUF34M:1; - vuint32_t BUF33M:1; - vuint32_t BUF32M:1; - } B; /* Interruput Masks Register */ - } IMRH; /* IMASK2 */ - - union { - vuint32_t R; - struct { - vuint32_t BUF31M:1; - vuint32_t BUF30M:1; - vuint32_t BUF29M:1; - vuint32_t BUF28M:1; - vuint32_t BUF27M:1; - vuint32_t BUF26M:1; - vuint32_t BUF25M:1; - vuint32_t BUF24M:1; - vuint32_t BUF23M:1; - vuint32_t BUF22M:1; - vuint32_t BUF21M:1; - vuint32_t BUF20M:1; - vuint32_t BUF19M:1; - vuint32_t BUF18M:1; - vuint32_t BUF17M:1; - vuint32_t BUF16M:1; - vuint32_t BUF15M:1; - vuint32_t BUF14M:1; - vuint32_t BUF13M:1; - vuint32_t BUF12M:1; - vuint32_t BUF11M:1; - vuint32_t BUF10M:1; - vuint32_t BUF09M:1; - vuint32_t BUF08M:1; - vuint32_t BUF07M:1; - vuint32_t BUF06M:1; - vuint32_t BUF05M:1; - vuint32_t BUF04M:1; - vuint32_t BUF03M:1; - vuint32_t BUF02M:1; - vuint32_t BUF01M:1; - vuint32_t BUF00M:1; - } B; /* Interruput Masks Register */ - } IMRL; /* IMASK1 */ - - union { - vuint32_t R; - struct { - vuint32_t BUF63I:1; - vuint32_t BUF62I:1; - vuint32_t BUF61I:1; - vuint32_t BUF60I:1; - vuint32_t BUF59I:1; - vuint32_t BUF58I:1; - vuint32_t BUF57I:1; - vuint32_t BUF56I:1; - vuint32_t BUF55I:1; - vuint32_t BUF54I:1; - vuint32_t BUF53I:1; - vuint32_t BUF52I:1; - vuint32_t BUF51I:1; - vuint32_t BUF50I:1; - vuint32_t BUF49I:1; - vuint32_t BUF48I:1; - vuint32_t BUF47I:1; - vuint32_t BUF46I:1; - vuint32_t BUF45I:1; - vuint32_t BUF44I:1; - vuint32_t BUF43I:1; - vuint32_t BUF42I:1; - vuint32_t BUF41I:1; - vuint32_t BUF40I:1; - vuint32_t BUF39I:1; - vuint32_t BUF38I:1; - vuint32_t BUF37I:1; - vuint32_t BUF36I:1; - vuint32_t BUF35I:1; - vuint32_t BUF34I:1; - vuint32_t BUF33I:1; - vuint32_t BUF32I:1; - } B; /* Interruput Flag Register */ - } IFRH; /* IFLAG2 */ - - union { - vuint32_t R; - struct { - vuint32_t BUF31I:1; - vuint32_t BUF30I:1; - vuint32_t BUF29I:1; - vuint32_t BUF28I:1; - vuint32_t BUF27I:1; - vuint32_t BUF26I:1; - vuint32_t BUF25I:1; - vuint32_t BUF24I:1; - vuint32_t BUF23I:1; - vuint32_t BUF22I:1; - vuint32_t BUF21I:1; - vuint32_t BUF20I:1; - vuint32_t BUF19I:1; - vuint32_t BUF18I:1; - vuint32_t BUF17I:1; - vuint32_t BUF16I:1; - vuint32_t BUF15I:1; - vuint32_t BUF14I:1; - vuint32_t BUF13I:1; - vuint32_t BUF12I:1; - vuint32_t BUF11I:1; - vuint32_t BUF10I:1; - vuint32_t BUF09I:1; - vuint32_t BUF08I:1; - vuint32_t BUF07I:1; - vuint32_t BUF06I:1; - vuint32_t BUF05I:1; - vuint32_t BUF04I:1; - vuint32_t BUF03I:1; - vuint32_t BUF02I:1; - vuint32_t BUF01I:1; - vuint32_t BUF00I:1; - } B; /* Interruput Flag Register */ - } IFRL; /* IFLAG1 */ - - uint32_t flexcan2_reserved2[19]; - -/****************************************************************************/ -/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ -/****************************************************************************/ - /* Standard Buffer Structure */ - struct FLEXCAN_BUF_t BUF[64]; - - /* RX FIFO and Buffer Structure *//* New options in MPC563xM */ - /*struct FLEXCAN_RXFIFO_t RXFIFO; */ - /*struct FLEXCAN_BUF_t BUF[56]; */ -/****************************************************************************/ - - uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 *//* (New in MPC563xM) Address Base + 0x0034 */ - - union { - vuint32_t R; - struct { - vuint32_t MI:32; - } B; /* RX Individual Mask Registers */ - } RXIMR[64]; /* (New in MPC563xM) Address Base + 0x0880 */ - - }; /* end of FLEXCAN_tag */ -/****************************************************************************/ -/* MODULE : Decimation Filter (DECFIL) */ -/****************************************************************************/ - struct DECFIL_tag { - union { - vuint32_t R; - struct { - vuint32_t MDIS:1; - vuint32_t FREN:1; - vuint32_t:1; - vuint32_t FRZ:1; - vuint32_t SRES:1; - vuint32_t:2; /* CASCD not supported in MPC563xM */ - vuint32_t IDEN:1; - vuint32_t ODEN:1; - vuint32_t ERREN:1; - vuint32_t:1; - vuint32_t FTYPE:2; - vuint32_t:1; - vuint32_t SCAL:2; - vuint32_t:1; - vuint32_t SAT:1; - vuint32_t ISEL:1; - vuint32_t:1; /* MIXM does not appear to be implemented on the MPC563xM */ - vuint32_t DEC_RATE:4; - vuint32_t:1; /* SDIE not supported in MPC563xM */ - vuint32_t DSEL:1; - vuint32_t IBIE:1; - vuint32_t OBIE:1; - vuint32_t EDME:1; - vuint32_t TORE:1; - vuint32_t TMODE:2; /* the LSB of TMODE is always 0 on the MPC563xM */ - } B; - } MCR; /* Configuration Register DECFILTER_MCR @baseaddress + 0x00 */ - - union { - vuint32_t R; - struct { - vuint32_t BSY:1; - vuint32_t:1; - vuint32_t DEC_COUNTER:4; - vuint32_t IDFC:1; - vuint32_t ODFC:1; - vuint32_t SDFC:1; /* SDFC not supported in MPC563xM */ - vuint32_t IBIC:1; - vuint32_t OBIC:1; - vuint32_t SVRC:1; /* SVRC not supported in MPC563xM */ - vuint32_t DIVRC:1; - vuint32_t OVFC:1; - vuint32_t OVRC:1; - vuint32_t IVRC:1; - vuint32_t:6; - vuint32_t IDF:1; - vuint32_t ODF:1; - vuint32_t SDF:1; /* SDF not supported in MPC563xM */ - vuint32_t IBIF:1; - vuint32_t OBIF:1; - vuint32_t SVR:1; /* SVR not supported in MPC563xM */ - vuint32_t DIVR:1; - vuint32_t OVF:1; - vuint32_t OVR:1; - vuint32_t IVR:1; - } B; - } MSR; /* Status Register DECFILTER_MSR @baseaddress + 0x04 */ - - /* Module Extended Config.Register - not siupported on the MPC563xM DECFILTER_MXCR @baseaddress + 0x08 */ - - uint32_t decfil_reserved1[2]; - - union { - vuint32_t R; - struct { - vuint32_t:4; - vuint32_t INTAG:4; - vuint32_t:6; - vuint32_t PREFILL:1; - vuint32_t FLUSH:1; - vuint32_t INPBUF:16; - } B; - } IB; /* Interface Input Buffer DECFILTER_IB @baseaddress + 0x10 */ - - union { - vuint32_t R; - struct { - vuint32_t:12; - vuint32_t OUTTAG:4; - vuint32_t OUTBUF:16; - } B; - } OB; /* Interface Output Buffer DECFILTER_OB @baseaddress + 0x14 */ - - uint32_t decfil_reserved2[2]; - - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t COEF:24; - } B; - } COEF[9]; /* Filter Coefficient Registers DECFILTER_COEFx @baseaddress + 0x20 - 0x40 */ - - uint32_t decfil_reserved3[13]; - - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t TAP:24; - } B; - } TAP[8]; /* Filter TAP Registers DECFILTER_TAPx @baseaddress + 0x78 - 0x94 */ - - uint32_t decfil_reserved4[14]; - - /* 0x0D0 */ - union { - vuint16_t R; - struct { - vuint32_t:16; - vuint32_t SAMP_DATA:16; - } B; - } EDID; /* Filter EDID Registers DECFILTER_EDID @baseaddress + 0xD0 */ - - uint32_t decfil_reserved5[3]; - - /* 0x0E0 */ - uint32_t decfil_reserved6; - /* Filter FINTVAL Registers - Not supported on MPC563xM DECFILTER_FINTVAL @baseaddress + 0xE0 */ - - /* 0x0E4 */ - uint32_t decfil_reserved7; - /* Filter FINTCNT Registers - Not supported on MPC563xM DECFILTER_FINTCNT @baseaddress + 0xE4 */ - - /* 0x0E8 */ - uint32_t decfil_reserved8; - /* Filter CINTVAL Registers - Not supported on MPC563xM DECFILTER_CINTVAL @baseaddress + 0xE8 */ - - /* 0x0EC */ - uint32_t decfil_reserved9; - /* Filter CINTCNT Registers - Not supported on MPC563xM DECFILTER_CINTCNT @baseaddress + 0xEC */ - - }; -/****************************************************************************/ -/* MODULE : Periodic Interval Timer (PIT) */ -/****************************************************************************/ - struct PIT_tag { - - union { - vuint32_t R; - struct { - vuint32_t:29; - vuint32_t MDIS_RTI:1; - vuint32_t MDIS:1; - vuint32_t FRZ:1; - } B; - } PITMCR; /* PIT Module Control Register */ - - uint32_t pit_reserved1[59]; - - struct { - union { - vuint32_t R; /* TSVn */ - } LDVAL; /* Timer Load Value Register */ - - union { - vuint32_t R; /* TVLn */ - } CVAL; /* Current Timer Value Register */ - - union { - vuint32_t R; - struct { - vuint32_t:30; - vuint32_t TIE:1; - vuint32_t TEN:1; - } B; - } TCTRL; /* Timer Control Register */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t TIF:1; - } B; - } TFLG; /* Timer Flag Register */ - } RTI; /* RTI Channel */ - - struct { - union { - vuint32_t R; - } LDVAL; /* Timer Load Value Register */ - - union { - vuint32_t R; - } CVAL; /* Current Timer Value Register */ - - union { - vuint32_t R; - struct { - vuint32_t:30; - vuint32_t TIE:1; - vuint32_t TEN:1; - } B; - } TCTRL; /* Timer Control Register */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t TIF:1; - } B; - } TFLG; /* Timer Flag Register */ - } TIMER[4]; /* Timer Channels */ - - }; -/****************************************************************************/ -/* MODULE : System Timer Module (STM) */ -/****************************************************************************/ - struct STM_tag { - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t CPS:8; - vuint32_t:6; - vuint32_t FRZ:1; - vuint32_t TEN:1; - } B; - } CR; /* STM Control Register STM_CR (new in MPC563xM) Offset 0x0000 */ - - union { - vuint32_t R; - } CNT; /* STM Count Register STM_CNT (new in MPC563xM) Offset Offset 0x0004 */ - - uint32_t stm_reserved1[2]; /* Reserved (new in MPC563xM) Offset Offset 0x0008 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CEN:1; - } B; - } CCR0; /* STM Channel Control Register STM_CCR0 (new in MPC563xM) Offset 0x0010 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CIF:1; - } B; - } CIR0; /* STM Channel Interrupt Register STM_CIR0 (new in MPC563xM) Offset 0x0014 */ - - union { - vuint32_t R; - } CMP0; /* STM Channel Compare Register STM_CMP0 (new in MPC563xM) Offset Offset 0x0018 */ - - uint32_t stm_reserved2; /* Reserved (new in MPC563xM) Offset Offset 0x001C */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CEN:1; - } B; - } CCR1; /* STM Channel Control Register STM_CCR1 (new in MPC563xM) Offset 0x0020 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CIF:1; - } B; - } CIR1; /* STM Channel Interrupt Register STM_CIR1 (new in MPC563xM) Offset 0x0024 */ - - union { - vuint32_t R; - } CMP1; /* STM Channel Compare Register STM_CMP1 (new in MPC563xM) Offset Offset 0x0028 */ - - uint32_t stm_reserved3; /* Reserved (new in MPC563xM) Offset Offset 0x002C */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CEN:1; - } B; - } CCR2; /* STM Channel Control Register STM_CCR2 (new in MPC563xM) Offset 0x0030 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CIF:1; - } B; - } CIR2; /* STM Channel Interrupt Register STM_CIR2 (new in MPC563xM) Offset 0x0034 */ - - union { - vuint32_t R; - } CMP2; /* STM Channel Compare Register STM_CMP2 (new in MPC563xM) Offset Offset 0x0038 */ - - uint32_t stm_reserved4; /* Reserved (new in MPC563xM) Offset Offset 0x003C */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CEN:1; - } B; - } CCR3; /* STM Channel Control Register STM_CCR3 (new in MPC563xM) Offset 0x0040 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CIF:1; - } B; - } CIR3; /* STM Channel Interrupt Register STM_CIR3 (new in MPC563xM) Offset 0x0044 */ - - union { - vuint32_t R; - } CMP3; /* STM Channel Compare Register STM_CMP3 (new in MPC563xM) Offset Offset 0x0048 */ - - uint32_t stm_reserved5; /* Reserved (new in MPC563xM) Offset Offset 0x004C */ - }; - -/****************************************************************************/ -/* MODULE : SWT */ -/****************************************************************************/ - - struct SWT_tag { - union { - vuint32_t R; - struct { - vuint32_t MAP0:1; - vuint32_t MAP1:1; - vuint32_t MAP2:1; - vuint32_t MAP3:1; - vuint32_t MAP4:1; - vuint32_t MAP5:1; - vuint32_t MAP6:1; - vuint32_t MAP7:1; - vuint32_t:14; - vuint32_t KEY:1; - vuint32_t RIA:1; - vuint32_t WND:1; - vuint32_t ITR:1; - vuint32_t HLK:1; - vuint32_t SLK:1; - vuint32_t CSL:1; - vuint32_t STP:1; - vuint32_t FRZ:1; - vuint32_t WEN:1; - } B; - } MCR; /*SWT_CR *//* Module Configuration Register */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t TIF:1; - } B; - } IR; /* Interrupt register SWT_IR */ - - union { - vuint32_t R; - struct { - vuint32_t WTO:32; - } B; - } TO; /* Timeout register SWT_TO */ - - union { - vuint32_t R; - struct { - vuint32_t WST:32; - - } B; - } WN; /* Window register SWT_WN */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t WSC:16; - } B; - } SR; /* Service register SWT_SR */ - - union { - vuint32_t R; - struct { - vuint32_t CNT:32; - } B; - } CO; /* Counter output register SWT_CO */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t SK:16; - } B; - } SK; /* Service key register SWT_SK */ - }; -/****************************************************************************/ -/* MODULE : Power Management Controller (PMC) */ -/****************************************************************************/ - struct PMC_tag { - union { - vuint32_t R; - struct { - vuint32_t LVRER:1; /* LVIRR */ - vuint32_t LVREH:1; /* LVIHR */ - vuint32_t LVRE50:1; /* LVI5R */ - vuint32_t LVRE33:1; /* LVI3R */ - vuint32_t LVREC:1; /* LVI1R */ - vuint32_t:3; - vuint32_t LVIER:1; /* LVIRE */ - vuint32_t LVIEH:1; /* LVIHE */ - vuint32_t LVIE50:1; /* LVI5E */ - vuint32_t LVIE33:1; /* LVI3E */ - vuint32_t LVIC:1; /* LVI1E */ - vuint32_t:2; - vuint32_t TLK:1; - vuint32_t:16; - } B; - } MCR; /* Module Configuration register CFGR */ - - union { - vuint32_t R; - struct { - vuint32_t:12; - vuint32_t LVDREGTRIM:4; /* LVI50TRIM */ - vuint32_t VDD33TRIM:4; /* BV33TRIM */ - vuint32_t LVD33TRIM:4; /* LVI33TRIM */ - vuint32_t VDDCTRIM:4; /* V12TRIM */ - vuint32_t LVDCTRIM:4; /* LVI33TRIM */ - } B; - } TRIMR; /* Trimming register */ - - union { - vuint32_t R; - struct { - vuint32_t:5; - vuint32_t LVFVSTBY:1; - vuint32_t BGRDY:1; /* BGS1 */ - vuint32_t BGTS:1; /* BGS2 */ - vuint32_t:5; - vuint32_t LVFCSTBY:1; - vuint32_t:1; - vuint32_t V33DIS:1; /* 3.3V Regulator Disable V33S */ - vuint32_t LVFCR:1; /* Clear LVFR LVIRC */ - vuint32_t LVFCH:1; /* Clear LVFH LVIHC */ - vuint32_t LVFC50:1; /* Clear LVF5 LVI5 */ - vuint32_t LVFC33:1; /* Clear LVF3 LVI3 */ - vuint32_t LVFCC:1; /* Clear LVFC LVI1 */ - vuint32_t:3; - vuint32_t LVFR:1; /* Low Voltage Flag Reset Supply LVIRF */ - vuint32_t LVFH:1; /* Low Voltage Flag VDDEH Supply LVIHF */ - vuint32_t LVF50:1; /* Low Voltage Flag 5V Supply LVI5F */ - vuint32_t LVF33:1; /* Low Voltage Flag 3.3V Supply LVI3F */ - vuint32_t LVFC:1; /* Low Voltage Flag Core (1.2V) LVI1F */ - vuint32_t:3; - - } B; - } SR; /* status register */ - }; -/****************************************************************************/ -/* MODULE : TSENS (Temperature Sensor) */ -/****************************************************************************/ - - struct TSENS_tag { - - union { - vuint32_t R; - struct { - vuint32_t TSCV2:16; - vuint32_t TSCV1:16; - } B; - } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t TSCV3:16; - } B; - } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */ - - uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */ - - }; - -/* Define memories */ -/* Comments need to be moved for different memory sizes */ - -#define SRAM_START 0x40000000 - /*#define SRAM_SIZE 0xC000 48K SRAM */ - /*#define SRAM_SIZE 0x10000 64K SRAM */ -#define SRAM_SIZE 0x17800 /* 94K SRAM */ - /*#define SRAM_END 0x4000BFFF 48K SRAM */ - /*#define SRAM_END 0x4000FFFF 64K SRAM */ -#define SRAM_END 0x400177FF /* 94K SRAM */ - -#define FLASH_START 0x0 - /*#define FLASH_SIZE 0x100000 1M Flash */ -#define FLASH_SIZE 0x180000 /* 1.5M Flash */ - /*#define FLASH_END 0xFFFFF 1M Flash */ -#define FLASH_END 0x17FFFF /* 1.5M Flash */ - -/* Shadow Flash start and end address */ -#define FLASH_SHADOW_START 0x00FFC000 -#define FLASH_SHADOW_SIZE 0x4000 -#define FLASH_SHADOW_END 0x00FFFFFF - -/* Define instances of modules */ -#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) -#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) -#define CFLASH0 (*( volatile struct FLASH_tag *) 0xC3F88000) -#define CFLASH1 (*( volatile struct FLASH_tag *) 0xC3FB0000) -#define CFLASH2 (*( volatile struct FLASH_tag *) 0xC3FB4000) -#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) - -#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) -#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) -#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) -#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) -#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) -#define ETPU_DATA_RAM_END 0xC3FC8BFC -#define CODE_RAM (*( uint32_t *) 0xC3FD0000) -#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) -#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) - -#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) -#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) -#define STM (*( volatile struct STM_tag *) 0xFFF3C000) -#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) -#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000) -#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) - -#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000) -#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000) - -#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) -#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) - -#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) -#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006) -#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) -#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006) - -#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) -#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) - -#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) - -#ifdef __MWERKS__ -#pragma pop -#endif /* - */ - -#ifdef __cplusplus -} -#endif /* - */ - -#endif /* ifdef _MPC563M_H */ -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ - diff --git a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/SPC56x/platform.dox deleted file mode 100644 index baab477..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/platform.dox +++ /dev/null @@ -1,48 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup SPC563_DRIVERS SPC563 Drivers - * @brief Device drivers included in the SPC563 support. - * - * @ingroup PPC - */ - -/** - * @defgroup SPC563_HAL SPC563 HAL Support - * @brief HAL support. - * - * @ingroup SPC563_DRIVERS - */ - -/** - * @defgroup SPC563_SERIAL SPC563 ESCI Support - * @brief ESCI support. - * @details The serial driver supports both the SPC563 ESCIs in asynchronous - * mode. - * - * @ingroup SPC563_DRIVERS - */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/SPC56x/platform.mk deleted file mode 100644 index e7bf2d4..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/platform.mk +++ /dev/null @@ -1,6 +0,0 @@ -# List of all the SPC56x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56x/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/SPC56x/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56x diff --git a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/SPC56x/serial_lld.c deleted file mode 100644 index c98821e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/serial_lld.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file SPC56x/serial_lld.c - * @brief SPC563 low level serial driver code. - * - * @addtogroup SPC563_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief eSCI-A serial driver identifier. - */ -#if USE_SPC563_ESCIA || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** - * @brief eSCI-B serial driver identifier. - */ -#if USE_SPC563_ESCIB || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static const SerialConfig default_config = { - SERIAL_DEFAULT_BITRATE, - SD_MODE_NORMAL | SD_MODE_PARITY_NONE -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief eSCI initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration - */ -static void esci_init(SerialDriver *sdp, const SerialConfig *config) { - volatile struct ESCI_tag *escip = sdp->escip; - uint8_t mode = config->sc_mode; - - escip->CR2.R = 0; /* MDIS off. */ - escip->CR1.R = 0; - escip->LCR.R = 0; - escip->CR1.B.SBR = SPC563_SYSCLK / (16 * config->sc_speed); - if (mode & SD_MODE_LOOPBACK) - escip->CR1.B.LOOPS = 1; - switch (mode & SD_MODE_PARITY) { - case SD_MODE_PARITY_ODD: - escip->CR1.B.PT = 1; - case SD_MODE_PARITY_EVEN: - escip->CR1.B.PE = 1; - escip->CR1.B.M = 1; /* Makes it 8 bits data + 1 bit parity. */ - default: - ; - } - escip->LPR.R = 0; - escip->CR1.R |= 0x0000002C; /* RIE, TE, RE to 1. */ - escip->CR2.R |= 0x000F; /* ORIE, NFIE, FEIE, PFIE to 1. */ -} - -/** - * @brief eSCI de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] escip pointer to an eSCI I/O block - */ -static void esci_deinit(volatile struct ESCI_tag *escip) { - - escip->LPR.R = 0; - escip->SR.R = 0xFFFFFFFF; - escip->CR1.R = 0; - escip->CR2.R = 0x8000; /* MDIS on. */ -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] sr eSCI SR register value - */ -static void set_error(SerialDriver *sdp, uint32_t sr) { - sdflags_t sts = 0; - - if (sr & 0x08000000) - sts |= SD_OVERRUN_ERROR; - if (sr & 0x04000000) - sts |= SD_NOISE_ERROR; - if (sr & 0x02000000) - sts |= SD_FRAMING_ERROR; - if (sr & 0x01000000) - sts |= SD_PARITY_ERROR; -/* if (sr & 0x00000000) - sts |= SD_BREAK_DETECTED;*/ - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -/** - * @brief Common IRQ handler. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -static void serve_interrupt(SerialDriver *sdp) { - volatile struct ESCI_tag *escip = sdp->escip; - - uint32_t sr = escip->SR.R; - escip->SR.R = 0x3FFFFFFF; /* Does not clear TDRE | TC.*/ - if (sr & 0x0F000000) /* OR | NF | FE | PF. */ - set_error(sdp, sr); - if (sr & 0x20000000) { /* RDRF. */ - chSysLockFromIsr(); - sdIncomingDataI(sdp, escip->DR.B.D); - chSysUnlockFromIsr(); - } - if (escip->CR1.B.TIE && (sr & 0x80000000)) { /* TDRE. */ - msg_t b; - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chEvtBroadcastI(&sdp->oevent); - escip->CR1.B.TIE = 0; - } - else { - ESCI_A.SR.B.TDRE = 1; - escip->DR.R = (uint16_t)b; - } - chSysUnlockFromIsr(); - } -} - -#if USE_SPC563_ESCIA || defined(__DOXYGEN__) -static void notify1(void) { - - if (ESCI_A.SR.B.TDRE) { - msg_t b = sdRequestDataI(&SD1); - if (b != Q_EMPTY) { - ESCI_A.SR.B.TDRE = 1; - ESCI_A.CR1.B.TIE = 1; - ESCI_A.DR.R = (uint16_t)b; - } - } -/* if (!ESCI_A.CR1.B.TIE) { - msg_t b = sdRequestDataI(&SD1); - if (b != Q_EMPTY) { - ESCI_A.CR1.B.TIE = 1; - ESCI_A.DR.R = (uint16_t)b; - } - }*/ -} -#endif - -#if USE_SPC563_ESCIB || defined(__DOXYGEN__) -static void notify2(void) { - - if (ESCI_B.SR.B.TDRE) { - msg_t b = sdRequestDataI(&SD2); - if (b != Q_EMPTY) { - ESCI_B.SR.B.TDRE = 1; - ESCI_B.CR1.B.TIE = 1; - ESCI_B.DR.R = (uint16_t)b; - } - } -/* if (!ESCI_B.CR1.B.TIE) { - msg_t b = sdRequestDataI(&SD2); - if (b != Q_EMPTY) { - ESCI_B.CR1.B.TIE = 1; - ESCI_B.DR.R = (uint16_t)b; - } - }*/ -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_SPC563_ESCIA || defined(__DOXYGEN__) -/** - * @brief eSCI-A interrupt handler. - */ -CH_IRQ_HANDLER(vector146) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if USE_SPC563_ESCIB || defined(__DOXYGEN__) -/** - * @brief eSCI-B interrupt handler. - */ -CH_IRQ_HANDLER(vector149) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD2); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_SPC563_ESCIA - sdObjectInit(&SD1, NULL, notify1); - SD1.escip = &ESCI_A; - ESCI_A.CR2.R = 0x8000; /* MDIS ON. */ - INTC.PSR[146].R = SPC563_ESCIA_PRIORITY; -#endif - -#if USE_SPC563_ESCIB - sdObjectInit(&SD2, NULL, notify2); - SD2.escip = &ESCI_B; - ESCI_B.CR2.R = 0x8000; /* MDIS ON. */ - INTC.PSR[149].R = SPC563_ESCIB_PRIORITY; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - esci_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) - esci_deinit(sdp->escip); -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/SPC56x/serial_lld.h deleted file mode 100644 index 80dbd52..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/serial_lld.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file SPC56x/serial_lld.h - * @brief SPC563 low level serial driver header. - * - * @addtogroup SPC563_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define SD_MODE_PARITY 0x03 /**< @brief Parity field mask. */ -#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ -#define SD_MODE_PARITY_EVEN 0x01 /**< @brief Even parity. */ -#define SD_MODE_PARITY_ODD 0x02 /**< @brief Odd parity. */ - -#define SD_MODE_NORMAL 0x00 /**< @brief Normal operations. */ -#define SD_MODE_LOOPBACK 0x80 /**< @brief Internal loopback. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief eSCI-A driver enable switch. - * @details If set to @p TRUE the support for eSCI-A is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SPC563_ESCIA) || defined(__DOXYGEN__) -#define USE_SPC563_ESCIA TRUE -#endif - -/** - * @brief eSCI-B driver enable switch. - * @details If set to @p TRUE the support for eSCI-B is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SPC563_ESCIB) || defined(__DOXYGEN__) -#define USE_SPC563_ESCIB TRUE -#endif - -/** - * @brief eSCI-A interrupt priority level setting. - */ -#if !defined(SPC563_ESCIA_PRIORITY) || defined(__DOXYGEN__) -#define SPC563_ESCIA_PRIORITY 8 -#endif - -/** - * @brief eSCI-B interrupt priority level setting. - */ -#if !defined(SPC563_ESCIB_PRIORITY) || defined(__DOXYGEN__) -#define SPC563_ESCIB_PRIORITY 8 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint8_t sdflags_t; - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /** - * @brief Mode flags. - */ - uint8_t sc_mode; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the volatile eSCI registers block.*/ \ - volatile struct ESCI_tag *escip; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_SPC563_ESCIA && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_SPC563_ESCIB && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/typedefs.h b/ChibiOS_2.0.8/os/hal/platforms/SPC56x/typedefs.h deleted file mode 100644 index 122d9c7..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/SPC56x/typedefs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file SPC56x/typedefs.h - * @brief Dummy typedefs file. - */ - -#ifndef _TYPEDEFS_H_ -#define _TYPEDEFS_H_ - -#include "chtypes.h" - -#endif /* _TYPEDEFS_H_ */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/adc_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM32/adc_lld.c deleted file mode 100644 index 7a1825e..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/adc_lld.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/adc_lld.c - * @brief STM32 ADC subsystem low level driver source. - * @addtogroup STM32_ADC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if USE_STM32_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_STM32_ADC1 || defined(__DOXYGEN__) -/** - * @brief ADC1 DMA interrupt handler (channel 1). - */ -CH_IRQ_HANDLER(Vector6C) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = DMA1->ISR; - DMA1->IFCR |= DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 | - DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1; - if ((isr & DMA_ISR_HTIF1) != 0) { - /* Half transfer processing.*/ - if (ADCD1.ad_callback != NULL) { - /* Invokes the callback passing the 1st half of the buffer.*/ - ADCD1.ad_callback(ADCD1.ad_samples, ADCD1.ad_depth / 2); - } - } - if ((isr & DMA_ISR_TCIF1) != 0) { - /* Transfer complete processing.*/ - if (!ADCD1.ad_grpp->acg_circular) { - /* End conversion.*/ - adc_lld_stop_conversion(&ADCD1); - ADCD1.ad_grpp = NULL; - ADCD1.ad_state = ADC_COMPLETE; - chSysLockFromIsr(); - chSemResetI(&ADCD1.ad_sem, 0); - chSysUnlockFromIsr(); - } - /* Callback handling.*/ - if (ADCD1.ad_callback != NULL) { - if (ADCD1.ad_depth > 1) { - /* Invokes the callback passing the 2nd half of the buffer.*/ - size_t half = ADCD1.ad_depth / 2; - ADCD1.ad_callback(ADCD1.ad_samples + half, half); - } - else { - /* Invokes the callback passing the whole buffer.*/ - ADCD1.ad_callback(ADCD1.ad_samples, ADCD1.ad_depth); - } - } - } - if ((isr & DMA_ISR_TEIF1) != 0) { - /* DMA error processing.*/ - STM32_ADC1_DMA_ERROR_HOOK(); - } - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - */ -void adc_lld_init(void) { - -#if USE_STM32_ADC1 - /* ADC reset, ensures reset state in order to avoid trouble with JTAGs.*/ - RCC->APB2RSTR = RCC_APB2RSTR_ADC1RST; - RCC->APB2RSTR = 0; - - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.ad_adc = ADC1; - ADCD1.ad_dma = DMA1_Channel1; - ADCD1.ad_dmaprio = STM32_ADC1_DMA_PRIORITY << 12; - - /* Temporary activation.*/ - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; - ADC1->CR1 = 0; - ADC1->CR2 = ADC_CR2_ADON; - - /* Reset calibration just to be safe.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; - while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) - ; - - /* Calibration.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; - while ((ADC1->CR2 & ADC_CR2_CAL) != 0) - ; - - /* Return the ADC in low power mode.*/ - ADC1->CR2 = 0; - RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->ad_state == ADC_STOP) { -#if USE_STM32_ADC1 - if (&ADCD1 == adcp) { - dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/ - NVICEnableVector(DMA1_Channel1_IRQn, - CORTEX_PRIORITY_MASK(STM32_ADC1_IRQ_PRIORITY)); - DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR; - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; - } -#endif - - /* ADC setup, the calibration procedure has already been performed - during initialization.*/ - adcp->ad_adc->CR1 = ADC_CR1_SCAN; - adcp->ad_adc->CR2 = 0; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock.*/ - if (adcp->ad_state == ADC_READY) { -#if USE_STM32_ADC1 - if (&ADCD1 == adcp) { - ADC1->CR1 = 0; - ADC1->CR2 = 0; - NVICDisableVector(DMA1_Channel1_IRQn); - dmaDisable(DMA1_ID); - RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; - } -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t ccr, n; - const ADCConversionGroup *grpp = adcp->ad_grpp; - - /* DMA setup.*/ - adcp->ad_dma->CMAR = (uint32_t)adcp->ad_samples; - ccr = adcp->ad_dmaprio | DMA_CCR1_EN | DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0 | - DMA_CCR1_MINC | DMA_CCR1_TCIE | DMA_CCR1_TEIE; - if (grpp->acg_circular) - ccr |= DMA_CCR1_CIRC; - if (adcp->ad_depth > 1) { - /* If the buffer depth is greater than one then the half transfer interrupt - interrupt is enabled in order to allows streaming processing.*/ - ccr |= DMA_CCR1_HTIE; - n = (uint32_t)grpp->acg_num_channels * (uint32_t)adcp->ad_depth; - } - else - n = (uint32_t)grpp->acg_num_channels; - adcp->ad_dma->CNDTR = n; - adcp->ad_dma->CCR = ccr; - - /* ADC setup.*/ - adcp->ad_adc->SMPR1 = grpp->acg_smpr1; - adcp->ad_adc->SMPR2 = grpp->acg_smpr2; - adcp->ad_adc->SQR1 = grpp->acg_sqr1; - adcp->ad_adc->SQR2 = grpp->acg_sqr2; - adcp->ad_adc->SQR3 = grpp->acg_sqr3; - adcp->ad_adc->CR1 = grpp->acg_cr1 | ADC_CR1_SCAN; - adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON; - - /* ADC start.*/ - adcp->ad_adc->CR2 |= ADC_CR2_SWSTART | ADC_CR2_EXTTRIG; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - adcp->ad_dma->CCR = 0; - adcp->ad_adc->CR2 = 0; -} - -#endif /* CH_HAL_USE_ADC */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/adc_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/adc_lld.h deleted file mode 100644 index d369b4a..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/adc_lld.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/adc_lld.h - * @brief STM32 ADC subsystem low level driver header. - * @addtogroup STM32_ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if CH_HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ -#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ - -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ -#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ -#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ -#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ -#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ -#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ -#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ -#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ -#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_ADC1) || defined(__DOXYGEN__) -#define USE_STM32_ADC1 TRUE -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC1_DMA_PRIORITY 3 -#endif - -/** - * @brief ADC1 interrupt priority level setting. - */ -#if !defined(STM32_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC1_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC1 DMA error hook. - * @note The default action for DMA errors is a system halt because DMA error - * can only happen because programming errors. - */ -#if !defined(STM32_ADC1_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief ADC notification callback type. - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(adcsample_t *buffer, size_t n); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool_t acg_circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t acg_num_channels; - /* End of the mandatory fields.*/ - /** - * @brief ADC CR1 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR1_SCAN that is enforced inside the driver. - */ - uint32_t acg_cr1; - /** - * @brief ADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA and @p ADC_CR2_ADON that are enforced inside the - * driver. - */ - uint32_t acg_cr2; - /** - * @brief ADC SMPR1 register initialization data. - */ - uint32_t acg_smpr1; - /** - * @brief ADC SMPR2 register initialization data. - */ - uint32_t acg_smpr2; - /** - * @brief ADC SQR1 register initialization data. - */ - uint32_t acg_sqr1; - /** - * @brief ADC SQR2 register initialization data. - */ - uint32_t acg_sqr2; - /** - * @brief ADC SQR3 register initialization data. - */ - uint32_t acg_sqr3; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /* * <---------- - * @brief ADC prescaler setting. - * @note This field can assume one of the following values: - * @p RCC_CFGR_ADCPRE_DIV2, @p RCC_CFGR_ADCPRE_DIV4, - * @p RCC_CFGR_ADCPRE_DIV6, @p RCC_CFGR_ADCPRE_DIV8. - */ -/* uint32_t ac_prescaler;*/ -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - adcstate_t ad_state; - /** - * @brief Current configuration data. - */ - const ADCConfig *ad_config; - /** - * @brief Synchronization semaphore. - */ - Semaphore ad_sem; - /** - * @brief Current callback function or @p NULL. - */ - adccallback_t ad_callback; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *ad_samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t ad_depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *ad_grpp; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *ad_adc; - /** - * @brief Pointer to the DMA channel registers block. - */ - DMA_Channel_TypeDef *ad_dma; - /** - * @brief DMA priority bit mask. - */ - uint32_t ad_dmaprio; -} ADCDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) - -#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ - -#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ - -#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ - -#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ -#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_STM32_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/can_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM32/can_lld.c deleted file mode 100644 index 2f6fdcf..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/can_lld.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/can_lld.c - * @brief STM32 CAN subsystem low level driver source. - * @addtogroup STM32_CAN - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if USE_STM32_CAN1 || defined(__DOXYGEN__) -CANDriver CAND1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/* - * CAN1 TX interrupt handler. - */ -CH_IRQ_HANDLER(Vector8C) { - - CH_IRQ_PROLOGUE(); - - /* No more events until a message is transmitted.*/ - CAN1->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2; - chSysLockFromIsr(); - while (chSemGetCounterI(&CAND1.cd_txsem) < 0) - chSemSignalI(&CAND1.cd_txsem); - chEvtBroadcastI(&CAND1.cd_txempty_event); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/* - * CAN1 RX0 interrupt handler. - */ -CH_IRQ_HANDLER(Vector90) { - uint32_t rf0r; - - CH_IRQ_PROLOGUE(); - - rf0r = CAN1->RF0R; - if ((rf0r & CAN_RF0R_FMP0) > 0) { - /* No more receive events until the queue 0 has been emptied.*/ - CAN1->IER &= ~CAN_IER_FMPIE0; - chSysLockFromIsr(); - while (chSemGetCounterI(&CAND1.cd_rxsem) < 0) - chSemSignalI(&CAND1.cd_rxsem); - chEvtBroadcastI(&CAND1.cd_rxfull_event); - chSysUnlockFromIsr(); - } - if ((rf0r & CAN_RF0R_FOVR0) > 0) { - /* Overflow events handling.*/ - CAN1->RF0R = CAN_RF0R_FOVR0; - canAddFlagsI(&CAND1, CAN_OVERFLOW_ERROR); - chSysLockFromIsr(); - chEvtBroadcastI(&CAND1.cd_error_event); - chSysUnlockFromIsr(); - } - - CH_IRQ_EPILOGUE(); -} - -/* - * CAN1 RX1 interrupt handler. - */ -CH_IRQ_HANDLER(Vector94) { - - CH_IRQ_PROLOGUE(); - - chSysHalt(); /* Not supported (yet).*/ - - CH_IRQ_EPILOGUE(); -} - -/* - * CAN1 SCE interrupt handler. - */ -CH_IRQ_HANDLER(Vector98) { - uint32_t msr; - - CH_IRQ_PROLOGUE(); - - msr = CAN1->MSR; - CAN1->MSR = CAN_MSR_ERRI | CAN_MSR_WKUI | CAN_MSR_SLAKI; - /* Wakeup event.*/ - if (msr & CAN_MSR_WKUI) { - chSysLockFromIsr(); - chEvtBroadcastI(&CAND1.cd_wakeup_event); - chSysUnlockFromIsr(); - } - /* Error event.*/ - if (msr & CAN_MSR_ERRI) { - canstatus_t flags; - uint32_t esr = CAN1->ESR; - - CAN1->ESR &= ~CAN_ESR_LEC; - flags = (canstatus_t)(esr & 7); - if ((esr & CAN_ESR_LEC) > 0) - flags |= CAN_FRAMING_ERROR; - chSysLockFromIsr(); - canAddFlagsI(&CAND1, flags); - chEvtBroadcastI(&CAND1.cd_error_event); - chSysUnlockFromIsr(); - } - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CAN driver initialization. - */ -void can_lld_init(void) { - -#if USE_STM32_CAN1 - /* CAN reset, ensures reset state in order to avoid trouble with JTAGs.*/ - RCC->APB1RSTR = RCC_APB1RSTR_CAN1RST; - RCC->APB1RSTR = 0; - - /* Driver initialization.*/ - canObjectInit(&CAND1); - CAND1.cd_can = CAN1; -#endif -} - -/** - * @brief Configures and activates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void can_lld_start(CANDriver *canp) { - - /* Clock activation.*/ -#if USE_STM32_CAN1 - if (&CAND1 == canp) { - NVICEnableVector(USB_HP_CAN1_TX_IRQn, - CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY)); - NVICEnableVector(USB_LP_CAN1_RX0_IRQn, - CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY)); - NVICEnableVector(CAN1_RX1_IRQn, - CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY)); - NVICEnableVector(CAN1_SCE_IRQn, - CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_CAN1EN; - } -#endif - - /* Entering initialization mode. */ - canp->cd_state = CAN_STARTING; - canp->cd_can->MCR = CAN_MCR_INRQ; - while ((canp->cd_can->MSR & CAN_MSR_INAK) == 0) - chThdSleepS(1); - /* BTR initialization.*/ - canp->cd_can->BTR = canp->cd_config->cc_btr; - /* MCR initialization.*/ - canp->cd_can->MCR = canp->cd_config->cc_mcr; - /* Filters initialization.*/ - canp->cd_can->FMR |= CAN_FMR_FINIT; - if (canp->cd_config->cc_num > 0) { - uint32_t i, fmask; - CAN_FilterRegister_TypeDef *cfp; - - canp->cd_can->FA1R = 0; - canp->cd_can->FM1R = 0; - canp->cd_can->FS1R = 0; - canp->cd_can->FFA1R = 0; - cfp = canp->cd_can->sFilterRegister; - fmask = 1; - for (i = 0; i < CAN_MAX_FILTERS; i++) { - if (i < canp->cd_config->cc_num) { - if (canp->cd_config->cc_filters[i].cf_mode) - canp->cd_can->FM1R |= fmask; - if (canp->cd_config->cc_filters[i].cf_scale) - canp->cd_can->FS1R |= fmask; - if (canp->cd_config->cc_filters[i].cf_assignment) - canp->cd_can->FFA1R |= fmask; - cfp->FR1 = canp->cd_config->cc_filters[i].cf_register1; - cfp->FR2 = canp->cd_config->cc_filters[i].cf_register2; - canp->cd_can->FA1R |= fmask; - } - else { - cfp->FR1 = 0; - cfp->FR2 = 0; - } - cfp++; - fmask <<= 1; - /* Gives a chance for preemption since this is a rather long loop.*/ - chSysUnlock(); - chThdYield(); - chSysLock(); - } - } - else { - /* Setup a default filter.*/ - canp->cd_can->sFilterRegister[0].FR1 = 0; - canp->cd_can->sFilterRegister[0].FR2 = 0; - canp->cd_can->FM1R = 0; - canp->cd_can->FFA1R = 0; - canp->cd_can->FS1R = 1; - canp->cd_can->FA1R = 1; - } - canp->cd_can->FMR &= ~CAN_FMR_FINIT; - /* Interrupt sources initialization.*/ - canp->cd_can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | - CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE | - CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE | - CAN_IER_FOVIE0 | CAN_IER_FOVIE1; -} - -/** - * @brief Deactivates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void can_lld_stop(CANDriver *canp) { - - /* If in ready state then disables the CAN peripheral.*/ - if (canp->cd_state == CAN_READY) { -#if USE_STM32_CAN1 - if (&CAND1 == canp) { - CAN1->MCR = 0x00010002; /* Register reset value. */ - CAN1->IER = 0x00000000; /* All sources disabled. */ - NVICDisableVector(USB_HP_CAN1_TX_IRQn); - NVICDisableVector(USB_LP_CAN1_RX0_IRQn); - NVICDisableVector(CAN1_RX1_IRQn); - NVICDisableVector(CAN1_SCE_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_CAN1EN; - } -#endif - } -} - -/** - * @brief Determines whether a frame can be transmitted. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - */ -bool_t can_lld_can_transmit(CANDriver *canp) { - - return (canp->cd_can->TSR & CAN_TSR_TME) != 0; -} - -/** - * @brief Inserts a frame into the transmit queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] ctfp pointer to the CAN frame to be transmitted - */ -void can_lld_transmit(CANDriver *canp, const CANTxFrame *ctfp) { - uint32_t tir; - CAN_TxMailBox_TypeDef *tmbp; - - /* Pointer to a free transmission mailbox.*/ - tmbp = &canp->cd_can->sTxMailBox[(canp->cd_can->TSR & CAN_TSR_CODE) >> 24]; - - /* Preparing the message.*/ - if (ctfp->cf_IDE) - tir = ((uint32_t)ctfp->cf_EID << 3) | ((uint32_t)ctfp->cf_RTR << 1) | - CAN_TI0R_IDE; - else - tir = ((uint32_t)ctfp->cf_SID << 21) | ((uint32_t)ctfp->cf_RTR << 1); - tmbp->TDTR = ctfp->cf_DLC; - tmbp->TDLR = ctfp->cf_data32[0]; - tmbp->TDHR = ctfp->cf_data32[1]; - tmbp->TIR = tir | CAN_TI0R_TXRQ; -} - -/** - * @brief Determines whether a frame has been received. - * - * @param[in] canp pointer to the @p CANDriver object - * - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - */ -bool_t can_lld_can_receive(CANDriver *canp) { - - return (canp->cd_can->RF0R & CAN_RF0R_FMP0) > 0; -} - -/** - * @brief Receives a frame from the input queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[out] crfp pointer to the buffer where the CAN frame is copied - */ -void can_lld_receive(CANDriver *canp, CANRxFrame *crfp) { - uint32_t r; - - /* Fetches the message.*/ - r = canp->cd_can->sFIFOMailBox[0].RIR; - crfp->cf_RTR = (r & CAN_RI0R_RTR) >> 1; - crfp->cf_IDE = (r & CAN_RI0R_IDE) >> 2; - if (crfp->cf_IDE) - crfp->cf_EID = r >> 3; - else - crfp->cf_SID = r >> 21; - r = canp->cd_can->sFIFOMailBox[0].RDTR; - crfp->cf_DLC = r & CAN_RDT0R_DLC; - crfp->cf_FMI = (uint8_t)(r >> 8); - crfp->cf_TIME = (uint16_t)(r >> 16); - crfp->cf_data32[0] = canp->cd_can->sFIFOMailBox[0].RDLR; - crfp->cf_data32[1] = canp->cd_can->sFIFOMailBox[0].RDHR; - - /* Releases the mailbox.*/ - canp->cd_can->RF0R = CAN_RF0R_RFOM0; - - /* If the queue is empty re-enables the interrupt in order to generate - events again.*/ - if ((canp->cd_can->RF0R & CAN_RF0R_FMP0) == 0) - canp->cd_can->IER |= CAN_IER_FMPIE0; -} - -#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) -/** - * @brief Enters the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void can_lld_sleep(CANDriver *canp) { - - canp->cd_can->MCR |= CAN_MCR_SLEEP; -} - -/** - * @brief Enforces leaving the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void can_lld_wakeup(CANDriver *canp) { - - canp->cd_can->MCR &= ~CAN_MCR_SLEEP; -} -#endif /* CAN_USE_SLEEP_MODE */ - -#endif /* CH_HAL_USE_CAN */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/can_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/can_lld.h deleted file mode 100644 index fcbc292..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/can_lld.h +++ /dev/null @@ -1,327 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/can_lld.h - * @brief STM32 CAN subsystem low level driver header. - * @addtogroup STM32_CAN - * @{ - */ - -#ifndef _CAN_LLD_H_ -#define _CAN_LLD_H_ - -#if CH_HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * The following macros from the ST header file are replaced with better - * equivalents. - */ -#undef CAN_BTR_BRP -#undef CAN_BTR_TS1 -#undef CAN_BTR_TS2 -#undef CAN_BTR_SJW - -/** - * @brief This switch defines whether the driver implementation supports - * a low power switch mode with automatic an wakeup feature. - */ -#define CAN_SUPPORTS_SLEEP TRUE - -/** - * @brief Minimum number of CAN filters. - */ -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) -#define CAN_MAX_FILTERS 28 -#else -#define CAN_MAX_FILTERS 14 -#endif - -#define CAN_BTR_BRP(n) (n) /**< @brief BRP field macro.*/ -#define CAN_BTR_TS1(n) ((n) << 16) /**< @brief TS1 field macro.*/ -#define CAN_BTR_TS2(n) ((n) << 20) /**< @brief TS2 field macro.*/ -#define CAN_BTR_SJW(n) ((n) << 24) /**< @brief SJW field macro.*/ - -#define CAN_IDE_STD 0 /**< @brief Standard id. */ -#define CAN_IDE_EXT 1 /**< @brief Extended id. */ - -#define CAN_RTR_DATA 0 /**< @brief Data frame. */ -#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief CAN1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_CAN1) || defined(__DOXYGEN__) -#define USE_STM32_CAN1 TRUE -#endif - -/** - * @brief CAN1 interrupt priority level setting. - */ -#if !defined(STM32_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CAN1_IRQ_PRIORITY 11 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP -#error "CAN sleep mode not supported in this architecture" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief CAN status flags. - */ -typedef uint32_t canstatus_t; - -/** - * @brief CAN transmission frame. - * @note Accessing the frame data as word16 or word32 is not portable because - * machine data endianness, it can be still useful for a quick filling. - */ -typedef struct { - struct { - uint8_t cf_DLC:4; /**< @brief Data length. */ - uint8_t cf_RTR:1; /**< @brief Frame type. */ - uint8_t cf_IDE:1; /**< @brief Identifier type. */ - }; - union { - struct { - uint32_t cf_SID:11; /**< @brief Standard identifier.*/ - }; - struct { - uint32_t cf_EID:29; /**< @brief Extended identifier.*/ - }; - }; - union { - uint8_t cf_data8[8]; /**< @brief Frame data. */ - uint16_t cf_data16[4]; /**< @brief Frame data. */ - uint32_t cf_data32[2]; /**< @brief Frame data. */ - }; -} CANTxFrame; - -/** - * @brief CAN received frame. - * @note Accessing the frame data as word16 or word32 is not portable because - * machine data endianness, it can be still useful for a quick filling. - */ -typedef struct { - struct { - uint8_t cf_FMI; /**< @brief Filter id. */ - uint16_t cf_TIME; /**< @brief Time stamp. */ - }; - struct { - uint8_t cf_DLC:4; /**< @brief Data length. */ - uint8_t cf_RTR:1; /**< @brief Frame type. */ - uint8_t cf_IDE:1; /**< @brief Identifier type. */ - }; - union { - struct { - uint32_t cf_SID:11; /**< @brief Standard identifier.*/ - }; - struct { - uint32_t cf_EID:29; /**< @brief Extended identifier.*/ - }; - }; - union { - uint8_t cf_data8[8]; /**< @brief Frame data. */ - uint16_t cf_data16[4]; /**< @brief Frame data. */ - uint32_t cf_data32[2]; /**< @brief Frame data. */ - }; -} CANRxFrame; - -/** - * @brief CAN filter. - * @note Refer to the STM32 reference manual for info about filters. - */ -typedef struct { - /** - * @brief Filter mode. - * @note This bit represent the CAN_FM1R register bit associated to this - * filter (0=mask mode, 1=list mode). - */ - uint32_t cf_mode:1; - /** - * @brief Filter sclae. - * @note This bit represent the CAN_FS1R register bit associated to this - * filter (0=16 bits mode, 1=32 bits mode). - */ - uint32_t cf_scale:1; - /** - * @brief Filter mode. - * @note This bit represent the CAN_FFA1R register bit associated to this - * filter, must be set to zero in this version of the driver. - */ - uint32_t cf_assignment:1; - /** - * @brief Filter register 1 (identifier). - */ - uint32_t cf_register1; - /** - * @brief Filter register 2 (mask/identifier depending on cf_mode=0/1). - */ - uint32_t cf_register2; -} CANFilter; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief CAN MCR register initialization data. - * @note Some bits in this register are enforced by the driver regardless - * their status in this field. - */ - uint32_t cc_mcr; - /** - * @brief CAN BTR register initialization data. - * @note Some bits in this register are enforced by the driver regardless - * their status in this field. - */ - uint32_t cc_btr; - /** - * @brief Number of elements into the filters array. - * @note By setting this field to zero a default filter is enabled that - * allows all frames, this should be adequate for simple applications. - */ - uint32_t cc_num; - /** - * @brief Pointer to an array of @p CANFilter structures. - * @note This field can be set to @p NULL if the field @p cc_num is set to - * zero. - */ - const CANFilter *cc_filters; -} CANConfig; - -/** - * @brief Structure representing an CAN driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - canstate_t cd_state; - /** - * @brief Current configuration data. - */ - const CANConfig *cd_config; - /** - * @brief Transmission queue semaphore. - */ - Semaphore cd_txsem; - /** - * @brief Receive queue semaphore. - */ - Semaphore cd_rxsem; - /** - * @brief One or more frames become available. - * @note After broadcasting this event it will not be broadcasted again - * until the received frames queue has been completely emptied. It - * is not broadcasted for each received frame. It is - * responsibility of the application to empty the queue by repeatedly - * invoking @p chReceive() when listening to this event. This behavior - * minimizes the interrupt served by the system because CAN traffic. - */ - EventSource cd_rxfull_event; - /** - * @brief One or more transmission slots become available. - */ - EventSource cd_txempty_event; - /** - * @brief A CAN bus error happened. - */ - EventSource cd_error_event; - /** - * @brief Error flags set when an error event is broadcasted. - */ - canstatus_t cd_status; -#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) - /** - * @brief Entering sleep state event. - */ - EventSource cd_sleep_event; - /** - * @brief Exiting sleep state event. - */ - EventSource cd_wakeup_event; -#endif /* CAN_USE_SLEEP_MODE */ - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the CAN registers. - */ - CAN_TypeDef *cd_can; -} CANDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_STM32_CAN1 && !defined(__DOXYGEN__) -extern CANDriver CAND1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void can_lld_init(void); - void can_lld_start(CANDriver *canp); - void can_lld_stop(CANDriver *canp); - bool_t can_lld_can_transmit(CANDriver *canp); - void can_lld_transmit(CANDriver *canp, const CANTxFrame *crfp); - bool_t can_lld_can_receive(CANDriver *canp); - void can_lld_receive(CANDriver *canp, CANRxFrame *ctfp); -#if CAN_USE_SLEEP_MODE - void can_lld_sleep(CANDriver *canp); - void can_lld_wakeup(CANDriver *canp); -#endif /* CAN_USE_SLEEP_MODE */ -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_CAN */ - -#endif /* _CAN_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c deleted file mode 100644 index fb98fb0..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/hal_lld.c - * @brief STM32 HAL subsystem low level driver source. - * - * @addtogroup STM32_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#define AIRCR_VECTKEY 0x05FA0000 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -const PALConfig pal_default_config = -{ - {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, - {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, - {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, - {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, -#if !defined(STM32F10X_LD) && !defined(CPU_WITH_NO_GPIOE) - {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, -#endif -#if defined(STM32F10X_HD) - {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, - {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - - /* SysTick initialization using the system clock.*/ - SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - -#if CH_HAL_USE_ADC || CH_HAL_USE_SPI - dmaInit(); -#endif -} - -/** - * @brief STM32 clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - */ -#if defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ - defined(STM32F10X_HD) || defined(__DOXYGEN__) -/* - * Clocks initialization for the LD, MD and HD sub-families. - */ -void stm32_clock_init(void) { - - /* HSI setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - RCC->CFGR = 0; /* CFGR reset value. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is the source.*/ - - /* HSE setup, it is only performed if the HSE clock is selected as source - of the system clock (directly or through the PLL).*/ -#if (STM32_SW == STM32_SW_HSE) || \ - ((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)) - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ -#endif - - /* PLL setup, it is only performed if the PLL is the selected source of - the system clock else it is left disabled.*/ -#if STM32_SW == STM32_SW_PLL - RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL is stable. */ -#endif - - /* Clock settings.*/ - RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; - - /* Flash setup and final clock selection. */ - FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ - - /* Switching on the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; -#endif -} -#elif defined(STM32F10X_CL) -/* - * Clocks initialization for the CL sub-family. - */ -void stm32_clock_init(void) { - - /* HSI setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - RCC->CFGR = 0; /* CFGR reset value. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is the source.*/ - RCC->CFGR2 = 0; - - /* HSE setup, it is only performed if the HSE clock is selected as source - of the system clock (directly or through the PLLs).*/ -#if (STM32_SW == STM32_SW_HSE) || \ - ((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1)) - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ -#endif - - /* PLL2 setup, it is only performed if the PLL2 clock is selected as source - for the PLL clock else it is left disabled.*/ -#if STM32_SW == STM32_SW_PLL -#if STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 - RCC->CFGR2 |= STM32_PREDIV2 | STM32_PLL2MUL; - RCC->CR |= RCC_CR_PLL2ON; - while (!(RCC->CR & RCC_CR_PLL2RDY)) - ; /* Waits until PLL is stable. */ -#endif - - /* PLL setup, it is only performed if the PLL is the selected source of - the system clock else it is left disabled.*/ - RCC->CFGR2 |= STM32_PREDIV1 | STM32_PREDIV1SRC; - RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL2 is stable. */ -#endif - - /* Clock settings.*/ - RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; - - /* Flash setup and final clock selection. */ - FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ - - /* Switching on the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; -#endif -} -#else -void stm32_clock_init(void) {} -#endif - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.h deleted file mode 100644 index 79cf018..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/hal_lld.h - * @brief STM32 HAL subsystem low level driver header. - * - * @addtogroup STM32_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -/* Tricks required to make the TRUE/FALSE declaration inside the library - compatible.*/ -#undef FALSE -#undef TRUE -#include "stm32f10x.h" -#define FALSE 0 -#define TRUE (!FALSE) - -#include "nvic.h" -#include "stm32_dma.h" - -/** - * @brief Platform name. - */ -#if defined(STM32F10X_MD) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32 MD" -#include "hal_lld_f103.h" -#elif defined(STM32F10X_LD) -#define PLATFORM_NAME "STM32 LD" -#include "hal_lld_f103.h" -#elif defined(STM32F10X_HD) -#define PLATFORM_NAME "STM32 HD" -#include "hal_lld_f103.h" -#elif defined(STM32F10X_CL) -#define PLATFORM_NAME "STM32 CL" -#include "hal_lld_f105_f107.h" -#else -#error "STM32 platform unknown or not specified" -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void stm32_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld_f103.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld_f103.h deleted file mode 100644 index 90b6d6c..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld_f103.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/hal_lld_f103.h - * @brief STM32F103 HAL subsystem low level driver header. - * - * @addtogroup STM32F103_HAL - * @{ - */ - -#ifndef _HAL_LLD_F103_H_ -#define _HAL_LLD_F103_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define STM32_HSICLK 8000000 /**< High speed internal clock. */ -#define STM32_LSICLK 40000 /**< Low speed internal clock. */ - -/* RCC_CFGR register bits definitions.*/ -#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ - -#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */ -#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */ -#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */ -#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */ - -#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ -#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ - -#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ -#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ - -#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ -#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ -#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */ -#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ -#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ -#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ -#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ -#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ -#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ -#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ -#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ -#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ -#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ -#define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ -#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ -#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ -#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ -#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#endif -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ -#endif -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#endif -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) -#define USART3_IRQHandler VectorDC /**< USART3. */ -#endif -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTCAlarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ -#define USBWakeUp_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ -#if defined(STM32F10X_HD) || defined(__DOXYGEN__) -#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ -#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ -#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and - Commutation. */ -#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ -#define ADC3_IRQHandler VectorFC /**< ADC3. */ -#define FSMC_IRQHandler Vector100 /**< FSMC. */ -#define SDIO_IRQHandler Vector104 /**< SDIO. */ -#define TIM5_IRQHandler Vector108 /**< TIM5. */ -#define SPI3_IRQHandler Vector10C /**< SPI3. */ -#define UART4_IRQHandler Vector110 /**< UART4. */ -#define UART5_IRQHandler Vector114 /**< UART5. */ -#define TIM6_IRQHandler Vector118 /**< TIM6. */ -#define TIM7_IRQHandler Vector11C /**< TIM7. */ -#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ -#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ -#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ -#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ -#endif - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -/** - * @brief Clock source for the PLL. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief Crystal PLL pre-divider. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#endif - -/** - * @brief PLL multiplier value. - * @note The allowed range is 2...16. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLMUL_VALUE 9 -#endif - -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 72MHz system clock from - * a 8MHz crystal using the PLL. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#endif - -/** - * @brief ADC prescaler value. - */ -#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#endif - -/** - * @brief MCO pin setting. - */ -#if !defined(STM32_MCO) || defined(__DOXYGEN__) -#define STM32_MCO STM32_MCO_NOCLOCK -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* HSE prescaler setting check.*/ -#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ - (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) -#error "invalid STM32_PLLXTPRE value specified" -#endif -/** - * @brief PLLMUL field. - */ -#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ - defined(__DOXYGEN__) -#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) -#else -#error "invalid STM32_PLLMUL_VALUE value specified" -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 -#define STM32_PLLCLKIN (STM32_HSECLK / 1) -#else -#define STM32_PLLCLKIN (STM32_HSECLK / 2) -#endif -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / 2) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* PLL input frequency range check.*/ -#if (STM32_PLLCLKIN < 3000000) || (STM32_PLLCLKIN > 12000000) -#error "STM32_PLLCLKIN outside acceptable range (3...12MHz)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) - -/* PLL output frequency range check.*/ -#if (STM32_PLLCLKOUT < 16000000) || (STM32_PLLCLKOUT > 72000000) -#error "STM32_PLLCLKOUT outside acceptable range (16...72MHz)" -#endif - -/** - * @brief System clock source. - */ -#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_PLLCLKOUT -#elif (STM32_SW == STM32_SW_HSI) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK -#else -#error "invalid STM32_SYSCLK_SW value specified" -#endif - -/* Check on the system clock.*/ -#if STM32_SYSCLK > 72000000 -#error "STM32_SYSCLK above maximum rated frequency (72MHz)" -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* AHB frequency check.*/ -#if STM32_HCLK > 72000000 -#error "STM32_HCLK exceeding maximum frequency (72MHz)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* APB1 frequency check.*/ -#if STM32_PCLK2 > 36000000 -#error "STM32_PCLK1 exceeding maximum frequency (36MHz)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* APB2 frequency check.*/ -#if STM32_PCLK2 > 72000000 -#error "STM32_PCLK2 exceeding maximum frequency (72MHz)" -#endif - -/** - * @brief ADC frequency. - */ -#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_ADCCLK (STM32_PCLK2 / 2) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK2 / 4) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 -#define STM32_ADCCLK (STM32_PCLK2 / 6) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 -#define STM32_ADCCLK (STM32_PCLK2 / 8) -#else -#error "invalid STM32_ADCPRE value specified" -#endif - -/* ADC frequency check.*/ -#if STM32_ADCCLK > 14000000 -#error "STM32_ADCCLK exceeding maximum frequency (14MHz)" -#endif - -/** - * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) -#endif - -/** - * @brief Timers 1, 8, 9, 10 and 11 clock. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000010 -#elif STM32_HCLK <= 48000000 -#define STM32_FLASHBITS 0x00000011 -#else -#define STM32_FLASHBITS 0x00000012 -#endif - -#endif /* _HAL_LLD_F103_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld_f105_f107.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld_f105_f107.h deleted file mode 100644 index b0ce98c..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld_f105_f107.h +++ /dev/null @@ -1,538 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/hal_lld_f105_f107.h - * @brief STM32F10x Connectivity Line HAL subsystem low level driver header. - * - * @addtogroup STM32F10X_CL_HAL - * @{ - */ - -#ifndef _HAL_LLD_F105_F107_H_ -#define _HAL_LLD_F105_F107_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define STM32_HSICLK 8000000 /**< High speed internal clock. */ -#define STM32_LSICLK 40000 /**< Low speed internal clock. */ - -/* RCC_CFGR register bits definitions.*/ -#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ -#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ -#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ - -#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */ -#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */ -#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */ -#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */ - -#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ -#define STM32_PLLSRC_PREDIV1 (1 << 16) /**< PLL clock source is - PREDIV1. */ - -#define STM32_OTGFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */ -#define STM32_OTGFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */ - -#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ -#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ -#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */ -#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ -#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ -#define STM32_MCO_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */ -#define STM32_MCO_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */ -#define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */ -#define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */ - -/* RCC_CFGR2 register bits definitions.*/ -#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ -#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ -#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ -#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ -#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ -#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ -#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ -#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ -#define ADC1_2_IRQHandler Vector88 /**< ADC1 and ADC2. */ -#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ -#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ -#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ -#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#define USART3_IRQHandler VectorDC /**< USART3. */ -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTCAlarm_IRQHandler VectorE4 /**< RTC alarm through EXTI - line. */ -#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through - EXTI line. */ -#define TIM5_IRQHandler Vector108 /**< TIM5. */ -#define SPI3_IRQHandler Vector10C /**< SPI3. */ -#define UART4_IRQHandler Vector110 /**< UART4. */ -#define UART5_IRQHandler Vector114 /**< UART5. */ -#define TIM6_IRQHandler Vector118 /**< TIM6. */ -#define TIM7_IRQHandler Vector11C /**< TIM7. */ -#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ -#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ -#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ -#define DMA2_Ch4_IRQHandler Vector12C /**< DMA2 Channel4. */ -#define DMA2_Ch5_IRQHandler Vector130 /**< DMA2 Channel5. */ -#define ETH_IRQHandler Vector134 /**< Ethernet. */ -#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through - EXTI line. */ -#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ -#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ -#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ -#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ -#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_SW) || defined(__DOXYGEN__) -#define STM32_SW STM32_SW_PLL -#endif - -/** - * @brief Clock source for the PLL. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 -#endif - -/** - * @brief PREDIV1 clock source. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PREDIV1SRC) || defined(__DOXYGEN__) -#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 -#endif - -/** - * @brief PREDIV1 division factor. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The allowed range is 1...16. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PREDIV1_VALUE) || defined(__DOXYGEN__) -#define STM32_PREDIV1_VALUE 5 -#endif - -/** - * @brief PLL multiplier value. - * @note The allowed range is 4...9. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLMUL_VALUE 9 -#endif - -/** - * @brief PREDIV2 division factor. - * @note This setting has only effect if the PLL2 is selected as the - * clock source for the PLL. - * @note The allowed range is 1...16. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PREDIV2_VALUE) || defined(__DOXYGEN__) -#define STM32_PREDIV2_VALUE 5 -#endif - -/** - * @brief PLL2 multiplier value. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_PLL2MUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL2MUL_VALUE 8 -#endif - -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 72MHz system clock from - * a 25MHz crystal using both PLL and PLL2. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#endif - -/** - * @brief ADC prescaler value. - */ -#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#endif - -/** - * @brief MCO pin setting. - */ -#if !defined(STM32_MCO) || defined(__DOXYGEN__) -#define STM32_MCO STM32_MCO_NOCLOCK -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief PREDIV1 field. - */ -#if (STM32_PREDIV1_VALUE >= 1) && (STM32_PREDIV1_VALUE <= 16) || \ - defined(__DOXYGEN__) -#define STM32_PREDIV1 ((STM32_PREDIV1_VALUE - 1) << 0) -#else -#error "invalid STM32_PREDIV1_VALUE value specified" -#endif - -/** - * @brief PREDIV2 field. - */ -#if (STM32_PREDIV2_VALUE >= 1) && (STM32_PREDIV2_VALUE <= 16) || \ - defined(__DOXYGEN__) -#define STM32_PREDIV2 ((STM32_PREDIV2_VALUE - 1) << 4) -#else -#error "invalid STM32_PREDIV2_VALUE value specified" -#endif - -/** - * @brief PLLMUL field. - */ -#if ((STM32_PLLMUL_VALUE >= 4) && (STM32_PLLMUL_VALUE <= 9)) || \ - defined(__DOXYGEN__) -#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) -#else -#error "invalid STM32_PLLMUL_VALUE value specified" -#endif - -/** - * @brief PLL2MUL field. - */ -#if ((STM32_PLL2MUL_VALUE >= 8) && (STM32_PLL2MUL_VALUE <= 14)) || \ - defined(__DOXYGEN__) -#define STM32_PLL2MUL ((STM32_PLL2MUL_VALUE - 2) << 8) -#elif (STM32_PLL2MUL_VALUE == 16) -#define STM32_PLL2MUL (14 << 8) -#elif (STM32_PLL2MUL_VALUE == 20) -#define STM32_PLL2MUL (15 << 8) -#else -#error "invalid STM32_PLL2MUL_VALUE value specified" -#endif - -/* The following values are only used if PLL2 clock is selected as source - for the PLL clock */ -#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__) -/** - * @brief PLL2 input frequency. - */ -#define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) - -/* PLL2 input frequency range check.*/ -#if (STM32_PLL2CLKIN < 3000000) || (STM32_PLL2CLKIN > 5000000) -#error "STM32_PLL2CLKIN outside acceptable range (3...5MHz)" -#endif - -/** - * @brief PLL2 output clock frequency. - */ -#define STM32_PLL2CLKOUT (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE) - -/* PLL2 output frequency range check.*/ -#if (STM32_PLL2CLKOUT < 40000000) || (STM32_PLL2CLKOUT > 74000000) -#error "STM32_PLL2CLKOUT outside acceptable range (40...74MHz)" -#endif -#endif /* STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 */ - -/** - * @brief PREDIV1 input frequency. - */ -#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__) -#define STM32_PREDIV1CLK STM32_PLL2CLKOUT -#elif STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE -#define STM32_PREDIV1CLK STM32_HSECLK -#else -#error "invalid STM32_PREDIV1SRC value specified" -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / 2) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* PLL input frequency range check.*/ -#if (STM32_PLLCLKIN < 3000000) || (STM32_PLLCLKIN > 12000000) -#error "STM32_PLLCLKIN outside acceptable range (3...12MHz)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) - -/* PLL output frequency range check.*/ -#if (STM32_PLLCLKOUT < 18000000) || (STM32_PLLCLKOUT > 72000000) -#error "STM32_PLLCLKOUT outside acceptable range (18...72MHz)" -#endif - -/** - * @brief System clock source. - */ -#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_PLLCLKOUT -#elif (STM32_SW == STM32_SW_HSI) -#define STM32_SYSCLK STM32_HSICLK -#elif (STM32_SW == STM32_SW_HSE) -#define STM32_SYSCLK STM32_HSECLK -#else -#error "invalid STM32_SYSCLK_SW value specified" -#endif - -/* Check on the system clock.*/ -#if STM32_SYSCLK > 72000000 -#error "STM32_SYSCLK above maximum rated frequency (72MHz)" -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* AHB frequency check.*/ -#if STM32_HCLK > 72000000 -#error "STM32_HCLK exceeding maximum frequency (72MHz)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* APB1 frequency check.*/ -#if STM32_PCLK1 > 36000000 -#error "STM32_PCLK1 exceeding maximum frequency (36MHz)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* APB2 frequency check.*/ -#if STM32_PCLK2 > 72000000 -#error "STM32_PCLK2 exceeding maximum frequency (72MHz)" -#endif - -/** - * @brief ADC frequency. - */ -#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_ADCCLK (STM32_PCLK2 / 2) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK2 / 4) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 -#define STM32_ADCCLK (STM32_PCLK2 / 6) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 -#define STM32_ADCCLK (STM32_PCLK2 / 8) -#else -#error "invalid STM32_ADCPRE value specified" -#endif - -/* ADC frequency check.*/ -#if STM32_ADCCLK > 14000000 -#error "STM32_ADCCLK exceeding maximum frequency (14MHz)" -#endif - -/** - * @brief Timers 2, 3, 4, 5, 6, 7 clock. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK1 (STM32_PCLK1 * 1) -#else -#define STM32_TIMCLK1 (STM32_PCLK1 * 2) -#endif - -/** - * @brief Timer 1 clock. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_TIMCLK2 (STM32_PCLK2 * 1) -#else -#define STM32_TIMCLK2 (STM32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) -#define STM32_FLASHBITS 0x00000010 -#elif STM32_HCLK <= 48000000 -#define STM32_FLASHBITS 0x00000011 -#else -#define STM32_FLASHBITS 0x00000012 -#endif - -#endif /* _HAL_LLD_F105_F107_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.c deleted file mode 100644 index 34b205d..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/pal_lld.c - * @brief STM32 GPIO low level driver code. - * - * @addtogroup STM32_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -#if defined(STM32F10X_LD) -#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \ - RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \ - RCC_APB2RSTR_AFIORST) -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_AFIOEN) -#elif defined(STM32F10X_HD) -#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \ - RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \ - RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_IOPFRST | \ - RCC_APB2RSTR_IOPGRST | RCC_APB2RSTR_AFIORST); -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \ - RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN) -#else - /* Defaults on Medium Density and Connection Line devices.*/ -#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \ - RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \ - RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_AFIORST); -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN) -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 I/O ports configuration. - * @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled. - * - * @param[in] config the STM32 ports configuration - */ -void _pal_lld_init(const PALConfig *config) { - - /* - * Enables the GPIO related clocks. - */ - RCC->APB2ENR |= APB2_EN_MASK; - - /* - * Resets the GPIO ports and AFIO. - */ - RCC->APB2RSTR = APB2_RST_MASK; - RCC->APB2RSTR = 0; - - IOPORT1->ODR = config->PAData.odr; - IOPORT1->CRH = config->PAData.crh; - IOPORT1->CRL = config->PAData.crl; - IOPORT2->ODR = config->PBData.odr; - IOPORT2->CRH = config->PBData.crh; - IOPORT2->CRL = config->PBData.crl; - IOPORT3->ODR = config->PCData.odr; - IOPORT3->CRH = config->PCData.crh; - IOPORT3->CRL = config->PCData.crl; - IOPORT4->ODR = config->PDData.odr; - IOPORT4->CRH = config->PDData.crh; - IOPORT4->CRL = config->PDData.crl; -#if !(defined(STM32F10X_LD) || defined(CPU_WITH_NO_GPIOE)) || defined(__DOXYGEN__) - IOPORT5->ODR = config->PEData.odr; - IOPORT5->CRH = config->PEData.crh; - IOPORT5->CRL = config->PEData.crl; -#endif -#if defined(STM32F10X_HD) || defined(__DOXYGEN__) - IOPORT6->ODR = config->PFData.odr; - IOPORT6->CRH = config->PFData.crh; - IOPORT6->CRL = config->PFData.crl; - IOPORT7->ODR = config->PGData.odr; - IOPORT7->CRH = config->PGData.crh; - IOPORT7->CRL = config->PGData.crl; -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - static const uint8_t cfgtab[] = { - 4, /* PAL_MODE_RESET, implemented as input.*/ - 2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/ - 4, /* PAL_MODE_INPUT */ - 8, /* PAL_MODE_INPUT_PULLUP */ - 8, /* PAL_MODE_INPUT_PULLDOWN */ - 0, /* PAL_MODE_INPUT_ANALOG */ - 3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/ - 7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 8, /* Reserved.*/ - 0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/ - 0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/ - }; - uint32_t mh, ml, crh, crl, cfg; - unsigned i; - - if (mode == PAL_MODE_INPUT_PULLUP) - port->BSRR = mask; - else if (mode == PAL_MODE_INPUT_PULLDOWN) - port->BRR = mask; - cfg = cfgtab[mode]; - mh = ml = crh = crl = 0; - for (i = 0; i < 8; i++) { - ml <<= 4; - mh <<= 4; - crl <<= 4; - crh <<= 4; - if ((mask & 0x0080) == 0) - ml |= 0xf; - else - crl |= cfg; - if ((mask & 0x8000) == 0) - mh |= 0xf; - else - crh |= cfg; - mask <<= 1; - } - port->CRH = (port->CRH & mh) | crh; - port->CRL = (port->CRL & ml) | crl; -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h deleted file mode 100644 index 3cfec41..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/pal_lld.h - * @brief STM32 GPIO low level driver header. - * - * @addtogroup STM32_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -/** - * @brief STM32 specific alternate push-pull output mode. - */ -#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16 - -/** - * @brief STM32 specific alternate open-drain output mode. - */ -#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17 - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for ODR register.*/ - uint32_t odr; - /** Initial value for CRL register.*/ - uint32_t crl; - /** Initial value for CRH register.*/ - uint32_t crh; -} stm32_gpio_setup_t; - -/** - * @brief STM32 GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialize the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** @brief Port A setup data.*/ - stm32_gpio_setup_t PAData; - /** @brief Port B setup data.*/ - stm32_gpio_setup_t PBData; - /** @brief Port C setup data.*/ - stm32_gpio_setup_t PCData; - /** @brief Port D setup data.*/ - stm32_gpio_setup_t PDData; -#if !(defined(STM32F10X_LD) || defined(CPU_WITH_NO_GPIOE)) || defined(__DOXYGEN__) - /** @brief Port E setup data.*/ - stm32_gpio_setup_t PEData; -#endif -#if defined(STM32F10X_HD) || defined(__DOXYGEN__) - /** @brief Port F setup data.*/ - stm32_gpio_setup_t PFData; - /** @brief Port G setup data.*/ - stm32_gpio_setup_t PGData; -#endif -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 16 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef GPIO_TypeDef * ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the STM32 */ -/* firmware library. */ -/*===========================================================================*/ - -/** - * @brief GPIO port A identifier. - */ -#define IOPORT1 GPIOA - -/** - * @brief GPIO port B identifier. - */ -#define IOPORT2 GPIOB - -/** - * @brief GPIO port C identifier. - */ -#define IOPORT3 GPIOC - -/** - * @brief GPIO port D identifier. - */ -#define IOPORT4 GPIOD - -/** - * @brief GPIO port E identifier. - */ -#if !defined(STM32F10X_LD) || defined(__DOXYGEN__) -#define IOPORT5 GPIOE -#endif - -/** - * @brief GPIO port F identifier. - */ -#if defined(STM32F10X_HD) || defined(__DOXYGEN__) -#define IOPORT6 GPIOF - -/** - * @brief GPIO port G identifier. - */ -#define IOPORT7 GPIOG -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, please put them in a file named ioports_lld.c if so. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports subsystem initialization. - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads an I/O port. - * @details This function is implemented by reading the GPIO IDR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port the port identifier - * @return The port bits. - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details This function is implemented by reading the GPIO ODR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the application - * code. - * - * @param[in] port the port identifier - * @return The latched logical states. - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes on a I/O port. - * @details This function is implemented by writing the GPIO ODR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be written on the specified port - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be ORed on the specified port - */ -#define pal_lld_setport(port, bits) ((port)->BSRR = (bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @details This function is implemented by writing the GPIO BRR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] bits the bits to be cleared on the specified port - */ -#define pal_lld_clearport(port, bits) ((port)->BRR = (bits)) - -/** - * @brief Writes a group of bits. - * @details This function is implemented by writing the GPIO BSRR register, the - * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] offset the group bit offset within the port - * @param[in] bits the bits to be written. Values exceeding the group - * width are masked. - */ -#define pal_lld_writegroup(port, mask, offset, bits) { \ - (port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \ - (((bits) & (mask)) << (offset)); \ -} - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Writing on pads programmed as pull-up or pull-down has the side - * effect to modify the resistor setting because the output latched - * data is used for the resistor selection. - * - * @param[in] port the port identifier - * @param[in] pad the pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - */ -#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) - -extern const PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/STM32/platform.dox deleted file mode 100644 index f59feb6..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/platform.dox +++ /dev/null @@ -1,150 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup STM32 STM32 Support - * @brief STM32 specific support. - * @details The STM32 support includes: - * - I/O ports driver. - * - Buffered, interrupt driven, serial driver. - * - Interrupt driver CAN driver. - * - DMA capable, high performance, ADC driver. - * - DMA capable, high performance, SPI driver. - * - PWM driver. - * - A demo supporting the kernel test suite. - * - A demo that demonstrate the FatFs use with the MMC driver. - * . - * @ingroup ARMCMx - */ - -/** - * @defgroup STM32_HAL STM32 HAL Support - * @brief HAL support. - * - * @ingroup STM32 - */ - -/** - * @defgroup STM32F103_HAL STM32F103 HAL Support - * @brief HAL support for STM32 LD, MD and HD families. - * - * @ingroup STM32_HAL - */ - -/** - * @defgroup STM32F10X_CL_HAL STM32F105/F107 HAL Support - * @brief HAL support for STM32 CL (Connectivity Line) family. - * - * @ingroup STM32_HAL - */ - -/** - * @defgroup STM32_PAL STM32 I/O Ports Support - * @brief I/O Ports peripherals support. - * @details This module supports the STM3 GPIO controller. The controller - * supports the following features (see @ref PAL): - * - 16 bits wide ports. - * - Atomic set/reset functions. - * - Atomic set+reset function (atomic bus operations). - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - *

Supported Setup Modes

- * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_INPUT_PULLUP. - * - @p PAL_MODE_INPUT_PULLDOWN. - * - @p PAL_MODE_INPUT_ANALOG. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * . - * Any attempt to setup an invalid mode is ignored. - * - *

Suboptimal Behavior

- * Some GPIO features are less than optimal: - * - Pad/port toggling operations are not atomic. - * - Pad/group mode setup is not atomic. - * - Writing on pads/groups/ports programmed as input with pull-up/down - * resistor can change the resistor setting because the output latch is - * used for resistor selection. - * . - * @ingroup STM32 - */ - -/** - * @defgroup STM32_SERIAL STM32 USART Support - * @brief USART peripherals support. - * @details The serial driver supports the STM32 USARTs in asynchronous - * mode. - * - * @ingroup STM32 - */ - -/** - * @defgroup STM32_DMA STM32 DMA Support - * @brief DMA support. - * @details The DMA helper driver allows to stop the DMA clock when no other - * driver requires its services. - * - * @ingroup STM32 - */ - -/** - * @defgroup STM32_ADC STM32 ADC Support - * @brief ADC peripherals support. - * @details The ADC driver supports the STM32 ADCs using DMA channels for - * improved performance. - * - * @ingroup STM32 - */ - -/** - * @defgroup STM32_CAN STM32 CAN Support - * @brief CAN peripheral support. - * @details The CAN driver supports the STM32 bxCAN unit. - * - * @ingroup STM32 - */ - - -/** - * @defgroup STM32_PWM STM32 PWM Support - * @brief TIMx peripherals as PWM generators support. - * @details The PWM driver supports the STM32 TIMx units as PWM generators. - * - * @ingroup STM32 - */ - -/** - * @defgroup STM32_SPI STM32 SPI Support - * @brief SPI peripherals support. - * @details The SPI driver supports the STM32 SPIs using DMA channels for - * improved performance. - * - * @ingroup STM32 - */ - diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/STM32/platform.mk deleted file mode 100644 index 0caf2e6..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/platform.mk +++ /dev/null @@ -1,12 +0,0 @@ -# List of all the STM32 platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/adc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/stm32_dma.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32 diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/pwm_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM32/pwm_lld.c deleted file mode 100644 index 4c10f98..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/pwm_lld.c +++ /dev/null @@ -1,455 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/pwm_lld.c - * @brief STM32 PWM subsystem low level driver header. - * - * @addtogroup STM32_PWM - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief PWM1 driver identifier. - * @note The driver PWM1 allocates the complex timer TIM1 when enabled. - */ -#if defined(USE_STM32_PWM1) || defined(__DOXYGEN__) -PWMDriver PWMD1; -#endif - -/** - * @brief PWM2 driver identifier. - * @note The driver PWM2 allocates the timer TIM2 when enabled. - */ -#if defined(USE_STM32_PWM2) || defined(__DOXYGEN__) -PWMDriver PWMD2; -#endif - -/** - * @brief PWM3 driver identifier. - * @note The driver PWM3 allocates the timer TIM3 when enabled. - */ -#if defined(USE_STM32_PWM3) || defined(__DOXYGEN__) -PWMDriver PWMD3; -#endif - -/** - * @brief PWM4 driver identifier. - * @note The driver PWM4 allocates the timer TIM4 when enabled. - */ -#if defined(USE_STM32_PWM4) || defined(__DOXYGEN__) -PWMDriver PWMD4; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if USE_STM32_PWM2 || USE_STM32_PWM3 || USE_STM32_PWM4 || defined(__DOXYGEN__) -/** - * @brief Common TIM2...TIM4 IRQ handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - */ -static void serve_interrupt(PWMDriver *pwmp) { - uint16_t sr; - - sr = pwmp->pd_tim->SR & pwmp->pd_tim->DIER; - pwmp->pd_tim->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | - TIM_SR_CC4IF | TIM_SR_UIF); - if ((sr & TIM_SR_CC1IF) != 0) - pwmp->pd_config->pc_channels[0].pcc_callback(pwmp); - if ((sr & TIM_SR_CC2IF) != 0) - pwmp->pd_config->pc_channels[1].pcc_callback(pwmp); - if ((sr & TIM_SR_CC3IF) != 0) - pwmp->pd_config->pc_channels[2].pcc_callback(pwmp); - if ((sr & TIM_SR_CC4IF) != 0) - pwmp->pd_config->pc_channels[3].pcc_callback(pwmp); - if ((sr & TIM_SR_UIF) != 0) - pwmp->pd_config->pc_callback(pwmp); -} -#endif /* USE_STM32_PWM2 || USE_STM32_PWM3 || USE_STM32_PWM4 */ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_STM32_PWM1 -/** - * @brief TIM1 update interrupt handler. - * @note It is assumed that this interrupt is only activated if the callback - * pointer is not equal to @p NULL in order to not perform an extra - * check in a potentially critical interrupt handler. - */ -CH_IRQ_HANDLER(VectorA4) { - - CH_IRQ_PROLOGUE(); - - TIM1->SR = ~TIM_SR_UIF; - PWMD1.pd_config->pc_callback(&PWMD1); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - */ -CH_IRQ_HANDLER(VectorAC) { - uint16_t sr; - - CH_IRQ_PROLOGUE(); - - sr = TIM1->SR & TIM1->DIER; - TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF); - if ((sr & TIM_SR_CC1IF) != 0) - PWMD1.pd_config->pc_channels[0].pcc_callback(&PWMD1); - if ((sr & TIM_SR_CC2IF) != 0) - PWMD1.pd_config->pc_channels[1].pcc_callback(&PWMD1); - if ((sr & TIM_SR_CC3IF) != 0) - PWMD1.pd_config->pc_channels[2].pcc_callback(&PWMD1); - if ((sr & TIM_SR_CC4IF) != 0) - PWMD1.pd_config->pc_channels[3].pcc_callback(&PWMD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_STM32_PWM1 */ - -#if USE_STM32_PWM2 -/** - * @brief TIM2 interrupt handler. - */ -CH_IRQ_HANDLER(VectorB0) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&PWMD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_STM32_PWM2 */ - -#if USE_STM32_PWM3 -/** - * @brief TIM3 interrupt handler. - */ -CH_IRQ_HANDLER(VectorB4) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&PWMD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_STM32_PWM3 */ - -#if USE_STM32_PWM4 -/** - * @brief TIM4 interrupt handler. - */ -CH_IRQ_HANDLER(VectorB8) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&PWMD4); - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_STM32_PWM4 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level PWM driver initialization. - */ -void pwm_lld_init(void) { - -#if USE_STM32_PWM1 - /* TIM1 reset, ensures reset state in order to avoid trouble with JTAGs.*/ - RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST; - RCC->APB2RSTR = 0; - - /* Driver initialization.*/ - pwmObjectInit(&PWMD1); - PWMD1.pd_enabled_channels = 0; - PWMD1.pd_tim = TIM1; -#endif - -#if USE_STM32_PWM2 - /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/ - RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST; - RCC->APB1RSTR = 0; - - /* Driver initialization.*/ - pwmObjectInit(&PWMD2); - PWMD2.pd_enabled_channels = 0; - PWMD2.pd_tim = TIM2; -#endif - -#if USE_STM32_PWM3 - /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/ - RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST; - RCC->APB1RSTR = 0; - - /* Driver initialization.*/ - pwmObjectInit(&PWMD3); - PWMD3.pd_enabled_channels = 0; - PWMD3.pd_tim = TIM3; -#endif - -#if USE_STM32_PWM4 - /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/ - RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST; - RCC->APB1RSTR = 0; - - /* Driver initialization.*/ - pwmObjectInit(&PWMD4); - PWMD4.pd_enabled_channels = 0; - PWMD4.pd_tim = TIM4; -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -void pwm_lld_start(PWMDriver *pwmp) { - uint16_t ccer; - - /* Reset channels.*/ - pwmp->pd_enabled_channels = 0; /* All channels disabled. */ - - if (pwmp->pd_state == PWM_STOP) { - /* Clock activation and timer reset.*/ -#if USE_STM32_PWM1 - if (&PWMD1 == pwmp) { - RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; - RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST; - RCC->APB2RSTR = 0; - NVICEnableVector(TIM1_UP_IRQn, - CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY)); - NVICEnableVector(TIM1_CC_IRQn, - CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY)); - } -#endif -#if USE_STM32_PWM2 - if (&PWMD2 == pwmp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST; - RCC->APB1RSTR = 0; - NVICEnableVector(TIM2_IRQn, - CORTEX_PRIORITY_MASK(STM32_PWM2_IRQ_PRIORITY)); - } -#endif -#if USE_STM32_PWM3 - if (&PWMD3 == pwmp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST; - RCC->APB1RSTR = 0; - NVICEnableVector(TIM3_IRQn, - CORTEX_PRIORITY_MASK(STM32_PWM3_IRQ_PRIORITY)); - } -#endif -#if USE_STM32_PWM4 - if (&PWMD4 == pwmp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST; - RCC->APB1RSTR = 0; - NVICEnableVector(TIM4_IRQn, - CORTEX_PRIORITY_MASK(STM32_PWM4_IRQ_PRIORITY)); - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - /* Really required ?????????? */ - pwmp->pd_tim->CR1 = 0; /* Timer stopped. */ - pwmp->pd_tim->CR2 = 0; /* Timer stopped. */ - pwmp->pd_tim->SMCR = 0; /* Slave mode disabled. */ - pwmp->pd_tim->CCR1 = 0; /* Comparator 1 disabled. */ - pwmp->pd_tim->CCR2 = 0; /* Comparator 2 disabled. */ - pwmp->pd_tim->CCR3 = 0; /* Comparator 3 disabled. */ - pwmp->pd_tim->CCR4 = 0; /* Comparator 4 disabled. */ - pwmp->pd_tim->CNT = 0; - } - - /* Timer configuration.*/ - pwmp->pd_tim->CR2 = pwmp->pd_config->pc_cr2; - pwmp->pd_tim->PSC = pwmp->pd_config->pc_psc; - pwmp->pd_tim->ARR = pwmp->pd_config->pc_arr; - /* Output enables and polarities setup.*/ - ccer = 0; - switch (pwmp->pd_config->pc_channels[0].pcc_mode) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC1P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC1E; - default: - ; - } - switch (pwmp->pd_config->pc_channels[1].pcc_mode) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC2P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC2E; - default: - ; - } - switch (pwmp->pd_config->pc_channels[2].pcc_mode) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC3P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC3E; - default: - ; - } - switch (pwmp->pd_config->pc_channels[3].pcc_mode) { - case PWM_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC4P; - case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC4E; - default: - ; - } - pwmp->pd_tim->CCER = ccer; - pwmp->pd_tim->EGR = TIM_EGR_UG; /* Update event. */ - pwmp->pd_tim->SR = 0; /* Clear pending IRQs. */ - pwmp->pd_tim->DIER = pwmp->pd_config->pc_callback == NULL ? 0 : TIM_DIER_UIE; - pwmp->pd_tim->BDTR = TIM_BDTR_MOE; - /* Timer configured and started.*/ - pwmp->pd_tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -void pwm_lld_stop(PWMDriver *pwmp) { - /* If in ready state then disables the PWM clock.*/ - if (pwmp->pd_state == PWM_READY) { - pwmp->pd_enabled_channels = 0; /* All channels disabled. */ - pwmp->pd_tim->CR1 = 0; - pwmp->pd_tim->CR2 = 0; - pwmp->pd_tim->CCER = 0; /* Outputs disabled. */ - pwmp->pd_tim->CCR1 = 0; /* Comparator 1 disabled. */ - pwmp->pd_tim->CCR2 = 0; /* Comparator 2 disabled. */ - pwmp->pd_tim->CCR3 = 0; /* Comparator 3 disabled. */ - pwmp->pd_tim->CCR4 = 0; /* Comparator 4 disabled. */ - pwmp->pd_tim->BDTR = 0; - pwmp->pd_tim->DIER = 0; - pwmp->pd_tim->SR = 0; - pwmp->pd_tim->EGR = TIM_EGR_UG; /* Update event. */ - -#if USE_STM32_PWM1 - if (&PWMD1 == pwmp) { - NVICDisableVector(TIM1_UP_IRQn); - NVICDisableVector(TIM1_CC_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN; - } -#endif -#if USE_STM32_PWM2 - if (&PWMD2 == pwmp) { - NVICDisableVector(TIM2_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN; - } -#endif -#if USE_STM32_PWM3 - if (&PWMD3 == pwmp) { - NVICDisableVector(TIM3_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN; - } -#endif -#if USE_STM32_PWM4 - if (&PWMD4 == pwmp) { - NVICDisableVector(TIM4_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN; - } -#endif - } -} - -/** - * @brief Enables a PWM channel. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * @param[in] width PWM pulse width as clock pulses number - */ -void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - - *(&pwmp->pd_tim->CCR1 + (channel * 2)) = width; /* New duty cycle. */ - if ((pwmp->pd_enabled_channels & (1 << channel)) == 0) { - /* The channel is not enabled yet.*/ - pwmp->pd_enabled_channels |= (1 << channel); - /* If there is a callback associated to the channel then the proper - interrupt is cleared and enabled.*/ - if (pwmp->pd_config->pc_channels[channel].pcc_callback) { - pwmp->pd_tim->SR = ~(2 << channel); - pwmp->pd_tim->DIER |= (2 << channel); - } - } -} - -/** - * @brief Disables a PWM channel. - * @details The channel is disabled and its output line returned to the - * idle state. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - */ -void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - - *(&pwmp->pd_tim->CCR1 + (channel * 2)) = 0; - pwmp->pd_tim->DIER &= ~(2 << channel); - pwmp->pd_enabled_channels &= ~(1 << channel); -} - -#endif /* CH_HAL_USE_PWM */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/pwm_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/pwm_lld.h deleted file mode 100644 index f0842d6..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/pwm_lld.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/pwm_lld.h - * @brief STM32 PWM subsystem low level driver header. - * - * @addtogroup PWM - * @{ - */ - -#ifndef _PWM_LLD_H_ -#define _PWM_LLD_H_ - -#if CH_HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of PWM channels per PWM driver. - */ -#define PWM_CHANNELS 4 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief PWM1 driver enable switch. - * @details If set to @p TRUE the support for PWM1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_PWM1) || defined(__DOXYGEN__) -#define USE_STM32_PWM1 TRUE -#endif - -/** - * @brief PWM2 driver enable switch. - * @details If set to @p TRUE the support for PWM2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_PWM2) || defined(__DOXYGEN__) -#define USE_STM32_PWM2 TRUE -#endif - -/** - * @brief PWM3 driver enable switch. - * @details If set to @p TRUE the support for PWM3 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_PWM3) || defined(__DOXYGEN__) -#define USE_STM32_PWM3 TRUE -#endif - -/** - * @brief PWM4 driver enable switch. - * @details If set to @p TRUE the support for PWM4 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_PWM4) || defined(__DOXYGEN__) -#define USE_STM32_PWM4 TRUE -#endif - -/** - * @brief PWM1 interrupt priority level setting. - */ -#if !defined(STM32_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWM2 interrupt priority level setting. - */ -#if !defined(STM32_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWM3 interrupt priority level setting. - */ -#if !defined(STM32_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief PWM4 interrupt priority level setting. - */ -#if !defined(STM32_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM4_IRQ_PRIORITY 7 -#endif - -/*===========================================================================*/ -/* Configuration checks. */ -/*===========================================================================*/ - -#if USE_STM32_PWM4 && defined(STM32F10X_LD) -#error "TIM4 not present in low density STM32 devices" -#endif - -#if !USE_STM32_PWM1 && !USE_STM32_PWM2 && \ - !USE_STM32_PWM3 && !USE_STM32_PWM4 -#error "PWM driver activated but no TIM peripheral assigned" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief PWM channel type. - */ -typedef uint8_t pwmchannel_t; - -/** - * @brief PWM counter type. - */ -typedef uint16_t pwmcnt_t; - -/** - * @brief Type of a structure representing an PWM driver. - */ -typedef struct PWMDriver PWMDriver; - -/** - * @brief PWM notification callback type. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -typedef void (*pwmcallback_t)(PWMDriver *pwmp); - -/** - * @brief PWM driver channel configuration structure. - */ -typedef struct { - /** - * @brief Channel active logic level. - */ - pwmmode_t pcc_mode; - /** - * @brief Channel callback pointer. - * @note This callback is invoked on the channel compare event. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t pcc_callback; - /* End of the mandatory fields.*/ -} PWMChannelConfig; - -/** - * @brief PWM driver configuration structure. - */ -typedef struct { - /** - * @brief Periodic callback pointer. - * @note This callback is invoked on PWM counter reset. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t pc_callback; - /** - * @brief Channels configurations. - */ - PWMChannelConfig pc_channels[PWM_CHANNELS]; - /* End of the mandatory fields.*/ - /** - * @brief TIM PSC (pre-scaler) register initialization data. - */ - uint16_t pc_psc; - /** - * @brief TIM ARR (auto-reload) register initialization data. - */ - uint16_t pc_arr; - /** - * @brief TIM CR2 register initialization data. - * @note The value of this field should normally be equal to zero. - */ - uint16_t pc_cr2; -} PWMConfig; - -/** - * @brief Structure representing a PWM driver. - */ -struct PWMDriver { - /** - * @brief Driver state. - */ - pwmstate_t pd_state; - /** - * @brief Current driver configuration data. - */ - const PWMConfig *pd_config; -#if defined(PWM_DRIVER_EXT_FIELDS) - PWM_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Bit mask of the enabled channels. - */ - uint32_t pd_enabled_channels; - /** - * @brief Pointer to the TIMx registers block. - */ - TIM_TypeDef *pd_tim; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief PWM clock prescaler initialization utility. - * @note The real clock value is rounded to the lower valid value, please - * make sure that the source clock frequency is a multiple of the - * requested PWM clock frequency. - * @note The calculated value must fit into an unsigned 16 bits integer. - * - * @param[in] clksrc clock source frequency, depending on the target timer - * cell it can be one of: - * - STM32_TIMCLK1 - * - STM32_TIMCLK2 - * . - * Please refer to the STM32 HAL driver documentation - * and/or the STM32 Reference Manual for the right clock - * source. - * @param[in] pwmclk PWM clock frequency in cycles - * @return The value to be stored in the @p pc_psc field of the - * @p PWMConfig structure. - */ -#define PWM_COMPUTE_PSC(clksrc, pwmclk) \ - ((uint16_t)(((clksrc) / (pwmclk)) - 1)) - -/** - * @brief PWM cycle period initialization utility. - * @note The calculated value must fit into an unsigned 16 bits integer. - * - * @param[in] pwmclk PWM clock frequency in cycles - * @param[in] pwmperiod PWM cycle period in nanoseconds - * @return The value to be stored in the @p pc_arr field of the - * @p PWMConfig structure. - */ -#define PWM_COMPUTE_ARR(pwmclk, pwmperiod) \ - ((uint16_t)(((pwmclk) / (1000000000 / (pwmperiod))) - 1)) - -/** - * @brief Converts from fraction to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify tenths of thousandth but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] numerator numerator of the fraction - * @param[in] denominator percentage as an integer between 0 and numerator - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_FRACTION_TO_WIDTH(pwmp, numerator, denominator) \ - ((uint16_t)((((uint32_t)(pwmp)->pd_config->pc_arr + 1UL) * \ - (uint32_t)(denominator)) / (uint32_t)(numerator))) - -/** - * @brief Converts from degrees to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify hundredths of degrees but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] degrees degrees as an integer between 0 and 36000 - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_DEGREES_TO_WIDTH(pwmp, degrees) \ - PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) - -/** - * @brief Converts from percentage to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify tenths of thousandth but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] percentage percentage as an integer between 0 and 10000 - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage) \ - PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if defined(USE_STM32_PWM1) && !defined(__DOXYGEN__) -extern PWMDriver PWMD1; -#endif - -#if defined(USE_STM32_PWM2) && !defined(__DOXYGEN__) -extern PWMDriver PWMD2; -#endif - -#if defined(USE_STM32_PWM3) && !defined(__DOXYGEN__) -extern PWMDriver PWMD3; -#endif - -#if defined(USE_STM32_PWM4) && !defined(__DOXYGEN__) -extern PWMDriver PWMD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void pwm_lld_init(void); - void pwm_lld_start(PWMDriver *pwmp); - void pwm_lld_stop(PWMDriver *pwmp); - void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PWM */ - -#endif /* _PWM_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM32/serial_lld.c deleted file mode 100644 index 99aebf9..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/serial_lld.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/serial_lld.c - * @brief STM32 low level serial driver code. - * - * @addtogroup STM32_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 serial driver identifier.*/ -#if USE_STM32_USART1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** @brief USART2 serial driver identifier.*/ -#if USE_STM32_USART2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/** @brief USART3 serial driver identifier.*/ -#if USE_STM32_USART3 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__) -/** @brief UART4 serial driver identifier.*/ -#if USE_STM32_UART4 || defined(__DOXYGEN__) -SerialDriver SD4; -#endif - -/** @brief UART5 serial driver identifier.*/ -#if USE_STM32_UART5 || defined(__DOXYGEN__) -SerialDriver SD5; -#endif -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = -{ - SERIAL_DEFAULT_BITRATE, - 0, - USART_CR2_STOP1_BITS | USART_CR2_LINEN, - 0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration - */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config) { - USART_TypeDef *u = sdp->usart; - - /* - * Baud rate setting. - */ - if (sdp->usart == USART1) - u->BRR = STM32_PCLK2 / config->sc_speed; - else - u->BRR = STM32_PCLK1 / config->sc_speed; - - /* - * Note that some bits are enforced. - */ - u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE | - USART_CR1_RXNEIE | USART_CR1_TE | - USART_CR1_RE; - u->CR2 = config->sc_cr2 | USART_CR2_LBDIE; - u->CR3 = config->sc_cr3 | USART_CR3_EIE; - (void)u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] u pointer to an USART I/O block - */ -static void usart_deinit(USART_TypeDef *u) { - - u->CR1 = 0; - u->CR2 = 0; - u->CR3 = 0; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] sr USART SR register value - */ -static void set_error(SerialDriver *sdp, uint16_t sr) { - sdflags_t sts = 0; - - if (sr & USART_SR_ORE) - sts |= SD_OVERRUN_ERROR; - if (sr & USART_SR_PE) - sts |= SD_PARITY_ERROR; - if (sr & USART_SR_FE) - sts |= SD_FRAMING_ERROR; - if (sr & USART_SR_NE) - sts |= SD_NOISE_ERROR; - if (sr & USART_SR_LBD) - sts |= SD_BREAK_DETECTED; - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -/** - * @brief Common IRQ handler. - * - * @param[in] sdp communication channel associated to the USART - */ -static void serve_interrupt(SerialDriver *sdp) { - USART_TypeDef *u = sdp->usart; - uint16_t cr1 = u->CR1; - uint16_t sr = u->SR; /* SR reset step 1.*/ - uint16_t dr = u->DR; /* SR reset step 2.*/ - - if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | - USART_SR_FE | USART_SR_PE)) { - set_error(sdp, sr); - u->SR = 0; /* Clears the LBD bit in the SR.*/ - } - if (sr & USART_SR_RXNE) { - chSysLockFromIsr(); - sdIncomingDataI(sdp, (uint8_t)dr); - chSysUnlockFromIsr(); - } - if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) { - msg_t b; - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chEvtBroadcastI(&sdp->oevent); - u->CR1 = cr1 & ~USART_CR1_TXEIE; - } - else - u->DR = b; - chSysUnlockFromIsr(); - } -} - -#if USE_STM32_USART1 || defined(__DOXYGEN__) -static void notify1(void) { - - USART1->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if USE_STM32_USART2 || defined(__DOXYGEN__) -static void notify2(void) { - - USART2->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if USE_STM32_USART3 || defined(__DOXYGEN__) -static void notify3(void) { - - USART3->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__) -#if USE_STM32_UART4 || defined(__DOXYGEN__) -static void notify4(void) { - - UART4->CR1 |= USART_CR1_TXEIE; -} -#endif - -#if USE_STM32_UART5 || defined(__DOXYGEN__) -static void notify5(void) { - - UART5->CR1 |= USART_CR1_TXEIE; -} -#endif -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_STM32_USART1 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(VectorD4) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if USE_STM32_USART2 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(VectorD8) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD2); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if USE_STM32_USART3 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(VectorDC) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD3); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__) -#if USE_STM32_UART4 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(Vector110) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD4); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if USE_STM32_UART5 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(Vector114) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD5); - - CH_IRQ_EPILOGUE(); -} -#endif -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_STM32_USART1 - sdObjectInit(&SD1, NULL, notify1); - SD1.usart = USART1; -#endif - -#if USE_STM32_USART2 - sdObjectInit(&SD2, NULL, notify2); - SD2.usart = USART2; -#endif - -#if USE_STM32_USART3 - sdObjectInit(&SD3, NULL, notify3); - SD3.usart = USART3; -#endif - -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#if USE_STM32_UART4 - sdObjectInit(&SD4, NULL, notify4); - SD4.usart = UART4; -#endif - -#if USE_STM32_UART5 - sdObjectInit(&SD5, NULL, notify5); - SD5.usart = UART5; -#endif -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if USE_STM32_USART1 - if (&SD1 == sdp) { - RCC->APB2ENR |= RCC_APB2ENR_USART1EN; - NVICEnableVector(USART1_IRQn, - CORTEX_PRIORITY_MASK(STM32_USART1_PRIORITY)); - } -#endif -#if USE_STM32_USART2 - if (&SD2 == sdp) { - RCC->APB1ENR |= RCC_APB1ENR_USART2EN; - NVICEnableVector(USART2_IRQn, - CORTEX_PRIORITY_MASK(STM32_USART2_PRIORITY)); - } -#endif -#if USE_STM32_USART3 - if (&SD3 == sdp) { - RCC->APB1ENR |= RCC_APB1ENR_USART3EN; - NVICEnableVector(USART3_IRQn, - CORTEX_PRIORITY_MASK(STM32_USART3_PRIORITY)); - } -#endif -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#if USE_STM32_UART4 - if (&SD4 == sdp) { - RCC->APB1ENR |= RCC_APB1ENR_UART4EN; - NVICEnableVector(UART4_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART4_PRIORITY)); - } -#endif -#if USE_STM32_UART5 - if (&SD5 == sdp) { - RCC->APB1ENR |= RCC_APB1ENR_UART5EN; - NVICEnableVector(UART5_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART5_PRIORITY)); - } -#endif -#endif - } - usart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - usart_deinit(sdp->usart); -#if USE_STM32_USART1 - if (&SD1 == sdp) { - RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; - NVICDisableVector(USART1_IRQn); - return; - } -#endif -#if USE_STM32_USART2 - if (&SD2 == sdp) { - RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; - NVICDisableVector(USART2_IRQn); - return; - } -#endif -#if USE_STM32_USART3 - if (&SD3 == sdp) { - RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; - NVICDisableVector(USART3_IRQn); - return; - } -#endif -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#if USE_STM32_UART4 - if (&SD4 == sdp) { - RCC->APB1ENR &= ~RCC_APB1ENR_UART4EN; - NVICDisableVector(UART4_IRQn); - return; - } -#endif -#if USE_STM32_UART5 - if (&SD5 == sdp) { - RCC->APB1ENR &= ~RCC_APB1ENR_UART5EN; - NVICDisableVector(UART5_IRQn); - return; - } -#endif -#endif - } -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/serial_lld.h deleted file mode 100644 index 44bb40f..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/serial_lld.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/serial_lld.h - * @brief STM32 low level serial driver header. - * - * @addtogroup STM32_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(USE_STM32_USART1) || defined(__DOXYGEN__) -#define USE_STM32_USART1 TRUE -#endif - -/** - * @brief USART2 driver enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_USART2) || defined(__DOXYGEN__) -#define USE_STM32_USART2 TRUE -#endif - -/** - * @brief USART3 driver enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(USE_STM32_USART3) || defined(__DOXYGEN__) -#define USE_STM32_USART3 TRUE -#endif - - -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__) -/** - * @brief UART4 driver enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE. - */ -#if !defined(USE_STM32_UART4) || defined(__DOXYGEN__) -#define USE_STM32_UART4 TRUE -#endif - -/** - * @brief UART5 driver enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE. - */ -#if !defined(USE_STM32_UART5) || defined(__DOXYGEN__) -#define USE_STM32_UART5 TRUE -#endif -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_USART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USART1_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_USART2_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USART2_PRIORITY 12) -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_USART3_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USART3_PRIORITY 12 -#endif - -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__) -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(STM32_UART4_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART4_PRIORITY 12 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(STM32_UART5_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART5_PRIORITY 12 -#endif -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint32_t sdflags_t; - -/** - * @brief STM32 Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /** - * @brief Initialization value for the CR1 register. - */ - uint16_t sc_cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint16_t sc_cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint16_t sc_cr3; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - USART_TypeDef *usart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * Extra USARTs definitions here (missing from the ST header file). - */ -#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/ -#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/ -#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/ -#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_STM32_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_STM32_USART2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif -#if USE_STM32_USART3 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#if USE_STM32_UART4 && !defined(__DOXYGEN__) -extern SerialDriver SD4; -#endif -#if USE_STM32_UART5 && !defined(__DOXYGEN__) -extern SerialDriver SD5; -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/spi_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM32/spi_lld.c deleted file mode 100644 index b6208c6..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/spi_lld.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/spi_lld.c - * @brief STM32 SPI subsystem low level driver source. - * @addtogroup STM32_SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SPI1 driver identifier.*/ -#if USE_STM32_SPI1 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** @brief SPI2 driver identifier.*/ -#if USE_STM32_SPI2 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -static uint16_t dummyrx; -static uint16_t dummytx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void spi_stop(SPIDriver *spip) { - - /* Stops RX and TX DMA channels.*/ - spip->spd_dmarx->CCR = 0; - spip->spd_dmatx->CCR = 0; - - /* Stops SPI operations.*/ - spip->spd_spi->CR1 &= ~SPI_CR1_SPE; - - chSysLockFromIsr(); - chSchReadyI(spip->spd_thread); - chSysUnlockFromIsr(); -} - -static void spi_start_wait(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - uint32_t ccr; - - /* Common DMA setup.*/ - ccr = spip->spd_dmaprio; - if ((spip->spd_config->spc_cr1 & SPI_CR1_DFF) != 0) - ccr |= DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0; /* 16 bits transfer.*/ - - /* RX DMA setup.*/ - spip->spd_dmarx->CMAR = (uint32_t)rxbuf; - spip->spd_dmarx->CNDTR = (uint32_t)n; - spip->spd_dmarx->CCR |= ccr; - - /* TX DMA setup.*/ - spip->spd_dmatx->CMAR = (uint32_t)txbuf; - spip->spd_dmatx->CNDTR = (uint32_t)n; - spip->spd_dmatx->CCR |= ccr; - - /* SPI enable.*/ - chSysLock(); - spip->spd_spi->CR1 |= SPI_CR1_SPE; - - /* DMAs start.*/ - spip->spd_dmarx->CCR |= DMA_CCR1_EN; - spip->spd_dmatx->CCR |= DMA_CCR1_EN; - - /* Wait for completion event.*/ - spip->spd_thread = currp; - chSchGoSleepS(THD_STATE_SUSPENDED); - spip->spd_thread = NULL; - chSysUnlock(); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_STM32_SPI1 || defined(__DOXYGEN__) -/** - * @brief SPI1 RX DMA interrupt handler (channel 2). - */ -CH_IRQ_HANDLER(Vector70) { - - CH_IRQ_PROLOGUE(); - - spi_stop(&SPID1); - if ((DMA1->ISR & DMA_ISR_TEIF2) != 0) { - STM32_SPI1_DMA_ERROR_HOOK(); - } - DMA1->IFCR |= DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 | - DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2; - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief SPI1 TX DMA interrupt handler (channel 3). - */ -CH_IRQ_HANDLER(Vector74) { - - CH_IRQ_PROLOGUE(); - - STM32_SPI1_DMA_ERROR_HOOK(); - DMA1->IFCR |= DMA_IFCR_CGIF3 | DMA_IFCR_CTCIF3 | - DMA_IFCR_CHTIF3 | DMA_IFCR_CTEIF3; - - CH_IRQ_EPILOGUE(); -} -#endif - -#if USE_STM32_SPI2 || defined(__DOXYGEN__) -/** - * @brief SPI2 RX DMA interrupt handler (channel 4). - */ -CH_IRQ_HANDLER(Vector78) { - - CH_IRQ_PROLOGUE(); - - spi_stop(&SPID2); - if ((DMA1->ISR & DMA_ISR_TEIF4) != 0) { - STM32_SPI2_DMA_ERROR_HOOK(); - } - DMA1->IFCR |= DMA_IFCR_CGIF4 | DMA_IFCR_CTCIF4 | - DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4; - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief SPI2 TX DMA interrupt handler (channel 5). - */ -CH_IRQ_HANDLER(Vector7C) { - - CH_IRQ_PROLOGUE(); - - STM32_SPI2_DMA_ERROR_HOOK(); - DMA1->IFCR |= DMA_IFCR_CGIF5 | DMA_IFCR_CTCIF5 | - DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5; - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - */ -void spi_lld_init(void) { - - dummytx = 0xFFFF; - -#if USE_STM32_SPI1 - RCC->APB2RSTR = RCC_APB2RSTR_SPI1RST; - RCC->APB2RSTR = 0; - spiObjectInit(&SPID1); - SPID1.spd_thread = NULL; - SPID1.spd_spi = SPI1; - SPID1.spd_dmarx = DMA1_Channel2; - SPID1.spd_dmatx = DMA1_Channel3; - SPID1.spd_dmaprio = STM32_SPI1_DMA_PRIORITY << 12; -#endif - -#if USE_STM32_SPI2 - RCC->APB1RSTR = RCC_APB1RSTR_SPI2RST; - RCC->APB1RSTR = 0; - spiObjectInit(&SPID2); - SPID2.spd_thread = NULL; - SPID2.spd_spi = SPI2; - SPID2.spd_dmarx = DMA1_Channel4; - SPID2.spd_dmatx = DMA1_Channel5; - SPID2.spd_dmaprio = STM32_SPI2_DMA_PRIORITY << 12; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_start(SPIDriver *spip) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (spip->spd_state == SPI_STOP) { -#if USE_STM32_SPI1 - if (&SPID1 == spip) { - dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/ - NVICEnableVector(DMA1_Channel2_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel3_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY)); - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; - } -#endif -#if USE_STM32_SPI2 - if (&SPID2 == spip) { - dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/ - NVICEnableVector(DMA1_Channel4_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel5_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; - } -#endif - } - - /* SPI setup.*/ - spip->spd_spi->CR1 = spip->spd_config->spc_cr1 | SPI_CR1_MSTR; - spip->spd_spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; - - /* DMA setup.*/ - spip->spd_dmarx->CPAR = (uint32_t)&spip->spd_spi->DR; - spip->spd_dmatx->CPAR = (uint32_t)&spip->spd_spi->DR; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_stop(SPIDriver *spip) { - - /* If in ready state then disables the SPI clock.*/ - if (spip->spd_state == SPI_READY) { -#if USE_STM32_SPI1 - if (&SPID1 == spip) { - NVICDisableVector(DMA1_Channel2_IRQn); - NVICDisableVector(DMA1_Channel3_IRQn); - dmaDisable(DMA1_ID); - RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN; - } -#endif -#if USE_STM32_SPI2 - if (&SPID2 == spip) { - NVICDisableVector(DMA1_Channel4_IRQn); - NVICDisableVector(DMA1_Channel5_IRQn); - dmaDisable(DMA1_ID); - RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN; - } -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This function transmits a series of idle words on the SPI bus and - * ignores the received data. This function can be invoked even - * when a slave select signal has not been yet asserted. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - spip->spd_dmarx->CCR = DMA_CCR1_TCIE | DMA_CCR1_TEIE; - spip->spd_dmatx->CCR = DMA_CCR1_DIR | DMA_CCR1_TEIE; - spi_start_wait(spip, n, &dummytx, &dummyrx); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This function performs a simultaneous transmit/receive operation. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - spip->spd_dmarx->CCR = DMA_CCR1_TCIE | DMA_CCR1_MINC | DMA_CCR1_TEIE; - spip->spd_dmatx->CCR = DMA_CCR1_DIR | DMA_CCR1_MINC | DMA_CCR1_TEIE; - spi_start_wait(spip, n, txbuf, rxbuf); -} - -/** - * @brief Sends data ever the SPI bus. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - spip->spd_dmarx->CCR = DMA_CCR1_TCIE | DMA_CCR1_TEIE; - spip->spd_dmatx->CCR = DMA_CCR1_DIR | DMA_CCR1_MINC | DMA_CCR1_TEIE; - spi_start_wait(spip, n, txbuf, &dummyrx); -} - -/** - * @brief Receives data from the SPI bus. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - spip->spd_dmarx->CCR = DMA_CCR1_TCIE | DMA_CCR1_MINC | DMA_CCR1_TEIE; - spip->spd_dmatx->CCR = DMA_CCR1_DIR | DMA_CCR1_TEIE; - spi_start_wait(spip, n, &dummytx, rxbuf); -} - -#endif /* CH_HAL_USE_SPI */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/spi_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/spi_lld.h deleted file mode 100644 index 3c024ec..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/spi_lld.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM32/spi_lld.h - * @brief STM32 SPI subsystem low level driver header. - * - * @addtogroup STM32_SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if CH_HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_SPI1) || defined(__DOXYGEN__) -#define USE_STM32_SPI1 TRUE -#endif - -/** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for SPI2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM32_SPI2) || defined(__DOXYGEN__) -#define USE_STM32_SPI2 TRUE -#endif - -/** - * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI1_DMA_PRIORITY 2 -#endif - -/** - * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI2_DMA_PRIORITY 2 -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. - */ -#if !defined(STM32_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI1 DMA error hook. - * @note The default action for DMA errors is a system halt because DMA error - * can only happen because programming errors. - */ -#if !defined(STM32_SPI1_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() -#endif - -/** - * @brief SPI2 DMA error hook. - * @note The default action for DMA errors is a system halt because DMA error - * can only happen because programming errors. - */ -#if !defined(STM32_SPI2_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI2_DMA_ERROR_HOOK() chSysHalt() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief The chip select line port. - */ - ioportid_t spc_ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t spc_sspad; - /** - * @brief SPI initialization data. - */ - uint16_t spc_cr1; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - spistate_t spd_state; -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex spd_mutex; -#elif CH_USE_SEMAPHORES - Semaphore spd_semaphore; -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ - /** - * @brief Current configuration data. - */ - const SPIConfig *spd_config; - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion. - */ - Thread *spd_thread; - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spd_spi; - /** - * @brief Pointer to the receive DMA channel registers block. - */ - DMA_Channel_TypeDef *spd_dmarx; - /** - * @brief Pointer to the transmit DMA channel registers block. - */ - DMA_Channel_TypeDef *spd_dmatx; - /** - * @brief DMA priority bit mask. - */ - uint32_t spd_dmaprio; -} SPIDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_STM32_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if USE_STM32_SPI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32_dma.c b/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32_dma.c deleted file mode 100644 index e4e9b32..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32_dma.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file stm32_dma.c - * @brief STM32 DMA helper driver code. - * @addtogroup STM32_DMA - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -static cnt_t dmacnt1; -#if defined(STM32F10X_HD) || defined (STM32F10X_CL) -static cnt_t dmacnt2; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - */ -void dmaInit(void) { - - dmacnt1 = 0; -#if defined(STM32F10X_HD) || defined (STM32F10X_CL) - dmacnt2 = 0; -#endif -} - -/** - * @brief Enables the specified DMA controller clock. - * - * @param[in] dma the DMA controller id - */ -void dmaEnable(uint32_t dma) { - - switch (dma) { - case DMA1_ID: - if (dmacnt1++ == 0) { - RCC->AHBENR |= RCC_AHBENR_DMA1EN; - DMA1->IFCR = 0x0FFFFFFF; - } - break; -#if defined(STM32F10X_HD) || defined (STM32F10X_CL) - case DMA2_ID: - if (dmacnt2++ == 0) { - RCC->AHBENR |= RCC_AHBENR_DMA2EN; - DMA2->IFCR = 0x0FFFFFFF; - } - break; -#endif - } -} - -/** - * @brief Disables the specified DMA controller clock. - * - * @param[in] dma the DMA controller id - */ -void dmaDisable(uint32_t dma) { - - switch (dma) { - case DMA1_ID: - if (--dmacnt1 == 0) - RCC->AHBENR &= ~RCC_AHBENR_DMA1EN; - break; -#if defined(STM32F10X_HD) || defined (STM32F10X_CL) - case DMA2_ID: - if (--dmacnt2 == 0) - RCC->AHBENR &= ~RCC_AHBENR_DMA2EN; - break; -#endif - } -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32_dma.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32_dma.h deleted file mode 100644 index c34dd15..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32_dma.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file stm32_dma.h - * @brief STM32 DMA helper driver header. - * - * @addtogroup STM32_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** @brief DMA1 identifier.*/ -#define DMA1_ID 0 - -/** @brief DMA2 identifier.*/ -#if defined(STM32F10X_HD) || defined (STM32F10X_CL) || defined(__DOXYGEN__) -#define DMA2_ID 1 -#endif - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - void dmaEnable(uint32_t dma); - void dmaDisable(uint32_t dma); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32f10x.h b/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32f10x.h deleted file mode 100644 index 78375ce..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM32/stm32f10x.h +++ /dev/null @@ -1,8224 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F10x Connectivity line, High - * density, Medium density, Medium density Value line, Low density - * and Low density Value line and XL-density devices. - ****************************************************************************** - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x - * @{ - */ - -#ifndef __STM32F10x_H -#define __STM32F10x_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ - /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ - /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - #define STM32F10X_XL /*!< STM32F10X_XL: STM32 XL-density devices */ - /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 16 and 32 Kbytes. - - Low-density value line devices are STM32F100xx microcontrollers where the Flash - memory density ranges between 16 and 32 Kbytes. - - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 64 and 128 Kbytes. - - Medium-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 64 and 128 Kbytes. - - High density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 256 and 512 Kbytes. - - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 512 and 1024 Kbytes. - - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. - */ - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_VALUE - #ifdef STM32F10X_CL - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_VALUE */ - - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ - -/** - * @brief STM32F10x Standard Peripheral Library version number - */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x03) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ - | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ - | __STM32F10X_STDPERIPH_VERSION_SUB2) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#ifdef STM32F10X_XL - #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ -#else - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#endif /* STM32F10X_XL */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - -#ifdef STM32F10X_LD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_LD */ - -#ifdef STM32F10X_LD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_LD_VL */ - -#ifdef STM32F10X_MD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_MD */ - -#ifdef STM32F10X_MD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_MD_VL */ - -#ifdef STM32F10X_HD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_XL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_XL */ - -#ifdef STM32F10X_CL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* STM32F10X_CL */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -/*#include "system_stm32f10x.h"*/ -#include - -/** @addtogroup Exported_types - * @{ - */ - -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -#ifndef __cplusplus -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -#endif - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT -#define HSE_Value HSE_VALUE -#define HSI_Value HSI_VALUE -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RTCCR; - uint16_t RESERVED11; - __IO uint16_t CR; - uint16_t RESERVED12; - __IO uint16_t CSR; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; -#ifndef STM32F10X_CL - CAN_FilterRegister_TypeDef sFilterRegister[14]; -#else - CAN_FilterRegister_TypeDef sFilterRegister[28]; -#endif /* STM32F10X_CL */ -} CAN_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t OAR; - __IO uint32_t PRES; - __IO uint32_t ESR; - __IO uint32_t CSR; - __IO uint32_t TXD; - __IO uint32_t RXD; -} CEC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - __IO uint32_t SR; -#endif -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -#ifdef STM32F10X_XL - uint32_t RESERVED1[8]; - __IO uint32_t KEYR2; - uint32_t RESERVED2; - __IO uint32_t SR2; - __IO uint32_t CR2; - __IO uint32_t AR2; -#endif /* STM32F10X_XL */ -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; - __IO uint32_t SR3; - __IO uint32_t PMEM3; - __IO uint32_t PATT3; - uint32_t RESERVED0; - __IO uint32_t ECCR3; -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; - __IO uint32_t SR4; - __IO uint32_t PMEM4; - __IO uint32_t PATT4; - __IO uint32_t PIO4; -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - -#ifdef STM32F10X_CL - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif /* STM32F10X_CL */ - -#if defined STM32F10X_LD_VL || defined STM32F10X_MD_VL - uint32_t RESERVED0; - __IO uint32_t CFGR2; -#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint16_t CRH; - uint16_t RESERVED0; - __IO uint16_t CRL; - uint16_t RESERVED1; - __IO uint16_t PRLH; - uint16_t RESERVED2; - __IO uint16_t PRLL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRH; - uint16_t RESERVED8; - __IO uint16_t ALRL; - uint16_t RESERVED9; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - __IO uint16_t RCR; - uint16_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ - -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define CEC_BASE (APB1PERIPH_BASE + 0x7800) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ -#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ -#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ -#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef STM32F10X_CL - #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ - #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ - #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ - #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#ifdef STM32F10X_CL - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ - #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ - - #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ - #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ - #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#else - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#endif /* STM32F10X_CL */ - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef STM32F10X_CL - #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ - #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ - #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ - #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ - #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ - #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* STM32F10X_CL */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) -#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ -#endif - -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ -#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ -#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ - #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ - #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ -#endif /* STM32F10X_XL */ - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ -#endif - -#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ - #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ - #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ - #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ -#endif /* STM32F10X_XL */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ - #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ - #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ - #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ - #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) -#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ -#endif - -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ -#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ -#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ - #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ - #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ -#endif - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ -#endif - -#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ - #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ - #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ - #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ - #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ -#endif /* STM32F10X_XL */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -#ifdef STM32F10X_CL -/******************* Bit definition for RCC_AHBRSTR register ****************/ - #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ - #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ - #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ - #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ - #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ - #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ - #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ - #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ - #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ - #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ - #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ - #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ - #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ - #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ - #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ - #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ - #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ - #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ - #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ - #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ - #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ - #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ - #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ - #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ - #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ - #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ - #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ - - #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ - #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ -#endif - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef STM32F10X_CL -/*!< ETH_REMAP configuration */ - #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ - #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ - #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ - #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ - #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ -#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ -#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ -#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ -#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ -#endif - -#ifdef STM32F10X_XL -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ -#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ -#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#endif - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ -#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*!. - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM8/hal_lld.c - * @brief STM8 HAL subsystem low level driver source. - * - * @addtogroup STM8_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -ROMCONST PALConfig pal_default_config = -{ - { - {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2}, - {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2}, - {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2}, - {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2}, - {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2}, - {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2}, - {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2}, - {VAL_GPIOHODR, 0, VAL_GPIOHDDR, VAL_GPIOHCR1, VAL_GPIOHCR2}, - {VAL_GPIOIODR, 0, VAL_GPIOIDDR, VAL_GPIOICR1, VAL_GPIOICR2} - } -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - -#if STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT -#if STM8_CLOCK_SOURCE == CLK_SOURCE_HSI - CLK_ICKR = 1; /* HSIEN */ - while ((CLK_ICKR & 2) == 0) /* HSIRDY */ - ; -#elif STM8_CLOCK_SOURCE == CLK_SOURCE_LSI - CLK_ICKR = 8; /* LSIEN */ - while ((CLK_ICKR & 16) == 0) /* LSIRDY */ - ; -#else /* STM8_CLOCK_SOURCE == CLK_SOURCE_HSE */ - CLK_ECKR = 1; /* HSEEN */ - while ((CLK_ECKR & 2) == 0) /* HSERDY */ - ; -#endif -#if STM8_CLOCK_SOURCE != CLK_SOURCE_HSI - /* Switching clock (manual switch mode).*/ - CLK_SWCR = 0; - CLK_SWR = STM8_CLOCK_SOURCE; - while ((CLK_SWCR & 8) == 0) /* SWIF */ - ; - CLK_SWCR = 2; /* SWEN */ -#endif - /* Setting up clock dividers.*/ - CLK_CKDIVR = (STM8_HSI_DIVIDER << 3) | (STM8_CPU_DIVIDER << 0); - - /* Clocks initially all disabled.*/ - CLK_PCKENR1 = 0; - CLK_PCKENR2 = 0; - - /* Other clock related initializations.*/ - CLK_CSSR = 0; - CLK_CCOR = 0; - CLK_CANCCR = 0; -#endif /* STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT */ -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM8/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM8/hal_lld.h deleted file mode 100644 index 7fb05b2..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM8/hal_lld.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM8/hal_lld.h - * @brief STM8 HAL subsystem low level driver source. - * - * @addtogroup STM8_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "stm8.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "STM8x" - -#define LSICLK 128000 /**< Low speed internal clock. */ -#define HSICLK 16000000 /**< High speed internal clock. */ - -#define CLK_SOURCE_DEFAULT 0 /**< No clock initialization. */ -#define CLK_SOURCE_HSI 0xE1 /**< HSI clock selector. */ -#define CLK_SOURCE_LSI 0xD2 /**< LSI clock selector. */ -#define CLK_SOURCE_HSE 0xB4 /**< HSE clock selector. */ - -#define CLK_HSI_DIV1 0 /**< HSI clock divided by 1. */ -#define CLK_HSI_DIV2 1 /**< HSI clock divided by 2. */ -#define CLK_HSI_DIV4 2 /**< HSI clock divided by 4. */ -#define CLK_HSI_DIV8 3 /**< HSI clock divided by 8. */ - -#define CLK_CPU_DIV1 0 /**< CPU clock divided by 1. */ -#define CLK_CPU_DIV2 1 /**< CPU clock divided by 2. */ -#define CLK_CPU_DIV4 2 /**< CPU clock divided by 4. */ -#define CLK_CPU_DIV8 3 /**< CPU clock divided by 8. */ -#define CLK_CPU_DIV16 4 /**< CPU clock divided by 16. */ -#define CLK_CPU_DIV32 5 /**< CPU clock divided by 32. */ -#define CLK_CPU_DIV64 6 /**< CPU clock divided by 64. */ -#define CLK_CPU_DIV128 7 /**< CPU clock divided by 128. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Clock source setting. - */ -#if !defined(STM8_CLOCK_SOURCE) || defined(__DOXYGEN__) -#define STM8_CLOCK_SOURCE CLK_SOURCE_DEFAULT -#endif - -/** - * @brief HSI clock divider. - */ -#if !defined(STM8_HSI_DIVIDER) || defined(__DOXYGEN__) -#define STM8_HSI_DIVIDER CLK_HSI_DIV8 -#endif - -/** - * @brief CPU clock divider. - */ -#if !defined(STM8_CPU_DIVIDER) || defined(__DOXYGEN__) -#define STM8_CPU_DIVIDER CLK_CPU_DIV1 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (STM8_HSI_DIVIDER != CLK_HSI_DIV1) && \ - (STM8_HSI_DIVIDER != CLK_HSI_DIV2) && \ - (STM8_HSI_DIVIDER != CLK_HSI_DIV4) && \ - (STM8_HSI_DIVIDER != CLK_HSI_DIV8) -#error "specified invalid HSI divider" -#endif - -#if (STM8_CPU_DIVIDER != CLK_CPU_DIV1) && \ - (STM8_CPU_DIVIDER != CLK_CPU_DIV2) && \ - (STM8_CPU_DIVIDER != CLK_CPU_DIV4) && \ - (STM8_CPU_DIVIDER != CLK_CPU_DIV8) && \ - (STM8_CPU_DIVIDER != CLK_CPU_DIV16) && \ - (STM8_CPU_DIVIDER != CLK_CPU_DIV32) && \ - (STM8_CPU_DIVIDER != CLK_CPU_DIV64) && \ - (STM8_CPU_DIVIDER != CLK_CPU_DIV128) -#error "specified invalid CPU divider" -#endif - -#if STM8_CLOCK_SOURCE == CLK_SOURCE_DEFAULT -#define SYSCLK (HSICLK / 8) -#elif STM8_CLOCK_SOURCE == CLK_SOURCE_HSI -#define SYSCLK (HSICLK / (1 << STM8_HSI_DIVIDER)) -#elif STM8_CLOCK_SOURCE == CLK_SOURCE_LSI -#define SYSCLK LSICLK -#elif STM8_CLOCK_SOURCE == CLK_SOURCE_HSE -#define SYSCLK HSECLK -#else -#error "specified invalid clock source" -#endif - -#define CPUCLK (SYSCLK / (1 << STM8_CPU_DIVIDER)) - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM8/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM8/pal_lld.c deleted file mode 100644 index 7d24626..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM8/pal_lld.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM8/pal_lld.c - * @brief STM8 GPIO low level driver code. - * - * @addtogroup STM8_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - - switch (mode & PAL_MODE_MASK) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT_PULLUP: - port->DDR &= ~mask; - port->CR1 |= mask; - port->CR2 &= ~mask; - break; - case PAL_MODE_INPUT: - case PAL_MODE_INPUT_ANALOG: - port->DDR &= ~mask; - port->CR1 &= ~mask; - port->CR2 &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - case PAL_MODE_OUTPUT_PUSHPULL_SLOW: - port->DDR |= mask; - port->CR1 |= mask; - port->CR2 &= ~mask; - break; - case PAL_MODE_OUTPUT_PUSHPULL: - port->DDR |= mask; - port->CR1 |= mask; - port->CR2 |= mask; - break; - case PAL_MODE_OUTPUT_OPENDRAIN_SLOW: - port->DDR |= mask; - port->CR1 &= ~mask; - port->CR2 &= ~mask; - break; - case PAL_MODE_OUTPUT_OPENDRAIN: - port->DDR |= mask; - port->CR1 &= ~mask; - port->CR2 |= mask; - break; - } -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM8/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM8/pal_lld.h deleted file mode 100644 index 8845616..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM8/pal_lld.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM8/pal_lld.h - * @brief STM8 GPIO low level driver header. - * - * @addtogroup STM8_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLDOWN - -/** - * @brief STM8 specific alternate push-pull slow output mode. - */ -#define PAL_MODE_OUTPUT_PUSHPULL_SLOW 16 - -/** - * @brief STM8 specific alternate open-drain slow output mode. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW 17 - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief GPIO port representation. - */ -typedef struct { - volatile uint8_t ODR; - volatile uint8_t IDR; - volatile uint8_t DDR; - volatile uint8_t CR1; - volatile uint8_t CR2; -} gpio_t; - -/** - * @brief Generic I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - gpio_t P[9]; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 8 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint8_t ioportmask_t; - -/** - * @brief Port Identifier. - */ -typedef gpio_t *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports as a whole. - */ -#define IOPORTS ((PALConfig *)0x5000) - -/** - * @brief GPIO port A identifier. - */ -#define IOPORT1 ((gpio_t *)0x5000) -#define GPIOA IOPORT1 - -/** - * @brief GPIO port B identifier. - */ -#define IOPORT2 ((gpio_t *)0x5005) -#define GPIOB IOPORT2 - -/** - * @brief GPIO port C identifier. - */ -#define IOPORT3 ((gpio_t *)0x500A) -#define GPIOC IOPORT3 - -/** - * @brief GPIO port D identifier. - */ -#define IOPORT4 ((gpio_t *)0x500F) -#define GPIOD IOPORT4 - -/** - * @brief GPIO port E identifier. - */ -#define IOPORT5 ((gpio_t *)0x5014) -#define GPIOE IOPORT5 - -/** - * @brief GPIO port F identifier. - */ -#define IOPORT6 ((gpio_t *)0x5019) -#define GPIOF IOPORT6 - -/** - * @brief GPIO port G identifier. - */ -#define IOPORT7 ((gpio_t *)0x501E) -#define GPIOG IOPORT7 - -/** - * @brief GPIO port H identifier. - */ -#define IOPORT8 ((gpio_t *)0x5023) -#define GPIOH IOPORT8 - -/** - * @brief GPIO port I identifier. - */ -#define IOPORT9 ((gpio_t *)0x5028) -#define GPIOI IOPORT9 - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - */ -#define pal_lld_init(config) *IOPORTS = *(config) - -/** - * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The port bits. - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The latched logical states. - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] mode group mode - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -extern ROMCONST PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM8/platform.dox b/ChibiOS_2.0.8/os/hal/platforms/STM8/platform.dox deleted file mode 100644 index 7e53cdc..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM8/platform.dox +++ /dev/null @@ -1,75 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup STM8_DRIVERS STM8 Drivers - * @brief Device drivers included in the STM8 support. - * - * @ingroup STM8 - */ - -/** - * @defgroup STM8_HAL STM8 HAL Support - * @brief HAL support. - * - * @ingroup STM8_DRIVERS - */ - -/** - * @defgroup STM8_PAL STM8 I/O Ports Support - * @brief I/O Ports peripherals support. - * @details This module supports the STM8 GPIO controller. The controller - * supports the following features (see @ref PAL): - * - 8 bits wide ports. - * - Atomic set/reset/toggle functions because special STM8 instruction set. - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - *

Supported Setup Modes

- * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_INPUT_PULLUP. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * . - * Any attempt to setup an invalid mode is ignored. - * - *

Suboptimal Behavior

- * Some STM8 I/O ports features are less than optimal: - * - Bus/group writing is not atomic. - * - Pad/group mode setup is not atomic. - * . - * @ingroup STM8_DRIVERS - */ - -/** - * @defgroup STM8_SERIAL STM8 UART Support - * @brief USART support. - * @details The serial driver supports the STM8 USARTs in asynchronous mode. - * - * @ingroup STM8_DRIVERS - */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM8/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/STM8/serial_lld.c deleted file mode 100644 index 1f93723..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM8/serial_lld.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM8/serial_lld.c - * @brief STM8 low level serial driver code. - * - * @addtogroup STM8_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/* Because someone somewhere couldn't use the same name for the same thing.*/ -#if STM8_PLATFORM == PLATFORM_STM8AF51AA -#define UART1_BRR1 USART_BRR1 -#define UART1_BRR2 USART_BRR2 -#define UART1_SR USART_SR -#define UART1_DR USART_DR -#define UART1_CR1 USART_CR1 -#define UART1_CR2 USART_CR2 -#define UART1_CR3 USART_CR3 -#define UART1_CR4 USART_CR4 -#define UART1_CR5 USART_CR5 - -#define UART3_BRR1 LINUART_BRR1 -#define UART3_BRR2 LINUART_BRR2 -#define UART3_SR LINUART_SR -#define UART3_DR LINUART_DR -#define UART3_CR1 LINUART_CR1 -#define UART3_CR2 LINUART_CR2 -#define UART3_CR3 LINUART_CR3 -#define UART3_CR4 LINUART_CR4 -#define UART3_CR5 LINUART_CR5 -#define UART3_CR6 LINUART_CR6 -#endif - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief UART1 serial driver identifier. - */ -#if USE_STM8_UART1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** - * @brief UART3 serial driver identifier. - */ -#if USE_STM8_UART3 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static ROMCONST SerialConfig default_config = { - BBR(SERIAL_DEFAULT_BITRATE), - SD_MODE_PARITY_NONE | SD_MODE_STOP_1 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void set_error(SerialDriver *sdp, uint8_t sr) { - sdflags_t sts = 0; - - if (sr & 0x08) /* OR bit. */ - sts |= SD_OVERRUN_ERROR; - if (sr & 0x04) /* NF bit. */ - sts |= SD_NOISE_ERROR; - if (sr & 0x02) /* FE bit. */ - sts |= SD_FRAMING_ERROR; - if (sr & 0x01) /* PE bit. */ - sts |= SD_PARITY_ERROR; - chSysLockFromIsr(); - sdAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -#if USE_STM8_UART1 || defined(__DOXYGEN__) -static void notify1(void) { - - UART1_CR2 |= 0x80; /* TIEN bit. */ -} - -/** - * @brief UART1 initialization. - * - * @param[in] config architecture-dependent serial driver configuration - */ -static void uart1_init(const SerialConfig *config) { - - UART1_BRR2 = ((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | - ((uint8_t)config->sc_brr & (uint8_t)0x0F); - UART1_BRR1 = (uint8_t)(config->sc_brr >> 4); - UART1_CR1 = config->sc_mode & - SD_MODE_PARITY; /* PIEN included. */ - UART1_CR2 = 0x2C; /* RIEN | TEN | REN. */ - UART1_CR3 = config->sc_mode & SD_MODE_STOP; - UART1_CR4 = 0; - UART1_CR5 = 0; - UART1_PSCR = 1; - (void)UART1_SR; - (void)UART1_DR; -} - -/** - * @brief UART1 de-initialization. - */ -static void uart1_deinit(void) { - - UART1_CR1 = 0x20; /* UARTD (low power). */ - UART1_CR2 = 0; - UART1_CR3 = 0; - UART1_CR4 = 0; - UART1_CR5 = 0; - UART1_PSCR = 0; -} -#endif /* USE_STM8_UART1 */ - -#if USE_STM8_UART3 || defined(__DOXYGEN__) -static void notify3(void) { - - UART3_CR2 |= 0x80; /* TIEN bit. */ -} - -/** - * @brief UART3 initialization. - * - * @param[in] config architecture-dependent serial driver configuration - */ -static void uart3_init(const SerialConfig *config) { - - UART3_BRR2 = ((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | - ((uint8_t)config->sc_brr & (uint8_t)0x0F); - UART3_BRR1 = (uint8_t)(config->sc_brr >> 4); - UART3_CR1 = config->sc_mode & - SD_MODE_PARITY; /* PIEN included. */ - UART3_CR2 = 0x2C; /* RIEN | TEN | REN. */ - UART3_CR3 = config->sc_mode & SD_MODE_STOP; - UART3_CR4 = 0; - UART3_CR6 = 0; - (void)UART3_SR; - (void)UART3_DR; -} - -/** - * @brief UART3 de-initialization. - */ -static void uart3_deinit(void) { - - UART3_CR1 = 0x20; /* UARTD (low power). */ - UART3_CR2 = 0; - UART3_CR3 = 0; - UART3_CR4 = 0; - UART3_CR6 = 0; -} -#endif /* USE_STM8_UART3 */ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_STM8_UART1 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(17) { - msg_t b; - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - b = sdRequestDataI(&SD1); - chSysUnlockFromIsr(); - if (b < Q_OK) - UART1_CR2 &= ~0x80; /* TIEN. */ - else - UART1_DR = b; - - CH_IRQ_EPILOGUE(); -} - -CH_IRQ_HANDLER(18) { - uint8_t sr = UART1_SR; - - CH_IRQ_PROLOGUE(); - - if ((sr = UART1_SR) & 0x0F) /* OR | BF | FE | PE. */ - set_error(&SD1, sr); - chSysLockFromIsr(); - sdIncomingDataI(&SD1, UART1_DR); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_STM8_UART1 */ - -#if USE_STM8_UART3 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(20) { - msg_t b; - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - b = sdRequestDataI(&SD3); - chSysUnlockFromIsr(); - if (b < Q_OK) - UART3_CR2 &= ~0x80; /* TIEN. */ - else - UART3_DR = b; - - CH_IRQ_EPILOGUE(); -} - -CH_IRQ_HANDLER(21) { - uint8_t sr = UART3_SR; - - CH_IRQ_PROLOGUE(); - - if ((sr = UART3_SR) & 0x0F) /* OR | BF | FE | PE. */ - set_error(&SD3, sr); - chSysLockFromIsr(); - sdIncomingDataI(&SD3, UART3_DR); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} -#endif /* USE_STM8_UART3 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_STM8_UART1 - sdObjectInit(&SD1, NULL, notify1); - CLK_PCKENR1 |= 4; /* PCKEN12, clock source. */ - UART1_CR1 = 0x20; /* UARTD (low power). */ -#endif - -#if USE_STM8_UART3 - sdObjectInit(&SD3, NULL, notify3); - CLK_PCKENR1 |= 8; /* PCKEN13, clock source. */ - UART3_CR1 = 0x20; /* UARTD (low power). */ -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -#if USE_STM8_UART1 - if (&SD1 == sdp) { - uart1_init(config); - return; - } -#endif -#if USE_STM8_UART3 - if (&SD3 == sdp) { - uart3_init(config); - return; - } -#endif -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - -#if USE_STM8_UART1 - if (&SD1 == sdp) { - uart1_deinit(); - return; - } -#endif -#if USE_STM8_UART3 - if (&SD3 == sdp) { - uart3_deinit(); - return; - } -#endif -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM8/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/STM8/serial_lld.h deleted file mode 100644 index b7baa2c..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM8/serial_lld.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM8/serial_lld.h - * @brief STM8 low level serial driver header. - * - * @addtogroup STM8_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define SD_MODE_PARITY 0x07 /**< @brief Parity field mask. */ -#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ -#define SD_MODE_PARITY_EVEN 0x05 /**< @brief Even parity. */ -#define SD_MODE_PARITY_ODD 0x07 /**< @brief Odd parity. */ - -#define SD_MODE_STOP 0x30 /**< @brief Stop bits mask. */ -#define SD_MODE_STOP_1 0x00 /**< @brief One stop bit. */ -#define SD_MODE_STOP_2 0x20 /**< @brief Two stop bits. */ -#define SD_MODE_STOP_1P5 0x30 /**< @brief 1.5 stop bits. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UART1 driver enable switch. - * @details If set to @p TRUE the support for UART1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM8_UART1) || defined(__DOXYGEN__) -#define USE_STM8_UART1 TRUE -#endif - -/** - * @brief UART3 driver enable switch. - * @details If set to @p TRUE the support for UART3 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_STM8_UART3) || defined(__DOXYGEN__) -#define USE_STM8_UART3 TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint8_t sdflags_t; - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate register. - */ - uint16_t sc_brr; - /** - * @brief Mode flags. - */ - uint8_t sc_mode; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Macro for baud rate computation. - * @note Make sure the final baud rate is within tolerance. - */ -#define BBR(b) (SYSCLK / (b)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_STM8_UART1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_STM8_UART3 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/STM8/stm8.h b/ChibiOS_2.0.8/os/hal/platforms/STM8/stm8.h deleted file mode 100644 index 0eebbff..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/STM8/stm8.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _STM8_H_ -#define _STM8_H_ - -/* - * Supported platforms. - */ -#define PLATFORM_STM8S208RB 1 -#define PLATFORM_STM8AF51AA 2 - -#ifndef STM8_PLATFORM -#error "STM8 platform not defined" -#endif - -#if STM8_PLATFORM == PLATFORM_STM8S208RB -#include "STM8/STM8S208RB.h" -#elif STM8_PLATFORM == PLATFORM_STM8AF51AA -#include "STM8/STM8AF51AA.h" -#else -#error "unsupported or invalid STM8 platform" -#endif - -#endif /* _STM8_H_ */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/console.c b/ChibiOS_2.0.8/os/hal/platforms/Win32/console.c deleted file mode 100644 index 2ae2da4..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/console.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file console.c - * @brief Simulator console driver code. - * @{ - */ - -#include - -#include "ch.h" -#include "console.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Console driver 1. - */ -BaseChannel CD1; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - - -static size_t writes(void *ip, const uint8_t *bp, size_t n) { - size_t ret; - - (void)ip; - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t reads(void *ip, uint8_t *bp, size_t n) { - - (void)ip; - return fread(bp, 1, n, stdin); -} - -static bool_t putwouldblock(void *ip) { - - (void)ip; - return FALSE; -} - -static bool_t getwouldblock(void *ip) { - - (void)ip; - return TRUE; -} - -static msg_t putt(void *ip, uint8_t b, systime_t time) { - - (void)ip; - (void)time; - fputc(b, stdout); - fflush(stdout); - return RDY_OK; -} - -static msg_t gett(void *ip, systime_t time) { - - (void)ip; - (void)time; - return fgetc(stdin); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { - size_t ret; - - (void)ip; - (void)time; - ret = fwrite(bp, 1, n, stdout); - fflush(stdout); - return ret; -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { - - (void)ip; - (void)time; - return fread(bp, 1, n, stdin); -} - -static const struct BaseChannelVMT vmt = { - writes, reads, putwouldblock, getwouldblock, putt, gett, writet, readt -}; - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void conInit(void) { - - CD1.vmt = &vmt; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/console.h b/ChibiOS_2.0.8/os/hal/platforms/Win32/console.h deleted file mode 100644 index 62e4a51..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/console.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file console.h - * @brief Simulator console driver header. - * @{ - */ - -#ifndef _CONSOLE_H_ -#define _CONSOLE_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern BaseChannel CD1; - -#ifdef __cplusplus -extern "C" { -#endif - void conInit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CONSOLE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/hal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/Win32/hal_lld.c deleted file mode 100644 index b4a42ba..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/hal_lld.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Win32/hal_lld.c - * @brief Win32 HAL subsystem low level driver code. - * @addtogroup WIN32_HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -static LARGE_INTEGER nextcnt; -static LARGE_INTEGER slice; - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - */ -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) -const PALConfig pal_default_config = { - {0, 0, 0}, - {0, 0, 0} -}; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - WSADATA wsaData; - - /* Initialization.*/ - if (WSAStartup(2, &wsaData) != 0) { - printf("Unable to locate a winsock DLL\n"); - exit(1); - } - - printf("ChibiOS/RT simulator (Win32)\n"); - if (!QueryPerformanceFrequency(&slice)) { - printf("QueryPerformanceFrequency() error"); - exit(1); - } - slice.QuadPart /= CH_FREQUENCY; - QueryPerformanceCounter(&nextcnt); - nextcnt.QuadPart += slice.QuadPart; - - fflush(stdout); -} - -/** - * @brief Interrupt simulation. - */ -void ChkIntSources(void) { - LARGE_INTEGER n; - -#if CH_HAL_USE_SERIAL - if (sd_lld_interrupt_pending()) { - if (chSchIsRescRequiredExI()) - chSchDoRescheduleI(); - return; - } -#endif - - // Interrupt Timer simulation (10ms interval). - QueryPerformanceCounter(&n); - if (n.QuadPart > nextcnt.QuadPart) { - nextcnt.QuadPart += slice.QuadPart; - chSysTimerHandlerI(); - if (chSchIsRescRequiredExI()) - chSchDoRescheduleI(); - } -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/hal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/Win32/hal_lld.h deleted file mode 100644 index 0fe2ae1..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/hal_lld.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Win32/hal_lld.h - * @brief WIN32 simulator HAL subsystem low level driver header. - * - * @addtogroup WIN32_HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include -#include - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "Win32" - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void ChkIntSources(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/pal_lld.c b/ChibiOS_2.0.8/os/hal/platforms/Win32/pal_lld.c deleted file mode 100644 index 41c904a..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/pal_lld.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Win32/pal_lld.c - * @brief Win32 low level simulated PAL driver code. - * - * @addtogroup WIN32_PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief VIO1 simulated port. - */ -sim_vio_port_t vio_port_1; - -/** - * @brief VIO2 simulated port. - */ -sim_vio_port_t vio_port_2; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @note This function is not meant to be invoked directly by the application - * code. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high - * state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - port->dir &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - port->latch |= mask; - case PAL_MODE_OUTPUT_PUSHPULL: - port->dir |= mask; - break; - } -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/pal_lld.h b/ChibiOS_2.0.8/os/hal/platforms/Win32/pal_lld.h deleted file mode 100644 index d062c5a..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/pal_lld.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Win32/pal_lld.h - * @brief Win32 low level simulated PAL driver header. - * - * @addtogroup WIN32_PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_OUTPUT_OPENDRAIN -#undef PAL_MODE_INPUT_ANALOG - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief VIO port structure. - */ -typedef struct { - /** - * @brief VIO_LATCH register. - * @details This register represents the output latch of the VIO port. - */ - uint32_t latch; - /** - * @brief VIO_PIN register. - * @details This register represents the logical level at the VIO port - * pin level. - */ - uint32_t pin; - /** - * @brief VIO_DIR register. - * @details Direction of the VIO port bits, 0=input, 1=output. - */ - uint32_t dir; -} sim_vio_port_t; - -/** - * @brief Virtual I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { - /** - * @brief Virtual port 1 setup data. - */ - sim_vio_port_t VP1Data; - /** - * @brief Virtual port 2 setup data. - */ - sim_vio_port_t VP2Data; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Port Identifier. - */ -typedef sim_vio_port_t *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief VIO port 1 identifier. - */ -#define IOPORT1 (&vio_port_1) - -/** - * @brief VIO port 2 identifier. - */ -#define IOPORT2 (&vio_port_2) - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - */ -#define pal_lld_init(config) { \ - vio_port_1 = (config)->VP1Data; \ - vio_port_2 = (config)->VP2Data; \ -} - -/** - * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The port bits. - */ -#define pal_lld_readport(port) ((port)->pin) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The latched logical states. - */ -#define pal_lld_readlatch(port) ((port)->latch) - -/** - * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - */ -#define pal_lld_writeport(port, bits) ((port)->latch = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] mode group mode - */ -#define pal_lld_setgroupmode(port, mask, mode) \ - _pal_lld_setgroupmode(port, mask, mode) - -#if !defined(__DOXYGEN__) -extern sim_vio_port_t vio_port_1; -extern sim_vio_port_t vio_port_2; -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - uint_fast8_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/platform.mk b/ChibiOS_2.0.8/os/hal/platforms/Win32/platform.mk deleted file mode 100644 index afc9284..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/platform.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of all the Win32 platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Win32/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/Win32/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/Win32/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Win32 diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/serial_lld.c b/ChibiOS_2.0.8/os/hal/platforms/Win32/serial_lld.c deleted file mode 100644 index ad391fd..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/serial_lld.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Win32/serial_lld.c - * @brief Win32 low level simulated serial driver code. - * @addtogroup WIN32_SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief Serial driver 1 identifier.*/ -#if USE_WIN32_SERIAL1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif -/** @brief Serial driver 2 identifier.*/ -#if USE_WIN32_SERIAL2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { -}; - -static u_long nb = 1; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void init(SerialDriver *sdp, uint16_t port) { - struct sockaddr_in sad; - struct protoent *prtp; - - if ((prtp = getprotobyname("tcp")) == NULL) { - printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name); - goto abort; - } - - sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto); - if (sdp->com_listen == INVALID_SOCKET) { - printf("%s: Error creating simulator socket\n", sdp->com_name); - goto abort; - } - - if (ioctlsocket(sdp->com_listen, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name); - goto abort; - } - - memset(&sad, 0, sizeof(sad)); - sad.sin_family = AF_INET; - sad.sin_addr.s_addr = INADDR_ANY; - sad.sin_port = htons(port); - if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) { - printf("%s: Error binding socket\n", sdp->com_name); - goto abort; - } - - if (listen(sdp->com_listen, 1) != 0) { - printf("%s: Error listening socket\n", sdp->com_name); - goto abort; - } - printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port); - return; - -abort: - if (sdp->com_listen != INVALID_SOCKET) - closesocket(sdp->com_listen); - WSACleanup(); - exit(1); -} - -static bool_t connint(SerialDriver *sdp) { - - if (sdp->com_data == INVALID_SOCKET) { - struct sockaddr addr; - int addrlen = sizeof(addr); - - if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET) - return FALSE; - - if (ioctlsocket(sdp->com_data, FIONBIO, &nb) != 0) { - printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name); - goto abort; - } - sdAddFlagsI(sdp, SD_CONNECTED); - return TRUE; - } - return FALSE; -abort: - if (sdp->com_listen != INVALID_SOCKET) - closesocket(sdp->com_listen); - if (sdp->com_data != INVALID_SOCKET) - closesocket(sdp->com_data); - WSACleanup(); - exit(1); -} - -static bool_t inint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int i; - uint8_t data[32]; - - /* - * Input. - */ - int n = recv(sdp->com_data, data, sizeof(data), 0); - switch (n) { - case 0: - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - sdAddFlagsI(sdp, SD_DISCONNECTED); - return FALSE; - case SOCKET_ERROR: - if (WSAGetLastError() == WSAEWOULDBLOCK) - return FALSE; - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - for (i = 0; i < n; i++) - sdIncomingDataI(sdp, data[i]); - return TRUE; - } - return FALSE; -} - -static bool_t outint(SerialDriver *sdp) { - - if (sdp->com_data != INVALID_SOCKET) { - int n; - uint8_t data[1]; - - /* - * Input. - */ - n = sdRequestDataI(sdp); - if (n < 0) - return FALSE; - data[0] = (uint8_t)n; - n = send(sdp->com_data, data, sizeof(data), 0); - switch (n) { - case 0: - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - sdAddFlagsI(sdp, SD_DISCONNECTED); - return FALSE; - case SOCKET_ERROR: - if (WSAGetLastError() == WSAEWOULDBLOCK) - return FALSE; - closesocket(sdp->com_data); - sdp->com_data = INVALID_SOCKET; - return FALSE; - } - return TRUE; - } - return FALSE; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * Low level serial driver initialization. - */ -void sd_lld_init(void) { - -#if USE_WIN32_SERIAL1 - sdObjectInit(&SD1, NULL, NULL); - SD1.com_listen = INVALID_SOCKET; - SD1.com_data = INVALID_SOCKET; - SD1.com_name = "SD1"; -#endif - -#if USE_WIN32_SERIAL1 - sdObjectInit(&SD2, NULL, NULL); - SD2.com_listen = INVALID_SOCKET; - SD2.com_data = INVALID_SOCKET; - SD2.com_name = "SD2"; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -#if USE_WIN32_SERIAL1 - if (sdp == &SD1) - init(&SD1, SD1_PORT); -#endif - -#if USE_WIN32_SERIAL1 - if (sdp == &SD2) - init(&SD2, SD2_PORT); -#endif -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - - (void)sdp; -} - -bool_t sd_lld_interrupt_pending(void) { - - return connint(&SD1) || connint(&SD2) || - inint(&SD1) || inint(&SD2) || - outint(&SD1) || outint(&SD2); -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/platforms/Win32/serial_lld.h b/ChibiOS_2.0.8/os/hal/platforms/Win32/serial_lld.h deleted file mode 100644 index edd2632..0000000 --- a/ChibiOS_2.0.8/os/hal/platforms/Win32/serial_lld.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file Win32/serial_lld.h - * @brief Win32 low level simulated serial driver header. - * - * @addtogroup WIN32_SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 1024 -#endif - -/** - * @brief SD1 driver enable switch. - * @details If set to @p TRUE the support for SD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_WIN32_SERIAL1) || defined(__DOXYGEN__) -#define USE_WIN32_SERIAL1 TRUE -#endif - -/** - * @brief SD2 driver enable switch. - * @details If set to @p TRUE the support for SD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_WIN32_SERIAL2) || defined(__DOXYGEN__) -#define USE_WIN32_SERIAL2 TRUE -#endif - -/** - * @brief Listen port for SD1. - */ -#if !defined(SD1_PORT) || defined(__DOXYGEN__) -#define SD1_PORT 29001 -#endif - -/** - * @brief Listen port for SD2. - */ -#if !defined(SD2_PORT) || defined(__DOXYGEN__) -#define SD2_PORT 29002 -#endif - -/*===========================================================================*/ -/* Unsupported event flags and custom events. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint32_t sdflags_t; - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Listen socket for simulated serial port.*/ \ - SOCKET com_listen; \ - /* Data socket for simulated serial port.*/ \ - SOCKET com_data; \ - /* Port readable name.*/ \ - const char *com_name; - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_WIN32_SERIAL1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_WIN32_SERIAL2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); - bool_t sd_lld_interrupt_pending(void); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/adc.c b/ChibiOS_2.0.8/os/hal/src/adc.c deleted file mode 100644 index 293173d..0000000 --- a/ChibiOS_2.0.8/os/hal/src/adc.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file adc.c - * @brief ADC Driver code. - * - * @addtogroup ADC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief ADC Driver initialization. - */ -void adcInit(void) { - - adc_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p ADCDriver structure. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adcObjectInit(ADCDriver *adcp) { - - adcp->ad_state = ADC_STOP; - adcp->ad_config = NULL; - adcp->ad_callback = NULL; - adcp->ad_samples = NULL; - adcp->ad_depth = 0; - adcp->ad_grpp = NULL; - chSemInit(&adcp->ad_sem, 0); -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] config pointer to the @p ADCConfig object - */ -void adcStart(ADCDriver *adcp, const ADCConfig *config) { - - chDbgCheck((adcp != NULL) && (config != NULL), "adcStart"); - - chSysLock(); - chDbgAssert((adcp->ad_state == ADC_STOP) || (adcp->ad_state == ADC_READY), - "adcStart(), #1", - "invalid state"); - adcp->ad_config = config; - adc_lld_start(adcp); - adcp->ad_state = ADC_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adcStop(ADCDriver *adcp) { - - chDbgCheck(adcp != NULL, "adcStop"); - - chSysLock(); - chDbgAssert((adcp->ad_state == ADC_STOP) || - (adcp->ad_state == ADC_READY) || - (adcp->ad_state == ADC_COMPLETE), - "adcStop(), #1", - "invalid state"); - adc_lld_stop(adcp); - adcp->ad_state = ADC_STOP; - chSysUnlock(); -} - -/** - * @brief Starts an ADC conversion. - * @details Starts a conversion operation, there are two kind of conversion - * modes: - * - LINEAR, in this mode the buffer is filled once and then - * the conversion stops automatically. - * - CIRCULAR, in this mode the conversion never stops and - * the buffer is filled circularly.
- * During the conversion the callback function is invoked when - * the buffer is 50% filled and when the buffer is 100% filled, - * this way is possible to process the conversion stream in real - * time. This kind of conversion can only be stopped by explicitly - * invoking @p adcStopConversion(). - * . - * @note The buffer is organized as a matrix of M*N elements where M is the - * channels number configured into the conversion group and N is the - * buffer depth. The samples are sequentially written into the buffer - * with no gaps. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] grpp pointer to a @p ADCConversionGroup object - * @param[out] samples pointer to the samples buffer - * @param[in] depth buffer depth (matrix rows number). The buffer depth - * must be one or an even number. - * @param[in] callback pointer to the conversion callback function, this - * parameter can be @p NULL if a callback is not required - * @return The operation status. - * @retval FALSE the conversion has been started. - * @retval TRUE the driver is busy, conversion not started. - */ -bool_t adcStartConversion(ADCDriver *adcp, - const ADCConversionGroup *grpp, - adcsample_t *samples, - size_t depth, - adccallback_t callback) { - - chDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) && - ((depth == 1) || ((depth & 1) == 0)), - "adcStartConversion"); - - chSysLock(); - chDbgAssert((adcp->ad_state == ADC_READY) || - (adcp->ad_state == ADC_RUNNING) || - (adcp->ad_state == ADC_COMPLETE), - "adcStartConversion(), #1", - "invalid state"); - if (adcp->ad_state == ADC_RUNNING) { - chSysUnlock(); - return TRUE; - } - adcp->ad_callback = callback; - adcp->ad_samples = samples; - adcp->ad_depth = depth; - adcp->ad_grpp = grpp; - adc_lld_start_conversion(adcp); - adcp->ad_state = ADC_RUNNING; - chSysUnlock(); - return FALSE; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adcStopConversion(ADCDriver *adcp) { - - chDbgCheck(adcp != NULL, "adcStopConversion"); - - chSysLock(); - chDbgAssert((adcp->ad_state == ADC_READY) || - (adcp->ad_state == ADC_RUNNING) || - (adcp->ad_state == ADC_COMPLETE), - "adcStopConversion(), #1", - "invalid state"); - if (adcp->ad_state == ADC_RUNNING) { - adc_lld_stop_conversion(adcp); - adcp->ad_grpp = NULL; - adcp->ad_state = ADC_READY; - chSemResetI(&adcp->ad_sem, 0); - chSchRescheduleS(); - } - else - adcp->ad_state = ADC_READY; - chSysUnlock(); -} - -/** - * @brief Waits for completion. - * @details If the conversion is not completed or not yet started then the - * invoking thread waits for a conversion completion event. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation result. - * @retval RDY_OK conversion finished. - * @retval RDY_TIMEOUT conversion not finished within the specified time. - */ -msg_t adcWaitConversion(ADCDriver *adcp, systime_t timeout) { - - chSysLock(); - chDbgAssert((adcp->ad_state == ADC_READY) || - (adcp->ad_state == ADC_RUNNING) || - (adcp->ad_state == ADC_COMPLETE), - "adcWaitConversion(), #1", - "invalid state"); - if (adcp->ad_state != ADC_COMPLETE) { - if (chSemWaitTimeoutS(&adcp->ad_sem, timeout) == RDY_TIMEOUT) { - chSysUnlock(); - return RDY_TIMEOUT; - } - } - chSysUnlock(); - return RDY_OK; -} - -#endif /* CH_HAL_USE_ADC */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/can.c b/ChibiOS_2.0.8/os/hal/src/can.c deleted file mode 100644 index ce87120..0000000 --- a/ChibiOS_2.0.8/os/hal/src/can.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file can.c - * @brief CAN Driver code. - * - * @addtogroup CAN - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief CAN Driver initialization. - */ -void canInit(void) { - - can_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p CANDriver structure. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void canObjectInit(CANDriver *canp) { - - canp->cd_state = CAN_STOP; - canp->cd_config = NULL; - chSemInit(&canp->cd_txsem, 0); - chSemInit(&canp->cd_rxsem, 0); - chEvtInit(&canp->cd_rxfull_event); - chEvtInit(&canp->cd_txempty_event); - chEvtInit(&canp->cd_error_event); - canp->cd_status = 0; -#if CAN_USE_SLEEP_MODE - chEvtInit(&canp->cd_sleep_event); - chEvtInit(&canp->cd_wakeup_event); -#endif /* CAN_USE_SLEEP_MODE */ -} - -/** - * @brief Configures and activates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] config pointer to the @p CANConfig object - */ -void canStart(CANDriver *canp, const CANConfig *config) { - - chDbgCheck((canp != NULL) && (config != NULL), "canStart"); - - chSysLock(); - chDbgAssert((canp->cd_state == CAN_STOP) || - (canp->cd_state == CAN_STARTING) || - (canp->cd_state == CAN_READY), - "canStart(), #1", - "invalid state"); - while (canp->cd_state == CAN_STARTING) - chThdSleepS(1); - if (canp->cd_state == CAN_STOP) { - canp->cd_config = config; - can_lld_start(canp); - canp->cd_state = CAN_READY; - } - chSysUnlock(); -} - -/** - * @brief Deactivates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void canStop(CANDriver *canp) { - - chDbgCheck(canp != NULL, "canStop"); - - chSysLock(); - chDbgAssert((canp->cd_state == CAN_STOP) || (canp->cd_state == CAN_READY), - "canStop(), #1", - "invalid state"); - can_lld_stop(canp); - chSemResetI(&canp->cd_rxsem, 0); - chSemResetI(&canp->cd_txsem, 0); - chSchRescheduleS(); - canp->cd_state = CAN_STOP; - canp->cd_status = 0; - chSysUnlock(); -} - -/** - * @brief Can frame transmission. - * @details The specified frame is queued for transmission, if the hardware - * queue is full then the invoking thread is queued. - * @note Trying to transmit while in sleep mode simply enqueues the thread. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] ctfp pointer to the CAN frame to be transmitted - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation result. - * @retval RDY_OK the frame has been queued for transmission. - * @retval RDY_TIMEOUT operation not finished within the specified time. - * @retval RDY_RESET driver stopped while waiting. - */ -msg_t canTransmit(CANDriver *canp, const CANTxFrame *ctfp, systime_t timeout) { - - chDbgCheck((canp != NULL) && (ctfp != NULL), "canTransmit"); - - chSysLock(); - chDbgAssert((canp->cd_state == CAN_READY) || (canp->cd_state == CAN_SLEEP), - "canTransmit(), #1", - "invalid state"); - while ((canp->cd_state == CAN_SLEEP) || !can_lld_can_transmit(canp)) { - msg_t msg = chSemWaitTimeoutS(&canp->cd_txsem, timeout); - if (msg != RDY_OK) { - chSysUnlock(); - return msg; - } - } - can_lld_transmit(canp, ctfp); - chSysUnlock(); - return RDY_OK; -} - -/** - * @brief Can frame receive. - * @details The function waits until a frame is received. - * @note Trying to receive while in sleep mode simply enqueues the thread. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[out] crfp pointer to the buffer where the CAN frame is copied - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout (useful in an - * event driven scenario where a thread never blocks - * for I/O). - * - @a TIME_INFINITE no timeout. - * . - * @return The operation result. - * @retval RDY_OK a frame has been received and placed in the buffer. - * @retval RDY_TIMEOUT operation not finished within the specified time or - * frame not immediately available if invoked using - * @p TIME_IMMEDIATE. - * @retval RDY_RESET driver stopped while waiting. - */ -msg_t canReceive(CANDriver *canp, CANRxFrame *crfp, systime_t timeout) { - - chDbgCheck((canp != NULL) && (crfp != NULL), "canReceive"); - - chSysLock(); - chDbgAssert((canp->cd_state == CAN_READY) || (canp->cd_state == CAN_SLEEP), - "canReceive(), #1", - "invalid state"); - while ((canp->cd_state == CAN_SLEEP) || !can_lld_can_receive(canp)) { - msg_t msg = chSemWaitTimeoutS(&canp->cd_rxsem, timeout); - if (msg != RDY_OK) { - chSysUnlock(); - return msg; - } - } - can_lld_receive(canp, crfp); - chSysUnlock(); - return RDY_OK; -} - -/** - * @brief Returns the current status mask and clears it. - * - * @param[in] canp pointer to the @p CANDriver object - * @return The status flags mask. - */ -canstatus_t canGetAndClearFlags(CANDriver *canp) { - canstatus_t status; - - chSysLock(); - status = canp->cd_status; - canp->cd_status = 0; - chSysUnlock(); - return status; -} - -#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) -/** - * @brief Enters the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void canSleep(CANDriver *canp) { - - chDbgCheck(canp != NULL, "canSleep"); - - chSysLock(); - chDbgAssert((canp->cd_state == CAN_READY) || (canp->cd_state == CAN_SLEEP), - "canSleep(), #1", - "invalid state"); - if (canp->cd_state == CAN_READY) { - can_lld_sleep(canp); - canp->cd_state = CAN_SLEEP; - chEvtBroadcastI(&canp->cd_sleep_event); - chSchRescheduleS(); - } - chSysUnlock(); -} - -/** - * @brief Enforces leaving the sleep mode. - * @note The sleep mode is supposed to be usually exited automatically by - * an hardware event. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void canWakeup(CANDriver *canp) { - - chDbgCheck(canp != NULL, "canWakeup"); - - chSysLock(); - chDbgAssert((canp->cd_state == CAN_READY) || (canp->cd_state == CAN_SLEEP), - "canWakeup(), #1", - "invalid state"); - if (canp->cd_state == CAN_SLEEP) { - can_lld_wakeup(canp); - canp->cd_state = CAN_READY; - chEvtBroadcastI(&canp->cd_wakeup_event); - chSchRescheduleS(); - } - chSysUnlock(); -} -#endif /* CAN_USE_SLEEP_MODE */ - -#endif /* CH_HAL_USE_CAN */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/hal.c b/ChibiOS_2.0.8/os/hal/src/hal.c deleted file mode 100644 index 3dfe6f9..0000000 --- a/ChibiOS_2.0.8/os/hal/src/hal.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file hal.c - * @brief HAL subsystem code. - * - * @addtogroup HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief HAL initialization. - */ -void halInit(void) { - - hal_lld_init(); - -#if CH_HAL_USE_PAL - palInit(&pal_default_config); -#endif -#if CH_HAL_USE_ADC - adcInit(); -#endif -#if CH_HAL_USE_CAN - canInit(); -#endif -#if CH_HAL_USE_MAC - macInit(); -#endif -#if CH_HAL_USE_PWM - pwmInit(); -#endif -#if CH_HAL_USE_SERIAL - sdInit(); -#endif -#if CH_HAL_USE_SPI - spiInit(); -#endif -#if CH_HAL_USE_MMC_SPI - mmcInit(); -#endif -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/mac.c b/ChibiOS_2.0.8/os/hal/src/mac.c deleted file mode 100644 index 8a87ca5..0000000 --- a/ChibiOS_2.0.8/os/hal/src/mac.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mac.c - * @brief MAC Driver code. - * - * @addtogroup MAC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief MAC Driver initialization. - */ -void macInit(void) { - - mac_lld_init(); -} - -/** - * @brief Initialize the standard part of a @p MACDriver structure. - * - * @param[in] macp pointer to the @p MACDriver object - */ -void macObjectInit(MACDriver *macp) { - - chSemInit(&macp->md_tdsem, 0); - chSemInit(&macp->md_rdsem, 0); -#if CH_USE_EVENTS - chEvtInit(&macp->md_rdevent); -#endif -} - -/** - * @brief MAC address setup. - * @note This function must be invoked only with the driver in the stopped - * state. If invoked on an active interface then it is ignored. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] p pointer to a six bytes buffer containing the MAC - * address. If this parameter is set to @p NULL then MAC - * a system default is used. - * - */ -void macSetAddress(MACDriver *macp, const uint8_t *p) { - - mac_lld_set_address(macp, p); -} - -/** - * @brief Allocates a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. If a descriptor is not currently available then the - * invoking thread is queued until one is freed. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK the descriptor was obtained. - * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized. - */ -msg_t macWaitTransmitDescriptor(MACDriver *macp, - MACTransmitDescriptor *tdp, - systime_t time) { - msg_t msg; - - while (((msg = max_lld_get_transmit_descriptor(macp, tdp)) != RDY_OK) && - (time > 0)) { - chSysLock(); - systime_t now = chTimeNow(); - if ((msg = chSemWaitTimeoutS(&macp->md_tdsem, time)) == RDY_TIMEOUT) - break; - if (time != TIME_INFINITE) - time -= (chTimeNow() - now); - chSysUnlock(); - } - return msg; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - */ -void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) { - - mac_lld_release_transmit_descriptor(tdp); -} - -/** - * @brief Waits for a received frame. - * @details Stops until a frame is received and buffered. If a frame is - * not immediately available then the invoking thread is queued - * until one is received. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK the descriptor was obtained. - * @retval RDY_TIMEOUT the operation timed out, descriptor not initialized. - */ -msg_t macWaitReceiveDescriptor(MACDriver *macp, - MACReceiveDescriptor *rdp, - systime_t time) { - msg_t msg; - - while (((msg = max_lld_get_receive_descriptor(macp, rdp)) != RDY_OK) && - (time > 0)) { - chSysLock(); - systime_t now = chTimeNow(); - if ((msg = chSemWaitTimeoutS(&macp->md_rdsem, time)) == RDY_TIMEOUT) - break; - if (time != TIME_INFINITE) - time -= (chTimeNow() - now); - chSysUnlock(); - } - return msg; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - */ -void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) { - - mac_lld_release_receive_descriptor(rdp); -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval TRUE if the link is active. - * @retval FALSE if the link is down. - */ -bool_t macPollLinkStatus(MACDriver *macp) { - - return mac_lld_poll_link_status(macp); -} - -#endif /* CH_HAL_USE_MAC */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/mmc_spi.c b/ChibiOS_2.0.8/os/hal/src/mmc_spi.c deleted file mode 100644 index ab86998..0000000 --- a/ChibiOS_2.0.8/os/hal/src/mmc_spi.c +++ /dev/null @@ -1,597 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file mmc_spi.c - * @brief MMC over SPI driver code. - * - * @addtogroup MMC_SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_MMC_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Inserion monitor timer callback function. - * - * @param[in] p pointer to the @p MMCDriver object - */ -void tmrfunc(void *p) { - MMCDriver *mmcp = p; - - if (mmcp->mmc_cnt > 0) { - if (mmcp->mmc_is_inserted()) { - if (--mmcp->mmc_cnt == 0) { - mmcp->mmc_state = MMC_INSERTED; - chEvtBroadcastI(&mmcp->mmc_inserted_event); - } - } - else - mmcp->mmc_cnt = MMC_POLLING_INTERVAL; - } - else { - if (!mmcp->mmc_is_inserted()) { - mmcp->mmc_state = MMC_WAIT; - mmcp->mmc_cnt = MMC_POLLING_INTERVAL; - chEvtBroadcastI(&mmcp->mmc_removed_event); - } - } - chVTSetI(&mmcp->mmc_vt, MS2ST(MMC_POLLING_DELAY), tmrfunc, mmcp); -} - -/** - * @brief Waits an idle condition. - * - * @param[in] mmcp pointer to the @p MMCDriver object - */ -static void wait(MMCDriver *mmcp) { - int i; - uint8_t buf[4]; - - for (i = 0; i < 16; i++) { - spiReceive(mmcp->mmc_spip, 1, buf); - if (buf[0] == 0xFF) - break; - } - /* Looks like it is a long wait.*/ - while (TRUE) { - spiReceive(mmcp->mmc_spip, 1, buf); - if (buf[0] == 0xFF) - break; -#ifdef MMC_NICE_WAITING - /* Trying to be nice with the other threads.*/ - chThdSleep(1); -#endif - } -} - -/** - * @brief Sends a command header. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param cmd[in] the command id - * @param arg[in] the command argument - */ -static void send_hdr(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { - uint8_t buf[6]; - - /* Wait for the bus to become idle if a write operation was in progress. */ - wait(mmcp); - - buf[0] = 0x40 | cmd; - buf[1] = arg >> 24; - buf[2] = arg >> 16; - buf[3] = arg >> 8; - buf[4] = arg; - buf[5] = 0x95; /* Valid for CMD0 ignored by other commands. */ - spiSend(mmcp->mmc_spip, 6, buf); -} - -/** - * @brief Receives a single byte response. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The response as an @p uint8_t value. - * @retval 0xFF timed out. - */ -static uint8_t recvr1(MMCDriver *mmcp) { - int i; - uint8_t r1[1]; - - for (i = 0; i < 9; i++) { - spiReceive(mmcp->mmc_spip, 1, r1); - if (r1[0] != 0xFF) - return r1[0]; - } - return 0xFF; -} - -/** - * @brief Sends a command an returns a single byte response. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param cmd[in] the command id - * @param arg[in] the command argument - * @return The response as an @p uint8_t value. - * @retval 0xFF timed out. - */ -static uint8_t send_command(MMCDriver *mmcp, uint8_t cmd, uint32_t arg) { - uint8_t r1; - - spiSelect(mmcp->mmc_spip); - send_hdr(mmcp, cmd, arg); - r1 = recvr1(mmcp); - spiUnselect(mmcp->mmc_spip); - return r1; -} - -/** - * @brief Waits that the card reaches an idle state. - * - * @param[in] mmcp pointer to the @p MMCDriver object - */ -static void sync(MMCDriver *mmcp) { - uint8_t buf[1]; - - spiSelect(mmcp->mmc_spip); - while (TRUE) { - spiReceive(mmcp->mmc_spip, 1, buf); - if (buf[0] == 0xFF) - break; -#ifdef MMC_NICE_WAITING - chThdSleep(1); /* Trying to be nice with the other threads.*/ -#endif - } - spiUnselect(mmcp->mmc_spip); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief MMC over SPI driver initialization. - */ -void mmcInit(void) { - -} - -/** - * @brief Initializes an instance. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] spip pointer to the SPI driver to be used as interface - * @param[in] lscfg low speed configuration for the SPI driver - * @param[in] hscfg high speed configuration for the SPI driver - * @param[in] is_protected function that returns the card write protection - * setting - * @param[in] is_inserted function that returns the card insertion sensor - * status - */ -void mmcObjectInit(MMCDriver *mmcp, SPIDriver *spip, - const SPIConfig *lscfg, const SPIConfig *hscfg, - mmcquery_t is_protected, mmcquery_t is_inserted) { - - mmcp->mmc_state = MMC_STOP; - mmcp->mmc_config = NULL; - mmcp->mmc_spip = spip; - mmcp->mmc_lscfg = lscfg; - mmcp->mmc_hscfg = hscfg; - mmcp->mmc_is_protected = is_protected; - mmcp->mmc_is_inserted = is_inserted; - chEvtInit(&mmcp->mmc_inserted_event); - chEvtInit(&mmcp->mmc_removed_event); -} - -/** - * @brief Configures and activates the MMC peripheral. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] config pointer to the @p MMCConfig object - */ -void mmcStart(MMCDriver *mmcp, const MMCConfig *config) { - - chDbgCheck((mmcp != NULL) && (config != NULL), "mmcStart"); - - chSysLock(); - chDbgAssert(mmcp->mmc_state == MMC_STOP, "mmcStart(), #1", "invalid state"); - mmcp->mmc_config = config; - mmcp->mmc_state = MMC_WAIT; - mmcp->mmc_cnt = MMC_POLLING_INTERVAL; - chVTSetI(&mmcp->mmc_vt, MS2ST(MMC_POLLING_DELAY), tmrfunc, mmcp); - chSysUnlock(); -} - -/** - * @brief Disables the MMC peripheral. - * - * @param[in] mmcp pointer to the @p MMCDriver object - */ -void mmcStop(MMCDriver *mmcp) { - - chDbgCheck(mmcp != NULL, "mmcStop"); - - chSysLock(); - chDbgAssert((mmcp->mmc_state != MMC_UNINIT) && - (mmcp->mmc_state != MMC_READING) && - (mmcp->mmc_state != MMC_WRITING), - "mmcStop(), #1", - "invalid state"); - if (mmcp->mmc_state != MMC_STOP) { - mmcp->mmc_state = MMC_STOP; - chVTResetI(&mmcp->mmc_vt); - } - chSysUnlock(); - spiStop(mmcp->mmc_spip); -} - -/** - * @brief Performs the initialization procedure on the inserted card. - * @details This function should be invoked when a card is inserted and - * brings the driver in the @p MMC_READY state where it is possible - * to perform read and write operations. - * @note It is possible to invoke this function from the insertion event - * handler. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The operation status. - * @retval FALSE the operation was successful and the driver is now - * in the @p MMC_READY state. - * @retval TRUE the operation failed. - */ -bool_t mmcConnect(MMCDriver *mmcp) { - unsigned i; - bool_t result; - - chDbgCheck(mmcp != NULL, "mmcConnect"); - - chDbgAssert((mmcp->mmc_state != MMC_UNINIT) && - (mmcp->mmc_state != MMC_STOP), - "mmcConnect(), #1", - "invalid state"); - - if (mmcp->mmc_state == MMC_INSERTED) { - /* Slow clock mode and 128 clock pulses.*/ - spiStart(mmcp->mmc_spip, mmcp->mmc_lscfg); - spiIgnore(mmcp->mmc_spip, 16); - - /* SPI mode selection.*/ - i = 0; - while (TRUE) { - if (send_command(mmcp, MMC_CMDGOIDLE, 0) == 0x01) - break; - if (++i >= MMC_CMD0_RETRY) - return TRUE; - chThdSleepMilliseconds(10); - } - - /* Initialization. */ - i = 0; - while (TRUE) { - uint8_t b = send_command(mmcp, MMC_CMDINIT, 0); - if (b == 0x00) - break; - if (b != 0x01) - return TRUE; - if (++i >= MMC_CMD1_RETRY) - return TRUE; - chThdSleepMilliseconds(10); - } - - /* Initialization complete, full speed. */ - spiStart(mmcp->mmc_spip, mmcp->mmc_hscfg); - - /* Setting block size.*/ - if (send_command(mmcp, MMC_CMDSETBLOCKLEN, MMC_SECTOR_SIZE) != 0x00) - return TRUE; - - /* Transition to MMC_READY state (if not extracted).*/ - chSysLock(); - if (mmcp->mmc_state == MMC_INSERTED) { - mmcp->mmc_state = MMC_READY; - result = FALSE; - } - else - result = TRUE; - chSysUnlock(); - return result; - } - if (mmcp->mmc_state == MMC_READY) - return FALSE; - /* Any other state is invalid.*/ - return TRUE; -} - -/** - * @brief Brings the driver in a state safe for card removal. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The operation status. - * @retval FALSE the operation was successful and the driver is now - * in the @p MMC_INSERTED state. - * @retval TRUE the operation failed. - */ -bool_t mmcDisconnect(MMCDriver *mmcp) { - bool_t status; - - chDbgCheck(mmcp != NULL, "mmcDisconnect"); - - chDbgAssert((mmcp->mmc_state != MMC_UNINIT) && - (mmcp->mmc_state != MMC_STOP), - "mmcDisconnect(), #1", - "invalid state"); - switch (mmcp->mmc_state) { - case MMC_READY: - /* Wait for the pending write operations to complete.*/ - sync(mmcp); - chSysLock(); - if (mmcp->mmc_state == MMC_READY) - mmcp->mmc_state = MMC_INSERTED; - chSysUnlock(); - case MMC_INSERTED: - status = FALSE; - default: - status = TRUE; - } - spiStop(mmcp->mmc_spip); - return status; -} - -/** - * @brief Starts a sequential read. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] startblk first block to read - * @return The operation status. - * @retval FALSE the operation was successful. - * @retval TRUE the operation failed. - */ -bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) { - - chDbgCheck(mmcp != NULL, "mmcStartSequentialRead"); - - chSysLock(); - if (mmcp->mmc_state != MMC_READY) { - chSysUnlock(); - return TRUE; - } - mmcp->mmc_state = MMC_READING; - chSysUnlock(); - - spiStart(mmcp->mmc_spip, mmcp->mmc_hscfg); - spiSelect(mmcp->mmc_spip); - send_hdr(mmcp, MMC_CMDREADMULTIPLE, startblk * MMC_SECTOR_SIZE); - if (recvr1(mmcp) != 0x00) { - spiUnselect(mmcp->mmc_spip); - chSysLock(); - if (mmcp->mmc_state == MMC_READING) - mmcp->mmc_state = MMC_READY; - chSysUnlock(); - return TRUE; - } - return FALSE; -} - -/** - * @brief Reads a block within a sequential read operation. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] buffer pointer to the read buffer - * @return The operation status. - * @retval FALSE the operation was successful. - * @retval TRUE the operation failed. - */ -bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) { - int i; - - chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialRead"); - - chSysLock(); - if (mmcp->mmc_state != MMC_READING) { - chSysUnlock(); - return TRUE; - } - chSysUnlock(); - - for (i = 0; i < MMC_WAIT_DATA; i++) { - spiReceive(mmcp->mmc_spip, 1, buffer); - if (buffer[0] == 0xFE) { - spiReceive(mmcp->mmc_spip, MMC_SECTOR_SIZE, buffer); - /* CRC ignored. */ - spiIgnore(mmcp->mmc_spip, 2); - return FALSE; - } - } - /* Timeout.*/ - spiUnselect(mmcp->mmc_spip); - chSysLock(); - if (mmcp->mmc_state == MMC_READING) - mmcp->mmc_state = MMC_READY; - chSysUnlock(); - return TRUE; -} - -/** - * @brief Stops a sequential read gracefully. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The operation status. - * @retval FALSE the operation was successful. - * @retval TRUE the operation failed. - */ -bool_t mmcStopSequentialRead(MMCDriver *mmcp) { - static const uint8_t stopcmd[] = {0x40 | MMC_CMDSTOP, 0, 0, 0, 0, 1, 0xFF}; - bool_t result; - - chDbgCheck(mmcp != NULL, "mmcStopSequentialRead"); - - chSysLock(); - if (mmcp->mmc_state != MMC_READING) { - chSysUnlock(); - return TRUE; - } - chSysUnlock(); - - spiSend(mmcp->mmc_spip, sizeof(stopcmd), stopcmd); -/* result = recvr1(mmcp) != 0x00;*/ - /* Note, ignored r1 response, it can be not zero, unknown issue.*/ - recvr1(mmcp); - result = FALSE; - spiUnselect(mmcp->mmc_spip); - - chSysLock(); - if (mmcp->mmc_state == MMC_READING) - mmcp->mmc_state = MMC_READY; - chSysUnlock(); - return result; -} - -/** - * @brief Starts a sequential write. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[in] startblk first block to write - * @return The operation status. - * @retval FALSE the operation was successful. - * @retval TRUE the operation failed. - */ -bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) { - - chDbgCheck(mmcp != NULL, "mmcStartSequentialWrite"); - - chSysLock(); - if (mmcp->mmc_state != MMC_READY) { - chSysUnlock(); - return TRUE; - } - mmcp->mmc_state = MMC_WRITING; - chSysUnlock(); - - spiStart(mmcp->mmc_spip, mmcp->mmc_hscfg); - spiSelect(mmcp->mmc_spip); - send_hdr(mmcp, MMC_CMDWRITEMULTIPLE, startblk * MMC_SECTOR_SIZE); - if (recvr1(mmcp) != 0x00) { - spiUnselect(mmcp->mmc_spip); - chSysLock(); - if (mmcp->mmc_state == MMC_WRITING) - mmcp->mmc_state = MMC_READY; - chSysUnlock(); - return TRUE; - } - return FALSE; -} - -/** - * @brief Writes a block within a sequential write operation. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @param[out] buffer pointer to the write buffer - * @return The operation status. - * @retval FALSE the operation was successful. - * @retval TRUE the operation failed. - */ -bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) { - static const uint8_t start[] = {0xFF, 0xFC}; - uint8_t b[1]; - - chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialWrite"); - - chSysLock(); - if (mmcp->mmc_state != MMC_WRITING) { - chSysUnlock(); - return TRUE; - } - chSysUnlock(); - - spiSend(mmcp->mmc_spip, sizeof(start), start); /* Data prologue. */ - spiSend(mmcp->mmc_spip, MMC_SECTOR_SIZE, buffer); /* Data. */ - spiIgnore(mmcp->mmc_spip, 2); /* CRC ignored. */ - spiReceive(mmcp->mmc_spip, 1, b); - if ((b[0] & 0x1F) == 0x05) { - wait(mmcp); - return FALSE; - } - - /* Error.*/ - spiUnselect(mmcp->mmc_spip); - chSysLock(); - if (mmcp->mmc_state == MMC_WRITING) - mmcp->mmc_state = MMC_READY; - chSysUnlock(); - return TRUE; -} - -/** - * @brief Stops a sequential write gracefully. - * - * @param[in] mmcp pointer to the @p MMCDriver object - * @return The operation status. - * @retval FALSE the operation was successful. - * @retval TRUE the operation failed. - */ -bool_t mmcStopSequentialWrite(MMCDriver *mmcp) { - static const uint8_t stop[] = {0xFD, 0xFF}; - - chDbgCheck(mmcp != NULL, "mmcStopSequentialWrite"); - - chSysLock(); - if (mmcp->mmc_state != MMC_WRITING) { - chSysUnlock(); - return TRUE; - } - chSysUnlock(); - - spiSend(mmcp->mmc_spip, sizeof(stop), stop); - spiUnselect(mmcp->mmc_spip); - - chSysLock(); - if (mmcp->mmc_state == MMC_WRITING) { - mmcp->mmc_state = MMC_READY; - chSysUnlock(); - return FALSE; - } - chSysUnlock(); - return TRUE; -} - -#endif /* CH_HAL_USE_MMC_SPI */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/pal.c b/ChibiOS_2.0.8/os/hal/src/pal.c deleted file mode 100644 index 63af575..0000000 --- a/ChibiOS_2.0.8/os/hal/src/pal.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file pal.c - * @brief I/O Ports Abstraction Layer code. - * - * @addtogroup PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Read from an I/O bus. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The function internally uses the @p palReadGroup() macro. The use - * of this function is preferred when you value code size, readability - * and error checking over speed. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @return The bus logical states. - */ -ioportmask_t palReadBus(IOBus *bus) { - - chDbgCheck((bus != NULL) && - (bus->bus_offset > PAL_IOPORTS_WIDTH), "palReadBus"); - - return palReadGroup(bus->bus_portid, bus->bus_mask, bus->bus_offset); -} - -/** - * @brief Write to an I/O bus. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @param[in] bits the bits to be written on the I/O bus. Values exceeding - * the bus width are masked so most significant bits are - * lost. - */ -void palWriteBus(IOBus *bus, ioportmask_t bits) { - - chDbgCheck((bus != NULL) && - (bus->bus_offset > PAL_IOPORTS_WIDTH), "palWriteBus"); - - palWriteGroup(bus->bus_portid, bus->bus_mask, bus->bus_offset, bits); -} - -/** - * @brief Programs a bus with the specified mode. - * @note The operation is not guaranteed to be atomic on all the - * architectures, for atomicity and/or portability reasons you may - * need to enclose port I/O operations between @p chSysLock() and - * @p chSysUnlock(). - * @note The default implementation is non atomic and not necessarily - * optimal. Low level drivers may optimize the function by using - * specific hardware or coding. - * - * @param[in] bus the I/O bus, pointer to a @p IOBus structure - * @param[in] mode the mode - */ -void palSetBusMode(IOBus *bus, uint_fast8_t mode) { - - chDbgCheck((bus != NULL) && - (bus->bus_offset > PAL_IOPORTS_WIDTH), "palSetBusMode"); - - palSetGroupMode(bus->bus_portid, bus->bus_mask, mode); -} - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/pwm.c b/ChibiOS_2.0.8/os/hal/src/pwm.c deleted file mode 100644 index 3252a7a..0000000 --- a/ChibiOS_2.0.8/os/hal/src/pwm.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file pwm.c - * @brief PWM Driver code. - * - * @addtogroup PWM - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief PWM Driver initialization. - */ -void pwmInit(void) { - - pwm_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p PWMDriver structure. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -void pwmObjectInit(PWMDriver *pwmp) { - - pwmp->pd_state = PWM_STOP; - pwmp->pd_config = NULL; -#if defined(PWM_DRIVER_EXT_INIT_HOOK) - PWM_DRIVER_EXT_INIT_HOOK(pwmp); -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] config pointer to a @p PWMConfig object - */ -void pwmStart(PWMDriver *pwmp, const PWMConfig *config) { - - chDbgCheck((pwmp != NULL) && (config != NULL), "pwmStart"); - - chSysLock(); - chDbgAssert((pwmp->pd_state == PWM_STOP) || (pwmp->pd_state == PWM_READY), - "pwmStart(), #1", "invalid state"); - pwmp->pd_config = config; - pwm_lld_start(pwmp); - pwmp->pd_state = PWM_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -void pwmStop(PWMDriver *pwmp) { - - chDbgCheck(pwmp != NULL, "pwmStop"); - - chSysLock(); - chDbgAssert((pwmp->pd_state == PWM_STOP) || (pwmp->pd_state == PWM_READY), - "pwmStop(), #1", "invalid state"); - pwm_lld_stop(pwmp); - pwmp->pd_state = PWM_STOP; - chSysUnlock(); -} - -/** - * @brief Enables a PWM channel. - * @details Programs (or reprograms) a PWM channel. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * @param[in] width PWM pulse width as clock pulses number - */ -void pwmEnableChannel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - - chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS), - "pwmEnableChannel"); - - chSysLock(); - chDbgAssert(pwmp->pd_state == PWM_READY, - "pwmEnableChannel(), #1", "not ready"); - pwm_lld_enable_channel(pwmp, channel, width); - chSysUnlock(); -} - -/** - * @brief Disables a PWM channel. - * @details The channel is disabled and its output line returned to the - * idle state. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - */ -void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel) { - - chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS), - "pwmEnableChannel"); - - chSysLock(); - chDbgAssert(pwmp->pd_state == PWM_READY, - "pwmDisableChannel(), #1", "not ready"); - pwm_lld_disable_channel(pwmp, channel); - chSysUnlock(); -} - -#endif /* CH_HAL_USE_PWM */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/serial.c b/ChibiOS_2.0.8/os/hal/src/serial.c deleted file mode 100644 index 1be4308..0000000 --- a/ChibiOS_2.0.8/os/hal/src/serial.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file serial.c - * @brief Serial Driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/* - * Interface implementation, the following functions just invoke the equivalent - * queue-level function or macro. - */ - -static size_t writes(void *ip, const uint8_t *bp, size_t n) { - - return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, - n, TIME_INFINITE); -} - -static size_t reads(void *ip, uint8_t *bp, size_t n) { - - return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, - n, TIME_INFINITE); -} - -static bool_t putwouldblock(void *ip) { - - return chOQIsFull(&((SerialDriver *)ip)->oqueue); -} - -static bool_t getwouldblock(void *ip) { - - return chIQIsEmpty(&((SerialDriver *)ip)->iqueue); -} - -static msg_t putt(void *ip, uint8_t b, systime_t timeout) { - - return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout); -} - -static msg_t gett(void *ip, systime_t timeout) { - - return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, timeout); -} - -static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) { - - return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, time); -} - -static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) { - - return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, time); -} - -static const struct SerialDriverVMT vmt = { - writes, reads, putwouldblock, getwouldblock, putt, gett, writet, readt -}; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver initialization. - */ -void sdInit(void) { - - sd_lld_init(); -} - -/** - * @brief Initializes a generic full duplex driver object. - * @details The HW dependent part of the initialization has to be performed - * outside, usually in the hardware initialization code. - * - * @param[out] sdp pointer to a @p SerialDriver structure - * @param[in] inotify pointer to a callback function that is invoked when - * some data is read from the Queue. The value can be - * @p NULL. - * @param[in] onotify pointer to a callback function that is invoked when - * some data is written in the Queue. The value can be - * @p NULL. - */ -void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) { - - sdp->vmt = &vmt; - chEvtInit(&sdp->ievent); - chEvtInit(&sdp->oevent); - chEvtInit(&sdp->sevent); - sdp->state = SD_STOP; - sdp->flags = SD_NO_ERROR; - chIQInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify); - chOQInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify); -} - -/** - * @brief Configures and starts the driver. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sdStart(SerialDriver *sdp, const SerialConfig *config) { - - chDbgCheck(sdp != NULL, "sdStart"); - - chSysLock(); - chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), - "sdStart(), #1", - "invalid state"); - sd_lld_start(sdp, config); - sdp->state = SD_READY; - chSysUnlock(); -} - -/** - * @brief Stops the driver. - * @details Any thread waiting on the driver's queues will be awakened with - * the message @p Q_RESET. - * - * @param[in] sdp pointer to a @p SerialDrive object - */ -void sdStop(SerialDriver *sdp) { - - chDbgCheck(sdp != NULL, "sdStop"); - - chSysLock(); - chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY), - "sdStop(), #1", - "invalid state"); - sd_lld_stop(sdp); - sdp->state = SD_STOP; - chOQResetI(&sdp->oqueue); - chIQResetI(&sdp->iqueue); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Handles incoming data. - * @details This function must be called from the input interrupt service - * routine in order to enqueue incoming data and generate the - * related events. - * @note The incoming data event is only generated when the input queue - * becomes non-empty. - * @note In order to gain some performance it is suggested to not use - * this function directly but copy this code directly into the - * interrupt service routine. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @param[in] b the byte to be written in the driver's Input Queue - */ -void sdIncomingDataI(SerialDriver *sdp, uint8_t b) { - - chDbgCheck(sdp != NULL, "sdIncomingDataI"); - - if (chIQIsEmpty(&sdp->iqueue)) - chEvtBroadcastI(&sdp->ievent); - if (chIQPutI(&sdp->iqueue, b) < Q_OK) - sdAddFlagsI(sdp, SD_OVERRUN_ERROR); -} - -/** - * @brief Handles outgoing data. - * @details Must be called from the output interrupt service routine in order - * to get the next byte to be transmitted. - * @note In order to gain some performance it is suggested to not use - * this function directly but copy this code directly into the - * interrupt service routine. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @return The byte value read from the driver's output queue. - * @retval Q_EMPTY if the queue is empty (the lower driver usually - * disables the interrupt source when this happens). - */ -msg_t sdRequestDataI(SerialDriver *sdp) { - msg_t b; - - chDbgCheck(sdp != NULL, "sdRequestDataI"); - - b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) - chEvtBroadcastI(&sdp->oevent); - return b; -} - -/** - * @brief Handles communication events/errors. - * @details Must be called from the I/O interrupt service routine in order to - * notify I/O conditions as errors, signals change etc. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @param[in] mask condition flags to be added to the mask - */ -void sdAddFlagsI(SerialDriver *sdp, sdflags_t mask) { - - chDbgCheck(sdp != NULL, "sdAddFlagsI"); - - sdp->flags |= mask; - chEvtBroadcastI(&sdp->sevent); -} - -/** - * @brief Returns and clears the errors mask associated to the driver. - * - * @param[in] sdp pointer to a @p SerialDriver structure - * @return The condition flags modified since last time this - * function was invoked. - */ -sdflags_t sdGetAndClearFlags(SerialDriver *sdp) { - sdflags_t mask; - - chDbgCheck(sdp != NULL, "sdGetAndClearFlags"); - - chSysLock(); - mask = sdp->flags; - sdp->flags = SD_NO_ERROR; - chSysUnlock(); - return mask; -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/src/spi.c b/ChibiOS_2.0.8/os/hal/src/spi.c deleted file mode 100644 index f8121c7..0000000 --- a/ChibiOS_2.0.8/os/hal/src/spi.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file spi.c - * @brief SPI Driver code. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief SPI Driver initialization. - */ -void spiInit(void) { - - spi_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p SPIDriver structure. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spiObjectInit(SPIDriver *spip) { - - spip->spd_state = SPI_STOP; -#if SPI_USE_MUTUAL_EXCLUSION -#if CH_USE_MUTEXES - chMtxInit(&spip->spd_mutex); -#else - chSemInit(&spip->spd_semaphore, 1); -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ - spip->spd_config = NULL; -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] config pointer to the @p SPIConfig object - */ -void spiStart(SPIDriver *spip, const SPIConfig *config) { - - chDbgCheck((spip != NULL) && (config != NULL), "spiStart"); - - chSysLock(); - chDbgAssert((spip->spd_state == SPI_STOP) || (spip->spd_state == SPI_READY), - "spiStart(), #1", - "invalid state"); - spip->spd_config = config; - spi_lld_start(spip); - spip->spd_state = SPI_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spiStop(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiStop"); - - chSysLock(); - chDbgAssert((spip->spd_state == SPI_STOP) || (spip->spd_state == SPI_READY), - "spiStop(), #1", - "invalid state"); - spi_lld_stop(spip); - spip->spd_state = SPI_STOP; - chSysUnlock(); -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spiSelect(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiSelect"); - - chSysLock(); - chDbgAssert((spip->spd_state == SPI_READY) || - (spip->spd_state == SPI_ACTIVE), - "spiSelect(), #1", - "not idle"); - spi_lld_select(spip); - spip->spd_state = SPI_ACTIVE; - chSysUnlock(); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spiUnselect(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiUnselect"); - - chSysLock(); - chDbgAssert((spip->spd_state == SPI_READY) || - (spip->spd_state == SPI_ACTIVE), - "spiUnselect(), #1", - "not locked"); - spi_lld_unselect(spip); - spip->spd_state = SPI_READY; - chSysUnlock(); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This function transmits a series of idle words on the SPI bus and - * ignores the received data. This function can be invoked even - * when a slave select signal has not been yet asserted. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - */ -void spiIgnore(SPIDriver *spip, size_t n) { - - chDbgCheck((spip != NULL) && (n > 0), "spiIgnore"); - chDbgAssert((spip->spd_state == SPI_READY) || (spip->spd_state == SPI_ACTIVE), - "spiIgnore(), #1", - "not active"); - - spi_lld_ignore(spip, n); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This function performs a simultaneous transmit/receive operation. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - */ -void spiExchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL), - "spiExchange"); - chDbgAssert(spip->spd_state == SPI_ACTIVE, - "spiExchange(), #1", - "not active"); - - spi_lld_exchange(spip, n, txbuf, rxbuf); -} - -/** - * @brief Sends data over the SPI bus. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - */ -void spiSend(SPIDriver *spip, size_t n, const void *txbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), - "spiSend"); - chDbgAssert(spip->spd_state == SPI_ACTIVE, - "spiSend(), #1", - "not active"); - - spi_lld_send(spip, n, txbuf); -} - -/** - * @brief Receives data from the SPI bus. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - */ -void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) { - - chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL), - "spiReceive"); - chDbgAssert(spip->spd_state == SPI_ACTIVE, - "spiReceive(), #1", - "not active"); - - spi_lld_receive(spip, n, rxbuf); -} - -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the SPI bus. - * @details This function tries to gain ownership to the SPI bus, if the bus - * is already being used then the invoking thread is queued. - * @note This function is only available when the @p SPI_USE_MUTUAL_EXCLUSION - * option is set to @p TRUE. - * - * @param[in] spip pointer to the @p SPIDriver object - * - */ -void spiAcquireBus(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiAcquireBus"); - -#if CH_USE_MUTEXES - chMtxLock(&spip->spd_mutex); -#elif CH_USE_SEMAPHORES - chSemWait(&spip->spd_semaphore); -#endif -} - -/** - * @brief Releases exclusive access to the SPI bus. - * @note This function is only available when the @p SPI_USE_MUTUAL_EXCLUSION - * option is set to @p TRUE. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spiReleaseBus(SPIDriver *spip) { - - chDbgCheck(spip != NULL, "spiReleaseBus"); - -#if CH_USE_MUTEXES - (void)spip; - chMtxUnlock(); -#elif CH_USE_SEMAPHORES - chSemSignal(&spip->spd_semaphore); -#endif -} -#endif /* SPI_USE_MUTUAL_EXCLUSION */ - -#endif /* CH_HAL_USE_SPI */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/adc_lld.c b/ChibiOS_2.0.8/os/hal/templates/adc_lld.c deleted file mode 100644 index 8d8202e..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/adc_lld.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/adc_lld.c - * @brief ADC Driver subsystem low level driver source template. - * - * @addtogroup ADC_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - */ -void adc_lld_init(void) { - -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adc_lld_start(ADCDriver *adcp) { - - if (adcp->adc_state == ADC_STOP) { - /* Clock activation.*/ - } - /* Configuration.*/ -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adc_lld_stop(ADCDriver *adcp) { - -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - -} - -#endif /* CH_HAL_USE_ADC */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/adc_lld.h b/ChibiOS_2.0.8/os/hal/templates/adc_lld.h deleted file mode 100644 index 47c0482..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/adc_lld.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/adc_lld.h - * @brief ADC Driver subsystem low level driver header template. - * - * @addtogroup ADC_LLD - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if CH_HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !CH_USE_SEMAPHORES -#error "the ADC driver requires CH_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief ADC notification callback type. - * - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(adcsample_t *buffer, size_t n); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool_t acg_circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t acg_num_channels; - /* End of the mandatory fields.*/ -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - adcstate_t ad_state; - /** - * @brief Current configuration data. - */ - const ADCConfig *ad_config; - /** - * @brief Synchronization semaphore. - */ - Semaphore ad_sem; - /** - * @brief Current callback function or @p NULL. - */ - adccallback_t ad_callback; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *ad_samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t ad_depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *ad_grpp; - /* End of the mandatory fields.*/ -} ADCDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/can_lld.c b/ChibiOS_2.0.8/os/hal/templates/can_lld.c deleted file mode 100644 index d258d09..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/can_lld.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/can_lld.c - * @brief CAN Driver subsystem low level driver source template. - * - * @addtogroup CAN_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CAN driver initialization. - */ -void can_lld_init(void) { - -} - -/** - * @brief Configures and activates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void can_lld_start(CANDriver *canp) { - -} - -/** - * @brief Deactivates the CAN peripheral. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void can_lld_stop(CANDriver *canp) { - - /* If in ready state then disables the CAN peripheral.*/ - if (canp->cd_state == CAN_READY) { - - } -} - - -/** - * @brief Determines whether a frame can be transmitted. - * - * @param[in] canp pointer to the @p CANDriver object - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - */ -bool_t can_lld_can_transmit(CANDriver *canp) { - - return FALSE; -} - -/** - * @brief Inserts a frame into the transmit queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[in] ctfp pointer to the CAN frame to be transmitted - */ -void can_lld_transmit(CANDriver *canp, const CANTxFrame *ctfp) { - -} - -/** - * @brief Determines whether a frame has been received. - * - * @param[in] canp pointer to the @p CANDriver object - * @return The queue space availability. - * @retval FALSE no space in the transmit queue. - * @retval TRUE transmit slot available. - */ -bool_t can_lld_can_receive(CANDriver *canp) { - - return FALSE; -} - -/** - * @brief Receives a frame from the input queue. - * - * @param[in] canp pointer to the @p CANDriver object - * @param[out] crfp pointer to the buffer where the CAN frame is copied - */ -void can_lld_receive(CANDriver *canp, CANRxFrame *crfp) { - -} - -#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) -/** - * @brief Enters the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void can_lld_sleep(CANDriver *canp) { - -} - -/** - * @brief Enforces leaving the sleep mode. - * - * @param[in] canp pointer to the @p CANDriver object - */ -void can_lld_wakeup(CANDriver *canp) { - -} -#endif /* CAN_USE_SLEEP_MODE */ - -#endif /* CH_HAL_USE_CAN */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/can_lld.h b/ChibiOS_2.0.8/os/hal/templates/can_lld.h deleted file mode 100644 index be8c46b..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/can_lld.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/can_lld.h - * @brief CAN Driver subsystem low level driver header template. - * - * @addtogroup CAN_LLD - * @{ - */ - -#ifndef _CAN_LLD_H_ -#define _CAN_LLD_H_ - -#if CH_HAL_USE_CAN || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief This switch defines whether the driver implementation supports - * a low power switch mode with automatic an wakeup feature. - */ -#define CAN_SUPPORTS_SLEEP TRUE - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - * @note This switch is enforced to @p FALSE if the driver implementation - * does not support the sleep mode. - */ -#if CAN_SUPPORTS_SLEEP || defined(__DOXYGEN__) -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif -#else /* !CAN_SUPPORTS_SLEEP */ -#define CAN_USE_SLEEP_MODE FALSE -#endif /* !CAN_SUPPORTS_SLEEP */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP -#error "CAN sleep mode not supported in this architecture" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief CAN status flags. - */ -typedef uint32_t canstatus_t; - -/** - * @brief CAN transmission frame. - * @note Accessing the frame data as word16 or word32 is not portable - * because machine data endianness, it can be still useful for a - * quick filling. - */ -typedef struct { - struct { - uint8_t cf_DLC:4; /**< @brief Data length. */ - uint8_t cf_RTR:1; /**< @brief Frame type. */ - uint8_t cf_IDE:1; /**< @brief Identifier type. */ - }; - union { - struct { - uint32_t cf_SID:11; /**< @brief Standard identifier.*/ - }; - struct { - uint32_t cf_EID:29; /**< @brief Extended identifier.*/ - }; - }; - union { - uint8_t cf_data8[8]; /**< @brief Frame data. */ - uint16_t cf_data16[4]; /**< @brief Frame data. */ - uint32_t cf_data32[2]; /**< @brief Frame data. */ - }; -} CANTxFrame; - -/** - * @brief CAN received frame. - * @note Accessing the frame data as word16 or word32 is not portable - * because machine data endianness, it can be still useful for a - * quick filling. - */ -typedef struct { - struct { - uint8_t cf_DLC:4; /**< @brief Data length. */ - uint8_t cf_RTR:1; /**< @brief Frame type. */ - uint8_t cf_IDE:1; /**< @brief Identifier type. */ - }; - union { - struct { - uint32_t cf_SID:11; /**< @brief Standard identifier.*/ - }; - struct { - uint32_t cf_EID:29; /**< @brief Extended identifier.*/ - }; - }; - union { - uint8_t cf_data8[8]; /**< @brief Frame data. */ - uint16_t cf_data16[4]; /**< @brief Frame data. */ - uint32_t cf_data32[2]; /**< @brief Frame data. */ - }; -} CANRxFrame; - -/** - * @brief CAN filter. - * @note It could not be present on some architectures. - */ -typedef struct { -} CANFilter; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { -} CANConfig; - -/** - * @brief Structure representing an CAN driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - canstate_t cd_state; - /** - * @brief Current configuration data. - */ - const CANConfig *cd_config; - /** - * @brief Transmission queue semaphore. - */ - Semaphore cd_txsem; - /** - * @brief Receive queue semaphore. - */ - Semaphore cd_rxsem; - /** - * @brief One or more frames become available. - * @note After broadcasting this event it will not be broadcasted again - * until the received frames queue has been completely emptied. It - * is not broadcasted for each received frame. It is - * responsibility of the application to empty the queue by repeatedly - * invoking @p chReceive() when listening to this event. This behavior - * minimizes the interrupt served by the system because CAN traffic. - */ - EventSource cd_rxfull_event; - /** - * @brief One or more transmission slots become available. - */ - EventSource cd_txempty_event; - /** - * @brief A CAN bus error happened. - */ - EventSource cd_error_event; - /** - * @brief Error flags set when an error event is broadcasted. - */ - canstatus_t cd_status; -#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) - /** - * @brief Entering sleep state event. - */ - EventSource cd_sleep_event; - /** - * @brief Exiting sleep state event. - */ - EventSource cd_wakeup_event; -#endif /* CAN_USE_SLEEP_MODE */ - /* End of the mandatory fields.*/ -} CANDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void can_lld_init(void); - void can_lld_start(CANDriver *canp); - void can_lld_stop(CANDriver *canp); - bool_t can_lld_can_transmit(CANDriver *canp); - void can_lld_transmit(CANDriver *canp, const CANTxFrame *crfp); - bool_t can_lld_can_receive(CANDriver *canp); - void can_lld_receive(CANDriver *canp, CANRxFrame *ctfp); -#if CAN_USE_SLEEP_MODE - void can_lld_sleep(CANDriver *canp); - void can_lld_wakeup(CANDriver *canp); -#endif /* CAN_USE_SLEEP_MODE */ -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_CAN */ - -#endif /* _CAN_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/hal_lld.c b/ChibiOS_2.0.8/os/hal/templates/hal_lld.c deleted file mode 100644 index 75daefc..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/hal_lld.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/hal_lld.c - * @brief HAL Driver subsystem low level driver source template. - * - * @addtogroup HAL_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - */ -void hal_lld_init(void) { - -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/hal_lld.h b/ChibiOS_2.0.8/os/hal/templates/hal_lld.h deleted file mode 100644 index aca705a..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/hal_lld.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/hal_lld.h - * @brief HAL subsystem low level driver header template. - * - * @addtogroup HAL_LLD - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "" - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/halconf.h b/ChibiOS_2.0.8/os/hal/templates/halconf.h deleted file mode 100644 index e06975d..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/halconf.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -/* - * - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -/*#include "mcuconf.h"*/ - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN TRUE -#endif - -/* - * Default CAN settings overrides (uncomment to override). - */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC TRUE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM TRUE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/mac_lld.c b/ChibiOS_2.0.8/os/hal/templates/mac_lld.c deleted file mode 100644 index db5dbfb..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/mac_lld.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/mac_lld.c - * @brief MAC Driver subsystem low level driver source template. - * - * @addtogroup MAC_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level MAC initialization. - */ -void mac_lld_init(void) { - -} - -/** - * @brief Low level MAC address setup. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] p pointer to a six bytes buffer containing the MAC - * address. If this parameter is set to @p NULL then - * a system default MAC is used. - */ -void mac_lld_set_address(MACDriver *macp, const uint8_t *p) { - -} - -/** - * @brief Returns a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @return The operation status. - * @retval RDY_OK a descriptor was obtained. - * @retval RDY_TIMEOUT descriptor not available. - */ -msg_t max_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp) { - - return RDY_OK; -} - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be - * written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum - * frame size is reached. - */ -size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size) { - - return 0; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - */ -void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { - -} - -/** - * @brief Returns a receive descriptor. - * - * @param[in] macp pointer to a @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @return The operation status. - * @retval RDY_OK a descriptor was obtained. - * @retval RDY_TIMEOUT descriptor not available. - */ -msg_t max_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp) { - - return RDY_OK; -} - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to a buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's stream, - * this value can be less than the amount specified in - * the parameter @p size if there are no more bytes to read. - */ -size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size) { - - return 0; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - */ -void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { - -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to a @p MACDriver object - * @return The link status. - * @retval TRUE if the link is active. - * @retval FALSE if the link is down. - */ -bool_t mac_lld_poll_link_status(MACDriver *macp) { - - return FALSE; -} - -#endif /* CH_HAL_USE_MAC */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/mac_lld.h b/ChibiOS_2.0.8/os/hal/templates/mac_lld.h deleted file mode 100644 index f691d47..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/mac_lld.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/mac_lld.h - * @brief MAC Driver subsystem low level driver header template. - * - * @addtogroup MAC_LLD - * @{ - */ - -#ifndef _MAC_LLD_H_ -#define _MAC_LLD_H_ - -#if CH_HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Number of available transmit buffers. - */ -#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) -#define MAC_TRANSMIT_BUFFERS 2 -#endif - -/** - * @brief Number of available receive buffers. - */ -#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) -#define MAC_RECEIVE_BUFFERS 2 -#endif - -/** - * @brief Maximum supported frame size. - */ -#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define MAC_BUFFERS_SIZE 1518 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Structure representing a MAC driver. - */ -typedef struct { - Semaphore md_tdsem; /**< Transmit semaphore. */ - Semaphore md_rdsem; /**< Receive semaphore. */ -#if CH_USE_EVENTS - EventSource md_rdevent; /**< Receive event source. */ -#endif - /* End of the mandatory fields.*/ -} MACDriver; - -/** - * @brief Structure representing a transmit descriptor. - */ -typedef struct { - size_t td_offset; /**< Current write offset. */ - size_t td_size; /**< Available space size. */ - /* End of the mandatory fields.*/ -} MACTransmitDescriptor; - -/** - * @brief Structure representing a receive descriptor. - */ -typedef struct { - size_t rd_offset; /**< Current read offset. */ - size_t rd_size; /**< Available data size. */ - /* End of the mandatory fields.*/ -} MACReceiveDescriptor; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void mac_lld_init(void); - void mac_lld_set_address(MACDriver *macp, const uint8_t *p); - msg_t max_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp); - size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size); - void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); - msg_t max_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp); - size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size); - void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); - bool_t mac_lld_poll_link_status(MACDriver *macp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_MAC */ - -#endif /* _MAC_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/meta/driver.c b/ChibiOS_2.0.8/os/hal/templates/meta/driver.c deleted file mode 100644 index 554a247..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/meta/driver.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file xxx.c - * @brief XXX Driver code. - * - * @addtogroup XXX - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_XXX || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief XXX Driver initialization. - */ -void xxxInit(void) { - - xxx_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p XXXDriver structure. - * - * @param[in] xxxp pointer to the @p XXXDriver object - */ -void xxxObjectInit(XXXDriver *xxxp) { - - xxxp->xxx_state = XXX_STOP; - xxxp->xxx_config = NULL; -} - -/** - * @brief Configures and activates the XXX peripheral. - * - * @param[in] xxxp pointer to the @p XXXDriver object - * @param[in] config pointer to the @p XXXConfig object - */ -void xxxStart(XXXDriver *xxxp, const XXXConfig *config) { - - chDbgCheck((xxxp != NULL) && (config != NULL), "xxxStart"); - - chSysLock(); - chDbgAssert((xxxp->xxx_state == XXX_STOP) || (xxxp->xxx_state == XXX_READY), - "xxxStart(), #1", - "invalid state"); - xxxp->xxx_config = config; - xxx_lld_start(xxxp); - xxxp->xxx_state = XXX_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the XXX peripheral. - * - * @param[in] xxxp pointer to the @p XXXDriver object - */ -void xxxStop(XXXDriver *xxxp) { - - chDbgCheck(xxxp != NULL, "xxxStop"); - - chSysLock(); - chDbgAssert((xxxp->xxx_state == XXX_STOP) || (xxxp->xxx_state == XXX_READY), - "xxxStop(), #1", - "invalid state"); - xxx_lld_stop(xxxp); - xxxp->xxx_state = XXX_STOP; - chSysUnlock(); -} - -#endif /* CH_HAL_USE_XXX */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/meta/driver.h b/ChibiOS_2.0.8/os/hal/templates/meta/driver.h deleted file mode 100644 index 1661c15..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/meta/driver.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file xxx.h - * @brief XXX Driver macros and structures. - * - * @addtogroup XXX - * @{ - */ - -#ifndef _XXX_H_ -#define _XXX_H_ - -#if CH_HAL_USE_XXX || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - XXX_UNINIT = 0, /**< @brief Not initialized. */ - XXX_STOP = 1, /**< @brief Stopped. */ - XXX_READY = 2, /**< @brief Ready. */ -} xxxstate_t; - -#include "xxx_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void xxxInit(void); - void xxxObjectInit(XXXDriver *xxxp); - void xxxStart(XXXDriver *xxxp, const XXXConfig *config); - void xxxStop(XXXDriver *xxxp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_XXX */ - -#endif /* _XXX_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/meta/driver_lld.c b/ChibiOS_2.0.8/os/hal/templates/meta/driver_lld.c deleted file mode 100644 index 4af3d8d..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/meta/driver_lld.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/xxx_lld.c - * @brief XXX Driver subsystem low level driver source template. - * - * @addtogroup XXX_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_XXX || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level XXX driver initialization. - */ -void xxx_lld_init(void) { - -} - -/** - * @brief Configures and activates the XXX peripheral. - * - * @param[in] xxxp pointer to the @p XXXDriver object - */ -void xxx_lld_start(XXXDriver *xxxp) { - - if (xxxp->xxx_state == XXX_STOP) { - /* Clock activation.*/ - } - /* Configuration.*/ -} - -/** - * @brief Deactivates the XXX peripheral. - * - * @param[in] xxxp pointer to the @p XXXDriver object - */ -void xxx_lld_stop(XXXDriver *xxxp) { - -} - -#endif /* CH_HAL_USE_XXX */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/meta/driver_lld.h b/ChibiOS_2.0.8/os/hal/templates/meta/driver_lld.h deleted file mode 100644 index 8658ca5..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/meta/driver_lld.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/xxx_lld.h - * @brief XXX Driver subsystem low level driver header template. - * - * @addtogroup XXX_LLD - * @{ - */ - -#ifndef _XXX_LLD_H_ -#define _XXX_LLD_H_ - -#if CH_HAL_USE_XXX || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - -} XXXConfig; - -/** - * @brief Structure representing an XXX driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - xxxstate_t xxx_state; - /** - * @brief Current configuration data. - */ - const XXXConfig *xxx_config; - /* End of the mandatory fields.*/ -} XXXDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void xxx_lld_init(void); - void xxx_lld_start(XXXDriver *xxxp); - void xxx_lld_stop(XXXDriver *xxxp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_XXX */ - -#endif /* _XXX_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/pal_lld.c b/ChibiOS_2.0.8/os/hal/templates/pal_lld.c deleted file mode 100644 index 5ed57e5..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/pal_lld.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/pal_lld.c - * @brief PAL subsystem low level driver template. - * - * @addtogroup PAL_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -#endif /* CH_HAL_USE_PAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/pal_lld.h b/ChibiOS_2.0.8/os/hal/templates/pal_lld.h deleted file mode 100644 index 81b6ac8..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/pal_lld.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/pal_lld.h - * @brief PAL subsystem low level driver header template. - * - * @addtogroup PAL_LLD - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if CH_HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief Generic I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - * @note This structure content is architecture dependent. The nome should - * be changed to include the architecture name following this - * pattern:
- * - [ARCH][CELL]Config. - * . - * As example:
- * - MSP430DIOConfig. - * . - */ -typedef struct { - -} GenericConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ -typedef uint32_t ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief First I/O port identifier. - * @details Low level drivers can define multiple ports, it is suggested to - * use this naming convention. - */ -#define IOPORT1 0 - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - */ -#define pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The port bits. - */ -#define pal_lld_readport(port) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @return The latched logical states. - */ -#define pal_lld_readlatch(port) - -/** - * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - */ -#define pal_lld_writeport(port, bits) - -/** - * @brief Sets a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - */ -#define pal_lld_setport(port, bits) - -/** - * @brief Clears a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - */ -#define pal_lld_clearport(port, bits) - -/** - * @brief Toggles a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be XORed on the specified port - */ -#define pal_lld_toggleport(port, bits) - -/** - * @brief Reads a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @return The group logical states. - */ -#define pal_lld_readgroup(port, mask, offset) - -/** - * @brief Writes a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group width - * are masked. - */ -#define pal_lld_writegroup(port, mask, offset, bits) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] mode group mode - */ -#define pal_lld_setgroupmode(port, mask, mode) - -/** - * @brief Reads a logical state from an I/O pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - */ -#define pal_lld_readpad(port, pad) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[out] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - */ -#define pal_lld_writepad(port, pad, bit) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#define pal_lld_setpad(port, pad) - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#define pal_lld_clearpad(port, pad) - -/** - * @brief Toggles a pad logical state. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - */ -#define pal_lld_togglepad(port, pad) - -/** - * @brief Pad mode setup. - * @details This function programs a pad with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] mode pad mode - */ -#define pal_lld_setpadmode(port, pad, mode) - -#endif /* CH_HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/pwm_lld.c b/ChibiOS_2.0.8/os/hal/templates/pwm_lld.c deleted file mode 100644 index 201ac3d..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/pwm_lld.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/pwm_lld.c - * @brief PWM Driver subsystem low level driver source template. - * - * @addtogroup PWM_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level PWM driver initialization. - */ -void pwm_lld_init(void) { - -} - -/** - * @brief Configures and activates the PWM peripheral. - * - * @param[in] pwmp pointer to the @p PWMDriver object - */ -void pwm_lld_start(PWMDriver *pwmp) { - - if (pwmp->pd_state == PWM_STOP) { - /* Clock activation.*/ - } - /* Configuration.*/ -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to the @p PWMDriver object - */ -void pwm_lld_stop(PWMDriver *pwmp) { - -} - -/** - * @brief Determines whatever the PWM channel is already enabled. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] channel PWM channel identifier - * @return The PWM channel status. - * @retval FALSE the channel is not enabled. - * @retval TRUE the channel is enabled. - */ -bool_t pwm_lld_is_enabled(PWMDriver *pwmp, pwmchannel_t channel) { - - return FALSE; -} - -/** - * @brief Enables a PWM channel. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - * @param[in] width PWM pulse width as clock pulses number - */ -void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) { - -} - -/** - * @brief Disables a PWM channel. - * @details The channel is disabled and its output line returned to the - * idle state. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1) - */ -void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - -} - -#endif /* CH_HAL_USE_PWM */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/pwm_lld.h b/ChibiOS_2.0.8/os/hal/templates/pwm_lld.h deleted file mode 100644 index 8a5310c..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/pwm_lld.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/pwm_lld.h - * @brief PWM Driver subsystem low level driver header template. - * - * @addtogroup PWM_LLD - * @{ - */ - -#ifndef _PWM_LLD_H_ -#define _PWM_LLD_H_ - -#if CH_HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Number of PWM channels per PWM driver. - */ -#if !defined(PWM_CHANNELS) || defined(__DOXYGEN__) -#define PWM_CHANNELS 1 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief PWM channel type. - */ -typedef uint8_t pwmchannel_t; - -/** - * @brief PWM counter type. - */ -typedef uint16_t pwmcnt_t; - -/** - * @brief Type of a structure representing an PWM driver. - */ -typedef struct PWMDriver PWMDriver; - -/** - * @brief PWM notification callback type. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -typedef void (*pwmcallback_t)(PWMDriver *pwmp); - -/** - * @brief PWM driver channel configuration structure. - * @note Some architectures may not be able to support the channel mode - * or the callback, in this case the fields are ignored. - */ -typedef struct { - /** - * @brief Channel active logic level. - */ - pwmmode_t pcc_mode; - /** - * @brief Channel callback pointer. - * @note This callback is invoked on the channel compare event. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t pcc_callback; - /* End of the mandatory fields.*/ -} PWMChannelConfig; - -/** - * @brief Driver configuration structure. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. - */ -typedef struct { - /** - * @brief Periodic callback pointer. - * @note This callback is invoked on PWM counter reset. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t pc_callback; - /** - * @brief Channels configurations. - */ - PWMChannelConfig pc_channels[PWM_CHANNELS]; - /* End of the mandatory fields.*/ -} PWMConfig; - -/** - * @brief Structure representing an PWM driver. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. - */ -struct PWMDriver { - /** - * @brief Driver state. - */ - pwmstate_t pd_state; - /** - * @brief Current configuration data. - */ - const PWMConfig *pd_config; -#if defined(PWM_DRIVER_EXT_FIELDS) - PWM_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Converts from fraction to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify tenths of thousandth but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] numerator numerator of the fraction - * @param[in] denominator percentage as an integer between 0 and numerator - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_FRACTION_TO_WIDTH(pwmp, numerator, denominator) 0 - -/** - * @brief Converts from degrees to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify hundredths of degrees but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] degrees degrees as an integer between 0 and 36000 - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_DEGREES_TO_WIDTH(pwmp, degrees) \ - PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) - -/** - * @brief Converts from percentage to pulse width. - * @note Be careful with rounding errors, this is integer math not magic. - * You can specify tenths of thousandth but make sure you have the - * proper hardware resolution by carefully choosing the clock source - * and prescaler settings, see @p PWM_COMPUTE_PSC. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] percentage percentage as an integer between 0 and 10000 - * @return The pulse width to be passed to @p pwmEnableChannel(). - * - * @api - */ -#define PWM_PERCENTAGE_TO_WIDTH(pwmp, percentage) \ - PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void pwm_lld_init(void); - void pwm_lld_start(PWMDriver *pwmp); - void pwm_lld_stop(PWMDriver *pwmp); - bool_t pwm_lld_is_enabled(PWMDriver *pwmp, pwmchannel_t channel); - void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_PWM */ - -#endif /* _PWM_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/serial_lld.c b/ChibiOS_2.0.8/os/hal/templates/serial_lld.c deleted file mode 100644 index 0a2f736..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/serial_lld.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/serial_lld.c - * @brief Serial Driver subsystem low level driver source template. - * - * @addtogroup SERIAL_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static const SerialConfig default_config = { -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) { - -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) { - -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/serial_lld.h b/ChibiOS_2.0.8/os/hal/templates/serial_lld.h deleted file mode 100644 index 9219970..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/serial_lld.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/serial_lld.h - * @brief Serial Driver subsystem low level driver header template. - * - * @addtogroup SERIAL_LLD - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Serial Driver condition flags type. - */ -typedef uint8_t sdflags_t; - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Status Change @p EventSource.*/ \ - EventSource sevent; \ - /* I/O driver status flags.*/ \ - sdflags_t flags; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/spi_lld.c b/ChibiOS_2.0.8/os/hal/templates/spi_lld.c deleted file mode 100644 index 5ca0314..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/spi_lld.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/spi_lld.c - * @brief SPI Driver subsystem low level driver source template. - * - * @addtogroup SPI_LLD - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if CH_HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - */ -void spi_lld_init(void) { - -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_start(SPIDriver *spip) { - - if (spip->spd_state == SPI_STOP) { - /* Clock activation.*/ - } - /* Configuration.*/ -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_stop(SPIDriver *spip) { - -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_select(SPIDriver *spip) { - -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -void spi_lld_unselect(SPIDriver *spip) { - -} - -/** - * @brief Ignores data on the SPI bus. - * @details This function transmits a series of idle words on the SPI bus and - * ignores the received data. This function can be invoked even - * when a slave select signal has not been yet asserted. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This function performs a simultaneous transmit/receive operation. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - -} - -/** - * @brief Sends data ever the SPI bus. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - -} - -/** - * @brief Receives data from the SPI bus. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - -} - -#endif /* CH_HAL_USE_SPI */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/hal/templates/spi_lld.h b/ChibiOS_2.0.8/os/hal/templates/spi_lld.h deleted file mode 100644 index 17a7e28..0000000 --- a/ChibiOS_2.0.8/os/hal/templates/spi_lld.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/spi_lld.h - * @brief SPI Driver subsystem low level driver header template. - * - * @addtogroup SPI_LLD - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if CH_HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver configuration structure. - */ -typedef struct { - -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -typedef struct { - /** - * @brief Driver state. - */ - spistate_t spd_state; -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex spd_mutex; -#elif CH_USE_SEMAPHORES - Semaphore spd_semaphore; -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ - /** - * @brief Current configuration data. - */ - const SPIConfig *spd_config; - /* End of the mandatory fields.*/ -} SPIDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); -#ifdef __cplusplus -} -#endif - -#endif /* CH_HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/ch.h b/ChibiOS_2.0.8/os/kernel/include/ch.h deleted file mode 100644 index 48e0af1..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/ch.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ch.h - * @brief ChibiOS/RT main include file. - * @details This header includes all the required kernel headers so it is the - * only kernel header you usually want to include in your application. - * - * @addtogroup kernel_info - * @details Kernel related info. - * @{ - */ - -#ifndef _CH_H_ -#define _CH_H_ - -/** - * @brief ChibiOS/RT identification macro. - */ -#define _CHIBIOS_RT_ - -/** - * @brief Kernel version string. - */ -#define CH_KERNEL_VERSION "2.0.8" - -/** - * @brief Kernel version major number. - */ -#define CH_KERNEL_MAJOR 2 - -/** - * @brief Kernel version minor number. - */ -#define CH_KERNEL_MINOR 0 - -/** - * @brief Kernel version patch number. - */ -#define CH_KERNEL_PATCH 8 - -/* - * Common values. - */ -#ifndef FALSE -#define FALSE 0 -#endif -#ifndef TRUE -#define TRUE (!FALSE) -#endif - -#include "chconf.h" -#include "chtypes.h" -#include "chlists.h" -#include "chcore.h" -#include "chsys.h" -#include "chvt.h" -#include "chschd.h" -#include "chsem.h" -#include "chmtx.h" -#include "chcond.h" -#include "chevents.h" -#include "chmsg.h" -#include "chmboxes.h" -#include "chmemcore.h" -#include "chheap.h" -#include "chmempools.h" -#include "chthreads.h" -#include "chregistry.h" -#include "chinline.h" -#include "chqueues.h" -#include "chstreams.h" -#include "chioch.h" -#include "chdebug.h" - -#endif /* _CH_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chcond.h b/ChibiOS_2.0.8/os/kernel/include/chcond.h deleted file mode 100644 index 9022e1e..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chcond.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file are contributed by and Copyright (C) 2008 - of Leon Woestenberg. - */ - -/** - * @file chcond.h - * @brief Condition Variables macros and structures. - * - * @addtogroup condvars - * @{ - */ - -#ifndef _CHCOND_H_ -#define _CHCOND_H_ - -#if CH_USE_CONDVARS - -/* - * Module dependencies check. - */ -#if !CH_USE_MUTEXES -#error "CH_USE_CONDVARS requires CH_USE_MUTEXES" -#endif - -/** - * @brief CondVar structure. - */ -typedef struct CondVar { - ThreadsQueue c_queue; /**< @brief CondVar threads queue.*/ -} CondVar; - -#ifdef __cplusplus -extern "C" { -#endif - void chCondInit(CondVar *cp); - void chCondSignal(CondVar *cp); - void chCondSignalI(CondVar *cp); - void chCondBroadcast(CondVar *cp); - void chCondBroadcastI(CondVar *cp); - msg_t chCondWait(CondVar *cp); - msg_t chCondWaitS(CondVar *cp); -#if CH_USE_CONDVARS_TIMEOUT - msg_t chCondWaitTimeout(CondVar *cp, systime_t time); - msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time); -#endif -#ifdef __cplusplus -} -#endif - -/** - * @brief Data part of a static condition variable initializer. - * @details This macro should be used when statically initializing a condition - * variable that is part of a bigger structure. - * - * @param[in] name the name of the condition variable - */ -#define _CONDVAR_DATA(name) {_THREADSQUEUE_DATA(name.c_queue)} - -/** - * @brief Static condition variable initializer. - * @details Statically initialized condition variables require no explicit - * initialization using @p chCondInit(). - * - * @param[in] name the name of the condition variable - */ -#define CONDVAR_DECL(name) CondVar name = _CONDVAR_DATA(name) - -#endif /* CH_USE_CONDVARS */ - -#endif /* _CHCOND_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chdebug.h b/ChibiOS_2.0.8/os/kernel/include/chdebug.h deleted file mode 100644 index cfa2719..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chdebug.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chdebug.h - * @brief Debug macros and structures. - * - * @addtogroup debug - * @{ - */ - -#ifndef _CHDEBUG_H_ -#define _CHDEBUG_H_ - -/** - * @brief Trace buffer entries. - */ -#ifndef TRACE_BUFFER_SIZE -#define TRACE_BUFFER_SIZE 64 -#endif - -/** - * @brief Fill value for thread stack area in debug mode. - */ -#ifndef STACK_FILL_VALUE -#define STACK_FILL_VALUE 0x55 -#endif - -/** - * @brief Fill value for thread area in debug mode. - * @note The chosen default value is 0xFF in order to make evident which - * thread fields were not initialized when inspecting the memory with - * a debugger. A uninitialized field is not an error in itself but it - * better to know it. - */ -#ifndef THREAD_FILL_VALUE -#define THREAD_FILL_VALUE 0xFF -#endif - -#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__) -/** - * @brief Trace buffer record. - */ -typedef struct { - void *cse_wtobjp; /**< @brief Object where going to - sleep. */ - systime_t cse_time; /**< @brief Time of the switch - event. */ - uint16_t cse_state: 4; /**< @brief Switched out thread - state. */ - uint16_t cse_tid: 12; /**< @brief Switched in thread id. */ -} CtxSwcEvent; - -/** - * @brief Trace buffer header. - */ -typedef struct { - unsigned tb_size; /**< @brief Trace buffer size - (entries). */ - CtxSwcEvent *tb_ptr; /**< @brief Pointer to the ring buffer - front. */ - /** @brief Ring buffer.*/ - CtxSwcEvent tb_buffer[TRACE_BUFFER_SIZE]; -} TraceBuffer; -#endif /* CH_DBG_ENABLE_TRACE */ - -#define __QUOTE_THIS(p) #p - -#if CH_DBG_ENABLE_CHECKS -/** - * @brief Function parameter check. - * @details If the condition check fails then the kernel panics and halts. - * @note The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch - * is specified in @p chconf.h else the macro does nothing. - * - * @param[in] c the condition to be verified to be true - * @param[in] func the undecorated function name - */ -#define chDbgCheck(c, func) { \ - if (!(c)) \ - chDbgPanic(__QUOTE_THIS(func)"(), line "__QUOTE_THIS(__LINE__)); \ -} -#else /* !CH_DBG_ENABLE_CHECKS */ -#define chDbgCheck(c, func) { \ - (void)(c), (void)__QUOTE_THIS(func)"(), line "__QUOTE_THIS(__LINE__); \ -} -#endif /* !CH_DBG_ENABLE_CHECKS */ - -#if CH_DBG_ENABLE_ASSERTS -/** - * @brief Condition assertion. - * @details If the condition check fails then the kernel panics with the - * specified message and halts. - * @note The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch - * is specified in @p chconf.h else the macro does nothing. - * @note The convention for the message is the following:
- * @(), #@ - * @note The remark string is not currently used except for putting a - * comment in the code about the assertion. - * - * @param[in] c the condition to be verified to be true - * @param[in] m the text message - * @param[in] r a remark string - */ -#define chDbgAssert(c, m, r) { \ - if (!(c)) \ - chDbgPanic(m); \ -} -#else /* !CH_DBG_ENABLE_ASSERTS */ -#define chDbgAssert(c, m, r) {(void)(c);} -#endif /* !CH_DBG_ENABLE_ASSERTS */ - -#if !(CH_DBG_ENABLE_ASSERTS || \ - CH_DBG_ENABLE_CHECKS || \ - CH_DBG_ENABLE_STACK_CHECK) -/* When the debug features are disabled this function is replaced by an empty - macro.*/ -#define chDbgPanic(msg) {} -#endif - -#if !CH_DBG_ENABLE_TRACE -/* When the trace feature is disabled this function is replaced by an empty - macro.*/ -#define chDbgTrace(otp) {} -#endif - -#if !defined(__DOXYGEN__) -#ifdef __cplusplus -extern "C" { -#endif -#if CH_DBG_ENABLE_TRACE - extern TraceBuffer trace_buffer; - void trace_init(void); - void chDbgTrace(Thread *otp); -#endif -#if CH_DBG_ENABLE_ASSERTS || CH_DBG_ENABLE_CHECKS || CH_DBG_ENABLE_STACK_CHECK - extern char *panic_msg; - void chDbgPanic(char *msg); -#endif -#ifdef __cplusplus -} -#endif -#endif /* !defined(__DOXYGEN__) */ - -#endif /* _CHDEBUG_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chevents.h b/ChibiOS_2.0.8/os/kernel/include/chevents.h deleted file mode 100644 index 28c1312..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chevents.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chevents.h - * @brief Events macros and structures. - * - * @addtogroup events - * @{ - */ - -#ifndef _CHEVENTS_H_ -#define _CHEVENTS_H_ - -#if CH_USE_EVENTS - -typedef struct EventListener EventListener; - -/** - * @brief Event Listener structure. - */ -struct EventListener { - EventListener *el_next; /**< @brief Next Event Listener - registered on the Event - Source. */ - Thread *el_listener; /**< @brief Thread interested in the - Event Source. */ - eventmask_t el_mask; /**< @brief Event flags mask associated - by the thread to the Event - Source. */ -}; - -/** - * @brief Event Source structure. - */ -typedef struct EventSource { - EventListener *es_next; /**< @brief First Event Listener - registered on the Event - Source. */ -} EventSource; - -/** - * @brief Data part of a static event source initializer. - * @details This macro should be used when statically initializing an event - * source that is part of a bigger structure. - * @param name the name of the event source variable - */ -#define _EVENTSOURCE_DATA(name) {(void *)(&name)} - -/** - * @brief Static event source initializer. - * @details Statically initialized event sources require no explicit - * initialization using @p chEvtInit(). - * - * @param name the name of the event source variable - */ -#define EVENTSOURCE_DECL(name) EventSource name = _EVENTSOURCE_DATA(name) - -/** All events allowed mask.*/ -#define ALL_EVENTS ((eventmask_t)-1) - -/** Returns the event mask from the event identifier.*/ -#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid))) - -/** - * @brief Registers an Event Listener on an Event Source. - * @note Multiple Event Listeners can use the same event identifier, the - * listener will share the callback function. - * - * @param[in] esp pointer to the @p EventSource structure - * @param[out] elp pointer to the @p EventListener structure - * @param[in] eid numeric identifier assigned to the Event Listener. The - * identifier is used as index for the event callback - * function. - * The value must range between zero and the size, in bit, - * of the @p eventid_t type minus one. - */ -#define chEvtRegister(esp, elp, eid) chEvtRegisterMask(esp, elp, EVENT_MASK(eid)) - -/** - * @brief Initializes an Event Source. - * @note Can be used with interrupts disabled or enabled. - * - * @param[in] esp pointer to the @p EventSource structure - */ -#define chEvtInit(esp) \ - ((esp)->es_next = (EventListener *)(void *)(esp)) - -/** - * @brief Verifies if there is at least one @p EventListener registered. - * @note Can be called with interrupts disabled or enabled. - * - * @param[in] esp pointer to the @p EventSource structure - */ -#define chEvtIsListening(esp) \ - ((void *)(esp) != (void *)(esp)->es_next) - -/** - * @brief Event Handler callback function. - */ -typedef void (*evhandler_t)(eventid_t); - -#ifdef __cplusplus -extern "C" { -#endif - void chEvtRegisterMask(EventSource *esp, - EventListener *elp, - eventmask_t mask); - void chEvtUnregister(EventSource *esp, EventListener *elp); - eventmask_t chEvtClear(eventmask_t mask); - eventmask_t chEvtPend(eventmask_t mask); - void chEvtSignal(Thread *tp, eventmask_t mask); - void chEvtSignalI(Thread *tp, eventmask_t mask); - void chEvtBroadcast(EventSource *esp); - void chEvtBroadcastI(EventSource *esp); - void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask); -#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT - eventmask_t chEvtWaitOne(eventmask_t mask); - eventmask_t chEvtWaitAny(eventmask_t mask); - eventmask_t chEvtWaitAll(eventmask_t mask); -#endif -#if CH_USE_EVENTS_TIMEOUT - eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time); - eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time); - eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time); -#endif -#ifdef __cplusplus -} -#endif - -#if !CH_OPTIMIZE_SPEED && CH_USE_EVENTS_TIMEOUT -#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE) -#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE) -#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE) -#endif - -#endif /* CH_USE_EVENTS */ - -#endif /* _CHEVENTS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chheap.h b/ChibiOS_2.0.8/os/kernel/include/chheap.h deleted file mode 100644 index 57ae4f2..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chheap.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chheap.h - * @brief Heaps macros and structures. - * - * @addtogroup heaps - * @{ - */ - -#ifndef _CHHEAP_H_ -#define _CHHEAP_H_ - -#if CH_USE_HEAP - -/* - * Module dependencies check. - */ -#if !CH_USE_MEMCORE && !CH_USE_MALLOC_HEAP -#error "CH_USE_HEAP requires CH_USE_MEMCORE or CH_USE_MALLOC_HEAP" -#endif - -#if !CH_USE_MUTEXES && !CH_USE_SEMAPHORES -#error "CH_USE_HEAP requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" -#endif - -typedef struct memory_heap MemoryHeap; - -/** - * @brief Memory heap block header. - */ -union heap_header { - stkalign_t align; - struct { - union { - union heap_header *next; /**< @brief Next block in free list. */ - MemoryHeap *heap; /**< @brief Block owner heap. */ - } u; /**< @brief Overlapped fields. */ - size_t size; /**< @brief Size of the memory block. */ - } h; -}; - -/** - * @brief Structure describing a memory heap. - */ -struct memory_heap { - memgetfunc_t h_provider; /**< @brief Memory blocks provider for - this heap. */ - union heap_header h_free; /**< @brief Free blocks list header. */ -#if CH_USE_MUTEXES - Mutex h_mtx; /**< @brief Heap access mutex. */ -#else - Semaphore h_sem; /**< @brief Heap access semaphore. */ -#endif -}; - -#ifdef __cplusplus -extern "C" { -#endif - void heap_init(void); - void chHeapInit(MemoryHeap *heapp, void *buf, size_t size); - void *chHeapAlloc(MemoryHeap *heapp, size_t size); - void chHeapFree(void *p); - size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_HEAP */ - -#endif /* _CHHEAP_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chinline.h b/ChibiOS_2.0.8/os/kernel/include/chinline.h deleted file mode 100644 index 14a9f6d..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chinline.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chinline.h - * @brief Kernel inlined functions. - * @details In this file there are a set of inlined functions if the - * @p CH_OPTIMIZE_SPEED is enabled. - */ - -#ifndef _CHINLINE_H_ -#define _CHINLINE_H_ - -/* If the performance code path has been chosen then all the following - functions are inlined into the various kernel modules.*/ -#if CH_OPTIMIZE_SPEED -static INLINE void prio_insert(Thread *tp, ThreadsQueue *tqp) { - - Thread *cp = (Thread *)tqp; - do { - cp = cp->p_next; - } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio)); - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = cp->p_prev = tp; -} - -static INLINE void queue_insert(Thread *tp, ThreadsQueue *tqp) { - - tp->p_next = (Thread *)tqp; - tp->p_prev = tqp->p_prev; - tp->p_prev->p_next = tqp->p_prev = tp; -} - -static INLINE Thread *fifo_remove(ThreadsQueue *tqp) { - Thread *tp = tqp->p_next; - - (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp; - return tp; -} - -static INLINE Thread *lifo_remove(ThreadsQueue *tqp) { - Thread *tp = tqp->p_prev; - - (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp; - return tp; -} - -static INLINE Thread *dequeue(Thread *tp) { - - tp->p_prev->p_next = tp->p_next; - tp->p_next->p_prev = tp->p_prev; - return tp; -} - -static INLINE void list_insert(Thread *tp, ThreadsList *tlp) { - - tp->p_next = tlp->p_next; - tlp->p_next = tp; -} - -static INLINE Thread *list_remove(ThreadsList *tlp) { - - Thread *tp = tlp->p_next; - tlp->p_next = tp->p_next; - return tp; -} -#endif /* CH_OPTIMIZE_SPEED */ - -#endif /* _CHINLINE_H_ */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chioch.h b/ChibiOS_2.0.8/os/kernel/include/chioch.h deleted file mode 100644 index 9bd4198..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chioch.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chioch.h - * @brief I/O channels. - * @details This header defines abstract interfaces useful to access generic - * I/O resources in a standardized way. - * - * @addtogroup io_channels - * @details This module defines an abstract interface for I/O channels by - * extending the @p BaseSequentialStream interface. Note that no code - * is present, I/O channels are just abstract interface like - * structures, you should look at the systems as to a set of abstract - * C++ classes (even if written in C). Specific device drivers can - * use/extend the interface and implement them.
- * This system has the advantage to make the access to channels - * independent from the implementation logic. - * @{ - */ - -#ifndef _CHIOCH_H_ -#define _CHIOCH_H_ - -/** - * @brief @p BaseChannel specific methods. - */ -#define _base_channel_methods \ - _base_sequential_stream_methods \ - /* Channel output check.*/ \ - bool_t (*putwouldblock)(void *instance); \ - /* Channel input check.*/ \ - bool_t (*getwouldblock)(void *instance); \ - /* Channel put method with timeout specification.*/ \ - msg_t (*put)(void *instance, uint8_t b, systime_t time); \ - /* Channel get method with timeout specification.*/ \ - msg_t (*get)(void *instance, systime_t time); \ - /* Channel write method with timeout specification.*/ \ - size_t (*writet)(void *instance, const uint8_t *bp, \ - size_t n, systime_t time); \ - /* Channel read method with timeout specification.*/ \ - size_t (*readt)(void *instance, uint8_t *bp, size_t n, systime_t time); - -/** - * @brief @p BaseChannel specific data. - * @note It is empty because @p BaseChannel is only an interface without - * implementation. - */ -#define _base_channel_data \ - _base_sequential_stream_data - -/** - * @brief @p BaseChannel virtual methods table. - */ -struct BaseChannelVMT { \ - _base_channel_methods \ -}; - -/** - * @extends BaseSequentialStream - * - * @brief Base channel class. - * @details This class represents a generic, byte-wide, I/O channel. This class - * introduces generic I/O primitives with timeout specification. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseChannelVMT *vmt; - _base_channel_data -} BaseChannel; - -/** - * @brief Channel output check. - * @details This function verifies if a subsequent put/write operation would - * block. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @return The output queue status: - * @retval FALSE if the output queue has space and would not block a - * write operation. - * @retval TRUE if the output queue is full and would block a write - * operation. - */ -#define chIOPutWouldBlock(ip) ((ip)->vmt->putwouldblock(ip)) - -/** - * @brief Channel input check. - * @details This function verifies if a subsequent get/read operation would - * block. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @return The input queue status: - * @retval FALSE if the input queue contains data and would not block a - * read operation. - * @retval TRUE if the input queue is empty and would block a read - * operation. - */ -#define chIOGetWouldBlock(ip) ((ip)->vmt->getwouldblock(ip)) - -/** - * @brief Channel blocking byte write. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] b the byte value to be written to the channel - * @return The operation status: - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if the channel associated queue (if any) was reset. - */ -#define chIOPut(ip, b) ((ip)->vmt->put(ip, b, TIME_INFINITE)) - -/** - * @brief Channel blocking byte write with timeout. - * @details This function writes a byte value to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] b the byte value to be written to the channel - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status: - * @retval Q_OK if the operation succeeded. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the channel associated queue (if any) was reset. - */ -#define chIOPutTimeout(ip, b, time) ((ip)->vmt->put(ip, b, time)) - -/** - * @brief Channel blocking byte read. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @return A byte value from the queue or: - * @retval Q_RESET if the channel associated queue (if any) was reset. - */ -#define chIOGet(ip) ((ip)->vmt->get(ip, TIME_INFINITE)) - -/** - * @brief Channel blocking byte read with timeout. - * @details This function reads a byte value from a channel. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue or: - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the channel associated queue (if any) was reset. - */ -#define chIOGetTimeout(ip, time) ((ip)->vmt->get(ip, time)) - -/** - * @brief Channel blocking write with timeout. - * @details The function writes data from a buffer to a channel. If the channel - * is not ready to accept data then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes transferred. - */ -#define chIOWriteTimeout(ip, bp, n, time) \ - ((ip)->vmt->writet(ip, bp, n, time)) - -/** - * @brief Channel blocking read with timeout. - * @details The function reads data from a channel into a buffer. If the data - * is not available then the calling thread is suspended. - * - * @param[in] ip pointer to a @p BaseChannel or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes transferred. - */ -#define chIOReadTimeout(ip, bp, n, time) \ - ((ip)->vmt->readt(ip, bp, n, time)) - -#if CH_USE_EVENTS -/** - * @brief @p BaseAsynchronousChannel specific methods. - */ -#define _base_asynchronous_channel_methods \ - _base_channel_methods - -/** - * @brief @p BaseAsynchronousChannel specific data. - */ -#define _base_asynchronous_channel_data \ - _base_channel_data \ - /* Data Available EventSource.*/ \ - EventSource ievent; \ - /* Data Transmitted EventSource.*/ \ - EventSource oevent; - -/** - * @brief @p BaseAsynchronousChannel virtual methods table. - */ -struct BaseAsynchronousChannelVMT { - _base_asynchronous_channel_methods -}; - -/** - * @extends BaseChannel - * - * @brief Base asynchronous channel class. - * @details This class extends @p BaseChannel by adding event sources fields - * for asynchronous I/O for use in an event-driven environment. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseAsynchronousChannelVMT *vmt; - _base_asynchronous_channel_data -} BaseAsynchronousChannel; - -/** - * @brief Returns the write event source. - * @details The write event source is broadcasted when the channel is ready - * for write operations. This usually happens when the internal - * output queue becomes empty. - * - * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived - * class - * @return A pointer to an @p EventSource object. - */ -#define chIOGetWriteEventSource(ip) (&((ip)->vmt->oevent)) - -/** - * @brief Returns the read event source. - * @details The read event source is broadcasted when the channel is ready - * for read operations. This usually happens when the internal - * input queue becomes non-empty. - * - * @param[in] ip pointer to a @p BaseAsynchronousChannel or derived - * class - * @return A pointer to an @p EventSource object. - */ -#define chIOGetReadEventSource(ip) (&((ip)->vmt->ievent)) - -#endif /* CH_USE_EVENTS */ - -#endif /* _CHIOCH_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chlists.h b/ChibiOS_2.0.8/os/kernel/include/chlists.h deleted file mode 100644 index 70a3451..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chlists.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chlists.h - * @brief Thread queues/lists macros and structures. - * @note All the macros present in this module, while public, are not - * an OS API and should not be directly used in the user applications - * code. - * - * @addtogroup internals - * @{ - */ - -#ifndef _CHLISTS_H_ -#define _CHLISTS_H_ - -typedef struct Thread Thread; - -/** - * @brief Threads queue initialization. - */ -#define queue_init(tqp) ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp)); - -/** - * @brief Threads list initialization. - */ -#define list_init(tlp) ((tlp)->p_next = (Thread *)(tlp)) - -/** - * @brief Evaluates to @p TRUE if the specified threads queue or list is - * empty. - */ -#define isempty(p) ((p)->p_next == (Thread *)(p)) - -/** - * @brief Evaluates to @p TRUE if the specified threads queue or list is - * not empty. - */ -#define notempty(p) ((p)->p_next != (Thread *)(p)) - -/** - * @brief Data part of a static threads queue initializer. - * @details This macro should be used when statically initializing a threads - * queue that is part of a bigger structure. - * - * @param[in] name the name of the threads queue variable - */ -#define _THREADSQUEUE_DATA(name) {(Thread *)&name, (Thread *)&name} - -/** - * @brief Static threads queue initializer. - * @details Statically initialized threads queues require no explicit - * initialization using @p queue_init(). - * - * @param[in] name the name of the threads queue variable - */ -#define THREADSQUEUE_DECL(name) ThreadsQueue name = _THREADSQUEUE_DATA(name) - -/** - * @extends ThreadsList - * - * @brief Generic threads bidirectional linked list header and element. - */ -typedef struct { - Thread *p_next; /**< First @p Thread in the queue, or - @p ThreadQueue when empty. */ - Thread *p_prev; /**< Last @p Thread in the queue, or - @p ThreadQueue when empty. */ -} ThreadsQueue; - -/** - * @brief Generic threads single link list, it works like a stack. - */ -typedef struct { - - Thread *p_next; /**< Last pushed @p Thread on the stack - list, or pointer to itself if - empty. */ -} ThreadsList; - -#if !CH_OPTIMIZE_SPEED - -#ifdef __cplusplus -extern "C" { -#endif - void prio_insert(Thread *tp, ThreadsQueue *tqp); - void queue_insert(Thread *tp, ThreadsQueue *tqp); - Thread *fifo_remove(ThreadsQueue *tqp); - Thread *lifo_remove(ThreadsQueue *tqp); - Thread *dequeue(Thread *tp); - void list_insert(Thread *tp, ThreadsList *tlp); - Thread *list_remove(ThreadsList *tlp); -#ifdef __cplusplus -} -#endif - -#endif /* !CH_OPTIMIZE_SPEED */ - -#endif /* _CHLISTS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chmboxes.h b/ChibiOS_2.0.8/os/kernel/include/chmboxes.h deleted file mode 100644 index d8e3d75..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chmboxes.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmboxes.h - * @brief Mailboxes macros and structures. - * - * @addtogroup mailboxes - * @{ - */ - -#ifndef _CHMBOXES_H_ -#define _CHMBOXES_H_ - -#if CH_USE_MAILBOXES - -/* - * Module dependencies check. - */ -#if !CH_USE_SEMAPHORES -#error "CH_USE_MAILBOXES requires CH_USE_SEMAPHORES" -#endif - -typedef struct { - msg_t *mb_buffer; /**< @brief Pointer to the mailbox - buffer. */ - msg_t *mb_top; /**< @brief Pointer to the location - after the buffer. */ - msg_t *mb_wrptr; /**< @brief Write pointer. */ - msg_t *mb_rdptr; /**< @brief Read pointer. */ - Semaphore mb_fullsem; /**< @brief Full counter - @p Semaphore. */ - Semaphore mb_emptysem; /**< @brief Empty counter - @p Semaphore. */ -} Mailbox; - -#ifdef __cplusplus -extern "C" { -#endif - void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n); - void chMBReset(Mailbox *mbp); - msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t timeout); - msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t timeout); - msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t timeout); - msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t timeout); -#ifdef __cplusplus -} -#endif - -/** - * @brief Returns the mailbox buffer size. - * - * @param[in] mbp the pointer to an initialized Mailbox object - */ -#define chMBSize(mbp) \ - ((mbp)->mb_top - (mbp)->mb_buffer) - -/** - * @brief Returns the free space into the mailbox. - * @note Can be invoked in any system state but if invoked out of a locked - * state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @return The number of empty message slots. - */ -#define chMBGetEmpty(mbp) chSemGetCounterI(&(mbp)->mb_emptysem) - -/** - * @brief Returns the number of messages into the mailbox. - * @note Can be invoked in any system state but if invoked out of a locked - * state then the returned value may change after reading. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @return The number of queued messages. - */ -#define chMBGetFull(mbp) chSemGetCounterI(&(mbp)->mb_fullsem) - -/** - * @brief Returns the next message in the queue without removing it. - * @note A message must be waiting in the queue for this function to work or - * it would return garbage. The correct way to use this macro is to - * use @p chMBGetFull() and then use this macro, all within a lock - * state. - */ -#define chMBPeek(mbp) (*(mbp)->mb_rdptr) - -/** - * @brief Data part of a static mailbox initializer. - * @details This macro should be used when statically initializing a - * mailbox that is part of a bigger structure. - * - * @param[in] name the name of the mailbox variable - * @param[in] buffer pointer to the mailbox buffer area - * @param[in] size size of the mailbox buffer area - */ -#define _MAILBOX_DATA(name, buffer, size) { \ - (msg_t *)(buffer), \ - (msg_t *)(buffer) + size, \ - (msg_t *)(buffer), \ - (msg_t *)(buffer), \ - _SEMAPHORE_DATA(name.mb_fullsem, 0), \ - _SEMAPHORE_DATA(name.mb_emptysem, size), \ -} - -/** - * @brief Static mailbox initializer. - * @details Statically initialized mailboxes require no explicit - * initialization using @p chMBInit(). - * - * @param[in] name the name of the mailbox variable - * @param[in] buffer pointer to the mailbox buffer area - * @param[in] size size of the mailbox buffer area - */ -#define MAILBOX_DECL(name, buffer, size) \ - Mailbox name = _MAILBOX_DATA(name, buffer, size) - -#endif /* CH_USE_MAILBOXES */ - -#endif /* _CHMBOXES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chmemcore.h b/ChibiOS_2.0.8/os/kernel/include/chmemcore.h deleted file mode 100644 index 7ec59c5..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chmemcore.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmemcore.h - * @brief Core memory manager macros and structures. - * - * @addtogroup memcore - * @{ - */ - -#ifndef _CHMEMCORE_H_ -#define _CHMEMCORE_H_ - -/** - * @brief Memory get function. - * @note This type must be assignment compatible with the @p chMemAlloc() - * function. - */ -typedef void *(*memgetfunc_t)(size_t size); - -/** - * @brief Alignment mask constant. - */ -#define MEM_ALIGN_MASK (sizeof(stkalign_t) - 1) - -/** - * @brief Alignment helper macro. - */ -#define MEM_ALIGN_SIZE(p) (((size_t)(p) + MEM_ALIGN_MASK) & ~MEM_ALIGN_MASK) - -/** - * @brief Returns whatever a pointer or memory size is aligned to - * the type @p align_t. - */ -#define MEM_IS_ALIGNED(p) (((size_t)(p) & MEM_ALIGN_MASK) == 0) - -#if CH_USE_MEMCORE - -#ifdef __cplusplus -extern "C" { -#endif - void core_init(void); - void *chCoreAlloc(size_t size); - void *chCoreAllocI(size_t size); - size_t chCoreStatus(void); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_MEMCORE */ - -#endif /* _CHMEMCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chmempools.h b/ChibiOS_2.0.8/os/kernel/include/chmempools.h deleted file mode 100644 index 1813f60..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chmempools.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmempools.h - * @brief Memory Pools macros and structures. - * - * @addtogroup pools - * @{ - */ - -#ifndef _CHMEMPOOLS_H_ -#define _CHMEMPOOLS_H_ - -#if CH_USE_MEMPOOLS - -/** - * @brief Memory pool free object header. - */ -struct pool_header { - struct pool_header *ph_next; /**< @brief Pointer to the next pool - header in the list. */ -}; - -/** - * @brief Memory pool descriptor. - */ -typedef struct { - struct pool_header *mp_next; /**< @brief Pointer to the header. */ - size_t mp_object_size; /**< @brief Memory pool objects - size. */ - memgetfunc_t mp_provider; /**< @brief Memory blocks provider for - this pool. */ -} MemoryPool; - -/** - * @brief Data part of a static memory pool initializer. - * @details This macro should be used when statically initializing a - * memory pool that is part of a bigger structure. - * - * @param[in] name the name of the memory pool variable - * @param[in] size size of the memory pool contained objects - * @param[in] provider memory provider function for the memory pool - */ -#define _MEMORYPOOL_DATA(name, size, provider) \ - {NULL, MEM_ALIGN_SIZE(size), provider} - -/** - * @brief Static memory pool initializer in hungry mode. - * @details Statically initialized memory pools require no explicit - * initialization using @p chPoolInit(). - * - * @param[in] name the name of the memory pool variable - * @param[in] size size of the memory pool contained objects - * @param[in] provider memory provider function for the memory pool or @p NULL - * if the pool is not allowed to grow automatically - */ -#define MEMORYPOOL_DECL(name, size, provider) \ - MemoryPool name = _MEMORYPOOL_DATA(name, size, provider) - -#ifdef __cplusplus -extern "C" { -#endif - void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider); - void *chPoolAllocI(MemoryPool *mp); - void *chPoolAlloc(MemoryPool *mp); - void chPoolFreeI(MemoryPool *mp, void *objp); - void chPoolFree(MemoryPool *mp, void *objp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_MEMPOOLS */ - -#endif /* _CHMEMPOOLS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chmsg.h b/ChibiOS_2.0.8/os/kernel/include/chmsg.h deleted file mode 100644 index e4d4cdd..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chmsg.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmsg.h - * @brief Messages macros and structures. - * - * @addtogroup messages - * @{ - */ - -#ifndef _CHMSG_H_ -#define _CHMSG_H_ - -#if CH_USE_MESSAGES - -/** - * @brief Evaluates to TRUE if the thread has pending messages. - */ -#define chMsgIsPendingI(tp) \ - ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue) - -/** - * @brief Returns the first message in the queue. - */ -#define chMsgGetI(tp) \ - ((tp)->p_msgqueue.p_next->p_msg) - -#ifdef __cplusplus -extern "C" { -#endif - msg_t chMsgSend(Thread *tp, msg_t msg); - msg_t chMsgWait(void); - msg_t chMsgGet(void); - void chMsgRelease(msg_t msg); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_MESSAGES */ - -#endif /* _CHMSG_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chmtx.h b/ChibiOS_2.0.8/os/kernel/include/chmtx.h deleted file mode 100644 index 8f796ea..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chmtx.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmtx.h - * @brief Mutexes macros and structures. - * - * @addtogroup mutexes - * @{ - */ - -#ifndef _CHMTX_H_ -#define _CHMTX_H_ - -#if CH_USE_MUTEXES - -/** - * @brief Mutex structure. - */ -typedef struct Mutex { - ThreadsQueue m_queue; /**< @brief Queue of the threads sleeping - on this Mutex. */ - Thread *m_owner; /**< @brief Owner @p Thread pointer or - @p NULL. */ - struct Mutex *m_next; /**< @brief Next @p Mutex into an - owner-list or @p NULL. */ -} Mutex; - -#ifdef __cplusplus -extern "C" { -#endif - void chMtxInit(Mutex *mp); - void chMtxLock(Mutex *mp); - void chMtxLockS(Mutex *mp); - bool_t chMtxTryLock(Mutex *mp); - bool_t chMtxTryLockS(Mutex *mp); - Mutex *chMtxUnlock(void); - Mutex *chMtxUnlockS(void); - void chMtxUnlockAll(void); -#ifdef __cplusplus -} -#endif - -/** - * @brief Data part of a static mutex initializer. - * @details This macro should be used when statically initializing a mutex - * that is part of a bigger structure. - * - * @param[in] name the name of the mutex variable - */ -#define _MUTEX_DATA(name) {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL} - -/** - * @brief Static mutex initializer. - * @details Statically initialized mutexes require no explicit initialization - * using @p chMtxInit(). - * - * @param[in] name the name of the mutex variable - */ -#define MUTEX_DECL(name) Mutex name = _MUTEX_DATA(name) - -/** - * @brief Returns @p TRUE if the mutex queue contains at least a waiting - * thread. - */ -#define chMtxQueueNotEmptyS(mp) notempty(&(mp)->m_queue) - -#endif /* CH_USE_MUTEXES */ - -#endif /* _CHMTX_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chqueues.h b/ChibiOS_2.0.8/os/kernel/include/chqueues.h deleted file mode 100644 index 5056e51..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chqueues.h +++ /dev/null @@ -1,249 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chqueues.h I/O - * @brief Queues macros and structures. - * - * @addtogroup io_queues - * @{ - */ - -#ifndef _CHQUEUES_H_ -#define _CHQUEUES_H_ - -#if CH_USE_QUEUES - -/* - * Module dependencies check. - */ -#if !CH_USE_SEMAPHORES -#error "CH_USE_QUEUES requires CH_USE_SEMAPHORES" -#endif - -/** @brief Queue notification callback type.*/ -typedef void (*qnotify_t)(void); - -/** @brief Returned by the queue functions if the operation is successful.*/ -#define Q_OK RDY_OK -/** @brief Returned by the queue functions if a timeout occurs.*/ -#define Q_TIMEOUT RDY_TIMEOUT -/** @brief Returned by the queue functions if the queue is reset.*/ -#define Q_RESET RDY_RESET -/** @brief Returned by the queue functions if the queue is empty.*/ -#define Q_EMPTY -3 -/** @brief Returned by the queue functions if the queue is full.*/ -#define Q_FULL -4 - -/** - * @brief Generic I/O queue structure. - * @details This structure represents a generic Input or Output asymmetrical - * queue. The queue is asymmetrical because one end is meant to be - * accessed from a thread context, and thus can be blocking, the other - * end is accessible from interrupt handlers or from within a kernel - * lock zone (see I-Locked and S-Locked states in - * @ref system_states) and is non-blocking. - */ -typedef struct { - uint8_t *q_buffer; /**< @brief Pointer to the queue buffer.*/ - uint8_t *q_top; /**< @brief Pointer to the first location - after the buffer. */ - uint8_t *q_wrptr; /**< @brief Write pointer. */ - uint8_t *q_rdptr; /**< @brief Read pointer. */ - Semaphore q_sem; /**< @brief Counter @p Semaphore. */ - qnotify_t q_notify; /**< @brief Data notification callback. */ -} GenericQueue; - -/** - * @brief Returns the queue's buffer size. - */ -#define chQSize(q) ((q)->q_top - (q)->q_buffer) - -/** - * @brief Queue space. - * @details Returns the used space if used on an Input Queue and the empty - * space if used on an Output Queue. - * @note The returned value can be less than zero when there are waiting - * threads on the internal semaphore. - */ -#define chQSpace(q) chSemGetCounterI(&(q)->q_sem) - -/** - * @extends GenericQueue - * - * @brief Input queue structure. - * @details This structure represents a generic asymmetrical input queue. - * Writing in the queue is non-blocking and can be performed from - * interrupt handlers or from within a kernel lock zone (see - * I-Locked and S-Locked states in @ref system_states). - * Reading the queue can be a blocking operation and is supposed to - * be performed by a system thread. - */ -typedef GenericQueue InputQueue; - -/** @brief Evaluates to @p TRUE if the specified Input Queue is empty.*/ -#define chIQIsEmpty(q) ((bool_t)(chQSpace(q) <= 0)) - -/** @brief Evaluates to @p TRUE if the specified Input Queue is full.*/ -#define chIQIsFull(q) ((bool_t)(chQSpace(q) >= chQSize(q))) - -/** - * @brief Input queue read. - * @details This function reads a byte value from an input queue. If the queue - * is empty then the calling thread is suspended until a byte arrives - * in the queue. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @return A byte value from the queue or: - * @retval Q_RESET if the queue was reset. - */ -#define chIQGet(iqp) chIQGetTimeout(iqp, TIME_INFINITE) - -/** - * @brief Data part of a static input queue initializer. - * @details This macro should be used when statically initializing an - * input queue that is part of a bigger structure. - * - * @param[in] name the name of the input queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] inotify input notification callback pointer - */ -#define _INPUTQUEUE_DATA(name, buffer, size, inotify) { \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer) + size, \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer), \ - _SEMAPHORE_DATA(name.q_sem, 0), \ - inotify \ -} - -/** - * @brief Static input queue initializer. - * @details Statically initialized input queues require no explicit - * initialization using @p chIQInit(). - * - * @param[in] name the name of the input queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] inotify input notification callback pointer - */ -#define INPUTQUEUE_DECL(name, buffer, size, inotify) \ - InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify) - -/** - * @extends GenericQueue - * - * @brief Output queue structure. - * @details This structure represents a generic asymmetrical output queue. - * Reading from the queue is non-blocking and can be performed from - * interrupt handlers or from within a kernel lock zone (see - * I-Locked and S-Locked states in @ref system_states). - * Writing the queue can be a blocking operation and is supposed to - * be performed by a system thread. - */ -typedef GenericQueue OutputQueue; - -/** - * @brief Evaluates to @p TRUE if the specified Output Queue is empty. - */ -#define chOQIsEmpty(q) ((bool_t)(chQSpace(q) >= chQSize(q))) - -/** - * @brief Evaluates to @p TRUE if the specified Output Queue is full. - */ -#define chOQIsFull(q) ((bool_t)(chQSpace(q) <= 0)) - -/** - * @brief Output queue write. - * @details This function writes a byte value to an output queue. If the queue - * is full then the calling thread is suspended until there is space - * in the queue. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @param[in] b the byte value to be written in the queue - * @return The operation status: - * @retval Q_OK if the operation succeeded. - * @retval Q_RESET if the queue was reset. - */ -#define chOQPut(oqp, b) chOQPutTimeout(oqp, b, TIME_INFINITE) - -/** - * @brief Data part of a static output queue initializer. - * @details This macro should be used when statically initializing an - * output queue that is part of a bigger structure. - * - * @param[in] name the name of the output queue variable. - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] onotify output notification callback pointer - */ -#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify) { \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer) + size, \ - (uint8_t *)(buffer), \ - (uint8_t *)(buffer), \ - _SEMAPHORE_DATA(name.q_sem, size), \ - onotify \ -} - -/** - * @brief Static output queue initializer. - * @details Statically initialized output queues require no explicit - * initialization using @p chOQInit(). - * - * @param[in] name the name of the output queue variable - * @param[in] buffer pointer to the queue buffer area - * @param[in] size size of the queue buffer area - * @param[in] onotify output notification callback pointer - */ -#define OUTPUTQUEUE_DECL(name, buffer, size, onotify) \ - InputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify) - -#ifdef __cplusplus -extern "C" { -#endif - void chIQInit(InputQueue *qp, uint8_t *bp, size_t size, qnotify_t infy); - void chIQResetI(InputQueue *qp); - msg_t chIQPutI(InputQueue *qp, uint8_t b); - msg_t chIQGetTimeout(InputQueue *qp, systime_t time); - size_t chIQReadTimeout(InputQueue *qp, uint8_t *bp, - size_t n, systime_t time); - - void chOQInit(OutputQueue *queue, uint8_t *bp, size_t size, qnotify_t onfy); - void chOQResetI(OutputQueue *queue); - msg_t chOQPutTimeout(OutputQueue *queue, uint8_t b, systime_t time); - msg_t chOQGetI(OutputQueue *queue); - size_t chOQWriteTimeout(OutputQueue *queue, const uint8_t *bp, - size_t n, systime_t time); -#ifdef __cplusplus -} -#endif -#endif /* CH_USE_QUEUES */ - -#endif /* _CHQUEUES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chregistry.h b/ChibiOS_2.0.8/os/kernel/include/chregistry.h deleted file mode 100644 index 38cf4ce..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chregistry.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chregistry.h - * @brief Threads registry macros and structures. - * - * @addtogroup registry - * @{ - */ - -#ifndef _CHREGISTRY_H_ -#define _CHREGISTRY_H_ - -#if CH_USE_REGISTRY - -/** - * @brief Removes a thread from the registry list. - * @note This macro is not meant for use in application code. - * - * @param[in] tp thread to remove from the registry - */ -#define REG_REMOVE(tp) { \ - (tp)->p_older->p_newer = (tp)->p_newer; \ - (tp)->p_newer->p_older = (tp)->p_older; \ -} - -/** - * @brief Adds a thread to the registry list. - * @note This macro is not meant for use in application code. - * - * @param[in] tp thread to add to the registry - */ -#define REG_INSERT(tp) { \ - (tp)->p_newer = (Thread *)&rlist; \ - (tp)->p_older = rlist.r_older; \ - (tp)->p_older->p_newer = rlist.r_older = (tp); \ -} - -#ifdef __cplusplus -extern "C" { -#endif - Thread *chRegFirstThread(void); - Thread *chRegNextThread(Thread *tp); -#ifdef __cplusplus -} -#endif - -#endif /* CH_USE_REGISTRY */ - -#endif /* _CHREGISTRY_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chschd.h b/ChibiOS_2.0.8/os/kernel/include/chschd.h deleted file mode 100644 index 8799520..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chschd.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chschd.h - * @brief Scheduler macros and structures. - * - * @addtogroup scheduler - * @{ - */ - -#ifndef _CHSCHD_H_ -#define _CHSCHD_H_ - -/** @brief Default thread wakeup low level message.*/ -#define RDY_OK 0 -/** @brief Low level message sent to a thread awakened by a timeout.*/ -#define RDY_TIMEOUT -1 -/** @brief Low level message sent to a thread awakened by a reset operation.*/ -#define RDY_RESET -2 - -#define NOPRIO 0 /**< @brief Ready list header priority. */ -#define IDLEPRIO 1 /**< @brief Idle thread priority. */ -#define LOWPRIO 2 /**< @brief Lowest user priority. */ -#define NORMALPRIO 64 /**< @brief Normal user priority. */ -#define HIGHPRIO 127 /**< @brief Highest user priority. */ -#define ABSPRIO 255 /**< @brief Greatest possible priority. */ - -/** - * @brief Zero time specification for some syscalls with a timeout - * specification. - * @note Not all functions accept @p TIME_IMMEDIATE as timeout parameter, - * see the specific function documentation. - */ -#define TIME_IMMEDIATE ((systime_t)-1) - -/** - * @brief Infinite time specification for all the syscalls with a timeout - * specification. - */ -#define TIME_INFINITE ((systime_t)0) - -/** - * @brief Returns the priority of the first thread on the given ready list. - */ -#define firstprio(rlp) ((rlp)->p_next->p_prio) - -/** - * @extends ThreadsQueue - * - * @brief Ready list header. - */ -#if !defined(PORT_OPTIMIZED_READYLIST_STRUCT) || defined(__DOXYGEN__) -typedef struct { - ThreadsQueue r_queue; /**< @brief Threads queue. */ - tprio_t r_prio; /**< @brief This field must be - initialized to zero. */ - struct context r_ctx; /**< @brief Not used, present because - offsets. */ -#if CH_USE_REGISTRY - Thread *r_newer; /**< @brief Newer registry element. */ - Thread *r_older; /**< @brief Older registry element. */ -#endif - /* End of the fields shared with the Thread structure.*/ -#if CH_TIME_QUANTUM > 0 - cnt_t r_preempt; /**< @brief Round robin counter. */ -#endif -#ifndef CH_CURRP_REGISTER_CACHE - Thread *r_current; /**< @brief The currently running - thread. */ -#endif -} ReadyList; -#endif /* !defined(PORT_OPTIMIZED_READYLIST_STRUCT) */ - -#if !defined(PORT_OPTIMIZED_RLIST_EXT) && !defined(__DOXYGEN__) -extern ReadyList rlist; -#endif /* !defined(PORT_OPTIMIZED_RLIST_EXT) */ - -/** - * @brief Current thread pointer access macro. - * @note This macro is not meant to be used in the application code but - * only from within the kernel, use the @p chThdSelf() API instead. - * @note It is forbidden to use this macro in order to change the pointer - * (currp = something), use @p setcurrp() instead. - */ -#if !defined(PORT_OPTIMIZED_CURRP) || defined(__DOXYGEN__) -#if !defined(CH_CURRP_REGISTER_CACHE) || defined(__DOXYGEN__) -#define currp rlist.r_current -#else /* defined(CH_CURRP_REGISTER_CACHE) */ -register Thread *currp asm(CH_CURRP_REGISTER_CACHE); -#endif /* defined(CH_CURRP_REGISTER_CACHE) */ -#endif /* !defined(PORT_OPTIMIZED_CURRP) */ - -/** - * @brief Current thread pointer change macro. - * @note This macro is not meant to be used in the application code but - * only from within the kernel. - */ -#if !defined(PORT_OPTIMIZED_SETCURRP) || defined(__DOXYGEN__) -#define setcurrp(tp) (currp = (tp)) -#endif /* !defined(PORT_OPTIMIZED_SETCURRP) */ - -/* - * Scheduler APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - void scheduler_init(void); -#if !defined(PORT_OPTIMIZED_READYI) - Thread *chSchReadyI(Thread *tp); -#endif -#if !defined(PORT_OPTIMIZED_GOSLEEPS) - void chSchGoSleepS(tstate_t newstate); -#endif -#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) - msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time); -#endif -#if !defined(PORT_OPTIMIZED_WAKEUPS) - void chSchWakeupS(Thread *tp, msg_t msg); -#endif -#if !defined(PORT_OPTIMIZED_DORESCHEDULEI) - void chSchDoRescheduleI(void); -#endif -#if !defined(PORT_OPTIMIZED_RESCHEDULES) - void chSchRescheduleS(void); -#endif -#if !defined(PORT_OPTIMIZED_ISRESCHREQUIREDEXI) - bool_t chSchIsRescRequiredExI(void); -#endif -#ifdef __cplusplus -} -#endif - -/** - * @brief Determines if the current thread must reschedule. - * @details This function returns @p TRUE if there is a ready thread with - * higher priority. - */ -#if !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) || defined(__DOXYGEN__) -#define chSchIsRescRequiredI() (firstprio(&rlist.r_queue) > currp->p_prio) -#endif /* !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) */ - -/** - * @brief Determines if yielding is possible. - * @details This function returns @p TRUE if there is a ready thread with - * equal or higher priority. - */ -#if !defined(PORT_OPTIMIZED_CANYIELDS) || defined(__DOXYGEN__) -#define chSchCanYieldS() (firstprio(&rlist.r_queue) >= currp->p_prio) -#endif /* !defined(PORT_OPTIMIZED_CANYIELDS) */ - -/** - * @brief Yields the time slot. - * @details Yields the CPU control to the next thread in the ready list with - * equal or higher priority, if any. - */ -#if !defined(PORT_OPTIMIZED_DOYIELDS) || defined(__DOXYGEN__) -#define chSchDoYieldS() { \ - if (chSchCanYieldS()) \ - chSchDoRescheduleI(); \ -} -#endif /* !defined(PORT_OPTIMIZED_DOYIELDS) */ - -#endif /* _CHSCHD_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chsem.h b/ChibiOS_2.0.8/os/kernel/include/chsem.h deleted file mode 100644 index 1bc8320..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chsem.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chsem.h - * @brief Semaphores macros and structures. - * - * @addtogroup semaphores - * @{ - */ - -#ifndef _CHSEM_H_ -#define _CHSEM_H_ - -#if CH_USE_SEMAPHORES - -/** - * @brief Semaphore structure. - */ -typedef struct Semaphore { - ThreadsQueue s_queue; /**< @brief Queue of the threads sleeping - on this semaphore. */ - cnt_t s_cnt; /**< @brief The semaphore counter. */ -} Semaphore; - -#ifdef __cplusplus -extern "C" { -#endif - void chSemInit(Semaphore *sp, cnt_t n); - void chSemReset(Semaphore *sp, cnt_t n); - void chSemResetI(Semaphore *sp, cnt_t n); - msg_t chSemWait(Semaphore *sp); - msg_t chSemWaitS(Semaphore *sp); - msg_t chSemWaitTimeout(Semaphore *sp, systime_t time); - msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time); - void chSemSignal(Semaphore *sp); - void chSemSignalI(Semaphore *sp); -#if CH_USE_SEMSW - msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw); -#endif -#ifdef __cplusplus -} -#endif - -/** - * @brief Data part of a static semaphore initializer. - * @details This macro should be used when statically initializing a semaphore - * that is part of a bigger structure. - * - * @param[in] name the name of the semaphore variable - * @param[in] n the counter initial value, this value must be - * non-negative - */ -#define _SEMAPHORE_DATA(name, n) {_THREADSQUEUE_DATA(name.s_queue), n} - -/** - * @brief Static semaphore initializer. - * @details Statically initialized semaphores require no explicit - * initialization using @p chSemInit(). - * - * @param[in] name the name of the semaphore variable - * @param[in] n the counter initial value, this value must be - * non-negative - */ -#define SEMAPHORE_DECL(name, n) Semaphore name = _SEMAPHORE_DATA(name, n) - -/** - * @brief Decreases the semaphore counter. - * @details This macro can be used when the counter is known to be positive. - */ -#define chSemFastWaitI(sp) ((sp)->s_cnt--) - -/** - * @brief Increases the semaphore counter. - * @details This macro can be used when the counter is known to be not negative. - */ -#define chSemFastSignalI(sp) ((sp)->s_cnt++) - -/** - * @brief Returns the semaphore counter current value. - */ -#define chSemGetCounterI(sp) ((sp)->s_cnt) - -#endif /* CH_USE_SEMAPHORES */ - -#endif /* _CHSEM_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chstreams.h b/ChibiOS_2.0.8/os/kernel/include/chstreams.h deleted file mode 100644 index a2d4c87..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chstreams.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chstreams.h - * @brief Data streams. - * @details This header defines abstract interfaces useful to access generic - * data streams in a standardized way. - * - * @addtogroup data_streams - * @details This module define an abstract interface for generic data streams. - * Note that no code is present, streams are just abstract interfaces - * like structures, you should look at the systems as to a set of - * abstract C++ classes (even if written in C). This system has the - * advantage to make the access to streams independent from the - * implementation logic.
- * The stream interface can be used as base class for high level - * object types such as files, sockets, serial ports, pipes etc. - * @{ - */ - -#ifndef _CHSTREAMS_H_ -#define _CHSTREAMS_H_ - -/** - * @brief BaseSequentialStream specific methods. - */ -#define _base_sequential_stream_methods \ - /* Stream write buffer method.*/ \ - size_t (*write)(void *instance, const uint8_t *bp, size_t n); \ - /* Stream read buffer method.*/ \ - size_t (*read)(void *instance, uint8_t *bp, size_t n); - -/** - * @brief @p BaseSequentialStream specific data. - * @note It is empty because @p BaseSequentialStream is only an interface - * without implementation. - */ -#define _base_sequential_stream_data - -/** - * @brief @p BaseSequentialStream virtual methods table. - */ -struct BaseSequentialStreamVMT { - _base_sequential_stream_methods -}; - -/** - * @brief Base stream class. - * @details This class represents a generic blocking unbuffered sequential - * data stream. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct BaseSequentialStreamVMT *vmt; - _base_sequential_stream_data -} BaseSequentialStream; - -/** - * @brief Sequential Stream write. - * @details The function writes data from a buffer to a stream. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if the - * stream reaches a physical end of file and cannot be - * extended. - */ -#define chSequentialStreamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n)) - -/** - * @brief Sequential Stream read. - * @details The function reads data from a stream into a buffer. - * - * @param[in] ip pointer to a @p BaseSequentialStream or derived class - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if the - * stream reaches the end of the available data. - */ -#define chSequentialStreamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n)) - -#endif /* _CHSTREAMS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chsys.h b/ChibiOS_2.0.8/os/kernel/include/chsys.h deleted file mode 100644 index 03fa0ed..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chsys.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chsys.h - * @brief System related macros and structures. - * - * @addtogroup system - * @{ - */ - -#ifndef _CHSYS_H_ -#define _CHSYS_H_ - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected, as example because a programming - * error in the application code that triggers an assertion while - * in debug mode. - */ -#define chSysHalt() port_halt() - -/** - * @brief Performs a context switch. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#define chSysSwitchI(ntp, otp) port_switch(ntp, otp) - -/** - * @brief Raises the system interrupt priority mask to the maximum level. - * @details All the maskable interrupt sources are disabled regardless their - * hardware priority. - * @note The implementation is architecture dependent, it may just disable - * the interrupts or be exactly equivalent to @p chSysDisable(). - * @note Do not invoke this API from within a kernel lock. - */ -#define chSysDisable() port_disable() - -/** - * @brief Raises the system interrupt priority mask to system level. - * @details The interrupt sources that should not be able to preempt the kernel - * are disabled, interrupt sources with higher priority are still - * enabled. - * @note The implementation is architecture dependent, it may just disable - * the interrupts. - * @note Do not invoke this API from within a kernel lock. - * @note This API is no replacement for @p chSysLock(), the @p chSysLock() - * could do more than just disable the interrupts. - */ -#define chSysSuspend() port_suspend() - -/** - * @brief Lowers the system interrupt priority mask to user level. - * @details All the interrupt sources are enabled. - * @note The implementation is architecture dependent, it may just enable - * the interrupts. - * @note Do not invoke this API from within a kernel lock. - * @note This API is no replacement for @p chSysUnlock(), the - * @p chSysUnlock() could do more than just enable the interrupts. - */ -#define chSysEnable() port_enable() - -/** - * @brief Enters the kernel lock mode. - * @note The use of kernel lock mode is not recommended in the user code, - * it is a better idea to use the semaphores or mutexes instead. - * @see CH_USE_NESTED_LOCKS - */ -#if CH_USE_NESTED_LOCKS || defined(__DOXYGEN__) -#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) -#define chSysLock() { \ - if (currp->p_locks++ == 0) \ - port_lock(); \ -} -#endif /* CH_OPTIMIZE_SPEED */ -#else /* !CH_USE_NESTED_LOCKS */ -#define chSysLock() port_lock() -#endif /* !CH_USE_NESTED_LOCKS */ - -/** - * @brief Leaves the kernel lock mode. - * @note The use of kernel lock mode is not recommended in the user code, - * it is a better idea to use the semaphores or mutexes instead. - * @see CH_USE_NESTED_LOCKS - */ -#if CH_USE_NESTED_LOCKS || defined(__DOXYGEN__) -#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) -#define chSysUnlock() { \ - if (--currp->p_locks == 0) \ - port_unlock(); \ -} -#endif /* CH_OPTIMIZE_SPEED */ -#else /* !CH_USE_NESTED_LOCKS */ -#define chSysUnlock() port_unlock() -#endif /* !CH_USE_NESTED_LOCKS */ - -/** - * @brief Enters the kernel lock mode from within an interrupt handler. - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API before invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - */ -#define chSysLockFromIsr() port_lock_from_isr() - -/** - * @brief Leaves the kernel lock mode from within an interrupt handler. - * - * @note This API may do nothing on some architectures, it is required - * because on ports that support preemptable interrupt handlers - * it is required to raise the interrupt mask to the same level of - * the system mutual exclusion zone.
- * It is good practice to invoke this API after invoking any I-class - * syscall from an interrupt handler. - * @note This API must be invoked exclusively from interrupt handlers. - */ -#define chSysUnlockFromIsr() port_unlock_from_isr() - -/** - * @brief IRQ handler enter code. - * @note Usually IRQ handlers functions are also declared naked. - * @note On some architectures this macro can be empty. - */ -#define CH_IRQ_PROLOGUE() PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ handler exit code. - * @note Usually IRQ handlers function are also declared naked. - * @note This macro usually performs the final reschedule by using - * @p chSchRescRequiredI() and @p chSchDoRescheduleI(). - */ -#define CH_IRQ_EPILOGUE() PORT_IRQ_EPILOGUE() - -/** - * @brief Standard normal IRQ handler declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id) - -/** - * @brief Standard fast IRQ handler declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - * @note Not all architectures support fast interrupts. - */ -#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id) - -#ifdef __cplusplus -extern "C" { -#endif - void chSysInit(void); - void chSysTimerHandlerI(void); -#if CH_USE_NESTED_LOCKS && !CH_OPTIMIZE_SPEED - void chSysLock(void); - void chSysUnlock(void); -#endif /* CH_USE_NESTED_LOCKS && !CH_OPTIMIZE_SPEED */ -#ifdef __cplusplus -} -#endif - -#endif /* _CHSYS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chthreads.h b/ChibiOS_2.0.8/os/kernel/include/chthreads.h deleted file mode 100644 index 1ac6f48..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chthreads.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chthreads.h - * @brief Threads macros and structures. - * - * @addtogroup threads - * @{ - */ - -#ifndef _CHTHREADS_H_ -#define _CHTHREADS_H_ - -/* - * Module dependencies check. - */ -#if CH_USE_DYNAMIC && !CH_USE_WAITEXIT -#error "CH_USE_DYNAMIC requires CH_USE_WAITEXIT" -#endif -#if CH_USE_DYNAMIC && !CH_USE_HEAP && !CH_USE_MEMPOOLS -#error "CH_USE_DYNAMIC requires CH_USE_HEAP and/or CH_USE_MEMPOOLS" -#endif - -/** - * @extends ThreadsQueue - * - * @brief Structure representing a thread. - * @note Not all the listed fields are always needed, by switching off some - * not needed ChibiOS/RT subsystems it is possible to save RAM space - * by shrinking the @p Thread structure. - */ -struct Thread { - Thread *p_next; /**< @brief Next in the list/queue. */ - /* End of the fields shared with the ThreadsList structure. */ - Thread *p_prev; /**< @brief Previous in the queue. */ - /* End of the fields shared with the ThreadsQueue structure. */ - tprio_t p_prio; /**< @brief Thread priority. */ - struct context p_ctx; /**< @brief Processor context. */ -#if CH_USE_REGISTRY - Thread *p_newer; /**< @brief Newer registry element. */ - Thread *p_older; /**< @brief Older registry element. */ -#endif - /* End of the fields shared with the ReadyList structure. */ - /** - * @brief Current thread state. - */ - tstate_t p_state; - /** - * @brief Various thread flags. - */ - tmode_t p_flags; -#if CH_USE_DYNAMIC - /** - * @brief References to this thread. - */ - trefs_t p_refs; -#endif -#if CH_USE_NESTED_LOCKS - /** - * @brief Number of nested locks. - */ - cnt_t p_locks; -#endif -#if CH_DBG_THREADS_PROFILING - /** - * @brief Thread consumed time in ticks. - * @note This field can overflow. - */ - volatile systime_t p_time; -#endif - /** - * @brief State-specific fields. - * @note All the fields declared in this union are only valid in the - * specified state or condition and are thus volatile. - */ - union { - /** - * @brief Thread wakeup code. - * @note This field contains the low level message sent to the thread - * by the waking thread or interrupt handler. The value is valid - * after exiting the @p chSchWakeupS() function. - */ - msg_t rdymsg; - /** - * @brief Thread exit code. - * @note The thread termination code is stored in this field in order - * to be retrieved by the thread performing a @p chThdWait() on - * this thread. - */ - msg_t exitcode; - /** - * @brief Pointer to a generic "wait" object. - * @note This field is used to get a generic pointer to a synchronization - * object and is valid when the thread is in one of the wait - * states. - */ - void *wtobjp; -#if CH_USE_EVENTS - /** - * @brief Enabled events mask. - * @note This field is only valied while the thread is in the - * @p THD_STATE_WTOREVT or @p THD_STATE_WTANDEVT states. - */ - eventmask_t ewmask; -#endif - } p_u; -#if CH_USE_WAITEXIT - /** - * @brief Termination waiting list. - */ - ThreadsList p_waiting; -#endif -#if CH_USE_MESSAGES - /** - * @brief Messages queue. - */ - ThreadsQueue p_msgqueue; - /** - * @brief Thread message. - */ - msg_t p_msg; -#endif -#if CH_USE_EVENTS - /** - * @brief Pending events mask. - */ - eventmask_t p_epending; -#endif -#if CH_USE_MUTEXES - /** - * @brief List of the mutexes owned by this thread. - * @note The list is terminated by a @p NULL in this field. - */ - Mutex *p_mtxlist; - /** - * @brief Thread's own, non-inherited, priority. - */ - tprio_t p_realprio; -#endif -#if CH_USE_DYNAMIC && CH_USE_MEMPOOLS - /** - * @brief Memory Pool where the thread workspace is returned. - */ - void *p_mpool; -#endif - /* Extra fields defined in chconf.h.*/ - THREAD_EXT_FIELDS -}; - -/** @brief Thread state: Ready to run, waiting on the ready list.*/ -#define THD_STATE_READY 0 -/** @brief Thread state: Currently running.*/ -#define THD_STATE_CURRENT 1 -/** @brief Thread state: Thread created in suspended state.*/ -#define THD_STATE_SUSPENDED 2 -/** @brief Thread state: Waiting on a semaphore.*/ -#define THD_STATE_WTSEM 3 -/** @brief Thread state: Waiting on a mutex.*/ -#define THD_STATE_WTMTX 4 -/** @brief Thread state: Waiting in @p chCondWait().*/ -#define THD_STATE_WTCOND 5 -/** @brief Thread state: Waiting in @p chThdSleep() or @p chThdSleepUntil().*/ -#define THD_STATE_SLEEPING 6 -/** @brief Thread state: Waiting in @p chThdWait().*/ -#define THD_STATE_WTEXIT 7 -/** @brief Thread state: Waiting in @p chEvtWaitXXX().*/ -#define THD_STATE_WTOREVT 8 -/** @brief Thread state: Waiting in @p chEvtWaitAllTimeout().*/ -#define THD_STATE_WTANDEVT 9 -/** @brief Thread state: Waiting in @p chMsgSend().*/ -#define THD_STATE_SNDMSG 10 -/** @brief Thread state: Waiting in @p chMsgWait().*/ -#define THD_STATE_WTMSG 11 -/** @brief Thread state: After termination.*/ -#define THD_STATE_FINAL 12 - -/* - * Various flags into the thread p_flags field. - */ -#define THD_MEM_MODE_MASK 3 /**< @brief Thread memory mode mask. */ -#define THD_MEM_MODE_STATIC 0 /**< @brief Thread memory mode: static. */ -#define THD_MEM_MODE_HEAP 1 /**< @brief Thread memory mode: heap. */ -#define THD_MEM_MODE_MEMPOOL 2 /**< @brief Thread memory mode: pool. */ -#define THD_TERMINATE 4 /**< @brief Termination requested. */ - -/** @brief Thread function.*/ -typedef msg_t (*tfunc_t)(void *); - -/* - * Threads APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - Thread *init_thread(Thread *tp, tprio_t prio); - Thread *chThdCreateI(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); - Thread *chThdCreateStatic(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); -#if CH_USE_DYNAMIC && CH_USE_WAITEXIT && CH_USE_HEAP - Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size, - tprio_t prio, tfunc_t pf, void *arg); -#endif -#if CH_USE_DYNAMIC && CH_USE_WAITEXIT && CH_USE_MEMPOOLS - Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio, - tfunc_t pf, void *arg); -#endif - tprio_t chThdSetPriority(tprio_t newprio); - Thread *chThdResume(Thread *tp); - void chThdTerminate(Thread *tp); - void chThdSleep(systime_t time); - void chThdSleepUntil(systime_t time); - void chThdYield(void); - void chThdExit(msg_t msg); -#if CH_USE_DYNAMIC - Thread *chThdAddRef(Thread *tp); - void chThdRelease(Thread *tp); -#endif -#if CH_USE_WAITEXIT - msg_t chThdWait(Thread *tp); -#endif -#ifdef __cplusplus -} -#endif - -/** - * @brief Returns a pointer to the current @p Thread. - */ -#define chThdSelf() currp - -/** - * @brief Returns the current thread priority. - */ -#define chThdGetPriority() (currp->p_prio) - -/** - * @brief Returns the pointer to the @p Thread local storage area, if any. - */ -#define chThdLS() (void *)(currp + 1) - -/** - * @brief Verifies if the specified thread is in the @p THD_STATE_FINAL state. - * - * @param[in] tp the pointer to the thread - * @retval TRUE thread terminated. - * @retval FALSE thread not terminated. - */ -#define chThdTerminated(tp) ((tp)->p_state == THD_STATE_FINAL) - -/** - * @brief Verifies if the current thread has a termination request pending. - * - * @retval TRUE termination request pended. - * @retval FALSE termination request not pended. - */ -#define chThdShouldTerminate() (currp->p_flags & THD_TERMINATE) - -/** - * @brief Resumes a thread created with @p chThdInit(). - * - * @param[in] tp the pointer to the thread - */ -#define chThdResumeI(tp) chSchReadyI(tp) - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE this value is accepted but - * interpreted as a normal time specification not as - * an immediate timeout specification. - * . - */ -#define chThdSleepS(time) chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time) - -/** - * @brief Delays the invoking thread for the specified number of seconds. - * @note The specified time is rounded up to a value allowed by the real - * system clock. - * @note The maximum specified value is implementation dependent. - * - * @param[in] sec the time in seconds - */ -#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec)) - -/** - * @brief Delays the invoking thread for the specified number of - * milliseconds. - * @note The specified time is rounded up to a value allowed by the real - * system clock. - * @note The maximum specified value is implementation dependent. - * - * @param[in] msec the time in milliseconds - */ -#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec)) - -/** - * @brief Delays the invoking thread for the specified number of - * microseconds. - * @note The specified time is rounded up to a value allowed by the real - * system clock. - * @note The maximum specified value is implementation dependent. - * - * @param[in] usec the time in microseconds - */ -#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec)) - -#endif /* _CHTHREADS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/include/chvt.h b/ChibiOS_2.0.8/os/kernel/include/chvt.h deleted file mode 100644 index d5ea133..0000000 --- a/ChibiOS_2.0.8/os/kernel/include/chvt.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chvt.h - * @brief Time macros and structures. - * - * @addtogroup time - * @{ - */ - -#ifndef _CHVT_H_ -#define _CHVT_H_ - -/** - * @brief Time conversion utility. - * @details Converts from seconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - */ -#define S2ST(sec) ((systime_t)((sec) * CH_FREQUENCY)) - -/** - * @brief Time conversion utility. - * @details Converts from milliseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - */ -#define MS2ST(msec) ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L)) - -/** - * @brief Time conversion utility. - * @details Converts from microseconds to system ticks number. - * @note The result is rounded upward to the next tick boundary. - */ -#define US2ST(usec) ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L)) - -/** - * @brief Virtual Timer callback function. - */ -typedef void (*vtfunc_t)(void *); - -/** - * @brief Virtual Timer structure type. - */ -typedef struct VirtualTimer VirtualTimer; - -/** - * @extends DeltaList - * - * @brief Virtual Timer descriptor structure. - */ -struct VirtualTimer { - VirtualTimer *vt_next; /**< @brief Next timer in the delta - list. */ - VirtualTimer *vt_prev; /**< @brief Previous timer in the delta - list. */ - systime_t vt_time; /**< @brief Time delta before timeout. */ - vtfunc_t vt_func; /**< @brief Timer callback function - pointer. */ - void *vt_par; /**< @brief Timer callback function - parameter. */ -}; - -/** - * @brief Virtual timers list header. - * @note The delta list is implemented as a double link bidirectional list - * in order to make the unlink time constant, the reset of a virtual - * timer is often used in the code. - */ -typedef struct { - VirtualTimer *vt_next; /**< @brief Next timer in the delta - list. */ - VirtualTimer *vt_prev; /**< @brief Last timer in the delta - list. */ - systime_t vt_time; /**< @brief Must be initialized to -1. */ - volatile systime_t vt_systime; /**< @brief System Time counter. */ -} VTList; - -extern VTList vtlist; - -/** - * @brief Virtual timers ticker. - */ -#define chVTDoTickI() { \ - vtlist.vt_systime++; \ - if (&vtlist != (VTList *)vtlist.vt_next) { \ - VirtualTimer *vtp; \ - \ - --vtlist.vt_next->vt_time; \ - while (!(vtp = vtlist.vt_next)->vt_time) { \ - vtfunc_t fn = vtp->vt_func; \ - vtp->vt_func = (vtfunc_t)NULL; \ - vtp->vt_next->vt_prev = (void *)&vtlist; \ - (&vtlist)->vt_next = vtp->vt_next; \ - fn(vtp->vt_par); \ - } \ - } \ -} - -/* - * Virtual Timers APIs. - */ -#ifdef __cplusplus -extern "C" { -#endif - void vt_init(void); - void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par); - void chVTResetI(VirtualTimer *vtp); - bool_t chTimeIsWithin(systime_t start, systime_t end); -#ifdef __cplusplus -} -#endif - -/** - * @brief Returns TRUE if the speciified timer is armed. - */ -#define chVTIsArmedI(vtp) ((vtp)->vt_func != NULL) - -/** - * @brief Current system time. - * @details Returns the number of system ticks since the @p chSysInit() - * invocation. - * @note The counter can reach its maximum and then restart from zero. - * @note This function is designed to work with the @p chThdSleepUntil(). - * - * @return The system time in ticks.r - */ -#define chTimeNow() (vtlist.vt_systime) - -#endif /* _CHVT_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/kernel.dox b/ChibiOS_2.0.8/os/kernel/kernel.dox deleted file mode 100644 index 2d351a4..0000000 --- a/ChibiOS_2.0.8/os/kernel/kernel.dox +++ /dev/null @@ -1,172 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup kernel Kernel - * @details The kernel is the portable part of ChibiOS/RT, this section - * documents the various kernel subsystems. - */ - -/** - * @defgroup kernel_info Version Numbers and Identification - * @ingroup kernel - */ - -/** - * @defgroup config Configuration - * @ingroup kernel - */ - -/** - * @defgroup types Types - * @ingroup kernel - */ - -/** - * @defgroup base Base Kernel Services - * @details Base kernel services, the base subsystems are always included in - * the OS builds. - * @ingroup kernel - */ - -/** - * @defgroup system System Management - * @ingroup base - */ - -/** - * @defgroup scheduler Scheduler - * @ingroup base - */ - -/** - * @defgroup threads Threads - * @ingroup base - */ - -/** - * @defgroup time Time and Virtual Timers - * @ingroup base - */ - -/** - * @defgroup synchronization Synchronization - * @details Synchronization services. - * @ingroup kernel - */ - -/** - * @defgroup semaphores Semaphores - * @ingroup synchronization - */ - -/** - * @defgroup mutexes Mutexes - * @ingroup synchronization - */ - -/** - * @defgroup condvars Condition Variables - * @ingroup synchronization - */ - -/** - * @defgroup events Event Flags - * @ingroup synchronization - */ - -/** - * @defgroup messages Synchronous Messages - * @ingroup synchronization - */ - -/** - * @defgroup mailboxes Mailboxes - * @ingroup synchronization - */ - -/** - * @defgroup memory Memory Management - * @details Memory Management services. - * @ingroup kernel - */ - -/** - * @defgroup memcore Core Memory Manager - * @ingroup memory - */ - -/** - * @defgroup heaps Heaps - * @ingroup memory - */ - -/** - * @defgroup pools Memory Pools - * @ingroup memory - */ - - /** - * @defgroup io_support I/O Support - * @details I/O related services. - * @ingroup kernel - */ - -/** - * @defgroup data_streams Data Streams - * @ingroup io_support - */ - -/** - * @defgroup io_channels I/O Channels - * @ingroup io_support - */ - -/** - * @defgroup io_queues I/O Queues - * @ingroup io_support - */ - -/** - * @defgroup registry Registry - * @ingroup kernel - */ - -/** - * @defgroup debug Debug - * @ingroup kernel - */ - -/** - * @defgroup core Port Templates - * @ingroup kernel - */ - -/** - * @defgroup internals Internals - * @ingroup kernel - */ - diff --git a/ChibiOS_2.0.8/os/kernel/kernel.mk b/ChibiOS_2.0.8/os/kernel/kernel.mk deleted file mode 100644 index 0cd1f94..0000000 --- a/ChibiOS_2.0.8/os/kernel/kernel.mk +++ /dev/null @@ -1,22 +0,0 @@ -# List of all the ChibiOS/RT kernel files, there is no need to remove the files -# from this list, you can disable parts of the kernel by editing chconf.h. -KERNSRC = ${CHIBIOS}/os/kernel/src/chsys.c \ - ${CHIBIOS}/os/kernel/src/chdebug.c \ - ${CHIBIOS}/os/kernel/src/chlists.c \ - ${CHIBIOS}/os/kernel/src/chvt.c \ - ${CHIBIOS}/os/kernel/src/chschd.c \ - ${CHIBIOS}/os/kernel/src/chthreads.c \ - ${CHIBIOS}/os/kernel/src/chregistry.c \ - ${CHIBIOS}/os/kernel/src/chsem.c \ - ${CHIBIOS}/os/kernel/src/chmtx.c \ - ${CHIBIOS}/os/kernel/src/chcond.c \ - ${CHIBIOS}/os/kernel/src/chevents.c \ - ${CHIBIOS}/os/kernel/src/chmsg.c \ - ${CHIBIOS}/os/kernel/src/chmboxes.c \ - ${CHIBIOS}/os/kernel/src/chqueues.c \ - ${CHIBIOS}/os/kernel/src/chmemcore.c \ - ${CHIBIOS}/os/kernel/src/chheap.c \ - ${CHIBIOS}/os/kernel/src/chmempools.c - -# Required include directories -KERNINC = ${CHIBIOS}/os/kernel/include diff --git a/ChibiOS_2.0.8/os/kernel/src/chcond.c b/ChibiOS_2.0.8/os/kernel/src/chcond.c deleted file mode 100644 index e1d32a3..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chcond.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* - Concepts and parts of this file have been contributed by Leon Woestenberg. - */ - -/** - * @file chcond.c - * @brief Condition Variables code. - * - * @addtogroup condvars Condition Variables - * @details This module implements the Condition Variables mechanism. Condition - * variables are an extensions to the Mutex subsystem and cannot - * work alone. - *

Operation mode

- * The condition variable is a synchronization object meant to be - * used inside a zone protected by a @p Mutex. Mutexes and CondVars - * together can implement a Monitor construct.
- * In order to use the Condition Variables APIs the @p CH_USE_CONDVARS - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_CONDVARS && CH_USE_MUTEXES - -/** - * @brief Initializes s @p CondVar structure. - * @note This function can be invoked from within an interrupt handler even - * if it is not an I-Class API because it does not touch any critical - * kernel data structure. - * - * @param[out] cp pointer to a @p CondVar structure - */ -void chCondInit(CondVar *cp) { - - chDbgCheck(cp != NULL, "chCondInit"); - - queue_init(&cp->c_queue); -} - -/** - * @brief Signals one thread that is waiting on the condition variable. - * - * @param[in] cp pointer to the @p CondVar structure - */ -void chCondSignal(CondVar *cp) { - - chDbgCheck(cp != NULL, "chCondSignal"); - - chSysLock(); - if (notempty(&cp->c_queue)) - chSchWakeupS(fifo_remove(&cp->c_queue), RDY_OK); - chSysUnlock(); -} - -/** - * @brief Signals one thread that is waiting on the condition variable. - * - * @param[in] cp pointer to the @p CondVar structure - */ -void chCondSignalI(CondVar *cp) { - - chDbgCheck(cp != NULL, "chCondSignalI"); - - if (notempty(&cp->c_queue)) - chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_OK; -} - -/** - * @brief Signals all threads that are waiting on the condition variable. - * - * @param[in] cp pointer to the @p CondVar structure - */ -void chCondBroadcast(CondVar *cp) { - - chSysLock(); - chCondBroadcastI(cp); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Signals all threads that are waiting on the condition variable. - * - * @param[in] cp pointer to the @p CondVar structure - */ -void chCondBroadcastI(CondVar *cp) { - - chDbgCheck(cp != NULL, "chCondBroadcastI"); - - /* Empties the condition variable queue and inserts all the Threads into the - ready list in FIFO order. The wakeup message is set to @p RDY_RESET in - order to make a chCondBroadcast() detectable from a chCondSignal().*/ - while (cp->c_queue.p_next != (void *)&cp->c_queue) - chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_RESET; -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @note The invoking thread must have at least one owned mutex on - * entry. - * - * @param[in] cp pointer to the @p CondVar structure - * @return The wakep mode. - * @retval RDY_OK if the condvar was signaled using @p chCondSignal(). - * @retval RDY_RESET if the condvar was signaled using @p chCondBroadcast(). - */ -msg_t chCondWait(CondVar *cp) { - msg_t msg; - - chSysLock(); - msg = chCondWaitS(cp); - chSysUnlock(); - return msg; -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @note The invoking thread must have at least one owned mutex on - * entry. - * - * @param[in] cp pointer to the @p CondVar structure - * @return The wakep mode. - * @retval RDY_OK if the condvar was signaled using @p chCondSignal(). - * @retval RDY_RESET if the condvar was signaled using @p chCondBroadcast(). - */ -msg_t chCondWaitS(CondVar *cp) { - Thread *ctp = currp; - Mutex *mp; - msg_t msg; - - chDbgCheck(cp != NULL, "chCondWaitS"); - chDbgAssert(ctp->p_mtxlist != NULL, - "chCondWaitS(), #1", - "not owning a mutex"); - - mp = chMtxUnlockS(); - ctp->p_u.wtobjp = cp; - prio_insert(ctp, &cp->c_queue); - chSchGoSleepS(THD_STATE_WTCOND); - msg = ctp->p_u.rdymsg; - chMtxLockS(mp); - return msg; -} - -#if CH_USE_CONDVARS_TIMEOUT -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @note The invoking thread must have at least one owned mutex on - * entry. - * @note Exiting the function because a timeout does not re-acquire the - * mutex, the mutex ownership is lost. - * - * @param[in] cp pointer to the @p CondVar structure - * @param[in] time the number of ticks before the operation timeouts, - * the special value @p TIME_INFINITE is allowed. - * It is not possible to specify zero @p TIME_IMMEDIATE - * as timeout specification because it would make no sense - * in this function. - * @return The wakep mode. - * @retval RDY_OK if the condvar was signaled using @p chCondSignal(). - * @retval RDY_RESET if the condvar was signaled using @p chCondBroadcast(). - * @retval RDY_TIMEOUT if the condvar was not signaled @p within the specified - * timeout. - */ -msg_t chCondWaitTimeout(CondVar *cp, systime_t time) { - msg_t msg; - - chSysLock(); - msg = chCondWaitTimeoutS(cp, time); - chSysUnlock(); - return msg; -} - -/** - * @brief Waits on the condition variable releasing the mutex lock. - * @details Releases the currently owned mutex, waits on the condition - * variable, and finally acquires the mutex again. All the sequence - * is performed atomically. - * @note The invoking thread must have at least one owned mutex on - * entry. - * @note Exiting the function because a timeout does not re-acquire the - * mutex, the mutex ownership is lost. - * - * @param[in] cp pointer to the @p CondVar structure - * @param[in] time the number of ticks before the operation timeouts, - * the special value @p TIME_INFINITE is allowed. - * It is not possible to specify zero @p TIME_IMMEDIATE - * as timeout specification because it would make no sense - * in this function. - * @return The wakep mode. - * @retval RDY_OK if the condvar was signaled using @p chCondSignal(). - * @retval RDY_RESET if the condvar was signaled using @p chCondBroadcast(). - * @retval RDY_TIMEOUT if the condvar was not signaled within the specified - * timeout. - */ -msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time) { - Mutex *mp; - msg_t msg; - - chDbgCheck(cp != NULL, "chCondWaitTimeoutS"); - chDbgAssert(currp->p_mtxlist != NULL, - "chCondWaitTimeoutS(), #1", - "not owning a mutex"); - - mp = chMtxUnlockS(); - currp->p_u.wtobjp = cp; - prio_insert(currp, &cp->c_queue); - msg = chSchGoSleepTimeoutS(THD_STATE_WTCOND, time); - if (msg != RDY_TIMEOUT) - chMtxLockS(mp); - return msg; -} -#endif /* CH_USE_CONDVARS_TIMEOUT */ - -#endif /* CH_USE_CONDVARS && CH_USE_MUTEXES */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chdebug.c b/ChibiOS_2.0.8/os/kernel/src/chdebug.c deleted file mode 100644 index 2416375..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chdebug.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chdebug.c - * @brief ChibiOS/RT Debug code. - * - * @addtogroup debug - * @details Debug APIs and services: - * - Trace buffer. - * - Parameters check. - * - Kernel assertions. - * . - * @{ - */ - -#include "ch.h" - -#if CH_DBG_ENABLE_TRACE -/** - * @brief Public trace buffer. - */ -TraceBuffer trace_buffer; - -/** - * @brief Trace circular buffer subsystem initialization. - */ -void trace_init(void) { - - trace_buffer.tb_size = TRACE_BUFFER_SIZE; - trace_buffer.tb_ptr = &trace_buffer.tb_buffer[0]; -} - -/** - * @brief Inserts in the circular debug trace buffer a context switch record. - * - * @param[in] otp the thread being switched out - */ -void chDbgTrace(Thread *otp) { - - trace_buffer.tb_ptr->cse_wtobjp = otp->p_u.wtobjp; - trace_buffer.tb_ptr->cse_time = chTimeNow(); - trace_buffer.tb_ptr->cse_state = otp->p_state; - trace_buffer.tb_ptr->cse_tid = (unsigned)currp >> 6; - if (++trace_buffer.tb_ptr >= &trace_buffer.tb_buffer[TRACE_BUFFER_SIZE]) - trace_buffer.tb_ptr = &trace_buffer.tb_buffer[0]; -} -#endif /* CH_DBG_ENABLE_TRACE */ - -#if CH_DBG_ENABLE_ASSERTS || CH_DBG_ENABLE_CHECKS || CH_DBG_ENABLE_STACK_CHECK -/** - * @brief Pointer to the panic message. - * @details This pointer is meant to be accessed through the debugger, it is - * written once and then the system is halted. This variable can be - * set to @p NULL if the halt is caused by a stack overflow. - */ -char *panic_msg; - -/** - * @brief Prints a panic message on the console and then halts the system. - * - * @param[in] msg the pointer to the panic message string - */ -void chDbgPanic(char *msg) { - - panic_msg = msg; - chSysHalt(); -} -#endif /* CH_DBG_ENABLE_ASSERTS || CH_DBG_ENABLE_CHECKS || CH_DBG_ENABLE_STACK_CHECK */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chevents.c b/ChibiOS_2.0.8/os/kernel/src/chevents.c deleted file mode 100644 index ff00366..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chevents.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chevents.c - * @brief Events code. - * - * @addtogroup events - * @details Event Flags, Event Sources and Event Listeners. - *

Operation mode

- * Each thread has a mask of pending event flags inside its @p Thread - * structure. - * Operations defined for event flags: - * - Wait, the invoking thread goes to sleep until a certain - * AND/OR combination of event flags becomes pending. - * - Clear, a mask of event flags is cleared from the pending - * events mask, the cleared event flags mask is returned (only the - * flags that were actually pending and then cleared). - * - Signal, an event mask is directly ORed to the mask of the - * signaled thread. - * - Broadcast, each thread registered on an Event Source is - * signaled with the event flags specified in its Event Listener. - * - Dispatch, an events mask is scanned and for each bit set - * to one an associated handler function is invoked. Bit masks are - * scanned from bit zero upward. - * . - * An Event Source is a special object that can be "broadcasted" by - * a thread or an interrupt service routine. Broadcasting an Event - * Source has the effect that all the threads registered on the - * Event Source will be signaled with an events mask.
- * An unlimited number of Event Sources can exists in a system and - * each thread can be listening on an unlimited number of - * them.

- * In order to use the Events APIs the @p CH_USE_EVENTS option must be - * enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_EVENTS -/** - * @brief Registers an Event Listener on an Event Source. - * @note Multiple Event Listeners can specify the same bits to be pended. - * - * @param[in] esp pointer to the @p EventSource structure - * @param[in] elp pointer to the @p EventListener structure - * @param[in] mask the mask of event flags to be pended to the thread when - * the event source is broadcasted - */ -void chEvtRegisterMask(EventSource *esp, EventListener *elp, eventmask_t mask) { - - chDbgCheck((esp != NULL) && (elp != NULL), "chEvtRegisterMask"); - - chSysLock(); - elp->el_next = esp->es_next; - esp->es_next = elp; - elp->el_listener = currp; - elp->el_mask = mask; - chSysUnlock(); -} - -/** - * @brief Unregisters an Event Listener from its Event Source. - * @note If the event listener is not registered on the specified event - * source then the function does nothing. - * @note For optimal performance it is better to perform the unregister - * operations in inverse order of the register operations (elements - * are found on top of the list). - * - * @param[in] esp pointer to the @p EventSource structure - * @param[in] elp pointer to the @p EventListener structure - */ -void chEvtUnregister(EventSource *esp, EventListener *elp) { - EventListener *p; - - chDbgCheck((esp != NULL) && (elp != NULL), "chEvtUnregister"); - - p = (EventListener *)esp; - chSysLock(); - while (p->el_next != (EventListener *)esp) { - if (p->el_next == elp) { - p->el_next = elp->el_next; - break; - } - p = p->el_next; - } - chSysUnlock(); -} - -/** - * @brief Clears the pending events specified in the mask. - * - * @param[in] mask the events to be cleared - * @return The pending events that were cleared. - */ -eventmask_t chEvtClear(eventmask_t mask) { - eventmask_t m; - - chSysLock(); - - m = currp->p_epending & mask; - currp->p_epending &= ~mask; - - chSysUnlock(); - return m; -} - -/** - * @brief Pends a set of event flags on the current thread, this is @b much - * faster than using @p chEvtBroadcast() or @p chEvtSignal(). - * - * @param[in] mask the events to be pended - * @return The current pending events mask. - */ -eventmask_t chEvtPend(eventmask_t mask) { - - chSysLock(); - - mask = (currp->p_epending |= mask); - - chSysUnlock(); - return mask; -} - -/** - * @brief Pends a set of event flags on the specified @p Thread. - * - * @param[in] tp the thread to be signaled - * @param[in] mask the event flags set to be pended - */ -void chEvtSignal(Thread *tp, eventmask_t mask) { - - chDbgCheck(tp != NULL, "chEvtSignal"); - - chSysLock(); - chEvtSignalI(tp, mask); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Pends a set of event flags on the specified @p Thread. - * - * @param[in] tp the thread to be signaled - * @param[in] mask the event flags set to be pended - */ -void chEvtSignalI(Thread *tp, eventmask_t mask) { - - chDbgCheck(tp != NULL, "chEvtSignalI"); - - tp->p_epending |= mask; - /* Test on the AND/OR conditions wait states.*/ - if (((tp->p_state == THD_STATE_WTOREVT) && - ((tp->p_epending & tp->p_u.ewmask) != 0)) || - ((tp->p_state == THD_STATE_WTANDEVT) && - ((tp->p_epending & tp->p_u.ewmask) == tp->p_u.ewmask))) - chSchReadyI(tp)->p_u.rdymsg = RDY_OK; -} - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * - * @param[in] esp pointer to the @p EventSource structure - */ -void chEvtBroadcast(EventSource *esp) { - - chSysLock(); - chEvtBroadcastI(esp); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Signals all the Event Listeners registered on the specified Event - * Source. - * - * @param[in] esp pointer to the @p EventSource structure - */ -void chEvtBroadcastI(EventSource *esp) { - EventListener *elp; - - chDbgCheck(esp != NULL, "chEvtBroadcastI"); - - elp = esp->es_next; - while (elp != (EventListener *)esp) { - chEvtSignalI(elp->el_listener, elp->el_mask); - elp = elp->el_next; - } -} - -/** - * @brief Invokes the event handlers associated to an event flags mask. - * - * @param[in] mask mask of the events to be dispatched - * @param[in] handlers an array of @p evhandler_t. The array must have size - * equal to the number of bits in eventmask_t. - */ -void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask) { - eventid_t eid; - - chDbgCheck(handlers != NULL, "chEvtDispatch"); - - eid = 0; - while (mask) { - if (mask & EVENT_MASK(eid)) { - chDbgAssert(handlers[eid] != NULL, - "chEvtDispatch(), #1", - "null handler"); - mask &= ~EVENT_MASK(eid); - handlers[eid](eid); - } - eid++; - } -} - -#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__) -/** - * @brief Waits for exactly one of the specified events. - * @details The function waits for one event among those specified in - * @p mask to become pending then the event is cleared and returned. - * @note One and only one event is served in the function, the one with the - * lowest event id. The function is meant to be invoked into a loop in - * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have - * an higher priority. - * - * @param[in] mask mask of the events that the function should wait for, - * @p ALL_EVENTS enables all the events - * @return The mask of the lowest id served and cleared event. - */ -eventmask_t chEvtWaitOne(eventmask_t mask) { - Thread *ctp = currp; - eventmask_t m; - - chSysLock(); - - if ((m = (ctp->p_epending & mask)) == 0) { - ctp->p_u.ewmask = mask; - chSchGoSleepS(THD_STATE_WTOREVT); - m = ctp->p_epending & mask; - } - m &= -m; - ctp->p_epending &= ~m; - - chSysUnlock(); - return m; -} - -/** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p mask to become pending then the events are cleared and returned. - * - * @param[in] mask mask of the events that the function should wait for, - * @p ALL_EVENTS enables all the events - * @return The mask of the served and cleared events. - */ -eventmask_t chEvtWaitAny(eventmask_t mask) { - Thread *ctp = currp; - eventmask_t m; - - chSysLock(); - - if ((m = (ctp->p_epending & mask)) == 0) { - ctp->p_u.ewmask = mask; - chSchGoSleepS(THD_STATE_WTOREVT); - m = ctp->p_epending & mask; - } - ctp->p_epending &= ~m; - - chSysUnlock(); - return m; -} - -/** - * @brief Waits for all the specified events. - * @details The function waits for all the events specified in @p mask to - * become pending then the events are cleared and returned. - * - * @param[in] mask mask of the event ids that the function should wait for - * @return The mask of the served and cleared events. - */ -eventmask_t chEvtWaitAll(eventmask_t mask) { - Thread *ctp = currp; - - chSysLock(); - - if ((ctp->p_epending & mask) != mask) { - ctp->p_u.ewmask = mask; - chSchGoSleepS(THD_STATE_WTANDEVT); - } - ctp->p_epending &= ~mask; - - chSysUnlock(); - return mask; -} -#endif /* CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT */ - -#if CH_USE_EVENTS_TIMEOUT -/** - * @brief Waits for exactly one of the specified events. - * @details The function waits for one event among those specified in - * @p mask to become pending then the event is cleared and returned. - * @note One and only one event is served in the function, the one with the - * lowest event id. The function is meant to be invoked into a loop in - * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have - * an higher priority. - * - * @param[in] mask mask of the events that the function should wait for, - * @p ALL_EVENTS enables all the events - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the lowest id served and cleared event. - * @retval 0 if the specified timeout expired. - */ -eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time) { - Thread *ctp = currp; - eventmask_t m; - - chSysLock(); - - if ((m = (ctp->p_epending & mask)) == 0) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = mask; - if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - m = ctp->p_epending & mask; - } - m &= -m; - ctp->p_epending &= ~m; - - chSysUnlock(); - return m; -} - -/** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p mask to become pending then the events are cleared and - * returned. - * - * @param[in] mask mask of the events that the function should wait for, - * @p ALL_EVENTS enables all the events - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the served and cleared events. - * @retval 0 if the specified timeout expired. - */ -eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time) { - Thread *ctp = currp; - eventmask_t m; - - chSysLock(); - - if ((m = (ctp->p_epending & mask)) == 0) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = mask; - if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - m = ctp->p_epending & mask; - } - ctp->p_epending &= ~m; - - chSysUnlock(); - return m; -} - -/** - * @brief Waits for all the specified events. - * @details The function waits for all the events specified in @p mask to - * become pending then the events are cleared and returned. - * - * @param[in] mask mask of the event ids that the function should wait for - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The mask of the served and cleared events. - * @retval 0 if the specified timeout expired. - */ -eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time) { - Thread *ctp = currp; - - chSysLock(); - - if ((ctp->p_epending & mask) != mask) { - if (TIME_IMMEDIATE == time) { - chSysUnlock(); - return (eventmask_t)0; - } - ctp->p_u.ewmask = mask; - if (chSchGoSleepTimeoutS(THD_STATE_WTANDEVT, time) < RDY_OK) { - chSysUnlock(); - return (eventmask_t)0; - } - } - ctp->p_epending &= ~mask; - - chSysUnlock(); - return mask; -} -#endif /* CH_USE_EVENTS_TIMEOUT */ - -#endif /* CH_USE_EVENTS */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chheap.c b/ChibiOS_2.0.8/os/kernel/src/chheap.c deleted file mode 100644 index be0fc60..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chheap.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chheap.c - * @brief Heaps code. - * - * @addtogroup heaps - * @details Heap Allocator related APIs. - *

Operation mode

- * The heap allocator implements a first-fit strategy and its APIs - * are functionally equivalent to the usual @p malloc() and @p free() - * library functions. The main difference is that the OS heap APIs - * are guaranteed to be thread safe.
- * By enabling the @p CH_USE_MALLOC_HEAP option the heap manager - * will use the runtime-provided @p malloc() and @p free() as - * backend for the heap APIs instead of the system provided - * allocator.
- * In order to use the heap APIs the @p CH_USE_HEAP option must - * be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_HEAP - -#if !CH_USE_MALLOC_HEAP - -/* - * Defaults on the best synchronization mechanism available. - */ -#if CH_USE_MUTEXES -#define H_LOCK(h) chMtxLock(&(h)->h_mtx) -#define H_UNLOCK(h) chMtxUnlock() -#else -#define H_LOCK(h) chSemWait(&(h)->h_sem) -#define H_UNLOCK(h) chSemSignal(&(h)->h_sem) -#endif - -/** - * @brief Default heap descriptor. - */ -static MemoryHeap default_heap; - -/** - * @brief Initializes the default heap. - * @note Internal use only. - */ -void heap_init(void) { - default_heap.h_provider = chCoreAlloc; - default_heap.h_free.h.u.next = (union heap_header *)NULL; - default_heap.h_free.h.size = 0; -#if CH_USE_MUTEXES - chMtxInit(&default_heap.h_mtx); -#else - chSemInit(&default_heap.h_sem, 1); -#endif -} - -/** - * @brief Initializes a memory heap from a static memory area. - * @note Both the heap buffer base and the heap size must be aligned to - * the @p align_t type size. - * - * @param[out] heapp pointer to the memory heap descriptor to be initialized - * @param[in] buf heap buffer base - * @param[in] size heap size - */ -void chHeapInit(MemoryHeap *heapp, void *buf, size_t size) { - union heap_header *hp; - - chDbgCheck(MEM_IS_ALIGNED(buf) && MEM_IS_ALIGNED(size), "chHeapInit"); - - heapp->h_provider = (memgetfunc_t)NULL; - heapp->h_free.h.u.next = hp = buf; - heapp->h_free.h.size = 0; - hp->h.u.next = NULL; - hp->h.size = size - sizeof(union heap_header); -#if CH_USE_MUTEXES - chMtxInit(&heapp->h_mtx); -#else - chSemInit(&heapp->h_sem, 1); -#endif -} - -/** - * @brief Allocates a block of memory from the heap by using the first-fit - * algorithm. - * @details The allocated block is guaranteed to be properly aligned for a - * pointer data type (@p align_t). - * - * @param[in] heapp pointer to a heap descriptor or @p NULL in order to - * access the default heap. - * @param[in] size the size of the block to be allocated. Note that the - * allocated block may be a bit bigger than the requested - * size for alignment and fragmentation reasons. - * @return A pointer to the allocated block. - * @retval NULL if the block cannot be allocated. - */ -void *chHeapAlloc(MemoryHeap *heapp, size_t size) { - union heap_header *qp, *hp, *fp; - - if (heapp == NULL) - heapp = &default_heap; - - size = MEM_ALIGN_SIZE(size); - qp = &heapp->h_free; - H_LOCK(heapp); - - while (qp->h.u.next != NULL) { - hp = qp->h.u.next; - if (hp->h.size >= size) { - if (hp->h.size < size + sizeof(union heap_header)) { - /* Gets the whole block even if it is slightly bigger than the - requested size because the fragment would be too small to be - useful.*/ - qp->h.u.next = hp->h.u.next; - } - else { - /* Block bigger enough, must split it.*/ - fp = (void *)((uint8_t *)(hp) + sizeof(union heap_header) + size); - fp->h.u.next = hp->h.u.next; - fp->h.size = hp->h.size - sizeof(union heap_header) - size; - qp->h.u.next = fp; - hp->h.size = size; - } - hp->h.u.heap = heapp; - - H_UNLOCK(heapp); - return (void *)(hp + 1); - } - qp = hp; - } - - H_UNLOCK(heapp); - - /* More memory is required, tries to get it from the associated provider - else fails.*/ - if (heapp->h_provider) { - hp = heapp->h_provider(size + sizeof(union heap_header)); - if (hp != NULL) { - hp->h.u.heap = heapp; - hp->h.size = size; - hp++; - return (void *)hp; - } - } - return NULL; -} - -#define LIMIT(p) (union heap_header *)((uint8_t *)(p) + \ - sizeof(union heap_header) + \ - (p)->h.size) - -/** - * @brief Frees a previously allocated memory block. - * - * @param[in] p pointer to the memory block to be freed - */ -void chHeapFree(void *p) { - union heap_header *qp, *hp; - MemoryHeap *heapp; - - chDbgCheck(p != NULL, "chHeapFree"); - - hp = (union heap_header *)p - 1; - heapp = hp->h.u.heap; - qp = &heapp->h_free; - H_LOCK(heapp); - - while (TRUE) { - chDbgAssert((hp < qp) || (hp >= LIMIT(qp)), - "chHeapFree(), #1", - "within free block"); - - if (((qp == &heapp->h_free) || (hp > qp)) && - ((qp->h.u.next == NULL) || (hp < qp->h.u.next))) { - /* Insertion after qp.*/ - hp->h.u.next = qp->h.u.next; - qp->h.u.next = hp; - /* Verifies if the newly inserted block should be merged.*/ - if (LIMIT(hp) == hp->h.u.next) { - /* Merge with the next block.*/ - hp->h.size += hp->h.u.next->h.size + sizeof(union heap_header); - hp->h.u.next = hp->h.u.next->h.u.next; - } - if ((LIMIT(qp) == hp)) { - /* Merge with the previous block.*/ - qp->h.size += hp->h.size + sizeof(union heap_header); - qp->h.u.next = hp->h.u.next; - } - break; - } - qp = qp->h.u.next; - } - - H_UNLOCK(heapp); - return; -} - -/** - * @brief Reports the heap status. - * @note This function is meant to be used in the test suite, it should - * not be really useful for the application code. - * @note This function is not implemented when the @p CH_USE_MALLOC_HEAP - * configuration option is used (it always returns zero). - * - * @param[in] heapp pointer to a heap descriptor or @p NULL in order to - * access the default heap. - * @param[in] sizep pointer to a variable that will receive the total - * fragmented free space - * @return The number of fragments in the heap. - */ -size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { - union heap_header *qp; - size_t n, sz; - - if (heapp == NULL) - heapp = &default_heap; - - H_LOCK(heapp); - - sz = 0; - for (n = 0, qp = &heapp->h_free; qp->h.u.next; n++, qp = qp->h.u.next) - sz += qp->h.u.next->h.size; - if (sizep) - *sizep = sz; - - H_UNLOCK(heapp); - return n; -} - -#else /* CH_USE_MALLOC_HEAP */ - -#include - -#if CH_USE_MUTEXES -#define H_LOCK() chMtxLock(&hmtx) -#define H_UNLOCK() chMtxUnlock() -static Mutex hmtx; -#elif CH_USE_SEMAPHORES -#define H_LOCK() chSemWait(&hsem) -#define H_UNLOCK() chSemSignal(&hsem) -static Semaphore hsem; -#endif - -void heap_init(void) { - -#if CH_USE_MUTEXES - chMtxInit(&hmtx); -#else - chSemInit(&hsem, 1); -#endif -} - -void *chHeapAlloc(MemoryHeap *heapp, size_t size) { - void *p; - - chDbgCheck(heapp == NULL, "chHeapAlloc"); - - H_LOCK(); - p = malloc(size); - H_UNLOCK(); - return p; -} - -void chHeapFree(void *p) { - - chDbgCheck(p != NULL, "chHeapFree"); - - H_LOCK(); - free(p); - H_UNLOCK(); -} - -size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { - - chDbgCheck(heapp == NULL, "chHeapStatus"); - - if (sizep) - *sizep = 0; - return 0; -} - -#endif /* CH_USE_MALLOC_HEAP */ - -#endif /* CH_USE_HEAP */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chlists.c b/ChibiOS_2.0.8/os/kernel/src/chlists.c deleted file mode 100644 index 5927106..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chlists.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chlists.c - * @brief Thread queues/lists code. - * - * @addtogroup internals - * @details All the functions present in this module, while public, are not - * an OS API and should not be directly used in the user applications - * code. - * @{ - */ -#include "ch.h" - -#if !CH_OPTIMIZE_SPEED || defined(__DOXYGEN__) -/** - * @brief Inserts a thread into a priority ordered queue. - * @note The insertion is done by scanning the list from the highest priority - * toward the lowest. - * @note This function is @b not an API. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tqp the pointer to the threads list header - */ -void prio_insert(Thread *tp, ThreadsQueue *tqp) { - - /* cp iterates over the queue.*/ - Thread *cp = (Thread *)tqp; - do { - /* Iterate to next thread in queue.*/ - cp = cp->p_next; - /* Not end of queue? and cp has equal or higher priority than tp?.*/ - } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio)); - /* Insertion on p_prev.*/ - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = cp->p_prev = tp; -} - -/** - * @brief Inserts a Thread into a queue. - * @note This function is @b not an API. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tqp the pointer to the threads list header - */ -void queue_insert(Thread *tp, ThreadsQueue *tqp) { - - tp->p_next = (Thread *)tqp; - tp->p_prev = tqp->p_prev; - tp->p_prev->p_next = tqp->p_prev = tp; -} - -/** - * @brief Removes the first-out Thread from a queue and returns it. - * @note If the queue is priority ordered then this function returns the - * thread with the highest priority. - * @note This function is @b not an API. - * - * @param[in] tqp the pointer to the threads list header - * @return The removed thread pointer. - */ -Thread *fifo_remove(ThreadsQueue *tqp) { - Thread *tp = tqp->p_next; - - (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp; - return tp; -} - -/** - * @brief Removes the last-out Thread from a queue and returns it. - * @note If the queue is priority ordered then this function returns the - * thread with the lowest priority. - * @note This function is @b not an API. - * - * @param[in] tqp the pointer to the threads list header - * @return The removed thread pointer. - */ -Thread *lifo_remove(ThreadsQueue *tqp) { - Thread *tp = tqp->p_prev; - - (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp; - return tp; -} - -/** - * @brief Removes a Thread from a queue and returns it. - * @details The thread is removed from the queue regardless of its relative - * position and regardless the used insertion method. - * @note This function is @b not an API. - * - * @param[in] tp the pointer to the thread to be removed from the queue - * @return The removed thread pointer. - */ -Thread *dequeue(Thread *tp) { - - tp->p_prev->p_next = tp->p_next; - tp->p_next->p_prev = tp->p_prev; - return tp; -} - -/** - * @brief Pushes a Thread on top of a stack list. - * @note This function is @b not an API. - * - * @param[in] tp the pointer to the thread to be inserted in the list - * @param[in] tlp the pointer to the threads list header - */ -void list_insert(Thread *tp, ThreadsList *tlp) { - - tp->p_next = tlp->p_next; - tlp->p_next = tp; -} - -/** - * @brief Pops a Thread from the top of a stack list and returns it. - * @note The list must be non-empty before calling this function. - * @note This function is @b not an API. - * - * @param[in] tlp the pointer to the threads list header - * @return The removed thread pointer. - */ -Thread *list_remove(ThreadsList *tlp) { - - Thread *tp = tlp->p_next; - tlp->p_next = tp->p_next; - return tp; -} -#endif /* CH_OPTIMIZE_SPEED */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chmboxes.c b/ChibiOS_2.0.8/os/kernel/src/chmboxes.c deleted file mode 100644 index 7b6e5ee..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chmboxes.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmboxes.c - * @brief Mailboxes code. - * - * @addtogroup mailboxes - * @details Asynchronous messages. - *

Operation mode

- * A mailbox is an asynchronous communication mechanism.
- * Operations defined for mailboxes: - * - Post: Posts a message on the mailbox in FIFO order. - * - Post Ahead: Posts a message on the mailbox with urgent - * priority. - * - Fetch: A message is fetched from the mailbox and removed - * from the queue. - * - Reset: The mailbox is emptied and all the stored messages - * are lost. - * . - * A message is a variable of type msg_t that is guaranteed to have - * the same size of and be compatible with (data) pointers (anyway an - * explicit cast is needed). - * If larger messages need to be exchanged then a pointer to a - * structure can be posted in the mailbox but the posting side has - * no predefined way to know when the message has been processed. A - * possible approach is to allocate memory (from a memory pool as - * example) from the posting side and free it on the fetching side. - * Another approach is to set a "done" flag into the structure pointed - * by the message.
- * In order to use the mailboxes APIs the @p CH_USE_MAILBOXES option - * must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MAILBOXES -/** - * @brief Initializes a Mailbox object. - * - * @param[out] mbp the pointer to the Mailbox structure to be initialized - * @param[in] buf the circular messages buffer - * @param[in] n the buffer size as number of @p msg_t - */ -void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n) { - - chDbgCheck((mbp != NULL) && (buf != NULL) && (n > 0), "chMBInit"); - - mbp->mb_buffer = mbp->mb_wrptr = mbp->mb_rdptr = buf; - mbp->mb_top = &buf[n]; - chSemInit(&mbp->mb_emptysem, n); - chSemInit(&mbp->mb_fullsem, 0); -} - -/** - * @brief Resets a Mailbox object. - * @details All the waiting threads are resumed with status @p RDY_RESET and - * the queued messages are lost. - * - * @param[in] mbp the pointer to an initialized Mailbox object - */ -void chMBReset(Mailbox *mbp) { - - chDbgCheck(mbp != NULL, "chMBReset"); - - chSysLock(); - mbp->mb_wrptr = mbp->mb_rdptr = mbp->mb_buffer; - chSemResetI(&mbp->mb_emptysem, mbp->mb_top - mbp->mb_buffer); - chSemResetI(&mbp->mb_fullsem, 0); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the message was correctly posted. - * @retval RDY_RESET if the mailbox was reset while waiting. - * @retval RDY_TIMEOUT if the operation timed out. - */ -msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t time) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBPostS(mbp, msg, time); - chSysUnlock(); - return rdymsg; -} - -/** - * @brief Posts a message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the message was correctly posted. - * @retval RDY_RESET if the mailbox was reset while waiting. - * @retval RDY_TIMEOUT if the operation timed out. - */ -msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t time) { - msg_t rdymsg; - - chDbgCheck(mbp != NULL, "chMBPostS"); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time); - if (rdymsg == RDY_OK) { - *mbp->mb_wrptr++ = msg; - if (mbp->mb_wrptr >= mbp->mb_top) - mbp->mb_wrptr = mbp->mb_buffer; - chSemSignalI(&mbp->mb_fullsem); - chSchRescheduleS(); - } - return rdymsg; -} - -/** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the message was correctly posted. - * @retval RDY_RESET if the mailbox was reset while waiting. - * @retval RDY_TIMEOUT if the operation timed out. - */ -msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t time) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBPostAheadS(mbp, msg, time); - chSysUnlock(); - return rdymsg; -} - -/** - * @brief Posts an high priority message into a mailbox. - * @details The invoking thread waits until a empty slot in the mailbox becomes - * available or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[in] msg the message to be posted on the mailbox - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the message was correctly posted. - * @retval RDY_RESET if the mailbox was reset while waiting. - * @retval RDY_TIMEOUT if the operation timed out. - */ -msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t time) { - msg_t rdymsg; - - chDbgCheck(mbp != NULL, "chMBPostAheadS"); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time); - if (rdymsg == RDY_OK) { - if (--mbp->mb_rdptr < mbp->mb_buffer) - mbp->mb_rdptr = mbp->mb_top - 1; - *mbp->mb_rdptr = msg; - chSemSignalI(&mbp->mb_fullsem); - chSchRescheduleS(); - } - return rdymsg; -} - -/** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the mailbox - * or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[out] msgp pointer to a message variable for the received message - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message was correctly fetched. - * @retval RDY_RESET if the mailbox was reset while waiting. - * @retval RDY_TIMEOUT if the operation timed out. - */ -msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t time) { - msg_t rdymsg; - - chSysLock(); - rdymsg = chMBFetchS(mbp, msgp, time); - chSysUnlock(); - return rdymsg; -} - -/** - * @brief Retrieves a message from a mailbox. - * @details The invoking thread waits until a message is posted in the mailbox - * or the specified time runs out. - * - * @param[in] mbp the pointer to an initialized Mailbox object - * @param[out] msgp pointer to a message variable for the received message - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if a message was correctly fetched. - * @retval RDY_RESET if the mailbox was reset while waiting. - * @retval RDY_TIMEOUT if the operation timed out. - */ -msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t time) { - msg_t rdymsg; - - chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchS"); - - rdymsg = chSemWaitTimeoutS(&mbp->mb_fullsem, time); - if (rdymsg == RDY_OK) { - *msgp = *mbp->mb_rdptr++; - if (mbp->mb_rdptr >= mbp->mb_top) - mbp->mb_rdptr = mbp->mb_buffer; - chSemSignalI(&mbp->mb_emptysem); - chSchRescheduleS(); - } - return rdymsg; -} -#endif /* CH_USE_MAILBOXES */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chmemcore.c b/ChibiOS_2.0.8/os/kernel/src/chmemcore.c deleted file mode 100644 index 6797df8..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chmemcore.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmemcore.c - * @brief Core memory manager code. - * - * @addtogroup memcore - * @details Core Memory Manager related APIs and services. - *

Operation mode

- * The core memory manager is a simplified allocator that only allows - * to allocate memory blocks without the possibility to free them.
- * This allocator is meant as a memory blocks provider for the other - * allocators such as: - * - C-Runtime allocator (through a compiler specific adapter module). - * - Heap allocator (see @ref heaps). - * - Memory pools allocator (see @ref pools). - * . - * By having a centralized memory provider the various allocators can - * coexist and share the main memory.
- * This allocator, alone, is also useful for very simple applications - * that just require a simple way to get memory blocks.
- * In order to use the core memory manager APIs the @p CH_USE_MEMCORE - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MEMCORE - -static uint8_t *nextmem; -static uint8_t *endmem; - -/** - * @brief Low level memory manager initialization. - * @note Internal use only. - */ -void core_init(void) { -#if CH_MEMCORE_SIZE == 0 - extern uint8_t __heap_base__; - extern uint8_t __heap_end__; - nextmem = &__heap_base__; - endmem = &__heap_end__; -#else - static stkalign_t buffer[MEM_ALIGN_SIZE(CH_MEMCORE_SIZE) / - sizeof(stkalign_t)]; - nextmem = (uint8_t *)&buffer[0]; - endmem = (uint8_t *)&buffer[MEM_ALIGN_SIZE(CH_MEMCORE_SIZE) / - sizeof(stkalign_t)]; -#endif -} - -/** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type @p stkalign_t so it is not possible to allocate less - * than sizeof(stkalign_t). - * - * - * @param[in] size the size of the block to be allocated - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - */ -void *chCoreAlloc(size_t size) { - void *p; - - chSysLock(); - p = chCoreAllocI(size); - chSysUnlock(); - return p; -} - -/** - * @brief Allocates a memory block. - * @details The size of the returned block is aligned to the alignment - * type @p align_t so it is not possible to allocate less than - * sizeof(align_t). - * - * @param[in] size the size of the block to be allocated. - * @return A pointer to the allocated memory block. - * @retval NULL allocation failed, core memory exhausted. - */ -void *chCoreAllocI(size_t size) { - void *p; - - size = MEM_ALIGN_SIZE(size); - if ((size_t)(endmem - nextmem) < size) - return NULL; - p = nextmem; - nextmem += size; - return p; -} - -/** - * @brief Core memory status. - * - * @return The size, in bytes, of the free core memory. - */ -size_t chCoreStatus(void) { - - return (size_t)(endmem - nextmem); -} -#endif /* CH_USE_MEMCORE */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chmempools.c b/ChibiOS_2.0.8/os/kernel/src/chmempools.c deleted file mode 100644 index 3d9896f..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chmempools.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmempools.c - * @brief Memory Pools code. - * - * @addtogroup pools - * @details Memory Pools related APIs and services. - *

Operation mode

- * The Memory Pools APIs allow to allocate/free fixed size objects in - * constant time and reliably without memory fragmentation - * problems.
- * In order to use the memory pools APIs the @p CH_USE_MEMPOOLS option - * must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MEMPOOLS -/** - * @brief Initializes an empty memory pool. - * @note The size is internally aligned to be a multiple of the @p align_t - * type size. - * - * @param[out] mp pointer to a @p MemoryPool structure - * @param[in] size the size of the objects contained in this memory pool, - * the minimum accepted size is the size of a pointer to - * void. - * @param[in] provider memory provider function for the memory pool or - * @p NULL if the pool is not allowed to grow - * automatically - */ -void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider) { - - chDbgCheck((mp != NULL) && (size >= sizeof(void *)), "chPoolInit"); - - mp->mp_next = NULL; - mp->mp_object_size = MEM_ALIGN_SIZE(size); - mp->mp_provider = provider; -} - -/** - * @brief Allocates an object from a memory pool. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - */ -void *chPoolAllocI(MemoryPool *mp) { - void *objp; - - chDbgCheck(mp != NULL, "chPoolAllocI"); - - if ((objp = mp->mp_next) != NULL) - mp->mp_next = mp->mp_next->ph_next; -#if CH_USE_MEMCORE - else if (mp->mp_provider != NULL) - objp = mp->mp_provider(mp->mp_object_size); -#endif - return objp; -} - -/** - * @brief Allocates an object from a memory pool. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @return The pointer to the allocated object. - * @retval NULL if pool is empty. - */ -void *chPoolAlloc(MemoryPool *mp) { - void *objp; - - chSysLock(); - objp = chPoolAllocI(mp); - chSysUnlock(); - return objp; -} - -/** - * @brief Releases (or adds) an object into (to) a memory pool. - * @note The object is assumed to be of the right size for the specified - * memory pool. - * @note The object is assumed to be memory aligned to the size of @p align_t - * type. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @param[in] objp the pointer to the object to be released or added - */ -void chPoolFreeI(MemoryPool *mp, void *objp) { - struct pool_header *php = objp; - - chDbgCheck((mp != NULL) && (objp != NULL) && MEM_IS_ALIGNED(objp), - "chPoolFreeI"); - - php->ph_next = mp->mp_next; - mp->mp_next = php; -} - -/** - * @brief Releases (or adds) an object into (to) a memory pool. - * @note The object is assumed to be of the right size for the specified - * memory pool. - * - * @param[in] mp pointer to a @p MemoryPool structure - * @param[in] objp the pointer to the object to be released or added - */ -void chPoolFree(MemoryPool *mp, void *objp) { - - chSysLock(); - chPoolFreeI(mp, objp); - chSysUnlock(); -} -#endif /* CH_USE_MEMPOOLS */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chmsg.c b/ChibiOS_2.0.8/os/kernel/src/chmsg.c deleted file mode 100644 index 45f1e8d..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chmsg.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmsg.c - * @brief Messages code. - * - * @addtogroup messages - * @details Synchronous inter-thread messages APIs and services. - *

Operation Mode

- * Synchronous messages are an easy to use and fast IPC mechanism, - * threads can both act as message servers and/or message clients, - * the mechanism allows data to be carried in both directions. Note - * that messages are not copied between the client and server threads - * but just a pointer passed so the exchange is very time - * efficient.
- * Messages are usually processed in FIFO order but it is possible to - * process them in priority order by enabling the - * @p CH_USE_MESSAGES_PRIORITY option in @p chconf.h.
- * Applications do not need to allocate buffers for synchronous - * message queues, the mechanism just requires two extra pointers in - * the @p Thread structure (the message queue header).
- * In order to use the Messages APIs the @p CH_USE_MESSAGES option - * must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MESSAGES - -#if CH_USE_MESSAGES_PRIORITY -#define msg_insert(tp, qp) prio_insert(tp, qp) -#else -#define msg_insert(tp, qp) queue_insert(tp, qp) -#endif - -/** - * @brief Sends a message to the specified thread. - * @details The sender is stopped until the receiver executes a - * @p chMsgRelease()after receiving the message. - * - * @param[in] tp the pointer to the thread - * @param[in] msg the message - * @return The answer message from @p chMsgRelease(). - */ -msg_t chMsgSend(Thread *tp, msg_t msg) { - Thread *ctp = currp; - - chDbgCheck(tp != NULL, "chMsgSend"); - - chSysLock(); - ctp->p_msg = msg; - ctp->p_u.wtobjp = &tp->p_msgqueue; - msg_insert(ctp, &tp->p_msgqueue); - if (tp->p_state == THD_STATE_WTMSG) - chSchReadyI(tp); - chSchGoSleepS(THD_STATE_SNDMSG); - msg = ctp->p_u.rdymsg; - chSysUnlock(); - return msg; -} - -/** - * @brief Suspends the thread and waits for an incoming message. - * @note You can assume that the data contained in the message is stable - * until you invoke @p chMsgRelease() because the sending thread is - * suspended until then. - * - * @return The pointer to the message structure. Note, it is - * always the message associated to the thread on the - * top of the messages queue. - */ -msg_t chMsgWait(void) { - msg_t msg; - - chSysLock(); - if (!chMsgIsPendingI(currp)) - chSchGoSleepS(THD_STATE_WTMSG); -#if defined(CH_ARCHITECTURE_STM8) - msg = chMsgGetI((volatile Thread *)currp); /* Temporary hack.*/ -#else - msg = chMsgGetI(currp); -#endif - chSysUnlock(); - return msg; -} - -/** - * @brief Returns the next message in the queue. - * @note You can assume that the data pointed by the message is stable until - * you invoke @p chMsgRelease() because the sending thread is - * suspended until then. Always remember that the message data is not - * copied between the sender and the receiver, just a pointer is - * passed. - * - * @return The pointer to the message structure. Note, it is - * always the message associated to the thread on the - * top of the messages queue. - * @retval NULL if the queue is empty. - */ -msg_t chMsgGet(void) { - msg_t msg; - - chSysLock(); - msg = chMsgIsPendingI(currp) ? chMsgGetI(currp) : (msg_t)NULL; - chSysUnlock(); - return msg; -} - -/** - * @brief Releases the thread waiting on top of the messages queue. - * @note You can call this function only if there is a message already in - * the queue else the result will be unpredictable (a crash most likely). - * Exiting from the @p chMsgWait() ensures you have at least one - * message in the queue so it is not a big deal.
- * The condition is only tested in debug mode in order to make this - * code as fast as possible. - * - * @param[in] msg the message returned to the message sender - */ -void chMsgRelease(msg_t msg) { - - chSysLock(); - chDbgAssert(chMsgIsPendingI(currp), - "chMsgRelease(), #1", - "no message pending"); - chSchWakeupS(fifo_remove(&currp->p_msgqueue), msg); - chSysUnlock(); -} - -#endif /* CH_USE_MESSAGES */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chmtx.c b/ChibiOS_2.0.8/os/kernel/src/chmtx.c deleted file mode 100644 index e0b63a3..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chmtx.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chmtx.c - * @brief Mutexes code. - * - * @addtogroup mutexes - * @details Mutexes related APIs and services. - * - *

Operation mode

- * A mutex is a threads synchronization object that can be in two - * distinct states: - * - Not owned. - * - Owned by a thread. - * . - * Operations defined for mutexes: - * - Lock: The mutex is checked, if the mutex is not owned by - * some other thread then it is associated to the locking thread - * else the thread is queued on the mutex in a list ordered by - * priority. - * - Unlock: The mutex is released by the owner and the highest - * priority thread waiting in the queue, if any, is resumed and made - * owner of the mutex. - * . - * In order to use the Mutexes APIs the @p CH_USE_MUTEXES option must - * be enabled in @p chconf.h. - *

Constraints

- * In ChibiOS/RT the Unlock operations are always performed in - * lock-reverse order. The unlock API does not even have a parameter, - * the mutex to unlock is selected from an internal, per-thread, stack - * of owned mutexes. This both improves the performance and is - * required for an efficient implementation of the priority - * inheritance mechanism. - * - *

The priority inversion problem

- * The mutexes in ChibiOS/RT implements the full priority - * inheritance mechanism in order handle the priority inversion - * problem.
- * When a thread is queued on a mutex, any thread, directly or - * indirectly, holding the mutex gains the same priority of the - * waiting thread (if their priority was not already equal or higher). - * The mechanism works with any number of nested mutexes and any - * number of involved threads. The algorithm complexity (worst case) - * is N with N equal to the number of nested mutexes. - * @{ - */ - -#include "ch.h" - -#if CH_USE_MUTEXES - -/** - * @brief Initializes s @p Mutex structure. - * - * @param[out] mp pointer to a @p Mutex structure - */ -void chMtxInit(Mutex *mp) { - - chDbgCheck(mp != NULL, "chMtxInit"); - - queue_init(&mp->m_queue); - mp->m_owner = NULL; -} - -/** - * @brief Locks the specified mutex. - * - * @param[in] mp pointer to the @p Mutex structure - */ -void chMtxLock(Mutex *mp) { - - chSysLock(); - - chMtxLockS(mp); - - chSysUnlock(); -} - -/** - * @brief Locks the specified mutex. - * - * @param[in] mp pointer to the @p Mutex structure - */ -void chMtxLockS(Mutex *mp) { - Thread *ctp = currp; - - chDbgCheck(mp != NULL, "chMtxLockS"); - - /* Ia the mutex already locked? */ - if (mp->m_owner != NULL) { - /* Priority inheritance protocol; explores the thread-mutex dependencies - boosting the priority of all the affected threads to equal the priority - of the running thread requesting the mutex.*/ - Thread *tp = mp->m_owner; - /* Does the running thread have higher priority than the mutex - ownning thread? */ - while (tp->p_prio < ctp->p_prio) { - /* Make priority of thread tp match the running thread's priority.*/ - tp->p_prio = ctp->p_prio; - /* The following states need priority queues reordering.*/ - switch (tp->p_state) { - case THD_STATE_WTMTX: - /* Re-enqueues the mutex owner with its new priority.*/ - prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp); - tp = ((Mutex *)tp->p_u.wtobjp)->m_owner; - continue; -#if CH_USE_CONDVARS | CH_USE_SEMAPHORES_PRIORITY | CH_USE_MESSAGES_PRIORITY -#if CH_USE_CONDVARS - case THD_STATE_WTCOND: -#endif -#if CH_USE_SEMAPHORES_PRIORITY - case THD_STATE_WTSEM: -#endif -#if CH_USE_MESSAGES_PRIORITY - case THD_STATE_SNDMSG: -#endif - /* Re-enqueues tp with its new priority on the queue.*/ - prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp); - break; -#endif - case THD_STATE_READY: - /* Re-enqueues tp with its new priority on the ready list.*/ - chSchReadyI(dequeue(tp)); - } - break; - } - /* Sleep on the mutex.*/ - prio_insert(ctp, &mp->m_queue); - ctp->p_u.wtobjp = mp; - chSchGoSleepS(THD_STATE_WTMTX); - /* It is assumed that the thread performing the unlock operation assigns - the mutex to this thread.*/ - chDbgAssert(mp->m_owner == ctp, "chMtxLockS(), #1", "not owner"); - chDbgAssert(ctp->p_mtxlist == mp, "chMtxLockS(), #2", "not owned"); - } - else { - /* It was not owned, inserted in the owned mutexes list.*/ - mp->m_owner = ctp; - mp->m_next = ctp->p_mtxlist; - ctp->p_mtxlist = mp; - } -} - -/** - * @brief Tries to lock a mutex. - * @details This function does not have any overhead related to - * the priority inheritance mechanism because it does not try to - * enter a sleep state on the mutex. - * - * @param[in] mp pointer to the @p Mutex structure - * @retval TRUE if the mutex was successfully acquired - * @retval FALSE if the lock attempt failed. - */ -bool_t chMtxTryLock(Mutex *mp) { - bool_t b; - - chSysLock(); - - b = chMtxTryLockS(mp); - - chSysUnlock(); - return b; -} - -/** - * @brief Tries to lock a mutex. - * @details This function does not have any overhead related to - * the priority inheritance mechanism because it does not try to - * enter a sleep state on the mutex. - * - * @param[in] mp pointer to the @p Mutex structure - * @retval TRUE if the mutex was successfully acquired - * @retval FALSE if the lock attempt failed. - */ -bool_t chMtxTryLockS(Mutex *mp) { - - chDbgCheck(mp != NULL, "chMtxTryLockS"); - - if (mp->m_owner != NULL) - return FALSE; - mp->m_owner = currp; - mp->m_next = currp->p_mtxlist; - currp->p_mtxlist = mp; - return TRUE; -} - -/** - * @brief Unlocks the next owned mutex in reverse lock order. - * - * @return The pointer to the unlocked mutex. - */ -Mutex *chMtxUnlock(void) { - Thread *ctp = currp; - Mutex *ump, *mp; - - chSysLock(); - chDbgAssert(ctp->p_mtxlist != NULL, - "chMtxUnlock(), #1", - "owned mutexes list empty"); - chDbgAssert(ctp->p_mtxlist->m_owner == ctp, - "chMtxUnlock(), #2", - "ownership failure"); - /* Removes the top Mutex from the Threads's owned mutexes list and matk it - as not owned.*/ - ump = ctp->p_mtxlist; - ctp->p_mtxlist = ump->m_next; - /* If a thread is waiting on the mutex then the fun part begins.*/ - if (chMtxQueueNotEmptyS(ump)) { - Thread *tp; - - /* Recalculates the optimal thread priority by scanning the owned - mutexes list.*/ - tprio_t newprio = ctp->p_realprio; - mp = ctp->p_mtxlist; - while (mp != NULL) { - /* If the highest priority thread waiting in the mutexes list has a - greater priority than the current thread base priority then the final - priority will have at least that priority.*/ - if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio)) - newprio = mp->m_queue.p_next->p_prio; - mp = mp->m_next; - } - /* Assigns to the current thread the highest priority among all the - waiting threads.*/ - ctp->p_prio = newprio; - /* Awakens the highest priority thread waiting for the unlocked mutex and - assigns the mutex to it.*/ - tp = fifo_remove(&ump->m_queue); - ump->m_owner = tp; - ump->m_next = tp->p_mtxlist; - tp->p_mtxlist = ump; - chSchWakeupS(tp, RDY_OK); - } - else - ump->m_owner = NULL; - chSysUnlock(); - return ump; -} - -/** - * @brief Unlocks the next owned mutex in reverse lock order. - * @note This function does not reschedule internally. - * - * @return The pointer to the unlocked mutex. - */ -Mutex *chMtxUnlockS(void) { - Thread *ctp = currp; - Mutex *ump, *mp; - - chDbgAssert(ctp->p_mtxlist != NULL, - "chMtxUnlockS(), #1", - "owned mutexes list empty"); - chDbgAssert(ctp->p_mtxlist->m_owner == ctp, - "chMtxUnlockS(), #2", - "ownership failure"); - - /* Removes the top Mutex from the owned mutexes list and marks it as not - owned.*/ - ump = ctp->p_mtxlist; - ctp->p_mtxlist = ump->m_next; - /* If a thread is waiting on the mutex then the fun part begins.*/ - if (chMtxQueueNotEmptyS(ump)) { - Thread *tp; - - /* Recalculates the optimal thread priority by scanning the owned - mutexes list.*/ - tprio_t newprio = ctp->p_realprio; - mp = ctp->p_mtxlist; - while (mp != NULL) { - /* If the highest priority thread waiting in the mutexes list has a - greater priority than the current thread base priority then the final - priority will have at least that priority.*/ - if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio)) - newprio = mp->m_queue.p_next->p_prio; - mp = mp->m_next; - } - ctp->p_prio = newprio; - /* Awakens the highest priority thread waiting for the unlocked mutex and - assigns the mutex to it.*/ - tp = fifo_remove(&ump->m_queue); - ump->m_owner = tp; - ump->m_next = tp->p_mtxlist; - tp->p_mtxlist = ump; - chSchReadyI(tp); - } - else - ump->m_owner = NULL; - return ump; -} - -/** - * @brief Unlocks all the mutexes owned by the invoking thread. - * @details This function is MUCH MORE efficient than releasing the - * mutexes one by one and not just because the call overhead, - * this function does not have any overhead related to the priority - * inheritance mechanism. - */ -void chMtxUnlockAll(void) { - Thread *ctp = currp; - - chSysLock(); - if (ctp->p_mtxlist != NULL) { - do { - Mutex *ump = ctp->p_mtxlist; - ctp->p_mtxlist = ump->m_next; - if (chMtxQueueNotEmptyS(ump)) { - Thread *tp = fifo_remove(&ump->m_queue); - ump->m_owner = tp; - ump->m_next = tp->p_mtxlist; - tp->p_mtxlist = ump; - chSchReadyI(tp); - } - else - ump->m_owner = NULL; - } while (ctp->p_mtxlist != NULL); - ctp->p_prio = ctp->p_realprio; - chSchRescheduleS(); - } - chSysUnlock(); -} - -#endif /* CH_USE_MUTEXES */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chqueues.c b/ChibiOS_2.0.8/os/kernel/src/chqueues.c deleted file mode 100644 index 8d35003..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chqueues.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chqueues.c - * @brief I/O Queues code. - * - * @addtogroup io_queues - * @details ChibiOS/RT queues are mostly used in serial-like device drivers. - * The device drivers are usually designed to have a lower side - * (lower driver, it is usually an interrupt service routine) and an - * upper side (upper driver, accessed by the application threads).
- * There are several kind of queues:
- * - Input queue, unidirectional queue where the writer is the - * lower side and the reader is the upper side. - * - Output queue, unidirectional queue where the writer is the - * upper side and the reader is the lower side. - * - Full duplex queue, bidirectional queue. Full duplex queues - * are implemented by pairing an input queue and an output queue - * together. - * . - * In order to use the I/O queues the @p CH_USE_QUEUES option must - * be enabled in @p chconf.h.
- * I/O queues are usually used as an implementation layer for the I/O - * channels interface, also see @ref io_channels. - * @{ - */ - -#include "ch.h" - -#if CH_USE_QUEUES - -/** - * @brief Initializes an input queue. - * @details A Semaphore is internally initialized and works as a counter of - * the bytes contained in the queue. - * @note The callback is invoked from within the S-Locked system state, - * see @ref system_states. - * - * @param[out] iqp pointer to an @p InputQueue structure - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] infy pointer to a callback function that is invoked when - * data is read from the queue. The value can be @p NULL. - */ -void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy) { - - iqp->q_buffer = iqp->q_rdptr = iqp->q_wrptr = bp; - iqp->q_top = bp + size; - iqp->q_notify = infy; - chSemInit(&iqp->q_sem, 0); -} - -/** - * @brief Resets an input queue. - * @details All the data in the input queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] iqp pointer to an @p InputQueue structure - */ -void chIQResetI(InputQueue *iqp) { - - iqp->q_rdptr = iqp->q_wrptr = iqp->q_buffer; - chSemResetI(&iqp->q_sem, 0); -} - -/** - * @brief Input queue write. - * @details A byte value is written into the low end of an input queue. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @param[in] b the byte value to be written in the queue - * @return The operation status, it can be one of: - * @retval Q_OK if the operation has been completed with success. - * @retval Q_FULL if the queue is full and the operation cannot be - * completed. - */ -msg_t chIQPutI(InputQueue *iqp, uint8_t b) { - - if (chIQIsFull(iqp)) - return Q_FULL; - - *iqp->q_wrptr++ = b; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - chSemSignalI(&iqp->q_sem); - return Q_OK; -} - -/** - * @brief Input queue read with timeout. - * @details This function reads a byte value from an input queue. If the queue - * is empty then the calling thread is suspended until a byte arrives - * in the queue or a timeout occurs. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return A byte value from the queue or: - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue was reset. - */ -msg_t chIQGetTimeout(InputQueue *iqp, systime_t time) { - uint8_t b; - msg_t msg; - - chSysLock(); - - if (iqp->q_notify) - iqp->q_notify(); - - if ((msg = chSemWaitTimeoutS(&iqp->q_sem, time)) < RDY_OK) { - chSysUnlock(); - return msg; - } - b = *iqp->q_rdptr++; - if (iqp->q_rdptr >= iqp->q_top) - iqp->q_rdptr = iqp->q_buffer; - - chSysUnlock(); - return b; -} - -/** - * @brief Input queue read with timeout. - * @details The function reads data from an input queue into a buffer. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is suggested - * to use a semaphore or a mutex for mutual exclusion. - * @note The queue callback is invoked before entering a sleep state and at - * the end of the transfer. - * - * @param[in] iqp pointer to an @p InputQueue structure - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - */ -size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp, - size_t n, systime_t time) { - qnotify_t nfy = iqp->q_notify; - size_t r = 0; - - chDbgCheck(n > 0, "chIQReadTimeout"); - - chSysLock(); - while (TRUE) { - if (chIQIsEmpty(iqp)) { - if (nfy) - nfy(); - if ((chSemWaitTimeoutS(&iqp->q_sem, time) != RDY_OK)) { - chSysUnlock(); - return r; - } - } - else - chSemFastWaitI(&iqp->q_sem); - *bp++ = *iqp->q_rdptr++; - if (iqp->q_rdptr >= iqp->q_top) - iqp->q_rdptr = iqp->q_buffer; - if (nfy) - nfy(); - chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - r++; - if (--n == 0) { - chSysLock(); - if (nfy) - nfy(); - chSysUnlock(); - return r; - } - chSysLock(); - } -} - -/** - * @brief Initializes an output queue. - * @details A Semaphore is internally initialized and works as a counter of - * the free bytes in the queue. - * @note The callback is invoked from within the S-Locked system state, - * see @ref system_states. - * - * @param[out] oqp pointer to an @p OutputQueue structure - * @param[in] bp pointer to a memory area allocated as queue buffer - * @param[in] size size of the queue buffer - * @param[in] onfy pointer to a callback function that is invoked when - * data is written to the queue. The value can be @p NULL. - */ -void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy) { - - oqp->q_buffer = oqp->q_rdptr = oqp->q_wrptr = bp; - oqp->q_top = bp + size; - oqp->q_notify = onfy; - chSemInit(&oqp->q_sem, (cnt_t)size); -} - -/** - * @brief Resets an output queue. - * @details All the data in the output queue is erased and lost, any waiting - * thread is resumed with status @p Q_RESET. - * @note A reset operation can be used by a low level driver in order to - * obtain immediate attention from the high level layers. - * - * @param[in] oqp pointer to an @p OutputQueue structure - */ -void chOQResetI(OutputQueue *oqp) { - - oqp->q_rdptr = oqp->q_wrptr = oqp->q_buffer; - chSemResetI(&oqp->q_sem, (cnt_t)(oqp->q_top - oqp->q_buffer)); -} - -/** - * @brief Output queue write with timeout. - * @details This function writes a byte value to an output queue. If the queue - * is full then the calling thread is suspended until there is space - * in the queue or a timeout occurs. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @param[in] b the byte value to be written in the queue - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status: - * @retval Q_OK if the operation succeeded. - * @retval Q_TIMEOUT if the specified time expired. - * @retval Q_RESET if the queue was reset. - */ -msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time) { - msg_t msg; - - chSysLock(); - if ((msg = chSemWaitTimeoutS(&oqp->q_sem, time)) < RDY_OK) { - chSysUnlock(); - return msg; - } - *oqp->q_wrptr++ = b; - if (oqp->q_wrptr >= oqp->q_top) - oqp->q_wrptr = oqp->q_buffer; - - if (oqp->q_notify) - oqp->q_notify(); - - chSysUnlock(); - return Q_OK; -} - -/** - * @brief Output queue read. - * @details A byte value is read from the low end of an output queue. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @return The byte value from the queue or: - * @retval Q_EMPTY if the queue is empty. - */ -msg_t chOQGetI(OutputQueue *oqp) { - uint8_t b; - - if (chOQIsEmpty(oqp)) - return Q_EMPTY; - - b = *oqp->q_rdptr++; - if (oqp->q_rdptr >= oqp->q_top) - oqp->q_rdptr = oqp->q_buffer; - chSemSignalI(&oqp->q_sem); - return b; -} - -/** - * @brief Output queue write with timeout. - * @details The function writes data from a buffer to an output queue. The - * operation completes when the specified amount of data has been - * transferred or after the specified timeout or if the queue has - * been reset. - * @note The function is not atomic, if you need atomicity it is suggested - * to use a semaphore or a mutex for mutual exclusion. - * @note The queue callback is invoked before entering a sleep state and at - * the end of the transfer. - * - * @param[in] oqp pointer to an @p OutputQueue structure - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred, the - * value 0 is reserved - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @return The number of bytes effectively transferred. - */ -size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp, - size_t n, systime_t time) { - qnotify_t nfy = oqp->q_notify; - size_t w = 0; - - chDbgCheck(n > 0, "chOQWriteTimeout"); - - chSysLock(); - while (TRUE) { - if (chOQIsFull(oqp)) { - if (nfy) - nfy(); - if ((chSemWaitTimeoutS(&oqp->q_sem, time) != RDY_OK)) { - chSysUnlock(); - return w; - } - } - else - chSemFastWaitI(&oqp->q_sem); - *oqp->q_wrptr++ = *bp++; - if (oqp->q_wrptr >= oqp->q_top) - oqp->q_wrptr = oqp->q_buffer; - chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - w++; - if (--n == 0) { - chSysLock(); - if (nfy) - nfy(); - chSysUnlock(); - return w; - } - chSysLock(); - } -} -#endif /* CH_USE_QUEUES */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chregistry.c b/ChibiOS_2.0.8/os/kernel/src/chregistry.c deleted file mode 100644 index c5d4ee1..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chregistry.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chregistry.c - * @brief Threads registry code. - * - * @addtogroup registry - * @details Threads Registry related APIs and services. - * - *

Operation mode

- * The Threads Registry is a double linked list that holds all the - * active threads in the system.
- * Operations defined for the registry: - * - First, returns the first, in creation order, active thread - * in the system. - * - Next, returns the next, in creation order, active thread - * in the system. - * . - * The registry is meant to be mainly a debug feature, as example, - * using the registry a debugger can enumerate the active threads - * in any given moment or the shell can print the active threads - * and their state.
- * Another possible use is for centralized threads memory management, - * terminating threads can pulse an event source and an event handler - * can perform a scansion of the registry in order to recover the - * memory.
- * In order to use the threads registry the @p CH_USE_REGISTRY option - * must be enabled in @p chconf.h. - * @{ - */ -#include "ch.h" - -#if CH_USE_REGISTRY - -/** - * @brief Returns the first thread in the system. - * @details Returns the most ancient thread in the system, usually this is - * the main thread unless it terminated. - * @note A reference is added to the returned thread in order to make sure - * it status is not lost. - * @note This function cannot return @p NULL because there is always at - * least one thread in the system. - * - * @return A reference to the first thread. - */ -Thread *chRegFirstThread(void) { - Thread *tp; - - chSysLock(); - tp = rlist.r_newer; -#if CH_USE_DYNAMIC - tp->p_refs++; -#endif - chSysUnlock(); - return tp; -} - -/** - * @brief Returns the thread next to the specified one. - * @details The reference counter of the specified thread is decremented and - * the reference counter of the returned thread is incremented. - * - * @param[in] tp pointer to the thread - * @return A reference to the next thread. - * @retval NULL if there is no next thread. - */ -Thread *chRegNextThread(Thread *tp) { - Thread *ntp; - - chSysLock(); - ntp = tp->p_newer; - if (ntp == (Thread *)&rlist) - ntp = NULL; -#if CH_USE_DYNAMIC - else { - chDbgAssert(ntp->p_refs < 255, "chRegNextThread(), #1", - "too many references"); - ntp->p_refs++; - } -#endif - chSysUnlock(); -#if CH_USE_DYNAMIC - chThdRelease(tp); -#endif - return ntp; -} - -#endif /* CH_USE_REGISTRY */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chschd.c b/ChibiOS_2.0.8/os/kernel/src/chschd.c deleted file mode 100644 index c98350c..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chschd.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chschd.c - * @brief Scheduler code. - * - * @addtogroup scheduler - * @details This module provides the default portable scheduler code, - * scheduler functions can be individually captured by the port - * layer in order to provide architecture optimized equivalents. - * When a function is captured its default code is not built into - * the OS image, the optimized version is included instead. - * @{ - */ - -#include "ch.h" - -/** - * @brief Ready list header. - */ -#if !defined(PORT_OPTIMIZED_RLIST_VAR) || defined(__DOXYGEN__) -ReadyList rlist; -#endif /* !defined(PORT_OPTIMIZED_RLIST_VAR) */ - -/** - * @brief Scheduler initialization. - * @note Internally invoked by the @p chSysInit(), not an API. - */ -void scheduler_init(void) { - - queue_init(&rlist.r_queue); - rlist.r_prio = NOPRIO; -#if CH_TIME_QUANTUM > 0 - rlist.r_preempt = CH_TIME_QUANTUM; -#endif -#if CH_USE_REGISTRY - rlist.r_newer = rlist.r_older = (Thread *)&rlist; -#endif -} - -/** - * @brief Inserts a thread in the Ready List. - * @note The function does not reschedule, the @p chSchRescheduleS() should - * be called soon after. - * - * @param[in] tp the Thread to be made ready - * @return The Thread pointer. - */ -#if !defined(PORT_OPTIMIZED_READYI) || defined(__DOXYGEN__) -#if CH_OPTIMIZE_SPEED -/* NOTE: it is inlined in this module only.*/ -INLINE Thread *chSchReadyI(Thread *tp) { -#else -Thread *chSchReadyI(Thread *tp) { -#endif - Thread *cp; - - tp->p_state = THD_STATE_READY; - cp = (Thread *)&rlist.r_queue; - do { - cp = cp->p_next; - } while (cp->p_prio >= tp->p_prio); - /* Insertion on p_prev.*/ - tp->p_next = cp; - tp->p_prev = cp->p_prev; - tp->p_prev->p_next = cp->p_prev = tp; - return tp; -} -#endif /* !defined(PORT_OPTIMIZED_READYI) */ - -/** - * @brief Puts the current thread to sleep into the specified state. - * @details The thread goes into a sleeping state. The @ref thread_states are - * described into @p threads.h. - * - * @param[in] newstate the new thread state - */ -#if !defined(PORT_OPTIMIZED_GOSLEEPS) || defined(__DOXYGEN__) -void chSchGoSleepS(tstate_t newstate) { - Thread *otp; - - (otp = currp)->p_state = newstate; -#if CH_TIME_QUANTUM > 0 - rlist.r_preempt = CH_TIME_QUANTUM; -#endif - setcurrp(fifo_remove(&rlist.r_queue)); - currp->p_state = THD_STATE_CURRENT; - chDbgTrace(otp); - chSysSwitchI(currp, otp); -} -#endif /* !defined(PORT_OPTIMIZED_GOSLEEPS) */ - -#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) || defined(__DOXYGEN__) -/* - * Timeout wakeup callback. - */ -static void wakeup(void *p) { - Thread *tp = (Thread *)p; - - switch (tp->p_state) { - case THD_STATE_READY: - /* Handling the special case where the thread has been made ready by - another thread with higher priority.*/ - return; -#if CH_USE_SEMAPHORES || (CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT) -#if CH_USE_SEMAPHORES - case THD_STATE_WTSEM: - chSemFastSignalI((Semaphore *)tp->p_u.wtobjp); - /* Falls into, intentional. */ -#endif -#if CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT - case THD_STATE_WTCOND: -#endif - /* States requiring dequeuing.*/ - dequeue(tp); -#endif - } - tp->p_u.rdymsg = RDY_TIMEOUT; - chSchReadyI(tp); -} - -/** - * @brief Puts the current thread to sleep into the specified state with - * timeout specification. - * @details The thread goes into a sleeping state, if it is not awakened - * explicitly within the specified timeout then it is forcibly - * awakened with a @p RDY_TIMEOUT low level message. The @ref - * thread_states are described into @p threads.h. - * - * @param[in] newstate the new thread state - * @param[in] time the number of ticks before the operation timeouts, the - * special values are handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state, this is equivalent to invoking - * @p chSchGoSleepS() but, of course, less efficient. - * - @a TIME_IMMEDIATE this value is accepted but - * interpreted as a normal time specification not as an - * immediate timeout specification. - * . - * @return The wakeup message. - * @retval RDY_TIMEOUT if a timeout occurs. - */ -msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) { - - if (TIME_INFINITE != time) { - VirtualTimer vt; - - chVTSetI(&vt, time, wakeup, currp); - chSchGoSleepS(newstate); - if (chVTIsArmedI(&vt)) - chVTResetI(&vt); - } - else - chSchGoSleepS(newstate); - return currp->p_u.rdymsg; -} -#endif /* !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) */ - -/** - * @brief Wakes up a thread. - * @details The thread is inserted into the ready list or immediately made - * running depending on its relative priority compared to the current - * thread. - * @note It is equivalent to a @p chSchReadyI() followed by a - * @p chSchRescheduleS() but much more efficient. - * @note The function assumes that the current thread has the highest - * priority. - * - * @param[in] ntp the Thread to be made ready - * @param[in] msg message to the awakened thread - */ -#if !defined(PORT_OPTIMIZED_WAKEUPS) || defined(__DOXYGEN__) -void chSchWakeupS(Thread *ntp, msg_t msg) { - - ntp->p_u.rdymsg = msg; - /* If the waken thread has a not-greater priority than the current - one then it is just inserted in the ready list else it made - running immediately and the invoking thread goes in the ready - list instead.*/ - if (ntp->p_prio <= currp->p_prio) - chSchReadyI(ntp); - else { - Thread *otp = chSchReadyI(currp); -#if CH_TIME_QUANTUM > 0 - rlist.r_preempt = CH_TIME_QUANTUM; -#endif - setcurrp(ntp); - ntp->p_state = THD_STATE_CURRENT; - chDbgTrace(otp); - chSysSwitchI(ntp, otp); - } -} -#endif /* !defined(PORT_OPTIMIZED_WAKEUPS) */ - -/** - * @brief Switches to the first thread on the runnable queue. - * @note It is intended to be called if @p chSchRescRequiredI() evaluates - * to @p TRUE. - */ -#if !defined(PORT_OPTIMIZED_DORESCHEDULEI) || defined(__DOXYGEN__) -void chSchDoRescheduleI(void) { - Thread *otp; - -#if CH_TIME_QUANTUM > 0 - rlist.r_preempt = CH_TIME_QUANTUM; -#endif - otp = currp; - /* Picks the first thread from the ready queue and makes it current.*/ - setcurrp(fifo_remove(&rlist.r_queue)); - currp->p_state = THD_STATE_CURRENT; - chSchReadyI(otp); - chDbgTrace(otp); - chSysSwitchI(currp, otp); -} -#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEI) */ - -/** - * @brief Performs a reschedule if a higher priority thread is runnable. - * @details If a thread with a higher priority than the current thread is in - * the ready list then make the higher priority thread running. - */ -#if !defined(PORT_OPTIMIZED_RESCHEDULES) || defined(__DOXYGEN__) -void chSchRescheduleS(void) { - - if (chSchIsRescRequiredI()) - chSchDoRescheduleI(); -} -#endif /* !defined(PORT_OPTIMIZED_RESCHEDULES) */ - -/** - * @brief Evaluates if a reschedule is required. - * @details The decision is taken by comparing the relative priorities and - * depending on the state of the round robin timeout counter. - * @note This function is meant to be used in the timer interrupt handler - * where @p chVTDoTickI() is invoked. - * - * @retval TRUE if there is a thread that should go in running state. - * @retval FALSE if a reschedule is not required. - */ -#if !defined(PORT_OPTIMIZED_ISRESCHREQUIREDEXI) || defined(__DOXYGEN__) -bool_t chSchIsRescRequiredExI(void) { - tprio_t p1 = firstprio(&rlist.r_queue); - tprio_t p2 = currp->p_prio; -#if CH_TIME_QUANTUM > 0 - /* If the running thread has not reached its time quantum, reschedule only - if the first thread on the ready queue has a higher priority. - Otherwise, if the running thread has used up its time quantum, reschedule - if the first thread on the ready queue has equal or higher priority.*/ - return rlist.r_preempt ? p1 > p2 : p1 >= p2; -#else - /* If the round robin preemption feature is not enabled then performs a - simpler comparison.*/ - return p1 > p2; -#endif -} -#endif /* !defined(PORT_OPTIMIZED_ISRESCHREQUIREDEXI) */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chsem.c b/ChibiOS_2.0.8/os/kernel/src/chsem.c deleted file mode 100644 index 4769f15..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chsem.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chsem.c - * @brief Semaphores code. - * - * @addtogroup semaphores - * @details Semaphores related APIs and services. - * - *

Operation mode

- * Semaphores are a flexible synchronization primitive, ChibiOS/RT - * implements semaphores in their "counting semaphores" variant as - * defined by Edsger Dijkstra plus several enhancements like: - * - Wait operation with timeout. - * - Reset operation. - * - Atomic wait+signal operation. - * - Return message from the wait operation (OK, RESET, TIMEOUT). - * . - * The binary semaphores variant can be easily implemented using - * counting semaphores.
- * Operations defined for semaphores: - * - Signal: The semaphore counter is increased and if the - * result is non-positive then a waiting thread is removed from - * the semaphore queue and made ready for execution. - * - Wait: The semaphore counter is decreased and if the result - * becomes negative the thread is queued in the semaphore and - * suspended. - * - Reset: The semaphore counter is reset to a non-negative - * value and all the threads in the queue are released. - * . - * Semaphores can be used as guards for mutual exclusion zones - * (note that mutexes are recommended for this kind of use) but - * also have other uses, queues guards and counters as example.
- * Semaphores usually use a FIFO queuing strategy but it is possible - * to make them order threads by priority by enabling - * @p CH_USE_SEMAPHORES_PRIORITY in @p chconf.h.
- * In order to use the Semaphores APIs the @p CH_USE_SEMAPHORES - * option must be enabled in @p chconf.h. - * @{ - */ - -#include "ch.h" - -#if CH_USE_SEMAPHORES - -#if CH_USE_SEMAPHORES_PRIORITY -#define sem_insert(tp, qp) prio_insert(tp, qp) -#else -#define sem_insert(tp, qp) queue_insert(tp, qp) -#endif - -/** - * @brief Initializes a semaphore with the specified counter value. - * - * @param[out] sp pointer to a @p Semaphore structure - * @param[in] n initial value of the semaphore counter. Must be - * non-negative. - */ -void chSemInit(Semaphore *sp, cnt_t n) { - - chDbgCheck((sp != NULL) && (n >= 0), "chSemInit"); - - queue_init(&sp->s_queue); - sp->s_cnt = n; -} - -/** - * @brief Performs a reset operation on the semaphore. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p chSemWait() will return - * @p RDY_RESET instead of @p RDY_OK. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] n the new value of the semaphore counter. The value must - * be non-negative. - */ -void chSemReset(Semaphore *sp, cnt_t n) { - - chSysLock(); - chSemResetI(sp, n); - chSchRescheduleS(); - chSysUnlock(); -} - -/** - * @brief Performs a reset operation on the semaphore. - * @note The released threads can recognize they were waked up by a reset - * rather than a signal because the @p chSemWait() will return - * @p RDY_RESET instead of @p RDY_OK. - * @note This function does not reschedule. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] n the new value of the semaphore counter. The value must - * be non-negative. - */ -void chSemResetI(Semaphore *sp, cnt_t n) { - cnt_t cnt; - - chDbgCheck((sp != NULL) && (n >= 0), "chSemResetI"); - - cnt = sp->s_cnt; - sp->s_cnt = n; - while (++cnt <= 0) - chSchReadyI(lifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_RESET; -} - -/** - * @brief Performs a wait operation on a semaphore. - * - * @param[in] sp pointer to a @p Semaphore structure - * @retval RDY_OK if the semaphore was signaled or not taken. - * @retval RDY_RESET if the semaphore was reset using @p chSemReset(). - */ -msg_t chSemWait(Semaphore *sp) { - msg_t msg; - - chSysLock(); - msg = chSemWaitS(sp); - chSysUnlock(); - return msg; -} - -/** - * @brief Performs a wait operation on a semaphore. - * - * @param[in] sp pointer to a @p Semaphore structure - * @retval RDY_OK if the semaphore was signaled or not taken. - * @retval RDY_RESET if the semaphore was reset using @p chSemReset(). - */ -msg_t chSemWaitS(Semaphore *sp) { - - chDbgCheck(sp != NULL, "chSemWaitS"); - - if (--sp->s_cnt < 0) { - currp->p_u.wtobjp = sp; - sem_insert(currp, &sp->s_queue); - chSchGoSleepS(THD_STATE_WTSEM); - return currp->p_u.rdymsg; - } - return RDY_OK; -} - -/** - * @brief Performs a wait operation on a semaphore with timeout specification. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @retval RDY_OK if the semaphore was signaled or not taken. - * @retval RDY_RESET if the semaphore was reset using @p chSemReset(). - * @retval RDY_TIMEOUT if the semaphore was not signaled or reset within the - * specified timeout. - */ -msg_t chSemWaitTimeout(Semaphore *sp, systime_t time) { - msg_t msg; - - chSysLock(); - msg = chSemWaitTimeoutS(sp, time); - chSysUnlock(); - return msg; -} - -/** - * @brief Performs a wait operation on a semaphore with timeout specification. - * - * @param[in] sp pointer to a @p Semaphore structure - * @param[in] time the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_IMMEDIATE immediate timeout. - * - @a TIME_INFINITE no timeout. - * . - * @retval RDY_OK if the semaphore was signaled or not taken. - * @retval RDY_RESET if the semaphore was reset using @p chSemReset(). - * @retval RDY_TIMEOUT if the semaphore was not signaled or reset within the - * specified timeout. - */ -msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time) { - - chDbgCheck(sp != NULL, "chSemWaitTimeoutS"); - - if (--sp->s_cnt < 0) { - if (TIME_IMMEDIATE == time) { - sp->s_cnt++; - return RDY_TIMEOUT; - } - currp->p_u.wtobjp = sp; - sem_insert(currp, &sp->s_queue); - return chSchGoSleepTimeoutS(THD_STATE_WTSEM, time); - } - return RDY_OK; -} - -/** - * @brief Performs a signal operation on a semaphore. - * - * @param[in] sp pointer to a @p Semaphore structure - */ -void chSemSignal(Semaphore *sp) { - - chDbgCheck(sp != NULL, "chSemSignal"); - - chSysLock(); - if (++sp->s_cnt <= 0) - chSchWakeupS(fifo_remove(&sp->s_queue), RDY_OK); - chSysUnlock(); -} - -/** - * @brief Performs a signal operation on a semaphore. - * @note This function does not reschedule. - * - * @param[in] sp pointer to a @p Semaphore structure - */ -void chSemSignalI(Semaphore *sp) { - - chDbgCheck(sp != NULL, "chSemSignalI"); - - if (++sp->s_cnt <= 0) { - /* note, it is done this way in order to allow a tail call on - chSchReadyI().*/ - Thread *tp = fifo_remove(&sp->s_queue); - tp->p_u.rdymsg = RDY_OK; - chSchReadyI(tp); - } -} - -#if CH_USE_SEMSW -/** - * @brief Performs atomic signal and wait operations on two semaphores. - * @note The function is available only if the @p CH_USE_SEMSW - * option is enabled in @p chconf.h. - * - * @param[in] sps pointer to a @p Semaphore structure to be signaled - * @param[in] spw pointer to a @p Semaphore structure to be wait on - * @retval RDY_OK if the semaphore was signaled or not taken. - * @retval RDY_RESET if the semaphore was reset using @p chSemReset(). - */ -msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw) { - msg_t msg; - - chDbgCheck((sps != NULL) && (spw != NULL), "chSemSignalWait"); - - chSysLock(); - if (++sps->s_cnt <= 0) - chSchReadyI(fifo_remove(&sps->s_queue))->p_u.rdymsg = RDY_OK; - if (--spw->s_cnt < 0) { - Thread *ctp = currp; - sem_insert(ctp, &spw->s_queue); - ctp->p_u.wtobjp = spw; - chSchGoSleepS(THD_STATE_WTSEM); - msg = ctp->p_u.rdymsg; - } - else { - chSchRescheduleS(); - msg = RDY_OK; - } - chSysUnlock(); - return msg; -} -#endif /* CH_USE_SEMSW */ - -#endif /* CH_USE_SEMAPHORES */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chsys.c b/ChibiOS_2.0.8/os/kernel/src/chsys.c deleted file mode 100644 index 21fee0e..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chsys.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chsys.c - * @brief System related code. - * - * @addtogroup system - * @details System related APIs and services: - * - Initialization. - * - Locks. - * - Interrupt Handling. - * - Power Management. - * - Abnormal Termination. - * . - * @{ - */ - -#include "ch.h" - -static WORKING_AREA(idle_thread_wa, IDLE_THREAD_STACK_SIZE); - -/** - * @brief This function implements the idle thread infinite loop. - * @details The function puts the processor in the lowest power mode capable - * to serve interrupts.
- * The priority is internally set to the minimum system value so - * that this thread is executed only if there are no other ready - * threads in the system. - * - * @param[in] p the thread parameter, unused in this scenario - */ -static void idle_thread(void *p) { - - (void)p; - while (TRUE) { - port_wait_for_interrupt(); - IDLE_LOOP_HOOK(); - } -} - -/** - * @brief ChibiOS/RT initialization. - * @details After executing this function the current instructions stream - * becomes the main thread. - * @note Interrupts should be still disabled when @p chSysInit() is invoked - * and are internally enabled. - * @note The main thread is created with priority @p NORMALPRIO. - */ -void chSysInit(void) { - static Thread mainthread; - - port_init(); - scheduler_init(); - vt_init(); -#if CH_USE_MEMCORE - core_init(); -#endif -#if CH_USE_HEAP - heap_init(); -#endif -#if CH_DBG_ENABLE_TRACE - trace_init(); -#endif - - /* Now this instructions flow becomes the main thread.*/ - setcurrp(init_thread(&mainthread, NORMALPRIO)); - currp->p_state = THD_STATE_CURRENT; - chSysEnable(); - - /* This thread has the lowest priority in the system, its role is just to - serve interrupts in its context while keeping the lowest energy saving - mode compatible with the system status.*/ - chThdCreateStatic(idle_thread_wa, sizeof(idle_thread_wa), IDLEPRIO, - (tfunc_t)idle_thread, NULL); -} - -/** - * @brief Handles time ticks for round robin preemption and timer increments. - * @details Decrements the remaining time quantum of the running thread - * and preempts it when the quantum is used up. Increments system - * time and manages the timers. - * - * @note The frequency of the timer determines the system tick granularity - * and, together with the @p CH_TIME_QUANTUM macro, the round robin - * interval. - */ -void chSysTimerHandlerI(void) { - -#if CH_TIME_QUANTUM > 0 - /* Running thread has not used up quantum yet? */ - if (rlist.r_preempt > 0) - /* Decrement remaining quantum.*/ - rlist.r_preempt--; -#endif -#if CH_DBG_THREADS_PROFILING - currp->p_time++; -#endif - chVTDoTickI(); -} - -#if CH_USE_NESTED_LOCKS && !CH_OPTIMIZE_SPEED -void chSysLock(void) { - - chDbgAssert(currp->p_locks >= 0, - "chSysLock(), #1", - "negative nesting counter"); - if (currp->p_locks++ == 0) - port_lock(); -} - -void chSysUnlock(void) { - - chDbgAssert(currp->p_locks > 0, - "chSysUnlock(), #1", - "non-positive nesting counter"); - if (--currp->p_locks == 0) - port_unlock(); -} -#endif /* CH_USE_NESTED_LOCKS && !CH_OPTIMIZE_SPEED */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chthreads.c b/ChibiOS_2.0.8/os/kernel/src/chthreads.c deleted file mode 100644 index 05caa40..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chthreads.c +++ /dev/null @@ -1,522 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chthreads.c - * @brief Threads code. - * - * @addtogroup threads - * @details Threads related APIs and services. - * - *

Operation mode

- * A thread is an abstraction of an independent instructions flow. - * In ChibiOS/RT a thread is represented by a "C" function owning - * a processor context, state informations and a dedicated stack - * area. In this scenario static variables are shared among all - * threads while automatic variables are local to the thread.
- * Operations defined for threads: - * - Init, a thread is prepared and put in the suspended - * state. - * - Create, a thread is started on the specified thread - * function. This operation is available in multiple variants, - * both static and dynamic. - * - Exit, a thread terminates by returning from its top - * level function or invoking a specific API, the thread can - * return a value that can be retrieved by other threads. - * - Wait, a thread waits for the termination of another - * thread and retrieves its return value. - * - Resume, a thread created in suspended state is started. - * - Sleep, the execution of a thread is suspended for the - * specified amount of time or the specified future absolute time - * is reached. - * - SetPriority, a thread changes its own priority level. - * - Yield, a thread voluntarily renounces to its time slot. - * . - * The threads subsystem is implicitly included in kernel however - * some of its part may be excluded by disabling them in @p chconf.h, - * see the @p CH_USE_WAITEXIT and @p CH_USE_DYNAMIC configuration - * options. - * @{ - */ - -#include "ch.h" - -/** - * @brief Initializes a thread structure. - * - * @param[in] tp pointer to the thread - * @param[in] prio the priority level for the new thread - * @return The same thread pointer passed as parameter. - */ -Thread *init_thread(Thread *tp, tprio_t prio) { - - tp->p_prio = prio; - tp->p_state = THD_STATE_SUSPENDED; - tp->p_flags = THD_MEM_MODE_STATIC; -#if CH_USE_MUTEXES - tp->p_realprio = prio; - tp->p_mtxlist = NULL; -#endif -#if CH_USE_EVENTS - tp->p_epending = 0; -#endif -#if CH_USE_NESTED_LOCKS - tp->p_locks = 0; -#endif -#if CH_DBG_THREADS_PROFILING - tp->p_time = 0; -#endif -#if CH_USE_DYNAMIC - tp->p_refs = 1; -#endif -#if CH_USE_WAITEXIT - list_init(&tp->p_waiting); -#endif -#if CH_USE_MESSAGES - queue_init(&tp->p_msgqueue); -#endif -#if CH_USE_REGISTRY - REG_INSERT(tp); -#endif -#if defined(THREAD_EXT_INIT) - THREAD_EXT_INIT(tp); -#endif - return tp; -} - -#if CH_DBG_FILL_THREADS -static void memfill(uint8_t *startp, uint8_t *endp, uint8_t v) { - - while (startp < endp) - *startp++ = v; -} -#endif - -/** - * @brief Creates a new thread into a static memory area. - * @details The new thread is initialized but not inserted in the ready list, - * the initial state is @p THD_STATE_SUSPENDED. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note Threads created using this function do not obey to the - * @p CH_DBG_FILL_THREADS debug option because it would keep - * the kernel locked for too much time. - * - * @param[out] wsp pointer to a working area dedicated to the thread stack - * @param[in] size size of the working area - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p Thread structure allocated for - * the thread into the working space area. - */ -Thread *chThdCreateI(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - /* Thread structure is layed out in the lower part of the thread workspace */ - Thread *tp = wsp; - - chDbgCheck((wsp != NULL) && (size >= THD_WA_SIZE(0)) && - (prio <= HIGHPRIO) && (pf != NULL), - "chThdCreateI"); - SETUP_CONTEXT(wsp, size, pf, arg); - return init_thread(tp, prio); -} - -/** - * @brief Creates a new thread into a static memory area. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * - * @param[out] wsp pointer to a working area dedicated to the thread stack - * @param[in] size size of the working area - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p Thread structure allocated for - * the thread into the working space area. - */ -Thread *chThdCreateStatic(void *wsp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - Thread *tp; - -#if CH_DBG_FILL_THREADS - memfill((uint8_t *)wsp, (uint8_t *)wsp + sizeof(Thread), THREAD_FILL_VALUE); - memfill((uint8_t *)wsp + sizeof(Thread), - (uint8_t *)wsp + size, STACK_FILL_VALUE); -#endif - chSysLock(); - chSchWakeupS(tp = chThdCreateI(wsp, size, prio, pf, arg), RDY_OK); - chSysUnlock(); - return tp; -} - -#if CH_USE_DYNAMIC && CH_USE_HEAP -/** - * @brief Creates a new thread allocating the memory from the heap. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note The memory allocated for the thread is not released when the thread - * terminates but when a @p chThdWait() is performed. - * @note The function is available only if the @p CH_USE_DYNAMIC, - * @p CH_USE_HEAP and @p CH_USE_WAITEXIT options are enabled - * in @p chconf.h. - * - * @param[in] heapp heap from which allocate the memory or @p NULL for the - * default heap - * @param[in] size size of the working area to be allocated - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p Thread structure allocated for - * the thread into the working space area. - * @retval NULL if the memory cannot be allocated. - */ -Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size, - tprio_t prio, tfunc_t pf, void *arg) { - void *wsp; - Thread *tp; - - wsp = chHeapAlloc(heapp, size); - if (wsp == NULL) - return NULL; - -#if CH_DBG_FILL_THREADS - memfill((uint8_t *)wsp, (uint8_t *)wsp + sizeof(Thread), THREAD_FILL_VALUE); - memfill((uint8_t *)wsp + sizeof(Thread), - (uint8_t *)wsp + size, STACK_FILL_VALUE); -#endif - - chSysLock(); - tp = chThdCreateI(wsp, size, prio, pf, arg); - tp->p_flags = THD_MEM_MODE_HEAP; - chSchWakeupS(tp, RDY_OK); - chSysUnlock(); - return tp; -} -#endif /* CH_USE_DYNAMIC && CH_USE_HEAP */ - -#if CH_USE_DYNAMIC && CH_USE_MEMPOOLS -/** - * @brief Creates a new thread allocating the memory from the specified - * memory pool. - * @note A thread can terminate by calling @p chThdExit() or by simply - * returning from its main function. - * @note The memory allocated for the thread is not released when the thread - * terminates but when a @p chThdWait() is performed. - * @note The function is available only if the @p CH_USE_DYNAMIC, - * @p CH_USE_MEMPOOLS and @p CH_USE_WAITEXIT options are enabled - * in @p chconf.h. - * - * @param[in] mp pointer to the memory pool object - * @param[in] prio the priority level for the new thread - * @param[in] pf the thread function - * @param[in] arg an argument passed to the thread function. It can be - * @p NULL. - * @return The pointer to the @p Thread structure allocated for - * the thread into the working space area. - * @retval NULL if the memory pool is empty. - */ -Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio, - tfunc_t pf, void *arg) { - void *wsp; - Thread *tp; - - chDbgCheck(mp != NULL, "chThdCreateFromMemoryPool"); - - wsp = chPoolAlloc(mp); - if (wsp == NULL) - return NULL; - -#if CH_DBG_FILL_THREADS - memfill((uint8_t *)wsp, (uint8_t *)wsp + sizeof(Thread), THREAD_FILL_VALUE); - memfill((uint8_t *)wsp + sizeof(Thread), - (uint8_t *)wsp + mp->mp_object_size, STACK_FILL_VALUE); -#endif - - chSysLock(); - tp = chThdCreateI(wsp, mp->mp_object_size, prio, pf, arg); - tp->p_flags = THD_MEM_MODE_MEMPOOL; - tp->p_mpool = mp; - chSchWakeupS(tp, RDY_OK); - chSysUnlock(); - return tp; -} -#endif /* CH_USE_DYNAMIC && CH_USE_MEMPOOLS */ - -/** - * @brief Changes the running thread priority level then reschedules if - * necessary. - * @note The function returns the real thread priority regardless of the - * current priority that could be higher than the real priority - * because the priority inheritance mechanism. - * - * @param[in] newprio the new priority level of the running thread - * @return The old priority level. - */ -tprio_t chThdSetPriority(tprio_t newprio) { - tprio_t oldprio; - - chDbgCheck((newprio >= LOWPRIO) && (newprio <= HIGHPRIO), - "chThdSetPriority"); - - chSysLock(); -#if CH_USE_MUTEXES - oldprio = currp->p_realprio; - if ((currp->p_prio == currp->p_realprio) || (newprio > currp->p_prio)) - currp->p_prio = newprio; - currp->p_realprio = newprio; -#else - oldprio = currp->p_prio; - currp->p_prio = newprio; -#endif - chSchRescheduleS(); - chSysUnlock(); - return oldprio; -} - -/** - * @brief Resumes a suspended thread. - * @note Use this function to resume threads created with @p chThdInit(). - * - * @param[in] tp pointer to the thread - * @return The pointer to the thread. - */ -Thread *chThdResume(Thread *tp) { - - chSysLock(); - chDbgAssert(tp->p_state == THD_STATE_SUSPENDED, - "chThdResume(), #1", - "thread not in THD_STATE_SUSPENDED state"); - chSchWakeupS(tp, RDY_OK); - chSysUnlock(); - return tp; -} - -/** - * @brief Requests a thread termination. - * @note The thread is not terminated but a termination request is added to - * its @p p_flags field. The thread can read this status by - * invoking @p chThdShouldTerminate() and then terminate cleanly. - * - * @param[in] tp pointer to the thread - */ -void chThdTerminate(Thread *tp) { - - chSysLock(); - tp->p_flags |= THD_TERMINATE; - chSysUnlock(); -} - -/** - * @brief Suspends the invoking thread for the specified time. - * - * @param[in] time the delay in system ticks, the special values are - * handled as follow: - * - @a TIME_INFINITE the thread enters an infinite sleep - * state. - * - @a TIME_IMMEDIATE this value is accepted but - * interpreted as a normal time specification not as an - * immediate timeout specification. - * . - */ -void chThdSleep(systime_t time) { - - chDbgCheck(time != TIME_INFINITE, "chThdSleep"); - - chSysLock(); - chThdSleepS(time); - chSysUnlock(); -} - -/** - * @brief Suspends the invoking thread until the system time arrives to the - * specified value. - * - * @param[in] time absolute system time - */ -void chThdSleepUntil(systime_t time) { - - chSysLock(); - if ((time -= chTimeNow()) > 0) - chThdSleepS(time); - chSysUnlock(); -} - -/** - * @brief Yields the time slot. - * @details Yields the CPU control to the next thread in the ready list with - * equal priority, if any. - */ -void chThdYield(void) { - - chSysLock(); - chSchDoYieldS(); - chSysUnlock(); -} - -/** - * @brief Terminates the current thread by specifying an exit status code. - * - * @param[in] msg thread exit code. The code can be retrieved by using - * @p chThdWait(). - */ -void chThdExit(msg_t msg) { - Thread *tp = currp; - - chSysLock(); - tp->p_u.exitcode = msg; -#if defined(THREAD_EXT_EXIT) - THREAD_EXT_EXIT(tp); -#endif -#if CH_USE_WAITEXIT - while (notempty(&tp->p_waiting)) - chSchReadyI(list_remove(&tp->p_waiting)); -#endif -#if CH_USE_REGISTRY - /* Static threads are immediately removed from the registry because - there is no memory to recover.*/ - if ((tp->p_flags & THD_MEM_MODE_MASK) == THD_MEM_MODE_STATIC) - REG_REMOVE(tp); -#endif - chSchGoSleepS(THD_STATE_FINAL); -} - -#if CH_USE_DYNAMIC || defined(__DOXYGEN__) -/** - * @brief Adds a reference to a thread object. - * - * @param[in] tp pointer to the thread - * @return The same thread pointer passed as parameter - * representing the new reference. - */ -Thread *chThdAddRef(Thread *tp) { - - chSysLock(); - chDbgAssert(tp->p_refs < 255, "chThdAddRef(), #1", "too many references"); - tp->p_refs++; - chSysUnlock(); - return tp; -} - -/** - * @brief Releases a reference to a thread object. - * @details If the references counter reaches zero and the thread - * is in the @p THD_STATE_FINAL state then the thread's memory is - * returned to the proper allocator. - * @note Static threads are not affected. - * - * @param[in] tp pointer to the thread - */ -void chThdRelease(Thread *tp) { - trefs_t refs; - - chSysLock(); - chDbgAssert(tp->p_refs > 0, "chThdRelease(), #1", "not referenced"); - refs = --tp->p_refs; - chSysUnlock(); - - /* If the references counter reaches zero and the thread is in its - terminated state then the memory can be returned to the proper - allocator. Of course static threads are not affected.*/ - if ((refs == 0) && (tp->p_state == THD_STATE_FINAL)) { - switch (tp->p_flags & THD_MEM_MODE_MASK) { -#if CH_USE_HEAP - case THD_MEM_MODE_HEAP: -#if CH_USE_REGISTRY - REG_REMOVE(tp); -#endif - chHeapFree(tp); - break; -#endif -#if CH_USE_MEMPOOLS - case THD_MEM_MODE_MEMPOOL: -#if CH_USE_REGISTRY - REG_REMOVE(tp); -#endif - chPoolFree(tp->p_mpool, tp); - break; -#endif - } - } -} -#endif /* CH_USE_DYNAMIC */ - -#if CH_USE_WAITEXIT || defined(__DOXYGEN__) -/** - * @brief Blocks the execution of the invoking thread until the specified - * thread terminates then the exit code is returned. - * @details This function waits for the specified thread to terminate then - * decrements its reference counter, if the counter reaches zero then - * the thread working area is returned to the proper allocator.
- * The memory used by the exited thread is handled in different ways - * depending on the API that spawned the thread: - * - If the thread was spawned by @p chThdCreateStatic() or by - * @p chThdInit() then nothing happens and the thread working area - * is not released or modified in any way. This is the default, - * totally static, behavior. - * - If the thread was spawned by @p chThdCreateFromHeap() then - * the working area is returned to the system heap. - * - If the thread was spawned by @p chThdCreateFromMemoryPool() - * then the working area is returned to the owning memory pool. - * . - * Please read the @ref article_lifecycle article for more details. - * @note After invoking @p chThdWait() the thread pointer becomes invalid - * and must not be used as parameter for further system calls. - * @note The function is available only if the @p CH_USE_WAITEXIT - * option is enabled in @p chconf.h. - * @note If @p CH_USE_DYNAMIC is not specified this function just waits for - * the thread termination, no memory allocators are involved. - * - * @param[in] tp pointer to the thread - * @return The exit code from the terminated thread. - */ -msg_t chThdWait(Thread *tp) { - msg_t msg; - - chDbgCheck(tp != NULL, "chThdWait"); - - chSysLock(); - chDbgAssert(tp != currp, "chThdWait(), #1", "waiting self"); -#if CH_USE_DYNAMIC - chDbgAssert(tp->p_refs > 0, "chThdWait(), #2", "not referenced"); -#endif - if (tp->p_state != THD_STATE_FINAL) { - list_insert(currp, &tp->p_waiting); - chSchGoSleepS(THD_STATE_WTEXIT); - } - msg = tp->p_u.exitcode; - chSysUnlock(); -#if CH_USE_DYNAMIC - chThdRelease(tp); -#endif - return msg; -} -#endif /* CH_USE_WAITEXIT */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/src/chvt.c b/ChibiOS_2.0.8/os/kernel/src/chvt.c deleted file mode 100644 index 539384b..0000000 --- a/ChibiOS_2.0.8/os/kernel/src/chvt.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file chvt.c - * @brief Time and Virtual Timers related code. - * - * @addtogroup time - * @details Time and Virtual Timers related APIs and services. - * @{ - */ - -#include "ch.h" - -/** - * @brief Virtual timers delta list header. - */ -VTList vtlist; - -/** - * @brief Virtual Timers initialization. - * @note Internal use only. - */ -void vt_init(void) { - - vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist; - vtlist.vt_time = (systime_t)-1; - vtlist.vt_systime = 0; -} - -/** - * @brief Enables a virtual timer. - * @note The associated function is invoked by an interrupt handler within - * the I-Locked state, see @ref system_states. - * - * @param[out] vtp the @p VirtualTimer structure pointer - * @param[in] time the number of time ticks, the value @p TIME_INFINITE - * is notallowed. The value @p TIME_IMMEDIATE is allowed - * but interpreted as a normal time specification not as - * an immediate timeout specification. - * @param[in] vtfunc the timer callback function. After invoking the - * callback the timer is disabled and the structure can - * be disposed or reused. - * @param[in] par a parameter that will be passed to the callback - * function - */ -void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par) { - VirtualTimer *p; - - chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (time != TIME_INFINITE), - "chVTSetI"); - - vtp->vt_par = par; - vtp->vt_func = vtfunc; - p = vtlist.vt_next; - while (p->vt_time < time) { - time -= p->vt_time; - p = p->vt_next; - } - - vtp->vt_prev = (vtp->vt_next = p)->vt_prev; - vtp->vt_prev->vt_next = p->vt_prev = vtp; - vtp->vt_time = time; - if (p != (void *)&vtlist) - p->vt_time -= time; -} - -/** - * @brief Disables a Virtual Timer. - * @note The timer MUST be active when this function is invoked. - * - * @param[in] vtp the @p VirtualTimer structure pointer - */ -void chVTResetI(VirtualTimer *vtp) { - - chDbgCheck(vtp != NULL, "chVTResetI"); - chDbgAssert(vtp->vt_func != NULL, - "chVTResetI(), #1", - "timer not set or already triggered"); - - if (vtp->vt_next != (void *)&vtlist) - vtp->vt_next->vt_time += vtp->vt_time; - vtp->vt_prev->vt_next = vtp->vt_next; - vtp->vt_next->vt_prev = vtp->vt_prev; - vtp->vt_func = (vtfunc_t)NULL; -} - -/** - * @brief Checks if the current system time is within the specified time - * window. - * @note When start==end then the function returns always true because the - * whole time range is specified. - * - * @param[in] start the start of the time window (inclusive) - * @param[in] end the end of the time window (non inclusive) - * @retval TRUE current time within the specified time window. - * @retval FALSE current time not within the specified time window. - */ -bool_t chTimeIsWithin(systime_t start, systime_t end) { - - systime_t time = chTimeNow(); - return end > start ? (time >= start) && (time < end) : - (time >= start) || (time < end); -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/templates/chconf.h b/ChibiOS_2.0.8/os/kernel/templates/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/os/kernel/templates/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/templates/chcore.c b/ChibiOS_2.0.8/os/kernel/templates/chcore.c deleted file mode 100644 index 259bc45..0000000 --- a/ChibiOS_2.0.8/os/kernel/templates/chcore.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chcore.c - * @brief Port related template code. - * @details This file is a template of the system driver functions provided by - * a port. Some of the following functions may be implemented as - * macros in chcore.h if the implementer decides that there is an - * advantage in doing so, as example because performance concerns. - * - * @addtogroup core - * @details Non portable code templates. - * @{ - */ - -#include "ch.h" - -/** - * @brief Port-related initialization code. - * @note This function is usually empty. - */ -void port_init(void) { -} - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform more - * actions. - */ -void port_lock(void) { -} - -/** - * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform more - * actions. - */ -void port_unlock(void) { -} - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - */ -void port_lock_from_isr(void) { -} - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - */ -void port_unlock_from_isr(void) { -} - -/** - * @brief Disables all the interrupt sources. - * @note Of course non maskable interrupt sources are not included. - */ -void port_disable(void) { -} - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - */ -void port_suspend(void) { -} - -/** - * @brief Enables all the interrupt sources. - */ -void port_enable(void) { -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - */ -void port_wait_for_interrupt(void) { -} - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected (as example because a programming - * error in the application code that triggers an assertion while in - * debug mode). - */ -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -void port_switch(Thread *ntp, Thread *otp) { -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/templates/chcore.h b/ChibiOS_2.0.8/os/kernel/templates/chcore.h deleted file mode 100644 index 1581469..0000000 --- a/ChibiOS_2.0.8/os/kernel/templates/chcore.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chcore.h - * @brief Port related template macros and structures. - * @details This file is a template of the system driver macros provided by - * a port. - * - * @addtogroup core - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/** - * @brief Unique macro for the implemented architecture. - */ -#define CH_ARCHITECTURE_XXX - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "" - -/** - * @brief Name of the architecture variant (optional). - */ -#define CH_ARCHITECTURE_VARIANT_NAME "" - -/** - * @brief Base type for stack and memory alignment. - */ -typedef uint8_t stkalign_t; - -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - */ -struct extctx { -}; - -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct intctx { -}; - -/** - * @brief Platform dependent part of the @p Thread structure. - * @details This structure usually contains just the saved stack pointer - * defined as a pointer to a @p intctx structure. - */ -struct context { - struct intctx *sp; -}; - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 0 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 0 -#endif - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - * @note Not all architectures support fast interrupts, in this case this - * macro must be omitted. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -#ifdef __cplusplus -extern "C" { -#endif - void port_init(void); - void port_lock(void); - void port_unlock(void); - void port_lock_from_isr(void); - void port_unlock_from_isr(void); - void port_disable(void); - void port_suspend(void); - void port_enable(void); - void port_wait_for_interrupt(void); - void port_halt(void); - void port_switch(Thread *ntp, Thread *otp); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/kernel/templates/chtypes.h b/ChibiOS_2.0.8/os/kernel/templates/chtypes.h deleted file mode 100644 index d88f9be..0000000 --- a/ChibiOS_2.0.8/os/kernel/templates/chtypes.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chtypes.h - * @brief System types template. - * @details The types defined in this file may change depending on the target - * architecture. You may also try to optimize the size of the various - * types in order to privilege size or performance, be careful in - * doing so. - * - * @addtogroup types - * @details System types and macros. - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#include - -#if !defined(_STDINT_H) && !defined(__STDINT_H_) -#include -#endif - -/** - * @brief Boolean, recommended the fastest signed. - */ -typedef int32_t bool_t; - -/** - * @brief Thread mode flags, uint8_t is ok. - */ -typedef uint8_t tmode_t; - -/** - * @brief Thread state, uint8_t is ok. - */ -typedef uint8_t tstate_t; - -/** - * @brief Thread references counter, uint8_t is ok. - */ -typedef uint8_t trefs_t; - -/** - * @brief Priority, use the fastest unsigned type. - */ -typedef uint32_t tprio_t; - -/** - * @brief Message, use signed pointer equivalent. - */ -typedef int32_t msg_t; - -/** - * @brief Event Id, use fastest signed. - */ -typedef int32_t eventid_t; - -/** - * @brief Event Mask, recommended fastest unsigned. - */ -typedef uint32_t eventmask_t; - -/** - * @brief System Time, recommended fastest unsigned. - */ -typedef uint32_t systime_t; - -/** - * @brief Counter, recommended fastest signed. - */ -typedef int32_t cnt_t; - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note This is required because some compilers require a custom keyword, - * usually this macro is just set to "const" for the GCC compiler. - * @note This macro is not used to place constants in different address - * spaces (like AVR requires as example) because it is assumed that - * a pointer to a ROMCONST constant is compatible with a pointer - * to a normal variable. It is just like the "const" keyword but - * requires that the constant is placed in ROM if the architecture - * supports it. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM/rules.mk b/ChibiOS_2.0.8/os/ports/GCC/ARM/rules.mk deleted file mode 100644 index 50729f0..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM/rules.mk +++ /dev/null @@ -1,146 +0,0 @@ -# ARM7 common makefile scripts and rules. - -# Output -OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp -ifeq ($(BUILDDIR),) - BUILDDIR = . - CLEANDIR = -else - CLEANDIR = $(BUILDDIR) -endif -ENSUREBUILDDIR = $(shell test -d $(BUILDDIR) || mkdir $(BUILDDIR)) - -# Automatic compiler options -OPT = $(USE_OPT) -CPPOPT = $(USE_CPPOPT) -ifeq ($(USE_CURRP_CACHING),yes) - OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' -endif -ifeq ($(USE_LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -# Source files groups -ifeq ($(USE_THUMB),yes) - TCSRC += $(CSRC) - TCPPSRC += $(CPPSRC) -else - ACSRC += $(CSRC) - ACPPSRC += $(CPPSRC) -endif -ASRC = $(ACSRC)$(ACPPSRC) -TSRC = $(TCSRC)$(TCPPSRC) -SRC = $(ASRC)$(TSRC) - -# Object files groups -ACOBJS = $(ACSRC:.c=.o) -ACPPOBJS = $(ACPPSRC:.cpp=.o) -TCOBJS = $(TCSRC:.c=.o) -TCPPOBJS = $(TCPPSRC:.cpp=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) - -# Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) - -# Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) - -# Libs -LIBS = $(DLIBS) $(ULIBS) - -# Various settings -MCFLAGS = -mcpu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) -ifeq ($(USE_LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CFLAGS += -DTHUMB_PRESENT - CPPFLAGS += -DTHUMB_PRESENT - ASFLAGS += -DTHUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB mode. - CFLAGS += -mthumb-interwork - CPPFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb - LDFLAGS += -mno-thumb-interwork -mthumb - endif -else - # Pure ARM mode - CFLAGS += -mno-thumb-interwork - CPPFLAGS += -mno-thumb-interwork - ASFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CFLAGS += -MD -MP -MF .dep/$(@F).d -CPPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(ENSUREBUILDDIR) $(OBJS) $(OUTFILES) - -$(ACPPOBJS) : %.o : %.cpp - @echo - $(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ - -$(TCPPOBJS) : %.o : %.cpp - @echo - $(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ - -$(ACOBJS) : %.o : %.c - @echo - $(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ - -$(TCOBJS) : %.o : %.c - @echo - $(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(ACSRC:.c=.lst) $(TCSRC:.c=.lst) $(ACPPSRC:.cpp=.lst) $(TCPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst) - -rm -f $(OUTFILES) $(BUILDDIR)/$(PROJECT).map - -rm -fR .dep $(CLEANDIR) - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/AT91SAM7/vectors.s b/ChibiOS_2.0.8/os/ports/GCC/ARM7/AT91SAM7/vectors.s deleted file mode 100644 index 0bfb954..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/AT91SAM7/vectors.s +++ /dev/null @@ -1,81 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -.section vectors -.code 32 -.balign 4 -/* - * System entry points. - */ -_start: - ldr pc, _reset - ldr pc, _undefined - ldr pc, _swi - ldr pc, _prefetch - ldr pc, _abort - nop - ldr pc, [pc,#-0xF20] /* AIC - AIC_IVR */ - ldr pc, [pc,#-0xF20] /* AIC - AIC_FVR */ - -_reset: - .word ResetHandler /* In crt0.s */ -_undefined: - .word UndHandler -_swi: - .word SwiHandler -_prefetch: - .word PrefetchHandler -_abort: - .word AbortHandler - .word 0 - .word 0 - .word 0 - -.text -.code 32 -.balign 4 - -/* - * Default exceptions handlers. The handlers are declared weak in order to be - * replaced by the real handling code. Everything is defaulted to an infinite - * loop. - */ -.weak UndHandler -UndHandler: - -.weak SwiHandler -SwiHandler: - -.weak PrefetchHandler -PrefetchHandler: - -.weak AbortHandler -AbortHandler: - -.weak FiqHandler -FiqHandler: - -.loop: b .loop diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/AT91SAM7/wfi.h b/ChibiOS_2.0.8/os/ports/GCC/ARM7/AT91SAM7/wfi.h deleted file mode 100644 index 4edcefc..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/AT91SAM7/wfi.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _WFI_H_ -#define _WFI_H_ - -#include "board.h" - -#ifndef port_wait_for_interrupt -#if ENABLE_WFI_IDLE != 0 -#define port_wait_for_interrupt() { \ - AT91C_BASE_SYS->PMC_SCDR = AT91C_PMC_PCK; \ -} -#else -#define port_wait_for_interrupt() -#endif -#endif - -#endif /* _WFI_H_ */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/LPC214x/vectors.s b/ChibiOS_2.0.8/os/ports/GCC/ARM7/LPC214x/vectors.s deleted file mode 100644 index b340523..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/LPC214x/vectors.s +++ /dev/null @@ -1,78 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -.section vectors -.code 32 -.balign 4 -/* - * System entry points. - */ -_start: - ldr pc, _reset - ldr pc, _undefined - ldr pc, _swi - ldr pc, _prefetch - ldr pc, _abort - nop - ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ - ldr pc, _fiq - -_reset: - .word ResetHandler /* In crt0.s */ -_undefined: - .word UndHandler -_swi: - .word SwiHandler -_prefetch: - .word PrefetchHandler -_abort: - .word AbortHandler -_fiq: - .word FiqHandler - .word 0 - .word 0 - -/* - * Default exceptions handlers. The handlers are declared weak in order to be - * replaced by the real handling code. Everything is defaulted to an infinite - * loop. - */ -.weak UndHandler -UndHandler: - -.weak SwiHandler -SwiHandler: - -.weak PrefetchHandler -PrefetchHandler: - -.weak AbortHandler -AbortHandler: - -.weak FiqHandler -FiqHandler: - -.loop: b .loop diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/LPC214x/wfi.h b/ChibiOS_2.0.8/os/ports/GCC/ARM7/LPC214x/wfi.h deleted file mode 100644 index 1693e55..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/LPC214x/wfi.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _WFI_H_ -#define _WFI_H_ - -#include "lpc214x.h" - -#ifndef port_wait_for_interrupt -#if ENABLE_WFI_IDLE != 0 -#define port_wait_for_interrupt() { \ - PCON = 1; \ -} -#else -#define port_wait_for_interrupt() -#endif -#endif - -#endif /* _WFI_H_ */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcore.c b/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcore.c deleted file mode 100644 index 905b8cf..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcore.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARM7/chcore.c - * @brief ARM7 architecture port code. - * - * @addtogroup ARM7_CORE - * @{ - */ - -#include "ch.h" - -/** - * Halts the system. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcore.h b/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcore.h deleted file mode 100644 index 0d883ca..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcore.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARM7/chcore.h - * @brief ARM7 architecture port macros and structures. - * - * @addtogroup ARM7_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/** - * @brief If enabled allows the idle thread to enter a low power mode. - */ -#ifndef ENABLE_WFI_IDLE -#define ENABLE_WFI_IDLE 0 -#endif -#include - -/** - * @brief Macro defining the ARM7 architecture. - */ -#define CH_ARCHITECTURE_ARM7 - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "ARM" - -/** - * @brief Name of the architecture variant (optional). - */ -#define CH_CORE_VARIANT_NAME "ARM7TDMI" - -/** - * @brief 32 bits stack and memory alignment enforcement. - */ -typedef uint32_t stkalign_t; - -/** - * @brief Generic ARM register. - */ -typedef void *regarm_t; - -#if !defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - */ -struct extctx { - regarm_t spsr_irq; - regarm_t lr_irq; - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_usr; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct intctx { - regarm_t r4; - regarm_t r5; - regarm_t r6; -#ifndef CH_CURRP_REGISTER_CACHE - regarm_t r7; -#endif - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief Platform dependent part of the @p Thread structure. - * @details In the ARM7 port this structure just holds a pointer to the - * @p intctx structure representing the stack pointer at the time - * of the context switch. - */ -struct context { - struct intctx *r13; -}; -#endif - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = _port_thread_start; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - * @note In this port it is set to 4 because the idle thread does have - * a stack frame when compiling without optimizations. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 4 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - * @note In this port 0x10 is a safe value, it can be reduced after careful - * analysis of the generated code. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 0x10 -#endif - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - * @note This macro has a different implementation depending if compiled in - * ARM or THUMB mode. - * @note The THUMB implementation starts with ARM code because interrupt - * vectors are always invoked in ARM mode regardless the bit 0 - * value. The switch in THUMB mode is done in the function prologue so - * it is transparent to the user code. - */ -#ifdef THUMB -#define PORT_IRQ_PROLOGUE() { \ - asm volatile (".code 32 \n\t" \ - "stmfd sp!, {r0-r3, r12, lr} \n\t" \ - "add r0, pc, #1 \n\t" \ - "bx r0 \n\t" \ - ".code 16" : : : "memory"); \ -} -#else /* !THUMB */ -#define PORT_IRQ_PROLOGUE() { \ - asm volatile ("stmfd sp!, {r0-r3, r12, lr}" : : : "memory"); \ -} -#endif /* !THUMB */ - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - * @note This macro has a different implementation depending if compiled in - * ARM or THUMB mode. - */ -#ifdef THUMB -#define PORT_IRQ_EPILOGUE() { \ - asm volatile ("ldr r0, =_port_irq_common \n\t" \ - "bx r0" : : : "memory"); \ -} -#else /* !THUMB */ -#define PORT_IRQ_EPILOGUE() { \ - asm volatile ("b _port_irq_common" : : : "memory"); \ -} -#endif /* !THUMB */ - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) __attribute__((naked)) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) \ - __attribute__((interrupt("FIQ"))) void id(void) - -/** - * @brief Port-related initialization code. - * @note This function is empty in this port. - */ -#define port_init() - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - * @note In this port it disables the IRQ sources and keeps FIQ sources - * enabled. - */ -#ifdef THUMB -#define port_lock() { \ - asm volatile ("bl _port_lock_thumb" : : : "r3", "lr", "memory"); \ -} -#else /* !THUMB */ -#define port_lock() asm volatile ("msr CPSR_c, #0x9F" : : : "memory") -#endif /* !THUMB */ - -/** - * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - * @note In this port it enables both the IRQ and FIQ sources. - */ -#ifdef THUMB -#define port_unlock() { \ - asm volatile ("bl _port_unlock_thumb" : : : "r3", "lr", "memory"); \ -} -#else /* !THUMB */ -#define port_unlock() asm volatile ("msr CPSR_c, #0x1F" : : : "memory") -#endif /* !THUMB */ - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note Empty in this port. - */ -#define port_lock_from_isr() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note Empty in this port. - */ -#define port_unlock_from_isr() - -/** - * @brief Disables all the interrupt sources. - * @note Of course non maskable interrupt sources are not included. - * @note In this port it disables both the IRQ and FIQ sources. - * @note Implements a workaround for spurious interrupts taken from the NXP - * LPC214x datasheet. - */ -#ifdef THUMB -#define port_disable() { \ - asm volatile ("bl _port_disable_thumb" : : : "r3", "lr", "memory"); \ -} -#else /* !THUMB */ -#define port_disable() { \ - asm volatile ("mrs r3, CPSR \n\t" \ - "orr r3, #0x80 \n\t" \ - "msr CPSR_c, r3 \n\t" \ - "orr r3, #0x40 \n\t" \ - "msr CPSR_c, r3" : : : "r3", "memory"); \ -} -#endif /* !THUMB */ - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note In this port it disables the IRQ sources and enables the - * FIQ sources. - */ -#ifdef THUMB -#define port_suspend() { \ - asm volatile ("bl _port_suspend_thumb" : : : "r3", "lr", "memory"); \ -} -#else /* !THUMB */ -#define port_suspend() asm volatile ("msr CPSR_c, #0x9F" : : : "memory") -#endif /* !THUMB */ - -/** - * @brief Enables all the interrupt sources. - * @note In this port it enables both the IRQ and FIQ sources. - */ -#ifdef THUMB -#define port_enable() { \ - asm volatile ("bl _port_enable_thumb" : : : "r3", "lr", "memory"); \ -} -#else /* !THUMB */ -#define port_enable() asm volatile ("msr CPSR_c, #0x1F" : : : "memory") -#endif /* !THUMB */ - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * @note Implemented as inlined code for performance reasons. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#ifdef THUMB -#if CH_DBG_ENABLE_STACK_CHECK -#define port_switch(ntp, otp) { \ - register Thread *_ntp asm ("r0") = (ntp); \ - register Thread *_otp asm ("r1") = (otp); \ - register char *sp asm ("sp"); \ - if (sp - sizeof(struct intctx) - sizeof(Thread) < (char *)_otp) \ - asm volatile ("mov r0, #0 \n\t" \ - "ldr r1, =chDbgPanic \n\t" \ - "bx r1"); \ - _port_switch_thumb(_ntp, _otp); \ -} -#else /* !CH_DBG_ENABLE_STACK_CHECK */ -#define port_switch(ntp, otp) _port_switch_thumb(ntp, otp) -#endif /* !CH_DBG_ENABLE_STACK_CHECK */ -#else /* !THUMB */ -#if CH_DBG_ENABLE_STACK_CHECK -#define port_switch(ntp, otp) { \ - register Thread *_ntp asm ("r0") = (ntp); \ - register Thread *_otp asm ("r1") = (otp); \ - register char *sp asm ("sp"); \ - if (sp - sizeof(struct intctx) - sizeof(Thread) < (char *)_otp) \ - asm volatile ("mov r0, #0 \n\t" \ - "b chDbgPanic"); \ - _port_switch_arm(_ntp, _otp); \ -} -#else /* !CH_DBG_ENABLE_STACK_CHECK */ -#define port_switch(ntp, otp) _port_switch_arm(ntp, otp) -#endif /* !CH_DBG_ENABLE_STACK_CHECK */ -#endif /* !THUMB */ - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); -#ifdef THUMB - void _port_switch_thumb(Thread *ntp, Thread *otp); -#else /* !THUMB */ - void _port_switch_arm(Thread *ntp, Thread *otp); -#endif /* !THUMB */ - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcoreasm.s b/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcoreasm.s deleted file mode 100644 index 3c63e1b..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/chcoreasm.s +++ /dev/null @@ -1,244 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARM7/chcoreasm.s - * @brief ARM7 architecture port low level code. - * - * @addtogroup ARM7_CORE - * @{ - */ - -#include "chconf.h" - -#if !defined(__DOXYGEN__) - -.set MODE_USR, 0x10 -.set MODE_FIQ, 0x11 -.set MODE_IRQ, 0x12 -.set MODE_SVC, 0x13 -.set MODE_ABT, 0x17 -.set MODE_UND, 0x1B -.set MODE_SYS, 0x1F - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.text - -/* - * Interrupt enable/disable functions, only present if there is THUMB code in - * the system because those are inlined in ARM code. - */ -#ifdef THUMB_PRESENT -.balign 16 -.code 16 -.thumb_func -.global _port_disable_thumb -_port_disable_thumb: - mov r3, pc - bx r3 -.code 32 - mrs r3, CPSR - orr r3, #I_BIT - msr CPSR_c, r3 - orr r3, #F_BIT - msr CPSR_c, r3 - bx lr - -.balign 16 -.code 16 -.thumb_func -.global _port_suspend_thumb -_port_suspend_thumb: -.thumb_func -.global _port_lock_thumb -_port_lock_thumb: - mov r3, pc - bx r3 -.code 32 - msr CPSR_c, #MODE_SYS | I_BIT - bx lr - -.balign 16 -.code 16 -.thumb_func -.global _port_enable_thumb -_port_enable_thumb: -.thumb_func -.global _port_unlock_thumb -_port_unlock_thumb: - mov r3, pc - bx r3 -.code 32 - msr CPSR_c, #MODE_SYS - bx lr - -#endif - -.balign 16 -#ifdef THUMB_PRESENT -.code 16 -.thumb_func -.global _port_switch_thumb -_port_switch_thumb: - mov r2, pc - bx r2 - // Jumps into _port_switch_arm in ARM mode -#endif -.code 32 -.global _port_switch_arm -_port_switch_arm: -#ifdef CH_CURRP_REGISTER_CACHE - stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - str sp, [r1, #12] - ldr sp, [r0, #12] -#ifdef THUMB_PRESENT - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - bx lr -#else /* !THUMB_PRESENT */ - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} -#endif /* !THUMB_PRESENT */ -#else /* !CH_CURRP_REGISTER_CACHE */ - stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - str sp, [r1, #12] - ldr sp, [r0, #12] -#ifdef THUMB_PRESENT - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - bx lr -#else /* !THUMB_PRESENT */ - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} -#endif /* !THUMB_PRESENT */ -#endif /* !CH_CURRP_REGISTER_CACHE */ - -/* - * Common exit point for all IRQ routines, it performs the rescheduling if - * required. - * System stack frame structure after a context switch in the - * interrupt handler: - * - * High +------------+ - * | LR_USR | -+ - * | R12 | | - * | R3 | | - * | R2 | | External context: IRQ handler frame - * | R1 | | - * | R0 | | - * | PC | | (user code return address) - * | PSR_USR | -+ (user code status) - * | .... | <- mk_DoRescheduleI() stack frame, optimize it for space - * | LR | -+ (system code return address) - * | R11 | | - * | R10 | | - * | R9 | | - * | R8 | | Internal context: mk_SwitchI() frame - * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) - * | R6 | | - * | R5 | | - * SP-> | R4 | -+ - * Low +------------+ - */ -.balign 16 -#ifdef THUMB_NO_INTERWORKING -.code 16 -.thumb_func -.globl _port_irq_common -_port_irq_common: - bl chSchIsRescRequiredExI - mov lr, pc - bx lr -.code 32 -#else /* !THUMB_NO_INTERWORKING */ -.code 32 -.globl _port_irq_common -_port_irq_common: - bl chSchIsRescRequiredExI -#endif /* !THUMB_NO_INTERWORKING */ - cmp r0, #0 // Simply returns if a - ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not - subeqs pc, lr, #4 // required. - - // Saves the IRQ mode registers in the system stack. - ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack. - msr CPSR_c, #MODE_IRQ | I_BIT - mrs r0, SPSR - mov r1, lr - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. - - // Context switch. -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl chSchDoRescheduleI - mov lr, pc - bx lr -.code 32 -#else /* !THUMB_NO_INTERWORKING */ - bl chSchDoRescheduleI -#endif /* !THUMB_NO_INTERWORKING */ - - // Re-establish the IRQ conditions again. - ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. - msr CPSR_c, #MODE_IRQ | I_BIT - msr SPSR_fsxc, r0 - mov lr, r1 - msr CPSR_c, #MODE_SYS | I_BIT - ldmfd sp!, {r0-r3, r12, lr} - msr CPSR_c, #MODE_IRQ | I_BIT - subs pc, lr, #4 - -/* - * Threads trampoline code. - * NOTE: The threads always start in ARM mode then switch to the thread-function mode. - */ -.balign 16 -.code 32 -.globl _port_thread_start -_port_thread_start: - msr CPSR_c, #MODE_SYS -#ifndef THUMB_NO_INTERWORKING - mov r0, r5 - mov lr, pc - bx r4 - bl chThdExit -#else /* !THUMB_NO_INTERWORKING */ - add r0, pc, #1 - bx r0 -.code 16 - mov r0, r5 - bl jmpr4 - bl chThdExit -jmpr4: - bx r4 -#endif /* !THUMB_NO_INTERWORKING */ - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/chtypes.h b/ChibiOS_2.0.8/os/ports/GCC/ARM7/chtypes.h deleted file mode 100644 index 9f1b2a3..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/chtypes.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARM7/chtypes.h - * @brief ARM7 architecture port system types. - * - * @addtogroup ARM7_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#define __need_ptrdiff_t -#include - -#if !defined(_STDINT_H) && !defined(__STDINT_H_) -#include -#endif - -typedef int32_t bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Event Id. */ -typedef uint32_t eventmask_t; /**< Events mask. */ -typedef uint32_t systime_t; /**< System time. */ -typedef int32_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note It uses the "packed" GCC attribute. - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/crt0.s b/ChibiOS_2.0.8/os/ports/GCC/ARM7/crt0.s deleted file mode 100644 index 8cb0b06..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/crt0.s +++ /dev/null @@ -1,191 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARM7/crt0.s - * @brief Generic ARM7 startup file for ChibiOS/RT. - * - * @addtogroup ARM7_CORE - * @{ - */ - -#if !defined(__DOXYGEN__) - -.set MODE_USR, 0x10 -.set MODE_FIQ, 0x11 -.set MODE_IRQ, 0x12 -.set MODE_SVC, 0x13 -.set MODE_ABT, 0x17 -.set MODE_UND, 0x1B -.set MODE_SYS, 0x1F - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.text -.code 32 -.balign 4 - -/* - * Reset handler. - */ -.global ResetHandler -ResetHandler: - /* - * Stack pointers initialization. - */ - ldr r0, =__ram_end__ - /* Undefined */ - msr CPSR_c, #MODE_UND | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__und_stack_size__ - sub r0, r0, r1 - /* Abort */ - msr CPSR_c, #MODE_ABT | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__abt_stack_size__ - sub r0, r0, r1 - /* FIQ */ - msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__fiq_stack_size__ - sub r0, r0, r1 - /* IRQ */ - msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__irq_stack_size__ - sub r0, r0, r1 - /* Supervisor */ - msr CPSR_c, #MODE_SVC | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__svc_stack_size__ - sub r0, r0, r1 - /* System */ - msr CPSR_c, #MODE_SYS | I_BIT | F_BIT - mov sp, r0 -// ldr r1, =__sys_stack_size__ -// sub r0, r0, r1 - /* - * Early initialization. - */ -#ifndef THUMB_NO_INTERWORKING - bl hwinit0 -#else - add r0, pc, #1 - bx r0 -.code 16 - bl hwinit0 - mov r0, pc - bx r0 -.code 32 -#endif - /* - * Data initialization. - * NOTE: It assumes that the DATA size is a multiple of 4. - */ - ldr r1, =_textdata - ldr r2, =_data - ldr r3, =_edata -dataloop: - cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo dataloop - /* - * BSS initialization. - * NOTE: It assumes that the BSS size is a multiple of 4. - */ - mov r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -bssloop: - cmp r1, r2 - strlo r0, [r1], #4 - blo bssloop - /* - * Late initialization. - */ -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl hwinit1 - mov r0, #0 - mov r1, r0 - bl main - ldr r1, =MainExitHandler - bx r1 -.code 32 -#else - bl hwinit1 - mov r0, #0 - mov r1, r0 - bl main - b MainExitHandler -#endif - -/* - * Default main function exit handler. - */ -.weak MainExitHandler -.globl MainExitHandler -MainExitHandler: - -.loop: b .loop - -/* - * Default early initialization code. It is declared weak in order to be - * replaced by the real initialization code. - * Early initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -#ifdef THUMB_NO_INTERWORKING -.thumb_func -.code 16 -#endif -.weak hwinit0 -hwinit0: - bx lr -.code 32 - -/* - * Default late initialization code. It is declared weak in order to be - * replaced by the real initialization code. - * Late initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -#ifdef THUMB_NO_INTERWORKING -.thumb_func -.code 16 -#endif -.weak hwinit1 -hwinit1: - bx lr -.code 32 - -#endif - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/port.dox b/ChibiOS_2.0.8/os/ports/GCC/ARM7/port.dox deleted file mode 100644 index e92332c..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/port.dox +++ /dev/null @@ -1,225 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup ARM7 ARM7TDMI - * @details The ARM7 architecture is quite complex for a microcontroller and - * some explanations are required about the port choices. - * - * @section ARM7_NOTES The ARM7 modes - * The ARM7 port supports three modes: - * - Pure ARM mode, this is the preferred mode for code speed. The code size - * is larger however. This mode is enabled when all the modules are compiled - * in ARM mode, see the Makefiles. - * - Pure THUMB mode, this is the preferred mode for code size. In this mode - * the execution speed is slower than the ARM mode. This mode is enabled - * when all the modules are compiled in THUMB mode, see the Makefiles. - * - Interworking mode, when in the system there are ARM modules mixed with - * THUMB modules then the interworking compiler option is enabled. This is - * usually the slowest mode and the code size is not as good as in pure - * THUMB mode. - * . - * @section ARM7_STATES Mapping of the System States in the ARM7 port - * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM7 - * port: - * - Init. This state is represented by the startup code and the - * initialization code before @p chSysInit() is executed. It has not a - * special hardware state associated, usually the CPU goes through several - * hardware states during the startup phase. - * - Normal. This is the state the system has after executing - * @p chSysInit(). In this state the ARM7TDMI has both the interrupt sources - * (IRQ and FIQ) enabled and is running in ARM System Mode. - * - Suspended. In this state the IRQ sources are disabled but the FIQ - * sources are served, the core is running in ARM System Mode. - * - Disabled. Both the IRQ and FIQ sources are disabled, the core is - * running in ARM System Mode. - * - Sleep. The ARM7 code does not have any built-in low power mode but - * there are clock stop modes implemented in custom ways by the various - * silicon vendors. This state is implemented in each microcontroller support - * code in a different way, the core is running (or freezed...) in ARM - * System Mode. - * - S-Locked. IRQ sources disabled, core running in ARM System Mode. - * - I-Locked. IRQ sources disabled, core running in ARM IRQ Mode. Note - * that this state is not different from the SRI state in this port, the - * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in - * order to formally change state because this may change). - * - Serving Regular Interrupt. IRQ sources disabled, core running in - * ARM IRQ Mode. See also the I-Locked state. - * - Serving Fast Interrupt. IRQ and FIQ sources disabled, core running - * in ARM FIQ Mode. - * - Serving Non-Maskable Interrupt. There are no asynchronous NMI - * sources in ARM7 architecture but synchronous SVC, ABT and UND exception - * handlers can be seen as belonging to this category. - * - Halted. Implemented as an infinite loop after disabling both IRQ - * and FIQ sources. The ARM state is whatever the processor was running when - * @p chSysHalt() was invoked. - * . - * @section ARM7_NOTES The ARM7 port notes - * The ARM7 port makes some assumptions on the application code organization: - * - The @p main() function is invoked in system mode. - * - Each thread has a private user/system stack, the system has a single - * interrupt stack where all the interrupts are processed. - * - The threads are started in system mode. - * - The threads code can run in system mode or user mode, however the - * code running in user mode cannot invoke the ChibiOS/RT APIs directly - * because privileged instructions are used inside.
- * The kernel APIs can be eventually invoked by using a SWI entry point - * that handles the switch in system mode and the return in user mode. - * - Other modes are not preempt-able because the system code assumes the - * threads running in system mode. When running in supervisor or other - * modes make sure that the interrupts are globally disabled. - * - Interrupts nesting is not supported in the ARM7 code because their - * implementation, even if possible, is not really efficient in this - * architecture. - * - FIQ sources can preempt the kernel (by design) so it is not possible to - * invoke the kernel APIs from inside a FIQ handler. FIQ handlers are not - * affected by the kernel activity so there is not added jitter. - * . - * @section ARM7_IH ARM7 Interrupt Handlers - * ARM7 Interrupt handlers do not save function-saved registers so you need to - * make sure your code saves them or does not use them (this happens - * because in the ARM7 port all the OS interrupt handler functions are declared - * naked).
- * Function-trashed registers (R0-R3, R12, LR, SR) are saved/restored by the - * system macros @p CH_IRQ_PROLOGUE() and @p CH_IRQ_EPILOGUE().
- * The easiest way to ensure this is to just invoke a normal function from - * within the interrupt handler, the function code will save all the required - * registers.
- * Example: - * @code - * CH_IRQ_HANDLER(irq_handler) { - * CH_IRQ_PROLOGUE(); - * - * serve_interrupt(); - * - * VICVectAddr = 0; // This is LPC214x-specific. - * CH_IRQ_EPILOGUE(); - * } - * @endcode - * This is not a bug but an implementation choice, this solution allows to - * have interrupt handlers compiled in thumb mode without have to use an - * interworking mode (the mode switch is hidden in the macros), this - * greatly improves code efficiency and size. You can look at the serial - * driver for real examples of interrupt handlers.
- * It is important that the serve_interrupt() interrupt function is not - * inlined by the compiler into the ISR or the code could still modify - * the unsaved registers, this can be accomplished using GCC by adding - * the attribute "noinline" to the function: - * @code - * #if defined(__GNUC__) - * __attribute__((noinline)) - * #endif - * static void serve_interrupt(void) { - * } - * @endcode - * Note that several commercial compilers support a GNU-like functions - * attribute mechanism.
- * Alternative ways are to use an appropriate pragma directive or disable - * inlining optimizations in the modules containing the interrupt handlers. - * - * @ingroup ports - */ - -/** - * @defgroup ARM7_CONF Configuration Options - * @brief ARM7 specific configuration options. - * @details The ARM7 port allows some architecture-specific configurations - * settings that can be overridden by redefining them in @p chconf.h. - * Usually there is no need to change the default values. - * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used - * by an interrupt handler between the @p extctx and @p intctx - * structures.
- * In practice this value is the stack space used by the chSchDoReschedule() - * stack frame.
- * This value can be affected by a variety of external things like compiler - * version, compiler options, kernel settings (speed/size) and so on.
- * The default for this value is @p 0x10 which should be a safe value, you - * can trim this down by defining the macro externally. This would save - * some valuable RAM space for each thread present in the system.
- * The default value is set into ./os/ports/GCC/ARM7/chcore.h. - * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE - * thread. Usually there is no need to change this value unless inserting - * code in the IDLE thread hook macro. - * . - * @ingroup ARM7 - */ - -/** - * @defgroup ARM7_CORE Core Port Implementation - * @brief ARM7 specific port code, structures and macros. - * - * @ingroup ARM7 - * @file ARM7/chtypes.h Port types. - * @file ARM7/chcore.h Port related structures and macros. - * @file ARM7/chcore.c Port related code. - */ - -/** - * @defgroup ARM7_STARTUP Startup Support - * @brief ARM7 startup code support. - * @details ChibiOS/RT provides its own generic startup file for the ARM7 port. - * Of course it is not mandatory to use it but care should be taken about the - * startup phase details. - * - *

Startup Process

- * The startup process, as implemented, is the following: - * -# The stacks are initialized by assigning them the sizes defined in the - * linker script (usually named @p ch.ld). Stack areas are allocated from - * the highest RAM location downward. - * -# The ARM state is switched to System with both IRQ and FIQ sources - * disabled. - * -# An early initialization routine @p hwinit0 is invoked, if the symbol is - * not defined then an empty default routine is executed (weak symbol). - * -# DATA and BSS segments are initialized. - * -# A late initialization routine @p hwinit1 is invoked, if the symbol not - * defined then an empty default routine is executed (weak symbol).
- * This late initialization function is also the proper place for a - * @a bootloader, if your application requires one. - * -# The @p main() function is invoked with the parameters @p argc and @p argv - * set to zero. - * -# Should the @p main() function return a branch is performed to the weak - * symbol MainExitHandler. The default code is an endless empty loop. - * . - *

Expected linker symbols

- * The startup code starts at the symbol @p ResetHandler and expects the - * following symbols to be defined in the linker script: - * - @p __ram_end__ RAM end location +1. - * - @p __und_stack_size__ Undefined Instruction stack size. - * - @p __abt_stack_size__ Memory Abort stack size. - * - @p __fiq_stack_size__ FIQ service stack size. - * - @p __irq_stack_size__ IRQ service stack size. - * - @p __svc_stack_size__ SVC service stack size. - * - @p __sys_stack_size__ System/User stack size. This is the stack area used - * by the @p main() function. - * - @p _textdata address of the data segment source read only data. - * - @p _data data segment start location. - * - @p _edata data segment end location +1. - * - @p _bss_start BSS start location. - * - @p _bss_end BSS end location +1. - * . - * @ingroup ARM7 - * @file ARM7/crt0.s Startup code. - */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARM7/port.mk b/ChibiOS_2.0.8/os/ports/GCC/ARM7/port.mk deleted file mode 100644 index 1bd2c30..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARM7/port.mk +++ /dev/null @@ -1,7 +0,0 @@ -# List of the ChibiOS/RT ARM7 port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/ARM7/chcore.c - -PORTASM = ${CHIBIOS}/os/ports/GCC/ARM7/crt0.s \ - ${CHIBIOS}/os/ports/GCC/ARM7/chcoreasm.s - -PORTINC = ${CHIBIOS}/os/ports/GCC/ARM7 diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h deleted file mode 100644 index a210bac..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/LPC11xx/cmparams.h - * @brief ARM Cortex-M0 LPC11xx Specific Parameters. - * - * @defgroup ARMCMx_LPC11xx LPC11xx Specific Parameters - * @ingroup ARMCMx - * @details This file contains the Cortex-M0 specific parameters for the - * LPC11xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL CORTEX_M0 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU FALSE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 2 - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/port.mk b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/port.mk deleted file mode 100644 index d360b42..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/port.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS/RT Cortex-M0 LPC11xx port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm0.c - -PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s - -PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/vectors.s b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/vectors.s deleted file mode 100644 index 29bc8e3..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC11xx/vectors.s +++ /dev/null @@ -1,219 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -.syntax unified -.thumb - -.section vectors -_vectors: - .word __ram_end__ - .word ResetHandler - .word NMIVector - .word HardFaultVector - .word MemManageVector - .word BusFaultVector - .word UsageFaultVector - .word Vector1C - .word Vector20 - .word Vector24 - .word Vector28 - .word SVCallVector - .word DebugMonitorVector - .word Vector34 - .word PendSVVector - .word SysTickVector - .word Vector40 - .word Vector44 - .word Vector48 - .word Vector4C - .word Vector50 - .word Vector54 - .word Vector58 - .word Vector5C - .word Vector60 - .word Vector64 - .word Vector68 - .word Vector6C - .word Vector70 - .word Vector74 - .word Vector78 - .word Vector7C - .word Vector80 - .word Vector84 - .word Vector88 - .word Vector8C - .word Vector90 - .word Vector94 - .word Vector98 - .word Vector9C - .word VectorA0 - .word VectorA4 - .word VectorA8 - .word VectorAC - .word VectorB0 - .word VectorB4 - .word VectorB8 - .word VectorBC - -.weak NMIVector -NMIVector: - -.weak HardFaultVector -HardFaultVector: - -.weak MemManageVector -MemManageVector: - -.weak BusFaultVector -BusFaultVector: - -.weak UsageFaultVector -UsageFaultVector: - -.weak Vector1C -Vector1C: - -.weak Vector20 -Vector20: - -.weak Vector24 -Vector24: - -.weak Vector28 -Vector28: - -.weak SVCallVector -SVCallVector: - -.weak DebugMonitorVector -DebugMonitorVector: - -.weak Vector34 -Vector34: - -.weak PendSVVector -PendSVVector: - -.weak SysTickVector -SysTickVector: - -.weak Vector40 -Vector40: - -.weak Vector44 -Vector44: - -.weak Vector48 -Vector48: - -.weak Vector4C -Vector4C: - -.weak Vector50 -Vector50: - -.weak Vector54 -Vector54: - -.weak Vector58 -Vector58: - -.weak Vector5C -Vector5C: - -.weak Vector60 -Vector60: - -.weak Vector64 -Vector64: - -.weak Vector68 -Vector68: - -.weak Vector6C -Vector6C: - -.weak Vector70 -Vector70: - -.weak Vector74 -Vector74: - -.weak Vector78 -Vector78: - -.weak Vector7C -Vector7C: - -.weak Vector80 -Vector80: - -.weak Vector84 -Vector84: - -.weak Vector88 -Vector88: - -.weak Vector8C -Vector8C: - -.weak Vector90 -Vector90: - -.weak Vector94 -Vector94: - -.weak Vector98 -Vector98: - -.weak Vector9C -Vector9C: - -.weak VectorA0 -VectorA0: - -.weak VectorA4 -VectorA4: - -.weak VectorA8 -VectorA8: - -.weak VectorAC -VectorAC: - -.weak VectorB0 -VectorB0: - -.weak VectorB4 -VectorB4: - -.weak VectorB8 -VectorB8: - -.weak VectorBC -VectorBC: - -here: b here diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h deleted file mode 100644 index 80d9d3c..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/LPC13xx/cmparams.h - * @brief ARM Cortex-M3 LPC13xx Specific Parameters. - * - * @defgroup ARMCMx_LPC13xx LPC13xx Specific Parameters - * @ingroup ARMCMx - * @details This file contains the Cortex-M3 specific parameters for the - * LPC13xx platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL CORTEX_M3 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU FALSE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 3 - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/port.mk b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/port.mk deleted file mode 100644 index 115bb30..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/port.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS/RT Cortex-M0 LPC13xx port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm3.c - -PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s - -PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/vectors.s b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/vectors.s deleted file mode 100644 index 397d68a..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/LPC13xx/vectors.s +++ /dev/null @@ -1,315 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -.syntax unified -.thumb - -.section vectors -_vectors: - .word __ram_end__ - .word ResetHandler - .word NMIVector - .word HardFaultVector - .word MemManageVector - .word BusFaultVector - .word UsageFaultVector - .word Vector1C - .word Vector20 - .word Vector24 - .word Vector28 - .word SVCallVector - .word DebugMonitorVector - .word Vector34 - .word PendSVVector - .word SysTickVector - .word Vector40 - .word Vector44 - .word Vector48 - .word Vector4C - .word Vector50 - .word Vector54 - .word Vector58 - .word Vector5C - .word Vector60 - .word Vector64 - .word Vector68 - .word Vector6C - .word Vector70 - .word Vector74 - .word Vector78 - .word Vector7C - .word Vector80 - .word Vector84 - .word Vector88 - .word Vector8C - .word Vector90 - .word Vector94 - .word Vector98 - .word Vector9C - .word VectorA0 - .word VectorA4 - .word VectorA8 - .word VectorAC - .word VectorB0 - .word VectorB4 - .word VectorB8 - .word VectorBC - .word VectorC0 - .word VectorC4 - .word VectorC8 - .word VectorCC - .word VectorD0 - .word VectorD4 - .word VectorD8 - .word VectorDC - .word VectorE0 - .word VectorE4 - .word VectorE8 - .word VectorEC - .word VectorF0 - .word VectorF4 - .word VectorF8 - .word VectorFC - .word Vector100 - .word Vector104 - .word Vector108 - .word Vector10C - .word Vector110 - .word Vector114 - .word Vector118 - .word Vector11C - -.weak NMIVector -NMIVector: - -.weak HardFaultVector -HardFaultVector: - -.weak MemManageVector -MemManageVector: - -.weak BusFaultVector -BusFaultVector: - -.weak UsageFaultVector -UsageFaultVector: - -.weak Vector1C -Vector1C: - -.weak Vector20 -Vector20: - -.weak Vector24 -Vector24: - -.weak Vector28 -Vector28: - -.weak SVCallVector -SVCallVector: - -.weak DebugMonitorVector -DebugMonitorVector: - -.weak Vector34 -Vector34: - -.weak PendSVVector -PendSVVector: - -.weak SysTickVector -SysTickVector: - -.weak Vector40 -Vector40: - -.weak Vector44 -Vector44: - -.weak Vector48 -Vector48: - -.weak Vector4C -Vector4C: - -.weak Vector50 -Vector50: - -.weak Vector54 -Vector54: - -.weak Vector58 -Vector58: - -.weak Vector5C -Vector5C: - -.weak Vector60 -Vector60: - -.weak Vector64 -Vector64: - -.weak Vector68 -Vector68: - -.weak Vector6C -Vector6C: - -.weak Vector70 -Vector70: - -.weak Vector74 -Vector74: - -.weak Vector78 -Vector78: - -.weak Vector7C -Vector7C: - -.weak Vector80 -Vector80: - -.weak Vector84 -Vector84: - -.weak Vector88 -Vector88: - -.weak Vector8C -Vector8C: - -.weak Vector90 -Vector90: - -.weak Vector94 -Vector94: - -.weak Vector98 -Vector98: - -.weak Vector9C -Vector9C: - -.weak VectorA0 -VectorA0: - -.weak VectorA4 -VectorA4: - -.weak VectorA8 -VectorA8: - -.weak VectorAC -VectorAC: - -.weak VectorB0 -VectorB0: - -.weak VectorB4 -VectorB4: - -.weak VectorB8 -VectorB8: - -.weak VectorBC -VectorBC: - -.weak VectorC0 -VectorC0: - -.weak VectorC4 -VectorC4: - -.weak VectorC8 -VectorC8: - -.weak VectorCC -VectorCC: - -.weak VectorD0 -VectorD0: - -.weak VectorD4 -VectorD4: - -.weak VectorD8 -VectorD8: - -.weak VectorDC -VectorDC: - -.weak VectorE0 -VectorE0: - -.weak VectorE4 -VectorE4: - -.weak VectorE8 -VectorE8: - -.weak VectorEC -VectorEC: - -.weak VectorF0 -VectorF0: - -.weak VectorF4 -VectorF4: - -.weak VectorF8 -VectorF8: - -.weak VectorFC -VectorFC: - -.weak Vector100 -Vector100: - -.weak Vector104 -Vector104: - -.weak Vector108 -Vector108: - -.weak Vector10C -Vector10C: - -.weak Vector110 -Vector110: - -.weak Vector114 -Vector114: - -.weak Vector118 -Vector118: - -.weak Vector11C -Vector11C: - -here: b here diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/cmparams.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/cmparams.h deleted file mode 100644 index e9839cb..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/cmparams.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/STM32F10x/cmparams.h - * @brief ARM Cortex-M3 STM32F10x Specific Parameters. - * - * @defgroup ARMCMx_STM32F10x STM32F10x Specific Parameters - * @ingroup ARMCMx - * @details This file contains the Cortex-M3 specific parameters for the - * STM32F10x platform. - * @{ - */ - -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ - -/** - * @brief Cortex core model. - */ -#define CORTEX_MODEL CORTEX_M3 - -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - -/** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU FALSE - -/** - * @brief Number of bits in priority masks. - */ -#define CORTEX_PRIORITY_BITS 4 - -#endif /* _CMPARAMS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/port.mk b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/port.mk deleted file mode 100644 index 4d44a76..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/port.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS/RT Cortex-M3 STM32 port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm3.c - -PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s - -PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F10x \ - ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/vectors.s b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/vectors.s deleted file mode 100644 index f5d6128..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/vectors.s +++ /dev/null @@ -1,377 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -.syntax unified -.thumb - -/* If the macro is not defined in the Makefile then a board.h file must be - provided containing the definition of the STM32 family member.*/ -#if !defined(STM32F10X_LD) && !defined(STM32F10X_MD) && \ - !defined(STM32F10X_HD) && !defined(STM32F10X_CL) -#include "board.h" -#endif - -.section vectors -_vectors: - .word __ram_end__ - .word ResetHandler - .word NMIVector - .word HardFaultVector - .word MemManageVector - .word BusFaultVector - .word UsageFaultVector - .word Vector1C - .word Vector20 - .word Vector24 - .word Vector28 - .word SVCallVector - .word DebugMonitorVector - .word Vector34 - .word PendSVVector - .word SysTickVector - .word Vector40 - .word Vector44 - .word Vector48 - .word Vector4C - .word Vector50 - .word Vector54 - .word Vector58 - .word Vector5C - .word Vector60 - .word Vector64 - .word Vector68 - .word Vector6C - .word Vector70 - .word Vector74 - .word Vector78 - .word Vector7C - .word Vector80 - .word Vector84 - .word Vector88 - .word Vector8C - .word Vector90 - .word Vector94 - .word Vector98 - .word Vector9C - .word VectorA0 - .word VectorA4 - .word VectorA8 - .word VectorAC - .word VectorB0 - .word VectorB4 - .word VectorB8 - .word VectorBC - .word VectorC0 - .word VectorC4 - .word VectorC8 - .word VectorCC - .word VectorD0 - .word VectorD4 - .word VectorD8 - .word VectorDC - .word VectorE0 - .word VectorE4 - .word VectorE8 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) - .word VectorEC - .word VectorF0 - .word VectorF4 - .word VectorF8 - .word VectorFC - .word Vector100 - .word Vector104 - .word Vector108 - .word Vector10C - .word Vector110 - .word Vector114 - .word Vector118 - .word Vector11C - .word Vector120 - .word Vector124 - .word Vector128 - .word Vector12C -#endif -#if defined(STM32F10X_CL) - .word Vector130 - .word Vector134 - .word Vector138 - .word Vector13C - .word Vector140 - .word Vector144 - .word Vector148 - .word Vector14C -#endif - -.weak NMIVector -NMIVector: - -.weak HardFaultVector -HardFaultVector: - -.weak MemManageVector -MemManageVector: - -.weak BusFaultVector -BusFaultVector: - -.weak UsageFaultVector -UsageFaultVector: - -.weak Vector1C -Vector1C: - -.weak Vector20 -Vector20: - -.weak Vector24 -Vector24: - -.weak Vector28 -Vector28: - -.weak SVCallVector -SVCallVector: - -.weak DebugMonitorVector -DebugMonitorVector: - -.weak Vector34 -Vector34: - -.weak PendSVVector -PendSVVector: - -.weak SysTickVector -SysTickVector: - -.weak Vector40 -Vector40: - -.weak Vector44 -Vector44: - -.weak Vector48 -Vector48: - -.weak Vector4C -Vector4C: - -.weak Vector50 -Vector50: - -.weak Vector54 -Vector54: - -.weak Vector58 -Vector58: - -.weak Vector5C -Vector5C: - -.weak Vector60 -Vector60: - -.weak Vector64 -Vector64: - -.weak Vector68 -Vector68: - -.weak Vector6C -Vector6C: - -.weak Vector70 -Vector70: - -.weak Vector74 -Vector74: - -.weak Vector78 -Vector78: - -.weak Vector7C -Vector7C: - -.weak Vector80 -Vector80: - -.weak Vector84 -Vector84: - -.weak Vector88 -Vector88: - -.weak Vector8C -Vector8C: - -.weak Vector90 -Vector90: - -.weak Vector94 -Vector94: - -.weak Vector98 -Vector98: - -.weak Vector9C -Vector9C: - -.weak VectorA0 -VectorA0: - -.weak VectorA4 -VectorA4: - -.weak VectorA8 -VectorA8: - -.weak VectorAC -VectorAC: - -.weak VectorB0 -VectorB0: - -.weak VectorB4 -VectorB4: - -.weak VectorB8 -VectorB8: - -.weak VectorBC -VectorBC: - -.weak VectorC0 -VectorC0: - -.weak VectorC4 -VectorC4: - -.weak VectorC8 -VectorC8: - -.weak VectorCC -VectorCC: - -.weak VectorD0 -VectorD0: - -.weak VectorD4 -VectorD4: - -.weak VectorD8 -VectorD8: - -.weak VectorDC -VectorDC: - -.weak VectorE0 -VectorE0: - -.weak VectorE4 -VectorE4: - -.weak VectorE8 -VectorE8: - -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -.weak VectorEC -VectorEC: - -.weak VectorF0 -VectorF0: - -.weak VectorF4 -VectorF4: - -.weak VectorF8 -VectorF8: - -.weak VectorFC -VectorFC: - -.weak Vector100 -Vector100: - -.weak Vector104 -Vector104: - -.weak Vector108 -Vector108: - -.weak Vector10C -Vector10C: - -.weak Vector110 -Vector110: - -.weak Vector114 -Vector114: - -.weak Vector118 -Vector118: - -.weak Vector11C -Vector11C: - -.weak Vector120 -Vector120: - -.weak Vector124 -Vector124: - -.weak Vector128 -Vector128: - -.weak Vector12C -Vector12C: -#endif -#if defined(STM32F10X_CL) -.weak Vector130 -Vector130: - -.weak Vector134 -Vector134: - -.weak Vector138 -Vector138: - -.weak Vector13C -Vector13C: - -.weak Vector140 -Vector140: - -.weak Vector144 -Vector144: - -.weak Vector148 -Vector148: - -.weak Vector14C -Vector14C: -#endif - -here: b here diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.c b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.c deleted file mode 100644 index b4e1813..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chcore.c - * @brief ARM Cortex-Mx port code. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#include "ch.h" - -/** - * @brief Halts the system. - * @note The function is declared as a weak symbol, it is possible - * to redefine it in your application code. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.h deleted file mode 100644 index eb62e9d..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chcore.h - * @brief ARM Cortex-Mx port macros and structures. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -#include "nvic.h" - -/*===========================================================================*/ -/* Port constants. */ -/*===========================================================================*/ - -#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ -#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ -#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ -#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ - -/* Inclusion of the Cortex-Mx implementation specific parameters.*/ -#include "cmparams.h" - -/* Cortex model check, only M0 and M3 supported right now.*/ -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) -#elif (CORTEX_MODEL == CORTEX_M1) || (CORTEX_MODEL == CORTEX_M4) -#warning "untested Cortex-M model" -#else -#error "unknown or unsupported Cortex-M model" -#endif - -/*===========================================================================*/ -/* Port statically derived parameters. */ -/*===========================================================================*/ - -/** - * @brief Total priority levels. - */ -#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) - -/** - * @brief Minimum priority level. - * @details This minimum priority level is calculated from the number of - * priority bits supported by the specific Cortex-Mx implementation. - */ -#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) - -/** - * @brief Maximum priority level. - * @details The maximum allowed priority level is always zero. - */ -#define CORTEX_MAXIMUM_PRIORITY 0 - -/** - * @brief Disabled value for BASEPRI register. - * @note ARMv7-M architecture only. - */ -#define CORTEX_BASEPRI_DISABLED 0 - -/*===========================================================================*/ -/* Port macros. */ -/*===========================================================================*/ - -/** - * @brief Priority level verification macro. - */ -#define CORTEX_IS_VALID_PRIORITY(n) \ - (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) - -/** - * @brief Priority level to priority mask conversion macro. - */ -#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS)) - -/*===========================================================================*/ -/* Port configurable parameters. */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#ifndef CORTEX_ENABLE_WFI_IDLE -#define CORTEX_ENABLE_WFI_IDLE FALSE -#endif - -/** - * @brief SYSTICK handler priority. - * @note The default SYSTICK handler priority is calculated as the priority - * level in the middle of the numeric priorities range. - */ -#ifndef CORTEX_PRIORITY_SYSTICK -#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) -#else -/* If it is externally redefined then better perform a validity check on it.*/ -#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) -#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" -#endif -#endif - -/** - * @brief SVCALL handler priority. - * @note The default SVCALL handler priority is calculated as - * @p CORTEX_MAXIMUM_PRIORITY+1, in the ARMv7-M port this reserves - * the @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts - * priority level. - * @note The SVCALL vector is only used in the ARMv7-M port, it is available - * to user in the ARMv6-M port. - */ -#ifndef CORTEX_PRIORITY_SVCALL -#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) -#else -/* If it is externally redefined then better perform a validity check on it.*/ -#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) -#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" -#endif -#endif - -/** - * @brief PENDSV handler priority. - * @note The default PENDSV handler priority is set at the - * @p CORTEX_MINIMUM_PRIORITY priority level. - * @note The PENDSV vector is only used in the ARMv7-M legacy port, it is - * available to user in the ARMv6-M and ARMv7-M ports. - * @note In the ARMv7-M legacy port this value should be not changed from - * the minimum priority level. - */ -#ifndef CORTEX_PRIORITY_PENDSV -#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY -#else -/* If it is externally redefined then better perform a validity check on it.*/ -#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV) -#error "invalid priority level specified for CORTEX_PRIORITY_PENDSV" -#endif -#endif - -/** - * @brief BASEPRI level within kernel lock. - * @note This value must not mask the SVCALL priority level or the - * kernel would hard fault. - * @note ARMv7-M architecture only. - */ -#ifndef CORTEX_BASEPRI_KERNEL -#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) -#endif - -/** - * @brief Stack alignment enforcement. - * @note The default value is 64 in order to comply with EABI, reducing - * the value to 32 can save some RAM space if you don't care about - * binary compatibility with EABI compiled libraries. - * @note Allowed values are 32 or 64. - */ -#ifndef CORTEX_STACK_ALIGNMENT -#define CORTEX_STACK_ALIGNMENT 64 -#endif - -/*===========================================================================*/ -/* Port exported info. */ -/*===========================================================================*/ - -/** - * @brief Macro defining a generic ARM architecture. - */ -#define CH_ARCHITECTURE_ARM - -#if defined(__DOXYGEN__) -/** - * @brief Macro defining the specific ARM architecture. - */ -#define CH_ARCHITECTURE_ARM_vxm - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "ARMvx-M" - -/** - * @brief Name of the architecture variant (optional). - */ -#define CH_CORE_VARIANT_NAME "Cortex-Mx" -#elif CORTEX_MODEL == CORTEX_M4 -#define CH_ARCHITECTURE_ARM_v7M -#define CH_ARCHITECTURE_NAME "ARMv7-ME" -#define CH_CORE_VARIANT_NAME "Cortex-M4" -#elif CORTEX_MODEL == CORTEX_M3 -#define CH_ARCHITECTURE_ARM_v7M -#define CH_ARCHITECTURE_NAME "ARMv7-M" -#define CH_CORE_VARIANT_NAME "Cortex-M3" -#elif CORTEX_MODEL == CORTEX_M1 -#define CH_ARCHITECTURE_ARM_v6M -#define CH_ARCHITECTURE_NAME "ARMv6-M" -#define CH_CORE_VARIANT_NAME "Cortex-M1" -#elif CORTEX_MODEL == CORTEX_M0 -#define CH_ARCHITECTURE_ARM_v6M -#define CH_ARCHITECTURE_NAME "ARMv6-M" -#define CH_CORE_VARIANT_NAME "Cortex-M0" -#endif - -/*===========================================================================*/ -/* Port implementation part (common). */ -/*===========================================================================*/ - -/** - * @brief Stack and memory alignment enforcement. - */ -#if (CORTEX_STACK_ALIGNMENT == 64) || defined(__DOXYGEN__) -typedef uint64_t stkalign_t __attribute__ ((aligned (8))); -#elif CORTEX_STACK_ALIGNMENT == 32 -typedef uint32_t stkalign_t __attribute__ ((aligned (4))); -#else -#error "invalid stack alignment selected" -#endif - -/** - * @brief Generic ARM register. - */ -typedef void *regarm_t; - -#if !defined(__DOXYGEN__) -/** - * @brief Platform dependent part of the @p Thread structure. - * @details In this port the structure just holds a pointer to the @p intctx - * structure representing the stack pointer at context switch time. - */ -struct context { - struct intctx *r13; -}; -#endif - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/* Includes the architecture-specific implementation part.*/ -#if defined(CH_ARCHITECTURE_ARM_v6M) -#include "chcore_v6m.h" -#elif defined(CH_ARCHITECTURE_ARM_v7M) -#include "chcore_v7m.h" -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v6m.c b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v6m.c deleted file mode 100644 index 7377511..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v6m.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chcore_v6m.c - * @brief ARMv6-M architecture port code. - * - * @addtogroup ARMCMx_V6M_CORE - * @{ - */ - -#include "ch.h" - -/** - * @brief PC register temporary storage. - */ -regarm_t _port_saved_pc; - -/** - * @brief IRQ nesting counter. - */ -unsigned _port_irq_nesting; - -/** - * @brief System Timer vector. - * @details This interrupt is used as system tick. - * @note The timer must be initialized in the startup code. - */ -CH_IRQ_HANDLER(SysTickVector) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief Post-IRQ switch code. - * @details On entry the stack and the registers are restored by the exception - * return, the PC value is stored in @p _port_saved_pc, the interrupts - * are disabled. - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void _port_switch_from_irq(void) { - /* Note, saves r4 to make space for the PC.*/ - asm volatile ("push {r0, r1, r2, r3, r4} \n\t" - "mrs r0, APSR \n\t" - "mov r1, r12 \n\t" - "push {r0, r1, lr} \n\t" - "ldr r0, =_port_saved_pc \n\t" - "ldr r0, [r0] \n\t" - "add r0, r0, #1 \n\t" - "str r0, [sp, #28]" : : : "memory"); - - chSchDoRescheduleI(); - - /* Note, the last registers are restored alone after re-enabling the - interrupts in order to minimize the (very remote and unlikely) - possibility that the stack is filled by continuous and saturating - interrupts that would not allow that last words to be pulled out of - the stack.*/ - asm volatile ("pop {r0, r1, r2} \n\t" - "mov r12, r1 \n\t" - "msr APSR, r0 \n\t" - "mov lr, r2 \n\t" - "cpsie i \n\t" - "pop {r0, r1, r2, r3, pc}" : : : "memory"); -} - -#define PUSH_CONTEXT(sp) { \ - asm volatile ("push {r4, r5, r6, r7, lr} \n\t" \ - "mov r4, r8 \n\t" \ - "mov r5, r9 \n\t" \ - "mov r6, r10 \n\t" \ - "mov r7, r11 \n\t" \ - "push {r4, r5, r6, r7}" : : : "memory"); \ -} - -#define POP_CONTEXT(sp) { \ - asm volatile ("pop {r4, r5, r6, r7} \n\t" \ - "mov r8, r4 \n\t" \ - "mov r9, r5 \n\t" \ - "mov r10, r6 \n\t" \ - "mov r11, r7 \n\t" \ - "pop {r4, r5, r6, r7, pc}" : : "r" (sp) : "memory"); \ -} - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void port_switch(Thread *ntp, Thread *otp) { - register struct intctx *r13 asm ("r13"); - - /* Stack overflow check, if enabled.*/ -#if CH_DBG_ENABLE_STACK_CHECK - if ((void *)(r13 - 1) < (void *)(otp + 1)) - asm volatile ("movs r0, #0 \n\t" - "b chDbgPanic"); -#endif /* CH_DBG_ENABLE_STACK_CHECK */ - - PUSH_CONTEXT(r13); - - otp->p_ctx.r13 = r13; - r13 = ntp->p_ctx.r13; - - POP_CONTEXT(r13); -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - - port_unlock(); - asm volatile ("mov r0, r5 \n\t" - "blx r4 \n\t" - "bl chThdExit"); -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v6m.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v6m.h deleted file mode 100644 index a79d7ed..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v6m.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chcore_v6m.h - * @brief ARMv6-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V6M_CORE - * @{ - */ - -#ifndef _CHCORE_V6M_H_ -#define _CHCORE_V6M_H_ - -/*===========================================================================*/ -/* Port implementation part. */ -/*===========================================================================*/ - -/** - * @brief Cortex-Mx exception context. - */ -struct cmxctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -}; - -#if !defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - */ -struct extctx { - regarm_t xpsr; - regarm_t r12; - regarm_t lr; - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t pc; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct intctx { - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t lr; -}; -#endif - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = _port_thread_start; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - * @note In this port it is set to 8 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 8 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - * @note In this port it is conservatively set to 16 because the function - * @p chSchDoRescheduleI() can have a stack frame, expecially with - * compiler optimizations disabled. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 16 -#endif - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() { \ - port_lock_from_isr(); \ - _port_irq_nesting++; \ - port_unlock_from_isr(); \ -} - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() { \ - port_lock_from_isr(); \ - if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) { \ - register struct cmxctx *ctxp; \ - \ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : ); \ - _port_saved_pc = ctxp->pc; \ - ctxp->pc = _port_switch_from_irq; \ - return; \ - } \ - port_unlock_from_isr(); \ -} - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Port-related initialization code. - */ -#define port_init() { \ - _port_irq_nesting = 0; \ - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ - NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ -} - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - */ -#define port_lock() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - */ -#define port_unlock() asm volatile ("cpsie i" : : : "memory") - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_lock_from_isr() port_lock() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_unlock_from_isr() port_unlock() - -/** - * @brief Disables all the interrupt sources. - */ -#define port_disable() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Disables the interrupt sources below kernel-level priority. - */ -#define port_suspend() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Enables all the interrupt sources. - */ -#define port_enable() asm volatile ("cpsie i" : : : "memory") - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) -#define port_wait_for_interrupt() asm volatile ("wfi" : : : "memory") -#else -#define port_wait_for_interrupt() -#endif - -#if !defined(__DOXYGEN__) -extern regarm_t _port_saved_pc; -extern unsigned _port_irq_nesting; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); - void port_switch(Thread *ntp, Thread *otp); - void _port_switch_from_irq(void); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_V6M_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.c b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.c deleted file mode 100644 index 6d5b35e..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chcore_v7m.c - * @brief ARMv7-M architecture port code. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#include "ch.h" - -#if !defined(CH_CURRP_REGISTER_CACHE) || defined(__DOXXYGEN__) -/** - * @brief Internal context stacking. - */ -#define PUSH_CONTEXT() { \ - asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" \ - : : : "memory"); \ -} - -/** - * @brief Internal context unstacking. - */ -#define POP_CONTEXT() { \ - asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \ - : : : "memory"); \ -} -#else /* defined(CH_CURRP_REGISTER_CACHE) */ -#define PUSH_CONTEXT() { \ - asm volatile ("push {r4, r5, r6, r8, r9, r10, r11, lr}" \ - : : : "memory"); \ -} - -#define POP_CONTEXT() { \ - asm volatile ("pop {r4, r5, r6, r8, r9, r10, r11, pc}" \ - : : : "memory"); \ -} -#endif /* defined(CH_CURRP_REGISTER_CACHE) */ - -#if !CH_OPTIMIZE_SPEED -void _port_lock(void) { - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); -} - -void _port_unlock(void) { - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); -} -#endif - -/** - * @brief System Timer vector. - * @details This interrupt is used as system tick. - * @note The timer must be initialized in the startup code. - */ -CH_IRQ_HANDLER(SysTickVector) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief SVC vector. - * @details The SVC vector is used for exception mode re-entering after a - * context switch. - */ -void SVCallVector(void) { - register struct extctx *ctxp; - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); - ctxp++; - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); - port_unlock_from_isr(); -} - -/** - * @brief Exception exit redirection to _port_switch_from_isr(). - */ -void _port_irq_epilogue(void) { - - port_lock_from_isr(); - if ((SCB_ICSR & ICSR_RETTOBASE)) { - register struct extctx *ctxp; - - /* Adding an artificial exception return context, there is no need to - populate it fully.*/ - asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory"); - ctxp--; - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); - ctxp->pc = _port_switch_from_isr; - ctxp->xpsr = (regarm_t)0x01000000; - /* Note, returning without unlocking is intentional, this is done in - order to keep the rest of the context switching atomic.*/ - return; - } - port_unlock_from_isr(); -} - -/** - * @brief Post-IRQ switch code. - * @details Exception handlers return here for context switching. - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void _port_switch_from_isr(void) { - - if (chSchIsRescRequiredExI()) - chSchDoRescheduleI(); - asm volatile ("svc #0"); -} - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void port_switch(Thread *ntp, Thread *otp) { - -#if CH_DBG_ENABLE_STACK_CHECK - /* Stack overflow check, if enabled.*/ - register struct intctx *r13 asm ("r13"); - if ((void *)(r13 - 1) < (void *)(otp + 1)) - asm volatile ("movs r0, #0 \n\t" - "b chDbgPanic"); -#endif /* CH_DBG_ENABLE_STACK_CHECK */ - - PUSH_CONTEXT(); - - asm volatile ("str sp, [%1, #12] \n\t" - "ldr sp, [%0, #12]" : : "r" (ntp), "r" (otp)); - - POP_CONTEXT(); -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - - port_unlock(); - asm volatile ("mov r0, r5 \n\t" - "blx r4 \n\t" - "bl chThdExit"); -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.h deleted file mode 100644 index 6fcf59a..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chcore_v7m.h - * @brief ARMv7-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#ifndef _CHCORE_V7M_H_ -#define _CHCORE_V7M_H_ - -/*===========================================================================*/ -/* Port implementation part. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note It is implemented to match the Cortex-Mx exception context. - */ -struct extctx { - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct intctx { - regarm_t r4; - regarm_t r5; - regarm_t r6; -#ifndef CH_CURRP_REGISTER_CACHE - regarm_t r7; -#endif - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr; -}; -#endif - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = _port_thread_start; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - * @note In this port it is set to 8 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 8 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - * @note In this port it is conservatively set to 16 because the function - * @p chSchDoRescheduleI() can have a stack frame, expecially with - * compiler optimizations disabled. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 16 -#endif - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Fast IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_FAST_IRQ_HANDLER(id) void id(void) - -/** - * @brief Port-related initialization code. - */ -#define port_init() { \ - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ - NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ - NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ -} - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - * @note In this port this it raises the base priority to kernel level. - */ -#if CH_OPTIMIZE_SPEED -#define port_lock() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ -} -#else -#define port_lock() { \ - asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \ -} -#endif - -/** - * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - * @note In this port this it lowers the base priority to user level. - */ -#if CH_OPTIMIZE_SPEED -#define port_unlock() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ -} -#else -#define port_unlock() { \ - asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \ -} -#endif - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_lock_from_isr() port_lock() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note Same as @p port_unlock() in this port. - */ -#define port_unlock_from_isr() port_unlock() - -/** - * @brief Disables all the interrupt sources. - * @note Of course non maskable interrupt sources are not included. - * @note In this port it disables all the interrupt sources by raising - * the priority mask to level 0. - */ -#define port_disable() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note In this port it raises/lowers the base priority to kernel level. - */ -#define port_suspend() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ - asm volatile ("msr BASEPRI, %0 \n\t" \ - "cpsie i" : : "r" (tmp) : "memory"); \ -} - -/** - * @brief Enables all the interrupt sources. - * @note In this port it lowers the base priority to user level. - */ -#define port_enable() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ - asm volatile ("msr BASEPRI, %0 \n\t" \ - "cpsie i" : : "r" (tmp) : "memory"); \ -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) -#define port_wait_for_interrupt() { \ - asm volatile ("wfi" : : : "memory"); \ -} -#else -#define port_wait_for_interrupt() -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); - void port_switch(Thread *ntp, Thread *otp); - void _port_irq_epilogue(void); - void _port_switch_from_isr(void); - void _port_thread_start(void); -#if !CH_OPTIMIZE_SPEED - void _port_lock(void); - void _port_unlock(void); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_V7M_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chtypes.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chtypes.h deleted file mode 100644 index cb1f5db..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chtypes.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chtypes.h - * @brief ARM Cortex-Mx port system types. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#define __need_ptrdiff_t -#include - -#include - -typedef int32_t bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Event Id. */ -typedef uint32_t eventmask_t; /**< Events mask. */ -typedef uint32_t systime_t; /**< System time. */ -typedef int32_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note It uses the "packed" GCC attribute. - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm0.c b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm0.c deleted file mode 100644 index d38074f..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm0.c +++ /dev/null @@ -1,455 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.c - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm0.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm0.h deleted file mode 100644 index e7c37de..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm0.h +++ /dev/null @@ -1,991 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * Parts of this files have been modified in ChibiOS/RT in order to fix - * some code quality issues. - */ - -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM0_CORE_H__ -#define __CM0_CORE_H__ - -/** @addtogroup CMSIS_CM0_core_LintCinfiguration CMSIS CM0 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - not yet checked - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - - -/** @addtogroup CMSIS_CM0_core_definitions CM0 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM0_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM0_core_register CMSIS CM0 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM0_NVIC CMSIS CM0 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< (Offset: 0x000) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< (Offset: 0x080) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< (Offset: 0x100) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< (Offset: 0x180) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IPR[8]; /*!< (Offset: 0x3EC) Interrupt Priority Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM0_NVIC */ - - -/** @addtogroup CMSIS_CM0_SCB CMSIS CM0 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x1C System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - uint32_t RESERVED2[2]; - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFul << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM0_SCB */ - - -/** @addtogroup CMSIS_CM0_SysTick CMSIS CM0 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM0_SysTick */ - - -/** @addtogroup CMSIS_CM0_CoreDebug CMSIS CM0 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24 /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1ul << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM0_CoreDebug */ - - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -/*@}*/ /* end of group CMSIS_CM0_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev - - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ - - -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - - - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP(void) { __ASM volatile ("nop"); } -static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } -static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } -static __INLINE void __SEV(void) { __ASM volatile ("sev"); } -static __INLINE void __ISB(void) { __ASM volatile ("isb"); } -static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } -static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM0_Core_FunctionInterface CMSIS CM0 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM0_Core_FunctionInterface */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM0_core_definitions */ - -#endif /* __CM0_CORE_H__ */ - -/*lint -restore */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c deleted file mode 100644 index fcff0d1..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.h deleted file mode 100644 index f227545..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.h +++ /dev/null @@ -1,1849 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * Parts of this files have been modified in ChibiOS/RT in order to fix - * some code quality issues. - */ - -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP(void) { __ASM volatile ("nop"); } -static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } -static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } -static __INLINE void __SEV(void) { __ASM volatile ("sev"); } -static __INLINE void __ISB(void) { __ASM volatile ("isb"); } -static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } -static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } -static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/crt0.s b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/crt0.s deleted file mode 100644 index 3db68e3..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/crt0.s +++ /dev/null @@ -1,169 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/crt0.s - * @brief Generic ARM Cortex-Mx startup file for ChibiOS/RT. - * - * @addtogroup ARMCMx_CORE - * @{ - */ - -#include "cmparams.h" - -#if !defined(__DOXYGEN__) - -.set CONTROL_MODE_PRIVILEGED, 0 -.set CONTROL_MODE_UNPRIVILEGED, 1 -.set CONTROL_USE_MSP, 0 -.set CONTROL_USE_PSP, 2 - -.text -.balign 2 -.syntax unified -.thumb - -/* - * Reset handler. - */ -.thumb_func -.global ResetHandler -.weak ResetHandler -ResetHandler: - /* - * Interrupts are globally masked initially. - */ - cpsid i - /* - * Stack pointers initialization. - */ - ldr r0, =__ram_end__ - ldr r1, =__main_stack_size__ - subs r0, r0, r1 - /* - * Note that r0 is the main stack low boundary address and process - * stack initial top address. - */ - msr PSP, r0 - /* - * Early initialization phase, it is empty by default. - */ - bl hwinit0 - /* - * Data initialization. - * NOTE: It assumes that the DATA size is a multiple of 4. - */ - ldr r1, =_textdata - ldr r2, =_data - ldr r3, =_edata -dloop: - cmp r2, r3 -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) - bge enddloop - ldr r0, [r1] - str r0, [r2] - adds r1, r1, #4 - adds r2, r2, #4 - b dloop -enddloop: -#else - ittt lo - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo dloop -#endif - /* - * BSS initialization. - * NOTE: It assumes that the BSS size is a multiple of 4. - */ - movs r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -bloop: - cmp r1, r2 -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) - bge endbloop - str r0, [r1] - adds r1, r1, #4 - b bloop -endbloop: -#else - itt lo - strlo r0, [r1], #4 - blo bloop -#endif - /* - * Switches to the Process Stack and uses a barrier just to be safe. - */ - movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP - msr CONTROL, r0 - isb - /* - * Late initialization phase, it is empty by default. - */ - bl hwinit1 - movs r0, #0 - mov r1, r0 - bl main - b MainExitHandler - -/* - * Default main exit code, just a loop. - * It is a weak symbol, the application code can redefine the behavior. - */ -.thumb_func -.global MainExitHandler -.weak MainExitHandler -MainExitHandler: -.loop: b .loop - -/* - * Default early initialization code. It is declared weak in order to be - * replaced by the real initialization code. - * Early initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -.thumb_func -.global hwinit0 -.weak hwinit0 -hwinit0: - bx lr - -/* - * Default late initialization code. It is declared weak in order to be - * replaced by the real initialization code. - * Late initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -.thumb_func -.global hwinit1 -.weak hwinit1 -hwinit1: - bx lr - -#endif - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.c b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.c deleted file mode 100644 index aaa474d..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/nvic.c - * @brief Cortex-Mx NVIC support code. - * - * @addtogroup ARMCMx_NVIC - * @{ - */ - -#include "ch.h" -#include "nvic.h" - -/** - * @brief Sets the priority of an interrupt handler and enables it. - * - * @param n the interrupt number - * @param prio the interrupt priority mask - * - * @note The parameters are not tested for correctness. - */ -void NVICEnableVector(uint32_t n, uint32_t prio) { - unsigned sh = (n & 3) << 3; - - NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh); - NVIC_ICPR(n >> 5) = 1 << (n & 0x1F); - NVIC_ISER(n >> 5) = 1 << (n & 0x1F); -} - -/** - * @brief Disables an interrupt handler. - * - * @param n the interrupt number - * - * @note The parameters are not tested for correctness. - */ -void NVICDisableVector(uint32_t n) { - unsigned sh = (n & 3) << 3; - - NVIC_ICER(n >> 5) = 1 << (n & 0x1F); - NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh); -} - -/** - * @brief Changes the priority of a system handler. - * - * @param handler the system handler number - * @param prio the system handler priority mask - * @note The parameters are not tested for correctness. - */ -void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { - unsigned sh = (handler & 3) * 8; - - SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & - ~(0xFF << sh)) | (prio << sh); -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.h deleted file mode 100644 index 9f53856..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/nvic.h - * @brief Cortex-Mx NVIC support macros and structures. - * - * @addtogroup ARMCMx_NVIC - * @{ - */ - -#ifndef _NVIC_H_ -#define _NVIC_H_ - -/* - * System vector constants for @p NVICSetSystemHandlerPriority(). - */ -#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ -#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ -#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */ -#define HANDLER_RESERVED_3 3 -#define HANDLER_RESERVED_4 4 -#define HANDLER_RESERVED_5 5 -#define HANDLER_RESERVED_6 6 -#define HANDLER_SVCALL 7 /**< SVCALL vector id. */ -#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */ -#define HANDLER_RESERVED_9 9 -#define HANDLER_PENDSV 10 /**< PENDSV vector id. */ -#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ - -typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */ -typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */ - -/** - * @brief NVIC ITCR register. - */ -#define NVIC_ITCR (*((IOREG32 *)0xE000E004)) - -/** - * @brief NVIC STIR register. - */ -#define NVIC_STIR (*((IOREG32 *)0xE000EF00)) - -/** - * @brief Structure representing the SYSTICK I/O space. - */ -typedef struct { - IOREG32 CSR; - IOREG32 RVR; - IOREG32 CVR; - IOREG32 CBVR; -} CM3_ST; - -/** - * @brief SYSTICK peripheral base address. - */ -#define STBase ((CM3_ST *)0xE000E010) -#define ST_CSR (STBase->CSR) -#define ST_RVR (STBase->RVR) -#define ST_CVR (STBase->CVR) -#define ST_CBVR (STBase->CBVR) - -#define CSR_ENABLE_MASK (0x1 << 0) -#define ENABLE_OFF_BITS (0 << 0) -#define ENABLE_ON_BITS (1 << 0) -#define CSR_TICKINT_MASK (0x1 << 1) -#define TICKINT_DISABLED_BITS (0 << 1) -#define TICKINT_ENABLED_BITS (1 << 1) -#define CSR_CLKSOURCE_MASK (0x1 << 2) -#define CLKSOURCE_EXT_BITS (0 << 2) -#define CLKSOURCE_CORE_BITS (1 << 2) -#define CSR_COUNTFLAG_MASK (0x1 << 16) - -#define RVR_RELOAD_MASK (0xFFFFFF << 0) - -#define CVR_CURRENT_MASK (0xFFFFFF << 0) - -#define CBVR_TENMS_MASK (0xFFFFFF << 0) -#define CBVR_SKEW_MASK (0x1 << 30) -#define CBVR_NOREF_MASK (0x1 << 31) - -/** - * @brief Structure representing the NVIC I/O space. - */ -typedef struct { - IOREG32 ISER[8]; - IOREG32 unused1[24]; - IOREG32 ICER[8]; - IOREG32 unused2[24]; - IOREG32 ISPR[8]; - IOREG32 unused3[24]; - IOREG32 ICPR[8]; - IOREG32 unused4[24]; - IOREG32 IABR[8]; - IOREG32 unused5[56]; - IOREG32 IPR[60]; -} CM3_NVIC; - -/** - * @brief NVIC peripheral base address. - */ -#define NVICBase ((CM3_NVIC *)0xE000E100) -#define NVIC_ISER(n) (NVICBase->ISER[n]) -#define NVIC_ICER(n) (NVICBase->ICER[n]) -#define NVIC_ISPR(n) (NVICBase->ISPR[n]) -#define NVIC_ICPR(n) (NVICBase->ICPR[n]) -#define NVIC_IABR(n) (NVICBase->IABR[n]) -#define NVIC_IPR(n) (NVICBase->IPR[n]) - -/** - * @brief Structure representing the System Control Block I/O space. - */ -typedef struct { - IOREG32 CPUID; - IOREG32 ICSR; - IOREG32 VTOR; - IOREG32 AIRCR; - IOREG32 SCR; - IOREG32 CCR; - IOREG32 SHPR[3]; - IOREG32 SHCSR; - IOREG32 CFSR; - IOREG32 HFSR; - IOREG32 DFSR; - IOREG32 MMFAR; - IOREG32 BFAR; - IOREG32 AFSR; -} CM3_SCB; - -/** - * @brief SCB peripheral base address. - */ -#define SCBBase ((CM3_SCB *)0xE000ED00) -#define SCB_CPUID (SCBBase->CPUID) -#define SCB_ICSR (SCBBase->ICSR) -#define SCB_VTOR (SCBBase->VTOR) -#define SCB_AIRCR (SCBBase->AIRCR) -#define SCB_SCR (SCBBase->SCR) -#define SCB_CCR (SCBBase->CCR) -#define SCB_SHPR(n) (SCBBase->SHPR[n]) -#define SCB_SHCSR (SCBBase->SHCSR) -#define SCB_CFSR (SCBBase->CFSR) -#define SCB_HFSR (SCBBase->HFSR) -#define SCB_DFSR (SCBBase->DFSR) -#define SCB_MMFAR (SCBBase->MMFAR) -#define SCB_BFAR (SCBBase->BFAR) -#define SCB_AFSR (SCBBase->AFSR) - -#define ICSR_VECTACTIVE_MASK (0x1FF << 0) -#define ICSR_RETTOBASE (0x1 << 11) -#define ICSR_VECTPENDING_MASK (0x1FF << 12) -#define ICSR_ISRPENDING (0x1 << 22) -#define ICSR_ISRPREEMPT (0x1 << 23) -#define ICSR_PENDSTCLR (0x1 << 25) -#define ICSR_PENDSTSET (0x1 << 26) -#define ICSR_PENDSVCLR (0x1 << 27) -#define ICSR_PENDSVSET (0x1 << 28) -#define ICSR_NMIPENDSET (0x1 << 31) - -#define AIRCR_VECTKEY 0x05FA0000 -#define AIRCR_PRIGROUP_MASK (0x7 << 8) -#define AIRCR_PRIGROUP(n) ((n) << 8) - -#ifdef __cplusplus -extern "C" { -#endif - void NVICEnableVector(uint32_t n, uint32_t prio); - void NVICDisableVector(uint32_t n); - void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio); -#ifdef __cplusplus -} -#endif - -#endif /* _NVIC_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/old/chcore_v7m.c b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/old/chcore_v7m.c deleted file mode 100644 index c8b95b1..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/old/chcore_v7m.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chcore_v7m.c - * @brief ARMv7-M architecture port code. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#include "ch.h" - -#if !CH_OPTIMIZE_SPEED -void _port_lock(void) { - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; - asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); -} - -void _port_unlock(void) { - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; - asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); -} -#endif - -/** - * @brief System Timer vector. - * @details This interrupt is used as system tick. - * @note The timer must be initialized in the startup code. - */ -void SysTickVector(void) { - - chSysLockFromIsr(); - chSysTimerHandlerI(); - if (chSchIsRescRequiredExI()) - SCB_ICSR = ICSR_PENDSVSET; - chSysUnlockFromIsr(); -} - -#if !defined(CH_CURRP_REGISTER_CACHE) -#define PUSH_CONTEXT(sp, prio) { \ - asm volatile ("mrs %0, PSP \n\t" \ - "stmdb %0!, {r3-r11,lr}" : \ - "=r" (sp) : "r" (sp), "r" (prio)); \ -} - -#define POP_CONTEXT(sp) { \ - asm volatile ("ldmia %0!, {r3-r11, lr} \n\t" \ - "msr PSP, %0 \n\t" \ - "msr BASEPRI, r3 \n\t" \ - "bx lr" : "=r" (sp) : "r" (sp)); \ -} -#else /* defined(CH_CURRP_REGISTER_CACHE) */ -#define PUSH_CONTEXT(sp, prio) { \ - asm volatile ("mrs %0, PSP \n\t" \ - "stmdb %0!, {r3-r6,r8-r11, lr}" : \ - "=r" (sp) : "r" (sp), "r" (prio)); \ -} - -#define POP_CONTEXT(sp) { \ - asm volatile ("ldmia %0!, {r3-r6,r8-r11, lr} \n\t" \ - "msr PSP, %0 \n\t" \ - "msr BASEPRI, r3 \n\t" \ - "bx lr" : "=r" (sp) : "r" (sp)); \ -} -#endif /* defined(CH_CURRP_REGISTER_CACHE) */ - -/** - * @brief SVC vector. - * @details The SVC vector is used for commanded context switch. Structures - * @p intctx are saved and restored from the process stacks of the - * switched threads. - * - * @param[in] ntp the thread to be switched it - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void SVCallVector(Thread *ntp, Thread *otp) { - register struct intctx *sp_thd asm("r2"); - register uint32_t prio asm ("r3"); - - asm volatile ("mrs r3, BASEPRI" : "=r" (prio) : ); - PUSH_CONTEXT(sp_thd, prio) - - otp->p_ctx.r13 = sp_thd; - sp_thd = ntp->p_ctx.r13; - - POP_CONTEXT(sp_thd) -} - -/** - * @brief Preemption code. - */ -#if !defined(__DOXYGEN__) -__attribute__((naked)) -#endif -void PendSVVector(void) { - register struct intctx *sp_thd asm("r2"); - register uint32_t prio asm ("r3"); - Thread *otp, *ntp; - - chSysLockFromIsr(); - - prio = CORTEX_BASEPRI_DISABLED; - PUSH_CONTEXT(sp_thd, prio) - - (otp = currp)->p_ctx.r13 = sp_thd; - ntp = fifo_remove(&rlist.r_queue); - setcurrp(ntp); - ntp->p_state = THD_STATE_CURRENT; - chSchReadyI(otp); -#if CH_TIME_QUANTUM > 0 - /* Set the round-robin time quantum.*/ - rlist.r_preempt = CH_TIME_QUANTUM; -#endif - chDbgTrace(otp); - sp_thd = ntp->p_ctx.r13; - - POP_CONTEXT(sp_thd) -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/old/chcore_v7m.h b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/old/chcore_v7m.h deleted file mode 100644 index 0822ff1..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/old/chcore_v7m.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ARMCMx/chcore_v7m.h - * @brief ARMv7-M architecture port macros and structures. - * - * @addtogroup ARMCMx_V7M_CORE - * @{ - */ - -#ifndef _CHCORE_V7M_H_ -#define _CHCORE_V7M_H_ - -/*===========================================================================*/ -/* Port implementation part. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note This structure is empty in this port. - */ -struct extctx { -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct intctx { - regarm_t basepri; - regarm_t r4; - regarm_t r5; - regarm_t r6; -#ifndef CH_CURRP_REGISTER_CACHE - regarm_t r7; -#endif - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr_exc; - /* Start of the hardware saved frame.*/ - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -}; -#endif - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->basepri = CORTEX_BASEPRI_DISABLED; \ - tp->p_ctx.r13->lr_exc = (regarm_t)0xFFFFFFFD; \ - tp->p_ctx.r13->r0 = arg; \ - tp->p_ctx.r13->lr_thd = chThdExit; \ - tp->p_ctx.r13->pc = pf; \ - tp->p_ctx.r13->xpsr = (regarm_t)0x01000000; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - * @note In this port it is set to 4 because the idle thread does have - * a stack frame when compiling without optimizations. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 4 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - * @note This port requires no extra stack space for interrupt handling. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 0 -#endif - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() { \ - chSysLockFromIsr(); \ - if (chSchIsRescRequiredI()) \ - SCB_ICSR = ICSR_PENDSVSET; \ - chSysUnlockFromIsr(); \ -} - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Port-related initialization code. - */ -#define port_init() { \ - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ - NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ - NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ - NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ -} - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - * @note In this port this it raises the base priority to kernel level. - */ -#if CH_OPTIMIZE_SPEED -#define port_lock() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ -} -#else -#define port_lock() { \ - asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \ -} -#endif - -/** - * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform - * more actions. - * @note In this port this it lowers the base priority to kernel level. - */ -#if CH_OPTIMIZE_SPEED -#define port_unlock() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \ -} -#else -#define port_unlock() { \ - asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \ -} -#endif - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note Same as @p port_lock() in this port. - */ -#define port_lock_from_isr() port_lock() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note Same as @p port_unlock() in this port. - */ -#define port_unlock_from_isr() port_unlock() - -/** - * @brief Disables all the interrupt sources. - * @note Of course non maskable interrupt sources are not included. - * @note In this port it disables all the interrupt sources by raising - * the priority mask to level 0. - */ -#define port_disable() asm volatile ("cpsid i" : : : "memory") - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note In this port it raises/lowers the base priority to kernel level. - */ -#define port_suspend() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ - asm volatile ("msr BASEPRI, %0 \n\t" \ - "cpsie i" : : "r" (tmp) : "memory"); \ -} - -/** - * @brief Enables all the interrupt sources. - * @note In this port it lowers the base priority to user level. - */ -#define port_enable() { \ - register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ - asm volatile ("msr BASEPRI, %0 \n\t" \ - "cpsie i" : : "r" (tmp) : "memory"); \ -} - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note Implemented as an inlined @p WFI instruction. - */ -#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) -#define port_wait_for_interrupt() { \ - asm volatile ("wfi" : : : "memory"); \ -} -#else -#define port_wait_for_interrupt() -#endif - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * @note Implemented as inlined code for performance reasons. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__) -#define port_switch(ntp, otp) { \ - register Thread *_ntp asm ("r0") = (ntp); \ - register Thread *_otp asm ("r1") = (otp); \ - asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp) : "memory"); \ -} -#else /* CH_DBG_ENABLE_STACK_CHECK */ -#define port_switch(ntp, otp) { \ - register Thread *_ntp asm ("r0") = (ntp); \ - register Thread *_otp asm ("r1") = (otp); \ - register struct intctx *r13 asm ("r13"); \ - if ((void *)(r13 - 1) < (void *)(_otp + 1)) \ - asm volatile ("movs r0, #0 \n\t" \ - "b chDbgPanic"); \ - asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp) : "memory"); \ -} -#endif /* CH_DBG_ENABLE_STACK_CHECK */ - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); -#if !CH_OPTIMIZE_SPEED - void _port_lock(void); - void _port_unlock(void); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_V7M_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/port.dox b/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/port.dox deleted file mode 100644 index 85b14f5..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/ARMCMx/port.dox +++ /dev/null @@ -1,213 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup ARMCMx ARM Cortex-Mx - * @details This port supports the ARMv6-M and ARMv7-M architectures (all the - * Cortex-Mx cores). - * - * @section ARMCMx_STATES_A System logical states in ARMv6-M - * - Init. This state is represented by the startup code and the - * initialization code before @p chSysInit() is executed. It has not a - * special hardware state associated. - * - Normal. This is the state the system has after executing - * @p chSysInit(). In this state interrupts are enabled. The processor - * is running in thread-privileged mode. - * - Suspended. In this state the interrupt sources are globally - * disabled. The processor is running in thread-privileged mode. In this - * mode this state is not different from the Disabled state. - * - Disabled. In this state the interrupt sources are globally - * disabled. The processor is running in thread-privileged mode. In this - * mode this state is not different from the Suspended state. - * - Sleep. This state is entered with the execution of the specific - * instruction @p wfi. - * - S-Locked. In this state the interrupt sources are globally - * disabled. The processor is running in thread-privileged mode. - * - I-Locked. In this state the interrupt sources are globally - * disabled. The processor is running in exception-privileged mode. - * - Serving Regular Interrupt. In this state the interrupt sources are - * not globally masked but only interrupts with higher priority can preempt - * the current handler. The processor is running in exception-privileged - * mode. - * - Serving Fast Interrupt. This state is not implemented in the - * ARMv6-M implementation. - * - Serving Non-Maskable Interrupt. The Cortex-M3 has a specific - * asynchronous NMI vector and several synchronous fault vectors that can - * be considered belonging to this category. - * - Halted. Implemented as an infinite loop after globally masking all - * the maskable interrupt sources. The ARM state is whatever the processor - * was running when @p chSysHalt() was invoked. - * - * @section ARMCMx_STATES_B System logical states in ARMv7-M - * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM - * Cortex-M3 port: - * - Init. This state is represented by the startup code and the - * initialization code before @p chSysInit() is executed. It has not a - * special hardware state associated. - * - Normal. This is the state the system has after executing - * @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register - * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The - * processor is running in thread-privileged mode. - * - Suspended. In this state the interrupt sources are not globally - * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus - * masking any interrupt source with lower or equal priority. The processor - * is running in thread-privileged mode. - * - Disabled. Interrupt sources are globally masked. The processor - * is running in thread-privileged mode. - * - Sleep. This state is entered with the execution of the specific - * instruction @p wfi. - * - S-Locked. In this state the interrupt sources are not globally - * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus - * masking any interrupt source with lower or equal priority. The processor - * is running in thread-privileged mode. - * - I-Locked. In this state the interrupt sources are not globally - * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus - * masking any interrupt source with lower or equal priority. The processor - * is running in exception-privileged mode. - * - Serving Regular Interrupt. In this state the interrupt sources are - * not globally masked but only interrupts with higher priority can preempt - * the current handler. The processor is running in exception-privileged - * mode. - * - Serving Fast Interrupt. It is basically the same of the SRI state - * but it is not possible to switch to the I-Locked state because fast - * interrupts can preempt the kernel critical zone. - * - Serving Non-Maskable Interrupt. The Cortex-M3 has a specific - * asynchronous NMI vector and several synchronous fault vectors that can - * be considered belonging to this category. - * - Halted. Implemented as an infinite loop after globally masking all - * the maskable interrupt sources. The ARM state is whatever the processor - * was running when @p chSysHalt() was invoked. - * . - * @section ARMCMx_NOTES The ARM Cortex-Mx port notes - * The ARM Cortex-Mx port is organized as follow: - * - The @p main() function is invoked in thread-privileged mode. - * - Each thread has a private process stack, the system has a single main - * stack where all the interrupts and exceptions are processed. - * - The threads are started in thread-privileged mode. - * - Interrupt nesting and the other advanced core/NVIC features are supported. - * . - * @ingroup ports - */ - -/** - * @defgroup ARMCMx_CONF Configuration Options - * @brief ARM Cortex-Mx Configuration Options. - * @details The ARMCMx port allows some architecture-specific configurations - * settings that can be overridden by redefining them in @p chconf.h. - * Usually there is no need to change the default values. - * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used - * by an interrupt handler between the @p extctx and @p intctx - * structures.
- * In the current implementation this value is guaranteed to be zero so - * there is no need to modify this value unless changes are done at the - * interrupts handling code. - * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE - * thread. Usually there is no need to change this value unless inserting - * code in the IDLE thread hook macro. - * - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock - * code. Code running at higher priority levels must not invoke any OS API. - * This setting is specific to the ARMv7-M architecture. - * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler. - * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler. - * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler. - * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the - * @p wfi instruction from within the idle loop. This is defaulted to - * FALSE because it can create problems with some debuggers. Setting this - * option to TRUE reduces the system power requirements. - * . - * @ingroup ARMCMx - */ - -/** - * @defgroup ARMCMx_CORE Core Port Implementation - * @brief ARM Cortex-Mx specific port code, structures and macros. - * - * @ingroup ARMCMx - */ - -/** - * @defgroup ARMCMx_V6M_CORE ARMv6-M Specific Implementation - * @brief ARMv6-M specific port code, structures and macros. - * - * @ingroup ARMCMx_CORE - */ - -/** - * @defgroup ARMCMx_V7M_CORE ARMv7-M Specific Implementation - * @brief ARMv7-M specific port code, structures and macros. - * - * @ingroup ARMCMx_CORE - */ - -/** - * @defgroup ARMCMx_STARTUP Startup Support - * @brief ARM Cortex-Mx startup code support. - * @details ChibiOS/RT provides its own generic startup file for the ARM - * Cortex-Mx port. - * Of course it is not mandatory to use it but care should be taken about the - * startup phase details. - * - *

Startup Process

- * The startup process, as implemented, is the following: - * -# Interrupts are masked globally. - * -# The two stacks are initialized by assigning them the sizes defined in the - * linker script (usually named @p ch.ld). Stack areas are allocated from - * the highest RAM location downward. - * -# An early initialization routine @p hwinit0 is invoked, if the symbol is - * not defined then an empty default routine is executed (weak symbol). - * -# DATA and BSS segments are initialized. - * -# The CPU state is switched to Privileged and the PSP stack is used. - * -# A late initialization routine @p hwinit1 is invoked, if the symbol not - * defined then an empty default routine is executed (weak symbol).
- * This late initialization function is also the proper place for a - * @a bootloader, if your application requires one. - * -# The @p main() function is invoked with the parameters @p argc and @p argv - * set to zero. - * -# Should the @p main() function return a branch is performed to the weak - * symbol MainExitHandler. The default code is an endless empty loop. - * . - *

Expected linker symbols

- * The startup code starts at the symbol @p ResetHandler and expects the - * following symbols to be defined in the linker script: - * - @p __ram_end__ RAM end location +1. - * - @p __main_stack_size__ Exception stack size. - * - @p __process_stack_size__ Process stack size. This is the stack area used - * by the @p main() function. - * - @p _textdata address of the data segment source read only data. - * - @p _data data segment start location. - * - @p _edata data segment end location +1. - * - @p _bss_start BSS start location. - * - @p _bss_end BSS end location +1. - * . - * @ingroup ARMCMx - */ - -/** - * @defgroup ARMCMx_NVIC NVIC Support - * @brief ARM Cortex-Mx NVIC support. - * - * @ingroup ARMCMx - */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/AVR/chcore.c b/ChibiOS_2.0.8/os/ports/GCC/AVR/chcore.c deleted file mode 100644 index 5e4fd1c..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/AVR/chcore.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AVR/chcore.c - * @brief AVR architecture port code. - * - * @addtogroup AVR_CORE - * @{ - */ - -#include "ch.h" - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * @note The function is declared as a weak symbol, it is possible to - * redefine it in your application code. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked, weak)) -#endif -void port_switch(Thread *ntp, Thread *otp) { - - asm volatile ("push r2"); - asm volatile ("push r3"); - asm volatile ("push r4"); - asm volatile ("push r5"); - asm volatile ("push r6"); - asm volatile ("push r7"); -#ifndef CH_CURRP_REGISTER_CACHE - asm volatile ("push r8"); - asm volatile ("push r9"); -#endif - asm volatile ("push r10"); - asm volatile ("push r11"); - asm volatile ("push r12"); - asm volatile ("push r13"); - asm volatile ("push r14"); - asm volatile ("push r15"); - asm volatile ("push r16"); - asm volatile ("push r17"); - asm volatile ("push r28"); - asm volatile ("push r29"); - - asm volatile ("movw r30, r22"); - asm volatile ("in r0, 0x3d"); - asm volatile ("std Z+5, r0"); - asm volatile ("in r0, 0x3e"); - asm volatile ("std Z+6, r0"); - - asm volatile ("movw r30, r24"); - asm volatile ("ldd r0, Z+5"); - asm volatile ("out 0x3d, r0"); - asm volatile ("ldd r0, Z+6"); - asm volatile ("out 0x3e, r0"); - - asm volatile ("pop r29"); - asm volatile ("pop r28"); - asm volatile ("pop r17"); - asm volatile ("pop r16"); - asm volatile ("pop r15"); - asm volatile ("pop r14"); - asm volatile ("pop r13"); - asm volatile ("pop r12"); - asm volatile ("pop r11"); - asm volatile ("pop r10"); -#ifndef CH_CURRP_REGISTER_CACHE - asm volatile ("pop r9"); - asm volatile ("pop r8"); -#endif - asm volatile ("pop r7"); - asm volatile ("pop r6"); - asm volatile ("pop r5"); - asm volatile ("pop r4"); - asm volatile ("pop r3"); - asm volatile ("pop r2"); - asm volatile ("ret"); -} - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected (as example because a programming - * error in the application code that triggers an assertion while in - * debug mode). - * @note The function is declared as a weak symbol, it is possible to - * redefine it in your application code. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - - asm volatile ("sei"); - asm volatile ("movw r24, r4"); - asm volatile ("movw r30, r2"); - asm volatile ("icall"); - asm volatile ("call chThdExit"); -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/AVR/chcore.h b/ChibiOS_2.0.8/os/ports/GCC/AVR/chcore.h deleted file mode 100644 index 4a9c04c..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/AVR/chcore.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AVR/chcore.h - * @brief AVR architecture port macros and structures. - * - * @addtogroup AVR_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -#include -#include - -/** - * @brief If enabled allows the idle thread to enter a low power mode. - */ -#ifndef ENABLE_WFI_IDLE -#define ENABLE_WFI_IDLE 0 -#endif - -/** - * @brief Macro defining the AVR architecture. - */ -#define CH_ARCHITECTURE_AVR - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "AVR" - -/** - * @brief Name of the architecture variant (optional). - */ -#define CH_CORE_VARIANT_NAME "MegaAVR" - -/** - * @brief 8 bits stack and memory alignment enforcement. - */ -typedef uint8_t stkalign_t; - -#if !defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note The field @p _next is not part of the context, it represents the - * offset of the structure relative to the stack pointer. - */ -struct extctx { - uint8_t _next; - uint8_t r31; - uint8_t r30; - uint8_t r27; - uint8_t r26; - uint8_t r25; - uint8_t r24; - uint8_t r23; - uint8_t r22; - uint8_t r21; - uint8_t r20; - uint8_t r19; - uint8_t r18; - uint8_t sr; - uint8_t r1; - uint8_t r0; - uint16_t pc; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - * @note The field @p _next is not part of the context, it represents the - * offset of the structure relative to the stack pointer. - */ -struct intctx { - uint8_t _next; - uint8_t r29; - uint8_t r28; - uint8_t r17; - uint8_t r16; - uint8_t r15; - uint8_t r14; - uint8_t r13; - uint8_t r12; - uint8_t r11; - uint8_t r10; -#ifndef CH_CURRP_REGISTER_CACHE - uint8_t r9; - uint8_t r8; -#endif - uint8_t r7; - uint8_t r6; - uint8_t r5; - uint8_t r4; - uint8_t r3; - uint8_t r2; - uint8_t pcl; - uint8_t pch; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief Platform dependent part of the @p Thread structure. - * @details In the AVR port this structure just holds a pointer to the - * @p intctx structure representing the stack pointer at the time - * of the context switch. - */ -struct context { - struct intctx *sp; -}; -#endif - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.sp = (struct intctx*)((uint8_t *)workspace + wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.sp->r2 = (int)pf; \ - tp->p_ctx.sp->r3 = (int)pf >> 8; \ - tp->p_ctx.sp->r4 = (int)arg; \ - tp->p_ctx.sp->r5 = (int)arg >> 8; \ - tp->p_ctx.sp->pcl = (int)_port_thread_start >> 8; \ - tp->p_ctx.sp->pch = (int)_port_thread_start; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - * @note In this port it is set to 8. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 8 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - * @note In this port the default is 32 bytes per thread. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - (sizeof(struct intctx) - 1) + \ - (sizeof(struct extctx) - 1) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - * @note This code tricks the compiler to save all the specified registers - * by "touching" them. - */ -#define PORT_IRQ_PROLOGUE() { \ - asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24", \ - "r25", "r26", "r27", "r30", "r31"); \ -} - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() { \ - if (chSchIsRescRequiredExI()) \ - chSchDoRescheduleI(); \ -} - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) ISR(id) - -/** - * @brief Port-related initialization code. - * @note This function is empty in this port. - */ -#define port_init() - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform more - * actions. - * @note Implemented as global interrupt disable. - */ -#define port_lock() asm volatile ("cli" : : : "memory") - -/** - * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform more - * actions. - * @note Implemented as global interrupt enable. - */ -#define port_unlock() asm volatile ("sei" : : : "memory") - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note This function is empty in this port. - */ -#define port_lock_from_isr() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note This function is empty in this port. - */ -#define port_unlock_from_isr() - -/** - * @brief Disables all the interrupt sources. - * @note Of course non maskable interrupt sources are not included. - * @note Implemented as global interrupt disable. - */ -#define port_disable() asm volatile ("cli" : : : "memory") - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note Same as @p port_disable() in this port, there is no difference - * between the two states. - */ -#define port_suspend() asm volatile ("cli" : : : "memory") - -/** - * @brief Enables all the interrupt sources. - * @note Implemented as global interrupt enable. - */ -#define port_enable() asm volatile ("sei" : : : "memory") - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note This port function is implemented as inlined code for performance - * reasons. - */ -#if ENABLE_WFI_IDLE != 0 -#define port_wait_for_interrupt() { \ - asm volatile ("sleep" : : : "memory"); \ -} -#else -#define port_wait_for_interrupt() -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_switch(Thread *ntp, Thread *otp); - void port_halt(void); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/AVR/chtypes.h b/ChibiOS_2.0.8/os/ports/GCC/AVR/chtypes.h deleted file mode 100644 index 3fa975e..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/AVR/chtypes.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file AVR/chtypes.h - * @brief AVR architecture port system types. - * - * @addtogroup AVR_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#define __need_ptrdiff_t -#include - -#if !defined(_STDINT_H) && !defined(__STDINT_H_) -#include -#endif - -typedef int8_t bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint8_t tprio_t; /**< Thread priority. */ -typedef int16_t msg_t; /**< Inter-thread message. */ -typedef uint8_t eventid_t; /**< Event Id. */ -typedef uint8_t eventmask_t; /**< Events mask. */ -typedef uint16_t systime_t; /**< System time. */ -typedef int8_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note It uses the "packed" GCC attribute. - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/AVR/port.dox b/ChibiOS_2.0.8/os/ports/GCC/AVR/port.dox deleted file mode 100644 index 7c1816d..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/AVR/port.dox +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup AVR MegaAVR - * @details AVR port details. This section how the ChibiOS/RT features are - * implemented on this architecture. - * - * @section AVR_STATES Mapping of the System States in the AVR port - * The ChibiOS/RT logical @ref system_states are mapped as follow in the AVR - * port: - * - Init. This state is represented by the startup code and the - * initialization code before @p chSysInit() is executed. It has not a - * special hardware state associated. - * - Normal. This is the state the system has after executing - * @p chSysInit(). Interrupts are enabled. - * - Suspended. Interrupts are disabled. - * - Disabled. Interrupts are disabled. This state is equivalent to the - * Suspended state because there are no fast interrupts in this architecture. - * - Sleep. This state is entered with the execution of the specific - * instruction @p sleep. - * - S-Locked. Interrupts are disabled. - * - I-Locked. This state is equivalent to the SRI state, the - * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in - * order to formally change state because this may change). - * - Serving Regular Interrupt. Normal interrupt service code. - * - Serving Fast Interrupt. Not present in this architecture. - * - Serving Non-Maskable Interrupt. Not present in this architecture. - * - Halted. Implemented as an infinite loop with interrupts disabled. - * . - * @section AVR_NOTES The AVR port notes - * - The AVR does not have a dedicated interrupt stack, make sure to reserve - * enough stack space for interrupts in each thread stack. This can be done - * by modifying the @p INT_REQUIRED_STACK macro into - * ./ports/AVR/chcore.h. - * . - * @ingroup ports - */ - -/** - * @defgroup AVR_CONF Configuration Options - * @brief AVR Configuration Options. - * @details The AVR port allows some architecture-specific configurations - * settings that can be overridden by redefining them in @p chconf.h. - * Usually there is no need to change the default values. - * - @p INT_REQUIRED_STACK, this value represent the amount of stack space - * used by the interrupt handlers.
- * The default for this value is @p 32, this space is allocated for each - * thread so be careful in order to not waste precious RAM space.
- * The default value is set into ./os/ports/GCC/AVR/chcore.h. - * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE - * thread. Usually there is no need to change this value unless inserting - * code in the IDLE thread hook macro. - * . - * @ingroup AVR - */ - -/** - * @defgroup AVR_CORE AVR Core Implementation - * @brief AVR specific port code, structures and macros. - * - * @ingroup AVR - * @file AVR/chtypes.h Port types. - * @file AVR/chcore.h Port related structures and macros. - * @file AVR/chcore.c Port related code. - */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/AVR/port.mk b/ChibiOS_2.0.8/os/ports/GCC/AVR/port.mk deleted file mode 100644 index 5cb2e0d..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/AVR/port.mk +++ /dev/null @@ -1,6 +0,0 @@ -# List of the ChibiOS/RT AVR port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/AVR/chcore.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/ports/GCC/AVR diff --git a/ChibiOS_2.0.8/os/ports/GCC/MSP430/chcore.c b/ChibiOS_2.0.8/os/ports/GCC/MSP430/chcore.c deleted file mode 100644 index 0938b8a..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/MSP430/chcore.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/chcore.c - * @brief MSP430 architecture port code. - * - * @addtogroup MSP430_CORE - * @{ - */ - -#include "ch.h" - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * @note The function is declared as a weak symbol, it is possible to - * redefine it in your application code. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -#if !defined(__DOXYGEN__) -__attribute__((naked, weak)) -#endif -void port_switch(Thread *ntp, Thread *otp) { - register struct intctx *sp asm("r1"); - - asm volatile ("push r11 \n\t" \ - "push r10 \n\t" \ - "push r9 \n\t" \ - "push r8 \n\t" \ - "push r7 \n\t" \ - "push r6 \n\t" \ - "push r5 \n\t" \ - "push r4" : : : "memory"); - otp->p_ctx.sp = sp; - sp = ntp->p_ctx.sp; - asm volatile ("pop r4 \n\t" \ - "pop r5 \n\t" \ - "pop r6 \n\t" \ - "pop r7 \n\t" \ - "pop r8 \n\t" \ - "pop r9 \n\t" \ - "pop r10 \n\t" \ - "pop r11 \n\t" \ - "ret" : : "r" (sp) : "memory"); -} - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected (as example because a programming - * error in the application code that triggers an assertion while in - * debug mode). - * @note The function is declared as a weak symbol, it is possible to - * redefine it in your application code. - */ -#if !defined(__DOXYGEN__) -__attribute__((weak)) -#endif -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - - asm volatile ("eint \n\t" \ - "mov r11, r15 \n\t" \ - "call r10 \n\t" \ - "call #chThdExit"); -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/MSP430/chcore.h b/ChibiOS_2.0.8/os/ports/GCC/MSP430/chcore.h deleted file mode 100644 index d89d994..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/MSP430/chcore.h +++ /dev/null @@ -1,295 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/chcore.h - * @brief MSP430 architecture port macros and structures. - * - * @addtogroup MSP430_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -#include -#include - -/** - * @brief Enables the use of a wait state in the idle thread loop. - */ -#ifndef ENABLE_WFI_IDLE -#define ENABLE_WFI_IDLE 0 -#endif - -/** - * @brief Macro defining the MSP430 architecture. - */ -#define CH_ARCHITECTURE_MSP430 - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "MSP430" - -/** - * @brief Name of the architecture variant (optional). - */ -#define CH_CORE_VARIANT_NAME "MSP430" - -/** - * @brief 16 bits stack and memory alignment enforcement. - */ -typedef uint16_t stkalign_t; - -/** - * @brief Generic MSP430 register. - */ -typedef void *regmsp_t; - -#if !defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - */ -struct extctx { - regmsp_t r12; - regmsp_t r13; - regmsp_t r14; - regmsp_t r15; - regmsp_t sr; - regmsp_t pc; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - */ -struct intctx { - regmsp_t r4; - regmsp_t r5; - regmsp_t r6; - regmsp_t r7; - regmsp_t r8; - regmsp_t r9; - regmsp_t r10; - regmsp_t r11; - regmsp_t pc; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief Platform dependent part of the @p Thread structure. - * @details This structure usually contains just the saved stack pointer - * defined as a pointer to a @p intctx structure. - */ -struct context { - struct intctx *sp; -}; -#endif - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.sp->r10 = pf; \ - tp->p_ctx.sp->r11 = arg; \ - tp->p_ctx.sp->pc = _port_thread_start; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 0 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - * @note In this port the default is 32 bytes per thread. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() { \ - if (chSchIsRescRequiredExI()) \ - chSchDoRescheduleI(); \ -} - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) interrupt(id) _vect_##id(void) - -/** - * @brief Port-related initialization code. - * @note This function is empty in this port. - */ -#define port_init() - -/** - * @brief Kernel-lock action. - * @details Usually this function just disables interrupts but may perform more - * actions. - * @note Implemented as global interrupt disable. - */ -#define port_lock() asm volatile ("dint" : : : "memory") - -/** - * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform more - * actions. - * @note Implemented as global interrupt enable. - */ -#define port_unlock() asm volatile ("eint" : : : "memory") - -/** - * @brief Kernel-lock action from an interrupt handler. - * @details This function is invoked before invoking I-class APIs from - * interrupt handlers. The implementation is architecture dependent, - * in its simplest form it is void. - * @note This function is empty in this port. - */ -#define port_lock_from_isr() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @details This function is invoked after invoking I-class APIs from interrupt - * handlers. The implementation is architecture dependent, in its - * simplest form it is void. - * @note This function is empty in this port. - */ -#define port_unlock_from_isr() - -/** - * @brief Disables all the interrupt sources. - * @note Of course non maskable interrupt sources are not included. - * @note Implemented as global interrupt disable. - */ -#define port_disable() asm volatile ("dint" : : : "memory") - -/** - * @brief Disables the interrupt sources below kernel-level priority. - * @note Interrupt sources above kernel level remains enabled. - * @note Same as @p port_disable() in this port, there is no difference - * between the two states. - */ -#define port_suspend() asm volatile ("dint" : : : "memory") - -/** - * @brief Enables all the interrupt sources. - * @note Implemented as global interrupt enable. - */ -#define port_enable() asm volatile ("eint" : : : "memory") - -/** - * @brief Enters an architecture-dependent IRQ-waiting mode. - * @details The function is meant to return when an interrupt becomes pending. - * The simplest implementation is an empty function or macro but this - * would not take advantage of architecture-specific power saving - * modes. - * @note This port function is implemented as inlined code for performance - * reasons. - * @note The port code does not define a low power mode, this macro has to - * be defined externally. The default implementation is a "nop", not - * a real low power mode. - */ -#if ENABLE_WFI_IDLE != 0 -#ifndef port_wait_for_interrupt -#define port_wait_for_interrupt() { \ - asm volatile ("nop" : : : "memory"); \ -} -#endif -#else -#define port_wait_for_interrupt() -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_switch(Thread *ntp, Thread *otp); - void port_halt(void); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/MSP430/chtypes.h b/ChibiOS_2.0.8/os/ports/GCC/MSP430/chtypes.h deleted file mode 100644 index 6bc72a0..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/MSP430/chtypes.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file MSP430/chtypes.h - * @brief MSP430 architecture port system types. - * - * @addtogroup MSP430_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#define __need_ptrdiff_t -#include - -#if !defined(_STDINT_H) && !defined(__STDINT_H_) -#include -#endif - -typedef int16_t bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint16_t tprio_t; /**< Thread priority. */ -typedef int16_t msg_t; /**< Inter-thread message. */ -typedef int16_t eventid_t; /**< Event Id. */ -typedef uint16_t eventmask_t; /**< Events mask. */ -typedef uint16_t systime_t; /**< System time. */ -typedef int16_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note It uses the "packed" GCC attribute. - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/MSP430/port.dox b/ChibiOS_2.0.8/os/ports/GCC/MSP430/port.dox deleted file mode 100644 index f85cfcb..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/MSP430/port.dox +++ /dev/null @@ -1,95 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup MSP430 MSP430 - * @details MSP430 port details. This section how the ChibiOS/RT features are - * implemented on this architecture. - * - * @section MSP430_STATES Mapping of the System States in the MSP430 port - * The ChibiOS/RT logical @ref system_states are mapped as follow in the MSP430 - * port: - * - Init. This state is represented by the startup code and the - * initialization code before @p chSysInit() is executed. It has not a - * special hardware state associated. - * - Normal. This is the state the system has after executing - * @p chSysInit(). Interrupts are enabled. - * - Suspended. Interrupts are disabled. - * - Disabled. Interrupts are disabled. This state is equivalent to the - * Suspended state because there are no fast interrupts in this architecture. - * - Sleep. Not yet implemented. - * - S-Locked. Interrupts are disabled. - * - I-Locked. This state is equivalent to the SRI state, the - * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in - * order to formally change state because this may change). - * - Serving Regular Interrupt. Normal interrupt service code. - * - Serving Fast Interrupt. Not present in this architecture. - * - Serving Non-Maskable Interrupt. The MSP430 has several non - * maskable interrupt sources that can be associated to this state. - * - Halted. Implemented as an infinite loop with interrupts disabled. - * . - * @section MSP430_NOTES The MSP430 port notes - * - The MSP430 does not have a dedicated interrupt stack, make sure to reserve - * enough stack space for interrupts in each thread stack. This can be done - * by modifying the @p INT_REQUIRED_STACK macro into - * ./ports/MSP430/chcore.h. - * - The state of the hardware multiplier is not saved in the thread context, - * make sure to use it in Suspended state (interrupts masked). - * - The port code does not define the switch to a low power mode for the - * idle thread because the MSP430 has several low power modes. You can - * select the proper low power mode for you application by defining the - * macro @p port_wait_for_interrupt(). - * . - * @ingroup ports - */ - -/** - * @defgroup MSP430_CONF Configuration Options - * @brief MSP430 Configuration Options. - * @details The MSP430 port allows some architecture-specific configurations - * settings that can be overridden by redefining them in @p chconf.h. - * Usually there is no need to change the default values. - * - @p INT_REQUIRED_STACK, this value represent the amount of stack space - * used by the interrupt handlers.
- * The default for this value is @p 32, this space is allocated for each - * thread so be careful in order to not waste precious RAM space.
- * The default value is set into ./os/ports/GCC/MSP430/chcore.h. - * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE - * thread. Usually there is no need to change this value unless inserting - * code in the IDLE thread hook macro. - * . - * @ingroup MSP430 - */ - -/** - * @defgroup MSP430_CORE Core Port Implementation - * @brief MSP430 specific port code, structures and macros. - * - * @ingroup MSP430 - * @file MSP430/chtypes.h Port types. - * @file MSP430/chcore.h Port related structures and macros. - * @file MSP430/chcore.c Port related code. - */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/MSP430/port.mk b/ChibiOS_2.0.8/os/ports/GCC/MSP430/port.mk deleted file mode 100644 index 88ec642..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/MSP430/port.mk +++ /dev/null @@ -1,6 +0,0 @@ -# List of the ChibiOS/RT MSP430 port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/MSP430/chcore.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/ports/GCC/MSP430 diff --git a/ChibiOS_2.0.8/os/ports/GCC/MSP430/rules.mk b/ChibiOS_2.0.8/os/ports/GCC/MSP430/rules.mk deleted file mode 100644 index 393340f..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/MSP430/rules.mk +++ /dev/null @@ -1,87 +0,0 @@ -# MSP430 makefile scripts and rules. - -# Automatic compiler options -OPT = $(USE_OPT) -CPPOPT = $(USE_CPPOPT) -ifeq ($(USE_CURRP_CACHING),yes) - OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' -endif -ifeq ($(USE_LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -# Source files groups -SRC = $(CSRC)$(CPPSRC) - -# Object files groups -COBJS = $(CSRC:.c=.o) -CPPOBJS = $(CPPSRC:.cpp=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(COBJS) $(CPPOBJS) - -# Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) - -# Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) - -# Libs -LIBS = $(DLIBS) $(ULIBS) - -MCFLAGS = -mmcu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) -else - LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(CPPOBJS) : %.o : %.cpp - @echo - $(CPPC) -c $(CPPFLAGS) -I . $(IINCDIR) $< -o $@ - -$(COBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) -I . $(IINCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(CSRC:.c=.lst) $(CPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst) - -rm -f $(PROJECT).elf $(PROJECT).dmp $(PROJECT).map $(PROJECT).hex $(PROJECT).bin - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/SPC56x/ivor.s b/ChibiOS_2.0.8/os/ports/GCC/PPC/SPC56x/ivor.s deleted file mode 100644 index 1caf567..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/SPC56x/ivor.s +++ /dev/null @@ -1,181 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file PPC/ivor.s - * @brief PowerPC IVORx handlers. - * - * @addtogroup PPC_CORE - * @{ - */ -/** @cond never */ - - /* - * INTC registers address. - */ - .equ INTC_IACKR, 0xfff48010 - .equ INTC_EOIR, 0xfff48018 - - .section .handlers - - /* - * IVOR10 handler (Book-E decrementer). - */ - .align 4 - .globl IVOR10 -IVOR10: - /* Creation of the external stack frame (extctx structure).*/ - stwu %sp, -80(%sp) /* Size of the extctx structure.*/ - stw %r0, 32(%sp) /* Saves GPR0. */ - mfSRR0 %r0 - stw %r0, 8(%sp) /* Saves PC. */ - mfSRR1 %r0 - stw %r0, 12(%sp) /* Saves MSR. */ - mfCR %r0 - stw %r0, 16(%sp) /* Saves CR. */ - mfLR %r0 - stw %r0, 20(%sp) /* Saves LR. */ - mfCTR %r0 - stw %r0, 24(%sp) /* Saves CTR. */ - mfXER %r0 - stw %r0, 28(%sp) /* Saves XER. */ - stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ - stw %r4, 40(%sp) - stw %r5, 44(%sp) - stw %r6, 48(%sp) - stw %r7, 52(%sp) - stw %r8, 56(%sp) - stw %r9, 60(%sp) - stw %r10, 64(%sp) - stw %r11, 68(%sp) - stw %r12, 72(%sp) - - /* Reset DIE bit in TSR register.*/ - lis %r3, 0x0800 /* DIS bit mask. */ - mtspr 336, %r3 /* TSR register. */ - - /* System tick handler invokation.*/ - bl chSysTimerHandlerI - bl chSchIsRescRequiredExI - cmpli cr0, %r3, 0 - beq cr0, .ctxrestore - bl chSchDoRescheduleI - b .ctxrestore - - /* - * IVOR4 handler (Book-E external interrupt). - */ - .align 4 - .globl IVOR4 -IVOR4: - /* Creation of the external stack frame (extctx structure).*/ - stwu %sp, -80(%sp) /* Size of the extctx structure.*/ - stw %r0, 32(%sp) /* Saves GPR0. */ - mfSRR0 %r0 - stw %r0, 8(%sp) /* Saves PC. */ - mfSRR1 %r0 - stw %r0, 12(%sp) /* Saves MSR. */ - mfCR %r0 - stw %r0, 16(%sp) /* Saves CR. */ - mfLR %r0 - stw %r0, 20(%sp) /* Saves LR. */ - mfCTR %r0 - stw %r0, 24(%sp) /* Saves CTR. */ - mfXER %r0 - stw %r0, 28(%sp) /* Saves XER. */ - stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ - stw %r4, 40(%sp) - stw %r5, 44(%sp) - stw %r6, 48(%sp) - stw %r7, 52(%sp) - stw %r8, 56(%sp) - stw %r9, 60(%sp) - stw %r10, 64(%sp) - stw %r11, 68(%sp) - stw %r12, 72(%sp) - - /* Software vector address from the INTC register.*/ - lis %r3, INTC_IACKR@h - ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */ - lwz %r3, 0(%r3) /* IACKR register value. */ - lwz %r3, 0(%r3) - mtCTR %r3 /* Software handler address. */ - -#if PPC_USE_IRQ_PREEMPTION - /* Allows preemption while executing the software handler.*/ - wrteei 1 -#endif - - /* Exectes the software handler.*/ - bctrl - -#if PPC_USE_IRQ_PREEMPTION - /* Prevents preemption again.*/ - wrteei 0 -#endif - - /* Informs the INTC that the interrupt has been served.*/ - mbar 0 - lis %r3, INTC_EOIR@h - ori %r3, %r3, INTC_EOIR@l - stw %r3, 0(%r3) /* Writing any value should do. */ - - /* Verifies if a reschedule is required.*/ - bl chSchIsRescRequiredExI - cmpli cr0, %r3, 0 - beq cr0, .ctxrestore - bl chSchDoRescheduleI - - /* Context restore.*/ -.ctxrestore: - lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */ - lwz %r4, 40(%sp) - lwz %r5, 44(%sp) - lwz %r6, 48(%sp) - lwz %r7, 52(%sp) - lwz %r8, 56(%sp) - lwz %r9, 60(%sp) - lwz %r10, 64(%sp) - lwz %r11, 68(%sp) - lwz %r12, 72(%sp) - lwz %r0, 8(%sp) - mtSRR0 %r0 /* Restores PC. */ - lwz %r0, 12(%sp) - mtSRR1 %r0 /* Restores MSR. */ - lwz %r0, 16(%sp) - mtCR %r0 /* Restores CR. */ - lwz %r0, 20(%sp) - mtLR %r0 /* Restores LR. */ - lwz %r0, 24(%sp) - mtCTR %r0 /* Restores CTR. */ - lwz %r0, 28(%sp) - mtXER %r0 /* Restores XER. */ - lwz %r0, 32(%sp) /* Restores GPR0. */ - addi %sp, %sp, 80 /* Back to the previous frame. */ - rfi - -/** @endcond */ -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/SPC56x/vectors.s b/ChibiOS_2.0.8/os/ports/GCC/PPC/SPC56x/vectors.s deleted file mode 100644 index 5c9c33a..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/SPC56x/vectors.s +++ /dev/null @@ -1,1501 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file PPC/SPC56x/vectors.s - * @brief SPC56x vectors table. - * - * @addtogroup PPC_CORE - * @{ - */ -/** @cond never */ - - /* - * BAM info, SWT off, WTE off, VLE off. - */ - .section .bam - .long 0x005A0000 - .long _boot_address - - /* - * Software vectors table. The vectors are accessed from the IVOR4 - * handler only. In order to declare an interrupt handler just create - * a function withe the same name of a vector, the symbol will - * override the weak symbol declared here. - */ - .section .vectors - .align 4 - .globl _vectors -_vectors: - .long vector0 - .long vector1 - .long vector2 - .long vector3 - .long vector4 - .long vector5 - .long vector6 - .long vector7 - .long vector8 - .long vector9 - .long vector10 - .long vector11 - .long vector12 - .long vector13 - .long vector14 - .long vector15 - .long vector16 - .long vector17 - .long vector18 - .long vector19 - .long vector20 - .long vector21 - .long vector22 - .long vector23 - .long vector24 - .long vector25 - .long vector26 - .long vector27 - .long vector28 - .long vector29 - .long vector30 - .long vector31 - .long vector32 - .long vector33 - .long vector34 - .long vector35 - .long vector36 - .long vector37 - .long vector38 - .long vector39 - .long vector40 - .long vector41 - .long vector42 - .long vector43 - .long vector44 - .long vector45 - .long vector46 - .long vector47 - .long vector48 - .long vector49 - .long vector50 - .long vector51 - .long vector52 - .long vector53 - .long vector54 - .long vector55 - .long vector56 - .long vector57 - .long vector58 - .long vector59 - .long vector60 - .long vector61 - .long vector62 - .long vector63 - .long vector64 - .long vector65 - .long vector66 - .long vector67 - .long vector68 - .long vector69 - .long vector70 - .long vector71 - .long vector72 - .long vector73 - .long vector74 - .long vector75 - .long vector76 - .long vector77 - .long vector78 - .long vector79 - .long vector80 - .long vector81 - .long vector82 - .long vector83 - .long vector84 - .long vector85 - .long vector86 - .long vector87 - .long vector88 - .long vector89 - .long vector90 - .long vector91 - .long vector92 - .long vector93 - .long vector94 - .long vector95 - .long vector96 - .long vector97 - .long vector98 - .long vector99 - .long vector100 - .long vector101 - .long vector102 - .long vector103 - .long vector104 - .long vector105 - .long vector106 - .long vector107 - .long vector108 - .long vector109 - .long vector110 - .long vector111 - .long vector112 - .long vector113 - .long vector114 - .long vector115 - .long vector116 - .long vector117 - .long vector118 - .long vector119 - .long vector120 - .long vector121 - .long vector122 - .long vector123 - .long vector124 - .long vector125 - .long vector126 - .long vector127 - .long vector128 - .long vector129 - .long vector130 - .long vector131 - .long vector132 - .long vector133 - .long vector134 - .long vector135 - .long vector136 - .long vector137 - .long vector138 - .long vector139 - .long vector140 - .long vector141 - .long vector142 - .long vector143 - .long vector144 - .long vector145 - .long vector146 - .long vector147 - .long vector148 - .long vector149 - .long vector150 - .long vector151 - .long vector152 - .long vector153 - .long vector154 - .long vector155 - .long vector156 - .long vector157 - .long vector158 - .long vector159 - .long vector160 - .long vector161 - .long vector162 - .long vector163 - .long vector164 - .long vector165 - .long vector166 - .long vector167 - .long vector168 - .long vector169 - .long vector170 - .long vector171 - .long vector172 - .long vector173 - .long vector174 - .long vector175 - .long vector176 - .long vector177 - .long vector178 - .long vector179 - .long vector180 - .long vector181 - .long vector182 - .long vector183 - .long vector184 - .long vector185 - .long vector186 - .long vector187 - .long vector188 - .long vector189 - .long vector190 - .long vector191 - .long vector192 - .long vector193 - .long vector194 - .long vector195 - .long vector196 - .long vector197 - .long vector198 - .long vector199 - .long vector200 - .long vector201 - .long vector202 - .long vector203 - .long vector204 - .long vector205 - .long vector206 - .long vector207 - .long vector208 - .long vector209 - .long vector210 - .long vector211 - .long vector212 - .long vector213 - .long vector214 - .long vector215 - .long vector216 - .long vector217 - .long vector218 - .long vector219 - .long vector220 - .long vector221 - .long vector222 - .long vector223 - .long vector224 - .long vector225 - .long vector226 - .long vector227 - .long vector228 - .long vector229 - .long vector230 - .long vector231 - .long vector232 - .long vector233 - .long vector234 - .long vector235 - .long vector236 - .long vector237 - .long vector238 - .long vector239 - .long vector240 - .long vector241 - .long vector242 - .long vector243 - .long vector244 - .long vector245 - .long vector246 - .long vector247 - .long vector248 - .long vector249 - .long vector250 - .long vector251 - .long vector252 - .long vector253 - .long vector254 - .long vector255 - .long vector256 - .long vector257 - .long vector258 - .long vector259 - .long vector260 - .long vector261 - .long vector262 - .long vector263 - .long vector264 - .long vector265 - .long vector266 - .long vector267 - .long vector268 - .long vector269 - .long vector270 - .long vector271 - .long vector272 - .long vector273 - .long vector274 - .long vector275 - .long vector276 - .long vector277 - .long vector278 - .long vector279 - .long vector280 - .long vector281 - .long vector282 - .long vector283 - .long vector284 - .long vector285 - .long vector286 - .long vector287 - .long vector288 - .long vector289 - .long vector290 - .long vector291 - .long vector292 - .long vector293 - .long vector294 - .long vector295 - .long vector296 - .long vector297 - .long vector298 - .long vector299 - .long vector300 - .long vector301 - .long vector302 - .long vector303 - .long vector304 - .long vector305 - .long vector306 - .long vector307 - .long vector308 - .long vector309 - .long vector310 - .long vector311 - .long vector312 - .long vector313 - .long vector314 - .long vector315 - .long vector316 - .long vector317 - .long vector318 - .long vector319 - .long vector320 - .long vector321 - .long vector322 - .long vector323 - .long vector324 - .long vector325 - .long vector326 - .long vector327 - .long vector328 - .long vector329 - .long vector330 - .long vector331 - .long vector332 - .long vector333 - .long vector334 - .long vector335 - .long vector336 - .long vector337 - .long vector338 - .long vector339 - .long vector340 - .long vector341 - .long vector342 - .long vector343 - .long vector344 - .long vector345 - .long vector346 - .long vector347 - .long vector348 - .long vector349 - .long vector350 - .long vector351 - .long vector352 - .long vector353 - .long vector354 - .long vector355 - .long vector356 - .long vector357 - .long vector358 - .long vector359 - - .text - .align 2 - .weak vector0 -vector0: - - .weak vector1 -vector1: - - .weak vector2 -vector2: - - .weak vector3 -vector3: - - .weak vector4 -vector4: - - .weak vector5 -vector5: - - .weak vector6 -vector6: - - .weak vector7 -vector7: - - .weak vector8 -vector8: - - .weak vector9 -vector9: - - .weak vector10 -vector10: - - .weak vector11 -vector11: - - .weak vector12 -vector12: - - .weak vector13 -vector13: - - .weak vector14 -vector14: - - .weak vector15 -vector15: - - .weak vector16 -vector16: - - .weak vector17 -vector17: - - .weak vector18 -vector18: - - .weak vector19 -vector19: - - .weak vector20 -vector20: - - .weak vector21 -vector21: - - .weak vector22 -vector22: - - .weak vector23 -vector23: - - .weak vector24 -vector24: - - .weak vector25 -vector25: - - .weak vector26 -vector26: - - .weak vector27 -vector27: - - .weak vector28 -vector28: - - .weak vector29 -vector29: - - .weak vector30 -vector30: - - .weak vector31 -vector31: - - .weak vector32 -vector32: - - .weak vector33 -vector33: - - .weak vector34 -vector34: - - .weak vector35 -vector35: - - .weak vector36 -vector36: - - .weak vector37 -vector37: - - .weak vector38 -vector38: - - .weak vector39 -vector39: - - .weak vector40 -vector40: - - .weak vector41 -vector41: - - .weak vector42 -vector42: - - .weak vector43 -vector43: - - .weak vector44 -vector44: - - .weak vector45 -vector45: - - .weak vector46 -vector46: - - .weak vector47 -vector47: - - .weak vector48 -vector48: - - .weak vector49 -vector49: - - .weak vector50 -vector50: - - .weak vector51 -vector51: - - .weak vector52 -vector52: - - .weak vector53 -vector53: - - .weak vector54 -vector54: - - .weak vector55 -vector55: - - .weak vector56 -vector56: - - .weak vector57 -vector57: - - .weak vector58 -vector58: - - .weak vector59 -vector59: - - .weak vector60 -vector60: - - .weak vector61 -vector61: - - .weak vector62 -vector62: - - .weak vector63 -vector63: - - .weak vector64 -vector64: - - .weak vector65 -vector65: - - .weak vector66 -vector66: - - .weak vector67 -vector67: - - .weak vector68 -vector68: - - .weak vector69 -vector69: - - .weak vector70 -vector70: - - .weak vector71 -vector71: - - .weak vector72 -vector72: - - .weak vector73 -vector73: - - .weak vector74 -vector74: - - .weak vector75 -vector75: - - .weak vector76 -vector76: - - .weak vector77 -vector77: - - .weak vector78 -vector78: - - .weak vector79 -vector79: - - .weak vector80 -vector80: - - .weak vector81 -vector81: - - .weak vector82 -vector82: - - .weak vector83 -vector83: - - .weak vector84 -vector84: - - .weak vector85 -vector85: - - .weak vector86 -vector86: - - .weak vector87 -vector87: - - .weak vector88 -vector88: - - .weak vector89 -vector89: - - .weak vector90 -vector90: - - .weak vector91 -vector91: - - .weak vector92 -vector92: - - .weak vector93 -vector93: - - .weak vector94 -vector94: - - .weak vector95 -vector95: - - .weak vector96 -vector96: - - .weak vector97 -vector97: - - .weak vector98 -vector98: - - .weak vector99 -vector99: - - .weak vector100 -vector100: - - .weak vector101 -vector101: - - .weak vector102 -vector102: - - .weak vector103 -vector103: - - .weak vector104 -vector104: - - .weak vector105 -vector105: - - .weak vector106 -vector106: - - .weak vector107 -vector107: - - .weak vector108 -vector108: - - .weak vector109 -vector109: - - .weak vector110 -vector110: - - .weak vector111 -vector111: - - .weak vector112 -vector112: - - .weak vector113 -vector113: - - .weak vector114 -vector114: - - .weak vector115 -vector115: - - .weak vector116 -vector116: - - .weak vector117 -vector117: - - .weak vector118 -vector118: - - .weak vector119 -vector119: - - .weak vector120 -vector120: - - .weak vector121 -vector121: - - .weak vector122 -vector122: - - .weak vector123 -vector123: - - .weak vector124 -vector124: - - .weak vector125 -vector125: - - .weak vector126 -vector126: - - .weak vector127 -vector127: - - .weak vector128 -vector128: - - .weak vector129 -vector129: - - .weak vector130 -vector130: - - .weak vector131 -vector131: - - .weak vector132 -vector132: - - .weak vector133 -vector133: - - .weak vector134 -vector134: - - .weak vector135 -vector135: - - .weak vector136 -vector136: - - .weak vector137 -vector137: - - .weak vector138 -vector138: - - .weak vector139 -vector139: - - .weak vector140 -vector140: - - .weak vector141 -vector141: - - .weak vector142 -vector142: - - .weak vector143 -vector143: - - .weak vector144 -vector144: - - .weak vector145 -vector145: - - .weak vector146 -vector146: - - .weak vector147 -vector147: - - .weak vector148 -vector148: - - .weak vector149 -vector149: - - .weak vector150 -vector150: - - .weak vector151 -vector151: - - .weak vector152 -vector152: - - .weak vector153 -vector153: - - .weak vector154 -vector154: - - .weak vector155 -vector155: - - .weak vector156 -vector156: - - .weak vector157 -vector157: - - .weak vector158 -vector158: - - .weak vector159 -vector159: - - .weak vector160 -vector160: - - .weak vector161 -vector161: - - .weak vector162 -vector162: - - .weak vector163 -vector163: - - .weak vector164 -vector164: - - .weak vector165 -vector165: - - .weak vector166 -vector166: - - .weak vector167 -vector167: - - .weak vector168 -vector168: - - .weak vector169 -vector169: - - .weak vector170 -vector170: - - .weak vector171 -vector171: - - .weak vector172 -vector172: - - .weak vector173 -vector173: - - .weak vector174 -vector174: - - .weak vector175 -vector175: - - .weak vector176 -vector176: - - .weak vector177 -vector177: - - .weak vector178 -vector178: - - .weak vector179 -vector179: - - .weak vector180 -vector180: - - .weak vector181 -vector181: - - .weak vector182 -vector182: - - .weak vector183 -vector183: - - .weak vector184 -vector184: - - .weak vector185 -vector185: - - .weak vector186 -vector186: - - .weak vector187 -vector187: - - .weak vector188 -vector188: - - .weak vector189 -vector189: - - .weak vector190 -vector190: - - .weak vector191 -vector191: - - .weak vector192 -vector192: - - .weak vector193 -vector193: - - .weak vector194 -vector194: - - .weak vector195 -vector195: - - .weak vector196 -vector196: - - .weak vector197 -vector197: - - .weak vector198 -vector198: - - .weak vector199 -vector199: - - .weak vector200 -vector200: - - .weak vector201 -vector201: - - .weak vector202 -vector202: - - .weak vector203 -vector203: - - .weak vector204 -vector204: - - .weak vector205 -vector205: - - .weak vector206 -vector206: - - .weak vector207 -vector207: - - .weak vector208 -vector208: - - .weak vector209 -vector209: - - .weak vector210 -vector210: - - .weak vector211 -vector211: - - .weak vector212 -vector212: - - .weak vector213 -vector213: - - .weak vector214 -vector214: - - .weak vector215 -vector215: - - .weak vector216 -vector216: - - .weak vector217 -vector217: - - .weak vector218 -vector218: - - .weak vector219 -vector219: - - .weak vector220 -vector220: - - .weak vector221 -vector221: - - .weak vector222 -vector222: - - .weak vector223 -vector223: - - .weak vector224 -vector224: - - .weak vector225 -vector225: - - .weak vector226 -vector226: - - .weak vector227 -vector227: - - .weak vector228 -vector228: - - .weak vector229 -vector229: - - .weak vector230 -vector230: - - .weak vector231 -vector231: - - .weak vector232 -vector232: - - .weak vector233 -vector233: - - .weak vector234 -vector234: - - .weak vector235 -vector235: - - .weak vector236 -vector236: - - .weak vector237 -vector237: - - .weak vector238 -vector238: - - .weak vector239 -vector239: - - .weak vector240 -vector240: - - .weak vector241 -vector241: - - .weak vector242 -vector242: - - .weak vector243 -vector243: - - .weak vector244 -vector244: - - .weak vector245 -vector245: - - .weak vector246 -vector246: - - .weak vector247 -vector247: - - .weak vector248 -vector248: - - .weak vector249 -vector249: - - .weak vector250 -vector250: - - .weak vector251 -vector251: - - .weak vector252 -vector252: - - .weak vector253 -vector253: - - .weak vector254 -vector254: - - .weak vector255 -vector255: - - .weak vector256 -vector256: - - .weak vector257 -vector257: - - .weak vector258 -vector258: - - .weak vector259 -vector259: - - .weak vector260 -vector260: - - .weak vector261 -vector261: - - .weak vector262 -vector262: - - .weak vector263 -vector263: - - .weak vector264 -vector264: - - .weak vector265 -vector265: - - .weak vector266 -vector266: - - .weak vector267 -vector267: - - .weak vector268 -vector268: - - .weak vector269 -vector269: - - .weak vector270 -vector270: - - .weak vector271 -vector271: - - .weak vector272 -vector272: - - .weak vector273 -vector273: - - .weak vector274 -vector274: - - .weak vector275 -vector275: - - .weak vector276 -vector276: - - .weak vector277 -vector277: - - .weak vector278 -vector278: - - .weak vector279 -vector279: - - .weak vector280 -vector280: - - .weak vector281 -vector281: - - .weak vector282 -vector282: - - .weak vector283 -vector283: - - .weak vector284 -vector284: - - .weak vector285 -vector285: - - .weak vector286 -vector286: - - .weak vector287 -vector287: - - .weak vector288 -vector288: - - .weak vector289 -vector289: - - .weak vector290 -vector290: - - .weak vector291 -vector291: - - .weak vector292 -vector292: - - .weak vector293 -vector293: - - .weak vector294 -vector294: - - .weak vector295 -vector295: - - .weak vector296 -vector296: - - .weak vector297 -vector297: - - .weak vector298 -vector298: - - .weak vector299 -vector299: - - .weak vector300 -vector300: - - .weak vector301 -vector301: - - .weak vector302 -vector302: - - .weak vector303 -vector303: - - .weak vector304 -vector304: - - .weak vector305 -vector305: - - .weak vector306 -vector306: - - .weak vector307 -vector307: - - .weak vector308 -vector308: - - .weak vector309 -vector309: - - .weak vector310 -vector310: - - .weak vector311 -vector311: - - .weak vector312 -vector312: - - .weak vector313 -vector313: - - .weak vector314 -vector314: - - .weak vector315 -vector315: - - .weak vector316 -vector316: - - .weak vector317 -vector317: - - .weak vector318 -vector318: - - .weak vector319 -vector319: - - .weak vector320 -vector320: - - .weak vector321 -vector321: - - .weak vector322 -vector322: - - .weak vector323 -vector323: - - .weak vector324 -vector324: - - .weak vector325 -vector325: - - .weak vector326 -vector326: - - .weak vector327 -vector327: - - .weak vector328 -vector328: - - .weak vector329 -vector329: - - .weak vector330 -vector330: - - .weak vector331 -vector331: - - .weak vector332 -vector332: - - .weak vector333 -vector333: - - .weak vector334 -vector334: - - .weak vector335 -vector335: - - .weak vector336 -vector336: - - .weak vector337 -vector337: - - .weak vector338 -vector338: - - .weak vector339 -vector339: - - .weak vector340 -vector340: - - .weak vector341 -vector341: - - .weak vector342 -vector342: - - .weak vector343 -vector343: - - .weak vector344 -vector344: - - .weak vector345 -vector345: - - .weak vector346 -vector346: - - .weak vector347 -vector347: - - .weak vector348 -vector348: - - .weak vector349 -vector349: - - .weak vector350 -vector350: - - .weak vector351 -vector351: - - .weak vector352 -vector352: - - .weak vector353 -vector353: - - .weak vector354 -vector354: - - .weak vector355 -vector355: - - .weak vector356 -vector356: - - .weak vector357 -vector357: - - .weak vector358 -vector358: - - .weak vector359 -vector359: - - .globl _unhandled_irq -_unhandled_irq: - b _unhandled_irq - -/** @endcond */ -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/chcore.c b/ChibiOS_2.0.8/os/ports/GCC/PPC/chcore.c deleted file mode 100644 index 8697d0c..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/chcore.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file PPC/chcore.c - * @brief PowerPC architecture port code. - * - * @addtogroup PPC_CORE - * @{ - */ - -#include "ch.h" - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected (as example because a programming - * error in the application code that triggers an assertion while - * in debug mode). - */ -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note The implementation of this code affects directly the context - * switch performance so optimize here as much as you can. - * - * @param[in] ntp the thread to be switched in - * @param[in] otp the thread to be switched out - */ -void port_switch(Thread *ntp, Thread *otp) { - - (void)otp; - (void)ntp; - - asm ("subi %sp, %sp, 80"); /* Size of the intctx structure. */ - asm ("mflr %r0"); - asm ("stw %r0, 84(%sp)"); /* LR into the caller frame. */ - asm ("mfcr %r0"); - asm ("stw %r0, 0(%sp)"); /* CR. */ - asm ("stmw %r14, 4(%sp)"); /* GPR14...GPR31. */ - - asm ("stw %sp, 12(%r4)"); /* Store swapped-out stack. */ - asm ("lwz %sp, 12(%r3)"); /* Load swapped-in stack. */ - - asm ("lmw %r14, 4(%sp)"); /* GPR14...GPR31. */ - asm ("lwz %r0, 0(%sp)"); /* CR. */ - asm ("mtcr %r0"); - asm ("lwz %r0, 84(%sp)"); /* LR from the caller frame. */ - asm ("mtlr %r0"); - asm ("addi %sp, %sp, 80"); /* Size of the intctx structure. */ -} - -/** - * @brief Start a thread by invoking its work function. - * @details If the work function returns @p chThdExit() is automatically - * invoked. - */ -void _port_thread_start(void) { - asm ("wrteei 1"); - asm ("mr %r3, %r31"); /* Thread parameter. */ - asm ("mtctr %r30"); - asm ("bctrl"); /* Invoke thread function. */ - asm ("bl chThdExit"); /* Thread termination on exit. */ -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/chcore.h b/ChibiOS_2.0.8/os/ports/GCC/PPC/chcore.h deleted file mode 100644 index ac349b4..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/chcore.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file PPC/chcore.h - * @brief PowerPC architecture port macros and structures. - * - * @addtogroup PPC_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/* - * Port-related configuration parameters. - */ - -/** - * @brief Enables the use of the @p WFI instruction. - */ -#ifndef ENABLE_WFI_IDLE -#define ENABLE_WFI_IDLE 0 -#endif - -/* Core variants identifiers.*/ -#define PPC_VARIANT_e200z3 3 /**< e200z3 core identifier. */ -#define PPC_VARIANT_e200z4 4 /**< e200z4 core identifier. */ - -/** - * @brief Core variant selector. - * @details This setting affects the predefined architecture strings and - * possibly code paths and structures into the port layer. - */ -#if !defined(PPC_VARIANT) || defined(__DOXYGEN__) -#define PPC_VARIANT PPC_VARIANT_e200z3 -#endif - -/** - * @brief Unique macro for the implemented architecture. - */ -#define CH_ARCHITECTURE_PPC - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "PowerPC" - -/** - * @brief Name of the architecture variant. - */ -#if (PPC_VARIANT == PPC_VARIANT_e200z3) || defined(__DOXYGEN__) -#define CH_CORE_VARIANT_NAME "e200z3" -#elif PPC_VARIANT == PPC_VARIANT_e200z4 -#define CH_CORE_VARIANT_NAME "e200z4" -#else -#error "unknown or unsupported PowerPC variant specified" -#endif - -/** - * @brief Base type for stack and memory alignment. - */ -typedef struct { - uint8_t a[8]; -} stkalign_t __attribute__((aligned(8))); - -/** - * @brief Generic PPC register. - */ -typedef void *regppc_t; - -/** - * @brief Mandatory part of a stack frame. - */ -struct eabi_frame { - regppc_t slink; /**< Stack back link. */ - regppc_t shole; /**< Stack hole for LR storage. */ -}; - -#if !defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note R2 and R13 are not saved because those are assumed to be immutable - * during the system life cycle. - */ -struct extctx { - struct eabi_frame frame; - /* Start of the e_stmvsrrw frame (offset 8).*/ - regppc_t pc; - regppc_t msr; - /* Start of the e_stmvsprw frame (offset 16).*/ - regppc_t cr; - regppc_t lr; - regppc_t ctr; - regppc_t xer; - /* Start of the e_stmvgprw frame (offset 32).*/ - regppc_t r0; - regppc_t r3; - regppc_t r4; - regppc_t r5; - regppc_t r6; - regppc_t r7; - regppc_t r8; - regppc_t r9; - regppc_t r10; - regppc_t r11; - regppc_t r12; - regppc_t padding; - }; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching. - * @note R2 and R13 are not saved because those are assumed to be immutable - * during the system life cycle. - * @note LR is stored in the caller contex so it is not present in this - * structure. - */ -struct intctx { - regppc_t cr; /* Part of it is not volatile... */ - regppc_t r14; - regppc_t r15; - regppc_t r16; - regppc_t r17; - regppc_t r18; - regppc_t r19; - regppc_t r20; - regppc_t r21; - regppc_t r22; - regppc_t r23; - regppc_t r24; - regppc_t r25; - regppc_t r26; - regppc_t r27; - regppc_t r28; - regppc_t r29; - regppc_t r30; - regppc_t r31; - regppc_t padding; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief Platform dependent part of the @p Thread structure. - * @details This structure usually contains just the saved stack pointer - * defined as a pointer to a @p intctx structure. - */ -struct context { - struct intctx *sp; -}; -#endif - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - uint8_t *sp = (uint8_t *)workspace + wsize - sizeof(struct eabi_frame); \ - ((struct eabi_frame *)sp)->slink = 0; \ - ((struct eabi_frame *)sp)->shole = _port_thread_start; \ - tp->p_ctx.sp = (struct intctx *)(sp - sizeof(struct intctx)); \ - tp->p_ctx.sp->r31 = arg; \ - tp->p_ctx.sp->r30 = pf; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 0 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 128 -#endif - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * @brief Kernel port layer initialization. - * @details IVPR4 and IVPR10 initialization, INTC_IACKR_PRC0 initialization. - */ -#define port_init() { \ - asm volatile ("li %r3, IVOR4@l \t\n" \ - "mtIVOR4 %r3 \t\n" \ - "li %r3, IVOR10@l \t\n" \ - "mtIVOR10 %r3"); \ -} - -/** - * @details Implemented as global interrupt disable. - */ -#define port_lock() asm volatile ("wrteei 0" : : : "memory") - -/** - * @details Implemented as global interrupt enable. - */ -#define port_unlock() asm volatile("wrteei 1" : : : "memory") - -/** - * @details Implemented as global interrupt disable. - */ -#define port_lock_from_isr() /*asm ("wrteei 0")*/ - -/** - * @details Implemented as global interrupt enable. - */ -#define port_unlock_from_isr() /*asm ("wrteei 1")*/ - -/** - * @details Implemented as global interrupt disable. - */ -#define port_disable() asm volatile ("wrteei 0" : : : "memory") - -/** - * @details Same as @p port_disable() in this port, there is no difference - * between the two states. - */ -#define port_suspend() asm volatile ("wrteei 0" : : : "memory") - -/** - * @details Implemented as global interrupt enable. - */ -#define port_enable() asm volatile ("wrteei 1" : : : "memory") - -/** - * @details This port function is implemented as inlined code for performance - * reasons. - */ -#if ENABLE_WFI_IDLE != 0 -#ifndef port_wait_for_interrupt -#define port_wait_for_interrupt() { \ - asm volatile ("wait" : : : "memory"); \ -} -#endif -#else -#define port_wait_for_interrupt() -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); - void port_switch(Thread *ntp, Thread *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/chtypes.h b/ChibiOS_2.0.8/os/ports/GCC/PPC/chtypes.h deleted file mode 100644 index e892ef4..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/chtypes.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file PPC/chtypes.h - * @brief PowerPC architecture port system types. - * - * @addtogroup PPC_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#include - -#if !defined(_STDINT_H) && !defined(__STDINT_H_) -#include -#endif - -/* - * Derived generic types. - */ -typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */ -typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */ -typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */ -typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */ -typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */ -typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */ - -/* - * Kernel types. - */ -typedef int32_t bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Event Id. */ -typedef uint32_t eventmask_t; /**< Events mask. */ -typedef uint32_t systime_t; /**< System time. */ -typedef int32_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note It uses the "packed" GCC attribute. - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/crt0.s b/ChibiOS_2.0.8/os/ports/GCC/PPC/crt0.s deleted file mode 100644 index 250ce29..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/crt0.s +++ /dev/null @@ -1,126 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file PPC/crt0.s - * @brief Generic PowerPC startup file for ChibiOS/RT. - * - * @addtogroup PPC_CORE - * @{ - */ -/** @cond never */ - - .section .text - .align 2 - .globl _boot_address -_boot_address: - /* - * Stack setup. - */ - lis %r1, __ram_end__@h - ori %r1, %r1, __ram_end__@l - li %r0, 0 - stwu %r0, -8(%r1) - /* - * IVPR initialization. - */ - lis %r4, __ivpr_base__@h - mtIVPR %r4 - /* - * Small sections registers initialization. - */ - lis %r2, __sdata2_start__@h - ori %r2, %r2, __sdata2_start__@l - lis %r13, __sdata_start__@h - ori %r13, %r13, __sdata_start__@l - /* - * Early initialization. - */ - bl hwinit0 - /* - * BSS clearing. - */ - lis %r4, __bss_start__@h - ori %r4, %r4, __bss_start__@l - lis %r5, __bss_end__@h - ori %r5, %r5, __bss_end__@l - li %r7, 0 -.bssloop: - cmpl cr0, %r4, %r5 - bge cr0, .bssend - stw %r7, 0(%r4) - addi %r4, %r4, 4 - b .bssloop -.bssend: - /* - * DATA initialization. - */ - lis %r4, __romdata_start__@h - ori %r4, %r4, __romdata_start__@l - lis %r5, __data_start__@h - ori %r5, %r5, __data_start__@l - lis %r6, __data_end__@h - ori %r6, %r6, __data_end__@l -.dataloop: - cmpl cr0, %r5, %r6 - bge cr0, .dataend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .dataloop -.dataend: - /* - * Late initialization. - */ - bl hwinit1 - li %r3, 0 - li %r4, 0 - bl main - b main_exit - - /* - * Default main exit code, infinite loop. - */ - .weak main_exit - .globl main_exit -main_exit: -forever: - b forever - - /* - * Default initialization code, none. - */ - .weak hwinit0 - .globl hwinit0 -hwinit0: - .weak hwinit1 - .globl hwinit1 -hwinit1: - blr - -/** @endcond */ -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/port.dox b/ChibiOS_2.0.8/os/ports/GCC/PPC/port.dox deleted file mode 100644 index d0ee7e7..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/port.dox +++ /dev/null @@ -1,138 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup PPC PowerPC - * @details PowerPC port details. This section describes how the ChibiOS/RT - * features are implemented on this architecture. - * - * @section PPC_STATES Mapping of the System States in the PowerPC port - * The ChibiOS/RT logical @ref system_states are mapped as follow in the - * PowerPC port: - * - Init. This state is represented by the startup code and the - * initialization code before @p chSysInit() is executed. It has not a - * special hardware state associated. - * - Normal. This is the state the system has after executing - * @p chSysInit(). Interrupts are enabled. - * - Suspended. Interrupts are disabled. - * - Disabled. Interrupts are disabled. This state is equivalent to the - * Suspended state because there are no fast interrupts in this architecture. - * - Sleep. This state is entered with the execution of the specific - * instruction @p wait. - * - S-Locked. Interrupts are disabled. - * - I-Locked. This state is equivalent to the SRI state, the - * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in - * order to formally change state because this may change). - * - Serving Regular Interrupt. Normal interrupt service code. - * - Serving Fast Interrupt. Not present in this architecture. - * - Serving Non-Maskable Interrupt. The PowerPC has several non - * maskable interrupt sources that can be associated to this state. - * - Halted. Implemented as an infinite loop with interrupts disabled. - * . - * @section PPC_NOTES The PowerPC port notes - * The PowerPC port is organized as follow: - * - The @p main() function is invoked in privileged mode. - * - Each thread has a private stack with extra storage for interrupts - * servicing. - * - The Book-E Decrementer Timer, mapped on IVOR10, is used for system tick. - * - Interrupt nesting is not currently supported. - * . - * @ingroup ports - */ - -/** - * @defgroup PPC_CONF Configuration Options - * @brief PowerPC Configuration Options. - * @details The PowerPC port allows some architecture-specific configurations - * settings that can be overridden by redefining them in @p chconf.h. - * Usually there is no need to change the default values. - * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used - * by an interrupt handler between the @p extctx and @p intctx - * structures. - * The default for this value is @p 128 bytes, this space is allocated for - * each thread so be careful in order to not waste precious RAM space.
- * The default value is set into ./os/ports/GCC/PPC/chcore.h. - * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE - * thread. Usually there is no need to change this value unless inserting - * code in the IDLE thread hook macro. - * - @p ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the @p wait - * instruction from within the idle loop. This is defaulted to 0 because - * it can create problems with some debuggers. Setting this option to 1 - * reduces the system power requirements. - * . - * @ingroup PPC - */ - -/** - * @defgroup PPC_CORE Core Port Implementation - * @brief PowerPC specific port code, structures and macros. - * - * @ingroup PPC - */ - -/** - * @defgroup PPC_STARTUP Startup Support - * @brief PPC startup code support. - * @details ChibiOS/RT provides its own generic startup file for the PowerPC - * port. - * Of course it is not mandatory to use it but care should be taken about the - * startup phase details. - * - *

Startup Process

- * The startup process, as implemented, is the following: - * -# The stacks pointer is initialized into the area defined in the linker - * script. - * -# The IVPR register is setup according to the linker script. - * -# The R2 and R13 registers are set to pointer to the SDA areas according - * to the EABI specification. - * -# An early initialization routine @p hwinit0 is invoked, if the symbol is - * not defined then an empty default routine is executed (weak symbol). - * -# DATA and BSS segments are initialized. - * -# A late initialization routine @p hwinit1 is invoked, if the symbol not - * defined then an empty default routine is executed (weak symbol).
- * This late initialization function is also the proper place for a - * @a bootloader, if your application requires one. - * -# The @p main() function is invoked with the parameters @p argc and @p argv - * set to zero. - * -# Should the @p main() function return a branch is performed to the weak - * symbol @p main_exit. The default code is an endless empty loop. - * . - *

Expected linker symbols

- * The startup code starts at the symbol @p _boot_address and expects the - * following symbols to be defined in the linker script: - * - @p __ram_end__ RAM end location +1. - * - @p __sdata2_start__ small constants data area - * - @p __sdata_start__ small variables data area - * - @p __romdata_start__ address of the data segment source read only data. - * - @p __data_start__ data segment start location. - * - @p __data_end__ data segment end location +1. - * - @p __bss_start__ BSS start location. - * - @p __bss_end__ BSS end location +1. - * - @p __ivpr_base__ IVPR register initialization address. - * . - * @ingroup PPC - * @file PPC/crt0.s Startup code. - */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/port.mk b/ChibiOS_2.0.8/os/ports/GCC/PPC/port.mk deleted file mode 100644 index a6d8e23..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/port.mk +++ /dev/null @@ -1,6 +0,0 @@ -# List of the ChibiOS/RT PPC port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c - -PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/crt0.s - -PORTINC = ${CHIBIOS}/os/ports/GCC/PPC diff --git a/ChibiOS_2.0.8/os/ports/GCC/PPC/rules.mk b/ChibiOS_2.0.8/os/ports/GCC/PPC/rules.mk deleted file mode 100644 index ab16e50..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/PPC/rules.mk +++ /dev/null @@ -1,87 +0,0 @@ -# PPC e200Z makefile scripts and rules. - -# Automatic compiler options -OPT = $(USE_OPT) -CPPOPT = $(USE_CPPOPT) -ifeq ($(USE_CURRP_CACHING),yes) - OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' -endif -ifeq ($(USE_LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -# Source files groups -SRC = $(CSRC)$(CPPSRC) - -# Object files groups -COBJS = $(CSRC:.c=.o) -CPPOBJS = $(CPPSRC:.cpp=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(COBJS) $(CPPOBJS) - -# Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) - -# Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) - -# Libs -LIBS = $(DLIBS) $(ULIBS) - -MCFLAGS = -mcpu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(CPPOBJS) : %.o : %.cpp - @echo - $(CPPC) -c $(CPPFLAGS) -I . $(IINCDIR) $< -o $@ - -$(COBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) -I . $(IINCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(CSRC:.c=.lst) $(CPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst) - -rm -f $(PROJECT).elf $(PROJECT).dmp $(PROJECT).map $(PROJECT).hex $(PROJECT).bin - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chcore.c b/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chcore.c deleted file mode 100644 index 95b2fe4..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chcore.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @addtogroup SIMIA32_CORE - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -/** - * Performs a context switch between two threads. - * @param otp the thread to be switched out - * @param ntp the thread to be switched in - */ -__attribute__((used)) -static void __dummy(Thread *ntp, Thread *otp) { - (void)ntp; (void)otp; -#if defined(WIN32) - asm volatile (".globl @port_switch@8 \n\t" \ - "@port_switch@8:"); -#elif defined(__APPLE__) - asm volatile (".globl _port_switch \n\t" \ - "_port_switch:"); -#else - asm volatile (".globl port_switch \n\t" \ - "port_switch:"); -#endif - asm volatile ("push %ebp \n\t" \ - "push %esi \n\t" \ - "push %edi \n\t" \ - "push %ebx \n\t" \ - "movl %esp, 12(%edx) \n\t" \ - "movl 12(%ecx), %esp \n\t" \ - "pop %ebx \n\t" \ - "pop %edi \n\t" \ - "pop %esi \n\t" \ - "pop %ebp \n\t" \ - "ret"); -} - -/** - * Halts the system. In this implementation it just exits the simulation. - */ -__attribute__((fastcall)) -void port_halt(void) { - - exit(2); -} - -/** - * Threads return point, it just invokes @p chThdExit(). - */ -void threadexit(void) { - -#if defined(WIN32) || defined (__APPLE__) - asm volatile ("push %eax \n\t" \ - "call _chThdExit"); -#else - asm volatile ("push %eax \n\t" \ - "call chThdExit"); -#endif -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chcore.h b/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chcore.h deleted file mode 100644 index 4154856..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chcore.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @addtogroup SIMIA32_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/** - * Macro defining the a simulated architecture into x86. - */ -#define CH_ARCHITECTURE_SIMIA32 - -/** - * Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "Simulator" - -/** - * @brief Name of the architecture variant (optional). - */ -#define CH_CORE_VARIANT_NAME "x86 (integer only)" - -/** - * 16 bytes stack alignment. - */ -typedef struct { - uint8_t a[16]; -} stkalign_t __attribute__((aligned(16))); - -/** - * Generic x86 register. - */ -typedef void *regx86; - -/** - * Interrupt saved context. - * This structure represents the stack frame saved during a preemption-capable - * interrupt handler. - */ -struct extctx { -}; - -/** - * System saved context. - * @note In this demo the floating point registers are not saved. - */ -struct intctx { - regx86 ebx; - regx86 edi; - regx86 esi; - regx86 ebp; - regx86 eip; -}; - -/** - * Platform dependent part of the @p Thread structure. - * This structure usually contains just the saved stack pointer defined as a - * pointer to a @p intctx structure. - */ -struct context { - struct intctx volatile *esp; -}; - -#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) - -/** - * Platform dependent part of the @p chThdInit() API. - * This code usually setup the context switching frame represented by a - * @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - uint8_t *esp = (uint8_t *)workspace + wsize; \ - APUSH(esp, 0); \ - APUSH(esp, 0); \ - APUSH(esp, 0); \ - APUSH(esp, arg); \ - APUSH(esp, threadexit); \ - esp -= sizeof(struct intctx); \ - ((struct intctx *)esp)->eip = pf; \ - ((struct intctx *)esp)->ebx = 0; \ - ((struct intctx *)esp)->edi = 0; \ - ((struct intctx *)esp)->esi = 0; \ - ((struct intctx *)esp)->ebp = 0; \ - tp->p_ctx.esp = (struct intctx *)esp; \ -} - -/** - * Stack size for the system idle thread. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 256 -#endif - -/** - * Per-thread stack overhead for interrupts servicing, it is used in the - * calculation of the correct working area size. - * It requires stack space because the simulated "interrupt handlers" can - * invoke host library functions inside so it better have a lot of space. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 16384 -#endif - -/** - * Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - - /** - * Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(void *) * 4 + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * Macro used to allocate a thread working area aligned as both position and - * size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/** - * IRQ prologue code, inserted at the start of all IRQ handlers enabled to - * invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to - * invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * IRQ handler function declaration. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * Simulator initialization. - */ -#define port_init() - -/** - * Does nothing in this simulator. - */ -#define port_lock() asm volatile("nop") - -/** - * Does nothing in this simulator. - */ -#define port_unlock() asm volatile("nop") - -/** - * Does nothing in this simulator. - */ -#define port_lock_from_isr() - -/** - * Does nothing in this simulator. - */ -#define port_unlock_from_isr() - -/** - * Does nothing in this simulator. - */ -#define port_disable() - -/** - * Does nothing in this simulator. - */ -#define port_suspend() - -/** - * Does nothing in this simulator. - */ -#define port_enable() - -/** - * In the simulator this does a polling pass on the simulated interrupt - * sources. - */ -#define port_wait_for_interrupt() ChkIntSources() - -#ifdef __cplusplus -extern "C" { -#endif - __attribute__((fastcall)) void port_switch(Thread *ntp, Thread *otp); - __attribute__((fastcall)) void port_halt(void); - void threadexit(void); - void ChkIntSources(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chtypes.h b/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chtypes.h deleted file mode 100644 index 46b7c3c..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/chtypes.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#define __need_ptrdiff_t -#include - -#if !defined(_STDINT_H) && !defined(__STDINT_H_) -#include -#endif - -typedef int32_t bool_t; /**< Fast boolean type. */ -typedef uint8_t tmode_t; /**< Thread flags. */ -typedef uint8_t tstate_t; /**< Thread state. */ -typedef uint8_t trefs_t; /**< Thread references counter. */ -typedef uint32_t tprio_t; /**< Thread priority. */ -typedef int32_t msg_t; /**< Inter-thread message. */ -typedef int32_t eventid_t; /**< Event Id. */ -typedef uint32_t eventmask_t; /**< Events mask. */ -typedef uint32_t systime_t; /**< System time. */ -typedef int32_t cnt_t; /**< Resources counter. */ - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note It is set to use the "const" keyword in this port. - */ -#define ROMCONST const - -/** - * @brief Packed structure modifier (within). - * @note It uses the "packed" GCC attribute. - */ -#define PACK_STRUCT_STRUCT __attribute__((packed)) - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ diff --git a/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/port.mk b/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/port.mk deleted file mode 100644 index 04b9953..0000000 --- a/ChibiOS_2.0.8/os/ports/GCC/SIMIA32/port.mk +++ /dev/null @@ -1,6 +0,0 @@ -# List of the ChibiOS/RT SIMIA32 port files. -PORTSRC = ${CHIBIOS}/os/ports/GCC/SIMIA32/chcore.c - -PORTASM = - -PORTINC = ${CHIBIOS}/os/ports/GCC/SIMIA32 diff --git a/ChibiOS_2.0.8/os/ports/RC/STM8/chcore.c b/ChibiOS_2.0.8/os/ports/RC/STM8/chcore.c deleted file mode 100644 index 186a9aa..0000000 --- a/ChibiOS_2.0.8/os/ports/RC/STM8/chcore.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file RC/STM8/chcore.c - * @brief STM8 architecture port code. - * - * @addtogroup STM8_CORE - * @{ - */ -#pragma SRC("tmp.asm") - -#include "ch.h" - -page0 ReadyList rlist; - -/** - * @brief Performs a context switch between two threads. - * - * @param otp the thread to be switched out - */ -void _port_switch(Thread *otp) { - - (void)otp; - /* Asm because unoptimal code would generated by using _getSP_().*/ -#pragma ASM - LDW Y,SP ; old context pointer - LDW (5,X),Y ; SP saved in otp->p_ctx.sp - LDW X,rlist + 5 ; r_current (currp) field - LDW X,(5,X) ; currp->p_ctx.sp - LDW SP,X ; new context pointer -#pragma ENDASM -} - -/** - * @brief Thread start code. - */ -void _port_thread_start(void) { - -#pragma ASM - RIM - POPW X -#pragma ENDASM -} - -/** - * @brief Halts the system. - * @details This function is invoked by the operating system when an - * unrecoverable error is detected (as example because a programming - * error in the application code that triggers an assertion while in - * debug mode). - */ -void port_halt(void) { - - port_disable(); - while (TRUE) { - } -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/RC/STM8/chcore.h b/ChibiOS_2.0.8/os/ports/RC/STM8/chcore.h deleted file mode 100644 index bfe3853..0000000 --- a/ChibiOS_2.0.8/os/ports/RC/STM8/chcore.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file RC/STM8/chcore.h - * @brief STM8 architecture port macros and structures. - * - * @addtogroup STM8_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -#include - -/*===========================================================================*/ -/* Port configurable parameters. */ -/*===========================================================================*/ - -/** - * @brief Enables the use of the WFI instruction in the idle thread loop. - */ -#ifndef STM8_ENABLE_WFI_IDLE -#define STM8_ENABLE_WFI_IDLE FALSE -#endif - -/*===========================================================================*/ -/* Port exported info. */ -/*===========================================================================*/ - -/** - * @brief Unique macro for the implemented architecture. - */ -#define CH_ARCHITECTURE_STM8 - -/** - * @brief Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "STM8" - -/*===========================================================================*/ -/* Port implementation part. */ -/*===========================================================================*/ - -/** - * @brief Base type for stack alignment. - * @note No alignment constraints so uint8_t. - */ -typedef uint8_t stkalign_t; - -/** - * @brief Generic STM8 function pointer. - * @note It is used to allocate the proper size for return addresses in - * context-related structures. - */ -typedef void (*stm8func_t)(void); - -#if !defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note The structure requires one dummy field at its start because the - * stack is handled as preincremented/postdecremented. - */ -struct extctx { - uint8_t _next; - uint16_t cx; - uint16_t bx; - uint8_t cc; - uint8_t a; - uint16_t x; - uint16_t y; - uint8_t pce; - uint8_t pch; - uint8_t pcl; -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switching.. - * @note The structure requires one dummy field at its start because the - * stack is handled as preincremented/postdecremented. - */ -struct intctx { - uint8_t _next; - stm8func_t pc; /* Function pointer sized return address. */ -}; -#endif - -#if !defined(__DOXYGEN__) -/** - * @brief Platform dependent part of the @p Thread structure. - * @details This structure usually contains just the saved stack pointer - * defined as a pointer to a @p intctx structure. - */ -struct context { - struct intctx *sp; -}; -#endif - -/** - * @brief Start context. - * @details This context is the stack organization for the trampoline code - * @p _port_thread_start(). - */ -struct stm8_startctx { - uint8_t _next; - stm8func_t ts; /* Trampoline address. */ - void *arg; /* Thread argument. */ - stm8func_t pc; /* Thread function address. */ - stm8func_t ret; /* chThdExit() address. */ -}; - -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - struct stm8_startctx *scp; \ - scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize - \ - sizeof(struct stm8_startctx)); \ - scp->ts = _port_thread_start; \ - scp->arg = arg; \ - scp->pc = (stm8func_t)pf; \ - scp->ret = (stm8func_t)chThdExit; \ - tp->p_ctx.sp = (struct intctx *)scp; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p INT_REQUIRED_STACK. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 0 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 32 -#endif - -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - -/** - * @brief Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - (sizeof(struct intctx) - 1) + \ - (sizeof(struct extctx) - 1) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] - -/** - * @brief IRQ prologue code. - * @details This macro must be inserted at the start of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * @brief IRQ epilogue code. - * @details This macro must be inserted at the end of all IRQ handlers - * enabled to invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() { \ - if (chSchIsRescRequiredExI()) \ - chSchDoRescheduleI(); \ -} - -/** - * @brief IRQ handler function declaration. - * @note @p id can be a function name or a vector number depending on the - * port implementation. - */ -#define PORT_IRQ_HANDLER(id) void irq##id(void) interrupt id - -/** - * @brief Port-related initialization code. - * @note None in this port. - */ -#define port_init() - -/** - * @brief Kernel-lock action. - * @note Implemented as global interrupts disable. - */ -#define port_lock() _sim_() - -/** - * @brief Kernel-unlock action. - * @note Implemented as global interrupts enable. - */ -#define port_unlock() _rim_() - -/** - * @brief Kernel-lock action from an interrupt handler. - * @note This function is empty in this port. - */ -#define port_lock_from_isr() - -/** - * @brief Kernel-unlock action from an interrupt handler. - * @note This function is empty in this port. - */ -#define port_unlock_from_isr() - -/** - * @brief Disables all the interrupt sources. - * @note Implemented as global interrupts disable. - * @note Of course non maskable interrupt sources are not included. - */ -#define port_disable() _sim_() - -/** - * @brief Disables the interrupt sources that are not supposed to preempt - * the kernel. - * @note Same as @p port_disable() in this port, there is no difference - * between the two states. - */ -#define port_suspend() _sim_() - -/** - * @brief Enables all the interrupt sources. - * @note Implemented as global interrupt enable. - */ -#define port_enable() _rim_() - -/** - * @brief Enters an architecture-dependent halt mode. - * @note Implemented with the specific "wfi" instruction. - */ -#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__) -#define port_wait_for_interrupt() _wfi_() -#else -#define port_wait_for_interrupt() -#endif - -/** - * @brief Performs a context switch between two threads. - * @details This is the most critical code in any port, this function - * is responsible for the context switch between 2 threads. - * @note Implemented as a call to a low level assembler routine. - * - * @param ntp the thread to be switched in - * @param otp the thread to be switched out - */ -#define port_switch(ntp, otp) _port_switch(otp) - -#ifdef __cplusplus -extern "C" { -#endif - void port_halt(void); - void _port_switch(Thread *otp); - void _port_thread_start(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Scheduler captured code. */ -/*===========================================================================*/ - -#define PORT_OPTIMIZED_RLIST_VAR -#define PORT_OPTIMIZED_RLIST_EXT -#define PORT_OPTIMIZED_READYLIST_STRUCT - -typedef struct { - ThreadsQueue r_queue; - tprio_t r_prio; - Thread *r_current; -#if CH_USE_REGISTRY - Thread *r_newer; - Thread *r_older; -#endif - /* End of the fields shared with the Thread structure.*/ -#if CH_TIME_QUANTUM > 0 - cnt_t r_preempt; -#endif -} ReadyList; - -extern page0 ReadyList rlist; - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/RC/STM8/chtypes.h b/ChibiOS_2.0.8/os/ports/RC/STM8/chtypes.h deleted file mode 100644 index 2897671..0000000 --- a/ChibiOS_2.0.8/os/ports/RC/STM8/chtypes.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file STM8/chtypes.h - * @brief STM8 port system types. - * - * @addtogroup STM8_CORE - * @{ - */ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#include - -//#if !defined(_STDINT_H) && !defined(__STDINT_H_) -//#include -//#endif - -typedef unsigned char uint8_t; /**< C99-style 8 bits unsigned. */ -typedef signed char int8_t; /**< C99-style 8 bits signed. */ -typedef unsigned int uint16_t; /**< C99-style 16 bits unsigned. */ -typedef signed int int16_t; /**< C99-style 16 bits signed. */ -typedef unsigned long uint32_t; /**< C99-style 32 bits unsigned. */ -typedef signed long int32_t; /**< C99-style 32 bits signed. */ -typedef uint8_t uint_fast8_t; /**< C99-style 8 bits unsigned. */ -typedef uint16_t uint_fast16_t; /**< C99-style 16 bits unsigned. */ -typedef uint32_t uint_fast32_t; /**< C99-style 32 bits unsigned. */ - -/** - * @brief Boolean, recommended the fastest signed. - */ -typedef int8_t bool_t; - -/** - * @brief Thread mode flags, uint8_t is ok. - */ -typedef uint8_t tmode_t; - -/** - * @brief Thread state, uint8_t is ok. - */ -typedef uint8_t tstate_t; - -/** - * @brief Thread references counter, uint8_t is ok. - */ -typedef uint8_t trefs_t; - -/** - * @brief Priority, use the fastest unsigned type. - */ -typedef uint8_t tprio_t; - -/** - * @brief Message, use signed pointer equivalent. - */ -typedef int16_t msg_t; - -/** - * @brief Event Id, use fastest signed. - */ -typedef int8_t eventid_t; - -/** - * @brief Event Mask, recommended fastest unsigned. - */ -typedef uint8_t eventmask_t; - -/** - * @brief System Time, recommended fastest unsigned. - */ -typedef uint16_t systime_t; - -/** - * @brief Counter, recommended fastest signed. - */ -typedef int16_t cnt_t; - -/** - * @brief Inline function modifier. - */ -#define INLINE inline - -/** - * @brief ROM constant modifier. - * @note Uses the custom "code" keyword in this port. - */ -#define ROMCONST code - -/** - * @brief Packed structure modifier (within). - * @note Empty in this port. - */ -#define PACK_STRUCT_STRUCT - -/** - * @brief Packed structure modifier (before). - * @note Empty in this port. - */ -#define PACK_STRUCT_BEGIN - -/** - * @brief Packed structure modifier (after). - * @note Empty in this port. - */ -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/ports/RC/STM8/port.dox b/ChibiOS_2.0.8/os/ports/RC/STM8/port.dox deleted file mode 100644 index 6eea647..0000000 --- a/ChibiOS_2.0.8/os/ports/RC/STM8/port.dox +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup STM8 STM8 - * @details STM8 port details. This section how the ChibiOS/RT features are - * implemented on this architecture. - * - * @section STM8_STATES Mapping of the System States in the STM8 port - * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8 - * port: - * - Init. This state is represented by the startup code and the - * initialization code before @p chSysInit() is executed. It has not a - * special hardware state associated. - * - Normal. This is the state the system has after executing - * @p chSysInit(). Interrupts are enabled. - * - Suspended. Interrupts are disabled. - * - Disabled. Interrupts are disabled. This state is equivalent to the - * Suspended state because there are no fast interrupts in this architecture. - * - Sleep. Implemented with "wait" instruction insertion in the idle - * loop. - * - S-Locked. Interrupts are disabled. - * - I-Locked. This state is equivalent to the SRI state, the - * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in - * order to formally change state because this may change). - * - Serving Regular Interrupt. Normal interrupt service code. - * - Serving Fast Interrupt. Not present in this architecture. - * - Serving Non-Maskable Interrupt. The STM8 ha non - * maskable interrupt sources that can be associated to this state. - * - Halted. Implemented as an infinite loop with interrupts disabled. - * . - * @section STM8_NOTES The STM8 port notes - * - The STM8 does not have a dedicated interrupt stack, make sure to reserve - * enough stack space for interrupts in each thread stack. This can be done - * by modifying the @p INT_REQUIRED_STACK macro into - * ./os/ports/RC/STM8/chcore.h. - * - The kernel currently supports only the small memory model so the - * kernel files should be loaded in the first 64K. Note that this is not - * a problem because upper addresses can be used by the user code, the - * kernel can context switch code running there. - * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported - * because the missing support of the @p inline "C" keyword in the - * compiler. - * . - * @ingroup ports - */ - -/** - * @defgroup STM8_CONF Configuration Options - * @brief STM8 Configuration Options. - * @details The STM8 port allows some architecture-specific configurations - * settings that can be specified externally, as example on the compiler - * command line: - * - @p INT_REQUIRED_STACK, this value represent the amount of stack space - * used by the interrupt handlers.
- * The default for this value is @p 32, this space is allocated for each - * thread so be careful in order to not waste precious RAM space.
- * The default value is set into ./os/ports/RC/STM8/chcore.h. - * . - * @ingroup STM8 - */ - -/** - * @defgroup STM8_CORE Core Port Implementation - * @brief STM8 specific port code, structures and macros. - * - * @ingroup STM8 - * @file STM8/chtypes.h Port types. - * @file STM8/chcore.h Port related structures and macros. - * @file STM8/chcore.c Port related code. - */ diff --git a/ChibiOS_2.0.8/os/ports/ports.dox b/ChibiOS_2.0.8/os/ports/ports.dox deleted file mode 100644 index 7fcb103..0000000 --- a/ChibiOS_2.0.8/os/ports/ports.dox +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup ports Ports - * This section describes the technical details of the various supported - * ChibiOS/RT ports. - */ - diff --git a/ChibiOS_2.0.8/os/various/ch.cpp b/ChibiOS_2.0.8/os/various/ch.cpp deleted file mode 100644 index 2e46966..0000000 --- a/ChibiOS_2.0.8/os/various/ch.cpp +++ /dev/null @@ -1,342 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/** - * @file ch.cpp - * @brief C++ wrapper code. - * @addtogroup cpp_library - * @{ - */ - -#include "ch.hpp" - -namespace chibios_rt { - - /*------------------------------------------------------------------------* - * chibios_rt::System * - *------------------------------------------------------------------------*/ - void System::Init(void) { - - chSysInit(); - } - - void System::Lock(void) { - - chSysLock(); - } - - void System::Unlock(void) { - - chSysUnlock(); - } - - systime_t System::GetTime(void) { - - return chTimeNow(); - } - - /*------------------------------------------------------------------------* - * chibios_rt::Timer * - *------------------------------------------------------------------------*/ - void Timer::Set(systime_t time, vtfunc_t vtfunc, void *par) { - - chVTSetI(&timer, time, vtfunc, par); - } - - void Timer::Reset() { - - chVTResetI(&timer); - } - - bool Timer::IsArmed(void) { - - return chVTIsArmedI(&timer); - } - - /*------------------------------------------------------------------------* - * chibios_rt::BaseThread * - *------------------------------------------------------------------------*/ - static msg_t thdstart(void *arg) { - - return ((BaseThread *)arg)->Main(); - } - - BaseThread::BaseThread(void *workspace, size_t wsize, tprio_t prio) { - - thread_ref = chThdCreateStatic(workspace, wsize, prio, thdstart, this); - } - - void BaseThread::Exit(msg_t msg) { - - chThdExit(msg); - } - -#if CH_USE_WAITEXIT - msg_t BaseThread::Wait(void) { - - return chThdWait(thread_ref); - } -#endif /* CH_USE_WAITEXIT */ - - void BaseThread::SetPriority(tprio_t newprio) { - - chThdSetPriority(newprio); - } - - void BaseThread::Resume(void) { - - chThdResume(thread_ref); - } - - void BaseThread::Terminate(void) { - - chThdTerminate(thread_ref); - } - - void BaseThread::Sleep(systime_t n) { - - chThdSleep(n); - } - - void BaseThread::SleepUntil(systime_t time) { - - chThdSleepUntil(time); - } - -#if CH_USE_MESSAGES - msg_t BaseThread::SendMessage(::Thread* tp, msg_t msg) { - - return chMsgSend(tp, msg); - } - - msg_t BaseThread::SendMessage(msg_t msg) { - - return chMsgSend(thread_ref, msg); - } - - msg_t BaseThread::WaitMessage(void) { - - return chMsgWait(); - } - - msg_t BaseThread::GetMessage(void) { - - return chMsgGet(); - } - - void BaseThread::ReleaseMessage(msg_t msg) { - - chMsgRelease(msg); - } - - bool BaseThread::IsPendingMessage(void) { - - return chMsgIsPendingI(currp); - } -#endif /* CH_USE_MESSAGES */ - - msg_t BaseThread::Main(void) { - - return 0; - } - -#if CH_USE_SEMAPHORES - /*------------------------------------------------------------------------* - * chibios_rt::Semaphore * - *------------------------------------------------------------------------*/ - Semaphore::Semaphore(cnt_t n) { - - chSemInit(&sem, n); - } - - void Semaphore::Reset(cnt_t n) { - - chSemReset(&sem, n); - } - - msg_t Semaphore::Wait(void) { - - return chSemWait(&sem); - } - - msg_t Semaphore::WaitTimeout(systime_t time) { - - return chSemWaitTimeout(&sem, time); - } - - void Semaphore::Signal(void) { - - chSemSignal(&sem); - } - -#if CH_USE_SEMSW - msg_t Semaphore::SignalWait(Semaphore *ssem, Semaphore *wsem) { - - return chSemSignalWait(&ssem->sem, &wsem->sem); - } -#endif /* CH_USE_SEMSW */ -#endif /* CH_USE_SEMAPHORES */ - -#if CH_USE_MUTEXES - /*------------------------------------------------------------------------* - * chibios_rt::Mutex * - *------------------------------------------------------------------------*/ - Mutex::Mutex(void) { - - chMtxInit(&mutex); - } - - bool Mutex::TryLock(void) { - - return chMtxTryLock(&mutex); - } - - void Mutex::Lock(void) { - - chMtxLock(&mutex); - } - - void Mutex::Unlock(void) { - - chMtxUnlock(); - } - - void UnlockAll(void) { - - chMtxUnlockAll(); - } - -#if CH_USE_CONDVARS - /*------------------------------------------------------------------------* - * chibios_rt::CondVar * - *------------------------------------------------------------------------*/ - CondVar::CondVar(void) { - - chCondInit(&condvar); - } - - void CondVar::Signal(void) { - - chCondSignal(&condvar); - } - - void CondVar::Broadcast(void) { - - chCondBroadcast(&condvar); - } - - msg_t CondVar::Wait(void) { - - return chCondWait(&condvar); - } - -#if CH_USE_CONDVARS_TIMEOUT - msg_t CondVar::WaitTimeout(systime_t time) { - - return chCondWaitTimeout(&condvar, time); - } -#endif /* CH_USE_CONDVARS_TIMEOUT */ -#endif /* CH_USE_CONDVARS */ -#endif /* CH_USE_MUTEXES */ - -#if CH_USE_EVENTS - /*------------------------------------------------------------------------* - * chibios_rt::Event * - *------------------------------------------------------------------------*/ - Event::Event(void) { - - chEvtInit(&event); - } - - void Event::Register(EventListener *elp, eventid_t eid) { - - chEvtRegister(&event,elp, eid); - } - - void Event::RegisterMask(EventListener *elp, eventmask_t emask) { - - chEvtRegisterMask(&event,elp, emask); - } - - void Event::Unregister(EventListener *elp) { - - chEvtUnregister(&event, elp); - } - - void Event::Broadcast(void) { - - chEvtBroadcast(&event); - } - - eventmask_t Event::Clear(eventmask_t mask) { - - return chEvtClear(mask); - } - - eventmask_t Event::Pend(eventmask_t mask) { - - return chEvtPend(mask); - } - - void Event::Dispatch(const evhandler_t handlers[], eventmask_t mask) { - - chEvtDispatch(handlers, mask); - } - - eventmask_t Event::WaitOne(eventmask_t ewmask) { - - return chEvtWaitOne(ewmask); - } - - eventmask_t Event::WaitAny(eventmask_t ewmask) { - - return chEvtWaitAny(ewmask); - } - - eventmask_t Event::WaitAll(eventmask_t ewmask) { - - return chEvtWaitAll(ewmask); - } - -#if CH_USE_EVENTS_TIMEOUT - eventmask_t Event::WaitOneTimeout(eventmask_t ewmask, systime_t time) { - - return chEvtWaitOneTimeout(ewmask, time); - } - - eventmask_t Event::WaitAnyTimeout(eventmask_t ewmask, systime_t time) { - - return chEvtWaitAnyTimeout(ewmask, time); - } - - eventmask_t Event::WaitAllTimeout(eventmask_t ewmask, systime_t time) { - - return chEvtWaitAllTimeout(ewmask, time); - } -#endif /* CH_USE_EVENTS_TIMEOUT */ -#endif /* CH_USE_EVENTS */ -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/various/ch.hpp b/ChibiOS_2.0.8/os/various/ch.hpp deleted file mode 100644 index 15d90de..0000000 --- a/ChibiOS_2.0.8/os/various/ch.hpp +++ /dev/null @@ -1,625 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file ch.hpp - * @brief C++ wrapper classes and definitions. - * @addtogroup cpp_library - * @{ - */ - -#include - -#ifndef _CH_HPP_ -#define _CH_HPP_ - -namespace chibios_rt { - - /** - * @brief Class encapsulating the base system functionalities. - */ - class System { - public: - /** - * @brief ChibiOS/RT initialization. - * @details The system is initialized, the idle thread is spawned and the - * current instruction flow becomes the main thread with priority - * @p NORMALPRIO. - */ - static void Init(void); - - /** - * @brief Kernel lock. - * - * @note On some ports it is faster to invoke chSysLock() directly because - * inlining. - */ - static void Lock(void); - - /** - * @brief Kernel unlock. - * - * @note On some ports it is faster to invoke chSysUnlock() directly - * because inlining. - */ - static void Unlock(void); - - /** - * @brief Returns the system time as system ticks. - * - * @note the system tick time interval is implementation dependent. - */ - static systime_t GetTime(void); - }; - - /** - * @brief Timer class. - */ - class Timer { - public: - /** - * @brief Embedded @p VirtualTimer structure. - */ - struct ::VirtualTimer timer; - - /** - * @brief Starts the timer. - * - * @param time the time in system ticks - * @param vtfunc the timer callback function - * @param par the parameter for the callback function - * @note It must be called with the interrupts disabled. - * @note The associated function is invoked by an interrupt handler. - */ - void Set(systime_t time, vtfunc_t vtfunc, void *par); - - /** - * @brief Resets the timer. - * - * @note It must be called with the interrupts disabled. - * @note The timer MUST be active when this function is invoked. - */ - void Reset(); - - /** - * @brief Returns the timer status. - * - * @retval TRUE The timer is armed. - * @retval FALSE The timer already fired its callback. - */ - bool IsArmed(void); - }; - - /** - * @brief Base class for a ChibiOS/RT thread. - * @details The thread body is the virtual function @p Main(). - */ - class BaseThread { - public: - /** - * @brief Pointer to the system thread. - */ - ::Thread *thread_ref; - - /** - * @brief Thread constructor. - * @details The thread object is initialized and a system thread is - * started. - * - * @param workspace pointer to the workspace area - * @param wsize size of the workspace area - * @param prio thread priority - */ - BaseThread(void *workspace, size_t wsize, tprio_t prio); - - /** - * @brief Thread exit. - * - * @param msg the exit message - */ - static void Exit(msg_t msg); - -#if CH_USE_WAITEXIT - /** - * @brief Synchronization on Thread exit. - * - * @return the exit message from the thread - */ - msg_t Wait(void); -#endif /* CH_USE_WAITEXIT */ - - /** - * @brief Resumes the thread. - * @details The thread encapsulated into the object is resumed. - */ - void Resume(void); - - /** - * @brief Changes the thread priority. - * - * @param newprio the new priority level - */ - static void SetPriority(tprio_t newprio); - - /** - * @brief Requests thread termination. - * @details A termination flag is pended on the thread, it is thread - * responsibility to detect it and exit. - */ - void Terminate(void); - - /** - * @brief Suspends the thread execution for the specified number of - * system ticks. - * - * @param n the number of system ticks - */ - static void Sleep(systime_t n); - - /** - * @brief Suspends the thread execution until the specified time arrives. - * - * @param time the system time - */ - static void SleepUntil(systime_t time); - -#if CH_USE_MESSAGES - /** - * @brief Sends a message to the thread and returns the answer. - * - * @param tp the target thread - * @param msg the sent message - * @return The returned message. - */ - static msg_t SendMessage(::Thread *tp, msg_t msg); - - /** - * @brief Sends a message to the thread and returns the answer. - * - * @param msg the sent message - * @return The returned message. - */ - msg_t SendMessage(msg_t msg); - - /** - * @brief Waits for a message and returns it. - * - * @return The incoming message. - */ - static msg_t WaitMessage(void); - - /** - * @brief Returns an enqueued message or @p NULL. - * - * @return The incoming message. - * @retval NULL No incoming message. - */ - static msg_t GetMessage(void); - - /** - * @brief Releases the next message in queue with a reply. - * - * @param msg the answer message - */ - static void ReleaseMessage(msg_t msg); - - /** - * @brief Returns true if there is at least one message in queue. - * - * @retval TRUE A message is waiting in queue. - * @retval FALSE A message is not waiting in queue. - */ - static bool IsPendingMessage(void); -#endif /* CH_USE_MESSAGES */ - - /** - * @brief Thread body function. - * - * @return The exit message. - */ - virtual msg_t Main(void); - }; - - /** - * @brief Enhanced threads template class. - * @details This class introduces thread names and static working area - * allocation. - * - * @param N the working area size for the thread class - */ - template - class EnhancedThread : public BaseThread { - protected: - WORKING_AREA(wa, N); // Thread working area. - - public: - /** - * @brief The thread name. - */ - const char *name; - - /** - * @brief Full constructor. - * @details This constructor allows to set a priority level for the new - * thread. - * @param tname the name to be assigned to the thread - * @param prio the priority to be assigned to the thread - */ - EnhancedThread(const char *tname, tprio_t prio) : - BaseThread(wa, sizeof wa, prio) { - - name = tname; - } - - /** - * @brief Simplified constructor. - * @details This constructor allows to create a thread by simply - * specifying a name. In is assumed @p NORMALPRIO as initial priority. - * - * @param tname the name to be assigned to the thread - */ - EnhancedThread(const char *tname) : - BaseThread(wa, sizeof wa, NORMALPRIO) { - - name = tname; - } - }; - -#if CH_USE_SEMAPHORES - /** - * @brief Class encapsulating a semaphore. - */ - class Semaphore { - public: - /** - * @brief Embedded @p ::Semaphore structure. - */ - struct ::Semaphore sem; - - /** - * @brief Semaphore constructor. - * @details The embedded @p ::Semaphore structure is initialized. - * - * @param n the semaphore counter value, must be greater or equal to zero - */ - Semaphore(cnt_t n); - - /** - * @brief Resets a semaphore. - * - * @param n the new semaphore counter value, must be greater or equal to zero - */ - void Reset(cnt_t n); - - /** - * @brief Wait operation on the semaphore. - * - * @retval RDY_OK if the semaphore was signaled or not taken. - * @retval RDY_RESET if the semaphore was reset. - */ - msg_t Wait(void); - - /** - * @brief Wait operation on the semaphore with timeout. - * - * @param time the number of ticks before the operation fails - * @retval RDY_OK if the semaphore was signaled or not taken. - * @retval RDY_RESET if the semaphore was reset. - * @retval RDY_TIMEOUT if the semaphore was not signaled or reset within the - * specified timeout. - */ - msg_t WaitTimeout(systime_t time); - - /** - * @brief Signal operation on the semaphore. - * @details The semaphore is signaled, the next thread in queue, if any, - * is awakened. - */ - void Signal(void); - -#if CH_USE_SEMSW - /** - * @brief Atomic signal and wait operations. - * - * @param ssem pointer to a @p Semaphore to be signaled - * @param wsem pointer to a @p Semaphore to be wait on - * @retval RDY_OK if the semaphore was signaled or not taken. - * @retval RDY_RESET if the semaphore was reset. - */ - static msg_t SignalWait(Semaphore *ssem, Semaphore *wsem); -#endif /* CH_USE_SEMSW */ - }; -#endif /* CH_USE_SEMAPHORES */ - -#if CH_USE_MUTEXES - /** - * @brief Class encapsulating a mutex. - */ - class Mutex { - public: - /** - * @brief Embedded @p ::Mutex structure. - */ - struct ::Mutex mutex; - - /** - * @brief Mutex constructor. - * @details The embedded @p ::Mutex structure is initialized. - */ - Mutex(void); - - /** - * @brief Tries a lock operation on the mutex. - * @retval TRUE if the mutex was successfully acquired - * @retval FALSE if the lock attempt failed. - */ - bool TryLock(void); - - /** - * @brief Locks the mutex. - * @details Performs a lock operation on the mutex, if the mutex is - * already locked then the thread enters the mutex priority queue and - * waits. - */ - void Lock(void); - - /** - * @brief Unlocks the mutex. - * @details Performs an unlock operation on the mutex, the next waiting - * thread, if any, is resumed and locks the mutex. - */ - static void Unlock(void); - - /** - * @brief Unlocks all the mutexes owned by the invoking thread. - * @details This operation is MUCH MORE efficient than releasing - * the mutexes one by one and not just because the call overhead, this - * function does not have any overhead related to the priority inheritance - * mechanism. - */ - static void UnlockAll(void); - }; - -#if CH_USE_CONDVARS - /** - * @brief Class encapsulating a conditional variable. - */ - class CondVar { - public: - /** - * @brief Embedded @p ::CondVar structure. - */ - struct ::CondVar condvar; - - /** - * @brief CondVar constructor. - * @details The embedded @p ::CondVar structure is initialized. - */ - CondVar(void); - - /** - * @brief Signals the CondVar. - * @details The next thread waiting on the @p CondVar, if any, is awakened. - */ - void Signal(void); - - /** - * @brief Broadcasts the CondVar. - * @details All the threads waiting on the @p CondVar, if any, are awakened. - */ - void Broadcast(void); - - /** - * @brief Waits on the CondVar while releasing the controlling mutex. - * - * @return The wakep mode. - * @retval RDY_OK if the condvar was signaled using chCondSignal(). - * @retval RDY_RESET if the condvar was signaled using chCondBroadcast(). - */ - msg_t Wait(void); - -#if CH_USE_CONDVARS_TIMEOUT - /** - * @brief Waits on the CondVar while releasing the controlling mutex. - * - * @param time the number of ticks before the operation fails - * @return The wakep mode. - * @retval RDY_OK if the condvar was signaled using chCondSignal(). - * @retval RDY_RESET if the condvar was signaled using chCondBroadcast(). - * @retval RDY_TIMEOUT if the condvar was not signaled within the specified - * timeout. - */ - msg_t WaitTimeout(systime_t time); -#endif /* CH_USE_CONDVARS_TIMEOUT */ - }; -#endif /* CH_USE_CONDVARS */ -#endif /* CH_USE_MUTEXES */ - -#if CH_USE_EVENTS - /** - * @brief Class encapsulating an event source. - */ - class Event { - public: - /** - * @brief Embedded @p ::EventSource structure. - */ - struct ::EventSource event; - - /** - * @brief Event constructor. - * @details The embedded @p ::EventSource structure is initialized. - */ - Event(void); - - /** - * @brief Registers a listener on the event source. - * - * @param elp pointer to the @p EventListener structure - * @param eid numeric identifier assigned to the Event Listener - */ - void Register(EventListener *elp, eventid_t eid); - - /** - * @brief Registers an Event Listener on an Event Source. - * - * @param elp pointer to the @p EventListener structure - * @param emask the mask of event flags to be pended to the thread when the - * event source is broadcasted - * @note Multiple Event Listeners can specify the same bits to be pended. - */ - void RegisterMask(EventListener *elp, eventmask_t emask); - - /** - * @brief Unregisters a listener. - * @details The specified listeners is no more signaled by the event - * source. - * - * @param elp the listener to be unregistered - */ - void Unregister(EventListener *elp); - - /** - * @brief Broadcasts an event. - * @details All the listeners registered on the event source are signaled. - */ - void Broadcast(void); - - /** - * @brief Clears specified events from the pending events mask. - * - * @param mask the events to be cleared - * @return The pending events that were cleared. - */ - static eventmask_t Clear(eventmask_t mask); - - /** - * @brief Makes an events mask pending in the current thread. - * @details This functon is @b much faster than using @p Broadcast(). - * - * @param mask the events to be pended - * @return The current pending events mask. - */ - static eventmask_t Pend(eventmask_t mask); - - /** - * @brief Invokes the event handlers associated with a mask. - * - * @param mask mask of the events to be dispatched - * @param handlers an array of @p evhandler_t. The array must be - * have indexes from zero up the higher registered event - * identifier. - */ - static void Dispatch(const evhandler_t handlers[], eventmask_t mask); - - /** - * @brief Waits for a single event. - * @details A pending event among those specified in @p ewmask is selected, - * cleared and its mask returned. - * - * @param ewmask mask of the events that the function should wait for, - * @p ALL_EVENTS enables all the events - * @return The mask of the lowest id served and cleared event. - * @note One and only one event is served in the function, the one with the - * lowest event id. The function is meant to be invoked into a loop in - * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have - * an higher priority. - */ - static eventmask_t WaitOne(eventmask_t ewmask); - - /** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p ewmask to become pending then the events are cleared and returned. - * - * @param ewmask mask of the events that the function should wait for, - * @p ALL_EVENTS enables all the events - * @return The mask of the served and cleared events. - */ - static eventmask_t WaitAny(eventmask_t ewmask); - - /** - * @brief Waits for all the specified event flags then clears them. - * @details The function waits for all the events specified in @p ewmask - * to become pending then the events are cleared and returned. - * - * @param ewmask mask of the event ids that the function should wait for - * @return The mask of the served and cleared events. - */ - static eventmask_t WaitAll(eventmask_t ewmask); - -#if CH_USE_EVENTS_TIMEOUT - /** - * @brief Waits for a single event. - * @details A pending event among those specified in @p ewmask is selected, - * cleared and its mask returned. - * @param ewmask mask of the events that the function should wait for, - * @p ALL_EVENTS enables all the events - * @param time the number of ticks before the operation timouts - * @return The mask of the lowest id served and cleared event. - * @retval 0 if the specified timeout expired. - * @note One and only one event is served in the function, the one with the - * lowest event id. The function is meant to be invoked into a loop in - * order to serve all the pending events.
- * This means that Event Listeners with a lower event identifier have - * an higher priority. - */ - static eventmask_t WaitOneTimeout(eventmask_t ewmask, systime_t time); - - /** - * @brief Waits for any of the specified events. - * @details The function waits for any event among those specified in - * @p ewmask to become pending then the events are cleared and returned. - * - * @param ewmask mask of the events that the function should wait for, - * @p ALL_EVENTS enables all the events - * @param time the number of ticks before the operation timouts - * @return The mask of the served and cleared events. - * @retval 0 if the specified timeout expired. - */ - static eventmask_t WaitAnyTimeout(eventmask_t ewmask, systime_t time); - - /** - * @brief Waits for all the specified event flags then clears them. - * @details The function waits for all the events specified in @p ewmask - * to become pending then the events are cleared and returned. - * - * @param ewmask mask of the event ids that the function should wait for - * @param time the number of ticks before the operation timouts - * @return The mask of the served and cleared events. - * @retval 0 if the specified timeout expired. - */ - static eventmask_t WaitAllTimeout(eventmask_t ewmask, systime_t time); - -#endif /* CH_USE_EVENTS_TIMEOUT */ - }; -#endif /* CH_USE_EVENTS */ -} - -#endif /* _CH_HPP_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/various/evtimer.c b/ChibiOS_2.0.8/os/various/evtimer.c deleted file mode 100644 index 38f57c7..0000000 --- a/ChibiOS_2.0.8/os/various/evtimer.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file evtimer.c - * @brief Events Generator Timer code. - * @addtogroup event_timer - * @{ - */ - -#include "ch.h" -#include "evtimer.h" - -static void tmrcb(void *p) { - EvTimer *etp = p; - - chEvtBroadcastI(&etp->et_es); - chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp); -} - -/** - * @brief Starts the timer - * @details If the timer was already running then the function has no effect. - * - * @param etp pointer to an initialized @p EvTimer structure. - */ -void evtStart(EvTimer *etp) { - - chSysLock(); - - if (!chVTIsArmedI(&etp->et_vt)) - chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp); - - chSysUnlock(); -} - -/** - * @brief Stops the timer. - * @details If the timer was already stopped then the function has no effect. - * - * @param etp pointer to an initialized @p EvTimer structure. - */ -void evtStop(EvTimer *etp) { - - chSysLock(); - - if (chVTIsArmedI(&etp->et_vt)) - chVTResetI(&etp->et_vt); - - chSysUnlock(); -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/various/evtimer.h b/ChibiOS_2.0.8/os/various/evtimer.h deleted file mode 100644 index 78ba869..0000000 --- a/ChibiOS_2.0.8/os/various/evtimer.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file evtimer.h - * @brief Events Generator Timer structures and macros. - * @addtogroup event_timer - * @{ - */ - -#ifndef _EVTIMER_H_ -#define _EVTIMER_H_ - -/** - * @brief Event timer structure. - */ -typedef struct { - VirtualTimer et_vt; - EventSource et_es; - systime_t et_interval; -} EvTimer; - -#ifdef __cplusplus -extern "C" { -#endif - void evtStart(EvTimer *etp); - void evtStop(EvTimer *etp); -#ifdef __cplusplus -} -#endif - -/** - * @brief Initializes an @p EvTimer structure. - * - * @param etp the EvTimer structure to be initialized - * @param time the interval in system ticks - */ -#define evtInit(etp, time) { \ - chEvtInit(&(etp)->et_es); \ - (etp)->et_vt.vt_func = NULL; \ - (etp)->et_interval = (time); \ -} - -#endif /* _EVTIMER_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/various/memstreams.c b/ChibiOS_2.0.8/os/various/memstreams.c deleted file mode 100644 index f1a7581..0000000 --- a/ChibiOS_2.0.8/os/various/memstreams.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file memstreams.c - * @brief Memory streams code. - * - * @addtogroup memory_streams - * @{ - */ - -#include - -#include "ch.h" -#include "memstreams.h" - -/* - * @brief Write virtual method implementation. - * - * @param[in] ip pointer to a @p MemoryStream object - * @param[in] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if the - * stream reaches a physical end of file and cannot be - * extended. - */ -static size_t writes(void *ip, const uint8_t *bp, size_t n) { - MemoryStream *msp = ip; - - if (msp->size - msp->eos < n) - n = msp->size - msp->eos; - memcpy(msp->buffer + msp->eos, bp, n); - msp->eos += n; - return n; -} - -/* - * @brief Read virtual method implementation. - * - * @param[in] ip pointer to a @p MemoryStream object - * @param[out] bp pointer to the data buffer - * @param[in] n the maximum amount of data to be transferred - * @return The number of bytes transferred. The return value can - * be less than the specified number of bytes if the - * stream reaches the end of the available data. - */ -static size_t reads(void *ip, uint8_t *bp, size_t n) { - MemoryStream *msp = ip; - - if (msp->eos - msp->offset < n) - n = msp->eos - msp->offset; - memcpy(bp, msp->buffer + msp->offset, n); - msp->offset += n; - return n; -} - -static const struct MemStreamVMT vmt = {writes, reads}; - -/** - * @brief Memory stream object initialization. - * - * @param[out] msp pointer to the @p MemoryStream object to be initialized - * @param[in] buffer pointer to the memory buffer for the memory stream - * @param[in] size total size of the memory stream buffer - * @param[in] eos initial End Of Stream offset. Normally you need to - * put this to zero for RAM buffers or equal to @p size - * for ROM streams. - */ -void msObjectInit(MemoryStream *msp, uint8_t *buffer, size_t size, size_t eos) { - - msp->vmt = &vmt; - msp->buffer = buffer; - msp->size = size; - msp->eos = eos; - msp->offset = 0; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/various/memstreams.h b/ChibiOS_2.0.8/os/various/memstreams.h deleted file mode 100644 index 879998f..0000000 --- a/ChibiOS_2.0.8/os/various/memstreams.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file memstreams.h - * @brief Memory streams structures and macros. - - * @addtogroup memory_streams - * @{ - */ - -#ifndef _MEMSTREAMS_H_ -#define _MEMSTREAMS_H_ - -/** - * @brief @p RamStream specific data. - */ -#define _memory_stream_data \ - _base_sequential_stream_data \ - /* Pointer to the stream buffer.*/ \ - uint8_t *buffer; \ - /* Size of the stream.*/ \ - size_t size; \ - /* Current end of stream.*/ \ - size_t eos; \ - /* Current read offset.*/ \ - size_t offset; - -/** - * @brief @p MemStream virtual methods table. - */ -struct MemStreamVMT { - _base_sequential_stream_methods -}; - -/** - * @extends BaseSequentialStream - * - * @brief Memory stream object. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct MemStreamVMT *vmt; - _memory_stream_data -} MemoryStream; - -#ifdef __cplusplus -extern "C" { -#endif - void msObjectInit(MemoryStream *msp, uint8_t *buffer, size_t size, size_t eos); -#ifdef __cplusplus -} -#endif - -#endif /* _MEMSTREAMS_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/various/shell.c b/ChibiOS_2.0.8/os/various/shell.c deleted file mode 100644 index 35551b4..0000000 --- a/ChibiOS_2.0.8/os/various/shell.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file shell.c - * @brief Simple CLI shell code. - * @addtogroup SHELL - * @{ - */ - -#include -#include - -#include "ch.h" -#include "hal.h" -#include "shell.h" - -#if SHELL_USE_IPRINTF -#define sprintf siprintf -#endif - -/** - * @brief Shell termination event source. - */ -EventSource shell_terminated; - -#if defined(WIN32) -/* - * MinGW does not seem to have this function... - */ -static char *strtok_r(char *str, const char *delim, char **saveptr) { - char *token; - if (str) - *saveptr = str; - token = *saveptr; - - if (!token) - return NULL; - - token += strspn(token, delim); - *saveptr = strpbrk(token, delim); - if (*saveptr) - *(*saveptr)++ = '\0'; - - return *token ? token : NULL; -} -#endif - -static void usage(BaseChannel *chp, char *p) { - - shellPrint(chp, "Usage: "); - shellPrintLine(chp, p); -} - -static void list_commands(BaseChannel *chp, const ShellCommand *scp) { - - while (scp->sc_name != NULL) { - shellPrint(chp, scp->sc_name); - shellPrint(chp, " "); - scp++; - } -} - -static void cmd_info(BaseChannel *chp, int argc, char *argv[]) { - - (void)argv; - if (argc > 0) { - usage(chp, "info"); - return; - } - - shellPrint(chp, "Kernel version: "); - shellPrintLine(chp, CH_KERNEL_VERSION); -#ifdef __GNUC__ - shellPrint(chp, "GCC Version: "); - shellPrintLine(chp, __VERSION__); -#endif - shellPrint(chp, "Architecture: "); - shellPrintLine(chp, CH_ARCHITECTURE_NAME); -#ifdef CH_CORE_VARIANT_NAME - shellPrint(chp, "Core Variant: "); - shellPrintLine(chp, CH_CORE_VARIANT_NAME); -#endif -#ifdef PLATFORM_NAME - shellPrint(chp, "Platform: "); - shellPrintLine(chp, PLATFORM_NAME); -#endif -#ifdef BOARD_NAME - shellPrint(chp, "Board: "); - shellPrintLine(chp, BOARD_NAME); -#endif -} - -static void cmd_systime(BaseChannel *chp, int argc, char *argv[]) { - char buf[12]; - - (void)argv; - if (argc > 0) { - usage(chp, "systime"); - return; - } - sprintf(buf, "%lu", (unsigned long)chTimeNow()); - shellPrintLine(chp, buf); -} - -/** - * @brief Array of the default commands. - */ -static ShellCommand local_commands[] = { - {"info", cmd_info}, - {"systime", cmd_systime}, - {NULL, NULL} -}; - -static bool_t cmdexec(const ShellCommand *scp, BaseChannel *chp, - char *name, int argc, char *argv[]) { - - while (scp->sc_name != NULL) { - if (strcasecmp(scp->sc_name, name) == 0) { - scp->sc_function(chp, argc, argv); - return FALSE; - } - scp++; - } - return TRUE; -} - -/** - * @brief Shell thread function. - * - * @param[in] p pointer to a @p BaseChannel object - * @return Termination reason. - * @retval RDY_OK terminated by command. - * @retval RDY_RESET terminated by reset condition on the I/O channel. - */ -static msg_t shell_thread(void *p) { - int n; - msg_t msg = RDY_OK; - BaseChannel *chp = ((ShellConfig *)p)->sc_channel; - const ShellCommand *scp = ((ShellConfig *)p)->sc_commands; - char *lp, *cmd, *tokp, line[SHELL_MAX_LINE_LENGTH]; - char *args[SHELL_MAX_ARGUMENTS + 1]; - - shellPrintLine(chp, ""); - shellPrintLine(chp, "ChibiOS/RT Shell"); - while (TRUE) { - shellPrint(chp, "ch> "); - if (shellGetLine(chp, line, sizeof(line))) { - shellPrint(chp, "\nlogout"); - break; - } - lp = strtok_r(line, " \009", &tokp); - cmd = lp; - n = 0; - while ((lp = strtok_r(NULL, " \009", &tokp)) != NULL) { - if (n >= SHELL_MAX_ARGUMENTS) { - shellPrintLine(chp, "too many arguments"); - cmd = NULL; - break; - } - args[n++] = lp; - } - args[n] = NULL; - if (cmd != NULL) { - if (strcasecmp(cmd, "exit") == 0) { - if (n > 0) - usage(chp, "exit"); - break; - } - else if (strcasecmp(cmd, "help") == 0) { - if (n > 0) - usage(chp, "help"); - shellPrint(chp, "Commands: help exit "); - list_commands(chp, local_commands); - if (scp != NULL) - list_commands(chp, scp); - shellPrintLine(chp, ""); - } - else if (cmdexec(local_commands, chp, cmd, n, args) && - ((scp == NULL) || cmdexec(scp, chp, cmd, n, args))) { - shellPrint(chp, cmd); - shellPrintLine(chp, " ?"); - } - } - } - chSysLock(); - chEvtBroadcastI(&shell_terminated); - return msg; -} - -/** - * @brief Shell manager initialization. - */ -void shellInit(void) { - - chEvtInit(&shell_terminated); -} - -/** - * @brief Spawns a new shell. - * - * @param[in] scp pointer to a @p ShellConfig object - * @param[in] size size of the shell working area to be allocated - * @param[in] prio the priority level for the new shell - * - * @return A pointer to the shell thread. - * @retval NULL thread creation failed because memory allocation. - */ -Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) { - - return chThdCreateFromHeap(NULL, size, prio, shell_thread, (void *)scp); -} - -/** - * @brief Prints a string. - * - * @param[in] chp pointer to a @p BaseChannel object - * @param[in] msg pointer to the string - */ -void shellPrint(BaseChannel *chp, const char *msg) { - - while (*msg) - chIOPut(chp, *msg++); -} - -/** - * @brief Prints a string with a final newline. - * - * @param[in] chp pointer to a @p BaseChannel object - * @param[in] msg pointer to the string - */ -void shellPrintLine(BaseChannel *chp, const char *msg) { - - shellPrint(chp, msg); - shellPrint(chp, "\r\n"); -} - -/** - * @brief Reads a whole line from the input channel. - * - * @param[in] chp pointer to a @p BaseChannel object - * @param[in] line pointer to the line buffer - * @param[in] size buffer maximum length - * - * @return The operation status. - * @retval TRUE the channel was reset or CTRL-D pressed. - * @retval FALSE operation successful. - */ -bool_t shellGetLine(BaseChannel *chp, char *line, unsigned size) { - char *p = line; - - while (TRUE) { - short c = (short)chIOGet(chp); - if (c < 0) - return TRUE; - if (c == 4) { - shellPrintLine(chp, "^D"); - return TRUE; - } - if (c == 8) { - if (p != line) { - chIOPut(chp, (uint8_t)c); - chIOPut(chp, 0x20); - chIOPut(chp, (uint8_t)c); - p--; - } - continue; - } - if (c == '\r') { - shellPrintLine(chp, ""); - *p = 0; - return FALSE; - } - if (c < 0x20) - continue; - if (p < line + size - 1) { - chIOPut(chp, (uint8_t)c); - *p++ = (char)c; - } - } -} - -/** @} */ diff --git a/ChibiOS_2.0.8/os/various/shell.h b/ChibiOS_2.0.8/os/various/shell.h deleted file mode 100644 index c67d6d5..0000000 --- a/ChibiOS_2.0.8/os/various/shell.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file shell.h - * @brief Simple CLI shell header. - * @addtogroup SHELL - * @{ - */ - -#ifndef _SHELL_H_ -#define _SHELL_H_ - -/** - * @brief Shell maximum input line length. - */ -#if !defined(SHELL_MAX_LINE_LENGTH) || defined(__DOXYGEN__) -#define SHELL_MAX_LINE_LENGTH 64 -#endif - -/** - * @brief Shell maximum arguments per command. - */ -#if !defined(SHELL_MAX_ARGUMENTS) || defined(__DOXYGEN__) -#define SHELL_MAX_ARGUMENTS 4 -#endif - -/** - * @brief Enforces the use of iprintf() on newlib. - */ -#if !defined(SHELL_USE_IPRINTF) || defined(__DOXYGEN__) -#define SHELL_USE_IPRINTF TRUE -#endif - -/** - * @brief Command handler function type. - */ -typedef void (*shellcmd_t)(BaseChannel *chp, int argc, char *argv[]); - -/** - * @brief Custom command entry type. - */ -typedef struct { - const char *sc_name; /**< @brief Command name. */ - shellcmd_t sc_function; /**< @brief Command function. */ -} ShellCommand; - -/** - * @brief Shell descriptor type. - */ -typedef struct { - BaseChannel *sc_channel; /**< @brief I/O channel associated - to the shell. */ - const ShellCommand *sc_commands; /**< @brief Shell extra commands - table. */ -} ShellConfig; - -extern EventSource shell_terminated; - -#ifdef __cplusplus -extern "C" { -#endif - void shellInit(void); - Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio); - void shellPrint(BaseChannel *chp, const char *msg); - void shellPrintLine(BaseChannel *chp, const char *msg); - bool_t shellGetLine(BaseChannel *chp, char *line, unsigned size); -#ifdef __cplusplus -} -#endif - -#endif /* _SHELL_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/os/various/syscalls.c b/ChibiOS_2.0.8/os/various/syscalls.c deleted file mode 100644 index 80510ae..0000000 --- a/ChibiOS_2.0.8/os/various/syscalls.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -/* -* **** This file incorporates work covered by the following copyright and **** -* **** permission notice: **** -* -* Copyright (c) 2009 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* History: -* -* 28.03.09 mifi First Version, based on the original syscall.c from -* newlib version 1.17.0 -* 17.08.09 gdisirio Modified the file for use under ChibiOS/RT -* 15.11.09 gdisirio Added read and write handling -****************************************************************************/ - -#include -#include -#include -#include -#include - -#include "ch.h" -#if defined(STDOUT_SD) || defined(STDIN_SD) -#include "hal.h" -#endif - -/***************************************************************************/ - -int _read_r(struct _reent *r, int file, char * ptr, int len) -{ - (void)r; -#if defined(STDIN_SD) - if (!len || (file != 0)) { - __errno_r(r) = EINVAL; - return -1; - } - len = sdRead(&STDIN_SD, (uint8_t *)ptr, (size_t)len); - return len; -#else - (void)file; - (void)ptr; - (void)len; - __errno_r(r) = EINVAL; - return -1; -#endif -} - -/***************************************************************************/ - -int _lseek_r(struct _reent *r, int file, int ptr, int dir) -{ - (void)r; - (void)file; - (void)ptr; - (void)dir; - - return 0; -} - -/***************************************************************************/ - -int _write_r(struct _reent *r, int file, char * ptr, int len) -{ - (void)r; - (void)file; - (void)ptr; -#if defined(STDOUT_SD) - if (file != 1) { - __errno_r(r) = EINVAL; - return -1; - } - sdWrite(&STDOUT_SD, (uint8_t *)ptr, (size_t)len); -#endif - return len; -} - -/***************************************************************************/ - -int _close_r(struct _reent *r, int file) -{ - (void)r; - (void)file; - - return 0; -} - -/***************************************************************************/ - -caddr_t _sbrk_r(struct _reent *r, int incr) -{ - void *p; - - chDbgCheck(incr > 0, "_sbrk_r"); - - (void)r; - p = chCoreAlloc((size_t)incr); - if (p == NULL) { - __errno_r(r) = ENOMEM; - return (caddr_t)-1; - } - return (caddr_t)p; -} - -/***************************************************************************/ - -int _fstat_r(struct _reent *r, int file, struct stat * st) -{ - (void)r; - (void)file; - - memset(st, 0, sizeof(*st)); - st->st_mode = S_IFCHR; - return 0; -} - -/***************************************************************************/ - -int _isatty_r(struct _reent *r, int fd) -{ - (void)r; - (void)fd; - - return 1; -} - -/*** EOF ***/ diff --git a/ChibiOS_2.0.8/os/various/various.dox b/ChibiOS_2.0.8/os/various/various.dox deleted file mode 100644 index 61d6f37..0000000 --- a/ChibiOS_2.0.8/os/various/various.dox +++ /dev/null @@ -1,75 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup various Various - * @brief Utilities Library. - * @details This is a collection of useful library code that is not part of - * the base kernel services. - *

Notes

- * The library code does not follow the same naming convention of the - * system APIs in order to make very clear that it is not "core" code.
- * The main difference is that library code is not formally tested in the - * test suite but through usage in the various demo applications. - */ - -/** - * @defgroup cpp_library C++ Wrapper - * @brief C++ wrapper module. - * @details This module allows to use the ChibiOS/RT functionalities - * from C++ as classes and objects rather the traditional "C" APIs. - * - * @ingroup various - */ - -/** - * @defgroup memory_streams Memory Streams - * @brief Memory Streams. - * @details This module allows to use a memory area (RAM or ROM) using a - * @ref data_streams interface. - * - * @ingroup various - */ - -/** - * @defgroup event_timer Periodic Events Timer - * @brief Periodic Event Timer. - * @details This timer generates an event at regular intervals. The - * listening threads can use the event to perform time related activities. - * Multiple threads can listen to the same timer. - * - * @ingroup various - */ - -/** - * @defgroup SHELL Command Shell - * @brief Small extendible command line shell. - * @details This module implements a generic extendible command line interface. - * The CLI just requires an I/O channel (@p BaseChannel), more commands can be - * added to the shell using the configuration structure. - * - * @ingroup various - */ diff --git a/ChibiOS_2.0.8/readme.txt b/ChibiOS_2.0.8/readme.txt deleted file mode 100644 index 78dcf0b..0000000 --- a/ChibiOS_2.0.8/readme.txt +++ /dev/null @@ -1,432 +0,0 @@ -***************************************************************************** -*** Files Organization *** -***************************************************************************** - ---{root} - ChibiOS/RT directory. - +--readme.txt - This file. - +--todo.txt - Current plan (development/unstable versions only). - +--license.txt - GPL license text. - +--exception.txt - GPL exception text (stable releases only). - +--boards/ - Board support files. - +--demos/ - Demo projects. - +--docs/ - Documentation. - | +--html/ - HTML documentation. - | +--reports/ - Test reports. - | +--src/ - Documentation source files (required for rebuild). - | +--rsc/ - Documentation resource files (required for rebuild). - | +--index.html - Documentation access. - +--ext/ - External libraries, not part of ChibiOS/RT. - +--os/ - ChibiOS/RT files. - | +--hal/ - Hardware Abstraction Layer. - | | +--include/ - HAL high level headers. - | | +--src/ - HAL high level source. - | | +--platforms/ - HAL low level drivers implementations. - | | | +--AT91SAM7/ - Drivers for AT91SAM7 platform. - | | | +--AVR/ - Drivers for AVR platform. - | | | +--LPC11xx/ - Drivers for LPC11xx platform. - | | | +--LPC13xx/ - Drivers for LPC13xx platform. - | | | +--LPC214x/ - Drivers for LPC214x platform. - | | | +--MSP430/ - Drivers for MSP430 platform. - | | | +--SPC56x/ - Drivers for SPC56x/MPC563xx platforms. - | | | +--STM32/ - Drivers for STM32 platform. - | | | +--STM8/ - Drivers for STM8 platform. - | | | +--Posix/ - Drivers for x86 Linux/OSX simulator platform. - | | | +--Win32/ - Drivers for x86 Win32 simulator platform. - | | +--templates/ - Driver template files. - | | +--meta/ - Driver meta templates. - | +--ports/ - Port files for the various architectures. - | | +--GCC/ - Ports for the GCC compiler. - | | | +--ARM/ - Port files for generic ARM architecture. - | | | +--ARM7/ - Port files for ARM7 architecture. - | | | +--ARMCM3/ - Port files for ARMCMx architectures (ARMv6/7-M). - | | | +--PPC/ - Port files for PowerPC architecture. - | | | +--AVR/ - Port files for AVR architecture. - | | | +--MSP430/ - Port files for MSP430 architecture. - | | | +--SIMIA32/ - Port files for SIMIA32 simulator architecture. - | | +--RC/ - Ports for the Raisonance compiler. - | | +--STM8/ - Port files for STM8 architecture. - | +--kernel/ - Kernel portable files. - | | +--include/ - Kernel headers. - | | +--src/ - Kernel source. - | | +--templates/ - Kernel port template files. - | +--various/ - Various portable support files. - +--test/ - Kernel test suite source code. - | +--coverage/ - Code coverage project. - +--testhal/ - HAL integration test demos. - -***************************************************************************** -*** Releases *** -***************************************************************************** - -*** 2.0.8 *** -- FIX: Fixed failed memory recovery by registry scan, improved the related - test case (bug 3116888). -- FIX: Fixed PWM channels going to ACTIVE state when the pulse width is - set to zero in the STM32 PWM driver (bug 3114481). -- FIX: Fixed PWM channels return to IDLE state in STM32 PWM driver (bug - 3114467). -- CHANGE: Bugs 3114467 and 3114481 have been fixed by backporting the 2.1.x - PWM driver, there is a difference in the PWM callback parameters. - -*** 2.0.7 *** -- FIX: Fixed typo in board name (bug 3113574). -- FIX: Fixed defective event wait functions with timeout (bug 3113443). - -*** 2.0.6 *** -- FIX: Fixed typo in memstreams.h (bug 3089567). -- FIX: Fixed wrong macro check in LPC214x and AT91SAM7 serial drivers (bug - 3088776). -- FIX: Fixed non functioning option SPI_USE_MUTUAL_EXCLUSION=FALSE (bug - 3084764). -- FIX: Fixed wrong macro check in STM32 serial support (but 3078891). -- FIX: Fixed lwIP demo not working (bug 3076354). -- FIX: Fixed non functioning option CH_USE_NESTED_LOCKS (bug 3075544). -- CHANGE: The API chThdInit() has been renamed to chThdCreateI(). - -*** 2.0.5 *** -- FIX: Incorrect AT91SAM7X initialization, thanks Leszek (bug 3075354). -- FIX: Fixed race condition in function chSchGoSleepTimeoutS, thanks Balázs - (bug 3074984). -- FIX: Fixed race condition in threads creation (bug 3069854). -- FIX: Fixed broken CH_DBG_ENABLE_STACK_CHECK option in legacy CM3 port (bug - 3064274). -- FIX: Fixed CAN_USE_SLEEP_MODE setting (bug 3064204). - -*** 2.0.4 *** -- FIX: Fixed potential issue with GCC reorganizing instructions around "asm - volatile" statements (bug 3058731). -- FIX: Fixed reduced ARM7 performance with GCC 4.5.x (bug 3056866). - -*** 2.0.3 *** -- Tests reports regenerated using GCC 4.5.1, small performance improvements - in all benchmarks. -- FIX: Fixed crash of the Posix simulator under Ubuntu 10.4 (bug 3055329). -- FIX: Fixed incorrect PLL2 setting in STM32 HAL (bug 3044770). -- FIX: Fixed wrong check on STM32_HCLK (bug 3044758). -- FIX: Fixed wrong condition check in STM32 PWM driver (bug 3041414). -- FIX: Corrupted IRQ stack in Cortex-Mx port (bug 3041117). -- FIX: Fixed a documentation error regarding the ADC driver function - adcStartConversion() (bug 3039890). -- FIX: Fixed insufficient stack size for idle thread (bug 3033624). -- FIX: Fixed misspelled word in some chioch.h and chstreams.h macros (bug - 3031534). -- FIX: Fixed wrong macro check in the STM32 SPI driver (bug 3028562). - -*** 2.0.2 *** -- FIX: Fixed invalid context restore in MSP430 port (bug 3027975). -- FIX: Fixed STM32 vectors file (bug 3026528). -- FIX: Fixed race condition in STM32 SPI driver (bug 3025854). -- FIX: Fixed H_LOCK and H_UNLOCK redefined with CH_USE_MALLOC_HEAP (bug - 3025549). -- FIX: Added option to enforce the stack alignment to 32 or 64 bits in the - Cortex-Mx port (bug 3025133). -- NEW: Added friendly interrupt vectors names to the STM32 HAL (change request - 3023944). -- CHANGE: Removed the option -mabi=apcs-gnu from all the Cortex-Mx demos. The - option is not compatible with the 64 bits stack alignment now default in - the Cortex-Mx port. Note that the 64 bits alignment has a cost both as - performance and as space but it is the "standard". - -*** 2.0.1 *** -- FIX: Fixed notification order in input queues (bug 3020708). -- FIX: Fixed non functional CH_CURRP_REGISTER_CACHE option in the Cortex-M3 - port (bug 3020702). -- FIX: Fixed non functional CH_DBG_ENABLE_STACK_CHECK option in the Cortex-M3 - caused by GCC 4.5.0, the fix also improves the context switch performance - because GCC 4.5.0 apparently was generating useless instructions within the - very critical context switch code (bug 3019738). -- FIX: Fixed insufficient stack space assigned to the idle thread in - Cortex-M3 port (bug 3019594). -- FIX: Fixed missing check in chIQReadTimeout() and chIQWriteTimeout() (bug - 3019158). -- FIX: Fixed instability in Mutexes subsystem (bug 3019099). -- NEW: Added timers clock macros to the STM32 clock tree HAL driver. - -*** 2.0.0 *** -- NEW: Implemented the concept of thread references, this mechanism ensures - that a dynamic thread's memory is not freed while some other thread still - owns a reference to the thread. Static threads are not affected by the new - mechanism. Two new APIs have been added: chThdAddRef() and chThdRelease(). -- NEW: Now more than one thread can be waiting in chThdWait() as long they - own a reference. -- NEW: Implemented a new threads registry subsystem, the registry allows to - enumerate the active threads at runtime and/or from a debugger. This is - a preparatory step for a dedicated ChibiOS/RT debugger. -- NEW: New chCoreFree() API that returns the core memory left. -- NEW: Added a PowerPC port and demo targeting the SPC563M/MPC563xM - ST/Freescale automotive SOCs. -- NEW: Added STM8 port and demo targeting the Raisonance REva board - with STM8S208RB piggyback. -- NEW: New unified ARM Cortex-Mx port, this port supports both the ARMv6M - and ARMv7-M architectures (Cortex-M0/M1/M3/M4 so far). The new port also - allow to easily add to new Cortex-M implementations by simply adding a - parameters file (cmparams.h). -- NEW: Improved clock initialization for the STM32, now it is possible to - configure the clock using any clock source and any HSE frequency. -- NEW: The STM32 clock tree parameters and checks are now calculated into - a separate file in order to support multiple clock trees for different - sub-families of the STM32 platform. -- NEW: Added separated clock trees for the STM32 LD/MD/HD sub-family and - the CL sub-family. Now the selection of the sub-family is done in the - board.h file, there is no more the need to put -DSTM32F10X_xx into - the makefile. -- NEW: Added support for STM32/HD/CL UART4 and UART5, thanks Egon for the - patch. -- NEW: Embedded Artists LPCxpresso Base Board support files added. -- NEW: LPC11xx support, drivers (Serial, PAL, HAL) and demo. -- NEW: LPC13xx support, drivers (Serial, PAL, HAL), demo and reports. -- NEW: The port layer now can "capture" the implementation of individual - scheduler API functions in order to provide architecture-optimized - versions. This is done because further scheduler optimizations are - becoming increasingly pointless without considering architecture and - compiler related constraints. -- NEW: Updated the STM32 FW Library files to latest version 3.3.0. -- NEW: AT91SAM7 HAL support for the DGBU UART peripheral, as SD3. -- NEW: Added a demo for the AT91SAM7S256 and board files for the Olimex - SAM7-P256. The demo has been contributed by Alexander Kozaruk. -- NEW: Added core variant name macro in chcore.h and platform name in - hal_lld.h, the info are printed in the test report and from the "info" - shell command. -- NEW: Added BOARD_NAME macro to the various board.h files. -- NEW: Added a MemoryStream class under ./os/various. -- NEW: Added Mac OS-X support for the simulator. The Linux simulator has - been renamed to Posix simulator in order to include this change in a - single project. -- NEW: New articles, sections and various improvements to the documentation. -- NEW: Added to the simulators shell demos two new commands: threads and mem, - that show the currently active threads (using the new registry) and the - memory allocators state. -- NEW: New articles and guides in the documentation. -- OPT: New Cortex-M3 port code, *huge* performance improvements in all the - context switching related benchmarks (up to 18% depending on the benchmark). - The new code does no more require the use of the PendSV vector that is - thus available to the user, it also saves four RAM bytes for each thread - in the system. The old code is still available as a fall back option while - the new one is being hardened by peer review and time, the two ports are - perfectly interchangeable. -- OPT: Speed/size optimization to the events subsystem. -- OPT: Speed/size optimization to the mutexes subsystem. -- OPT: Speed/size optimization to the condvars subsystem. -- OPT: Speed/size optimization to the synchronous messages subsystem. -- OPT: Small size optimization in the semaphores subsystem. -- OPT: Minor optimizations in the "compact" code path. -- OPT: Optimization on the interface between scheduler and port layer, now - the kernel is even smaller and the context switch performance improved - quite a bit on all the supported architectures. -- OPT: Simplified the implementation of chSchYieldS() and made it a macro. - The previous implementation was probably overkill and took too much space - even if a bit faster. -- OPT: Internal optimization in the serial driver, it now is a bit smaller - and uses less RAM (all architectures). - -*** 1.4.3 *** -- FIX: Fixed centralized ARM makefile (bug 2992747). -- FIX: Fixed write problems in MMC_SPI driver (bug 2991714). -- FIX: Fixed wrong macro check in serial.h (bug 2989459). - -*** 1.4.2 *** -- FIX: Fixed missing reschedule in chEvtSignal() (bug 2961208). -- FIX: Removed C99-style variables declarations (bug 2964418). -- Minor documentation fixes. - -*** 1.4.1 *** -- FIX: Fixed wrong UART deinitialization sequence in LPC214x serial driver - (bug 2953985). -- FIX: Fixed wrong PINSEL2 offset into lpc214x.h (bug 2953981). -- FIX: Fixed invalid UART-related macro in the LPC214x HAL (bug 2953195). -- FIX: Wrong prototype in template file chcore.c (bug 2951529). -- FIX: Fixed insufficient stack space for the idle thread in the ARMCM3 port - when compiling without optimizations (bug 2946233). -- FIX: Fixed wrong notes on function chThdResume() (bug 2943160). -- FIX: Fixed missing dependencies check for CH_USE_DYNAMIC (bug 2942757). -- FIX: Fixed swapped thread states descriptions (bug 2938445). -- FIX_ Fixed C99-style variable declaration (bug 2938444). - -*** 1.4.0 *** -- Full test cycle and test reports updated. -- NEW: Reorganized and rationalized the distribution tree and the - documentation. -- NEW: Abstract Streams and I/O Channels mechanisms introduced. -- NEW: Added a new core memory manager. -- NEW: Improved Heap and Pools allocators. -- NEW: The I/O queues code has been improved, now there are 2 separate - structures: InputQueue and OutputQueue. -- NEW: Added timeout specification to the I/O queues read/write primitives. -- NEW: Static initializers macros introduced for most kernel objects. -- NEW: Added new APIs chSchDoYieldS() and chThdYield(). -- NEW: Improved and simplified kernel configuration files. -- MEW: Added new benchmarks and test cases. -- NEW: Added more test cases in order to improve the test suite code coverage - (it was 74% in version 1.2.0, it is now close to 100%). -- NEW: Added a code coverage analysis application under ./tests/coverage. -- NEW: Added the test suite documentation to the general documentation. -- NEW: Linux x86 simulator demo added. -- NEW: Improved the Cortex-M3 preemption code. -- NEW: Added standard CMSIS 1.2.0 support to the Cortex-M3 port. -- NEW: Added support for the ST firmware library to the STM32 port. -- NEW: Added support for HD and CL STM32 devices. -- NEW: Improvements to the AT91SAM7 support. -- NEW: Improved makefiles and makefile fragments, now the paths are not fixed. -- NEW: Unified the initialization of the various drivers from a single HAL - driver. The single drivers can be enabled or disabled from a HAL - configuration file halconf.h. -- NEW: Hardware Abstraction Layer (HAL) with support for PAL, ADC, CAN, MAC, - MMC/SD, PWM, Serial, SPI drivers. Added driver implementations to the - various platforms. -- NEW: Added support for uIP, lwIP, FatFS external libraries, added demos. -- Many many other improvements and minor features. - -*** 1.2.4 *** -- FIX: Fixed GCC 4.4.x aliasing warnings (bug 2846336). -- FIX: Modified linker scripts for GCC 4.4.x (bug 2846302). -- FIX: Fixed the CH_OPTIMIZE_SPEED option in the CM3 port (bug 2846278). -- FIX: Fixed GCC 4.4.x related problems in CM3 port (bug 2846162). -- FIX: Fixed LPC214x UART problem (bug 2841088). - -*** 1.2.3 *** -- FIX: Fixed C99-style variable declarations (bug 2792919). -- FIX: Fixed instance of obsolete CH_USE_TERMINATE option in the C++ wrapper - (bug 2796065). -- FIX: Insufficient stack allocated to the C++ LPC2148 demo (bug 2796069). -- FIX: Fixed errors in events test case (bug 2796081). -- CHANGE: Increased main stack size to 1KiB for all the ARMx demos, 2KiB for - the C++ LPC2148 demo. This should make things easier for unexperienced - users. - -*** 1.2.2 *** -- FIX: Fixed macro in test.h (bug 2781176). -- FIX: Fixed @file tag in sam7x_serial.c (bug 2788573). -- FIX: Fixed sequence assertion in test.c (bug 2789377). -- FIX: Fixed test_cpu_pulse() incorrect behavior (bug 2789383). -- FIX: Fixed missing volatile modifier for p_time field in Thread structure - (bug 2789501). -- CHANGE: Made the option CH_DBG_THREADS_PROFILING default to TRUE because it - is now required in order to execute the whole test suite. Note that this - option is very light so there is no real overhead in the system. -- Added a (harmless) workaround to the Cortex-M3 startup file in order to - make the RIDE7 demo compile on an unmodified distribution. - -*** 1.2.1 *** -- FIX: Fixed regression in MinGW demo (bug 2745153). -- FIX: Fixed problem with the timeout constant TIME_IMMEDIATE (bug 2755170). -- FIX: Fixed a problem in semaphores test case #2 (bug 2755195). -- FIX: Removed unused list functions (bug 2755230). -- FIX: Added the exception notes into the source headers (bug 2772129). -- FIX: Added license notice to several files (bug 2772160). -- FIX: Found new instances of the obsolete function chSysGetTime() in the - C++ wrapper and in the WEB demo (bug 2772237). - -*** 1.2.0 *** -- Full test cycle and test reports updated. -- NEW: Better separation between the port code and the system APIs, now an - architecture-specific "driver" contains all the port related code. - Port functions/macros are no more directly exposed as APIs to the user code. -- NEW: Added a configuration option to enable nested system locks/unlocks. -- NEW: Improved the interrupt handlers related code. Now interrupts are - handled in a very similar way in every architecture. See the "Concepts" - section and the "Writing interrupt handlers under ChibiOS/RT" article in the - documentation. -- NEW: Added the chEvtSignal() and chEvtSignalI() APIs that allows direct - thread signaling, much more efficient that chEvtBroadcast() when the target - is a known single thread. -- NEW: Added a configuration option that enables the priority enqueuing on - semaphores. It is defaulted to off because usually semaphores are used for - I/O related tasks without hard realtime requirements. -- NEW: Now the all the options in chconf.h and the various driver headers - can be overridden externally, as example from within the Makefile. - The options are no mode a simple define but a define with an assigned - TRUE/FALSE value within an #ifndef block. -- NEW: Idle thread hook macro added to the configuration file. -- NEW: Changed the ARM7 and Cortex-M3 startup files, now the action when - the main() function returns can be overridden by redefining the symbol - MainExitHandler. -- NEW: Mailboxes (asynchronous messages) subsystem and test cases added. -- NEW: Most APIs with a timeout specification now accept the constant - TIME_IMMEDIATE (-1) that triggers an immediate timeout when trying to enter - a sleep state. -- NEW: Mode flexible debug configuration options, removed the old CH_USE_DEBUG - and CH_USE_TRACE. Replaced with CH_DBG_ENABLE_CHECKS, SCH_DBG_ENABLE_ASSERTS, - CH_DBG_ENABLE_TRACE and CH_DBG_FILL_THREADS. -- NEW: Added a debug option CH_DBG_THREADS_PROFILING for threads profiling. - A field into the Thread structure counts the consumed time. The information - is not used into the kernel, it is meant for debugging. -- NEW: Added a debug option CH_DBG_ENABLE_STACK_CHECK for stack overflow - checking. The check is not performed in the kernel but in the port code. - Currently only the ARM7 and ARMCM3 ports implements it. -- NEW: Unified makefiles for ARM7, ARMCM3 MSP430 projects, the new makefiles - share a common part making them easier to maintain. Also reorganized the - demo-specific part of the makefile, now it is easier to configure and the - option can be overridden from outside. -- OPT: Improved ARM7 thumb port code, thanks to some GCC tricks involving - registers usage now the kernel is much smaller, faster and most OS APIs - use less RAM in stack frames (note, this is an ARM7 thumb mode specific - optimization). -- OPT: Small optimization to the Cortex-M3 thread startup code, improved thread - related performance scores and smaller code. -- OPT: Alternative, non-inlined and more compact, implementations for - port_lock() and port_unlock() in the Cortex-M3 port when CH_OPTIMIZE_SPEED - is FALSE. -- OPT: Improved ready list and priority ordered lists code, some space saved, - better context switch performance. -- CHANGE: Now the API chThdSetPriority() returns the old priority instead - of void. -- CHANGE: Modified the signature of the chMsgSendWithEvent() API, it now uses - a more efficient event signaling method. -- CHANGE: Removed the field p_tid from the Thread structure and the related - code, this improved the thread creation scores (~2%) and saves some RAM. - The trace buffer field cse_tid is now populated with a simple hash of the - thread pointer as thread identifier. -- CHANGE: Renamed the macros chSysIRQEnter() and chSysIRQExit() in - CH_IRQ_PROLOGUE() and CH_IRQ_EPILOGUE() in order to make very clear that - those are not functions but inlined code. Also introduced a new macro - CH_IRQ_HANDLER that should be used when declaring an interrupt handler. -- CHANGE: Renamed several internal initialization functions by removing the - "ch" prefix because could not be considered system APIs. -- CHANGE: Changed the chSemFastWaitS() macro in chSemFastWaitI() and - chSemGetCounter() in chSemGetCounterI(). -- Improved ARM7 and Cortex-M3 support, new configuration options. -- Introduced the concept of interrupt classes, see the documentation. -- Introduced the concept of system states, see the documentation. -- Huge improvements to the documentation. -- Articles and notes previously in the wiki now merged in the general - documentation and updated, the wiki entries are obsolete and will be removed. -- New application notes and articles added. -- Added kernel size metrics to the test reports. -- Removed the inclusion graph from the documentation because the little - info they add and the size of all the images. It is possible to configure - Doxygen to have them again (and more graph types). -- Improvements to the test suite, added a new level of indirection that allows - to make tests depend on the configuration options without have to put #ifs - into the test main module. New benchmarks about semaphores and mutexes. -- Modified the test thread function to return the global test result flag. -- Removed testcond.c|h and moved the test cases into testmtx.c. Mutexes and - condvars have to be tested together. -- Added architecture diagram to the documentation. - -*** 1.0.2 *** -- FIX: Fixed priority inheritance problem with condvars (bug 2674756). -- FIX: Fixed a problem in time ranges (bug 2680425). -- Replaced ./docs/index.html with a direct shortcut to the documentation. - -*** 1.0.1 *** -- NEW: Added to the STM32 demo makefile an option to build ChibiOS/RT with the - full STM32 FWLib 2.03. - Note that, except for the compile option, the library is not used by the - OS nor supported. -- FIX: Fixed a problem into the STACK_ALIGN() macro. -- FIX: Fixed a problem with a wrong declaration of the PLL structure in the - file lpc214x.h. -- FIX: Modified the default value for the STM32 HSI setup it was 1, it should - be 0x10. -- FIX: Removed an obsolete constant (P_SUSPENDED) from thread.h. -- FIX: Removed unused field mp_grow in the MemoryPool structure. -- FIX: Fixed wrong assertions in chThdWait() and chHeapFree(). -- FIX: Fixed a problem with some event APIs not showing in the documentation. - -*** 1.0.0 *** -- License switch, added GPL exception, see exception.txt. -- Full test cycle and test reports updated. -- Renamed some occurrences of "Conditional Variable" in "Condition Variable" in - the documentation. -- FIX: Fixed some images in the documentation because problems when seen in - Internet Explorer. diff --git a/ChibiOS_2.0.8/test/coverage/Makefile b/ChibiOS_2.0.8/test/coverage/Makefile deleted file mode 100644 index 1866d5a..0000000 --- a/ChibiOS_2.0.8/test/coverage/Makefile +++ /dev/null @@ -1,150 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = mingw32- -CC = $(TRGT)gcc -AS = $(TRGT)gcc -x assembler-with-cpp -COV = gcov - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSIMULATOR - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = -lws2_32 - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/Win32/platform.mk -include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk - -# List C source files here -SRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/hal/platforms/Win32/console.c \ - main.c - -# List ASM source files here -ASRC = - -# List all user directories here -UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# Define optimisation level here -OPT = -ggdb -O0 -fomit-frame-pointer -fprofile-arcs -ftest-coverage - -# -# End of user defines -############################################################################################## - - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) -LIBS = $(DLIBS) $(ULIBS) - -LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch -lgcov $(LIBDIR) -ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# makefile rules -# - -all: $(OBJS) $(PROJECT).exe - -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -%o : %s - $(AS) -c $(ASFLAGS) $< -o $@ - -%exe: $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -.PHONY: gcov -gcov: - -mkdir gcov - $(COV) -u $(subst /,\,$(KERNSRC)) - -mv -f *.gcov ./gcov - -.PHONY: clean -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).exe - -rm -f $(PROJECT).map - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(SRC:.c=.gcno) - -rm -f $(SRC:.c=.gcda) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/ChibiOS_2.0.8/test/coverage/board.h b/ChibiOS_2.0.8/test/coverage/board.h deleted file mode 100644 index b57abb9..0000000 --- a/ChibiOS_2.0.8/test/coverage/board.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_2.0.8/test/coverage/chconf.h b/ChibiOS_2.0.8/test/coverage/chconf.h deleted file mode 100644 index f70c434..0000000 --- a/ChibiOS_2.0.8/test/coverage/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS TRUE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0x20000 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED FALSE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE TRUE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/test/coverage/halconf.h b/ChibiOS_2.0.8/test/coverage/halconf.h deleted file mode 100644 index fdae565..0000000 --- a/ChibiOS_2.0.8/test/coverage/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -/*#include "mcuconf.h"*/ - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL FALSE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/test/coverage/main.c b/ChibiOS_2.0.8/test/coverage/main.c deleted file mode 100644 index 1f9f9a5..0000000 --- a/ChibiOS_2.0.8/test/coverage/main.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include -#include - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "console.h" - -/* - * Simulator main. - */ -int main(int argc, char *argv[]) { - msg_t result; - - (void)argc; - (void)argv; - - halInit(); - conInit(); - chSysInit(); - - result = TestThread(&CD1); - if (result) - exit(1); - else - exit(0); -} diff --git a/ChibiOS_2.0.8/test/coverage/readme.txt b/ChibiOS_2.0.8/test/coverage/readme.txt deleted file mode 100644 index 564caa1..0000000 --- a/ChibiOS_2.0.8/test/coverage/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -In order to compute the code coverage: - -- Build the test application: make -- Run the test suite: ch -- Compute the code coverage: make gcov -- Clear everything: make clean diff --git a/ChibiOS_2.0.8/test/test.c b/ChibiOS_2.0.8/test/test.c deleted file mode 100644 index dec0717..0000000 --- a/ChibiOS_2.0.8/test/test.c +++ /dev/null @@ -1,393 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file test.c - * @brief Tests support code. - * - * @addtogroup test - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "test.h" -#include "testthd.h" -#include "testsem.h" -#include "testmtx.h" -#include "testmsg.h" -#include "testmbox.h" -#include "testevt.h" -#include "testheap.h" -#include "testpools.h" -#include "testdyn.h" -#include "testqueues.h" -#include "testbmk.h" - -/* - * Array of all the test patterns. - */ -static const struct testcase **patterns[] = { - patternthd, - patternsem, - patternmtx, - patternmsg, - patternmbox, - patternevt, - patternheap, - patternpools, - patterndyn, - patternqueues, - patternbmk, - NULL -}; - -static bool_t local_fail, global_fail; -static unsigned failpoint; -static char tokens_buffer[MAX_TOKENS]; -static char *tokp; - -/* - * Static working areas, the following areas can be used for threads or - * used as temporary buffers. - */ -union test_buffers test; - -/* - * Pointers to the spawned threads. - */ -Thread *threads[MAX_THREADS]; - -/* - * Pointers to the working areas. - */ -void * const wa[5] = {test.wa.T0, test.wa.T1, test.wa.T2, - test.wa.T3, test.wa.T4}; - -/* - * Console output. - */ -static BaseChannel *chp; - -/** - * @brief Prints a decimal unsigned number. - * - * @param[in] n the number to be printed - */ -void test_printn(uint32_t n) { - char buf[16], *p; - - if (!n) - chIOPut(chp, '0'); - else { - p = buf; - while (n) - *p++ = (n % 10) + '0', n /= 10; - while (p > buf) - chIOPut(chp, *--p); - } -} - -/** - * @brief Prints a line without final end-of-line. - * - * @param[in] msgp the message - */ -void test_print(char *msgp) { - - while (*msgp) - chIOPut(chp, *msgp++); -} - -/** - * @brief Prints a line. - * - * @param[in] msgp the message - */ -void test_println(char *msgp) { - - test_print(msgp); - chIOPut(chp, '\r'); - chIOPut(chp, '\n'); -} - -/* - * Tokens. - */ -static void clear_tokens(void) { - - tokp = tokens_buffer; -} - -static void print_tokens(void) { - char *cp = tokens_buffer; - - while (cp < tokp) - chIOPut(chp, *cp++); -} - -/** - * @brief Emits a token into the tokens buffer. - * - * @param[in] token the token as a char - */ -void test_emit_token(char token) { - - chSysLock(); - *tokp++ = token; - chSysUnlock(); -} - -/* - * Assertions. - */ -bool_t _test_fail(unsigned point) { - - local_fail = TRUE; - global_fail = TRUE; - failpoint = point; - return TRUE; -} - -bool_t _test_assert(unsigned point, bool_t condition) { - - if (!condition) - return _test_fail(point); - return FALSE; -} - -bool_t _test_assert_sequence(unsigned point, char *expected) { - char *cp = tokens_buffer; - while (cp < tokp) { - if (*cp++ != *expected++) - return _test_fail(point); - } - if (*expected) - return _test_fail(point); - clear_tokens(); - return FALSE; -} - -bool_t _test_assert_time_window(unsigned point, systime_t start, systime_t end) { - - return _test_assert(point, chTimeIsWithin(start, end)); -} - -/* - * Threads utils. - */ - -/** - * @brief Pends a termination request in all the test-spawned threads. - */ -void test_terminate_threads(void) { - int i; - - for (i = 0; i < MAX_THREADS; i++) - if (threads[i]) - chThdTerminate(threads[i]); -} - -/** - * @brief Waits for the completion of all the test-spawned threads. - */ -void test_wait_threads(void) { - int i; - - for (i = 0; i < MAX_THREADS; i++) - if (threads[i] != NULL) { - chThdWait(threads[i]); - threads[i] = NULL; - } -} - -#if CH_DBG_THREADS_PROFILING -/** - * @brief CPU pulse. - * @note The current implementation is not totally reliable. - * - * @param[in] duration CPU pulse duration in milliseconds - */ -void test_cpu_pulse(unsigned duration) { - systime_t start, end, now; - - start = chThdSelf()->p_time; - end = start + MS2ST(duration); - do { - now = chThdSelf()->p_time; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } - while (end > start ? (now >= start) && (now < end) : - (now >= start) || (now < end)); -} -#endif - -/** - * @brief Delays execution until next system time tick. - */ -systime_t test_wait_tick(void) { - - chThdSleep(1); - return chTimeNow(); -} - -/* - * Timer utils. - */ - -/** @brief Set to @p TRUE when the test timer reaches its deadline.*/ -bool_t test_timer_done; - -static VirtualTimer vt; -static void tmr(void *p) { - (void)p; - - test_timer_done = TRUE; -} - -/** - * @brief Starts the test timer. - * - * @param[in] ms time in milliseconds - */ -void test_start_timer(unsigned ms) { - - systime_t duration = MS2ST(ms); - test_timer_done = FALSE; - chSysLock(); - chVTSetI(&vt, duration, tmr, NULL); - chSysUnlock(); -} - -/* - * Test suite execution. - */ -static void execute_test(const struct testcase *tcp) { - int i; - - /* Initialization */ - clear_tokens(); - local_fail = FALSE; - for (i = 0; i < MAX_THREADS; i++) - threads[i] = NULL; - - if (tcp->setup != NULL) - tcp->setup(); - tcp->execute(); - if (tcp->teardown != NULL) - tcp->teardown(); - - test_wait_threads(); -} - -static void print_line(void) { - unsigned i; - - for (i = 0; i < 76; i++) - chIOPut(chp, '-'); - chIOPut(chp, '\r'); - chIOPut(chp, '\n'); -} - -/** - * @brief Test execution thread function. - * - * @param[in] p pointer to a @p BaseChannel object for test output - */ -msg_t TestThread(void *p) { - int i, j; - - chp = p; - test_println(""); - test_println("*** ChibiOS/RT test suite"); - test_println("***"); - test_print("*** Kernel: "); - test_println(CH_KERNEL_VERSION); -#ifdef __GNUC__ - test_print("*** GCC Version: "); - test_println(__VERSION__); -#endif - test_print("*** Architecture: "); - test_println(CH_ARCHITECTURE_NAME); -#ifdef CH_CORE_VARIANT_NAME - test_print("*** Core Variant: "); - test_println(CH_CORE_VARIANT_NAME); -#endif -#ifdef PLATFORM_NAME - test_print("*** Platform: "); - test_println(PLATFORM_NAME); -#endif -#ifdef BOARD_NAME - test_print("*** Test Board: "); - test_println(BOARD_NAME); -#endif - test_println(""); - - global_fail = FALSE; - i = 0; - while (patterns[i]) { - j = 0; - while (patterns[i][j]) { - print_line(); - test_print("--- Test Case "); - test_printn(i + 1); - test_print("."); - test_printn(j + 1); - test_print(" ("); - test_print(patterns[i][j]->gettest()); - test_println(")"); -#if DELAY_BETWEEN_TESTS > 0 - chThdSleepMilliseconds(DELAY_BETWEEN_TESTS); -#endif - execute_test(patterns[i][j]); - if (local_fail) { - test_print("--- Result: FAILURE (#"); - test_printn(failpoint); - test_print(" ["); - print_tokens(); - test_println("])"); - } - else - test_println("--- Result: SUCCESS"); - j++; - } - i++; - } - print_line(); - test_println(""); - test_print("Final result: "); - if (global_fail) - test_println("FAILURE"); - else - test_println("SUCCESS"); - - return (msg_t)global_fail; -} - -/** @} */ diff --git a/ChibiOS_2.0.8/test/test.dox b/ChibiOS_2.0.8/test/test.dox deleted file mode 100644 index 094bb45..0000000 --- a/ChibiOS_2.0.8/test/test.dox +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @defgroup test Test Runtime - * @details Runtime code for the test suite execution, this code is not part - * of the OS and should not be included in user applications. - */ - -/** - * @page testsuite Testing Strategy - *

Description

- * Most of the ChibiOS/RT demos link a set of software modules (test suite) in - * order to verify the proper working of the kernel, the port and the demo - * itself. - * - *

Strategy by Component

- * The OS components are tested in various modes depending on their importance: - * - Kernel. The kernel code is subject to rigorous testing. The test - * suite aims to test all the kernel code and reach a code coverage - * as close to 100% as possible. In addition to the code coverage, the kernel - * code is tested for functionality and benchmarked for speed - * and size before each stable release. In addition to the code - * coverage and functional testing a batch compilation test is - * performed before each release, the kernel is compiled by alternatively - * enabling and disabling all the various configuration options, the - * kernel code is expected to compile without errors nor warnings and - * execute the test suite without failures (a specific simulator is used - * for this execution test, it is done automatically by a script because - * the entire sequence can take hours).
- * All the tests results are included as reports in the OS distribution - * under @p ./docs/reports. - * - Ports. The port code is tested by executing the kernel test - * suite on the target hardware. A port is validated only if it passes all - * the tests. Speed and size benchmarks for all the supported architectures - * are performed, both size and speed regressions are monitored. - * - HAL. The HAL high level code and device drivers implementations - * are tested by use in the various demos and/or by users. - * - Various. The miscellaneous code is tested by use in the various - * demos and/or by users. - * - External Code. Not tested, external libraries or components are - * used as-is or with minor patching where required, problems are usually - * reported upstream. - * . - *

Kernel Test Suite

- * The kernel test suite is divided in modules or test sequences. Each Test - * Module performs a series of tests on a specified kernel subsystem or - * subsystems and can report a failure/success status and/or a performance - * index as the test suite output.
- * The test suite is usually activated in the demo applications by pressing a - * button on the target board, see the readme into the various demos - * directories. The test suite output is usually sent through a serial port - * and can be examined by using a terminal emulator program. - * - *

Kernel Test Modules

- * - * - @subpage test_threads - * - @subpage test_dynamic - * - @subpage test_msg - * - @subpage test_sem - * - @subpage test_mtx - * - @subpage test_events - * - @subpage test_mbox - * - @subpage test_queues - * - @subpage test_heap - * - @subpage test_pools - * - @subpage test_benchmarks - * . - */ diff --git a/ChibiOS_2.0.8/test/test.h b/ChibiOS_2.0.8/test/test.h deleted file mode 100644 index b648e7c..0000000 --- a/ChibiOS_2.0.8/test/test.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file test.h - * @brief Tests support header. - * - * @addtogroup test - * @{ - */ - -#ifndef _TEST_H_ -#define _TEST_H_ - -/** - * @brief Delay inserted between test cases. - */ -#if !defined(DELAY_BETWEEN_TESTS) || defined(__DOXYGEN__) -#define DELAY_BETWEEN_TESTS 200 -#endif - -/** - * @brief If @p TRUE then benchmarks are not included. - */ -#if !defined(TEST_NO_BENCHMARKS) || defined(__DOXYGEN__) -#define TEST_NO_BENCHMARKS FALSE -#endif - -#define MAX_THREADS 5 -#define MAX_TOKENS 16 - -#if defined(CH_ARCHITECTURE_AVR) || \ - defined(CH_ARCHITECTURE_MSP430) || \ - defined(CH_ARCHITECTURE_STM8) -#define THREADS_STACK_SIZE 48 -#elif defined(CH_ARCHITECTURE_SIMIA32) -#define THREADS_STACK_SIZE 512 -#else -#define THREADS_STACK_SIZE 128 -#endif -#define WA_SIZE THD_WA_SIZE(THREADS_STACK_SIZE) - -/** - * @brief Structure representing a test case. - */ -struct testcase { - char *(*gettest)(void); /**< @brief Test case name get function. */ - void (*setup)(void); /**< @brief Test case preparation function. */ - void (*teardown)(void); /**< @brief Test case clean up function. */ - void (*execute)(void); /**< @brief Test case execution function. */ -}; - -#ifndef __DOXYGEN__ -union test_buffers { - struct { - WORKING_AREA(T0, THREADS_STACK_SIZE); - WORKING_AREA(T1, THREADS_STACK_SIZE); - WORKING_AREA(T2, THREADS_STACK_SIZE); - WORKING_AREA(T3, THREADS_STACK_SIZE); - WORKING_AREA(T4, THREADS_STACK_SIZE); - } wa; - uint8_t buffer[WA_SIZE * 5]; -}; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - msg_t TestThread(void *p); - void test_printn(uint32_t n); - void test_print(char *msgp); - void test_println(char *msgp); - void test_emit_token(char token); - bool_t _test_fail(unsigned point); - bool_t _test_assert(unsigned point, bool_t condition); - bool_t _test_assert_sequence(unsigned point, char *expected); - bool_t _test_assert_time_window(unsigned point, systime_t start, systime_t end); - void test_terminate_threads(void); - void test_wait_threads(void); - systime_t test_wait_tick(void); - void test_start_timer(unsigned ms); -#if CH_DBG_THREADS_PROFILING - void test_cpu_pulse(unsigned duration); -#endif -#if defined(WIN32) - void ChkIntSources(void); -#endif -#ifdef __cplusplus -} -#endif - -/** - * @brief Test failure enforcement. - */ -#define test_fail(point) { \ - _test_fail(point); \ - return; \ -} - -/** - * @brief Test assertion. - * - * @param[in] point numeric assertion identifier - * @param[in] condition a boolean expression that must be verified to be true - * @param[in] msg failure message - */ -#define test_assert(point, condition, msg) { \ - if (_test_assert(point, condition)) \ - return; \ -} - -/** - * @brief Test sequence assertion. - * - * @param[in] point numeric assertion identifier - * @param[in] expected string to be matched with the tokens buffer - */ -#define test_assert_sequence(point, expected) { \ - if (_test_assert_sequence(point, expected)) \ - return; \ -} - -/** - * @brief Test time window assertion. - * - * @param[in] point numeric assertion identifier - * @param[in] start initial time in the window (included) - * @param[in] end final time in the window (not included) - */ -#define test_assert_time_window(point, start, end) { \ - if (_test_assert_time_window(point, start, end)) \ - return; \ -} - -#if !defined(__DOXYGEN__) -extern Thread *threads[MAX_THREADS]; -extern union test_buffers test; -extern void * const wa[]; -extern bool_t test_timer_done; -#endif - -#endif /* _TEST_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/test/test.mk b/ChibiOS_2.0.8/test/test.mk deleted file mode 100644 index 593cd6e..0000000 --- a/ChibiOS_2.0.8/test/test.mk +++ /dev/null @@ -1,16 +0,0 @@ -# List of all the ChibiOS/RT test files. -TESTSRC = ${CHIBIOS}/test/test.c \ - ${CHIBIOS}/test/testthd.c \ - ${CHIBIOS}/test/testsem.c \ - ${CHIBIOS}/test/testmtx.c \ - ${CHIBIOS}/test/testmsg.c \ - ${CHIBIOS}/test/testmbox.c \ - ${CHIBIOS}/test/testevt.c \ - ${CHIBIOS}/test/testheap.c \ - ${CHIBIOS}/test/testpools.c \ - ${CHIBIOS}/test/testdyn.c \ - ${CHIBIOS}/test/testqueues.c \ - ${CHIBIOS}/test/testbmk.c - -# Required include directories -TESTINC = ${CHIBIOS}/test diff --git a/ChibiOS_2.0.8/test/testbmk.c b/ChibiOS_2.0.8/test/testbmk.c deleted file mode 100644 index e2270d5..0000000 --- a/ChibiOS_2.0.8/test/testbmk.c +++ /dev/null @@ -1,778 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_benchmarks Kernel Benchmarks - * - * File: @ref testbmk.c - * - *

Description

- * This module implements a series of system benchmarks. The benchmarks are - * useful as a stress test and as a reference when comparing ChibiOS/RT - * with similar systems. - * - *

Objective

- * Objective of the test module is to provide a performance index for the - * most critical system subsystems. The performance numbers allow to - * discover performance regressions between successive ChibiOS/RT releases. - * - *

Preconditions

- * None. - * - *

Test Cases

- * - @subpage test_benchmarks_001 - * - @subpage test_benchmarks_002 - * - @subpage test_benchmarks_003 - * - @subpage test_benchmarks_004 - * - @subpage test_benchmarks_005 - * - @subpage test_benchmarks_006 - * - @subpage test_benchmarks_007 - * - @subpage test_benchmarks_008 - * - @subpage test_benchmarks_009 - * - @subpage test_benchmarks_010 - * - @subpage test_benchmarks_011 - * - @subpage test_benchmarks_012 - * - @subpage test_benchmarks_013 - * . - * @file testbmk.c Kernel Benchmarks - * @brief Kernel Benchmarks source file - * @file testbmk.h - * @brief Kernel Benchmarks header file - */ - -static Semaphore sem1; -#if CH_USE_MUTEXES -static Mutex mtx1; -#endif - -static msg_t thread1(void *p) { - msg_t msg; - - (void)p; - do { - chMsgRelease(msg = chMsgWait()); - } while (msg); - return 0; -} - -#ifdef __GNUC__ -__attribute__((noinline)) -#endif -static unsigned int msg_loop_test(Thread *tp) { - - uint32_t n = 0; - test_wait_tick(); - test_start_timer(1000); - do { - (void)chMsgSend(tp, 1); - n++; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - (void)chMsgSend(tp, 0); - return n; -} - -/** - * @page test_benchmarks_001 Messages performance #1 - * - *

Description

- * A message server thread is created with a lower priority than the client - * thread, the messages throughput per second is measured and the result - * printed in the output log. - */ - -static char *bmk1_gettest(void) { - - return "Benchmark, messages #1"; -} - -static void bmk1_execute(void) { - uint32_t n; - - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-1, thread1, NULL); - n = msg_loop_test(threads[0]); - test_wait_threads(); - test_print("--- Score : "); - test_printn(n); - test_print(" msgs/S, "); - test_printn(n << 1); - test_println(" ctxswc/S"); -} - -const struct testcase testbmk1 = { - bmk1_gettest, - NULL, - NULL, - bmk1_execute -}; - -/** - * @page test_benchmarks_002 Messages performance #2 - * - *

Description

- * A message server thread is created with an higher priority than the client - * thread, the messages throughput per second is measured and the result - * printed in the output log. - */ - -static char *bmk2_gettest(void) { - - return "Benchmark, messages #2"; -} - -static void bmk2_execute(void) { - uint32_t n; - - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread1, NULL); - n = msg_loop_test(threads[0]); - test_wait_threads(); - test_print("--- Score : "); - test_printn(n); - test_print(" msgs/S, "); - test_printn(n << 1); - test_println(" ctxswc/S"); -} - -const struct testcase testbmk2 = { - bmk2_gettest, - NULL, - NULL, - bmk2_execute -}; - -static msg_t thread2(void *p) { - - return (msg_t)p; -} - -/** - * @page test_benchmarks_003 Messages performance #3 - * - *

Description

- * A message server thread is created with an higher priority than the client - * thread, four lower priority threads crowd the ready list, the messages - * throughput per second is measured while the ready list and the result - * printed in the output log. - */ - -static char *bmk3_gettest(void) { - - return "Benchmark, messages #3"; -} - -static void bmk3_execute(void) { - uint32_t n; - - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread1, NULL); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-2, thread2, NULL); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread2, NULL); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-4, thread2, NULL); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-5, thread2, NULL); - n = msg_loop_test(threads[0]); - test_wait_threads(); - test_print("--- Score : "); - test_printn(n); - test_print(" msgs/S, "); - test_printn(n << 1); - test_println(" ctxswc/S"); -} - -const struct testcase testbmk3 = { - bmk3_gettest, - NULL, - NULL, - bmk3_execute -}; - -/** - * @page test_benchmarks_004 Context Switch performance - * - *

Description

- * A thread is created that just performs a @p chSchGoSleepS() into a loop, - * the thread is awakened as fast is possible by the tester thread.
- * The Context Switch performance is calculated by measuring the number of - * iterations after a second of continuous operations. - */ - -static char *bmk4_gettest(void) { - - return "Benchmark, context switch"; -} - -msg_t thread4(void *p) { - msg_t msg; - Thread *self = chThdSelf(); - - (void)p; - chSysLock(); - do { - chSchGoSleepS(THD_STATE_SUSPENDED); - msg = self->p_u.rdymsg; - } while (msg == RDY_OK); - chSysUnlock(); - return 0; -} - -static void bmk4_execute(void) { - Thread *tp; - uint32_t n; - - tp = threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread4, NULL); - n = 0; - test_wait_tick(); - test_start_timer(1000); - do { - chSysLock(); - chSchWakeupS(tp, RDY_OK); - chSchWakeupS(tp, RDY_OK); - chSchWakeupS(tp, RDY_OK); - chSchWakeupS(tp, RDY_OK); - chSysUnlock(); - n += 4; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - chSysLock(); - chSchWakeupS(tp, RDY_TIMEOUT); - chSysUnlock(); - - test_wait_threads(); - test_print("--- Score : "); - test_printn(n * 2); - test_println(" ctxswc/S"); -} - -const struct testcase testbmk4 = { - bmk4_gettest, - NULL, - NULL, - bmk4_execute -}; - -/** - * @page test_benchmarks_005 Threads performance, full cycle - * - *

Description

- * Threads are continuously created and terminated into a loop. A full - * @p chThdCreateStatic() / @p chThdExit() / @p chThdWait() cycle is performed - * in each iteration.
- * The performance is calculated by measuring the number of iterations after - * a second of continuous operations. - */ - -static char *bmk5_gettest(void) { - - return "Benchmark, threads, full cycle"; -} - -static void bmk5_execute(void) { - - uint32_t n = 0; - void *wap = wa[0]; - tprio_t prio = chThdGetPriority() - 1; - test_wait_tick(); - test_start_timer(1000); - do { - chThdWait(chThdCreateStatic(wap, WA_SIZE, prio, thread2, NULL)); - n++; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - test_print("--- Score : "); - test_printn(n); - test_println(" threads/S"); -} - -const struct testcase testbmk5 = { - bmk5_gettest, - NULL, - NULL, - bmk5_execute -}; - -/** - * @page test_benchmarks_006 Threads performance, create/exit only - * - *

Description

- * Threads are continuously created and terminated into a loop. A partial - * @p chThdCreateStatic() / @p chThdExit() cycle is performed in each - * iteration, the @p chThdWait() is not necessary because the thread is - * created at an higher priority so there is no need to wait for it to - * terminate.
- * The performance is calculated by measuring the number of iterations after - * a second of continuous operations. - */ - -static char *bmk6_gettest(void) { - - return "Benchmark, threads, create only"; -} - -static void bmk6_execute(void) { - - uint32_t n = 0; - void *wap = wa[0]; - tprio_t prio = chThdGetPriority() + 1; - test_wait_tick(); - test_start_timer(1000); - do { - chThdCreateStatic(wap, WA_SIZE, prio, thread2, NULL); - n++; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - test_print("--- Score : "); - test_printn(n); - test_println(" threads/S"); -} - -const struct testcase testbmk6 = { - bmk6_gettest, - NULL, - NULL, - bmk6_execute -}; - -/** - * @page test_benchmarks_007 Mass reschedule performance - * - *

Description

- * Five threads are created and atomically rescheduled by resetting the - * semaphore where they are waiting on. The operation is performed into a - * continuous loop.
- * The performance is calculated by measuring the number of iterations after - * a second of continuous operations. - */ - -static msg_t thread3(void *p) { - - (void)p; - while (!chThdShouldTerminate()) - chSemWait(&sem1); - return 0; -} - -static char *bmk7_gettest(void) { - - return "Benchmark, mass reschedule, 5 threads"; -} - -static void bmk7_setup(void) { - - chSemInit(&sem1, 0); -} - -static void bmk7_execute(void) { - uint32_t n; - - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+5, thread3, NULL); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()+4, thread3, NULL); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()+3, thread3, NULL); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()+2, thread3, NULL); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()+1, thread3, NULL); - - n = 0; - test_wait_tick(); - test_start_timer(1000); - do { - chSemReset(&sem1, 0); - n++; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - test_terminate_threads(); - chSemReset(&sem1, 0); - test_wait_threads(); - - test_print("--- Score : "); - test_printn(n); - test_print(" reschedules/S, "); - test_printn(n * 6); - test_println(" ctxswc/S"); -} - -const struct testcase testbmk7 = { - bmk7_gettest, - bmk7_setup, - NULL, - bmk7_execute -}; - -/** - * @page test_benchmarks_008 I/O Round-Robin voluntary reschedule. - * - *

Description

- * Five threads are created at equal priority, each thread just increases a - * variable and yields.
- * The performance is calculated by measuring the number of iterations after - * a second of continuous operations. - */ - -static msg_t thread8(void *p) { - - do { - chThdYield(); - chThdYield(); - chThdYield(); - chThdYield(); - (*(uint32_t *)p) += 4; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while(!chThdShouldTerminate()); - return 0; -} - -static char *bmk8_gettest(void) { - - return "Benchmark, round robin context switching"; -} - -static void bmk8_execute(void) { - uint32_t n; - - n = 0; - test_wait_tick(); - - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-1, thread8, (void *)&n); - - chThdSleepSeconds(1); - test_terminate_threads(); - test_wait_threads(); - - test_print("--- Score : "); - test_printn(n); - test_println(" ctxswc/S"); -} - -const struct testcase testbmk8 = { - bmk8_gettest, - NULL, - NULL, - bmk8_execute -}; - -/** - * @page test_benchmarks_009 I/O Queues throughput - * - *

Description

- * Four bytes are written and then read from an @p InputQueue into a continuous - * loop.
- * The performance is calculated by measuring the number of iterations after - * a second of continuous operations. - */ - -static char *bmk9_gettest(void) { - - return "Benchmark, I/O Queues throughput"; -} - -static void bmk9_execute(void) { - uint32_t n; - static uint8_t ib[16]; - static InputQueue iq; - - chIQInit(&iq, ib, sizeof(ib), NULL); - n = 0; - test_wait_tick(); - test_start_timer(1000); - do { - chIQPutI(&iq, 0); - chIQPutI(&iq, 1); - chIQPutI(&iq, 2); - chIQPutI(&iq, 3); - (void)chIQGet(&iq); - (void)chIQGet(&iq); - (void)chIQGet(&iq); - (void)chIQGet(&iq); - n++; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - test_print("--- Score : "); - test_printn(n * 4); - test_println(" bytes/S"); -} - -const struct testcase testbmk9 = { - bmk9_gettest, - NULL, - NULL, - bmk9_execute -}; - -/** - * @page test_benchmarks_010 Virtual Timers set/reset performance - * - *

Description

- * A virtual timer is set and immediately reset into a continuous loop.
- * The performance is calculated by measuring the number of iterations after - * a second of continuous operations. - */ - -static char *bmk10_gettest(void) { - - return "Benchmark, virtual timers set/reset"; -} - -static void tmo(void *param) {(void)param;} - -static void bmk10_execute(void) { - static VirtualTimer vt1, vt2; - uint32_t n = 0; - - test_wait_tick(); - test_start_timer(1000); - do { - chSysLock(); - chVTSetI(&vt1, 1, tmo, NULL); - chVTSetI(&vt2, 10000, tmo, NULL); - chVTResetI(&vt1); - chVTResetI(&vt2); - chSysUnlock(); - n++; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - test_print("--- Score : "); - test_printn(n * 2); - test_println(" timers/S"); -} - -const struct testcase testbmk10 = { - bmk10_gettest, - NULL, - NULL, - bmk10_execute -}; - -/** - * @page test_benchmarks_011 Semaphores wait/signal performance - * - *

Description

- * A counting semaphore is taken/released into a continuous loop, no Context - * Switch happens because the counter is always non negative.
- * The performance is calculated by measuring the number of iterations after - * a second of continuous operations. - */ - -static char *bmk11_gettest(void) { - - return "Benchmark, semaphores wait/signal"; -} - -static void bmk11_setup(void) { - - chSemInit(&sem1, 1); -} - -static void bmk11_execute(void) { - uint32_t n = 0; - - test_wait_tick(); - test_start_timer(1000); - do { - chSemWait(&sem1); - chSemSignal(&sem1); - chSemWait(&sem1); - chSemSignal(&sem1); - chSemWait(&sem1); - chSemSignal(&sem1); - chSemWait(&sem1); - chSemSignal(&sem1); - n++; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - test_print("--- Score : "); - test_printn(n * 4); - test_println(" wait+signal/S"); -} - -const struct testcase testbmk11 = { - bmk11_gettest, - bmk11_setup, - NULL, - bmk11_execute -}; - -#if CH_USE_MUTEXES -/** - * @page test_benchmarks_012 Mutexes lock/unlock performance - * - *

Description

- * A mutex is locked/unlocked into a continuous loop, no Context Switch happens - * because there are no other threads asking for the mutex.
- * The performance is calculated by measuring the number of iterations after - * a second of continuous operations. - */ - -static char *bmk12_gettest(void) { - - return "Benchmark, mutexes lock/unlock"; -} - -static void bmk12_setup(void) { - - chMtxInit(&mtx1); -} - -static void bmk12_execute(void) { - uint32_t n = 0; - - test_wait_tick(); - test_start_timer(1000); - do { - chMtxLock(&mtx1); - chMtxUnlock(); - chMtxLock(&mtx1); - chMtxUnlock(); - chMtxLock(&mtx1); - chMtxUnlock(); - chMtxLock(&mtx1); - chMtxUnlock(); - n++; -#if defined(SIMULATOR) - ChkIntSources(); -#endif - } while (!test_timer_done); - test_print("--- Score : "); - test_printn(n * 4); - test_println(" lock+unlock/S"); -} - -const struct testcase testbmk12 = { - bmk12_gettest, - bmk12_setup, - NULL, - bmk12_execute -}; -#endif - -/** - * @page test_benchmarks_013 RAM Footprint - * - *

Description

- * The memory size of the various kernel objects is printed. - */ - -static char *bmk13_gettest(void) { - - return "Benchmark, RAM footprint"; -} - -static void bmk13_execute(void) { - - test_print("--- System: "); - test_printn(sizeof(ReadyList) + sizeof(VTList) + IDLE_THREAD_STACK_SIZE + - (sizeof(Thread) + sizeof(struct intctx) + sizeof(struct extctx) + - INT_REQUIRED_STACK) * 2); - test_println(" bytes"); - test_print("--- Thread: "); - test_printn(sizeof(Thread)); - test_println(" bytes"); - test_print("--- Timer : "); - test_printn(sizeof(VirtualTimer)); - test_println(" bytes"); - test_print("--- Semaph: "); - test_printn(sizeof(Semaphore)); - test_println(" bytes"); -#if CH_USE_EVENTS - test_print("--- EventS: "); - test_printn(sizeof(EventSource)); - test_println(" bytes"); - test_print("--- EventL: "); - test_printn(sizeof(EventListener)); - test_println(" bytes"); -#endif -#if CH_USE_MUTEXES - test_print("--- Mutex : "); - test_printn(sizeof(Mutex)); - test_println(" bytes"); -#endif -#if CH_USE_CONDVARS - test_print("--- CondV.: "); - test_printn(sizeof(CondVar)); - test_println(" bytes"); -#endif -#if CH_USE_QUEUES - test_print("--- Queue : "); - test_printn(sizeof(GenericQueue)); - test_println(" bytes"); -#endif -#if CH_USE_MAILBOXES - test_print("--- MailB.: "); - test_printn(sizeof(Mailbox)); - test_println(" bytes"); -#endif -} - -const struct testcase testbmk13 = { - bmk13_gettest, - NULL, - NULL, - bmk13_execute -}; - -/** - * @brief Test sequence for benchmarks. - */ -const struct testcase * const patternbmk[] = { -#if !TEST_NO_BENCHMARKS - &testbmk1, - &testbmk2, - &testbmk3, - &testbmk4, - &testbmk5, - &testbmk6, - &testbmk7, - &testbmk8, - &testbmk9, - &testbmk10, - &testbmk11, -#if CH_USE_MUTEXES - &testbmk12, -#endif - &testbmk13, -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testbmk.h b/ChibiOS_2.0.8/test/testbmk.h deleted file mode 100644 index fc9efff..0000000 --- a/ChibiOS_2.0.8/test/testbmk.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTBMK_H_ -#define _TESTBMK_H_ - -extern const struct testcase *patternbmk[]; - -#endif /* _TESTBMK_H_ */ diff --git a/ChibiOS_2.0.8/test/testdyn.c b/ChibiOS_2.0.8/test/testdyn.c deleted file mode 100644 index c456c45..0000000 --- a/ChibiOS_2.0.8/test/testdyn.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_dynamic Dynamic APIs test - * - * File: @ref testdyn.c - * - *

Description

- * This module implements the test sequence for the dynamic thread creation - * APIs. - * - *

Objective

- * Objective of the test module is to cover 100% of the dynamic APIs code. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_DYNAMIC - * - @p CH_USE_HEAP - * - @p CH_USE_MEMPOOLS - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_dynamic_001 - * - @subpage test_dynamic_002 - * - @subpage test_dynamic_003 - * . - * @file testdyn.c - * @brief Dynamic thread APIs test source file - * @file testdyn.h - * @brief Dynamic thread APIs test header file - */ - -#if CH_USE_DYNAMIC -#if CH_USE_HEAP -static MemoryHeap heap1; -#endif -#if CH_USE_MEMPOOLS -static MemoryPool mp1; -#endif - -/** - * @page test_dynamic_001 Threads creation from Memory Heap - * - *

Description

- * Two threads are started by allocating the memory from the Memory Heap then - * the remaining heap space is arbitrarily allocated and a third tread startup - * is attempted.
- * The test expects the first two threads to successfully start and the last - * one to fail. - */ - -static msg_t thread(void *p) { - - test_emit_token(*(char *)p); - return 0; -} - -#if CH_USE_HEAP -static char *dyn1_gettest(void) { - - return "Dynamic APIs, threads creation from heap"; -} - -static void dyn1_setup(void) { - - chHeapInit(&heap1, test.buffer, sizeof(union test_buffers)); -} - -static void dyn1_execute(void) { - size_t n, sz; - void *p1; - tprio_t prio = chThdGetPriority(); - - (void)chHeapStatus(&heap1, &sz); - /* Starting threads from the heap. */ - threads[0] = chThdCreateFromHeap(&heap1, THD_WA_SIZE(THREADS_STACK_SIZE), - prio-1, thread, "A"); - threads[1] = chThdCreateFromHeap(&heap1, THD_WA_SIZE(THREADS_STACK_SIZE), - prio-2, thread, "B"); - /* Allocating the whole heap in order to make the thread creation fail.*/ - (void)chHeapStatus(&heap1, &n); - p1 = chHeapAlloc(&heap1, n); - threads[2] = chThdCreateFromHeap(&heap1, THD_WA_SIZE(THREADS_STACK_SIZE), - prio-3, thread, "C"); - chHeapFree(p1); - - test_assert(1, (threads[0] != NULL) && - (threads[1] != NULL) && - (threads[2] == NULL) && - (threads[3] == NULL) && - (threads[4] == NULL), - "thread creation failed"); - - /* Claiming the memory from terminated threads. */ - test_wait_threads(); - test_assert_sequence(2, "AB"); - - /* Heap status checked again.*/ - test_assert(3, chHeapStatus(&heap1, &n) == 1, "heap fragmented"); - test_assert(4, n == sz, "heap size changed"); -} - -const struct testcase testdyn1 = { - dyn1_gettest, - dyn1_setup, - NULL, - dyn1_execute -}; -#endif /* CH_USE_HEAP */ - -#if CH_USE_MEMPOOLS -/** - * @page test_dynamic_002 Threads creation from Memory Pool - * - *

Description

- * Five thread creation are attempted from a pool containing only four - * elements.
- * The test expects the first four threads to successfully start and the last - * one to fail. - */ - -static char *dyn2_gettest(void) { - - return "Dynamic APIs, threads creation from memory pool"; -} - -static void dyn2_setup(void) { - - chPoolInit(&mp1, THD_WA_SIZE(THREADS_STACK_SIZE), NULL); -} - -static void dyn2_execute(void) { - int i; - tprio_t prio = chThdGetPriority(); - - /* Adding the WAs to the pool. */ - for (i = 0; i < 4; i++) - chPoolFree(&mp1, wa[i]); - - /* Starting threads from the memory pool. */ - threads[0] = chThdCreateFromMemoryPool(&mp1, prio-1, thread, "A"); - threads[1] = chThdCreateFromMemoryPool(&mp1, prio-2, thread, "B"); - threads[2] = chThdCreateFromMemoryPool(&mp1, prio-3, thread, "C"); - threads[3] = chThdCreateFromMemoryPool(&mp1, prio-4, thread, "D"); - threads[4] = chThdCreateFromMemoryPool(&mp1, prio-5, thread, "E"); - - test_assert(1, (threads[0] != NULL) && - (threads[1] != NULL) && - (threads[2] != NULL) && - (threads[3] != NULL) && - (threads[4] == NULL), - "thread creation failed"); - - /* Claiming the memory from terminated threads. */ - test_wait_threads(); - test_assert_sequence(2, "ABCD"); - - /* Now the pool must be full again. */ - for (i = 0; i < 4; i++) - test_assert(3, chPoolAlloc(&mp1) != NULL, "pool list empty"); - test_assert(4, chPoolAlloc(&mp1) == NULL, "pool list not empty"); -} - -const struct testcase testdyn2 = { - dyn2_gettest, - dyn2_setup, - NULL, - dyn2_execute -}; -#endif /* CH_USE_MEMPOOLS */ - -#if CH_USE_HEAP && CH_USE_REGISTRY -/** - * @page test_dynamic_003 Registry and References test - * - *

Description

- * Registry and Thread References APIs are tested for functionality and - * coverage. - */ - -static bool_t regfind(Thread *tp) { - Thread *ftp; - bool_t found = FALSE; - - ftp = chRegFirstThread(); - do { - found |= ftp == tp; - ftp = chRegNextThread(ftp); - } while (ftp != NULL); - return found; -} - -static char *dyn3_gettest(void) { - - return "Dynamic APIs, registry and references"; -} - -static void dyn3_setup(void) { - - chHeapInit(&heap1, test.buffer, sizeof(union test_buffers)); -} - -static void dyn3_execute(void) { - Thread *tp; - tprio_t prio = chThdGetPriority(); - - /* Testing references increase/decrease and final detach.*/ - tp = chThdCreateFromHeap(&heap1, WA_SIZE, prio-1, thread, "A"); - test_assert(1, tp->p_refs == 1, "wrong initial reference counter"); - chThdAddRef(tp); - test_assert(2, tp->p_refs == 2, "references increase failure"); - chThdRelease(tp); - test_assert(3, tp->p_refs == 1, "references decrease failure"); - - /* Verify the new threads count.*/ - test_assert(4, regfind(tp), "thread missing from registry"); - test_assert(5, regfind(tp), "thread disappeared"); - - /* Detach and let the thread execute and terminate.*/ - chThdRelease(tp); - test_assert(6, tp->p_refs == 0, "detach failure"); - test_assert(7, tp->p_state == THD_STATE_READY, "invalid state"); - test_assert(8, regfind(tp), "thread disappeared"); - test_assert(9, regfind(tp), "thread disappeared"); - chThdSleepMilliseconds(50); /* The thread just terminates. */ - test_assert(10, tp->p_state == THD_STATE_FINAL, "invalid state"); - - /* Clearing the zombie by scanning the registry.*/ - test_assert(11, regfind(tp), "thread disappeared"); - test_assert(12, !regfind(tp), "thread still in registry"); -} - -const struct testcase testdyn3 = { - dyn3_gettest, - dyn3_setup, - NULL, - dyn3_execute -}; -#endif /* CH_USE_HEAP && CH_USE_REGISTRY */ -#endif /* CH_USE_DYNAMIC */ - -/** - * @brief Test sequence for dynamic APIs. - */ -const struct testcase * const patterndyn[] = { -#if CH_USE_DYNAMIC -#if CH_USE_HEAP - &testdyn1, -#endif -#if CH_USE_MEMPOOLS - &testdyn2, -#endif -#if CH_USE_HEAP && CH_USE_REGISTRY - &testdyn3, -#endif -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testdyn.h b/ChibiOS_2.0.8/test/testdyn.h deleted file mode 100644 index ed3c7e2..0000000 --- a/ChibiOS_2.0.8/test/testdyn.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTDYN_H_ -#define _TESTDYN_H_ - -extern const struct testcase *patterndyn[]; - -#endif /* _TESTDYN_H_ */ diff --git a/ChibiOS_2.0.8/test/testevt.c b/ChibiOS_2.0.8/test/testevt.c deleted file mode 100644 index a72a4ea..0000000 --- a/ChibiOS_2.0.8/test/testevt.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_events Events test - * - * File: @ref testevt.c - * - *

Description

- * This module implements the test sequence for the @ref events subsystem. - * - *

Objective

- * Objective of the test module is to cover 100% of the @ref events subsystem. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_EVENTS - * - @p CH_USE_EVENTS_TIMEOUT - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_events_001 - * - @subpage test_events_002 - * - @subpage test_events_003 - * . - * @file testevt.c - * @brief Events test source file - * @file testevt.h - * @brief Events test header file - */ - -#if CH_USE_EVENTS - -#define ALLOWED_DELAY MS2ST(5) - -/* - * Note, the static initializers are not really required because the - * variables are explicitly initialized in each test case. It is done in order - * to test the macros. - */ -static EVENTSOURCE_DECL(es1); -static EVENTSOURCE_DECL(es2); - -/** - * @page test_events_001 Events registration and dispatch - * - *

Description

- * Two event listeners are registered on an event source and then unregistered - * in the same order.
- * The test expects that the even source has listeners after the registrations - * and after the first unregistration, then, after the second unegistration, - * the test expects no more listeners.
- * In the second part the test dispatches three event flags and verifies that - * the associated event handlers are invoked in LSb-first order. - */ - -static char *evt1_gettest(void) { - - return "Events, registration and dispatch"; -} - -static void evt1_setup(void) { - - chEvtClear(ALL_EVENTS); -} - -static void h1(eventid_t id) {(void)id;test_emit_token('A');} -static void h2(eventid_t id) {(void)id;test_emit_token('B');} -static void h3(eventid_t id) {(void)id;test_emit_token('C');} -static const evhandler_t evhndl[] = {h1, h2, h3}; - -static void evt1_execute(void) { - EventListener el1, el2; - - /* - * Testing chEvtRegisterMask() and chEvtUnregister(). - */ - chEvtInit(&es1); - chEvtRegisterMask(&es1, &el1, 1); - chEvtRegisterMask(&es1, &el2, 2); - test_assert(1, chEvtIsListening(&es1), "no listener"); - chEvtUnregister(&es1, &el1); - test_assert(2, chEvtIsListening(&es1), "no listener"); - chEvtUnregister(&es1, &el2); - test_assert(3, !chEvtIsListening(&es1), "stuck listener"); - - /* - * Testing chEvtDispatch(). - */ - chEvtDispatch(evhndl, 7); - test_assert_sequence(4, "ABC"); -} - -const struct testcase testevt1 = { - evt1_gettest, - evt1_setup, - NULL, - evt1_execute -}; - -/** - * @page test_events_002 Events wait and broadcast - * - *

Description

- * In this test the following APIs are indipently tested by starting threads - * that signal/broadcast events after fixed delays: - * - @p chEvtWaitOne() - * - @p chEvtWaitAny() - * - @p chEvtWaitAll() - * . - * After each test phase the test verifies that the events have been served at - * the expected time and that there are no stuck event flags. - */ - -static char *evt2_gettest(void) { - - return "Events, wait and broadcast"; -} - -static void evt2_setup(void) { - - chEvtClear(ALL_EVENTS); -} - -static msg_t thread1(void *p) { - - chThdSleepMilliseconds(50); - chEvtSignal((Thread *)p, 1); - return 0; -} - -static msg_t thread2(void *p) { - - (void)p; - chEvtBroadcast(&es1); - chThdSleepMilliseconds(50); - chEvtBroadcast(&es2); - return 0; -} - -static void evt2_execute(void) { - eventmask_t m; - EventListener el1, el2; - systime_t target_time; - - /* - * Test on chEvtWaitOne() without wait. - */ - chEvtPend(5); - m = chEvtWaitOne(ALL_EVENTS); - test_assert(1, m == 1, "single event error"); - m = chEvtWaitOne(ALL_EVENTS); - test_assert(2, m == 4, "single event error"); - m = chEvtClear(ALL_EVENTS); - test_assert(3, m == 0, "stuck event"); - - /* - * Test on chEvtWaitOne() with wait. - */ - test_wait_tick(); - target_time = chTimeNow() + MS2ST(50); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() - 1, - thread1, chThdSelf()); - m = chEvtWaitOne(ALL_EVENTS); - test_assert_time_window(4, target_time, target_time + ALLOWED_DELAY); - test_assert(5, m == 1, "single event error"); - m = chEvtClear(ALL_EVENTS); - test_assert(6, m == 0, "stuck event"); - test_wait_threads(); - - /* - * Test on chEvtWaitAny() without wait. - */ - chEvtPend(5); - m = chEvtWaitAny(ALL_EVENTS); - test_assert(7, m == 5, "unexpected pending bit"); - m = chEvtClear(ALL_EVENTS); - test_assert(8, m == 0, "stuck event"); - - /* - * Test on chEvtWaitAny() with wait. - */ - test_wait_tick(); - target_time = chTimeNow() + MS2ST(50); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() - 1, - thread1, chThdSelf()); - m = chEvtWaitAny(ALL_EVENTS); - test_assert_time_window(9, target_time, target_time + ALLOWED_DELAY); - test_assert(10, m == 1, "single event error"); - m = chEvtClear(ALL_EVENTS); - test_assert(11, m == 0, "stuck event"); - test_wait_threads(); - - /* - * Test on chEvtWaitAll(). - */ - chEvtInit(&es1); - chEvtInit(&es2); - chEvtRegisterMask(&es1, &el1, 1); - chEvtRegisterMask(&es2, &el2, 4); - test_wait_tick(); - target_time = chTimeNow() + MS2ST(50); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() - 1, - thread2, "A"); - m = chEvtWaitAll(5); - test_assert_time_window(12, target_time, target_time + ALLOWED_DELAY); - m = chEvtClear(ALL_EVENTS); - test_assert(13, m == 0, "stuck event"); - test_wait_threads(); - chEvtUnregister(&es1, &el1); - chEvtUnregister(&es2, &el2); - test_assert(14, !chEvtIsListening(&es1), "stuck listener"); - test_assert(15, !chEvtIsListening(&es2), "stuck listener"); -} - -const struct testcase testevt2 = { - evt2_gettest, - evt2_setup, - NULL, - evt2_execute -}; - -#if CH_USE_EVENTS_TIMEOUT -/** - * @page test_events_003 Events timeout - * - *

Description

- * In this test the following APIs are let to timeout twice: immediatly and - * after 10ms: - * In this test the following APIs are indipently tested by starting threads - * that broadcast events after fixed delays: - * - @p chEvtWaitOneTimeout() - * - @p chEvtWaitAnyTimeout() - * - @p chEvtWaitAllTimeout() - * . - * After each test phase the test verifies that there are no stuck event flags. - */ - -static char *evt3_gettest(void) { - - return "Events, timeouts"; -} - -static void evt3_setup(void) { - - chEvtClear(ALL_EVENTS); -} - -static void evt3_execute(void) { - eventmask_t m; - - /* - * Tests various timeout situations. - */ - m = chEvtWaitOneTimeout(ALL_EVENTS, TIME_IMMEDIATE); - test_assert(1, m == 0, "spurious event"); - m = chEvtWaitAnyTimeout(ALL_EVENTS, TIME_IMMEDIATE); - test_assert(2, m == 0, "spurious event"); - m = chEvtWaitAllTimeout(ALL_EVENTS, TIME_IMMEDIATE); - test_assert(3, m == 0, "spurious event"); - m = chEvtWaitOneTimeout(ALL_EVENTS, 10); - test_assert(4, m == 0, "spurious event"); - m = chEvtWaitAnyTimeout(ALL_EVENTS, 10); - test_assert(5, m == 0, "spurious event"); - m = chEvtWaitAllTimeout(ALL_EVENTS, 10); - test_assert(6, m == 0, "spurious event"); -} - -const struct testcase testevt3 = { - evt3_gettest, - evt3_setup, - NULL, - evt3_execute -}; -#endif /* CH_USE_EVENTS_TIMEOUT */ - -/** - * @brief Test sequence for events. - */ -const struct testcase * const patternevt[] = { -#if CH_USE_EVENTS - &testevt1, - &testevt2, -#if CH_USE_EVENTS_TIMEOUT - &testevt3, -#endif -#endif - NULL -}; - -#endif /* CH_USE_EVENTS */ diff --git a/ChibiOS_2.0.8/test/testevt.h b/ChibiOS_2.0.8/test/testevt.h deleted file mode 100644 index 05c4342..0000000 --- a/ChibiOS_2.0.8/test/testevt.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTEVT_H_ -#define _TESTEVT_H_ - -extern const struct testcase *patternevt[]; - -#endif /* _TESTEVT_H_ */ diff --git a/ChibiOS_2.0.8/test/testheap.c b/ChibiOS_2.0.8/test/testheap.c deleted file mode 100644 index d22dbe4..0000000 --- a/ChibiOS_2.0.8/test/testheap.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_heap Memory Heap test - * - * File: @ref testheap.c - * - *

Description

- * This module implements the test sequence for the @ref heaps subsystem. - * - *

Objective

- * Objective of the test module is to cover 100% of the @ref heaps subsystem. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_HEAP - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_heap_001 - * . - * @file testheap.c - * @brief Heap test source file - * @file testheap.h - * @brief Heap header file - */ - -#if CH_USE_HEAP - -#define SIZE 16 - -static MemoryHeap test_heap; - -/** - * @page test_heap_001 Allocation and fragmentation test - * - *

Description

- * Series of allocations/deallocations are performed in carefully designed - * sequences in order to stimulate all the possible code paths inside the - * allocator.
- * The test expects to find the heap back to the initial status after each - * sequence. - */ - -static char *heap1_gettest(void) { - - return "Heap, allocation and fragmentation test"; -} - -static void heap1_setup(void) { - - chHeapInit(&test_heap, test.buffer, sizeof(union test_buffers)); -} - -static void heap1_execute(void) { - void *p1, *p2, *p3; - size_t n, sz; - - /* Unrelated, for coverage only.*/ - (void)chCoreStatus(); - - /* - * Test on the default heap in order to cover the core allocator at - * least one time. - */ - (void)chHeapStatus(NULL, &sz); - p1 = chHeapAlloc(NULL, SIZE); - test_assert(1, p1 != NULL, "allocation failed"); - chHeapFree(p1); - p1 = chHeapAlloc(NULL, (size_t)-256); - test_assert(2, p1 == NULL, "allocation not failed"); - - /* Initial local heap state.*/ - (void)chHeapStatus(&test_heap, &sz); - - /* Same order.*/ - p1 = chHeapAlloc(&test_heap, SIZE); - p2 = chHeapAlloc(&test_heap, SIZE); - p3 = chHeapAlloc(&test_heap, SIZE); - chHeapFree(p1); /* Does not merge.*/ - chHeapFree(p2); /* Merges backward.*/ - chHeapFree(p3); /* Merges both sides.*/ - test_assert(3, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); - - /* Reverse order.*/ - p1 = chHeapAlloc(&test_heap, SIZE); - p2 = chHeapAlloc(&test_heap, SIZE); - p3 = chHeapAlloc(&test_heap, SIZE); - chHeapFree(p3); /* Merges forward.*/ - chHeapFree(p2); /* Merges forward.*/ - chHeapFree(p1); /* Merges forward.*/ - test_assert(4, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); - - /* Small fragments handling.*/ - p1 = chHeapAlloc(&test_heap, SIZE + 1); - p2 = chHeapAlloc(&test_heap, SIZE); - chHeapFree(p1); - test_assert(5, chHeapStatus(&test_heap, &n) == 2, "invalid state"); - p1 = chHeapAlloc(&test_heap, SIZE); - /* Note, the first situation happens when the alignment size is smaller - than the header size, the second in the other cases.*/ - test_assert(6, (chHeapStatus(&test_heap, &n) == 1) || - (chHeapStatus(&test_heap, &n) == 2), "heap fragmented"); - chHeapFree(p2); - chHeapFree(p1); - test_assert(7, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); - - /* Skip fragment handling.*/ - p1 = chHeapAlloc(&test_heap, SIZE); - p2 = chHeapAlloc(&test_heap, SIZE); - chHeapFree(p1); - test_assert(8, chHeapStatus(&test_heap, &n) == 2, "invalid state"); - p1 = chHeapAlloc(&test_heap, SIZE * 2); /* Skips first fragment.*/ - chHeapFree(p1); - chHeapFree(p2); - test_assert(9, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); - - /* Allocate all handling.*/ - (void)chHeapStatus(&test_heap, &n); - p1 = chHeapAlloc(&test_heap, n); - test_assert(10, chHeapStatus(&test_heap, &n) == 0, "not empty"); - chHeapFree(p1); - - test_assert(11, chHeapStatus(&test_heap, &n) == 1, "heap fragmented"); - test_assert(12, n == sz, "size changed"); -} - -const struct testcase testheap1 = { - heap1_gettest, - heap1_setup, - NULL, - heap1_execute -}; - -#endif /* CH_USE_HEAP.*/ - -/** - * @brief Test sequence for heap. - */ -const struct testcase * const patternheap[] = { -#if CH_USE_HEAP - &testheap1, -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testheap.h b/ChibiOS_2.0.8/test/testheap.h deleted file mode 100644 index 2f53f39..0000000 --- a/ChibiOS_2.0.8/test/testheap.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTHEAP_H_ -#define _TESTHEAP_H_ - -extern const struct testcase *patternheap[]; - -#endif /* _TESTHEAP_H_ */ diff --git a/ChibiOS_2.0.8/test/testmbox.c b/ChibiOS_2.0.8/test/testmbox.c deleted file mode 100644 index 113356e..0000000 --- a/ChibiOS_2.0.8/test/testmbox.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_mbox Mailboxes test - * - * File: @ref testmbox.c - * - *

Description

- * This module implements the test sequence for the @ref mailboxes subsystem. - * - *

Objective

- * Objective of the test module is to cover 100% of the @ref mailboxes - * subsystem code.
- * Note that the @ref mailboxes subsystem depends on the @ref semaphores - * subsystem that has to met its testing objectives as well. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_MAILBOXES - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_mbox_001 - * . - * @file testmbox.c - * @brief Mailboxes test source file - * @file testmbox.h - * @brief Mailboxes header file - */ - -#if CH_USE_MAILBOXES - -#define ALLOWED_DELAY MS2ST(5) -#define MB_SIZE 5 - -/* - * Note, the static initializers are not really required because the - * variables are explicitly initialized in each test case. It is done in order - * to test the macros. - */ -static MAILBOX_DECL(mb1, test.wa.T0, MB_SIZE); - -/** - * @page test_mbox_001 Queuing and timeouts - * - *

Description

- * Messages are posted/fetched from a mailbox in carefully designed sequences - * in order to stimulate all the possible code paths inside the mailbox.
- * The test expects to find a consistent mailbox status after each operation. - */ - -static char *mbox1_gettest(void) { - - return "Mailboxes, queuing and timeouts"; -} - -static void mbox1_setup(void) { - - chMBInit(&mb1, (msg_t *)test.wa.T0, MB_SIZE); -} - -static void mbox1_execute(void) { - msg_t msg1, msg2; - unsigned i; - - /* - * Testing initial space. - */ - test_assert(1, chMBGetEmpty(&mb1) == MB_SIZE, "wrong size"); - - /* - * Testing enqueuing and backward circularity. - */ - for (i = 0; i < MB_SIZE - 1; i++) { - msg1 = chMBPost(&mb1, 'B' + i, TIME_INFINITE); - test_assert(2, msg1 == RDY_OK, "wrong wake-up message"); - } - msg1 = chMBPostAhead(&mb1, 'A', TIME_INFINITE); - test_assert(3, msg1 == RDY_OK, "wrong wake-up message"); - - /* - * Testing post timeout. - */ - msg1 = chMBPost(&mb1, 'X', 1); - test_assert(4, msg1 == RDY_TIMEOUT, "wrong wake-up message"); - - /* - * Testing final conditions. - */ - test_assert(5, chMBGetEmpty(&mb1) == 0, "still empty"); - test_assert(6, chMBGetFull(&mb1) == MB_SIZE, "not full"); - test_assert(7, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned"); - - /* - * Testing dequeuing. - */ - for (i = 0; i < MB_SIZE; i++) { - msg1 = chMBFetch(&mb1, &msg2, TIME_INFINITE); - test_assert(8, msg1 == RDY_OK, "wrong wake-up message"); - test_emit_token(msg2); - } - test_assert_sequence(9, "ABCDE"); - - /* - * Testing buffer circularity. - */ - msg1 = chMBPost(&mb1, 'B' + i, TIME_INFINITE); - test_assert(10, msg1 == RDY_OK, "wrong wake-up message"); - msg1 = chMBFetch(&mb1, &msg2, TIME_INFINITE); - test_assert(11, msg1 == RDY_OK, "wrong wake-up message"); - test_assert(12, mb1.mb_buffer == mb1.mb_wrptr, "write pointer not aligned to base"); - test_assert(13, mb1.mb_buffer == mb1.mb_rdptr, "read pointer not aligned to base"); - - /* - * Testing fetch timeout. - */ - msg1 = chMBFetch(&mb1, &msg2, 1); - test_assert(14, msg1 == RDY_TIMEOUT, "wrong wake-up message"); - - /* - * Testing final conditions. - */ - test_assert(15, chMBGetEmpty(&mb1) == MB_SIZE, "not empty"); - test_assert(16, chMBGetFull(&mb1) == 0, "still full"); - test_assert(17, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned"); - - /* - * Testing reset. - */ - chMBReset(&mb1); - - /* - * Re-testing final conditions. - */ - test_assert(18, chMBGetEmpty(&mb1) == MB_SIZE, "not empty"); - test_assert(19, chMBGetFull(&mb1) == 0, "still full"); - test_assert(20, mb1.mb_buffer == mb1.mb_wrptr, "write pointer not aligned to base"); - test_assert(21, mb1.mb_buffer == mb1.mb_rdptr, "read pointer not aligned to base"); -} - -const struct testcase testmbox1 = { - mbox1_gettest, - mbox1_setup, - NULL, - mbox1_execute -}; - -#endif /* CH_USE_MAILBOXES */ - -/** - * @brief Test sequence for mailboxes. - */ -const struct testcase * const patternmbox[] = { -#if CH_USE_MAILBOXES - &testmbox1, -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testmbox.h b/ChibiOS_2.0.8/test/testmbox.h deleted file mode 100644 index 2155166..0000000 --- a/ChibiOS_2.0.8/test/testmbox.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTMBOX_H_ -#define _TESTMBOX_H_ - -extern const struct testcase *patternmbox[]; - -#endif /* _TESTMBOX_H_ */ diff --git a/ChibiOS_2.0.8/test/testmsg.c b/ChibiOS_2.0.8/test/testmsg.c deleted file mode 100644 index ea1ca9e..0000000 --- a/ChibiOS_2.0.8/test/testmsg.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_msg Messages test - * - * File: @ref testmsg.c - * - *

Description

- * This module implements the test sequence for the @ref messages subsystem. - * - *

Objective

- * Objective of the test module is to cover 100% of the @ref messages - * subsystem code. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_MESSAGES - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_msg_001 - * . - * @file testmsg.c - * @brief Messages test source file - * @file testmsg.h - * @brief Messages header file - */ - -#if CH_USE_MESSAGES - -/** - * @page test_msg_001 Messages Server loop - * - *

Description

- * A thread is spawned that sends four messages back to the tester thread.
- * The test expect to receive the messages in the correct sequence and to - * not find a fifth message waiting. - */ - -static char *msg1_gettest(void) { - - return "Messages, loop"; -} - -static msg_t thread(void *p) { - - chMsgSend(p, 'A'); - chMsgSend(p, 'B'); - chMsgSend(p, 'C'); - chMsgSend(p, 'D'); - return 0; -} - -static void msg1_execute(void) { - msg_t msg; - - /* - * Testing the whole messages loop. - */ - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() + 1, - thread, chThdSelf()); - chMsgRelease(msg = chMsgWait()); - test_emit_token(msg); - chMsgRelease(msg = chMsgWait()); - test_emit_token(msg); - chMsgRelease(msg = chMsgWait()); - test_emit_token(msg); - test_assert_sequence(1, "ABC"); - - /* - * Testing message fetch using chMsgGet(). - * Note, the following is valid because the sender has higher priority than - * the receiver. - */ - msg = chMsgGet(); - test_assert(1, msg != 0, "no message"); - chMsgRelease(0); - test_assert(2, msg == 'D', "wrong message"); - - /* - * Must not have pending messages. - */ - msg = chMsgGet(); - test_assert(3, msg == 0, "unknown message"); -} - -const struct testcase testmsg1 = { - msg1_gettest, - NULL, - NULL, - msg1_execute -}; - -#endif /* CH_USE_MESSAGES */ - -/** - * @brief Test sequence for messages. - */ -const struct testcase * const patternmsg[] = { -#if CH_USE_MESSAGES - &testmsg1, -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testmsg.h b/ChibiOS_2.0.8/test/testmsg.h deleted file mode 100644 index f2e77a7..0000000 --- a/ChibiOS_2.0.8/test/testmsg.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTMSG_H_ -#define _TESTMSG_H_ - -extern const struct testcase *patternmsg[]; - -#endif /* _TESTMSG_H_ */ diff --git a/ChibiOS_2.0.8/test/testmtx.c b/ChibiOS_2.0.8/test/testmtx.c deleted file mode 100644 index 5b26455..0000000 --- a/ChibiOS_2.0.8/test/testmtx.c +++ /dev/null @@ -1,674 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_mtx Mutexes test - * - * File: @ref testmtx.c - * - *

Description

- * This module implements the test sequence for the @ref mutexes and - * @ref condvars subsystems.
- * Tests on those subsystems are particularly critical because the system-wide - * implications of the Priority Inheritance mechanism. - * - *

Objective

- * Objective of the test module is to cover 100% of the subsystems code. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_MUTEXES - * - @p CH_USE_CONDVARS - * - @p CH_DBG_THREADS_PROFILING - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_mtx_001 - * - @subpage test_mtx_002 - * - @subpage test_mtx_003 - * - @subpage test_mtx_004 - * - @subpage test_mtx_005 - * - @subpage test_mtx_006 - * - @subpage test_mtx_007 - * - @subpage test_mtx_008 - * . - * @file testmtx.c - * @brief Mutexes and CondVars test source file - * @file testmtx.h - * @brief Mutexes and CondVars test header file - */ - -#if CH_USE_MUTEXES - -#define ALLOWED_DELAY 5 - -/* - * Note, the static initializers are not really required because the - * variables are explicitly initialized in each test case. It is done in order - * to test the macros. - */ -static MUTEX_DECL(m1); -static MUTEX_DECL(m2); -#if CH_USE_CONDVARS -static CONDVAR_DECL(c1); -#endif - -/** - * @page test_mtx_001 Priority enqueuing test - * - *

Description

- * Five threads, with increasing priority, are enqueued on a locked mutex then - * the mutex is unlocked.
- * The test expects the threads to perform their operations in increasing - * priority order regardless of the initial order. - */ -static char *mtx1_gettest(void) { - - return "Mutexes, priority enqueuing test"; -} - -static void mtx1_setup(void) { - - chMtxInit(&m1); -} - -static msg_t thread1(void *p) { - - chMtxLock(&m1); - test_emit_token(*(char *)p); - chMtxUnlock(); - return 0; -} - -static void mtx1_execute(void) { - - tprio_t prio = chThdGetPriority(); // Because priority inheritance. - chMtxLock(&m1); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread1, "E"); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread1, "D"); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, prio+3, thread1, "C"); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, prio+4, thread1, "B"); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, prio+5, thread1, "A"); - chMtxUnlock(); - test_wait_threads(); - test_assert(1, prio == chThdGetPriority(), "wrong priority level"); - test_assert_sequence(2, "ABCDE"); -} - -const struct testcase testmtx1 = { - mtx1_gettest, - mtx1_setup, - NULL, - mtx1_execute -}; - -#if CH_DBG_THREADS_PROFILING -/** - * @page test_mtx_002 Priority inheritance, simple case - * - *

Description

- * Three threads are involved in the classic priority inversion scenario, a - * medium priority thread tries to starve an high priority thread by - * blocking a low priority thread into a mutex lock zone.
- * The test expects the threads to reach their goal in increasing priority - * order by rearranging their priorities in order to avoid the priority - * inversion trap. - * - *

Scenario

- * This weird looking diagram should explain what happens in the test case: - * @code - * Time ----> 0 10 20 30 40 50 60 70 80 90 100 - * 0 ......AL++++++++++............2+++++++++++AU0---------------++++++G... - * 1 ..................++++++++++++------------------++++++++++++G......... - * 2 .............................AL..........++++++AUG................... - * ^ ^ - * Legend: - * 0..2 - Priority levels - * +++ - Running - * --- - Ready - * ... - Waiting or Terminated - * xL - Lock operation on mutex 'x' - * xUn - Unlock operation on mutex 'x' with priority returning to level 'n' - * G - Goal - * ^ - Priority transition (boost or return). - * @endcode - */ - -static char *mtx2_gettest(void) { - - return "Mutexes, priority inheritance, simple case"; -} - -static void mtx2_setup(void) { - - chMtxInit(&m1); -} - -/* Low priority thread */ -static msg_t thread2L(void *p) { - - (void)p; - chMtxLock(&m1); - test_cpu_pulse(40); - chMtxUnlock(); - test_cpu_pulse(10); - test_emit_token('C'); - return 0; -} - -/* Medium priority thread */ -static msg_t thread2M(void *p) { - - (void)p; - chThdSleepMilliseconds(20); - test_cpu_pulse(40); - test_emit_token('B'); - return 0; -} - -/* High priority thread */ -static msg_t thread2H(void *p) { - - (void)p; - chThdSleepMilliseconds(40); - chMtxLock(&m1); - test_cpu_pulse(10); - chMtxUnlock(); - test_emit_token('A'); - return 0; -} - -static void mtx2_execute(void) { - systime_t time; - - test_wait_tick(); - time = chTimeNow(); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-1, thread2H, 0); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-2, thread2M, 0); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread2L, 0); - test_wait_threads(); - test_assert_sequence(1, "ABC"); - test_assert_time_window(2, time + MS2ST(100), time + MS2ST(100) + ALLOWED_DELAY); -} - -const struct testcase testmtx2 = { - mtx2_gettest, - mtx2_setup, - NULL, - mtx2_execute -}; - -/** - * @page test_mtx_003 Priority inheritance, complex case - * - *

Description

- * Five threads are involved in the complex priority inversion scenario, - * please refer to the diagram below for the complete scenario.
- * The test expects the threads to perform their operations in increasing - * priority order by rearranging their priorities in order to avoid the - * priority inversion trap. - * - *

Scenario

- * This weird looking diagram should explain what happens in the test case: - * @code - * Time ----> 0 10 20 30 40 50 60 70 80 90 100 110 - * 0 ......BL++++------------2+++++------4+++++BU0---------------------------G..... - * 1 ............AL++++2+++++BL----------4-----++++++BU4+++AU1---------------G..... - * 2 ..................AL----------------------------------------------++++++AUG... - * 3 ..............................+++++++-----------------------++++++G........... - * 4 ....................................AL................++++++AUG............... - * ^ ^ ^ ^ ^ ^ - * Legend: - * 0..4 - Priority levels - * +++ - Running - * --- - Ready - * ... - Waiting or Terminated - * xL - Lock operation on mutex 'x' - * xUn - Unlock operation on mutex 'x' with priority returning to level 'n' - * ^ - Priority transition (boost or return). - * @endcode - */ -static char *mtx3_gettest(void) { - - return "Mutexes, priority inheritance, complex case"; -} - -static void mtx3_setup(void) { - - chMtxInit(&m1); // Mutex B - chMtxInit(&m2); // Mutex A -} - -/* Lowest priority thread */ -static msg_t thread3LL(void *p) { - - (void)p; - chMtxLock(&m1); - test_cpu_pulse(30); - chMtxUnlock(); - test_emit_token('E'); - return 0; -} - -/* Low priority thread */ -static msg_t thread3L(void *p) { - - (void)p; - chThdSleepMilliseconds(10); - chMtxLock(&m2); - test_cpu_pulse(20); - chMtxLock(&m1); - test_cpu_pulse(10); - chMtxUnlock(); - test_cpu_pulse(10); - chMtxUnlock(); - test_emit_token('D'); - return 0; -} - -/* Medium priority thread */ -static msg_t thread3M(void *p) { - - (void)p; - chThdSleepMilliseconds(20); - chMtxLock(&m2); - test_cpu_pulse(10); - chMtxUnlock(); - test_emit_token('C'); - return 0; -} - -/* High priority thread */ -static msg_t thread3H(void *p) { - - (void)p; - chThdSleepMilliseconds(40); - test_cpu_pulse(20); - test_emit_token('B'); - return 0; -} - -/* Highest priority thread */ -static msg_t thread3HH(void *p) { - - (void)p; - chThdSleepMilliseconds(50); - chMtxLock(&m2); - test_cpu_pulse(10); - chMtxUnlock(); - test_emit_token('A'); - return 0; -} - -static void mtx3_execute(void) { - systime_t time; - - test_wait_tick(); - time = chTimeNow(); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-5, thread3LL, 0); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-4, thread3L, 0); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread3M, 0); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-2, thread3H, 0); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-1, thread3HH, 0); - test_wait_threads(); - test_assert_sequence(1, "ABCDE"); - test_assert_time_window(2, time + MS2ST(110), time + MS2ST(110) + ALLOWED_DELAY); -} - -const struct testcase testmtx3 = { - mtx3_gettest, - mtx3_setup, - NULL, - mtx3_execute -}; -#endif /* CH_DBG_THREADS_PROFILING */ - -/** - * @page test_mtx_004 Priority return verification - * - *

Description

- * Two threads are spawned that try to lock the mutexes locked by the tester - * thread with precise timing.
- * The test expects that the priority changes caused by the priority - * inheritance algorithm happen at the right moment and with the right values. - */ -static char *mtx4_gettest(void) { - - return "Mutexes, priority return"; -} - -static void mtx4_setup(void) { - - chMtxInit(&m1); - chMtxInit(&m2); -} - -static msg_t thread4a(void *p) { - - (void)p; - chThdSleepMilliseconds(50); - chMtxLock(&m2); - chMtxUnlock(); - return 0; -} - -static msg_t thread4b(void *p) { - - (void)p; - chThdSleepMilliseconds(150); - chMtxLock(&m1); - chMtxUnlock(); - return 0; -} - -static void mtx4_execute(void) { - tprio_t p, p1, p2; - - p = chThdGetPriority(); - p1 = p + 1; - p2 = p + 2; - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, p1, thread4a, "B"); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, p2, thread4b, "A"); - chMtxLock(&m2); - test_assert(1, chThdGetPriority() == p, "wrong priority level"); - chThdSleepMilliseconds(100); - test_assert(2, chThdGetPriority() == p1, "wrong priority level"); - chMtxLock(&m1); - test_assert(3, chThdGetPriority() == p1, "wrong priority level"); - chThdSleepMilliseconds(100); - test_assert(4, chThdGetPriority() == p2, "wrong priority level"); - chMtxUnlock(); - test_assert(5, chThdGetPriority() == p1, "wrong priority level"); - chThdSleepMilliseconds(100); - test_assert(6, chThdGetPriority() == p1, "wrong priority level"); - chMtxUnlockAll(); - test_assert(7, chThdGetPriority() == p, "wrong priority level"); - test_wait_threads(); - - /* Test repeated in order to cover chMtxUnlockS().*/ - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, p1, thread4a, "D"); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, p2, thread4b, "C"); - chMtxLock(&m2); - test_assert(8, chThdGetPriority() == p, "wrong priority level"); - chThdSleepMilliseconds(100); - test_assert(9, chThdGetPriority() == p1, "wrong priority level"); - chMtxLock(&m1); - test_assert(10, chThdGetPriority() == p1, "wrong priority level"); - chThdSleepMilliseconds(100); - test_assert(11, chThdGetPriority() == p2, "wrong priority level"); - chSysLock(); - chMtxUnlockS(); - chSysUnlock(); - test_assert(12, chThdGetPriority() == p1, "wrong priority level"); - chThdSleepMilliseconds(100); - test_assert(13, chThdGetPriority() == p1, "wrong priority level"); - chMtxUnlockAll(); - test_assert(14, chThdGetPriority() == p, "wrong priority level"); - test_wait_threads(); -} - -const struct testcase testmtx4 = { - mtx4_gettest, - mtx4_setup, - NULL, - mtx4_execute -}; - -/** - * @page test_mtx_005 Mutex status - * - *

Description

- * Various tests on the mutex structure status after performing some lock and - * unlock operations.
- * The test expects that the internal mutex status is consistent after each - * operation. - */ -static char *mtx5_gettest(void) { - - return "Mutexes, status"; -} - -static void mtx5_setup(void) { - - chMtxInit(&m1); -} - -static void mtx5_execute(void) { - bool_t b; - tprio_t prio; - - prio = chThdGetPriority(); - - b = chMtxTryLock(&m1); - test_assert(1, b, "already locked"); - - b = chMtxTryLock(&m1); - test_assert(2, !b, "not locked"); - - chSysLock(); - chMtxUnlockS(); - chSysUnlock(); - - test_assert(3, isempty(&m1.m_queue), "queue not empty"); - test_assert(4, m1.m_owner == NULL, "still owned"); - test_assert(5, chThdGetPriority() == prio, "wrong priority level"); -} - -const struct testcase testmtx5 = { - mtx5_gettest, - mtx5_setup, - NULL, - mtx5_execute -}; - -#if CH_USE_CONDVARS -/** - * @page test_mtx_006 Condition Variable signal test - * - *

Description

- * Five threads take a mutex and then enter a conditional variable queue, the - * tester thread then proceeds to signal the conditional variable five times - * atomically.
- * The test expects the threads to reach their goal in increasing priority - * order regardless of the initial order. - */ -static char *mtx6_gettest(void) { - - return "CondVar, signal test"; -} - -static void mtx6_setup(void) { - - chCondInit(&c1); - chMtxInit(&m1); -} - -static msg_t thread10(void *p) { - - chMtxLock(&m1); - chCondWait(&c1); - test_emit_token(*(char *)p); - chMtxUnlock(); - return 0; -} - -static void mtx6_execute(void) { - - tprio_t prio = chThdGetPriority(); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread10, "E"); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread10, "D"); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, prio+3, thread10, "C"); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, prio+4, thread10, "B"); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, prio+5, thread10, "A"); - chSysLock(); - chCondSignalI(&c1); - chCondSignalI(&c1); - chCondSignalI(&c1); - chCondSignalI(&c1); - chCondSignalI(&c1); - chSchRescheduleS(); - chSysUnlock(); - test_wait_threads(); - test_assert_sequence(1, "ABCDE"); -} - -const struct testcase testmtx6 = { - mtx6_gettest, - mtx6_setup, - NULL, - mtx6_execute -}; - -/** - * @page test_mtx_007 Condition Variable broadcast test - * - *

Description

- * Five threads take a mutex and then enter a conditional variable queue, the - * tester thread then proceeds to broadcast the conditional variable.
- * The test expects the threads to reach their goal in increasing priority - * order regardless of the initial order. - */ -static char *mtx7_gettest(void) { - - return "CondVar, broadcast test"; -} - -static void mtx7_setup(void) { - - chCondInit(&c1); - chMtxInit(&m1); -} - -static void mtx7_execute(void) { - - // Bacause priority inheritance. - tprio_t prio = chThdGetPriority(); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread10, "E"); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread10, "D"); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, prio+3, thread10, "C"); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, prio+4, thread10, "B"); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, prio+5, thread10, "A"); - chCondBroadcast(&c1); - test_wait_threads(); - test_assert_sequence(1, "ABCDE"); -} - -const struct testcase testmtx7 = { - mtx7_gettest, - mtx7_setup, - NULL, - mtx7_execute -}; - -/** - * @page test_mtx_008 Condition Variable priority boost test - * - *

Description

- * This test case verifies the priority boost of a thread waiting on a - * conditional variable queue. It tests this very specific situation in order - * to complete the code coverage. - */ -static char *mtx8_gettest(void) { - - return "CondVar, boost test"; -} - -static void mtx8_setup(void) { - - chCondInit(&c1); - chMtxInit(&m1); - chMtxInit(&m2); -} - -static msg_t thread11(void *p) { - - chMtxLock(&m2); - chMtxLock(&m1); -#if CH_USE_CONDVARS_TIMEOUT - chCondWaitTimeout(&c1, TIME_INFINITE); -#else - chCondWait(&c1); -#endif - test_emit_token(*(char *)p); - chMtxUnlock(); - chMtxUnlock(); - return 0; -} - -static msg_t thread12(void *p) { - - chMtxLock(&m2); - test_emit_token(*(char *)p); - chMtxUnlock(); - return 0; -} - -static void mtx8_execute(void) { - - tprio_t prio = chThdGetPriority(); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, prio+1, thread11, "A"); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, prio+2, thread10, "C"); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, prio+3, thread12, "B"); - chCondSignal(&c1); - chCondSignal(&c1); - test_wait_threads(); - test_assert_sequence(1, "ABC"); -} - -const struct testcase testmtx8 = { - mtx8_gettest, - mtx8_setup, - NULL, - mtx8_execute -}; -#endif /* CH_USE_CONDVARS */ -#endif /* CH_USE_MUTEXES */ - -/** - * @brief Test sequence for mutexes. - */ -const struct testcase * const patternmtx[] = { -#if CH_USE_MUTEXES - &testmtx1, -#if CH_DBG_THREADS_PROFILING - &testmtx2, - &testmtx3, -#endif - &testmtx4, - &testmtx5, -#if CH_USE_CONDVARS - &testmtx6, - &testmtx7, - &testmtx8, -#endif -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testmtx.h b/ChibiOS_2.0.8/test/testmtx.h deleted file mode 100644 index c68a985..0000000 --- a/ChibiOS_2.0.8/test/testmtx.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTMTX_H_ -#define _TESTMTX_H_ - -extern const struct testcase *patternmtx[]; - -#endif /* _TESTMTX_H_ */ diff --git a/ChibiOS_2.0.8/test/testpools.c b/ChibiOS_2.0.8/test/testpools.c deleted file mode 100644 index 14bfca6..0000000 --- a/ChibiOS_2.0.8/test/testpools.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_pools Memory Pools test - * - * File: @ref testpools.c - * - *

Description

- * This module implements the test sequence for the @ref pools subsystem. - * - *

Objective

- * Objective of the test module is to cover 100% of the @ref pools code. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_MEMPOOLS - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_pools_001 - * . - * @file testpools.c - * @brief Memory Pools test source file - * @file testpools.h - * @brief Memory Pools test header file - */ - -#if CH_USE_MEMPOOLS - -static MEMORYPOOL_DECL(mp1, THD_WA_SIZE(THREADS_STACK_SIZE), NULL); - -/** - * @page test_pools_001 Allocation and enqueuing test - * - *

Description

- * Five memory blocks are added to a memory pool then removed.
- * The test expects to find the pool queue in the proper status after each - * operation. - */ - -static void *null_provider(size_t size) { - - (void)size; - return NULL; -} - -static char *pools1_gettest(void) { - - return "Memory Pools, queue/dequeue"; -} - -static void pools1_setup(void) { - - chPoolInit(&mp1, THD_WA_SIZE(THREADS_STACK_SIZE), NULL); -} - -static void pools1_execute(void) { - int i; - - /* Adding the WAs to the pool. */ - for (i = 0; i < MAX_THREADS; i++) - chPoolFree(&mp1, wa[i]); - - /* Empting the pool again. */ - for (i = 0; i < MAX_THREADS; i++) - test_assert(1, chPoolAlloc(&mp1) != NULL, "list empty"); - - /* Now must be empty. */ - test_assert(2, chPoolAlloc(&mp1) == NULL, "list not empty"); - - /* Covering the case where a provider is unable to return more memory.*/ - chPoolInit(&mp1, 16, null_provider); - test_assert(3, chPoolAlloc(&mp1) == NULL, "provider returned memory"); -} - -const struct testcase testpools1 = { - pools1_gettest, - pools1_setup, - NULL, - pools1_execute -}; - -#endif /* CH_USE_MEMPOOLS */ - -/* - * @brief Test sequence for pools. - */ -const struct testcase * const patternpools[] = { -#if CH_USE_MEMPOOLS - &testpools1, -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testpools.h b/ChibiOS_2.0.8/test/testpools.h deleted file mode 100644 index 616ed3a..0000000 --- a/ChibiOS_2.0.8/test/testpools.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTPOOLS_H_ -#define _TESTPOOLS_H_ - -extern const struct testcase *patternpools[]; - -#endif /* _TESTPOOLS_H_ */ diff --git a/ChibiOS_2.0.8/test/testqueues.c b/ChibiOS_2.0.8/test/testqueues.c deleted file mode 100644 index 803c74d..0000000 --- a/ChibiOS_2.0.8/test/testqueues.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_queues I/O Queues test - * - * File: @ref testqueues.c - * - *

Description

- * This module implements the test sequence for the @ref io_queues subsystem. - * The tests are performed by inserting and removing data from queues and by - * checking both the queues status and the correct sequence of the extracted - * data. - * - *

Objective

- * Objective of the test module is to cover 100% of the @ref io_queues code.
- * Note that the @ref io_queues subsystem depends on the @ref semaphores - * subsystem that has to met its testing objectives as well. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_QUEUES (and dependent options) - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_queues_001 - * - @subpage test_queues_002 - * . - * @file testqueues.c - * @brief I/O Queues test source file - * @file testqueues.h - * @brief I/O Queues test header file - */ - -#if CH_USE_QUEUES - -#define TEST_QUEUES_SIZE 4 - -static void notify(void) {} - -/* - * Note, the static initializers are not really required because the - * variables are explicitly initialized in each test case. It is done in order - * to test the macros. - */ -static INPUTQUEUE_DECL(iq, test.wa.T0, TEST_QUEUES_SIZE, notify); -static OUTPUTQUEUE_DECL(oq, test.wa.T1, TEST_QUEUES_SIZE, notify); - -/** - * @page test_queues_001 Input Queues functionality and APIs - * - *

Description

- * This test case tests sysnchronos and asynchronous operations on an - * @p InputQueue object including timeouts. The queue state must remain - * consistent through the whole test. - */ - -static char *queues1_gettest(void) { - - return "Queues, input queues"; -} - -static void queues1_setup(void) { - - chIQInit(&iq, wa[0], TEST_QUEUES_SIZE, notify); -} - -static void queues1_execute(void) { - unsigned i; - size_t n; - - /* Initial empty state */ - test_assert(1, chIQIsEmpty(&iq), "not empty"); - - /* Queue filling */ - for (i = 0; i < TEST_QUEUES_SIZE; i++) - chIQPutI(&iq, 'A' + i); - test_assert(2, chIQIsFull(&iq), "still has space"); - test_assert(3, chIQPutI(&iq, 0) == Q_FULL, "failed to report Q_FULL"); - - /* Queue emptying */ - for (i = 0; i < TEST_QUEUES_SIZE; i++) - test_emit_token(chIQGet(&iq)); - test_assert(4, chIQIsEmpty(&iq), "still full"); - test_assert_sequence(5, "ABCD"); - - /* Queue filling again */ - for (i = 0; i < TEST_QUEUES_SIZE; i++) - chIQPutI(&iq, 'A' + i); - - /* Reading the whole thing */ - n = chIQReadTimeout(&iq, wa[1], TEST_QUEUES_SIZE * 2, TIME_IMMEDIATE); - test_assert(6, n == TEST_QUEUES_SIZE, "wrong returned size"); - test_assert(7, chIQIsEmpty(&iq), "still full"); - - /* Queue filling again */ - for (i = 0; i < TEST_QUEUES_SIZE; i++) - chIQPutI(&iq, 'A' + i); - - /* Partial reads */ - n = chIQReadTimeout(&iq, wa[1], TEST_QUEUES_SIZE / 2, TIME_IMMEDIATE); - test_assert(8, n == TEST_QUEUES_SIZE / 2, "wrong returned size"); - n = chIQReadTimeout(&iq, wa[1], TEST_QUEUES_SIZE / 2, TIME_IMMEDIATE); - test_assert(9, n == TEST_QUEUES_SIZE / 2, "wrong returned size"); - test_assert(10, chIQIsEmpty(&iq), "still full"); - - /* Testing reset */ - chIQPutI(&iq, 0); - chIQResetI(&iq); - test_assert(11, chIQIsEmpty(&iq), "still full"); - - /* Timeout */ - test_assert(12, chIQGetTimeout(&iq, 10) == Q_TIMEOUT, "wrong timeout return"); -} - -const struct testcase testqueues1 = { - queues1_gettest, - queues1_setup, - NULL, - queues1_execute -}; - -/** - * @page test_queues_002 Output Queues functionality and APIs - * - *

Description

- * This test case tests sysnchronos and asynchronous operations on an - * @p OutputQueue object including timeouts. The queue state must remain - * consistent through the whole test. - */ -static char *queues2_gettest(void) { - - return "Queues, output queues"; -} - -static void queues2_setup(void) { - - chOQInit(&oq, wa[0], TEST_QUEUES_SIZE, notify); -} - -static void queues2_execute(void) { - unsigned i; - size_t n; - - /* Initial empty state */ - test_assert(1, chOQIsEmpty(&oq), "not empty"); - - /* Queue filling */ - for (i = 0; i < TEST_QUEUES_SIZE; i++) - chOQPut(&oq, 'A' + i); - test_assert(2, chOQIsFull(&oq), "still has space"); - - /* Queue emptying */ - for (i = 0; i < TEST_QUEUES_SIZE; i++) - test_emit_token(chOQGetI(&oq)); - test_assert(3, chOQIsEmpty(&oq), "still full"); - test_assert_sequence(4, "ABCD"); - test_assert(5, chOQGetI(&oq) == Q_EMPTY, "failed to report Q_EMPTY"); - - /* Writing the whole thing */ - n = chOQWriteTimeout(&oq, wa[1], TEST_QUEUES_SIZE * 2, TIME_IMMEDIATE); - test_assert(6, n == TEST_QUEUES_SIZE, "wrong returned size"); - test_assert(7, chOQIsFull(&oq), "not full"); - - /* Testing reset */ - chOQResetI(&oq); - test_assert(8, chOQIsEmpty(&oq), "still full"); - - /* Partial writes */ - n = chOQWriteTimeout(&oq, wa[1], TEST_QUEUES_SIZE / 2, TIME_IMMEDIATE); - test_assert(9, n == TEST_QUEUES_SIZE / 2, "wrong returned size"); - n = chOQWriteTimeout(&oq, wa[1], TEST_QUEUES_SIZE / 2, TIME_IMMEDIATE); - test_assert(10, n == TEST_QUEUES_SIZE / 2, "wrong returned size"); - test_assert(11, chOQIsFull(&oq), "not full"); - - /* Timeout */ - test_assert(12, chOQPutTimeout(&oq, 0, 10) == Q_TIMEOUT, "wrong timeout return"); -} - -const struct testcase testqueues2 = { - queues2_gettest, - queues2_setup, - NULL, - queues2_execute -}; -#endif /* CH_USE_QUEUES */ - -/** - * @brief Test sequence for queues. - */ -const struct testcase * const patternqueues[] = { -#if CH_USE_QUEUES - &testqueues1, - &testqueues2, -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testqueues.h b/ChibiOS_2.0.8/test/testqueues.h deleted file mode 100644 index f5ad2ca..0000000 --- a/ChibiOS_2.0.8/test/testqueues.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTQUEUES_H_ -#define _TESTQUEUES_H_ - -extern const struct testcase *patternqueues[]; - -#endif /* _TESTQUEUES_H_ */ diff --git a/ChibiOS_2.0.8/test/testsem.c b/ChibiOS_2.0.8/test/testsem.c deleted file mode 100644 index 619ed56..0000000 --- a/ChibiOS_2.0.8/test/testsem.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_sem Semaphores test - * - * File: @ref testsem.c - * - *

Description

- * This module implements the test sequence for the @ref semaphores subsystem. - * - *

Objective

- * Objective of the test module is to cover 100% of the @ref semaphores code. - * - *

Preconditions

- * The module requires the following kernel options: - * - @p CH_USE_SEMAPHORES - * . - * In case some of the required options are not enabled then some or all tests - * may be skipped. - * - *

Test Cases

- * - @subpage test_sem_001 - * - @subpage test_sem_002 - * - @subpage test_sem_003 - * . - * @file testsem.c - * @brief Semaphores test source file - * @file testsem.h - * @brief Semaphores test header file - */ - -#if CH_USE_SEMAPHORES - -#define ALLOWED_DELAY MS2ST(5) - -/* - * Note, the static initializers are not really required because the - * variables are explicitly initialized in each test case. It is done in order - * to test the macros. - */ -static SEMAPHORE_DECL(sem1, 0); - -/** - * @page test_sem_001 Enqueuing test - * - *

Description

- * Five threads with randomized priorities are enqueued to a semaphore then - * awakened one at time.
- * The test expects that the threads reach their goal in FIFO order or - * priority order depending on the CH_USE_SEMAPHORES_PRIORITY configuration - * setting. - */ -static char *sem1_gettest(void) { - - return "Semaphores, enqueuing"; -} - -static void sem1_setup(void) { - - chSemInit(&sem1, 0); -} - -static msg_t thread1(void *p) { - - chSemWait(&sem1); - test_emit_token(*(char *)p); - return 0; -} - -static void sem1_execute(void) { - - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+5, thread1, "A"); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()+1, thread1, "B"); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()+3, thread1, "C"); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()+4, thread1, "D"); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()+2, thread1, "E"); - chSemSignal(&sem1); - chSemSignal(&sem1); - chSemSignal(&sem1); - chSemSignal(&sem1); - chSemSignal(&sem1); - test_wait_threads(); -#if CH_USE_SEMAPHORES_PRIORITY - test_assert_sequence(1, "ADCEB"); -#else - test_assert_sequence(1, "ABCDE"); -#endif -} - -/** - * @page test_sem_002 Timeout test - * - *

Description

- * The three possible semaphore waiting modes (do not wait, wait with timeout, - * wait without timeout) are explored.
- * The test expects that the semaphore wait function returns the correct value - * in each of the above scenario and that the semaphore structure status is - * correct after each operation. - */ -const struct testcase testsem1 = { - sem1_gettest, - sem1_setup, - NULL, - sem1_execute -}; - -static char *sem2_gettest(void) { - - return "Semaphores, timeout"; -} - -static void sem2_setup(void) { - - chSemInit(&sem1, 0); -} - -static msg_t thread2(void *p) { - - (void)p; - chThdSleepMilliseconds(50); - chSysLock(); - chSemSignalI(&sem1); /* For coverage reasons */ - chSchRescheduleS(); - chSysUnlock(); - return 0; -} - -static void sem2_execute(void) { - int i; - systime_t target_time; - msg_t msg; - - /* - * Testing special case TIME_IMMEDIATE. - */ - msg = chSemWaitTimeout(&sem1, TIME_IMMEDIATE); - test_assert(1, msg == RDY_TIMEOUT, "wrong wake-up message"); - test_assert(2, isempty(&sem1.s_queue), "queue not empty"); - test_assert(3, sem1.s_cnt == 0, "counter not zero"); - - /* - * Testing not timeout condition. - */ - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority() - 1, - thread2, 0); - msg = chSemWaitTimeout(&sem1, MS2ST(500)); - test_wait_threads(); - test_assert(4, msg == RDY_OK, "wrong wake-up message"); - test_assert(5, isempty(&sem1.s_queue), "queue not empty"); - test_assert(6, sem1.s_cnt == 0, "counter not zero"); - - /* - * Testing timeout condition. - */ - test_wait_tick(); - target_time = chTimeNow() + MS2ST(5 * 500); - for (i = 0; i < 5; i++) { - test_emit_token('A' + i); - msg = chSemWaitTimeout(&sem1, MS2ST(500)); - test_assert(7, msg == RDY_TIMEOUT, "wrong wake-up message"); - test_assert(8, isempty(&sem1.s_queue), "queue not empty"); - test_assert(9, sem1.s_cnt == 0, "counter not zero"); - } - test_assert_sequence(10, "ABCDE"); - test_assert_time_window(11, target_time, target_time + ALLOWED_DELAY); -} - -const struct testcase testsem2 = { - sem2_gettest, - sem2_setup, - NULL, - sem2_execute -}; - -#if CH_USE_SEMSW -/** - * @page test_sem_003 Atomic signal-wait test - * - *

Description

- * This test case explicitly address the @p chSemWaitSignal() function. A - * thread is created that performs a wait and a signal operations. - * The tester thread is awakened from an atomic wait/signal operation.
- * The test expects that the semaphore wait function returns the correct value - * in each of the above scenario and that the semaphore structure status is - * correct after each operation. - */ - -static char *sem3_gettest(void) { - - return "Semaphores, atomic signal-wait"; -} - -static void sem3_setup(void) { - - chSemInit(&sem1, 0); -} - -static msg_t thread3(void *p) { - - (void)p; - chSemWait(&sem1); - chSemSignal(&sem1); - return 0; -} - -static void sem3_execute(void) { - - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()+1, thread3, 0); - chSemSignalWait(&sem1, &sem1); - test_assert(1, isempty(&sem1.s_queue), "queue not empty"); - test_assert(2, sem1.s_cnt == 0, "counter not zero"); - - chSemSignalWait(&sem1, &sem1); - test_assert(3, isempty(&sem1.s_queue), "queue not empty"); - test_assert(4, sem1.s_cnt == 0, "counter not zero"); -} - -const struct testcase testsem3 = { - sem3_gettest, - sem3_setup, - NULL, - sem3_execute -}; -#endif /* CH_USE_SEMSW */ -#endif /* CH_USE_SEMAPHORES */ - -/** - * @brief Test sequence for semaphores. - */ -const struct testcase * const patternsem[] = { -#if CH_USE_SEMAPHORES - &testsem1, - &testsem2, -#if CH_USE_SEMSW - &testsem3, -#endif -#endif - NULL -}; diff --git a/ChibiOS_2.0.8/test/testsem.h b/ChibiOS_2.0.8/test/testsem.h deleted file mode 100644 index 0e9663d..0000000 --- a/ChibiOS_2.0.8/test/testsem.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTSEM_H_ -#define _TESTSEM_H_ - -extern const struct testcase *patternsem[]; - -#endif /* _TESTSEM_H_ */ diff --git a/ChibiOS_2.0.8/test/testthd.c b/ChibiOS_2.0.8/test/testthd.c deleted file mode 100644 index 38dbff7..0000000 --- a/ChibiOS_2.0.8/test/testthd.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "test.h" - -/** - * @page test_threads Threads and Scheduler test - * - * File: @ref testthd.c - * - *

Description

- * This module implements the test sequence for the @ref scheduler, - * @ref threads and @ref time subsystems.
- * Note that the tests on those subsystems are formally required but most of - * their functionality is already demonstrated because the test suite itself - * depends on them, anyway double check is good. - * - *

Objective

- * Objective of the test module is to cover 100% of the subsystems code. - * - *

Preconditions

- * None. - * - *

Test Cases

- * - @subpage test_threads_001 - * - @subpage test_threads_002 - * - @subpage test_threads_003 - * - @subpage test_threads_004 - * . - * @file testthd.c - * @brief Threads and Scheduler test source file - * @file testthd.h - * @brief Threads and Scheduler test header file - */ - -/** - * @page test_threads_001 Ready List functionality #1 - * - *

Description

- * Five threads, with increasing priority, are enqueued in the ready list - * and atomically executed.
- * The test expects the threads to perform their operations in increasing - * priority order regardless of the initial order. - */ - -static msg_t thread(void *p) { - - test_emit_token(*(char *)p); - return 0; -} - -static char *thd1_gettest(void) { - - return "Threads, enqueuing test #1"; -} - -static void thd1_execute(void) { - - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-5, thread, "E"); - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-4, thread, "D"); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread, "C"); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-2, thread, "B"); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-1, thread, "A"); - test_wait_threads(); - test_assert_sequence(1, "ABCDE"); -} - -const struct testcase testthd1 = { - thd1_gettest, - NULL, - NULL, - thd1_execute -}; - -/** - * @page test_threads_002 Ready List functionality #2 - * - *

Description

- * Five threads, with pseudo-random priority, are enqueued in the ready list - * and atomically executed.
- * The test expects the threads to perform their operations in increasing - * priority order regardless of the initial order. - */ - -static char *thd2_gettest(void) { - - return "Threads, enqueuing test #2"; -} - -static void thd2_execute(void) { - - threads[1] = chThdCreateStatic(wa[1], WA_SIZE, chThdGetPriority()-4, thread, "D"); - threads[0] = chThdCreateStatic(wa[0], WA_SIZE, chThdGetPriority()-5, thread, "E"); - threads[4] = chThdCreateStatic(wa[4], WA_SIZE, chThdGetPriority()-1, thread, "A"); - threads[3] = chThdCreateStatic(wa[3], WA_SIZE, chThdGetPriority()-2, thread, "B"); - threads[2] = chThdCreateStatic(wa[2], WA_SIZE, chThdGetPriority()-3, thread, "C"); - test_wait_threads(); - test_assert_sequence(1, "ABCDE"); -} - -const struct testcase testthd2 = { - thd2_gettest, - NULL, - NULL, - thd2_execute -}; - -/** - * @page test_threads_003 Threads priority change test - * - *

Description

- * A series of priority changes are performed on the current thread in order - * to verify that the priority change happens as expected.
- * If the @p CH_USE_MUTEXES option is enabled then the priority changes are - * also tested under priority inheritance boosted priority state. - */ - -static char *thd3_gettest(void) { - - return "Threads, priority change"; -} - -static void thd3_execute(void) { - tprio_t prio, p1; - - prio = chThdGetPriority(); - p1 = chThdSetPriority(prio + 1); - test_assert(1, p1 == prio, - "unexpected returned priority level"); - test_assert(2, chThdGetPriority() == prio + 1, - "unexpected priority level"); - p1 = chThdSetPriority(p1); - test_assert(3, p1 == prio + 1, - "unexpected returned priority level"); - test_assert(4, chThdGetPriority() == prio, - "unexpected priority level"); - -#if CH_USE_MUTEXES - /* Simulates a priority boost situation (p_prio > p_realprio).*/ - chSysLock(); - chThdSelf()->p_prio += 2; - chSysUnlock(); - test_assert(5, chThdGetPriority() == prio + 2, - "unexpected priority level"); - - /* Tries to raise but below the boost level. */ - p1 = chThdSetPriority(prio + 1); - test_assert(6, p1 == prio, - "unexpected returned priority level"); - test_assert(7, chThdSelf()->p_prio == prio + 2, - "unexpected priority level"); - test_assert(8, chThdSelf()->p_realprio == prio + 1, - "unexpected returned real priority level"); - - /* Tries to raise above the boost level. */ - p1 = chThdSetPriority(prio + 3); - test_assert(9, p1 == prio + 1, - "unexpected returned priority level"); - test_assert(10, chThdSelf()->p_prio == prio + 3, - "unexpected priority level"); - test_assert(11, chThdSelf()->p_realprio == prio + 3, - "unexpected real priority level"); - - chSysLock(); - chThdSelf()->p_prio = prio; - chThdSelf()->p_realprio = prio; - chSysUnlock(); -#endif -} - -const struct testcase testthd3 = { - thd3_gettest, - NULL, - NULL, - thd3_execute -}; - -/** - * @page test_threads_004 Threads delays test - * - *

Description

- * Delay APIs and associated macros are tested, the invoking thread is verified - * to wake up at the exact expected time. - */ - -static char *thd4_gettest(void) { - - return "Threads, delays"; -} - -static void thd4_execute(void) { - systime_t time; - - test_wait_tick(); - - /* Timeouts in microseconds.*/ - time = chTimeNow(); - chThdSleepMicroseconds(100000); - test_assert_time_window(1, time + US2ST(100000), time + US2ST(100000) + 1); - - /* Timeouts in milliseconds.*/ - time = chTimeNow(); - chThdSleepMilliseconds(100); - test_assert_time_window(2, time + MS2ST(100), time + MS2ST(100) + 1); - - /* Timeouts in seconds.*/ - time = chTimeNow(); - chThdSleepSeconds(1); - test_assert_time_window(3, time + S2ST(1), time + S2ST(1) + 1); - - /* Absolute timelines.*/ - time = chTimeNow() + MS2ST(100); - chThdSleepUntil(time); - test_assert_time_window(4, time, time + 1); -} - -const struct testcase testthd4 = { - thd4_gettest, - NULL, - NULL, - thd4_execute -}; - -/** - * @brief Test sequence for threads. - */ -const struct testcase * const patternthd[] = { - &testthd1, - &testthd2, - &testthd3, - &testthd4, - NULL -}; diff --git a/ChibiOS_2.0.8/test/testthd.h b/ChibiOS_2.0.8/test/testthd.h deleted file mode 100644 index 2994c45..0000000 --- a/ChibiOS_2.0.8/test/testthd.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#ifndef _TESTRDY_H_ -#define _TESTRDY_H_ - -extern const struct testcase *patternthd[]; - -#endif /* _TESTRDY_H_ */ diff --git a/ChibiOS_2.0.8/testhal/STM32/Makefile b/ChibiOS_2.0.8/testhal/STM32/Makefile deleted file mode 100644 index 0aa9439..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/Makefile +++ /dev/null @@ -1,204 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FWLIB),) - USE_FWLIB = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - settings.c main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m3 - -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -ifeq ($(USE_FWLIB),yes) - include $(CHIBIOS)/ext/stm32lib/stm32lib.mk - CSRC += $(STM32SRC) - INCDIR += $(STM32INC) - USE_OPT += -DUSE_STDPERIPH_DRIVER -endif - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/ChibiOS_2.0.8/testhal/STM32/ch.ld b/ChibiOS_2.0.8/testhal/STM32/ch.ld deleted file mode 100644 index d64ee32..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/ch.ld +++ /dev/null @@ -1,120 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * ST32F103 memory setup. - */ -__main_stack_size__ = 0x0400; -__process_stack_size__ = 0x0400; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x08000000, len = 128k - ram : org = 0x20000000, len = 20k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ctors : - { - PROVIDE(_ctors_start_ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(_ctors_end_ = .); - } > flash - - .dtors : - { - PROVIDE(_dtors_start_ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(_dtors_end_ = .); - } > flash - - .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} - - __exidx_start = .; - .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash - __exidx_end = .; - - .eh_frame_hdr : {*(.eh_frame_hdr)} - - .eh_frame : ONLY_IF_RO {*(.eh_frame)} - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/ChibiOS_2.0.8/testhal/STM32/chconf.h b/ChibiOS_2.0.8/testhal/STM32/chconf.h deleted file mode 100644 index 65b9045..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/chconf.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/testhal/STM32/halconf.h b/ChibiOS_2.0.8/testhal/STM32/halconf.h deleted file mode 100644 index d8c494d..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/halconf.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM TRUE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/ChibiOS_2.0.8/testhal/STM32/main.c b/ChibiOS_2.0.8/testhal/STM32/main.c deleted file mode 100644 index 4f69776..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/main.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ -#include - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "settings.h" - -/* - * LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(blinker_wa, 128); -static msg_t blinker_thread(void *p) { - - (void)p; - while (TRUE) { - palClearPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - palSetPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - } - return 0; -} - -#if CH_HAL_USE_ADC -static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; -static Thread *adctp; - -/* - * ADC continuous conversion thread. - */ -size_t nx = 0, ny = 0; -static void adccallback(adcsample_t *buffer, size_t n) { - - if (samples == buffer) { - nx += n; - } - else { - ny += n; - } -} - -static WORKING_AREA(adc_continuous_wa, 256); -static msg_t adc_continuous_thread(void *p){ - - (void)p; - palSetGroupMode(IOPORT3, - PAL_PORT_BIT(0) | PAL_PORT_BIT(1), - PAL_MODE_INPUT_ANALOG); - adcStart(&ADCD1, &adccfg); - adcStartConversion(&ADCD1, &adcgrpcfg, samples, - ADC_GRP1_BUF_DEPTH, adccallback); - adcWaitConversion(&ADCD1, TIME_INFINITE); - adcStop(&ADCD1); - return 0; -} -#endif /* CH_HAL_USE_ADC */ - -#if CH_HAL_USE_CAN -static Thread *canrtp; -static Thread *canttp; - -static WORKING_AREA(can_rx_wa, 256); -static msg_t can_rx(void *p) { - EventListener el; - CANRxFrame rxmsg; - - (void)p; - chEvtRegister(&CAND1.cd_rxfull_event, &el, 0); - while(!chThdShouldTerminate()) { - if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) - continue; - while (canReceive(&CAND1, &rxmsg, TIME_IMMEDIATE) == RDY_OK) { - /* Process message.*/ - palTogglePad(IOPORT3, GPIOC_LED); - } - } - chEvtUnregister(&CAND1.cd_rxfull_event, &el); - return 0; -} - -static WORKING_AREA(can_tx_wa, 256); -static msg_t can_tx(void * p) { - CANTxFrame txmsg; - - (void)p; - txmsg.cf_IDE = CAN_IDE_EXT; - txmsg.cf_EID = 0x01234567; - txmsg.cf_RTR = CAN_RTR_DATA; - txmsg.cf_DLC = 8; - txmsg.cf_data32[0] = 0x55AA55AA; - txmsg.cf_data32[1] = 0x00FF00FF; - - while (!chThdShouldTerminate()) { - canTransmit(&CAND1, &txmsg, MS2ST(100)); -/* chThdSleepMilliseconds(5);*/ - } - return 0; -} -#endif /* CH_HAL_USE_CAN */ - -#if CH_HAL_USE_SPI -static uint8_t txbuf[512]; -static uint8_t rxbuf[512]; -static Thread *spitp; - -/* - * Maximum speed SPI continuous loopback thread. - */ -static WORKING_AREA(spi_loopback_wa, 256); -static msg_t spi_loopback_thread(void *p){ - - (void)p; - palSetPadMode(IOPORT1, GPIOA_SPI1NSS, PAL_MODE_OUTPUT_PUSHPULL); - palSetPad(IOPORT1, GPIOA_SPI1NSS); - spiStart(&SPID1, &spicfg); - while (!chThdShouldTerminate()) { - spiSelect(&SPID1); - spiExchange(&SPID1, 512, txbuf, rxbuf); - spiUnselect(&SPID1); - } - spiStop(&SPID1); - return 0; -} -#endif /* CH_HAL_USE_SPI */ - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - unsigned i; - - (void)argc; - (void)argv; - (void)i; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD2, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(blinker_wa, sizeof(blinker_wa), - NORMALPRIO + 10, blinker_thread, NULL); - -#if CH_HAL_USE_ADC - /* - * Creates the ADC continuous conversion test thread. - */ - adctp = chThdCreateStatic(adc_continuous_wa, sizeof(adc_continuous_wa), - NORMALPRIO + 9, adc_continuous_thread, NULL); -#endif - -#if CH_HAL_USE_CAN - canStart(&CAND1, &cancfg); - canrtp = chThdCreateStatic(can_rx_wa, sizeof(can_rx_wa), - NORMALPRIO + 7, can_rx, NULL); - canttp = chThdCreateStatic(can_tx_wa, sizeof(can_tx_wa), - NORMALPRIO + 7, can_tx, NULL); -#endif - -#if CH_HAL_USE_SPI - /* - * Creates the SPI loopback test thread. - */ - for (i = 0; i < sizeof(txbuf); i++) - txbuf[i] = (uint8_t)i; - spitp = chThdCreateStatic(spi_loopback_wa, sizeof(spi_loopback_wa), - NORMALPRIO + 8, spi_loopback_thread, NULL); -#endif - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. - */ - while (TRUE) { - if (palReadPad(IOPORT1, GPIOA_BUTTON)) { - TestThread(&SD2); -#if CH_HAL_USE_ADC - adcStopConversion(&ADCD1); - chThdWait(adctp); -#endif -#if CH_HAL_USE_CAN - chThdTerminate(canttp); - chThdWait(canttp); - chThdTerminate(canrtp); - chThdWait(canrtp); -#endif -#if CH_HAL_USE_SPI - chThdTerminate(spitp); - chThdWait(spitp); -#endif - chThdSleepMilliseconds(500); - TestThread(&SD2); - chThdSleepMilliseconds(500); - chSysHalt(); - } - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/ChibiOS_2.0.8/testhal/STM32/mcuconf.h b/ChibiOS_2.0.8/testhal/STM32/mcuconf.h deleted file mode 100644 index c862cf9..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/mcuconf.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * STM32 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -/* - * HAL driver system settings. - */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_MCO STM32_MCO_NOCLOCK - -/* - * ADC driver system settings. - */ -#define USE_STM32_ADC1 TRUE -#define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() - -/* - * CAN driver system settings. - */ -#define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 11 - -/* - * PWM driver system settings. - */ -#define USE_STM32_PWM1 TRUE -#define USE_STM32_PWM2 FALSE -#define USE_STM32_PWM3 FALSE -#define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM4_IRQ_PRIORITY 7 - -/* - * SERIAL driver system settings. - */ -#define USE_STM32_USART1 FALSE -#define USE_STM32_USART2 TRUE -#define USE_STM32_USART3 FALSE -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define USE_STM32_UART4 FALSE -#define USE_STM32_UART5 FALSE -#endif -#define STM32_USART1_PRIORITY 12 -#define STM32_USART2_PRIORITY 12 -#define STM32_USART3_PRIORITY 12 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 12 -#define STM32_UART5_PRIORITY 12 -#endif - -/* - * SPI driver system settings. - */ -#define USE_STM32_SPI1 TRUE -#define USE_STM32_SPI2 TRUE -#define STM32_SPI1_DMA_PRIORITY 2 -#define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/ChibiOS_2.0.8/testhal/STM32/readme.txt b/ChibiOS_2.0.8/testhal/STM32/readme.txt deleted file mode 100644 index b7d773d..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/readme.txt +++ /dev/null @@ -1,30 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** -***************************************************************************** - -** TARGET ** - -The demo will on an Olimex STM32-P103 board. - -** The Demo ** - -The demo is a stress test for the STM32 I/O subsystem, simultaneous activity -is performed on a SPI, an ADC, the CAN and a serial port all while executing -the complex test suite. -The demo is DMA and IRQ intensive so the debugging can be difficoult, so be -warned if you see anomalies in your debugger. - -** Build Procedure ** - -The demo has been tested by using the free Codesourcery GCC-based toolchain, -YAGARTO and an experimental WinARM build including GCC 4.3.0. -Just modify the TRGT line in the makefile in order to use different GCC ports. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -ST Microelectronics and are licensed under a different license. -Also note that not all the files present in the ST library are distribited -with ChibiOS/RT, you can find the whole library on the ST web site: - - http://www.st.com diff --git a/ChibiOS_2.0.8/testhal/STM32/settings.c b/ChibiOS_2.0.8/testhal/STM32/settings.c deleted file mode 100644 index f65d220..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/settings.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#include "ch.h" -#include "hal.h" -#include "settings.h" - -#if CH_HAL_USE_ADC -/* - * ADC configuration. - */ -const ADCConfig adccfg = {}; -const ADCConversionGroup adcgrpcfg = { - TRUE, - ADC_GRP1_NUM_CHANNELS, - 0, - ADC_CR2_EXTSEL_SWSTART | ADC_CR2_TSVREFE | ADC_CR2_CONT, - 0, - 0, - ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), - ADC_SQR2_SQ7_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ6_N(ADC_CHANNEL_VREFINT), - ADC_SQR3_SQ5_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ4_N(ADC_CHANNEL_IN10) | - ADC_SQR3_SQ3_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN10) | - ADC_SQR3_SQ1_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ0_N(ADC_CHANNEL_IN10) -}; -#endif - -#if CH_HAL_USE_CAN - -#define CAN_BTR_PRESCALER(n) (n) -#undef CAN_BTR_TS1 -#define CAN_BTR_TS1(n) ((n) << 16) -#undef CAN_BTR_TS2 -#define CAN_BTR_TS2(n) ((n) << 20) -#undef CAN_BTR_SJW -#define CAN_BTR_SJW(n) ((n) << 24) - -/* - * Internal loopback mode, 500KBaud, automatic wakeup, automatic recover - * from abort mode. - * See section 22.7.7 on the STM32 reference manual. - */ -const CANConfig cancfg = { - CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, - CAN_BTR_LBKM | CAN_BTR_SJW(0) | CAN_BTR_TS2(1) | - CAN_BTR_TS1(8) | CAN_BTR_PRESCALER(6), - 0, - NULL -}; -#endif /* CH_HAL_USE_CAN */ - -#if CH_HAL_USE_SPI -/* - * SPI configuration, maximum speed. - */ -const SPIConfig spicfg = { - IOPORT1, GPIOA_SPI1NSS, 0 -}; -#endif diff --git a/ChibiOS_2.0.8/testhal/STM32/settings.h b/ChibiOS_2.0.8/testhal/STM32/settings.h deleted file mode 100644 index 530b9a5..0000000 --- a/ChibiOS_2.0.8/testhal/STM32/settings.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -#if CH_HAL_USE_ADC -#define ADC_GRP1_NUM_CHANNELS 8 -#define ADC_GRP1_BUF_DEPTH 16 - -extern const ADCConfig adccfg; -extern const ADCConversionGroup adcgrpcfg; -#endif - -#if CH_HAL_USE_CAN -extern const CANConfig cancfg; -#endif /* CH_HAL_USE_CAN */ - -#if CH_HAL_USE_SPI -extern const SPIConfig spicfg; -#endif