stlinkv2.py: merge Cortex-M0 support for FSM-55
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@@ -8,11 +8,9 @@
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#define FLASH_SR_OFFSET 0x0c
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#define FLASH_CR_OFFSET 0x10
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#define COUNT 0x1000
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.cpu cortex-m3
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.cpu cortex-m0
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.thumb
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movw r2, #COUNT
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ldr r2, .SIZE
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ldr r0, .SRC_ADDR
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ldr r1, .TARGET_ADDR
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ldr r4, .FLASH_BASE_ADDR
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@@ -35,5 +33,6 @@
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bkpt #0x00
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.align 2
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.FLASH_BASE_ADDR: .word 0x40022000
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.SRC_ADDR: .word 0x20000038
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.SRC_ADDR: .word 0x2000003C
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.TARGET_ADDR: .word 0x08000000
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.SIZE: .word 0x00000000
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