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SPI flash support starts for FST-01

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NIIBE Yutaka
2012-07-06 08:26:20 +09:00
parent a796e9f145
commit 9ad6c6461d
3 changed files with 17 additions and 5 deletions
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5
ChangeLog
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@@ -1,3 +1,8 @@
2012-07-06 Niibe Yutaka <gniibe@fsij.org>
* boards/FST_01/board.h (VAL_GPIOACRL): Change for SPI flash.
* tool/stlinkv2.py (stlinkv2.setup_gpio): Likewise.
2012-07-05 Niibe Yutaka <gniibe@fsij.org> 2012-07-05 Niibe Yutaka <gniibe@fsij.org>
* src/call-rsa.c (rsa_sign, rsa_decrypt): Don't need to setup N. * src/call-rsa.c (rsa_sign, rsa_decrypt): Don't need to setup N.

6
boards/FST_01/board.h
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@@ -97,12 +97,16 @@
* PA0 - input with pull-up (TIM2_CH1) * PA0 - input with pull-up (TIM2_CH1)
* PA1 - input with pull-down (TIM2_CH2) * PA1 - input with pull-down (TIM2_CH2)
* PA2 - input with pull-up (TIM2_CH3) * PA2 - input with pull-up (TIM2_CH3)
* PA4 - Push pull output (SPI1_NSS)
* PA5 - Alternate Push pull output (SPI1_SCK)
* PA6 - Alternate Push pull output (SPI1_MISO)
* PA7 - Alternate Push pull output (SPI1_MOSI)
* PA11 - input with pull-up (USBDM) * PA11 - input with pull-up (USBDM)
* PA12 - input with pull-up (USBDP) * PA12 - input with pull-up (USBDP)
* Everything input with pull-up except: * Everything input with pull-up except:
* PA10 - Push pull output (USB 1:ON 0:OFF) * PA10 - Push pull output (USB 1:ON 0:OFF)
*/ */
#define VAL_GPIOACRL 0x88888888 /* PA7...PA0 */ #define VAL_GPIOACRL 0xBBB38888 /* PA7...PA0 */
#define VAL_GPIOACRH 0x88888388 /* PA15...PA8 */ #define VAL_GPIOACRH 0x88888388 /* PA15...PA8 */
#define VAL_GPIOAODR 0xFFFFFFFD #define VAL_GPIOAODR 0xFFFFFFFD

9
tool/stlinkv2.py
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@@ -217,19 +217,22 @@ class stlinkv2(object):
# For FST-01-00 and FST-01: LED on, USB off # For FST-01-00 and FST-01: LED on, USB off
def setup_gpio(self): def setup_gpio(self):
apb2enr = self.read_memory_u32(0x40021018) apb2enr = self.read_memory_u32(0x40021018)
apb2enr = apb2enr | 4 | 8 # Enable port A and B apb2enr = apb2enr | 4 | 8 | 0x1000 # Enable port A, port B, and SPI1
self.write_memory_u32(0x40021018, apb2enr) # RCC->APB2ENR self.write_memory_u32(0x40021018, apb2enr) # RCC->APB2ENR
self.write_memory_u32(0x4002100c, 4|8) # RCC->APB2RSTR self.write_memory_u32(0x4002100c, 4|8|0x1000) # RCC->APB2RSTR
self.write_memory_u32(0x4002100c, 0) self.write_memory_u32(0x4002100c, 0)
self.write_memory_u32(GPIOA+0x0c, 0xfffffbff) # ODR self.write_memory_u32(GPIOA+0x0c, 0xfffffbff) # ODR
self.write_memory_u32(GPIOA+0x04, 0x88888383) # CRH self.write_memory_u32(GPIOA+0x04, 0x88888383) # CRH
self.write_memory_u32(GPIOA+0x00, 0x88888888) # CRL self.write_memory_u32(GPIOA+0x00, 0xBBB38888) # CRL
self.write_memory_u32(GPIOB+0x0c, 0xffffffff) # ODR self.write_memory_u32(GPIOB+0x0c, 0xffffffff) # ODR
self.write_memory_u32(GPIOB+0x04, 0x88888883) # CRH self.write_memory_u32(GPIOB+0x04, 0x88888883) # CRH
self.write_memory_u32(GPIOB+0x00, 0x88888888) # CRL self.write_memory_u32(GPIOB+0x00, 0x88888888) # CRL
# For FST-01-00 and FST-01: LED off, USB off # For FST-01-00 and FST-01: LED off, USB off
def finish_gpio(self): def finish_gpio(self):
apb2enr = self.read_memory_u32(0x40021018)
apb2enr = apb2enr & ~(4 | 8 | 0x1000)
self.write_memory_u32(0x40021018, apb2enr) # RCC->APB2ENR
self.write_memory_u32(GPIOA+0x0c, 0xfffffaff) # ODR self.write_memory_u32(GPIOA+0x0c, 0xfffffaff) # ODR
self.write_memory_u32(GPIOB+0x0c, 0xfffffffe) # ODR self.write_memory_u32(GPIOB+0x0c, 0xfffffffe) # ODR