From 95587b8cae74371378a37366af993a0390d0f861 Mon Sep 17 00:00:00 2001 From: NIIBE Yutaka Date: Sat, 2 Nov 2013 14:28:06 +0900 Subject: [PATCH] update sys --- ChangeLog | 6 + README | 2 +- src/stm32f103.h | 494 +++++++++++++++++++++++++++++++++++++++++++++++- src/sys.c | 41 +++- src/usb_lld.h | 2 - 5 files changed, 533 insertions(+), 12 deletions(-) diff --git a/ChangeLog b/ChangeLog index a7c0f13..b38078c 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2013-11-02 Niibe Yutaka + + * src/sys.c: Update from Chopstx. + * src/usb_lld.h: Remove interrupt definition. + * src/stm32f103.h: Add AFIO, EXTI, and TIMER constants. + 2013-10-31 Niibe Yutaka * src/main.c (main): Call msc_init before USB interrupt thread. diff --git a/README b/README index bb8949f..7d598ff 100644 --- a/README +++ b/README @@ -459,7 +459,7 @@ STM8S Discovery Kit If you are using FTDI-2232D module and the connection is standard, type: - $ openocd -f interface/openocd-usb.cfg -f target/stm32.cfg + $ openocd -f interface/openocd-usb.cfg -f target/stm32f1x.cfg Initially, the flash ROM of the chip is protected. you need to do: diff --git a/src/stm32f103.h b/src/stm32f103.h index a4ecaa1..d611bd0 100644 --- a/src/stm32f103.h +++ b/src/stm32f103.h @@ -1,10 +1,8 @@ #define PERIPH_BASE 0x40000000 +#define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) -#define RCC_APB2RSTR_ADC1RST 0x00000200 -#define RCC_APB2RSTR_ADC2RST 0x00000400 - struct RCC { volatile uint32_t CR; volatile uint32_t CFGR; @@ -26,6 +24,15 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE); #define RCC_APB2ENR_ADC1EN 0x00000200 #define RCC_APB2ENR_ADC2EN 0x00000400 +#define RCC_APB2ENR_TIM1EN 0x00000800 +#define RCC_APB1ENR_TIM2EN 0x00000001 +#define RCC_APB1ENR_TIM3EN 0x00000002 + +#define RCC_APB2RSTR_ADC1RST 0x00000200 +#define RCC_APB2RSTR_ADC2RST 0x00000400 +#define RCC_APB2RSTR_TIM1RST 0x00000800 +#define RCC_APB1RSTR_TIM2RST 0x00000001 +#define RCC_APB1RSTR_TIM3RST 0x00000002 #define CRC_CR_RESET 0x00000001 @@ -202,3 +209,484 @@ struct SCB #define SCS_BASE 0xE000E000 #define SCB_BASE (SCS_BASE + 0x0D00) static struct SCB *const SCB = (struct SCB *const)SCB_BASE; + +/* Timer */ +struct TIM +{ + volatile uint16_t CR1; uint16_t RESERVED0; + volatile uint16_t CR2; uint16_t RESERVED1; + volatile uint16_t SMCR; uint16_t RESERVED2; + volatile uint16_t DIER; uint16_t RESERVED3; + volatile uint16_t SR; uint16_t RESERVED4; + volatile uint16_t EGR; uint16_t RESERVED5; + volatile uint16_t CCMR1; uint16_t RESERVED6; + volatile uint16_t CCMR2; uint16_t RESERVED7; + volatile uint16_t CCER; uint16_t RESERVED8; + volatile uint16_t CNT; uint16_t RESERVED9; + volatile uint16_t PSC; uint16_t RESERVED10; + volatile uint16_t ARR; uint16_t RESERVED11; + volatile uint16_t RCR; uint16_t RESERVED12; + volatile uint16_t CCR1; uint16_t RESERVED13; + volatile uint16_t CCR2; uint16_t RESERVED14; + volatile uint16_t CCR3; uint16_t RESERVED15; + volatile uint16_t CCR4; uint16_t RESERVED16; + volatile uint16_t BDTR; uint16_t RESERVED17; + volatile uint16_t DCR; uint16_t RESERVED18; + volatile uint16_t DMAR; uint16_t RESERVED19; +}; + +#define TIM2_BASE 0x40000000 +#define TIM3_BASE 0x40000400 +static struct TIM *const TIM2 = (struct TIM *const)TIM2_BASE; +static struct TIM *const TIM3 = (struct TIM *const)TIM3_BASE; + +#define TIM_CR1_CEN 0x0001 +#define TIM_CR1_UDIS 0x0002 +#define TIM_CR1_URS 0x0004 +#define TIM_CR1_OPM 0x0008 +#define TIM_CR1_DIR 0x0010 +#define TIM_CR1_CMS 0x0060 +#define TIM_CR1_CMS_0 0x0020 +#define TIM_CR1_CMS_1 0x0040 +#define TIM_CR1_ARPE 0x0080 +#define TIM_CR1_CKD 0x0300 +#define TIM_CR1_CKD_0 0x0100 +#define TIM_CR1_CKD_1 0x0200 + +#define TIM_CR2_CCPC 0x0001 +#define TIM_CR2_CCUS 0x0004 +#define TIM_CR2_CCDS 0x0008 +#define TIM_CR2_MMS 0x0070 +#define TIM_CR2_MMS_0 0x0010 +#define TIM_CR2_MMS_1 0x0020 +#define TIM_CR2_MMS_2 0x0040 +#define TIM_CR2_TI1S 0x0080 +#define TIM_CR2_OIS1 0x0100 +#define TIM_CR2_OIS1N 0x0200 +#define TIM_CR2_OIS2 0x0400 +#define TIM_CR2_OIS2N 0x0800 +#define TIM_CR2_OIS3 0x1000 +#define TIM_CR2_OIS3N 0x2000 +#define TIM_CR2_OIS4 0x4000 + +#define TIM_SMCR_SMS 0x0007 +#define TIM_SMCR_SMS_0 0x0001 +#define TIM_SMCR_SMS_1 0x0002 +#define TIM_SMCR_SMS_2 0x0004 +#define TIM_SMCR_TS 0x0070 +#define TIM_SMCR_TS_0 0x0010 +#define TIM_SMCR_TS_1 0x0020 +#define TIM_SMCR_TS_2 0x0040 +#define TIM_SMCR_MSM 0x0080 + +#define TIM_SMCR_ETF 0x0F00 +#define TIM_SMCR_ETF_0 0x0100 +#define TIM_SMCR_ETF_1 0x0200 +#define TIM_SMCR_ETF_2 0x0400 +#define TIM_SMCR_ETF_3 0x0800 + +#define TIM_SMCR_ETPS 0x3000 +#define TIM_SMCR_ETPS_0 0x1000 +#define TIM_SMCR_ETPS_1 0x2000 + +#define TIM_SMCR_ECE 0x4000 +#define TIM_SMCR_ETP 0x8000 + +#define TIM_DIER_UIE 0x0001 +#define TIM_DIER_CC1IE 0x0002 +#define TIM_DIER_CC2IE 0x0004 +#define TIM_DIER_CC3IE 0x0008 +#define TIM_DIER_CC4IE 0x0010 +#define TIM_DIER_COMIE 0x0020 +#define TIM_DIER_TIE 0x0040 +#define TIM_DIER_BIE 0x0080 +#define TIM_DIER_UDE 0x0100 +#define TIM_DIER_CC1DE 0x0200 +#define TIM_DIER_CC2DE 0x0400 +#define TIM_DIER_CC3DE 0x0800 +#define TIM_DIER_CC4DE 0x1000 +#define TIM_DIER_COMDE 0x2000 +#define TIM_DIER_TDE 0x4000 + +#define TIM_SR_UIF 0x0001 +#define TIM_SR_CC1IF 0x0002 +#define TIM_SR_CC2IF 0x0004 +#define TIM_SR_CC3IF 0x0008 +#define TIM_SR_CC4IF 0x0010 +#define TIM_SR_COMIF 0x0020 +#define TIM_SR_TIF 0x0040 +#define TIM_SR_BIF 0x0080 +#define TIM_SR_CC1OF 0x0200 +#define TIM_SR_CC2OF 0x0400 +#define TIM_SR_CC3OF 0x0800 +#define TIM_SR_CC4OF 0x1000 + +#define TIM_EGR_UG 0x01 +#define TIM_EGR_CC1G 0x02 +#define TIM_EGR_CC2G 0x04 +#define TIM_EGR_CC3G 0x08 +#define TIM_EGR_CC4G 0x10 +#define TIM_EGR_COMG 0x20 +#define TIM_EGR_TG 0x40 +#define TIM_EGR_BG 0x80 + +#define TIM_CCMR1_CC1S 0x0003 +#define TIM_CCMR1_CC1S_0 0x0001 +#define TIM_CCMR1_CC1S_1 0x0002 + +#define TIM_CCMR1_OC1FE 0x0004 +#define TIM_CCMR1_OC1PE 0x0008 + +#define TIM_CCMR1_OC1M 0x0070 +#define TIM_CCMR1_OC1M_0 0x0010 +#define TIM_CCMR1_OC1M_1 0x0020 +#define TIM_CCMR1_OC1M_2 0x0040 + +#define TIM_CCMR1_OC1CE 0x0080 + +#define TIM_CCMR1_CC2S 0x0300 +#define TIM_CCMR1_CC2S_0 0x0100 +#define TIM_CCMR1_CC2S_1 0x0200 + +#define TIM_CCMR1_OC2FE 0x0400 +#define TIM_CCMR1_OC2PE 0x0800 + +#define TIM_CCMR1_OC2M 0x7000 +#define TIM_CCMR1_OC2M_0 0x1000 +#define TIM_CCMR1_OC2M_1 0x2000 +#define TIM_CCMR1_OC2M_2 0x4000 + +#define TIM_CCMR1_OC2CE 0x8000 + + +#define TIM_CCMR1_IC1PSC 0x000C +#define TIM_CCMR1_IC1PSC_0 0x0004 +#define TIM_CCMR1_IC1PSC_1 0x0008 + +#define TIM_CCMR1_IC1F 0x00F0 +#define TIM_CCMR1_IC1F_0 0x0010 +#define TIM_CCMR1_IC1F_1 0x0020 +#define TIM_CCMR1_IC1F_2 0x0040 +#define TIM_CCMR1_IC1F_3 0x0080 + +#define TIM_CCMR1_IC2PSC 0x0C00 +#define TIM_CCMR1_IC2PSC_0 0x0400 +#define TIM_CCMR1_IC2PSC_1 0x0800 + +#define TIM_CCMR1_IC2F 0xF000 +#define TIM_CCMR1_IC2F_0 0x1000 +#define TIM_CCMR1_IC2F_1 0x2000 +#define TIM_CCMR1_IC2F_2 0x4000 +#define TIM_CCMR1_IC2F_3 0x8000 + +#define TIM_CCMR2_CC3S 0x0003 +#define TIM_CCMR2_CC3S_0 0x0001 +#define TIM_CCMR2_CC3S_1 0x0002 + +#define TIM_CCMR2_OC3FE 0x0004 +#define TIM_CCMR2_OC3PE 0x0008 + +#define TIM_CCMR2_OC3M 0x0070 +#define TIM_CCMR2_OC3M_0 0x0010 +#define TIM_CCMR2_OC3M_1 0x0020 +#define TIM_CCMR2_OC3M_2 0x0040 + +#define TIM_CCMR2_OC3CE 0x0080 + +#define TIM_CCMR2_CC4S 0x0300 +#define TIM_CCMR2_CC4S_0 0x0100 +#define TIM_CCMR2_CC4S_1 0x0200 + +#define TIM_CCMR2_OC4FE 0x0400 +#define TIM_CCMR2_OC4PE 0x0800 + +#define TIM_CCMR2_OC4M 0x7000 +#define TIM_CCMR2_OC4M_0 0x1000 +#define TIM_CCMR2_OC4M_1 0x2000 +#define TIM_CCMR2_OC4M_2 0x4000 + +#define TIM_CCMR2_OC4CE 0x8000 + + +#define TIM_CCMR2_IC3PSC 0x000C +#define TIM_CCMR2_IC3PSC_0 0x0004 +#define TIM_CCMR2_IC3PSC_1 0x0008 + +#define TIM_CCMR2_IC3F 0x00F0 +#define TIM_CCMR2_IC3F_0 0x0010 +#define TIM_CCMR2_IC3F_1 0x0020 +#define TIM_CCMR2_IC3F_2 0x0040 +#define TIM_CCMR2_IC3F_3 0x0080 + +#define TIM_CCMR2_IC4PSC 0x0C00 +#define TIM_CCMR2_IC4PSC_0 0x0400 +#define TIM_CCMR2_IC4PSC_1 0x0800 + +#define TIM_CCMR2_IC4F 0xF000 +#define TIM_CCMR2_IC4F_0 0x1000 +#define TIM_CCMR2_IC4F_1 0x2000 +#define TIM_CCMR2_IC4F_2 0x4000 +#define TIM_CCMR2_IC4F_3 0x8000 + +#define TIM_CCER_CC1E 0x0001 +#define TIM_CCER_CC1P 0x0002 +#define TIM_CCER_CC1NE 0x0004 +#define TIM_CCER_CC1NP 0x0008 +#define TIM_CCER_CC2E 0x0010 +#define TIM_CCER_CC2P 0x0020 +#define TIM_CCER_CC2NE 0x0040 +#define TIM_CCER_CC2NP 0x0080 +#define TIM_CCER_CC3E 0x0100 +#define TIM_CCER_CC3P 0x0200 +#define TIM_CCER_CC3NE 0x0400 +#define TIM_CCER_CC3NP 0x0800 +#define TIM_CCER_CC4E 0x1000 +#define TIM_CCER_CC4P 0x2000 + +#define TIM_CNT_CNT 0xFFFF + +#define TIM_PSC_PSC 0xFFFF + +#define TIM_ARR_ARR 0xFFFF + +#define TIM_RCR_REP 0xFF + +#define TIM_CCR1_CCR1 0xFFFF +#define TIM_CCR2_CCR2 0xFFFF +#define TIM_CCR3_CCR3 0xFFFF +#define TIM_CCR4_CCR4 0xFFFF + +#define TIM_BDTR_DTG 0x00FF +#define TIM_BDTR_DTG_0 0x0001 +#define TIM_BDTR_DTG_1 0x0002 +#define TIM_BDTR_DTG_2 0x0004 +#define TIM_BDTR_DTG_3 0x0008 +#define TIM_BDTR_DTG_4 0x0010 +#define TIM_BDTR_DTG_5 0x0020 +#define TIM_BDTR_DTG_6 0x0040 +#define TIM_BDTR_DTG_7 0x0080 + +#define TIM_BDTR_LOCK 0x0300 +#define TIM_BDTR_LOCK_0 0x0100 +#define TIM_BDTR_LOCK_1 0x0200 + +#define TIM_BDTR_OSSI 0x0400 +#define TIM_BDTR_OSSR 0x0800 +#define TIM_BDTR_BKE 0x1000 +#define TIM_BDTR_BKP 0x2000 +#define TIM_BDTR_AOE 0x4000 +#define TIM_BDTR_MOE 0x8000 + +#define TIM_DCR_DBA 0x001F +#define TIM_DCR_DBA_0 0x0001 +#define TIM_DCR_DBA_1 0x0002 +#define TIM_DCR_DBA_2 0x0004 +#define TIM_DCR_DBA_3 0x0008 +#define TIM_DCR_DBA_4 0x0010 + +#define TIM_DCR_DBL 0x1F00 +#define TIM_DCR_DBL_0 0x0100 +#define TIM_DCR_DBL_1 0x0200 +#define TIM_DCR_DBL_2 0x0400 +#define TIM_DCR_DBL_3 0x0800 +#define TIM_DCR_DBL_4 0x1000 + +#define TIM_DMAR_DMAB 0xFFFF + +struct EXTI +{ + volatile uint32_t IMR; + volatile uint32_t EMR; + volatile uint32_t RTSR; + volatile uint32_t FTSR; + volatile uint32_t SWIER; + volatile uint32_t PR; +}; + +#define EXTI_BASE 0x40010400 +static struct EXTI *const EXTI = (struct EXTI *const)EXTI_BASE; + +#define EXTI_IMR_MR0 0x00000001 +#define EXTI_IMR_MR1 0x00000002 +#define EXTI_IMR_MR2 0x00000004 +#define EXTI_IMR_MR3 0x00000008 +#define EXTI_IMR_MR4 0x00000010 +#define EXTI_IMR_MR5 0x00000020 +#define EXTI_IMR_MR6 0x00000040 +#define EXTI_IMR_MR7 0x00000080 +#define EXTI_IMR_MR8 0x00000100 +#define EXTI_IMR_MR9 0x00000200 +#define EXTI_IMR_MR10 0x00000400 +#define EXTI_IMR_MR11 0x00000800 +#define EXTI_IMR_MR12 0x00001000 +#define EXTI_IMR_MR13 0x00002000 +#define EXTI_IMR_MR14 0x00004000 +#define EXTI_IMR_MR15 0x00008000 +#define EXTI_IMR_MR16 0x00010000 +#define EXTI_IMR_MR17 0x00020000 +#define EXTI_IMR_MR18 0x00040000 +#define EXTI_IMR_MR19 0x00080000 + +#define EXTI_EMR_MR0 0x00000001 +#define EXTI_EMR_MR1 0x00000002 +#define EXTI_EMR_MR2 0x00000004 +#define EXTI_EMR_MR3 0x00000008 +#define EXTI_EMR_MR4 0x00000010 +#define EXTI_EMR_MR5 0x00000020 +#define EXTI_EMR_MR6 0x00000040 +#define EXTI_EMR_MR7 0x00000080 +#define EXTI_EMR_MR8 0x00000100 +#define EXTI_EMR_MR9 0x00000200 +#define EXTI_EMR_MR10 0x00000400 +#define EXTI_EMR_MR11 0x00000800 +#define EXTI_EMR_MR12 0x00001000 +#define EXTI_EMR_MR13 0x00002000 +#define EXTI_EMR_MR14 0x00004000 +#define EXTI_EMR_MR15 0x00008000 +#define EXTI_EMR_MR16 0x00010000 +#define EXTI_EMR_MR17 0x00020000 +#define EXTI_EMR_MR18 0x00040000 +#define EXTI_EMR_MR19 0x00080000 + +#define EXTI_RTSR_TR0 0x00000001 +#define EXTI_RTSR_TR1 0x00000002 +#define EXTI_RTSR_TR2 0x00000004 +#define EXTI_RTSR_TR3 0x00000008 +#define EXTI_RTSR_TR4 0x00000010 +#define EXTI_RTSR_TR5 0x00000020 +#define EXTI_RTSR_TR6 0x00000040 +#define EXTI_RTSR_TR7 0x00000080 +#define EXTI_RTSR_TR8 0x00000100 +#define EXTI_RTSR_TR9 0x00000200 +#define EXTI_RTSR_TR10 0x00000400 +#define EXTI_RTSR_TR11 0x00000800 +#define EXTI_RTSR_TR12 0x00001000 +#define EXTI_RTSR_TR13 0x00002000 +#define EXTI_RTSR_TR14 0x00004000 +#define EXTI_RTSR_TR15 0x00008000 +#define EXTI_RTSR_TR16 0x00010000 +#define EXTI_RTSR_TR17 0x00020000 +#define EXTI_RTSR_TR18 0x00040000 +#define EXTI_RTSR_TR19 0x00080000 + +#define EXTI_FTSR_TR0 0x00000001 +#define EXTI_FTSR_TR1 0x00000002 +#define EXTI_FTSR_TR2 0x00000004 +#define EXTI_FTSR_TR3 0x00000008 +#define EXTI_FTSR_TR4 0x00000010 +#define EXTI_FTSR_TR5 0x00000020 +#define EXTI_FTSR_TR6 0x00000040 +#define EXTI_FTSR_TR7 0x00000080 +#define EXTI_FTSR_TR8 0x00000100 +#define EXTI_FTSR_TR9 0x00000200 +#define EXTI_FTSR_TR10 0x00000400 +#define EXTI_FTSR_TR11 0x00000800 +#define EXTI_FTSR_TR12 0x00001000 +#define EXTI_FTSR_TR13 0x00002000 +#define EXTI_FTSR_TR14 0x00004000 +#define EXTI_FTSR_TR15 0x00008000 +#define EXTI_FTSR_TR16 0x00010000 +#define EXTI_FTSR_TR17 0x00020000 +#define EXTI_FTSR_TR18 0x00040000 +#define EXTI_FTSR_TR19 0x00080000 + +#define EXTI_SWIER_SWIER0 0x00000001 +#define EXTI_SWIER_SWIER1 0x00000002 +#define EXTI_SWIER_SWIER2 0x00000004 +#define EXTI_SWIER_SWIER3 0x00000008 +#define EXTI_SWIER_SWIER4 0x00000010 +#define EXTI_SWIER_SWIER5 0x00000020 +#define EXTI_SWIER_SWIER6 0x00000040 +#define EXTI_SWIER_SWIER7 0x00000080 +#define EXTI_SWIER_SWIER8 0x00000100 +#define EXTI_SWIER_SWIER9 0x00000200 +#define EXTI_SWIER_SWIER10 0x00000400 +#define EXTI_SWIER_SWIER11 0x00000800 +#define EXTI_SWIER_SWIER12 0x00001000 +#define EXTI_SWIER_SWIER13 0x00002000 +#define EXTI_SWIER_SWIER14 0x00004000 +#define EXTI_SWIER_SWIER15 0x00008000 +#define EXTI_SWIER_SWIER16 0x00010000 +#define EXTI_SWIER_SWIER17 0x00020000 +#define EXTI_SWIER_SWIER18 0x00040000 +#define EXTI_SWIER_SWIER19 0x00080000 + +#define EXTI_PR_PR0 0x00000001 +#define EXTI_PR_PR1 0x00000002 +#define EXTI_PR_PR2 0x00000004 +#define EXTI_PR_PR3 0x00000008 +#define EXTI_PR_PR4 0x00000010 +#define EXTI_PR_PR5 0x00000020 +#define EXTI_PR_PR6 0x00000040 +#define EXTI_PR_PR7 0x00000080 +#define EXTI_PR_PR8 0x00000100 +#define EXTI_PR_PR9 0x00000200 +#define EXTI_PR_PR10 0x00000400 +#define EXTI_PR_PR11 0x00000800 +#define EXTI_PR_PR12 0x00001000 +#define EXTI_PR_PR13 0x00002000 +#define EXTI_PR_PR14 0x00004000 +#define EXTI_PR_PR15 0x00008000 +#define EXTI_PR_PR16 0x00010000 +#define EXTI_PR_PR17 0x00020000 +#define EXTI_PR_PR18 0x00040000 +#define EXTI_PR_PR19 0x00080000 + +#define EXTI2_IRQ 8 +#define EXTI9_5_IRQ 23 +#define TIM2_IRQ 28 +#define TIM3_IRQ 29 + +struct AFIO +{ + volatile uint32_t EVCR; + volatile uint32_t MAPR; + volatile uint32_t EXTICR[4]; + uint32_t RESERVED0; + volatile uint32_t MAPR2; +}; + +#define AFIO_BASE 0x40010000 +static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE; + +#define AFIO_EXTICR1_EXTI0_PA 0x0000 +#define AFIO_EXTICR1_EXTI0_PB 0x0001 +#define AFIO_EXTICR1_EXTI0_PC 0x0002 +#define AFIO_EXTICR1_EXTI0_PD 0x0003 + +#define AFIO_EXTICR1_EXTI1_PA 0x0000 +#define AFIO_EXTICR1_EXTI1_PB 0x0010 +#define AFIO_EXTICR1_EXTI1_PC 0x0020 +#define AFIO_EXTICR1_EXTI1_PD 0x0030 + +#define AFIO_EXTICR1_EXTI2_PA 0x0000 +#define AFIO_EXTICR1_EXTI2_PB 0x0100 +#define AFIO_EXTICR1_EXTI2_PC 0x0200 +#define AFIO_EXTICR1_EXTI2_PD 0x0300 + +#define AFIO_EXTICR1_EXTI3_PA 0x0000 +#define AFIO_EXTICR1_EXTI3_PB 0x1000 +#define AFIO_EXTICR1_EXTI3_PC 0x2000 +#define AFIO_EXTICR1_EXTI3_PD 0x3000 + +#define AFIO_EXTICR2_EXTI4_PA 0x0000 +#define AFIO_EXTICR2_EXTI4_PB 0x0001 +#define AFIO_EXTICR2_EXTI4_PC 0x0002 +#define AFIO_EXTICR2_EXTI4_PD 0x0003 + +#define AFIO_EXTICR2_EXTI5_PA 0x0000 +#define AFIO_EXTICR2_EXTI5_PB 0x0010 +#define AFIO_EXTICR2_EXTI5_PC 0x0020 +#define AFIO_EXTICR2_EXTI5_PD 0x0030 + +#define AFIO_EXTICR2_EXTI6_PA 0x0000 +#define AFIO_EXTICR2_EXTI6_PB 0x0100 +#define AFIO_EXTICR2_EXTI6_PC 0x0200 +#define AFIO_EXTICR2_EXTI6_PD 0x0300 + +#define AFIO_EXTICR2_EXTI7_PA 0x0000 +#define AFIO_EXTICR2_EXTI7_PB 0x1000 +#define AFIO_EXTICR2_EXTI7_PC 0x2000 +#define AFIO_EXTICR2_EXTI7_PD 0x3000 + +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800 diff --git a/src/sys.c b/src/sys.c index 36184b7..75fe7d2 100644 --- a/src/sys.c +++ b/src/sys.c @@ -181,15 +181,33 @@ clock_init (void) ; } -#define RCC_APB2ENR_IOPAEN 0x00000004 +#define RCC_APB2RSTR_AFIORST 0x00000001 #define RCC_APB2RSTR_IOPARST 0x00000004 -#define RCC_APB2ENR_IOPBEN 0x00000008 #define RCC_APB2RSTR_IOPBRST 0x00000008 -#define RCC_APB2ENR_IOPCEN 0x00000010 #define RCC_APB2RSTR_IOPCRST 0x00000010 -#define RCC_APB2ENR_IOPDEN 0x00000020 #define RCC_APB2RSTR_IOPDRST 0x00000020 +#define RCC_APB2ENR_AFIOEN 0x00000001 +#define RCC_APB2ENR_IOPAEN 0x00000004 +#define RCC_APB2ENR_IOPBEN 0x00000008 +#define RCC_APB2ENR_IOPCEN 0x00000010 +#define RCC_APB2ENR_IOPDEN 0x00000020 + + +struct AFIO +{ + volatile uint32_t EVCR; + volatile uint32_t MAPR; + volatile uint32_t EXTICR[4]; + uint32_t RESERVED0; + volatile uint32_t MAPR2; +}; + +#define AFIO_BASE 0x40010000 +static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE; + +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800 + struct GPIO { volatile uint32_t CRL; @@ -214,6 +232,9 @@ struct GPIO { static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE); static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE); +#ifdef GPIO_OTHER_BASE +static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE); +#endif static void gpio_init (void) @@ -223,6 +244,10 @@ gpio_init (void) RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST; RCC->APB2RSTR = 0; +#ifdef AFIO_MAPR_SOMETHING + AFIO->MAPR |= AFIO_MAPR_SOMETHING; +#endif + GPIO_USB->ODR = VAL_GPIO_ODR; GPIO_USB->CRH = VAL_GPIO_CRH; GPIO_USB->CRL = VAL_GPIO_CRL; @@ -232,6 +257,12 @@ gpio_init (void) GPIO_LED->CRH = VAL_GPIO_LED_CRH; GPIO_LED->CRL = VAL_GPIO_LED_CRL; #endif + +#ifdef GPIO_OTHER_BASE + GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR; + GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH; + GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL; +#endif } static void @@ -276,8 +307,6 @@ static void wait (int count) asm volatile ("" : : "r" (i) : "memory"); } -#define USB_IRQ 20 -#define USB_IRQ_PRIORITY ((11) << 4) static void usb_lld_sys_shutdown (void) diff --git a/src/usb_lld.h b/src/usb_lld.h index b98d267..3175312 100644 --- a/src/usb_lld.h +++ b/src/usb_lld.h @@ -91,8 +91,6 @@ enum DEVICE_STATE extern uint32_t bDeviceState; extern const uint8_t usb_initial_feature; -#define STM32_USB_IRQ_PRIORITY 11 - extern void usb_lld_init (uint8_t feature); extern void usb_lld_to_pmabuf (const void *src, uint16_t addr, size_t n);