more update to newer chibios

This commit is contained in:
NIIBE Yutaka
2013-02-18 16:08:47 +09:00
parent daeac800d8
commit 605d8ef6c1
17 changed files with 137 additions and 48 deletions

View File

@@ -38,6 +38,14 @@
#define GPIO_LED GPIOD_LED1
#define IOPORT_LED GPIOD
/* NeuG settings for ADC2. */
#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \
| ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5)
#define NEUG_ADC_SETTING2_SMPR2 0
#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) \
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11)
#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
/*
* Board identifier.
*/
@@ -148,6 +156,8 @@
/*
* Port C setup.
* PC0 - Digital input with PullUp. AN10 for NeuG
* PC1 - Digital input with PullUp. AN11 for NeuG
* Everything input with pull-up except:
*/
#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */
@@ -157,7 +167,7 @@
/*
* Port D setup.
* Everything input with pull-up except:
* PD3 - Push pull output (USB ENABLE 1:DISABLE 0:ENABLE) 2MHz
* PD3 - Push pull output (USB_DISC 1:USB-DISABLE 0:USB-ENABLE) 2MHz
* PD4 - Open Drain output 2MHz (LED1).
*/
#define VAL_GPIODCRL 0x88862888 /* PD7...PD0 */
@@ -187,4 +197,15 @@
#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */
#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */
#define VAL_GPIOGODR 0xFFFFFFFF
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */