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fix regnual/sys.c

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NIIBE Yutaka
2012-05-28 11:03:26 +09:00
parent 95fd3711d8
commit 4e8af02ac0
1 changed files with 11 additions and 18 deletions
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29
regnual/sys.c
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@@ -15,28 +15,21 @@ void entry (void)
{ {
asm volatile ("ldr r0, =__ram_end__\n\t" asm volatile ("ldr r0, =__ram_end__\n\t"
"ldr r1, =__main_stack_size__\n\t" "ldr r1, =__main_stack_size__\n\t"
"subs r0, r0, r1\n\t" "sub r0, r0, r1\n\t"
"msr PSP, r0\n\t" /* Process (main routine) stack */ "mov sp, r0\n\t"
"movs r0, #0\n\t" "mov r0, #0\n\t"
"ldr r1, =_bss_start\n\t" "ldr r1, =_bss_start\n\t"
"ldr r2, =_bss_start\n" "ldr r2, =_bss_end\n"
"0:\n\t" "0:\n\t"
"cmp r1, r2\n\t" "str r0, [r1], #4\n\t"
"bge 1f\n\t" "cmp r2, r1\n\t"
"str r0, [r1]\n\t" "bhi 0b\n\t"
"adds r1, r1, #4\n\t" "cpsie i\n\t" /* Enable interrupts */
"b 0b\n" "mov r0, #0\n\t"
"1:\n\t"
"movs r0, #2\n\t" /* Switch to PSP */
"msr CONTROL, r0\n\t"
"isb\n\t"
"movs r0, #0\n\t"
"msr BASEPRI, r0\n\t" /* Enable interrupts */
"cpsie i\n\t"
"mov r1, r0\n\t" "mov r1, r0\n\t"
"bl main\n" "bl main\n"
"2:\n\t" "1:\n\t"
"b 2b\n" "b 1b\n"
: /* no output */ : /* no input */ : "memory"); : /* no output */ : /* no input */ : "memory");
} }