update regnual
This commit is contained in:
NIIBE Yutaka
@@ -25,7 +25,7 @@
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* ReGNUal
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*/
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#include "ch.h"
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#include "types.h"
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#include "usb_lld.h"
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extern void set_led (int);
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@@ -100,13 +100,6 @@ const struct Descriptor String_Descriptors[] = {
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#define NUM_STRING_DESC (sizeof (String_Descriptors)/sizeof (struct Descriptor))
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static void
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regnual_device_init (void)
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{
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usb_lld_set_configuration (0);
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USB_Cable_Config (1);
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}
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static void
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regnual_device_reset (void)
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{
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@@ -252,7 +245,6 @@ static int regnual_interface (uint8_t cmd, uint16_t interface, uint16_t alt)
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}
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const struct usb_device_method Device_Method = {
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regnual_device_init,
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regnual_device_reset,
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regnual_ctrl_write_finish,
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regnual_setup,
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@@ -261,6 +253,16 @@ const struct usb_device_method Device_Method = {
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regnual_interface,
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};
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static void wait (int count)
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{
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int i;
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for (i = 0; i < count; i++)
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asm volatile ("" : : "r" (i) : "memory");
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}
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#define WAIT 2400000
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int
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main (int argc, char *argv[])
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{
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@@ -273,8 +275,8 @@ main (int argc, char *argv[])
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while (1)
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{
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set_led (1);
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chThdSleep (MS2ST (200));
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wait (WAIT);
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set_led (0);
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chThdSleep (MS2ST (200));
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wait (WAIT);
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}
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}
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16
regnual/sys-stbee.h
Normal file
16
regnual/sys-stbee.h
Normal file
@@ -0,0 +1,16 @@
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/*
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* system settings.
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*/
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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#define STM32_PLLMUL_VALUE 6
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#define STM32_HSECLK 12000000
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#define GPIO_USB_CLEAR_TO_ENABLE 3
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#define GPIO_LED_CLEAR_TO_EMIT 4
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#define VAL_GPIO_ODR 0xFFFFFFFF
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#define VAL_GPIO_CRH 0x88888888 /* PD15...PD8 */
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#define VAL_GPIO_CRL 0x88862888 /* PD7...PD0 */
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#define GPIO_USB_BASE GPIOD_BASE
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#define GPIO_LED_BASE GPIOD_BASE
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310
regnual/sys.c
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310
regnual/sys.c
Normal file
@@ -0,0 +1,310 @@
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#include "types.h"
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#include "sys.h"
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#define STM32_SW_PLL (2 << 0)
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#define STM32_PLLSRC_HSE (1 << 16)
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#define STM32_PLLXTPRE_DIV1 (0 << 17)
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#define STM32_PLLXTPRE_DIV2 (1 << 17)
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#define STM32_HPRE_DIV1 (0 << 4)
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#define STM32_PPRE1_DIV2 (4 << 8)
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#define STM32_PPRE2_DIV2 (4 << 11)
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#define STM32_ADCPRE_DIV4 (1 << 14)
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#define STM32_MCO_NOCLOCK (0 << 24)
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCO STM32_MCO_NOCLOCK
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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#define STM32_SYSCLK STM32_PLLCLKOUT
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#define STM32_HCLK (STM32_SYSCLK / 1)
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#define STM32_FLASHBITS 0x00000012
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struct NVIC {
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uint32_t ISER[8];
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uint32_t unused1[24];
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uint32_t ICER[8];
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uint32_t unused2[24];
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uint32_t ISPR[8];
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uint32_t unused3[24];
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uint32_t ICPR[8];
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uint32_t unused4[24];
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uint32_t IABR[8];
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uint32_t unused5[56];
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uint32_t IPR[60];
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};
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#define NVICBase ((struct NVIC *)0xE000E100)
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#define NVIC_ISER(n) (NVICBase->ISER[n])
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#define NVIC_ICPR(n) (NVICBase->ICPR[n])
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#define NVIC_IPR(n) (NVICBase->IPR[n])
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static void NVICEnableVector (uint32_t n, uint32_t prio)
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{
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unsigned int sh = (n & 3) << 3;
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NVIC_IPR (n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
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NVIC_ICPR (n >> 5) = 1 << (n & 0x1F);
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NVIC_ISER (n >> 5) = 1 << (n & 0x1F);
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}
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#define PERIPH_BASE 0x40000000
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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struct RCC {
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__IO uint32_t CR;
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__IO uint32_t CFGR;
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__IO uint32_t CIR;
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__IO uint32_t APB2RSTR;
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__IO uint32_t APB1RSTR;
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__IO uint32_t AHBENR;
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__IO uint32_t APB2ENR;
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__IO uint32_t APB1ENR;
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__IO uint32_t BDCR;
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__IO uint32_t CSR;
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};
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#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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#define RCC ((struct RCC *)RCC_BASE)
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#define RCC_APB1ENR_USBEN 0x00800000
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#define RCC_APB1RSTR_USBRST 0x00800000
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#define RCC_CR_HSION 0x00000001
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#define RCC_CR_HSIRDY 0x00000002
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#define RCC_CR_HSITRIM 0x000000F8
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#define RCC_CR_HSEON 0x00010000
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#define RCC_CR_HSERDY 0x00020000
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#define RCC_CR_PLLON 0x01000000
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#define RCC_CR_PLLRDY 0x02000000
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#define RCC_CFGR_SWS 0x0000000C
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#define RCC_CFGR_SWS_HSI 0x00000000
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struct FLASH {
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__IO uint32_t ACR;
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__IO uint32_t KEYR;
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__IO uint32_t OPTKEYR;
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__IO uint32_t SR;
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__IO uint32_t CR;
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__IO uint32_t AR;
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__IO uint32_t RESERVED;
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__IO uint32_t OBR;
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__IO uint32_t WRPR;
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};
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#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
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#define FLASH ((struct FLASH *) FLASH_R_BASE)
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static __attribute__ ((used))
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void clock_init (void)
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{
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/* HSI setup */
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY))
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;
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
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RCC->CFGR = 0;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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;
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/* HSE setup */
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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;
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/* PLL setup */
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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/* Clock settings */
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RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
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STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* Flash setup */
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FLASH->ACR = STM32_FLASHBITS;
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/* Switching on the configured clock source. */
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RCC->CFGR |= STM32_SW;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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}
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#define RCC_APB2ENR_IOPAEN 0x00000004
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#define RCC_APB2RSTR_IOPARST 0x00000004
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#define RCC_APB2ENR_IOPDEN 0x00000020
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#define RCC_APB2RSTR_IOPDRST 0x00000020
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#define VAL_GPIOAODR 0xFFFFFFFF
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#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */
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#define VAL_GPIOACRL 0x88888884 /* PA7...PA0 */
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struct GPIO {
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__IO uint32_t CRL;
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__IO uint32_t CRH;
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__IO uint32_t IDR;
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__IO uint32_t ODR;
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__IO uint32_t BSRR;
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__IO uint32_t BRR;
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__IO uint32_t LCKR;
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};
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#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
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#define GPIOA ((struct GPIO *) GPIOA_BASE)
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#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
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#define GPIOB ((struct GPIO *) GPIOB_BASE)
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#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
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#define GPIOC ((struct GPIO *) GPIOC_BASE)
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#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
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#define GPIOD ((struct GPIO *) GPIOD_BASE)
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#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
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#define GPIOE ((struct GPIO *) GPIOE_BASE)
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#define GPIO_USB ((struct GPIO *) GPIO_USB_BASE)
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#define GPIO_LED ((struct GPIO *) GPIO_LED_BASE)
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static __attribute__ ((used))
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void gpio_init (void)
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{
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/* Enable GPIOD clock. */
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RCC->APB2ENR |= RCC_APB2ENR_IOPDEN;
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RCC->APB2RSTR = RCC_APB2RSTR_IOPDRST;
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RCC->APB2RSTR = 0;
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GPIO_USB->ODR = VAL_GPIO_ODR;
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GPIO_USB->CRH = VAL_GPIO_CRH;
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GPIO_USB->CRL = VAL_GPIO_CRL;
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#if GPIO_USB_BASE != GPIO_LED_BASE
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GPIO_LED->ODR = VAL_GPIO_LED_ODR;
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GPIO_LED->CRH = VAL_GPIO_LED_CRH;
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GPIO_LED->CRL = VAL_GPIO_LED_CRL;
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#endif
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}
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static void
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usb_cable_config (int on)
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{
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#if defined(GPIO_USB_CLEAR_TO_ENABLE)
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if (on)
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GPIO_USB->BRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
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else
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GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
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#endif
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}
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void
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set_led (int on)
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{
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#if defined(GPIO_LED_CLEAR_TO_EMIT)
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if (on)
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GPIO_LED->BRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
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else
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GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
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#endif
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}
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#define USB_IRQ 20
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#define USB_IRQ_PRIORITY ((11) << 4)
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void usb_lld_sys_init (void)
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{
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RCC->APB1ENR |= RCC_APB1ENR_USBEN;
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NVICEnableVector (USB_IRQ, USB_IRQ_PRIORITY);
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RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
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RCC->APB1RSTR = 0;
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usb_cable_config (1);
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}
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void usb_lld_sys_shutdown (void)
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{
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RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
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}
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static void fatal (void)
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{
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for (;;);
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}
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static void none (void)
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{
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}
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static __attribute__ ((naked))
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void reset (void)
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{
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asm volatile ("cpsid i\n\t" /* Mask all interrupts */
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"ldr r0, =__ram_end__\n\t"
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"msr MSP, r0\n\t" /* Main (interrupt handler) stack */
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"ldr r1, =__main_stack_size__\n\t"
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"subs r0, r0, r1\n\t"
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"msr PSP, r0\n\t" /* Process (main routine) stack */
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"bl clock_init\n\t"
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"movs r0, #0\n\t"
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"ldr r1, =_bss_start\n\t"
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"ldr r2, =_bss_start\n"
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"0:\n\t"
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"cmp r1, r2\n\t"
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"bge 1f\n\t"
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"str r0, [r1]\n\t"
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"adds r1, r1, #4\n\t"
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"b 0b\n"
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"1:\n\t"
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"movs r0, #2\n\t" /* Switch to PSP */
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"msr CONTROL, r0\n\t"
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"isb\n\t"
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"bl gpio_init\n\t"
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"movs r0, #0\n\t"
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"msr BASEPRI, r0\n\t" /* Enable interrupts */
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"cpsie i\n\t"
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"mov r1, r0\n\t"
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"bl main\n"
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"2:\n\t"
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"b 2b\n"
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: /* no output */ : /* no input */ : "memory");
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}
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typedef void (*handler)(void);
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extern uint8_t __ram_end__;
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extern void usb_interrupt_handler (void);
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handler vector_table[] __attribute__ ((section(".vectors"))) = {
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(handler)&__ram_end__,
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reset,
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fatal, /* nmi */
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fatal, /* hard fault */
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/* 10 */
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fatal, /* mem manage */
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fatal, /* bus fault */
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fatal, /* usage fault */
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none,
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/* 20 */
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none, none, none, none, none, none, none, none,
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/* 40 */
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none, none, none, none, none, none, none, none,
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/* 60 */
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none, none, none, none, none, none, none, none,
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/* 80 */
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none, none, none, none,
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/* 90 */
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usb_interrupt_handler,
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};
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10
regnual/types.h
Normal file
10
regnual/types.h
Normal file
@@ -0,0 +1,10 @@
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typedef unsigned long size_t;
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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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typedef unsigned int uint32_t;
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#define TRUE 1
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#define FALSE 0
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#define __IO volatile
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