171 lines
7.7 KiB
C
171 lines
7.7 KiB
C
/*
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* clk_gpio_init-kl.c - Clock and GPIO initialization for Kinetis L.
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*
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* Copyright (C) 2016 Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* This file is a part of Chopstx, a thread library for embedded.
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*
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* Chopstx is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Chopstx is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* As additional permission under GNU GPL version 3 section 7, you may
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* distribute non-source form of the Program without the copy of the
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* GNU GPL normally required by section 4, provided you inform the
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* receipents of GNU GPL by a written offer.
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*
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*/
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/* System Integration Module. */
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struct SIM {
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volatile uint32_t SOPT1; /* System Options Register 1 */
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volatile uint32_t SOPT1CFG; /* SOPT1 Configuration Register */
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uint32_t reserved0[1023]; /* */
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volatile uint32_t SOPT2; /* System Options Register 2 */
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uint32_t reserved1[1]; /* */
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volatile uint32_t SOPT4; /* System Options Register 4 */
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volatile uint32_t SOPT5; /* System Options Register 5 */
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uint32_t reserved2[1]; /* */
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volatile uint32_t SOPT7; /* System Options Register 7 */
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uint32_t reserved3[2]; /* */
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volatile uint32_t SDID; /* System Device Identification Register */
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uint32_t reserved4[3]; /* */
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volatile uint32_t SCGC4; /* System Clock Gating Control Register 4 */
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volatile uint32_t SCGC5; /* System Clock Gating Control Register 5 */
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volatile uint32_t SCGC6; /* System Clock Gating Control Register 6 */
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volatile uint32_t SCGC7; /* System Clock Gating Control Register 7 */
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volatile uint32_t CLKDIV1; /* System Clock Divider Register 1 */
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uint32_t reserved5[1]; /* */
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volatile uint32_t FCFG1; /* Flash Configuration Register 1 */
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volatile uint32_t FCFG2; /* Flash Configuration Register 2 */
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uint32_t reserved6[1]; /* */
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volatile uint32_t UIDMH; /* Unique Identification Register Mid-High */
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volatile uint32_t UIDML; /* Unique Identification Register Mid Low */
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volatile uint32_t UIDL; /* Unique Identification Register Low */
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uint32_t reserved7[39]; /* */
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volatile uint32_t COPC; /* COP Control Register */
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volatile uint32_t SRVCOP; /* Service COP */
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};
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static struct SIM *const SIM = (struct SIM *const)0x40047000;
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struct MCG {
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volatile uint8_t C1; /* MCG Control Register 1 */
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volatile uint8_t C2; /* MCG Control Register 2 */
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uint8_t reserved0[4]; /* */
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volatile uint8_t S; /* MCG Status Register */
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uint8_t reserved1[1]; /* */
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volatile uint8_t SC; /* MCG Status and Control Register */
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uint8_t reserved2[15]; /* */
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volatile uint8_t MC; /* MCG Miscellaneous Control Register */
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};
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static struct MCG *const MCG = (struct MCG *const)0x40064000;
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struct USB_CLK_RECOVER {
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volatile uint8_t CTRL; /* USB Clock */
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uint8_t rsvd38[3]; /* recovery control */
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volatile uint8_t IRC_EN; /* IRC48M oscillator */
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uint8_t rsvd39[3]; /* enable register */
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volatile uint8_t INT_EN; /* Clock recovery */
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uint8_t rsvd40[3]; /* interrupt enable */
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volatile uint8_t INT_STATUS; /* Clock recovery */
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/* interrupt status */
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};
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static struct USB_CLK_RECOVER *const USB_CLK_RECOVER =
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(struct USB_CLK_RECOVER *const)0x40072140;
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static void __attribute__((used))
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clock_init (void)
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{
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SIM->CLKDIV1 = (SIM->CLKDIV1 & 0xF0070000)
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| (1 << 16) /* OUTDIV4 = 001: Divide-by-2 */
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;
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MCG->MC = 0x80; /* HIRC Enable, LIRC_DIV2=000: Division factor=1 */
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MCG->C1 = 0x00; /* Select HIRC clock, LIRC disabled. */
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/* Make sure HIRC clock is selected. */
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while ((MCG->S & 0x0c) != 0)
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;
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SIM->SOPT2 = 0x00040060; /* USBSRC=IRC48, CLOKOUTSEL=LPO, RTC-clock */
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SIM->SCGC4 = (1 << 18); /* Enable USB FS clock */
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SIM->SCGC5 = (1 << 10); /* Enable Port B clock */
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SIM->COPC = 0; /* COP disabled */
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/* Crystal-less USB setup. */
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USB_CLK_RECOVER->IRC_EN = 0x02;
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USB_CLK_RECOVER->CTRL = 0x80;
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}
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struct PORT {
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volatile uint32_t PCR0; volatile uint32_t PCR1;
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volatile uint32_t PCR2; volatile uint32_t PCR3;
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volatile uint32_t PCR4; volatile uint32_t PCR5;
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volatile uint32_t PCR6; volatile uint32_t PCR7;
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volatile uint32_t PCR8; volatile uint32_t PCR9;
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volatile uint32_t PCR10; volatile uint32_t PCR11;
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volatile uint32_t PCR12; volatile uint32_t PCR13;
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volatile uint32_t PCR14; volatile uint32_t PCR15;
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volatile uint32_t PCR16; volatile uint32_t PCR17;
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volatile uint32_t PCR18; volatile uint32_t PCR19;
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volatile uint32_t PCR20; volatile uint32_t PCR21;
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volatile uint32_t PCR22; volatile uint32_t PCR23;
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volatile uint32_t PCR24; volatile uint32_t PCR25;
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volatile uint32_t PCR26; volatile uint32_t PCR27;
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volatile uint32_t PCR28; volatile uint32_t PCR29;
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volatile uint32_t PCR30; volatile uint32_t PCR31;
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volatile uint32_t GPCLR; volatile uint32_t GPCHR;
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uint32_t reserved[6];
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volatile uint32_t ISFR;
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};
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static struct PORT *const PORTB = (struct PORT *const)0x4004A000;
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static struct PORT *const PORTD = (struct PORT *const)0x4004C000;
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static struct PORT *const PORTE = (struct PORT *const)0x4004D000;
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struct GPIO {
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volatile uint32_t PDOR; /* Port Data Output Register */
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volatile uint32_t PSOR; /* Port Set Output Register */
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volatile uint32_t PCOR; /* Port Clear Output Register */
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volatile uint32_t PTOR; /* Port Toggle Output Register */
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volatile uint32_t PDIR; /* Port Data Input Register */
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volatile uint32_t PDDR; /* Port Data Direction Register */
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};
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static struct GPIO *const GPIOB = (struct GPIO *const)0x400FF040;
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static struct GPIO *const GPIOD = (struct GPIO *const)0x400FF0C0;
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static struct GPIO *const GPIOE = (struct GPIO *const)0x400FF100;
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static void __attribute__((used))
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gpio_init (void)
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{
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PORTB->PCR0 = (1<<8) /* GPIO */
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| (0<<6) /* DriveStrengthEnable=0 */
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| (0<<4) /* PassiveFilterEnable=0 */
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| (1<<2) /* SlewRateEnable = slow */
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| (0<<1) /* pull enable = 0 */
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| (0<<0) /* puddselect= 0 */
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;
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PORTB->PCR1 = (1<<8) /* GPIO */
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| (0<<6) /* DriveStrengthEnable=0 */
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| (0<<4) /* PassiveFilterEnable=0 */
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| (1<<2) /* SlewRateEnable = slow */
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| (0<<1) /* pull enable = 0 */
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| (0<<0) /* puddselect= 0 */
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;
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GPIOB->PDDR = (1 << 1) | (1 << 0); /* PTB0, PTB1 : Output */
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GPIOB->PSOR = (1 << 0); /* PTB0: Set : Light off */
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GPIOB->PCOR = (1 << 1); /* PTB1: Clear: Output 0 */
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}
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