71 lines
2.7 KiB
C
71 lines
2.7 KiB
C
#define FLASH_PAGE_SIZE 1024
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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#define STM32_PLLMUL_VALUE 6
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#define STM32_HSECLK 12000000
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#define GPIO_LED_BASE GPIOB_BASE
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#define GPIO_LED_SET_TO_EMIT 0
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#define GPIO_USB_BASE GPIOA_BASE
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#define GPIO_USB_SET_TO_ENABLE 10
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#undef GPIO_OTHER_BASE
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/* For pin-cir settings of Gnuk */
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#define TIMx TIM2
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#define INTR_REQ_TIM TIM2_IRQ
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#define AFIO_EXTICR_INDEX 0
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#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA
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#define EXTI_PR EXTI_PR_PR2
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#define EXTI_IMR EXTI_IMR_MR2
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#define EXTI_FTSR_TR EXTI_FTSR_TR2
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#define INTR_REQ_EXTI EXTI2_IRQ
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#define ENABLE_RCC_APB1
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#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM2EN
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#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM2RST
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/*
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* Port A setup.
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* PA0 - input with pull-up (TIM2_CH1): AN0 for NeuG
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* PA1 - input with pull-down (TIM2_CH2)
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* PA2 - input with pull-up (TIM2_CH3) connected to CIR module
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* PA3 - input with pull-up: external pin available to user
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* PA4 - Push pull output (SPI1_NSS)
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* PA5 - Alternate Push pull output (SPI1_SCK)
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* PA6 - Alternate Push pull output (SPI1_MISO)
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* PA7 - Alternate Push pull output (SPI1_MOSI)
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* PA10 - Push pull output (USB 1:ON 0:OFF)
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* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
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* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
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* ------------------------ Default
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* PA8 - input with pull-up.
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* PA9 - input with pull-up.
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* PA13 - input with pull-up.
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* PA14 - input with pull-up.
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* PA15 - input with pull-up.
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*/
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#define VAL_GPIO_USB_ODR 0xFFFFE7FD
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#define VAL_GPIO_USB_CRL 0xBBB38888 /* PA7...PA0 */
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#define VAL_GPIO_USB_CRH 0x88811388 /* PA15...PA8 */
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/*
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* Port B setup.
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* PB0 - Push pull output (LED 1:ON 0:OFF)
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* PB1 - input with pull-up: AN9 for NeuG
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* ------------------------ Default
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* PBx - input with pull-up.
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*/
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#define VAL_GPIO_LED_ODR 0xFFFFFFFF
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#define VAL_GPIO_LED_CRL 0x88888883 /* PA7...PA0 */
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#define VAL_GPIO_LED_CRH 0x88888888 /* PA15...PA8 */
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#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
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#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
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/* NeuG settings for ADC2. */
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#define NEUG_ADC_SETTING2_SMPR1 0
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#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5) \
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| ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5)
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#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0) \
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| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9)
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#define NEUG_ADC_SETTING2_NUM_CHANNELS 2
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