228 lines
6.3 KiB
C
228 lines
6.3 KiB
C
/*
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* adc_kl27z.c - ADC driver for KL27Z
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* In this ADC driver, there are NeuG specific parts.
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* You need to modify to use this as generic ADC driver.
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*
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* Copyright (C) 2016 Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* This file is a part of Chopstx, a thread library for embedded.
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*
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* Chopstx is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Chopstx is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* As additional permission under GNU GPL version 3 section 7, you may
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* distribute non-source form of the Program without the copy of the
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* GNU GPL normally required by section 4, provided you inform the
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* receipents of GNU GPL by a written offer.
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*
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <chopstx.h>
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#include "kl_sim.h"
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#define INTR_REQ_ADC 15
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struct ADC {
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volatile uint32_t SC1[2];/* Status and Control Registers 1 */
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volatile uint32_t CFG1; /* Configuration Register 1 */
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volatile uint32_t CFG2; /* Configuration Register 2 */
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volatile uint32_t R[2]; /* Data Result Register */
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/* Compare Value Registers 1, 2 */
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volatile uint32_t CV1;
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volatile uint32_t CV2;
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volatile uint32_t SC2; /* Status and Control Register 2 */
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volatile uint32_t SC3; /* Status and Control Register 3 */
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volatile uint32_t OFS; /* Offset Correction Register */
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volatile uint32_t PG; /* Plus-Side Gain Register */
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volatile uint32_t MG; /* Minus-Side Gain Register */
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/* Plus-Side General Calibration Value Registers */
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volatile uint32_t CLPD;
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volatile uint32_t CLPS;
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volatile uint32_t CLP4;
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volatile uint32_t CLP3;
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volatile uint32_t CLP2;
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volatile uint32_t CLP1;
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volatile uint32_t CLP0;
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uint32_t rsvd0;
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/* Minus-Side General Calibration Value Registers */
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volatile uint32_t CLMD;
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volatile uint32_t CLMS;
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volatile uint32_t CLM4;
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volatile uint32_t CLM3;
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volatile uint32_t CLM2;
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volatile uint32_t CLM1;
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volatile uint32_t CLM0;
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};
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static struct ADC *const ADC = (struct ADC *const)0x4003B000;
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/* SC1 */
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#define ADC_SC1_DIFF (1 << 5)
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#define ADC_SC1_AIEN (1 << 6)
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#define ADC_SC1_COCO (1 << 7)
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#define ADC_SC1_TEMPSENSOR 26
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#define ADC_SC1_BANDGAP 27
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#define ADC_SC1_ADCSTOP 31
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/* CFG1 */
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#define ADC_CLOCK_SOURCE_ASYNCH (3 << 0)
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#define ADC_MODE_16BIT (3 << 2)
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#define ADC_ADLSMP_SHORT (0 << 4)
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#define ADC_ADLSMP_LONG (1 << 4)
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#define ADC_ADIV_1 (0 << 5)
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#define ADC_ADIV_8 (3 << 5)
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#define ADC_ADLPC_NORMAL (0 << 7)
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#define ADC_ADLPC_LOWPOWER (1 << 7)
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/**/
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#define ADC_CLOCK_SOURCE ADC_CLOCK_SOURCE_ASYNCH
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#define ADC_MODE ADC_MODE_16BIT
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#if 0
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#define ADC_ADLSMP ADC_ADLSMP_SHORT
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#else
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#define ADC_ADLSMP ADC_ADLSMP_LONG
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#endif
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#define ADC_ADIV ADC_ADIV_8
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#define ADC_ADLPC ADC_ADLPC_LOWPOWER
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/* CFG2 */
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#define ADC_ADLSTS_DEFAULT 0 /* 24 cycles if CFG1.ADLSMP=1, 4 if not. */
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#define ADC_ADHSC_NORMAL (0 << 2)
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#define ADC_ADHSC_HIGHSPEED (1 << 2)
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#define ADC_ADACK_DISABLE (0 << 3)
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#define ADC_ADACK_ENABLE (1 << 3)
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#define ADC_MUXSEL_A (0 << 4)
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#define ADC_MUXSEL_B (1 << 4)
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/**/
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#define ADC_ADLSTS ADC_ADLSTS_DEFAULT
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#define ADC_ADHSC ADC_ADHSC_NORMAL
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#define ADC_ADACKEN ADC_ADACK_ENABLE
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#define ADC_MUXSEL ADC_MUXSEL_A
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/* SC2 */
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#define ADC_SC2_REFSEL_DEFAULT 1 /* Internal Voltage Reference??? */
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#define ADC_SC2_DMAEN (1 << 2)
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#define ADC_SC2_ACREN (1 << 3)
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#define ADC_SC2_ACFGT (1 << 4)
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#define ADC_SC2_ACFE (1 << 5)
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#define ADC_SC2_ADTRG (1 << 6) /* For hardware trigger */
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/* SC3 */
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#define ADC_SC3_AVGS11 0x03
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#define ADC_SC3_AVGE (1 << 2)
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#define ADC_SC3_ADCO (1 << 3)
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#define ADC_SC3_CALF (1 << 6)
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#define ADC_SC3_CAL (1 << 7)
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/*
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* Initialize ADC module, do calibration.
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* This is called by MAIN, only once, before creating any other threads.
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*/
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int
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adc_init (void)
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{
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uint32_t v;
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/* Enable ADC0 clock. */
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SIM->SCGC6 |= (1 << 27);
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ADC->CFG1 = ADC_CLOCK_SOURCE | ADC_MODE | ADC_ADLSMP | ADC_ADIV | ADC_ADLPC;
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ADC->CFG2 = ADC_ADLSTS | ADC_ADHSC | ADC_ADACKEN | ADC_MUXSEL;
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ADC->SC2 = ADC_SC2_REFSEL_DEFAULT;
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ADC->SC3 = ADC_SC3_CAL | ADC_SC3_CALF | ADC_SC3_AVGE | ADC_SC3_AVGS11;
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/* Wait ADC completion */
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while ((ADC->SC1[0] & ADC_SC1_COCO) == 0)
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if ((ADC->SC3 & ADC_SC3_CALF) != 0)
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/* Calibration failure */
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return -1;
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if ((ADC->SC3 & ADC_SC3_CALF) != 0)
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/* Calibration failure */
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return -1;
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/* Configure PG by the calibration values. */
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v = ADC->CLP0 + ADC->CLP1 + ADC->CLP2 + ADC->CLP3 + ADC->CLP4 + ADC->CLPS;
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ADC->PG = 0x8000 | (v >> 1);
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/* Configure MG by the calibration values. */
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v = ADC->CLM0 + ADC->CLM1 + ADC->CLM2 + ADC->CLM3 + ADC->CLM4 + ADC->CLMS;
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ADC->MG = 0x8000 | (v >> 1);
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return 0;
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}
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/*
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* Start using ADC.
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*/
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void
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adc_start (void)
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{
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ADC->CFG1 = ADC_CLOCK_SOURCE | ADC_MODE | ADC_ADLSMP | ADC_ADIV | ADC_ADLPC;
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ADC->CFG2 = ADC_ADLSTS | ADC_ADHSC | ADC_ADACKEN | ADC_MUXSEL;
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ADC->SC2 = ADC_SC2_REFSEL_DEFAULT;
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ADC->SC3 = 0;
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}
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/*
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* Buffer to save ADC data.
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*/
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uint32_t adc_buf[64];
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/*
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* Kick getting data for COUNT times.
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* Data will be saved in ADC_BUF starting at OFFSET.
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*/
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void
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adc_start_conversion (int offset, int count)
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{
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ADC->SC1[0] = /*ADC_SC1_AIEN*/0 | ADC_SC1_TEMPSENSOR;
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}
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static void
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adc_stop_conversion (void)
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{
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ADC->SC1[0] = ADC_SC1_ADCSTOP;
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}
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/*
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* Stop using ADC.
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*/
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void
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adc_stop (void)
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{
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SIM->SCGC6 &= ~(1 << 27);
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}
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/*
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* Return 0 on success.
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* Return 1 on error.
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*/
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int
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adc_wait_completion (chopstx_intr_t *intr)
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{
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/* Wait ADC completion */
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while ((ADC->SC1[0] & ADC_SC1_COCO) == 0)
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;
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adc_buf[0] = ADC->R[0];
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adc_stop_conversion ();
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return 0;
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}
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