Version 1.3.

Signed-off-by: Szczepan Zalega <szczepan@nitrokey.com>

AUTHORS

@@ -22,18 +22,18 @@ Mateusz Zalega:
 	board/board-nitrokey-start.h
 
 NIIBE Yutaka:
-    Write the library:
+    Wrote the library:
 	chopstx.c, entry.c, eventflag.c,
         chopstx.h, eventflag.h
-    Write the drivers mcu/*:
+    Wrote the drivers mcu/*:
     	clk_gpio_init-mkl27z.c, clk_gpio_init-stm32.c,
 	sys-stm32f103.c, sys-stm32f030.c, sys-mkl27z.c,
 	adc-stm32f103.c, adc-mkl27z.c
-    Draw the logo:
+    Drew the logo:
 	chopstx.svg, chopstx.png
-    Write examples:
+    Wrote examples:
         example-led, example-cdc, example-fsm-55, example-fs-bb48
-    Write board/*:
+    Wrote board/*:
         board-fst-01.h, board-fst-01-00.h,
 	board-olimex-stm32-h103.h, board-stm8s-discovery.h
 	board-cq-starm.h, board-stbee-mini.h, board-stbee.h,
@@ -41,3 +41,11 @@ NIIBE Yutaka:
 	board-stm32f0-discovery.h, board-fsm-55.h,
 
 	board-fs-bb48.h
+
+Paul Fertser:
+    Added Blue Pill support.
+	board/board-blue-pill.h
+
+Szczepan Zalega:
+    Modified Nitrokey-Start support.
+	board/board-nitrokey-start.h

ChangeLog

@@ -1,3 +1,33 @@
+2017-02-02  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.3.
+	* doc/chopstx.texi (VERSION): 1.3.
+
+2017-02-01  Paul Fertser <fercerpav@gmail.com>
+
+	* board/board-blue-pill.h: New.
+
+2016-12-08  Szczepan Zalega <szczepan@nitrokey.com>
+
+	* board/board-nitrokey-start.h (VAL_GPIO_USB_ODR): Switch off red
+	LED for Nitrokey Start.
+
+2016-10-13  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* VERSION: 1.2.
+	* doc/chopstx.texi (VERSION): 1.2.
+
+2016-10-12  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* chopstx.c (chopstx_join, chopstx_cancel): chopstx_join is
+	cancellation point.
+
+2016-07-11  NIIBE Yutaka  <gniibe@fsij.org>
+
+	* mcu/stm32f103.h: Add more from Gnuk 1.1.9.
+	* example-cdc, example-fs-bb48, example-fsm-55, example-led:
+	Update for stack addr/size.
+
 2016-07-01  NIIBE Yutaka  <gniibe@fsij.org>
 
 	* VERSION: 1.1.

NEWS

@@ -1,6 +1,22 @@
 NEWS - Noteworthy changes
 
 
+* Major changes in Chopstx 1.3
+
+  Released 2017-02-02
+
+** New board support: Blue Pill
+It is contributed by Paul Fertser.
+
+
+* Major changes in Chopstx 1.2
+
+  Released 2016-10-13
+
+** Fix: chopstx_join
+chopstx_join is now cancellation point.
+
+
 * Major changes in Chopstx 1.1
 
   Released 2016-07-01

README

@@ -1,6 +1,6 @@
 Chopstx - Threads and only Threads
-							 Version 1.1
-							  2016-07-01
+							 Version 1.3
+							  2017-02-02
 							Niibe Yutaka
 					     Flying Stone Technology
 

VERSION

@@ -1 +1 @@
-release/1.1
+release/1.3

board/board-blue-pill.h

@@ -0,0 +1,36 @@
+#define BOARD_NAME "Blue Pill"
+/* http://wiki.stm32duino.com/index.php?title=Blue_Pill */
+/* echo -n "Blue Pill" | shasum -a 256 | sed -e 's/^.*\(........\)  -$/\1/' */
+#define BOARD_ID    0xa1099d43
+
+#define STM32F10X_MD		/* Medium-density device */
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              9
+#define STM32_HSECLK                    8000000
+
+#define GPIO_LED_BASE   GPIOC_BASE
+#define GPIO_LED_CLEAR_TO_EMIT          13
+#define GPIO_USB_BASE   GPIOA_BASE
+#define GPIO_USB_SET_TO_ENABLE          12
+#undef  GPIO_OTHER_BASE
+
+/*
+ * Port A setup.
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF)
+ * ------------------------ Default
+ * PAx  - input with pull-up
+ * PCx  - input with pull-up
+ */
+#define VAL_GPIO_USB_ODR            0xFFFFE7FF
+#define VAL_GPIO_USB_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_USB_CRH            0x88811888      /* PA15...PA8 */
+
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIO_LED_CRH            0x88388888      /* PC15...PC8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPCRST)

board/board-nitrokey-start.h

@@ -22,7 +22,7 @@
  * PA4 - floating input
  * PA5 - floating input
  * PA6 - floating input
- * PA7 - Push pull output   (LED1 1:ON 0:OFF)
+ * PA7 - Push pull output   (Red LED1 1:ON 0:OFF)
  * PA8 - floating input (smartcard, SCDSA)
  * PA9 - floating input
  * PA10 - floating input
@@ -37,13 +37,13 @@
  * PA14 - input with pull-up.
  * PA15 - Push pull output   (USB 1:ON 0:OFF)
  */
-#define VAL_GPIO_USB_ODR            0xFFFFE7FF
+#define VAL_GPIO_USB_ODR            0xFFFFE77F
 #define VAL_GPIO_USB_CRL            0x34444488      /*  PA7...PA0 */
 #define VAL_GPIO_USB_CRH            0x38811444      /* PA15...PA8 */
 
 /*
  * Port B setup.
- * PB0  - Push pull output   (LED2 1:ON 0:OFF)
+ * PB0  - Push pull output   (Green LED2 1:ON 0:OFF)
  * ------------------------ Default
  * PBx  - input with pull-up.
  */

chopstx.c

@@ -1559,6 +1559,8 @@ chopstx_join (chopstx_t thd, void **ret)
    * We don't offer deadlock detection.  It's users' responsibility.
    */
 
+  chopstx_testcancel ();
+
   chx_cpu_sched_lock ();
   if (tp->flag_detached)
     {
@@ -1661,7 +1663,7 @@ chopstx_cancel (chopstx_t thd)
       return;
     }
 
-  /* Cancellation points: cond_wait, usec_wait, and poll.  */
+  /* Cancellation points: cond_wait, usec_wait, join, and poll.  */
   if (tp->state == THREAD_WAIT_CND)
     {
       struct chx_cond *cond = (struct chx_cond *)tp->parent;
@@ -1672,6 +1674,12 @@ chopstx_cancel (chopstx_t thd)
     }
   else if (tp->state == THREAD_WAIT_TIME)
     chx_timer_dequeue (tp);
+  else if (tp->state == THREAD_WAIT_EXIT)
+    {
+      chx_spin_lock (&q_join.lock);
+      ll_dequeue ((struct chx_pq *)tp);
+      chx_spin_unlock (&q_join.lock);
+    }
   else if (tp->state == THREAD_WAIT_POLL)
     {
       if (tp->parent == &q_timer.q)

doc/chopstx.texi

@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
 @c %**start of header
 @setfilename chopstx.info
-@set VERSION 1.1
+@set VERSION 1.3
 @settitle Chopstx Reference Manual
 @c Unify some of the indices.
 @syncodeindex tp fn

example-cdc/sample.c

@@ -61,14 +61,14 @@ blk (void *arg)
 #define PRIO_PWM 3
 #define PRIO_BLK 2
 
-extern uint8_t __process1_stack_base__, __process1_stack_size__;
-extern uint8_t __process2_stack_base__, __process2_stack_size__;
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
 
-const uint32_t __stackaddr_pwm = (uint32_t)&__process1_stack_base__;
-const size_t __stacksize_pwm = (size_t)&__process1_stack_size__;
+#define STACK_ADDR_PWM ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_PWM ((uint32_t)__process1_stack_size__)
 
-const uint32_t __stackaddr_blk = (uint32_t)&__process2_stack_base__;
-const size_t __stacksize_blk = (size_t)&__process2_stack_size__;
+#define STACK_ADDR_BLK ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BLK ((uint32_t)__process2_stack_size__)
 
 
 static char hexchar (uint8_t x)
@@ -98,8 +98,8 @@ main (int argc, const char *argv[])
 
   m = 10;
 
-  chopstx_create (PRIO_PWM, __stackaddr_pwm, __stacksize_pwm, pwm, NULL);
-  chopstx_create (PRIO_BLK, __stackaddr_blk, __stacksize_blk, blk, NULL);
+  chopstx_create (PRIO_PWM, STACK_ADDR_PWM, STACK_SIZE_PWM, pwm, NULL);
+  chopstx_create (PRIO_BLK, STACK_ADDR_BLK, STACK_SIZE_BLK, blk, NULL);
 
   chopstx_usec_wait (200*1000);
 

example-cdc/usb-cdc.c

@@ -642,9 +642,9 @@ static void *tty_main (void *arg);
 #define INTR_REQ_USB 20
 #define PRIO_TTY      4
 
-extern uint8_t __process3_stack_base__, __process3_stack_size__;
-const uint32_t __stackaddr_tty = (uint32_t)&__process3_stack_base__;
-const size_t __stacksize_tty = (size_t)&__process3_stack_size__;
+extern uint8_t __process3_stack_base__[], __process3_stack_size__[];
+#define STACK_ADDR_TTY ((uint32_t)__process3_stack_base__)
+#define STACK_SIZE_TTY ((uint32_t)__process3_stack_size__)
 
 struct tty *
 tty_open (void)
@@ -659,7 +659,7 @@ tty_open (void)
   tty0.device_state = UNCONNECTED;
   memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
 
-  chopstx_create (PRIO_TTY, __stackaddr_tty, __stacksize_tty, tty_main, &tty0);
+  chopstx_create (PRIO_TTY, STACK_ADDR_TTY, STACK_SIZE_TTY, tty_main, &tty0);
   return &tty0;
 }
 

example-fs-bb48/sample.c

@@ -75,14 +75,14 @@ blk (void *arg)
 #define PRIO_PWM 3
 #define PRIO_BLK 2
 
-extern uint8_t __process1_stack_base__, __process1_stack_size__;
-extern uint8_t __process2_stack_base__, __process2_stack_size__;
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
 
-const uint32_t __stackaddr_pwm = (uint32_t)&__process1_stack_base__;
-const size_t __stacksize_pwm = (size_t)&__process1_stack_size__;
+#define STACK_ADDR_PWM ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_PWM ((uint32_t)__process1_stack_size__)
 
-const uint32_t __stackaddr_blk = (uint32_t)&__process2_stack_base__;
-const size_t __stacksize_blk = (size_t)&__process2_stack_size__;
+#define STACK_ADDR_BLK ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BLK ((uint32_t)__process2_stack_size__)
 
 
 static char hexchar (uint8_t x)
@@ -114,8 +114,8 @@ main (int argc, const char *argv[])
 
   m = 10;
 
-  chopstx_create (PRIO_PWM, __stackaddr_pwm, __stacksize_pwm, pwm, NULL);
-  chopstx_create (PRIO_BLK, __stackaddr_blk, __stacksize_blk, blk, NULL);
+  chopstx_create (PRIO_PWM, STACK_ADDR_PWM, STACK_SIZE_PWM, pwm, NULL);
+  chopstx_create (PRIO_BLK, STACK_ADDR_BLK, STACK_SIZE_BLK, blk, NULL);
 
   chopstx_usec_wait (200*1000);
 

example-fs-bb48/usb-cdc.c

@@ -629,9 +629,9 @@ static void *tty_main (void *arg);
 #define INTR_REQ_USB 24
 #define PRIO_TTY      4
 
-extern uint8_t __process3_stack_base__, __process3_stack_size__;
-const uint32_t __stackaddr_tty = (uint32_t)&__process3_stack_base__;
-const size_t __stacksize_tty = (size_t)&__process3_stack_size__;
+extern uint8_t __process3_stack_base__[], __process3_stack_size__[];
+#define STACK_ADDR_TTY ((uint32_t)__process3_stack_base__)
+#define STACK_SIZE_TTY ((uint32_t)__process3_stack_size__)
 
 struct tty *
 tty_open (void)
@@ -646,7 +646,7 @@ tty_open (void)
   tty0.device_state = UNCONNECTED;
   memcpy (&tty0.line_coding, &line_coding0, sizeof (struct line_coding));
 
-  chopstx_create (PRIO_TTY, __stackaddr_tty, __stacksize_tty, tty_main, &tty0);
+  chopstx_create (PRIO_TTY, STACK_ADDR_TTY, STACK_SIZE_TTY, tty_main, &tty0);
   return &tty0;
 }
 

example-fsm-55/debian-logo.c

@@ -166,14 +166,14 @@ button (void *arg)
 #define PRIO_LED 3
 #define PRIO_BUTTON 2
 
-extern uint8_t __process1_stack_base__, __process1_stack_size__;
-extern uint8_t __process2_stack_base__, __process2_stack_size__;
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
 
-const uint32_t __stackaddr_led = (uint32_t)&__process1_stack_base__;
-const size_t __stacksize_led = (size_t)&__process1_stack_size__;
+#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
 
-const uint32_t __stackaddr_button = (uint32_t)&__process2_stack_base__;
-const size_t __stacksize_button = (size_t)&__process2_stack_size__;
+#define STACK_ADDR_BUTTON ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BUTTON ((uint32_t)__process2_stack_size__)
 
 #define DATA55(x0,x1,x2,x3,x4) (x0<<20)|(x1<<15)|(x2<<10)|(x3<< 5)|(x4<< 0)
 #define SIZE55(img) (sizeof (img) / sizeof (uint32_t))
@@ -382,10 +382,10 @@ main (int argc, const char *argv[])
   chopstx_cond_init (&cnd0);
   chopstx_cond_init (&cnd1);
 
-  led_thd = chopstx_create (PRIO_LED, __stackaddr_led,
-			    __stacksize_led, led, NULL);
-  button_thd = chopstx_create (PRIO_BUTTON, __stackaddr_button,
-			       __stacksize_button, button, NULL);
+  led_thd = chopstx_create (PRIO_LED, STACK_ADDR_LED,
+			    STACK_SIZE_LED, led, NULL);
+  button_thd = chopstx_create (PRIO_BUTTON, STACK_ADDR_BUTTON,
+			       STACK_SIZE_BUTTON, button, NULL);
 
   chopstx_usec_wait (200*1000);
 

example-fsm-55/hh.c

@@ -166,14 +166,14 @@ button (void *arg)
 #define PRIO_LED 3
 #define PRIO_BUTTON 2
 
-extern uint8_t __process1_stack_base__, __process1_stack_size__;
-extern uint8_t __process2_stack_base__, __process2_stack_size__;
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
 
-const uint32_t __stackaddr_led = (uint32_t)&__process1_stack_base__;
-const size_t __stacksize_led = (size_t)&__process1_stack_size__;
+#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
 
-const uint32_t __stackaddr_button = (uint32_t)&__process2_stack_base__;
-const size_t __stacksize_button = (size_t)&__process2_stack_size__;
+#define STACK_ADDR_BUTTON ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BUTTON ((uint32_t)__process2_stack_size__)
 
 #define DATA55(x0,x1,x2,x3,x4) (x0<<20)|(x1<<15)|(x2<<10)|(x3<< 5)|(x4<< 0)
 #define SIZE55(img) (sizeof (img) / sizeof (uint32_t))
@@ -370,10 +370,10 @@ main (int argc, const char *argv[])
   chopstx_cond_init (&cnd0);
   chopstx_cond_init (&cnd1);
 
-  led_thd = chopstx_create (PRIO_LED, __stackaddr_led,
-			    __stacksize_led, led, NULL);
-  button_thd = chopstx_create (PRIO_BUTTON, __stackaddr_button,
-			       __stacksize_button, button, NULL);
+  led_thd = chopstx_create (PRIO_LED, STACK_ADDR_LED,
+			    STACK_SIZE_LED, led, NULL);
+  button_thd = chopstx_create (PRIO_BUTTON, STACK_ADDR_BUTTON,
+			       STACK_SIZE_BUTTON, button, NULL);
 
   chopstx_usec_wait (200*1000);
 

example-fsm-55/hiroshi-ayumi.c

@@ -88,10 +88,10 @@ led_enable_column (uint8_t col)
 
 #define PRIO_LED 3
 
-extern uint8_t __process1_stack_base__, __process1_stack_size__;
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
 
-const uint32_t stackaddr_led = (uint32_t)&__process1_stack_base__;
-const size_t stacksize_led = (size_t)&__process1_stack_size__;
+#define STACK_ADDR_LED ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_LED ((uint32_t)__process1_stack_size__)
 
 static void *
 led (void *arg)
@@ -119,10 +119,10 @@ led (void *arg)
 
 
 #define PRIO_SPK 4
-extern uint8_t __process2_stack_base__, __process2_stack_size__;
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
 
-const uint32_t stackaddr_spk = (uint32_t)&__process2_stack_base__;
-const size_t stacksize_spk = (size_t)&__process2_stack_size__;
+#define STACK_ADDR_SPK ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_SPK ((uint32_t)__process2_stack_size__)
 
 static chopstx_mutex_t spk_mtx;
 static chopstx_cond_t spk_cnd;
@@ -193,10 +193,10 @@ spk (void *arg)
 
 
 #define PRIO_MUSIC 2
-extern uint8_t __process3_stack_base__, __process3_stack_size__;
+extern uint8_t __process3_stack_base__[], __process3_stack_size__[];
 
-const uint32_t stackaddr_music = (uint32_t)&__process3_stack_base__;
-const size_t stacksize_music = (size_t)&__process3_stack_size__;
+#define STACK_ADDR_MUSIC ((uint32_t)__process3_stack_base__)
+#define STACK_SIZE_MUSIC ((uint32_t)__process3_stack_size__)
 
 #define C 0
 #define D 1
@@ -254,7 +254,7 @@ music (void *arg)
   chopstx_cond_init (&spk_cnd);
   chopstx_cond_init (&spk_cnd_no_tone);
 
-  chopstx_create (PRIO_SPK, stackaddr_spk, stacksize_spk, spk, NULL);
+  chopstx_create (PRIO_SPK, STACK_ADDR_SPK, STACK_SIZE_SPK, spk, NULL);
 
   while (1)
     {
@@ -350,8 +350,8 @@ main (int argc, const char *argv[])
   chopstx_mutex_init (&mtx);
   chopstx_cond_init (&cnd);
 
-  chopstx_create (PRIO_LED, stackaddr_led, stacksize_led, led, NULL);
-  chopstx_create (PRIO_MUSIC, stackaddr_music, stacksize_music, music, NULL);
+  chopstx_create (PRIO_LED, STACK_ADDR_LED, STACK_SIZE_LED, led, NULL);
+  chopstx_create (PRIO_MUSIC, STACK_ADDR_MUSIC, STACK_SIZE_MUSIC, music, NULL);
 
   chopstx_usec_wait (200*1000);
 

example-led/sample.c

@@ -72,14 +72,14 @@ blk (void *arg)
 #define PRIO_BLK 2
 #endif
 
-extern uint8_t __process1_stack_base__, __process1_stack_size__;
-extern uint8_t __process2_stack_base__, __process2_stack_size__;
+extern uint8_t __process1_stack_base__[], __process1_stack_size__[];
+extern uint8_t __process2_stack_base__[], __process2_stack_size__[];
 
-const uint32_t __stackaddr_pwm = (uint32_t)&__process1_stack_base__;
-const size_t __stacksize_pwm = (size_t)&__process1_stack_size__;
+#define STACK_ADDR_PWM ((uint32_t)__process1_stack_base__)
+#define STACK_SIZE_PWM ((uint32_t)__process1_stack_size__)
 
-const uint32_t __stackaddr_blk = (uint32_t)&__process2_stack_base__;
-const size_t __stacksize_blk = (size_t)&__process2_stack_size__;
+#define STACK_ADDR_BLK ((uint32_t)__process2_stack_base__)
+#define STACK_SIZE_BLK ((uint32_t)__process2_stack_size__)
 
 
 int
@@ -94,8 +94,8 @@ main (int argc, const char *argv[])
 
   m = 10;
 
-  chopstx_create (PRIO_PWM, __stackaddr_pwm, __stacksize_pwm, pwm, NULL);
-  chopstx_create (PRIO_BLK, __stackaddr_blk, __stacksize_blk, blk, NULL);
+  chopstx_create (PRIO_PWM, STACK_ADDR_PWM, STACK_SIZE_PWM, pwm, NULL);
+  chopstx_create (PRIO_BLK, STACK_ADDR_BLK, STACK_SIZE_BLK, blk, NULL);
 
   chopstx_usec_wait (200*1000);
 

mcu/stm32f103.h

@@ -1,10 +1,8 @@
 #define PERIPH_BASE	0x40000000
+#define APB1PERIPH_BASE PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
 
-#define RCC_APB2RSTR_ADC1RST 0x00000200
-#define RCC_APB2RSTR_ADC2RST 0x00000400
-
 struct RCC {
   volatile uint32_t CR;
   volatile uint32_t CFGR;
@@ -26,6 +24,17 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE;
 
 #define RCC_APB2ENR_ADC1EN      0x00000200
 #define RCC_APB2ENR_ADC2EN      0x00000400
+#define RCC_APB2ENR_TIM1EN      0x00000800
+#define RCC_APB1ENR_TIM2EN      0x00000001
+#define RCC_APB1ENR_TIM3EN      0x00000002
+#define RCC_APB1ENR_TIM4EN      0x00000004
+
+#define RCC_APB2RSTR_ADC1RST    0x00000200
+#define RCC_APB2RSTR_ADC2RST    0x00000400
+#define RCC_APB2RSTR_TIM1RST    0x00000800
+#define RCC_APB1RSTR_TIM2RST    0x00000001
+#define RCC_APB1RSTR_TIM3RST    0x00000002
+#define RCC_APB1RSTR_TIM4RST    0x00000004
 
 #define  CRC_CR_RESET                        0x00000001
 
@@ -202,3 +211,490 @@ struct SCB
 #define SCS_BASE 0xE000E000
 #define SCB_BASE (SCS_BASE + 0x0D00)
 static struct SCB *const SCB = (struct SCB *)SCB_BASE;
+
+/* Timer */
+struct TIM
+{
+  volatile uint16_t CR1;   uint16_t  RESERVED0;
+  volatile uint16_t CR2;   uint16_t  RESERVED1;
+  volatile uint16_t SMCR;  uint16_t  RESERVED2;
+  volatile uint16_t DIER;  uint16_t  RESERVED3;
+  volatile uint16_t SR;    uint16_t  RESERVED4;
+  volatile uint16_t EGR;   uint16_t  RESERVED5;
+  volatile uint16_t CCMR1; uint16_t  RESERVED6;
+  volatile uint16_t CCMR2; uint16_t  RESERVED7;
+  volatile uint16_t CCER;  uint16_t  RESERVED8;
+  volatile uint16_t CNT;   uint16_t  RESERVED9;
+  volatile uint16_t PSC;   uint16_t  RESERVED10;
+  volatile uint16_t ARR;   uint16_t  RESERVED11;
+  volatile uint16_t RCR;   uint16_t  RESERVED12;
+  volatile uint16_t CCR1;  uint16_t  RESERVED13;
+  volatile uint16_t CCR2;  uint16_t  RESERVED14;
+  volatile uint16_t CCR3;  uint16_t  RESERVED15;
+  volatile uint16_t CCR4;  uint16_t  RESERVED16;
+  volatile uint16_t BDTR;  uint16_t  RESERVED17;
+  volatile uint16_t DCR;   uint16_t  RESERVED18;
+  volatile uint16_t DMAR;  uint16_t  RESERVED19;
+};
+
+#define TIM2_BASE 0x40000000
+#define TIM3_BASE 0x40000400
+#define TIM4_BASE 0x40000800
+static struct TIM *const TIM2 = (struct TIM *)TIM2_BASE;
+static struct TIM *const TIM3 = (struct TIM *)TIM3_BASE;
+static struct TIM *const TIM4 = (struct TIM *)TIM4_BASE;
+
+#define  TIM_CR1_CEN   	0x0001
+#define  TIM_CR1_UDIS  	0x0002
+#define  TIM_CR1_URS   	0x0004
+#define  TIM_CR1_OPM   	0x0008
+#define  TIM_CR1_DIR   	0x0010
+#define  TIM_CR1_CMS   	0x0060
+#define  TIM_CR1_CMS_0 	0x0020
+#define  TIM_CR1_CMS_1 	0x0040
+#define  TIM_CR1_ARPE  	0x0080
+#define  TIM_CR1_CKD   	0x0300
+#define  TIM_CR1_CKD_0 	0x0100
+#define  TIM_CR1_CKD_1 	0x0200
+
+#define  TIM_CR2_CCPC  	0x0001
+#define  TIM_CR2_CCUS  	0x0004
+#define  TIM_CR2_CCDS  	0x0008
+#define  TIM_CR2_MMS   	0x0070
+#define  TIM_CR2_MMS_0 	0x0010
+#define  TIM_CR2_MMS_1 	0x0020
+#define  TIM_CR2_MMS_2 	0x0040
+#define  TIM_CR2_TI1S  	0x0080
+#define  TIM_CR2_OIS1  	0x0100
+#define  TIM_CR2_OIS1N 	0x0200
+#define  TIM_CR2_OIS2  	0x0400
+#define  TIM_CR2_OIS2N 	0x0800
+#define  TIM_CR2_OIS3  	0x1000
+#define  TIM_CR2_OIS3N 	0x2000
+#define  TIM_CR2_OIS4  	0x4000
+
+#define  TIM_SMCR_SMS   0x0007
+#define  TIM_SMCR_SMS_0 0x0001
+#define  TIM_SMCR_SMS_1 0x0002
+#define  TIM_SMCR_SMS_2 0x0004
+#define  TIM_SMCR_TS    0x0070
+#define  TIM_SMCR_TS_0  0x0010
+#define  TIM_SMCR_TS_1  0x0020
+#define  TIM_SMCR_TS_2  0x0040
+#define  TIM_SMCR_MSM   0x0080
+
+#define  TIM_SMCR_ETF   0x0F00
+#define  TIM_SMCR_ETF_0 0x0100
+#define  TIM_SMCR_ETF_1 0x0200
+#define  TIM_SMCR_ETF_2 0x0400
+#define  TIM_SMCR_ETF_3 0x0800
+
+#define  TIM_SMCR_ETPS   0x3000
+#define  TIM_SMCR_ETPS_0 0x1000
+#define  TIM_SMCR_ETPS_1 0x2000
+
+#define  TIM_SMCR_ECE    0x4000
+#define  TIM_SMCR_ETP    0x8000
+
+#define  TIM_DIER_UIE    0x0001
+#define  TIM_DIER_CC1IE  0x0002
+#define  TIM_DIER_CC2IE  0x0004
+#define  TIM_DIER_CC3IE  0x0008
+#define  TIM_DIER_CC4IE  0x0010
+#define  TIM_DIER_COMIE  0x0020
+#define  TIM_DIER_TIE    0x0040
+#define  TIM_DIER_BIE    0x0080
+#define  TIM_DIER_UDE    0x0100
+#define  TIM_DIER_CC1DE  0x0200
+#define  TIM_DIER_CC2DE  0x0400
+#define  TIM_DIER_CC3DE  0x0800
+#define  TIM_DIER_CC4DE  0x1000
+#define  TIM_DIER_COMDE  0x2000
+#define  TIM_DIER_TDE    0x4000
+
+#define  TIM_SR_UIF      0x0001
+#define  TIM_SR_CC1IF    0x0002
+#define  TIM_SR_CC2IF    0x0004
+#define  TIM_SR_CC3IF    0x0008
+#define  TIM_SR_CC4IF    0x0010
+#define  TIM_SR_COMIF    0x0020
+#define  TIM_SR_TIF      0x0040
+#define  TIM_SR_BIF      0x0080
+#define  TIM_SR_CC1OF    0x0200
+#define  TIM_SR_CC2OF    0x0400
+#define  TIM_SR_CC3OF    0x0800
+#define  TIM_SR_CC4OF    0x1000
+
+#define  TIM_EGR_UG      0x01
+#define  TIM_EGR_CC1G    0x02
+#define  TIM_EGR_CC2G    0x04
+#define  TIM_EGR_CC3G    0x08
+#define  TIM_EGR_CC4G    0x10
+#define  TIM_EGR_COMG    0x20
+#define  TIM_EGR_TG      0x40
+#define  TIM_EGR_BG      0x80
+
+#define  TIM_CCMR1_CC1S   0x0003
+#define  TIM_CCMR1_CC1S_0 0x0001
+#define  TIM_CCMR1_CC1S_1 0x0002
+
+#define  TIM_CCMR1_OC1FE  0x0004
+#define  TIM_CCMR1_OC1PE  0x0008
+
+#define  TIM_CCMR1_OC1M   0x0070
+#define  TIM_CCMR1_OC1M_0 0x0010
+#define  TIM_CCMR1_OC1M_1 0x0020
+#define  TIM_CCMR1_OC1M_2 0x0040
+
+#define  TIM_CCMR1_OC1CE  0x0080
+
+#define  TIM_CCMR1_CC2S   0x0300
+#define  TIM_CCMR1_CC2S_0 0x0100
+#define  TIM_CCMR1_CC2S_1 0x0200
+
+#define  TIM_CCMR1_OC2FE  0x0400
+#define  TIM_CCMR1_OC2PE  0x0800
+
+#define  TIM_CCMR1_OC2M   0x7000
+#define  TIM_CCMR1_OC2M_0 0x1000
+#define  TIM_CCMR1_OC2M_1 0x2000
+#define  TIM_CCMR1_OC2M_2 0x4000
+
+#define  TIM_CCMR1_OC2CE  0x8000
+
+
+#define  TIM_CCMR1_IC1PSC   0x000C
+#define  TIM_CCMR1_IC1PSC_0 0x0004
+#define  TIM_CCMR1_IC1PSC_1 0x0008
+
+#define  TIM_CCMR1_IC1F     0x00F0
+#define  TIM_CCMR1_IC1F_0   0x0010
+#define  TIM_CCMR1_IC1F_1   0x0020
+#define  TIM_CCMR1_IC1F_2   0x0040
+#define  TIM_CCMR1_IC1F_3   0x0080
+
+#define  TIM_CCMR1_IC2PSC   0x0C00
+#define  TIM_CCMR1_IC2PSC_0 0x0400
+#define  TIM_CCMR1_IC2PSC_1 0x0800
+
+#define  TIM_CCMR1_IC2F     0xF000
+#define  TIM_CCMR1_IC2F_0   0x1000
+#define  TIM_CCMR1_IC2F_1   0x2000
+#define  TIM_CCMR1_IC2F_2   0x4000
+#define  TIM_CCMR1_IC2F_3   0x8000
+
+#define  TIM_CCMR2_CC3S     0x0003
+#define  TIM_CCMR2_CC3S_0   0x0001
+#define  TIM_CCMR2_CC3S_1   0x0002
+
+#define  TIM_CCMR2_OC3FE    0x0004
+#define  TIM_CCMR2_OC3PE    0x0008
+
+#define  TIM_CCMR2_OC3M     0x0070
+#define  TIM_CCMR2_OC3M_0   0x0010
+#define  TIM_CCMR2_OC3M_1   0x0020
+#define  TIM_CCMR2_OC3M_2   0x0040
+
+#define  TIM_CCMR2_OC3CE    0x0080
+
+#define  TIM_CCMR2_CC4S     0x0300
+#define  TIM_CCMR2_CC4S_0   0x0100
+#define  TIM_CCMR2_CC4S_1   0x0200
+
+#define  TIM_CCMR2_OC4FE    0x0400
+#define  TIM_CCMR2_OC4PE    0x0800
+
+#define  TIM_CCMR2_OC4M     0x7000
+#define  TIM_CCMR2_OC4M_0   0x1000
+#define  TIM_CCMR2_OC4M_1   0x2000
+#define  TIM_CCMR2_OC4M_2   0x4000
+
+#define  TIM_CCMR2_OC4CE    0x8000
+
+
+#define  TIM_CCMR2_IC3PSC   0x000C
+#define  TIM_CCMR2_IC3PSC_0 0x0004
+#define  TIM_CCMR2_IC3PSC_1 0x0008
+
+#define  TIM_CCMR2_IC3F     0x00F0
+#define  TIM_CCMR2_IC3F_0   0x0010
+#define  TIM_CCMR2_IC3F_1   0x0020
+#define  TIM_CCMR2_IC3F_2   0x0040
+#define  TIM_CCMR2_IC3F_3   0x0080
+
+#define  TIM_CCMR2_IC4PSC   0x0C00
+#define  TIM_CCMR2_IC4PSC_0 0x0400
+#define  TIM_CCMR2_IC4PSC_1 0x0800
+
+#define  TIM_CCMR2_IC4F     0xF000
+#define  TIM_CCMR2_IC4F_0   0x1000
+#define  TIM_CCMR2_IC4F_1   0x2000
+#define  TIM_CCMR2_IC4F_2   0x4000
+#define  TIM_CCMR2_IC4F_3   0x8000
+
+#define  TIM_CCER_CC1E      0x0001
+#define  TIM_CCER_CC1P      0x0002
+#define  TIM_CCER_CC1NE     0x0004
+#define  TIM_CCER_CC1NP     0x0008
+#define  TIM_CCER_CC2E      0x0010
+#define  TIM_CCER_CC2P      0x0020
+#define  TIM_CCER_CC2NE     0x0040
+#define  TIM_CCER_CC2NP     0x0080
+#define  TIM_CCER_CC3E      0x0100
+#define  TIM_CCER_CC3P      0x0200
+#define  TIM_CCER_CC3NE     0x0400
+#define  TIM_CCER_CC3NP     0x0800
+#define  TIM_CCER_CC4E      0x1000
+#define  TIM_CCER_CC4P      0x2000
+
+#define  TIM_CNT_CNT        0xFFFF
+
+#define  TIM_PSC_PSC        0xFFFF
+
+#define  TIM_ARR_ARR        0xFFFF
+
+#define  TIM_RCR_REP        0xFF
+
+#define  TIM_CCR1_CCR1      0xFFFF
+#define  TIM_CCR2_CCR2      0xFFFF
+#define  TIM_CCR3_CCR3      0xFFFF
+#define  TIM_CCR4_CCR4      0xFFFF
+
+#define  TIM_BDTR_DTG       0x00FF
+#define  TIM_BDTR_DTG_0     0x0001
+#define  TIM_BDTR_DTG_1     0x0002
+#define  TIM_BDTR_DTG_2     0x0004
+#define  TIM_BDTR_DTG_3     0x0008
+#define  TIM_BDTR_DTG_4     0x0010
+#define  TIM_BDTR_DTG_5     0x0020
+#define  TIM_BDTR_DTG_6     0x0040
+#define  TIM_BDTR_DTG_7     0x0080
+
+#define  TIM_BDTR_LOCK      0x0300
+#define  TIM_BDTR_LOCK_0    0x0100
+#define  TIM_BDTR_LOCK_1    0x0200
+
+#define  TIM_BDTR_OSSI      0x0400
+#define  TIM_BDTR_OSSR      0x0800
+#define  TIM_BDTR_BKE       0x1000
+#define  TIM_BDTR_BKP       0x2000
+#define  TIM_BDTR_AOE       0x4000
+#define  TIM_BDTR_MOE       0x8000
+
+#define  TIM_DCR_DBA        0x001F
+#define  TIM_DCR_DBA_0      0x0001
+#define  TIM_DCR_DBA_1      0x0002
+#define  TIM_DCR_DBA_2      0x0004
+#define  TIM_DCR_DBA_3      0x0008
+#define  TIM_DCR_DBA_4      0x0010
+
+#define  TIM_DCR_DBL        0x1F00
+#define  TIM_DCR_DBL_0      0x0100
+#define  TIM_DCR_DBL_1      0x0200
+#define  TIM_DCR_DBL_2      0x0400
+#define  TIM_DCR_DBL_3      0x0800
+#define  TIM_DCR_DBL_4      0x1000
+
+#define  TIM_DMAR_DMAB      0xFFFF
+
+struct EXTI
+{
+  volatile uint32_t IMR;
+  volatile uint32_t EMR;
+  volatile uint32_t RTSR;
+  volatile uint32_t FTSR;
+  volatile uint32_t SWIER;
+  volatile uint32_t PR;
+};
+
+#define EXTI_BASE 0x40010400
+static struct EXTI *const EXTI = (struct EXTI *)EXTI_BASE;
+
+#define  EXTI_IMR_MR0       0x00000001
+#define  EXTI_IMR_MR1       0x00000002
+#define  EXTI_IMR_MR2       0x00000004
+#define  EXTI_IMR_MR3       0x00000008
+#define  EXTI_IMR_MR4       0x00000010
+#define  EXTI_IMR_MR5       0x00000020
+#define  EXTI_IMR_MR6       0x00000040
+#define  EXTI_IMR_MR7       0x00000080
+#define  EXTI_IMR_MR8       0x00000100
+#define  EXTI_IMR_MR9       0x00000200
+#define  EXTI_IMR_MR10      0x00000400
+#define  EXTI_IMR_MR11      0x00000800
+#define  EXTI_IMR_MR12      0x00001000
+#define  EXTI_IMR_MR13      0x00002000
+#define  EXTI_IMR_MR14      0x00004000
+#define  EXTI_IMR_MR15      0x00008000
+#define  EXTI_IMR_MR16      0x00010000
+#define  EXTI_IMR_MR17      0x00020000
+#define  EXTI_IMR_MR18      0x00040000
+#define  EXTI_IMR_MR19      0x00080000
+
+#define  EXTI_EMR_MR0       0x00000001
+#define  EXTI_EMR_MR1       0x00000002
+#define  EXTI_EMR_MR2       0x00000004
+#define  EXTI_EMR_MR3       0x00000008
+#define  EXTI_EMR_MR4       0x00000010
+#define  EXTI_EMR_MR5       0x00000020
+#define  EXTI_EMR_MR6       0x00000040
+#define  EXTI_EMR_MR7       0x00000080
+#define  EXTI_EMR_MR8       0x00000100
+#define  EXTI_EMR_MR9       0x00000200
+#define  EXTI_EMR_MR10      0x00000400
+#define  EXTI_EMR_MR11      0x00000800
+#define  EXTI_EMR_MR12      0x00001000
+#define  EXTI_EMR_MR13      0x00002000
+#define  EXTI_EMR_MR14      0x00004000
+#define  EXTI_EMR_MR15      0x00008000
+#define  EXTI_EMR_MR16      0x00010000
+#define  EXTI_EMR_MR17      0x00020000
+#define  EXTI_EMR_MR18      0x00040000
+#define  EXTI_EMR_MR19      0x00080000
+
+#define  EXTI_RTSR_TR0      0x00000001
+#define  EXTI_RTSR_TR1      0x00000002
+#define  EXTI_RTSR_TR2      0x00000004
+#define  EXTI_RTSR_TR3      0x00000008
+#define  EXTI_RTSR_TR4      0x00000010
+#define  EXTI_RTSR_TR5      0x00000020
+#define  EXTI_RTSR_TR6      0x00000040
+#define  EXTI_RTSR_TR7      0x00000080
+#define  EXTI_RTSR_TR8      0x00000100
+#define  EXTI_RTSR_TR9      0x00000200
+#define  EXTI_RTSR_TR10     0x00000400
+#define  EXTI_RTSR_TR11     0x00000800
+#define  EXTI_RTSR_TR12     0x00001000
+#define  EXTI_RTSR_TR13     0x00002000
+#define  EXTI_RTSR_TR14     0x00004000
+#define  EXTI_RTSR_TR15     0x00008000
+#define  EXTI_RTSR_TR16     0x00010000
+#define  EXTI_RTSR_TR17     0x00020000
+#define  EXTI_RTSR_TR18     0x00040000
+#define  EXTI_RTSR_TR19     0x00080000
+
+#define  EXTI_FTSR_TR0      0x00000001
+#define  EXTI_FTSR_TR1      0x00000002
+#define  EXTI_FTSR_TR2      0x00000004
+#define  EXTI_FTSR_TR3      0x00000008
+#define  EXTI_FTSR_TR4      0x00000010
+#define  EXTI_FTSR_TR5      0x00000020
+#define  EXTI_FTSR_TR6      0x00000040
+#define  EXTI_FTSR_TR7      0x00000080
+#define  EXTI_FTSR_TR8      0x00000100
+#define  EXTI_FTSR_TR9      0x00000200
+#define  EXTI_FTSR_TR10     0x00000400
+#define  EXTI_FTSR_TR11     0x00000800
+#define  EXTI_FTSR_TR12     0x00001000
+#define  EXTI_FTSR_TR13     0x00002000
+#define  EXTI_FTSR_TR14     0x00004000
+#define  EXTI_FTSR_TR15     0x00008000
+#define  EXTI_FTSR_TR16     0x00010000
+#define  EXTI_FTSR_TR17     0x00020000
+#define  EXTI_FTSR_TR18     0x00040000
+#define  EXTI_FTSR_TR19     0x00080000
+
+#define  EXTI_SWIER_SWIER0  0x00000001
+#define  EXTI_SWIER_SWIER1  0x00000002
+#define  EXTI_SWIER_SWIER2  0x00000004
+#define  EXTI_SWIER_SWIER3  0x00000008
+#define  EXTI_SWIER_SWIER4  0x00000010
+#define  EXTI_SWIER_SWIER5  0x00000020
+#define  EXTI_SWIER_SWIER6  0x00000040
+#define  EXTI_SWIER_SWIER7  0x00000080
+#define  EXTI_SWIER_SWIER8  0x00000100
+#define  EXTI_SWIER_SWIER9  0x00000200
+#define  EXTI_SWIER_SWIER10 0x00000400
+#define  EXTI_SWIER_SWIER11 0x00000800
+#define  EXTI_SWIER_SWIER12 0x00001000
+#define  EXTI_SWIER_SWIER13 0x00002000
+#define  EXTI_SWIER_SWIER14 0x00004000
+#define  EXTI_SWIER_SWIER15 0x00008000
+#define  EXTI_SWIER_SWIER16 0x00010000
+#define  EXTI_SWIER_SWIER17 0x00020000
+#define  EXTI_SWIER_SWIER18 0x00040000
+#define  EXTI_SWIER_SWIER19 0x00080000
+
+#define  EXTI_PR_PR0        0x00000001
+#define  EXTI_PR_PR1        0x00000002
+#define  EXTI_PR_PR2        0x00000004
+#define  EXTI_PR_PR3        0x00000008
+#define  EXTI_PR_PR4        0x00000010
+#define  EXTI_PR_PR5        0x00000020
+#define  EXTI_PR_PR6        0x00000040
+#define  EXTI_PR_PR7        0x00000080
+#define  EXTI_PR_PR8        0x00000100
+#define  EXTI_PR_PR9        0x00000200
+#define  EXTI_PR_PR10       0x00000400
+#define  EXTI_PR_PR11       0x00000800
+#define  EXTI_PR_PR12       0x00001000
+#define  EXTI_PR_PR13       0x00002000
+#define  EXTI_PR_PR14       0x00004000
+#define  EXTI_PR_PR15       0x00008000
+#define  EXTI_PR_PR16       0x00010000
+#define  EXTI_PR_PR17       0x00020000
+#define  EXTI_PR_PR18       0x00040000
+#define  EXTI_PR_PR19       0x00080000
+
+#define EXTI0_IRQ    6
+#define EXTI1_IRQ    7
+#define EXTI2_IRQ    8
+#define EXTI9_5_IRQ 23
+#define TIM2_IRQ    28
+#define TIM3_IRQ    29
+#define TIM4_IRQ    30
+
+struct AFIO
+{
+  volatile uint32_t EVCR;
+  volatile uint32_t MAPR;
+  volatile uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  volatile uint32_t MAPR2;
+};
+
+#define AFIO_BASE 0x40010000
+static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE;
+
+#define AFIO_EXTICR1_EXTI0_PA 0x0000
+#define AFIO_EXTICR1_EXTI0_PB 0x0001
+#define AFIO_EXTICR1_EXTI0_PC 0x0002
+#define AFIO_EXTICR1_EXTI0_PD 0x0003
+
+#define AFIO_EXTICR1_EXTI1_PA 0x0000
+#define AFIO_EXTICR1_EXTI1_PB 0x0010
+#define AFIO_EXTICR1_EXTI1_PC 0x0020
+#define AFIO_EXTICR1_EXTI1_PD 0x0030
+
+#define AFIO_EXTICR1_EXTI2_PA 0x0000
+#define AFIO_EXTICR1_EXTI2_PB 0x0100
+#define AFIO_EXTICR1_EXTI2_PC 0x0200
+#define AFIO_EXTICR1_EXTI2_PD 0x0300
+
+#define AFIO_EXTICR1_EXTI3_PA 0x0000
+#define AFIO_EXTICR1_EXTI3_PB 0x1000
+#define AFIO_EXTICR1_EXTI3_PC 0x2000
+#define AFIO_EXTICR1_EXTI3_PD 0x3000
+
+#define AFIO_EXTICR2_EXTI4_PA 0x0000
+#define AFIO_EXTICR2_EXTI4_PB 0x0001
+#define AFIO_EXTICR2_EXTI4_PC 0x0002
+#define AFIO_EXTICR2_EXTI4_PD 0x0003
+
+#define AFIO_EXTICR2_EXTI5_PA 0x0000
+#define AFIO_EXTICR2_EXTI5_PB 0x0010
+#define AFIO_EXTICR2_EXTI5_PC 0x0020
+#define AFIO_EXTICR2_EXTI5_PD 0x0030
+
+#define AFIO_EXTICR2_EXTI6_PA 0x0000
+#define AFIO_EXTICR2_EXTI6_PB 0x0100
+#define AFIO_EXTICR2_EXTI6_PC 0x0200
+#define AFIO_EXTICR2_EXTI6_PD 0x0300
+
+#define AFIO_EXTICR2_EXTI7_PA 0x0000
+#define AFIO_EXTICR2_EXTI7_PB 0x1000
+#define AFIO_EXTICR2_EXTI7_PC 0x2000
+#define AFIO_EXTICR2_EXTI7_PD 0x3000
+
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000