Version 0.04

.gitignore

@@ -1,7 +1,4 @@
-example-cdc/.dep
+*/board.h
-example-cdc/board.h
+*/build
-example-cdc/build
+*/.dep
-example-led/.dep
-example-led/board.h
-example-led/build
 doc/chopstx.info

ChangeLog

@@ -1,3 +1,40 @@
+2014-12-10  Niibe Yutaka  <gniibe@fsij.org>
+
+	* Version 0.04.
+	* doc/chopstx.texi (VERSION): 0.04.
+
+	* board/*.h: Updated.
+
+	* example-cdc/sys.c: Copied from example-led.
+
+	* example-led/sys.c (clock_init, GPIO_USB): Follow the change of
+	entry.c.
+	(gpio_init): Use RCC_ENR_IOP_EN and RCC_RSTR_IOP_RST.
+	(reset): Use ldr instead of mov.w and movt.
+
+	* entry.c (GPIO_USB) [GPIO_USB_BASE]: Conditionally defined.
+
+	* chopstx.c (preempt): Add ! for stm.
+	(chx_exit): Make sure RETVAL is saved onto r8.
+	(chopstx_usec_wait_var): Make sure USEC_P is saved onto r8.
+
+2013-11-27  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-stbee-mini.h: New.
+
+	* entry.c (AFIO_MAPR_SWJ_CFG_DISABLE): New.
+
+2013-11-26  Niibe Yutaka  <gniibe@fsij.org>
+
+	* board/board-stbee.h: New.
+
+	* rules.mk (OUTFILES) [ENABLE_OUTPUT_HEX]: Add hex generation.
+
+2013-11-21  Niibe Yutaka  <gniibe@fsij.org>
+
+	* example-cdc/usb_stm32f103.c, example-cdc/usb_lld.h: Update from
+	Gnuk.
+
 2013-11-08  Niibe Yutaka  <gniibe@fsij.org>
 
 	* Version 0.03.

NEWS

@@ -1,5 +1,22 @@
 NEWS - Noteworthy changes
 
+* Major changes in Chopstx 0.04
+
+  Released 2014-12-10, by NIIBE Yutaka
+
+** new board.h macros and sys.c in example
+In board.h, RCC_APB2ENR_IOP_EN was renamed to RCC_ENR_IOP_EN and
+RCC_APB2RSTR_IOP_RST was renamed to RCC_RSTR_IOP_RST.  Example sys.c
+was changed accordingly.
+
+** Bug fix of chopstx_wakeup_usec_wait
+chopstx_usec_wait_var/chopstx_usec_wait won't be woken up
+by chopstx_wakeup_usec_wait.  This is now fixed in 0.04.
+
+** Board support STBee and STBee Mini
+The board STBee and STBee Mini are now supported.
+
+
 * Major changes in Chopstx 0.03
 
   Released 2013-11-08, by NIIBE Yutaka

README

@@ -1,6 +1,6 @@
 Chopstx - Threads and only Threads
-							Version 0.03
+							Version 0.04
-							  2013-11-08
+							  2014-12-10
 							Niibe Yutaka
 					     Flying Stone Technology
 
@@ -35,4 +35,13 @@ USB CDC-ACM function.  You can build it like:
    $ ln -s ../board/board-olimex-stm32-h103.h board.h
    $ make
 
+
+Future Works
+============
+
+We have a development branch for ARM Cortex-M0 and it works fine.
+It will be merged into mainline.
+
+Thread local storage and support of interface like poll/select would
+be next thing to be done.
 -- 

board/board-fst-01-00.h

@@ -25,7 +25,7 @@
 #define GPIO_USB_BASE   GPIOA_BASE
 #define GPIO_LED_BASE   GPIOA_BASE
 
-#define RCC_APB2ENR_IOP_EN      RCC_APB2ENR_IOPAEN
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPAEN
-#define RCC_APB2RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPARST
 
 /* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */

board/board-fst-01.h

@@ -58,8 +58,8 @@
 #define GPIO_USB_BASE   GPIOA_BASE
 #define GPIO_LED_BASE   GPIOB_BASE
 
-#define RCC_APB2ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
-#define RCC_APB2RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
 
 /* NeuG settings for ADC2.  */
 #define NEUG_ADC_SETTING2_SMPR1 0

board/board-olimex-stm32-h103.h

@@ -25,8 +25,8 @@
 #define GPIO_USB_BASE   GPIOC_BASE
 #define GPIO_LED_BASE   GPIOC_BASE
 
-#define RCC_APB2ENR_IOP_EN      RCC_APB2ENR_IOPCEN
+#define RCC_ENR_IOP_EN      RCC_APB2ENR_IOPCEN
-#define RCC_APB2RSTR_IOP_RST    RCC_APB2RSTR_IOPCRST
+#define RCC_RSTR_IOP_RST    RCC_APB2RSTR_IOPCRST
 
 /* NeuG settings for ADC2.  */
 #define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \

board/board-stbee-mini.h

@@ -0,0 +1,115 @@
+#define FLASH_PAGE_SIZE 1024
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
+
+#define GPIO_USB_SET_TO_ENABLE          14
+#define GPIO_LED_CLEAR_TO_EMIT          13
+
+#if defined(PINPAD_CIR_SUPPORT) || defined(PINPAD_DIAL_SUPPORT)
+#define HAVE_7SEGLED	1
+/*
+ * Timer assignment for CIR
+ */
+#define TIMx                  TIM3
+#define INTR_REQ_TIM          TIM3_IRQ
+#define AFIO_EXTICR_INDEX     0
+#endif
+
+#if defined(PINPAD_CIR_SUPPORT)
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI0_PB
+#define EXTI_PR               EXTI_PR_PR0
+#define EXTI_IMR              EXTI_IMR_MR0
+#define EXTI_FTSR_TR          EXTI_FTSR_TR0
+#define INTR_REQ_EXTI         EXTI0_IRQ
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM3EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM3RST
+#elif defined(PINPAD_DIAL_SUPPORT)
+#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PB
+#define EXTI_PR               EXTI_PR_PR2
+#define EXTI_IMR              EXTI_IMR_MR2
+#define EXTI_FTSR_TR          EXTI_FTSR_TR2
+#define INTR_REQ_EXTI         EXTI2_IRQ
+#define RCC_APBnENR_TIMxEN    RCC_APB1ENR_TIM4EN
+#define RCC_APBnRSTR_TIMxRST  RCC_APB1RSTR_TIM4RST
+#endif
+#define ENABLE_RCC_APB1
+
+#if defined(PINPAD_CIR_SUPPORT) || defined(PINPAD_DIAL_SUPPORT)
+/*
+ * Port A setup.
+ * PA1  - Digital input with PullUp.  AN1 for NeuG
+ * PA2  - Digital input with PullUp.  AN2 for NeuG
+ * PA6  - (TIM3_CH1) input with pull-up
+ * PA7  - (TIM3_CH2) input with pull-down
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * PA13 - Open Drain output (LED1 0:ON 1:OFF)
+ * PA14 - Push pull output  (USB ENABLE 0:DISABLE 1:ENABLE)
+ * PA15 - Open Drain output (LED2 0:ON 1:OFF)
+ */
+#define VAL_GPIO_ODR            0xFFFFE77F
+#define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_CRH            0x63611888      /* PA15...PA8 */
+
+/*
+ * Port B setup.
+ * PB0  - Push pull output   (LED 1:ON 0:OFF)
+ * ------------------------ Default
+ * PBx  - input with pull-up.
+ */
+#define VAL_GPIO_LED_ODR            0xFFFFFFFF
+#define VAL_GPIO_LED_CRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIO_LED_CRH            0x66666666      /* PB15...PB8 */
+
+/* Port B setup. */
+#define GPIOB_CIR               0
+#define GPIOB_BUTTON            2
+#define GPIOB_ROT_A             6
+#define GPIOB_ROT_B             7
+
+#define GPIOB_7SEG_DP           15
+#define GPIOB_7SEG_A            14
+#define GPIOB_7SEG_B            13
+#define GPIOB_7SEG_C            12
+#define GPIOB_7SEG_D            11
+#define GPIOB_7SEG_E            10
+#define GPIOB_7SEG_F            9
+#define GPIOB_7SEG_G            8
+
+#define RCC_ENR_IOP_EN      \
+        (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
+#define RCC_RSTR_IOP_RST    \
+        (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)
+#else
+/*
+ * Port A setup.
+ * PA1  - Digital input with PullUp.  AN1 for NeuG
+ * PA2  - Digital input with PullUp.  AN2 for NeuG
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ * PA13 - Open Drain output (LED1 0:ON 1:OFF)
+ * PA14 - Push pull output  (USB ENABLE 0:DISABLE 1:ENABLE)
+ * PA15 - Open Drain output (LED2 0:ON 1:OFF)
+ */
+#define VAL_GPIO_ODR            0xFFFFE7FF
+#define VAL_GPIO_CRL            0x88888888      /*  PA7...PA0 */
+#define VAL_GPIO_CRH            0x63611888      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_AFIORST)
+#endif
+
+
+#define GPIO_USB_BASE           GPIOA_BASE
+#define GPIO_LED_BASE           GPIOA_BASE
+#define AFIO_MAPR_SOMETHING     AFIO_MAPR_SWJ_CFG_DISABLE
+
+/* NeuG settings for ADC2.  */
+#define NEUG_ADC_SETTING2_SMPR1 0
+#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5)    \
+                              | ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5)
+#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1)      \
+                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2)
+#define NEUG_ADC_SETTING2_NUM_CHANNELS 2

board/board-stbee.h

@@ -0,0 +1,42 @@
+#define FLASH_PAGE_SIZE 2048
+
+#define STM32_PLLXTPRE                  STM32_PLLXTPRE_DIV1
+#define STM32_PLLMUL_VALUE              6
+#define STM32_HSECLK                    12000000
+
+#define GPIO_USB_CLEAR_TO_ENABLE        3
+#define GPIO_LED_CLEAR_TO_EMIT          4
+
+/*
+ * Port A setup.
+ * PA0  - Normal input.
+ * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
+ * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
+ */
+#define VAL_GPIO_OTHER_ODR      0xFFFFE7FF
+#define VAL_GPIO_OTHER_CRL      0x88888884      /*  PA7...PA0 */
+#define VAL_GPIO_OTHER_CRH      0x88811888      /* PA15...PA8 */
+
+#define RCC_ENR_IOP_EN      (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPDEN)
+#define RCC_RSTR_IOP_RST    (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPDRST)
+
+/*
+ * Port D setup.
+ * PD3  - Push pull output  (USB_DISC 1:USB-DISABLE 0:USB-ENABLE) 2MHz
+ * PD4  - Open Drain output 2MHz (LED1).
+ */
+#define VAL_GPIO_ODR            0xFFFFFFFF
+#define VAL_GPIO_CRL            0x88862888      /*  PD7...PD0 */
+#define VAL_GPIO_CRH            0x88888888      /* PD15...PD8 */
+
+#define GPIO_USB_BASE   GPIOD_BASE
+#define GPIO_LED_BASE   GPIOD_BASE
+#define GPIO_OTHER_BASE GPIOA_BASE
+
+/* NeuG settings for ADC2.  */
+#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \
+                              | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5)
+#define NEUG_ADC_SETTING2_SMPR2 0
+#define NEUG_ADC_SETTING2_SQR3  ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)   \
+                              | ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11)
+#define NEUG_ADC_SETTING2_NUM_CHANNELS 2

board/board-stm8s-discovery.h

@@ -39,9 +39,9 @@
 #define GPIO_USB_BASE   GPIOA_BASE
 #define GPIO_LED_BASE   GPIOA_BASE
 
-#define RCC_APB2ENR_IOP_EN   \
+#define RCC_ENR_IOP_EN   \
   (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN)
-#define RCC_APB2RSTR_IOP_RST \
+#define RCC_RSTR_IOP_RST \
   (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)
 
 /* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1).  */

chopstx.c

@@ -1,7 +1,7 @@
 /*
  * chopstx.c - Threads and only threads.
  *
- * Copyright (C) 2013 Flying Stone Technology
+ * Copyright (C) 2013, 2014 Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -449,7 +449,7 @@ preempt (void)
        "mov	r4, r10\n\t"
        "mov	r5, r11\n\t"
        "mrs	r6, PSP\n\t" /* r13(=SP) in user space.  */
-       "stm	r1, {r2, r3, r4, r5, r6}"
+       "stm	r1!, {r2, r3, r4, r5, r6}"
        : "=r" (tp)
        : "r" (tp)
        : "r1", "r2", "r3", "r4", "r5", "r6", "cc", "memory");
@@ -502,7 +502,7 @@ svc (void)
        "mov	r4, r10\n\t"
        "mov	r5, r11\n\t"
        "mrs	r6, PSP\n\t" /* r13(=SP) in user space.  */
-       "stm	r1, {r2, r3, r4, r5, r6}\n\t"
+       "stm	r1!, {r2, r3, r4, r5, r6}\n\t"
        "ldr	r1, [r6]"
        : "=r" (tp), "=r" (orig_r0)
        : /* no input */
@@ -777,9 +777,11 @@ chx_sched (uint32_t arg)
 static void __attribute__((noreturn))
 chx_exit (void *retval)
 {
-  register uint32_t r8 asm ("r8") = (uint32_t)retval;
+  register uint32_t r8 asm ("r8");
   struct chx_thread *q;
 
+  asm volatile ("mov	%0, %1" : "=r" (r8) : "r" (retval));
+
   chx_cpu_sched_lock ();
   if (running->flag_join_req)
     {		       /* wake up a thread which requests to join */
@@ -917,14 +919,16 @@ chopstx_create (uint32_t flags_and_prio,
 void
 chopstx_usec_wait_var (uint32_t *var)
 {
-  register uint32_t *usec_p asm ("r8") = var;
+  register uint32_t *r8 asm ("r8");
+  uint32_t *usec_p = var;
   uint32_t usec;
   uint32_t usec0 = 0;
 
+  asm volatile ("mov	%0, %1" : "=r" (r8) : "r" (usec_p));
   while (1)
     {
       chx_cpu_sched_lock ();
-      if (!usec_p)		/* awakened */
+      if (!r8)		/* awakened */
 	break;
       *usec_p -= usec0;
       usec = *usec_p;
@@ -937,8 +941,9 @@ chopstx_usec_wait_var (uint32_t *var)
       running->state = THREAD_WAIT_TIME;
       chx_timer_insert (running, usec0);
       chx_spin_unlock (&q_timer.lock);
+      asm volatile ("mov	%0, %1" : "=r" (r8) : "r" (usec_p));
       chx_sched (CHX_SLEEP);
-      asm ("" : "=r" (usec_p) : "r" (usec_p));
+      asm ("" : "=r" (r8) : "r" (r8));
     }
 
   chx_cpu_sched_unlock ();

doc/chopstx.texi

@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
 @c %**start of header
 @setfilename chopstx.info
-@set VERSION 0.03
+@set VERSION 0.04
 @settitle Chopstx Reference Manual
 @c Unify some of the indices.
 @syncodeindex tp fn

entry.c

@@ -1,7 +1,7 @@
 /*
  * entry.c - Entry routine when reset and interrupt vectors.
  *
- * Copyright (C) 2013 Flying Stone Technology
+ * Copyright (C) 2013, 2014 Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * This file is a part of Chopstx, a thread library for embedded.
@@ -33,10 +33,13 @@
 #ifdef HAVE_SYS_H
 #define INLINE __attribute__ ((used))
 #include "sys.h"
+#include "board.h"
 #else
 #include "board.h"
 
+#define STM32_SW_HSI		(0 << 0)
 #define STM32_SW_PLL		(2 << 0)
+#define STM32_PLLSRC_HSI	(0 << 16)
 #define STM32_PLLSRC_HSE	(1 << 16)
 
 #define STM32_PLLXTPRE_DIV1	(0 << 17)
@@ -44,6 +47,7 @@
 
 #define STM32_HPRE_DIV1		(0 << 4)
 
+#define STM32_PPRE1_DIV1	(0 << 8)
 #define STM32_PPRE1_DIV2	(4 << 8)
 
 #define STM32_PPRE2_DIV1        (0 << 11)
@@ -56,26 +60,29 @@
 
 #define STM32_MCO_NOCLOCK	(0 << 24)
 
-#define STM32_SW		STM32_SW_PLL
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_HPRE		STM32_HPRE_DIV1
 #define STM32_PPRE1		STM32_PPRE1_DIV2
+#define STM32_PLLSRC		STM32_PLLSRC_HSE
+#define STM32_FLASHBITS		0x00000012
+#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
+
+#define STM32_SW		STM32_SW_PLL
+#define STM32_HPRE		STM32_HPRE_DIV1
 #define STM32_PPRE2		STM32_PPRE2_DIV1
 #define STM32_ADCPRE		STM32_ADCPRE_DIV6
 #define STM32_MCOSEL		STM32_MCO_NOCLOCK
 #define STM32_USBPRE            STM32_USBPRE_DIV1P5
 
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
 #define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
 #define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
 #define STM32_SYSCLK		STM32_PLLCLKOUT
 #define STM32_HCLK		(STM32_SYSCLK / 1)
 
-#define STM32_FLASHBITS		0x00000012
 
 #define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
 
 struct RCC {
   volatile uint32_t CR;
@@ -109,6 +116,18 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
 
 #define RCC_AHBENR_CRCEN        0x0040
 
+#define RCC_APB2RSTR_AFIORST	0x00000001
+#define RCC_APB2RSTR_IOPARST	0x00000004
+#define RCC_APB2RSTR_IOPBRST	0x00000008
+#define RCC_APB2RSTR_IOPCRST	0x00000010
+#define RCC_APB2RSTR_IOPDRST	0x00000020
+
+#define RCC_APB2ENR_AFIOEN	0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+
 struct FLASH {
   volatile uint32_t ACR;
   volatile uint32_t KEYR;
@@ -131,7 +150,8 @@ clock_init (void)
   RCC->CR |= RCC_CR_HSION;
   while (!(RCC->CR & RCC_CR_HSIRDY))
     ;
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
+  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
+  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
   RCC->CFGR = 0;
   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
     ;
@@ -151,6 +171,10 @@ clock_init (void)
   RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
     | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
 
+  /*
+   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
+   */
+
   /* Flash setup */
   FLASH->ACR = STM32_FLASHBITS;
 
@@ -163,18 +187,6 @@ clock_init (void)
     ;
 }
 
-#define RCC_APB2RSTR_AFIORST	0x00000001
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-#define RCC_APB2ENR_AFIOEN	0x00000001
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-
 
 struct AFIO
 {
@@ -189,6 +201,7 @@ struct AFIO
 static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
 
 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
 
 
 struct GPIO {
@@ -212,8 +225,10 @@ struct GPIO {
 #define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
 #define GPIOE		((struct GPIO *) GPIOE_BASE)
 
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
 static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
+#ifdef GPIO_USB_BASE
+static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
+#endif
 #ifdef GPIO_OTHER_BASE
 static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
 #endif
@@ -222,8 +237,8 @@ static void __attribute__((used))
 gpio_init (void)
 {
   /* Enable GPIO clock. */
-  RCC->APB2ENR |= RCC_APB2ENR_IOP_EN;
+  RCC->APB2ENR |= RCC_ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
+  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
   RCC->APB2RSTR = 0;
 
 #ifdef AFIO_MAPR_SOMETHING
@@ -249,6 +264,12 @@ gpio_init (void)
 #endif
 
 
+extern uint8_t __main_stack_end__;
+extern void svc (void);
+extern void preempt (void);
+extern void chx_timer_expired (void);
+extern void chx_handle_intr (void);
+
 static void nmi (void)
 {
   for (;;);
@@ -333,12 +354,6 @@ void entry (void)
 
 
 typedef void (*handler)(void);
-extern uint8_t __main_stack_end__;
-
-extern void svc (void);
-extern void preempt (void);
-extern void chx_timer_expired (void);
-extern void chx_handle_intr (void);
 
 handler vector_table[] __attribute__ ((section(".startup.vectors"))) = {
   (handler)&__main_stack_end__,

example-cdc/sys.c

@@ -1,7 +1,7 @@
 /*
  * sys.c - system routines for the initial page for STM32F103.
  *
- * Copyright (C) 2013 Flying Stone Technology
+ * Copyright (C) 2013, 2014 Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * Copying and distribution of this file, with or without modification,
@@ -24,7 +24,9 @@
 #define STM32_USB_IRQ_PRIORITY   11
 
 
+#define STM32_SW_HSI		(0 << 0)
 #define STM32_SW_PLL		(2 << 0)
+#define STM32_PLLSRC_HSI	(0 << 16)
 #define STM32_PLLSRC_HSE	(1 << 16)
 
 #define STM32_PLLXTPRE_DIV1	(0 << 17)
@@ -32,6 +34,7 @@
 
 #define STM32_HPRE_DIV1		(0 << 4)
 
+#define STM32_PPRE1_DIV1	(0 << 8)
 #define STM32_PPRE1_DIV2	(4 << 8)
 
 #define STM32_PPRE2_DIV1        (0 << 11)
@@ -44,23 +47,23 @@
 
 #define STM32_MCO_NOCLOCK	(0 << 24)
 
-#define STM32_SW		STM32_SW_PLL
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_HPRE		STM32_HPRE_DIV1
 #define STM32_PPRE1		STM32_PPRE1_DIV2
+#define STM32_PLLSRC		STM32_PLLSRC_HSE
+#define STM32_FLASHBITS		0x00000012
+#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
+
+#define STM32_SW		STM32_SW_PLL
+#define STM32_HPRE		STM32_HPRE_DIV1
 #define STM32_PPRE2		STM32_PPRE2_DIV1
 #define STM32_ADCPRE		STM32_ADCPRE_DIV6
 #define STM32_MCOSEL		STM32_MCO_NOCLOCK
 #define STM32_USBPRE            STM32_USBPRE_DIV1P5
 
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
 #define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
 #define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
 #define STM32_SYSCLK		STM32_PLLCLKOUT
 #define STM32_HCLK		(STM32_SYSCLK / 1)
 
-#define STM32_FLASHBITS		0x00000012
-
 struct NVIC {
   uint32_t ISER[8];
   uint32_t unused1[24];
@@ -92,8 +95,10 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
 
 
 #define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
 
 struct RCC {
   volatile uint32_t CR;
@@ -127,6 +132,18 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
 
 #define RCC_AHBENR_CRCEN        0x0040
 
+#define RCC_APB2RSTR_AFIORST	0x00000001
+#define RCC_APB2RSTR_IOPARST	0x00000004
+#define RCC_APB2RSTR_IOPBRST	0x00000008
+#define RCC_APB2RSTR_IOPCRST	0x00000010
+#define RCC_APB2RSTR_IOPDRST	0x00000020
+
+#define RCC_APB2ENR_AFIOEN	0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+
 struct FLASH {
   volatile uint32_t ACR;
   volatile uint32_t KEYR;
@@ -149,7 +166,8 @@ clock_init (void)
   RCC->CR |= RCC_CR_HSION;
   while (!(RCC->CR & RCC_CR_HSIRDY))
     ;
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
+  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
+  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
   RCC->CFGR = 0;
   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
     ;
@@ -169,6 +187,10 @@ clock_init (void)
   RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
     | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
 
+  /*
+   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
+   */
+
   /* Flash setup */
   FLASH->ACR = STM32_FLASHBITS;
 
@@ -181,18 +203,6 @@ clock_init (void)
     ;
 }
 
-#define RCC_APB2RSTR_AFIORST    0x00000001
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-#define RCC_APB2ENR_AFIOEN      0x00000001
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-
 
 struct AFIO
 {
@@ -207,6 +217,7 @@ struct AFIO
 static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
 
 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
 
 
 struct GPIO {
@@ -230,8 +241,10 @@ struct GPIO {
 #define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
 #define GPIOE		((struct GPIO *) GPIOE_BASE)
 
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
 static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
+#ifdef GPIO_USB_BASE
+static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
+#endif
 #ifdef GPIO_OTHER_BASE
 static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
 #endif
@@ -240,8 +253,8 @@ static void
 gpio_init (void)
 {
   /* Enable GPIO clock. */
-  RCC->APB2ENR |= RCC_APB2ENR_IOP_EN;
+  RCC->APB2ENR |= RCC_ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
+  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
   RCC->APB2RSTR = 0;
 
 #ifdef AFIO_MAPR_SOMETHING
@@ -577,10 +590,13 @@ reset (void)
 {
   extern const unsigned long *FT0, *FT1, *FT2;
 
+  /*
+   * This code may not be at the start of flash ROM, because of DFU.
+   * So, we take the address from PC.
+   */
   asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
-		"mov.w	r0, #0xed00\n\t" /* r0 = SCR */
+		"ldr	r0, 1f\n\t"     /* r0 = SCR */
-		"movt	r0, #0xe000\n\t"
+		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
-		"mov	r1, pc\n\t"	 /* r1 = (PC + 0x1000) & ~0x0fff */
 		"mov	r2, #0x1000\n\t"
 		"add	r1, r1, r2\n\t"
 		"sub	r2, r2, #1\n\t"
@@ -589,7 +605,9 @@ reset (void)
 		"ldr	r0, [r1], #4\n\t"
 		"msr	MSP, r0\n\t"	/* Main (exception handler) stack. */
 		"ldr	r0, [r1]\n\t"	/* Reset handler.                  */
-		"bx	r0\n"
+		"bx	r0\n\t"
+		".align	2\n"
+	"1:	.word	0xe000ed00"
 		: /* no output */ : /* no input */ : "memory");
 
   /* Never reach here. */

example-cdc/usb_lld.h

@@ -89,7 +89,6 @@ enum DEVICE_STATE
   CONFIGURED
 };
 
-extern const uint8_t usb_initial_feature;
 
 extern void usb_lld_init (uint8_t feature);
 

example-cdc/usb_stm32f103.c

@@ -160,7 +160,7 @@ static struct DATA_INFO *const data_p = &data_info;
 #define EPRX_DTOG1     (0x1000) /* EndPoint RX Data TOGgle bit1 */
 #define EPRX_DTOG2     (0x2000) /* EndPoint RX Data TOGgle bit1 */
 
-static void usb_handle_transfer (void);
+static void usb_handle_transfer (uint16_t istr_value);
 
 static void st103_set_btable (void)
 {
@@ -390,20 +390,22 @@ usb_interrupt_handler (void)
 {
   uint16_t istr_value = st103_get_istr ();
 
-  if ((istr_value & ISTR_CTR))
-    usb_handle_transfer ();
-
   if ((istr_value & ISTR_RESET))
     {
       st103_set_istr (CLR_RESET);
       usb_cb_device_reset ();
     }
+  else
+    {
+      if ((istr_value & ISTR_OVR))
+	st103_set_istr (CLR_OVR);
 
-  if ((istr_value & ISTR_OVR))
+      if ((istr_value & ISTR_ERR))
-    st103_set_istr (CLR_OVR);
+	st103_set_istr (CLR_ERR);
 
-  if ((istr_value & ISTR_ERR))
+      if ((istr_value & ISTR_CTR))
-    st103_set_istr (CLR_ERR);
+	usb_handle_transfer (istr_value);
+    }
 }
 
 static void handle_datastage_out (void)
@@ -931,70 +933,66 @@ void WEAK EP6_OUT_Callback (void);
 void WEAK EP7_OUT_Callback (void);
 
 static void
-usb_handle_transfer (void)
+usb_handle_transfer (uint16_t istr_value)
 {
   uint16_t ep_value = 0;
-  uint16_t istr_value;
   uint8_t ep_index;
 
-  while (((istr_value = st103_get_istr ()) & ISTR_CTR))
+  ep_index = (istr_value & ISTR_EP_ID);
+  /* Decode and service non control endpoints interrupt  */
+  /* process related endpoint register */
+  ep_value = st103_get_epreg (ep_index);
+
+  if (ep_index == 0)
     {
-      ep_index = (istr_value & ISTR_EP_ID);
+      if ((ep_value & EP_CTR_TX))
-      /* Decode and service non control endpoints interrupt  */
-      /* process related endpoint register */
-      ep_value = st103_get_epreg (ep_index);
-
-      if (ep_index == 0)
 	{
-	  if ((ep_value & EP_CTR_TX))
+	  st103_ep_clear_ctr_tx (ep_index);
-	    {
+	  handle_in0 ();
-	      st103_ep_clear_ctr_tx (ep_index);
-	      handle_in0 ();
-	    }
-
-	  if ((ep_value & EP_CTR_RX))
-	    {
-	      st103_ep_clear_ctr_rx (ep_index);
-
-	      if ((ep_value & EP_SETUP))
-		handle_setup0 ();
-	      else
-		handle_out0 ();
-	    }
-
-	  if (dev_p->state == STALLED)
-	    st103_ep_set_rxtx_status (ENDP0, EP_RX_STALL, EP_TX_STALL);
 	}
-      else
-	{
-	  if ((ep_value & EP_CTR_RX))
-	    {
-	      st103_ep_clear_ctr_rx (ep_index);
-	      switch ((ep_index - 1))
-		{
-		case 0: EP1_OUT_Callback ();  break;
-		case 1: EP2_OUT_Callback ();  break;
-		case 2: EP3_OUT_Callback ();  break;
-		case 3: EP4_OUT_Callback ();  break;
-		case 4: EP5_OUT_Callback ();  break;
-		case 5: EP6_OUT_Callback ();  break;
-		case 6: EP7_OUT_Callback ();  break;
-		}
-	    }
 
-	  if ((ep_value & EP_CTR_TX))
+      if ((ep_value & EP_CTR_RX))
+	{
+	  st103_ep_clear_ctr_rx (ep_index);
+
+	  if ((ep_value & EP_SETUP))
+	    handle_setup0 ();
+	  else
+	    handle_out0 ();
+	}
+
+      if (dev_p->state == STALLED)
+	st103_ep_set_rxtx_status (ENDP0, EP_RX_STALL, EP_TX_STALL);
+    }
+  else
+    {
+      if ((ep_value & EP_CTR_RX))
+	{
+	  st103_ep_clear_ctr_rx (ep_index);
+	  switch ((ep_index - 1))
 	    {
-	      st103_ep_clear_ctr_tx (ep_index);
+	    case 0: EP1_OUT_Callback ();  break;
-	      switch ((ep_index - 1))
+	    case 1: EP2_OUT_Callback ();  break;
-		{
+	    case 2: EP3_OUT_Callback ();  break;
-		case 0: EP1_IN_Callback ();  break;
+	    case 3: EP4_OUT_Callback ();  break;
-		case 1: EP2_IN_Callback ();  break;
+	    case 4: EP5_OUT_Callback ();  break;
-		case 2: EP3_IN_Callback ();  break;
+	    case 5: EP6_OUT_Callback ();  break;
-		case 3: EP4_IN_Callback ();  break;
+	    case 6: EP7_OUT_Callback ();  break;
-		case 4: EP5_IN_Callback ();  break;
+	    }
-		case 5: EP6_IN_Callback ();  break;
+	}
-		case 6: EP7_IN_Callback ();  break;
+
-		}
+      if ((ep_value & EP_CTR_TX))
+	{
+	  st103_ep_clear_ctr_tx (ep_index);
+	  switch ((ep_index - 1))
+	    {
+	    case 0: EP1_IN_Callback ();  break;
+	    case 1: EP2_IN_Callback ();  break;
+	    case 2: EP3_IN_Callback ();  break;
+	    case 3: EP4_IN_Callback ();  break;
+	    case 4: EP5_IN_Callback ();  break;
+	    case 5: EP6_IN_Callback ();  break;
+	    case 6: EP7_IN_Callback ();  break;
 	    }
 	}
     }

example-led/sys.c

@@ -1,7 +1,7 @@
 /*
  * sys.c - system routines for the initial page for STM32F103.
  *
- * Copyright (C) 2013 Flying Stone Technology
+ * Copyright (C) 2013, 2014 Flying Stone Technology
  * Author: NIIBE Yutaka <gniibe@fsij.org>
  *
  * Copying and distribution of this file, with or without modification,
@@ -24,7 +24,9 @@
 #define STM32_USB_IRQ_PRIORITY   11
 
 
+#define STM32_SW_HSI		(0 << 0)
 #define STM32_SW_PLL		(2 << 0)
+#define STM32_PLLSRC_HSI	(0 << 16)
 #define STM32_PLLSRC_HSE	(1 << 16)
 
 #define STM32_PLLXTPRE_DIV1	(0 << 17)
@@ -32,6 +34,7 @@
 
 #define STM32_HPRE_DIV1		(0 << 4)
 
+#define STM32_PPRE1_DIV1	(0 << 8)
 #define STM32_PPRE1_DIV2	(4 << 8)
 
 #define STM32_PPRE2_DIV1        (0 << 11)
@@ -44,23 +47,23 @@
 
 #define STM32_MCO_NOCLOCK	(0 << 24)
 
-#define STM32_SW		STM32_SW_PLL
-#define STM32_PLLSRC		STM32_PLLSRC_HSE
-#define STM32_HPRE		STM32_HPRE_DIV1
 #define STM32_PPRE1		STM32_PPRE1_DIV2
+#define STM32_PLLSRC		STM32_PLLSRC_HSE
+#define STM32_FLASHBITS		0x00000012
+#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
+
+#define STM32_SW		STM32_SW_PLL
+#define STM32_HPRE		STM32_HPRE_DIV1
 #define STM32_PPRE2		STM32_PPRE2_DIV1
 #define STM32_ADCPRE		STM32_ADCPRE_DIV6
 #define STM32_MCOSEL		STM32_MCO_NOCLOCK
 #define STM32_USBPRE            STM32_USBPRE_DIV1P5
 
-#define STM32_PLLCLKIN		(STM32_HSECLK / 1)
 #define STM32_PLLMUL		((STM32_PLLMUL_VALUE - 2) << 18)
 #define STM32_PLLCLKOUT		(STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
 #define STM32_SYSCLK		STM32_PLLCLKOUT
 #define STM32_HCLK		(STM32_SYSCLK / 1)
 
-#define STM32_FLASHBITS		0x00000012
-
 struct NVIC {
   uint32_t ISER[8];
   uint32_t unused1[24];
@@ -92,8 +95,10 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
 
 
 #define PERIPH_BASE	0x40000000
+#define APBPERIPH_BASE   PERIPH_BASE
 #define APB2PERIPH_BASE	(PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE	(PERIPH_BASE + 0x20000)
+#define AHB2PERIPH_BASE	(PERIPH_BASE + 0x08000000)
 
 struct RCC {
   volatile uint32_t CR;
@@ -127,6 +132,18 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
 
 #define RCC_AHBENR_CRCEN        0x0040
 
+#define RCC_APB2RSTR_AFIORST	0x00000001
+#define RCC_APB2RSTR_IOPARST	0x00000004
+#define RCC_APB2RSTR_IOPBRST	0x00000008
+#define RCC_APB2RSTR_IOPCRST	0x00000010
+#define RCC_APB2RSTR_IOPDRST	0x00000020
+
+#define RCC_APB2ENR_AFIOEN	0x00000001
+#define RCC_APB2ENR_IOPAEN	0x00000004
+#define RCC_APB2ENR_IOPBEN	0x00000008
+#define RCC_APB2ENR_IOPCEN	0x00000010
+#define RCC_APB2ENR_IOPDEN	0x00000020
+
 struct FLASH {
   volatile uint32_t ACR;
   volatile uint32_t KEYR;
@@ -149,7 +166,8 @@ clock_init (void)
   RCC->CR |= RCC_CR_HSION;
   while (!(RCC->CR & RCC_CR_HSIRDY))
     ;
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION;
+  /* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
+  RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
   RCC->CFGR = 0;
   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
     ;
@@ -169,6 +187,10 @@ clock_init (void)
   RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
     | STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
 
+  /*
+   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
+   */
+
   /* Flash setup */
   FLASH->ACR = STM32_FLASHBITS;
 
@@ -181,18 +203,6 @@ clock_init (void)
     ;
 }
 
-#define RCC_APB2RSTR_AFIORST    0x00000001
-#define RCC_APB2RSTR_IOPARST	0x00000004
-#define RCC_APB2RSTR_IOPBRST	0x00000008
-#define RCC_APB2RSTR_IOPCRST	0x00000010
-#define RCC_APB2RSTR_IOPDRST	0x00000020
-
-#define RCC_APB2ENR_AFIOEN      0x00000001
-#define RCC_APB2ENR_IOPAEN	0x00000004
-#define RCC_APB2ENR_IOPBEN	0x00000008
-#define RCC_APB2ENR_IOPCEN	0x00000010
-#define RCC_APB2ENR_IOPDEN	0x00000020
-
 
 struct AFIO
 {
@@ -207,6 +217,7 @@ struct AFIO
 static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
 
 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
+#define AFIO_MAPR_SWJ_CFG_DISABLE         0x04000000
 
 
 struct GPIO {
@@ -230,8 +241,10 @@ struct GPIO {
 #define GPIOE_BASE	(APB2PERIPH_BASE + 0x1800)
 #define GPIOE		((struct GPIO *) GPIOE_BASE)
 
-static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
 static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
+#ifdef GPIO_USB_BASE
+static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
+#endif
 #ifdef GPIO_OTHER_BASE
 static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
 #endif
@@ -240,8 +253,8 @@ static void
 gpio_init (void)
 {
   /* Enable GPIO clock. */
-  RCC->APB2ENR |= RCC_APB2ENR_IOP_EN;
+  RCC->APB2ENR |= RCC_ENR_IOP_EN;
-  RCC->APB2RSTR = RCC_APB2RSTR_IOP_RST;
+  RCC->APB2RSTR = RCC_RSTR_IOP_RST;
   RCC->APB2RSTR = 0;
 
 #ifdef AFIO_MAPR_SOMETHING
@@ -577,10 +590,13 @@ reset (void)
 {
   extern const unsigned long *FT0, *FT1, *FT2;
 
+  /*
+   * This code may not be at the start of flash ROM, because of DFU.
+   * So, we take the address from PC.
+   */
   asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
-		"mov.w	r0, #0xed00\n\t" /* r0 = SCR */
+		"ldr	r0, 1f\n\t"     /* r0 = SCR */
-		"movt	r0, #0xe000\n\t"
+		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
-		"mov	r1, pc\n\t"	 /* r1 = (PC + 0x1000) & ~0x0fff */
 		"mov	r2, #0x1000\n\t"
 		"add	r1, r1, r2\n\t"
 		"sub	r2, r2, #1\n\t"
@@ -589,7 +605,9 @@ reset (void)
 		"ldr	r0, [r1], #4\n\t"
 		"msr	MSP, r0\n\t"	/* Main (exception handler) stack. */
 		"ldr	r0, [r1]\n\t"	/* Reset handler.                  */
-		"bx	r0\n"
+		"bx	r0\n\t"
+		".align	2\n"
+	"1:	.word	0xe000ed00"
 		: /* no output */ : /* no input */ : "memory");
 
   /* Never reach here. */

rules.mk

@@ -10,6 +10,10 @@ INCDIR += $(CHOPSTX)
 
 BUILDDIR = build
 OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).bin
+ifneq ($(ENABLE_OUTPUT_HEX),)
+OUTFILES += $(BUILDDIR)/$(PROJECT).hex
+endif
+
 
 OPT += -ffunction-sections -fdata-sections -fno-common
 
@@ -49,6 +53,9 @@ $(OBJS) : $(BUILDDIR)/%.o : %.c Makefile
 %.bin: %.elf $(LDSCRIPT)
 	$(OBJCOPY) -O binary $< $@
 
+%.hex: %.elf $(LDSCRIPT)
+	$(OBJCOPY) -O ihex $< $@
+
 clean:
 	-rm -f -r .dep $(BUILDDIR)