NIIBE Yutaka
a70b1acbf6
Change asm for Cortex-M0/3/4.
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Signed-off-by: NIIBE Yutaka <gniibe@fsij.org >
2021-02-25 12:52:26 +09:00
NIIBE Yutaka
eaa47d5059
Update copyright notices.
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Signed-off-by: NIIBE Yutaka <gniibe@fsij.org >
2021-02-10 10:44:37 +09:00
NIIBE Yutaka
cfcdeebb78
More fixes for Cortex-M0/Cortex-M3/Cortex-M4 implementations.
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Signed-off-by: NIIBE Yutaka <gniibe@fsij.org >
2021-02-08 12:22:16 +09:00
NIIBE Yutaka
b0986cdb09
Fix preemption.
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Consider the sequence:
chx_handle_intr -> chx_handle_intr -> preempt
We can't use R0 passing as an argument to preempt.
Signed-off-by: NIIBE Yutaka <gniibe@fsij.org >
2021-02-05 11:26:20 +09:00
NIIBE Yutaka
214066fd82
Add RISC-V 32 IMAC support.
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Signed-off-by: NIIBE Yutaka <gniibe@fsij.org >
2019-12-03 13:27:16 +09:00
