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Fix for Cortex-M0.

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Signed-off-by: NIIBE Yutaka <gniibe@fsij.org>
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NIIBE Yutaka
2021-02-25 10:35:29 +09:00
parent 95fe257dc0
commit fd8bb46b8b
2 changed files with 17 additions and 1 deletions
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ChangeLog
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@@ -1,3 +1,8 @@
2021-02-25 NIIBE Yutaka <gniibe@fsij.org>
* chopstx-cortex-m.c [__ARM_ARCH_6M__] (chx_handle_intr): More
fix, it's actually different syntax in assembler.
2021-02-19 NIIBE Yutaka <gniibe@fsij.org>
* chopstx-cortex-m.c (chx_handle_intr): Fix SUB instruction.

13
chopstx-cortex-m.c
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@@ -334,7 +334,18 @@ chx_handle_intr (void)
register struct chx_thread *tp_next asm ("r0");;
asm volatile ("mrs %0, IPSR\n\t"
"subs %0, #16\n\t" /* Exception # - 16 = interrupt number. */
/* Exception # - 16 = interrupt number. */
/*
* Confusingly, ARM_ARCH_6M uses Pre-UAL Thumb syntax,
* while we use UAL syntax for newer. Note that the
* binary representation of the instruction is exactly
* same, despite the syntax difference.
*/
#if defined(__ARM_ARCH_6M__)
"sub %0, #16\n\t"
#else
"subs %0, #16\n\t"
#endif
"bpl 0f\n\t"
"bl chx_timer_expired\n\t"
"b 1f\n"