Version 0.05
Merge branch 'cortex-m0-support'
This commit is contained in:
NIIBE Yutaka
@@ -1,5 +1,5 @@
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/*
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* sys.c - system routines for the initial page for STM32F103.
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* sys.c - system routines for the initial page for STM32F030 / STM32F103.
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*
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* Copyright (C) 2013, 2014 Flying Stone Technology
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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@@ -47,10 +47,17 @@
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#define STM32_MCO_NOCLOCK (0 << 24)
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#if defined(MCU_STM32F0)
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#define STM32_PPRE1 STM32_PPRE1_DIV1
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#define STM32_PLLSRC STM32_PLLSRC_HSI
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#define STM32_FLASHBITS 0x00000011
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#define STM32_PLLCLKIN (STM32_HSICLK / 2)
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#else
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_FLASHBITS 0x00000012
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#endif
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#define STM32_SW STM32_SW_PLL
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#define STM32_HPRE STM32_HPRE_DIV1
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@@ -111,6 +118,12 @@ struct RCC {
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volatile uint32_t APB1ENR;
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volatile uint32_t BDCR;
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volatile uint32_t CSR;
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#if defined(MCU_STM32F0)
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volatile uint32_t AHBRSTR;
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volatile uint32_t CFGR2;
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volatile uint32_t CFGR3;
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volatile uint32_t CR2;
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#endif
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};
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#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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@@ -132,6 +145,22 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
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#define RCC_AHBENR_CRCEN 0x0040
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#if MCU_STM32F0
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#define RCC_AHBRSTR_IOPARST 0x00020000
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#define RCC_AHBRSTR_IOPBRST 0x00040000
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#define RCC_AHBRSTR_IOPCRST 0x00080000
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#define RCC_AHBRSTR_IOPDRST 0x00100000
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#define RCC_AHBRSTR_IOPFRST 0x00400000
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#define RCC_AHBENR_IOPAEN 0x00020000
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#define RCC_AHBENR_IOPBEN 0x00040000
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#define RCC_AHBENR_IOPCEN 0x00080000
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#define RCC_AHBENR_IOPDEN 0x00100000
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#define RCC_AHBENR_IOPFEN 0x00400000
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#define RCC_APB2RSTR_SYSCFGRST 0x00000001
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#define RCC_APB2ENR_SYSCFGEN 0x00000001
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#else
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#define RCC_APB2RSTR_AFIORST 0x00000001
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#define RCC_APB2RSTR_IOPARST 0x00000004
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#define RCC_APB2RSTR_IOPBRST 0x00000008
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@@ -143,6 +172,20 @@ static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
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#define RCC_APB2ENR_IOPBEN 0x00000008
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#define RCC_APB2ENR_IOPCEN 0x00000010
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#define RCC_APB2ENR_IOPDEN 0x00000020
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#endif
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#if MCU_STM32F0
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struct SYSCFG {
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volatile uint32_t CFGR1;
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uint32_t dummy0;
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volatile uint32_t EXTICR[4];
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volatile uint32_t CFGR2;
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};
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#define SYSCFG_CFGR1_MEM_MODE 0x03
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#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
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static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
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#endif
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struct FLASH {
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volatile uint32_t ACR;
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@@ -172,10 +215,12 @@ clock_init (void)
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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;
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#if !defined(MCU_STM32F0)
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/* HSE setup */
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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;
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#endif
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/* PLL setup */
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RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
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@@ -201,9 +246,48 @@ clock_init (void)
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RCC->CFGR |= STM32_SW;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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#if defined(MCU_STM32F0)
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
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RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
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RCC->APB2RSTR = 0;
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/* Use vectors on RAM */
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SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
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#endif
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}
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#if defined(MCU_STM32F0)
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struct GPIO {
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volatile uint32_t MODER;
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volatile uint16_t OTYPER;
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uint16_t dummy0;
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volatile uint32_t OSPEEDR;
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volatile uint32_t PUPDR;
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volatile uint16_t IDR;
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uint16_t dummy1;
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volatile uint16_t ODR;
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uint16_t dummy2;
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volatile uint16_t BSRR;
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uint16_t dummy3;
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volatile uint32_t LCKR;
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volatile uint32_t AFR[2];
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volatile uint16_t BRR;
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uint16_t dummy4;
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};
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#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
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#define GPIOA ((struct GPIO *) GPIOA_BASE)
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#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
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#define GPIOB ((struct GPIO *) GPIOB_BASE)
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#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
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#define GPIOC ((struct GPIO *) GPIOC_BASE)
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#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
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#define GPIOD ((struct GPIO *) GPIOD_BASE)
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#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
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#define GPIOF ((struct GPIO *) GPIOF_BASE)
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#else
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struct AFIO
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{
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volatile uint32_t EVCR;
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@@ -240,6 +324,7 @@ struct GPIO {
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#define GPIOD ((struct GPIO *) GPIOD_BASE)
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#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
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#define GPIOE ((struct GPIO *) GPIOE_BASE)
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#endif
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static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
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#ifdef GPIO_USB_BASE
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@@ -253,10 +338,29 @@ static void
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gpio_init (void)
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{
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/* Enable GPIO clock. */
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#if defined(MCU_STM32F0)
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RCC->AHBENR |= RCC_ENR_IOP_EN;
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RCC->AHBRSTR = RCC_RSTR_IOP_RST;
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RCC->AHBRSTR = 0;
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#else
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RCC->APB2ENR |= RCC_ENR_IOP_EN;
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RCC->APB2RSTR = RCC_RSTR_IOP_RST;
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RCC->APB2RSTR = 0;
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#endif
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#if MCU_STM32F0
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GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
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GPIO_LED->OTYPER = VAL_GPIO_OTYPER;
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GPIO_LED->MODER = VAL_GPIO_MODER;
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GPIO_LED->PUPDR = VAL_GPIO_PUPDR;
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#ifdef GPIO_OTHER_BASE
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GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
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GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
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GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
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GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
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#endif
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#else
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#ifdef AFIO_MAPR_SOMETHING
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AFIO->MAPR |= AFIO_MAPR_SOMETHING;
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#endif
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@@ -276,6 +380,7 @@ gpio_init (void)
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GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
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GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
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#endif
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#endif
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}
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static void
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@@ -594,6 +699,28 @@ reset (void)
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* This code may not be at the start of flash ROM, because of DFU.
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* So, we take the address from PC.
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*/
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#if defined(__ARM_ARCH_6M__)
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asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
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"ldr r0, 1f\n\t" /* r0 = RAM start */
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"mov r1, pc\n\t" /* r1 = (PC + 0x0400) & ~0x03ff */
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"mov r2, #0x04\n\t"
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"lsl r2, #8\n\t"
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"add r1, r1, r2\n\t"
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"sub r2, r2, #1\n\t"
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"bic r1, r1, r2\n\t"
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"mov r2, #188\n"
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"2:\n\t" /* Copy vectors. It will be enabled later by clock_init. */
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"ldr r3, [r1, r2]\n\t"
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"str r3, [r0, r2]\n\t"
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"sub r2, #4\n\t"
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"bcs 2b\n\t"
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"msr MSP, r3\n\t" /* Main (exception handler) stack. */
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"ldr r0, [r1, #4]\n\t" /* Reset handler. */
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"bx r0\n\t"
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".align 2\n"
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"1: .word 0x20000000"
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: /* no output */ : /* no input */ : "memory");
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#else
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asm volatile ("cpsid i\n\t" /* Mask all interrupts. */
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"ldr r0, 1f\n\t" /* r0 = SCR */
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"mov r1, pc\n\t" /* r1 = (PC + 0x1000) & ~0x0fff */
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@@ -609,6 +736,7 @@ reset (void)
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".align 2\n"
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"1: .word 0xe000ed00"
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: /* no output */ : /* no input */ : "memory");
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#endif
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/* Never reach here. */
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/* Artificial entry to refer FT0, FT1, and FT2. */
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