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Rename _PHR_ (as peripheral) to specific bus (AHB, APB, etc.).

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This commit is contained in:
NIIBE Yutaka
2019-04-12 10:45:12 +09:00
parent 52efc84f5c
commit f237314ebf
4 changed files with 18 additions and 17 deletions
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2
board/board-st-nucleo-l432.h
View File

@@ -59,4 +59,4 @@
#define VAL_GPIO_LED_AFRL 0x00000000
#define VAL_GPIO_LED_AFRH 0x00000000
#define RCC_PHR_GPIO (RCC_PHR_GPIOA | RCC_PHR_GPIOB)
#define RCC_AHB2_GPIO (RCC_AHB2_GPIOA | RCC_AHB2_GPIOB)

6
mcu/clk_gpio_init-stm32l.c
View File

@@ -69,12 +69,12 @@ void
gpio_init (void)
{
/* Enable GPIO clock. */
RCC->AHB2ENR |= RCC_PHR_GPIO;
RCC->AHB2ENR |= RCC_AHB2_GPIO;
/* Delay (more than two clocks) is needed. */
while ((RCC->AHB2ENR & RCC_PHR_GPIO) == 0)
while ((RCC->AHB2ENR & RCC_AHB2_GPIO) == 0)
;
RCC->AHB2RSTR = RCC_PHR_GPIO;
RCC->AHB2RSTR = RCC_AHB2_GPIO;
RCC->AHB2RSTR = 0;
/* Delay (more than two clocks) is needed. */

16
mcu/stm32l.h
View File

@@ -59,15 +59,15 @@ struct RCC {
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000)
static struct RCC *const RCC = (struct RCC *)RCC_BASE;
#define RCC_PHR_GPIOA 0x00000001
#define RCC_PHR_GPIOB 0x00000002
#define RCC_PHR_GPIOC 0x00000004
#define RCC_PHR_GPIOD 0x00000008
#define RCC_PHR_GPIOE 0x00000010
#define RCC_PHR_GPIOH 0x00000080
#define RCC_AHB2_GPIOA 0x00000001
#define RCC_AHB2_GPIOB 0x00000002
#define RCC_AHB2_GPIOC 0x00000004
#define RCC_AHB2_GPIOD 0x00000008
#define RCC_AHB2_GPIOE 0x00000010
#define RCC_AHB2_GPIOH 0x00000080
#define RCC_PHR_USB (1 << 26)
#define RCC_PHR_CRS (1 << 24)
#define RCC_APB1_1_USB (1 << 26)
#define RCC_APB1_1_CRS (1 << 24)
struct PWR

11
mcu/sys-stm32l4.c
View File

@@ -47,8 +47,8 @@ static void wait (int count)
void
usb_lld_sys_shutdown (void)
{
RCC->APB1ENR1 &= ~(RCC_PHR_USB | RCC_PHR_CRS);
RCC->APB1RSTR1 |= (RCC_PHR_USB | RCC_PHR_CRS);
RCC->APB1ENR1 &= ~(RCC_APB1_1_USB | RCC_APB1_1_CRS);
RCC->APB1RSTR1 |= (RCC_APB1_1_USB | RCC_APB1_1_CRS);
}
void
@@ -56,7 +56,8 @@ usb_lld_sys_init (void)
{
/* XXX: should configure CRS (clock recovery system) and HSI48 clock */
if ((RCC->APB1ENR1 & RCC_PHR_USB) && (RCC->APB1RSTR1 & RCC_PHR_USB) == 0)
if ((RCC->APB1ENR1 & RCC_APB1_1_USB)
&& (RCC->APB1RSTR1 & RCC_APB1_1_USB) == 0)
/* Make sure the device is disconnected, even after core reset. */
{
usb_lld_sys_shutdown ();
@@ -64,8 +65,8 @@ usb_lld_sys_init (void)
wait (5*MHZ);
}
RCC->APB1ENR1 |= (RCC_PHR_USB | RCC_PHR_CRS);
RCC->APB1RSTR1 = (RCC_PHR_USB | RCC_PHR_CRS);
RCC->APB1ENR1 |= (RCC_APB1_1_USB | RCC_APB1_1_CRS);
RCC->APB1RSTR1 = (RCC_APB1_1_USB | RCC_APB1_1_CRS);
RCC->APB1RSTR1 = 0;
}