Version 0.01

ChangeLog

@@ -1,6 +1,20 @@
+2013-11-03  Niibe Yutaka  <gniibe@fsij.org>
+
+	* Version 0.01.
+	* doc/chopstx.texi (VERSION): 0.01.
+
+	* chopstx.c (chx_clr_intr): New.
+	(chopstx_intr_wait): Call chopstx.c.
+	(chx_enable_intr): Let chx_clr_intr clear pending-bit.
+
 2013-11-02  Niibe Yutaka  <gniibe@fsij.org>
 
-	* example-cdc/sys.c, example-led/sys.c: Update.
+	* example-cdc/usb_lld.h, example-cdc/usb_stm32f103.c: Update from
+	Gnuk.
+	* example-cdc/usb-cdc.c (usb_cb_get_descriptor): Follow the
+	change.
+
+	* example-cdc/sys.c, example-led/sys.c: Update from Gnuk.
 
 	* chopstx.c (CPU_EXCEPTION_PRIORITY_INTERRUPT)
 	(CPU_EXCEPTION_PRIORITY_PENDSV): Change the value, so that

NEWS

@@ -0,0 +1,43 @@
+NEWS - Noteworthy changes
+
+* Major changes in Chopstx 0.01
+
+  Released 2013-11-03, by NIIBE Yutaka
+
+** Interrupt handling change
+There was a bug in 0.00, which caused spurious interrupts.  Every
+interrupt event caused two events.  Specifically, after valid
+interrupt event (for the caller of chopstx_intr_wait), another
+spurious event was always occurred.  This was fixed.
+
+In the design of Chopstx, interrupt handling is done by a thread.
+Lower level interrupt handler just accepts interrupt, disabling the
+interrupt, and switchs the control to the thread.  It is the thread to
+check the cause of interrupt, to process it, and to clear the cause.
+Next call to chopstx_intr_wait will enable the interrupt again.
+
+The bug was related to pending interrupt flag.  Pending interrupt flag
+for a specific interrupt is set, on return from handler mode if the
+cause is still active.  With traditional interrupt handling, lower
+level interrupt handler processes it and clears the cause.  Thus,
+pending interrupt flag is not set on return.
+
+In Chopstx, pending interrupt flag was always set, because the control
+goes from lower level interrupt handler (in handler mode) to a
+interrupt handling thread which processes the interrupt.  In 0.01, new
+internal routine chx_clr_intr is introduced, and pending interrupt
+flag is cleared within chopstx_intr_wait after waked up.
+
+For detail of interrupt operation, see the section B.3.4, Nested
+Vectored Interrupt Controller (NVIC), in the ARM v7-M Architecture
+Reference Manual.  The subsection, B3.4.1, Theory of operation,
+explains how it works.
+
+
+** gpio_init change
+Now, gpi_init support AFIO mapping and another GPIO (GPIO_OTHER)
+settings.
+
+Local Variables:
+mode: outline
+End:

chopstx.c

@@ -642,10 +642,15 @@ chx_timer_expired (void)
 static void
 chx_enable_intr (uint8_t irq_num)
 {
-  NVIC_ICPR (irq_num) = 1 << (irq_num & 0x1f); /* Clear pending.  */
   NVIC_ISER (irq_num) = 1 << (irq_num & 0x1f);
 }
 
+static void
+chx_clr_intr (uint8_t irq_num)
+{				/* Clear pending interrupt.  */
+  NVIC_ICPR (irq_num) = 1 << (irq_num & 0x1f);
+}
+
 static void
 chx_disable_intr (uint8_t irq_num)
 {
@@ -1253,6 +1258,7 @@ chopstx_intr_wait (chopstx_intr_t *intr)
       running->state = THREAD_WAIT_INT;
       running->v = 0;
       chx_sched (CHX_SLEEP);
+      chx_clr_intr (intr->irq_num);
     }
   else
     chx_cpu_sched_unlock ();

doc/chopstx.texi

@@ -1,7 +1,7 @@
 \input texinfo                      @c -*-texinfo-*-
 @c %**start of header
 @setfilename chopstx.info
-@set VERSION 0.00
+@set VERSION 0.01
 @settitle Chopstx Reference Manual
 @c Unify some of the indices.
 @syncodeindex tp fn