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cortex-m: Multiple interrupts handling may occur on Cortex-M3 too.

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Signed-off-by: NIIBE Yutaka <gniibe@fsij.org>
This commit is contained in:
NIIBE Yutaka
2021-02-05 10:54:41 +09:00
parent 6d46ea2a4c
commit c3f00e1c69
1 changed files with 2 additions and 6 deletions
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8
chopstx-cortex-m.c
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@@ -29,9 +29,7 @@
*/
static struct chx_thread *running;
#if defined(__ARM_ARCH_6M__)
static struct chx_thread *preempting;
#endif
static struct chx_thread *
chx_running (void)
@@ -265,7 +263,6 @@ chx_request_preemption_possibly (struct chx_thread *tp_next)
if (!tp_next)
return NULL;
#if defined(__ARM_ARCH_6M__)
if (preempting)
{
chx_ready_push (tp_next);
@@ -273,7 +270,6 @@ chx_request_preemption_possibly (struct chx_thread *tp_next)
}
else
preempting = tp_next;
#endif
*ICSR = (1 << 28);
asm volatile ("" : : : "memory");
@@ -494,12 +490,12 @@ preempt (struct chx_thread * tp_next)
register struct chx_thread *tp_current asm ("r1");
asm (
#if defined(__ARM_ARCH_6M__)
"mov r1, #0\n\t"
"ldr r2, =preempting\n\t"
#if defined(__ARM_ARCH_6M__)
"ldr r0, [r2]\n\t"
"str r1, [r2]\n\t"
#endif
"str r1, [r2]\n\t"
"ldr r2, =running\n\t"
"ldr r1, [r2]"
: "=r" (tp_current)