Version 2.1.

Signed-off-by: NIIBE Yutaka <gniibe@fsij.org>
This commit is contained in:
NIIBE Yutaka
2021-02-12 09:19:08 +09:00
parent 27791641aa
commit c0f3567ed6
4 changed files with 36 additions and 6 deletions

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@@ -1,3 +1,8 @@
2021-02-12 NIIBE Yutaka <gniibe@fsij.org>
* VERSION: 2.1
* doc/chopstx.texi (VERSION): 2.1.
2021-02-10 NIIBE Yutaka <gniibe@fsij.org>
* example-cdc-gnu-linux/usb-cdc.c (tty_recv): Cancel the input.

25
NEWS
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@@ -1,6 +1,31 @@
NEWS - Noteworthy changes
* Major changes in Chopstx 2.1
Released 2021-02-12
** GNU/Linux emulation change
The process can be asked to exit by SIGINT or SIGTERM.
** Bug fix for interrupt handling
The check to find waiting thread was wrong. If no waiting thread,
it failed.
** Bug fix for GNU/Linux emulation
In 2.0, GNU/Linux emulation doesn't work well with chx_idle when it
handles interrupt synchronously and the waken thread is the same one
which called chx_idle.
** Bug fix for Cortex-M0/Cortex-M3 Support
In 2.0, Cortex-M0 with no tail-chaining support (e.g. STM32F030)
doesn't work. In 2.0, Cortex-M3/M4 may fail when two or more
interrupts occur simultaneously; A waken thread (which is about to
preempt RUNNING) by the first interrupt may be lost (and never
scheduled again), by the second interrupt handling before the call of
preempt function.
* Major changes in Chopstx 2.0
Released 2020-06-26

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release/2.0
release/2.1

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\input texinfo @c -*-texinfo-*-
@c %**start of header
@setfilename chopstx.info
@set VERSION 2.0
@set VERSION 2.1
@settitle Chopstx Reference Manual
@c Unify some of the indices.
@syncodeindex tp fn
@@ -11,7 +11,7 @@
This manual is for Chopstx (version @value{VERSION}).
@noindent
Copyright @copyright{} 2013, 2015, 2016, 2017, 2018, 2019, 2020 Flying Stone Technology @*
Copyright @copyright{} 2013, 2015, 2016, 2017, 2018, 2019, 2020, 2021 Flying Stone Technology @*
@quotation
Permission is granted to copy, distribute and/or modify this document
@@ -91,7 +91,7 @@ Indexes
Chopstx is an RT thread library for ARM Cortex-M0, Cortex-M0plus,
Cortex-M3, Cortex-M4 with no FPU or DSP, RISC-V Bumblebee, and
GNU/Linux emulation. Specifically, it is used for STM32F030, MKL27Z,
STM32F103, GD32F103, STM32L432, GD32V103 and as a command on
STM32F103, GD32F103, STM32L432, GD32VF103 and as a command on
GNU/Linux.
While most RTOSes come with many features, drivers, and stacks,
@@ -126,7 +126,7 @@ done by interrupt handler, bottom half, and thead is crucial for
applications' performance. And because the demarcation should be done
at an early stage of an application development, it has a tendency,
many parts are getting demanding higher priority. Amount of code for
higher priority interrupt hander is getting bigger and bigger, while
higher priority interrupt handler is getting bigger and bigger, while
losing performance.
On the other hand, ``Threads (and only Threads)'' programming style
@@ -239,7 +239,7 @@ chx_handle_intr entries.
Obviously, this is suboptimal. It kills the hardware effort to
decrease interrupt latency.
I is certainly possible to support configurable vector table and/or
It is certainly possible to support configurable vector table and/or
better dispatch.
The reason why I keep this badness is that I believe that when