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board update, adding ST Dongle

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This commit is contained in:
NIIBE Yutaka
2015-07-29 17:06:17 +09:00
parent 83486efd5f
commit a9de53c36b
14 changed files with 92 additions and 47 deletions
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4
AUTHORS
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@@ -6,6 +6,10 @@ Kaz Kojima:
Added STM32 Primer2 support. Added STM32 Primer2 support.
board/board-stm32-primer2.h board/board-stm32-primer2.h
Kenji Rikitake:
Added ST Dongle support.
board/board-st-dongle.h
NIIBE Yutaka: NIIBE Yutaka:
Write the library: Write the library:
chopstx.c, eventflag.c, entry.c, clk_gpio_init.c chopstx.c, eventflag.c, entry.c, clk_gpio_init.c

6
ChangeLog
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@@ -1,3 +1,9 @@
2015-07-29 Niibe Yutaka <gniibe@fsij.org>
* board/board-st-dongle.h: New.
* board/board-*.h (FLASH_PAGE_SIZE): Remove.
2015-07-28 Niibe Yutaka <gniibe@fsij.org> 2015-07-28 Niibe Yutaka <gniibe@fsij.org>
* example-cdc/usb_stm32f103.c: Update from Gnuk. * example-cdc/usb_stm32f103.c: Update from Gnuk.

4
board/board-cq-starm.h
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@@ -1,7 +1,6 @@
#define BOARD_NAME "CQ STARM" #define BOARD_NAME "CQ STARM"
#define BOARD_ID 0xc5480875 #define BOARD_ID 0xc5480875
#define FLASH_PAGE_SIZE 1024
#define STM32F10X_MD /* Medium-density device */ #define STM32F10X_MD /* Medium-density device */
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
@@ -10,8 +9,7 @@
#define GPIO_LED_BASE GPIOC_BASE #define GPIO_LED_BASE GPIOC_BASE
#define GPIO_LED_SET_TO_EMIT 6 #define GPIO_LED_SET_TO_EMIT 6
#undef GPIO_USB_BASE #undef GPIO_USB_BASE /* No external DISCONNECT/RENUM circuit. */
#undef GPIO_USB_CLEAR_TO_ENABLE
#define GPIO_OTHER_BASE GPIOA_BASE #define GPIO_OTHER_BASE GPIOA_BASE
/* /*

2
board/board-fsm-55.h
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@@ -9,8 +9,6 @@
/* __ARM_ARCH_6M__ */ /* __ARM_ARCH_6M__ */
#define FLASH_PAGE_SIZE 1024
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 12 #define STM32_PLLMUL_VALUE 12
#define STM32_HSICLK 8000000 #define STM32_HSICLK 8000000

1
board/board-fst-01-00.h
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@@ -1,7 +1,6 @@
#define BOARD_NAME "FST-01-00" #define BOARD_NAME "FST-01-00"
#define BOARD_ID 0x613870a9 #define BOARD_ID 0x613870a9
#define FLASH_PAGE_SIZE 1024
#define STM32F10X_MD /* Medium-density device */ #define STM32F10X_MD /* Medium-density device */
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1

45
board/board-fst-01.h
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@@ -2,7 +2,6 @@
#define BOARD_ID 0x696886af #define BOARD_ID 0x696886af
/* echo -n "FST-01" | sha256sum | sed -e 's/^.*\(........\) -$/\1/' */ /* echo -n "FST-01" | sha256sum | sed -e 's/^.*\(........\) -$/\1/' */
#define FLASH_PAGE_SIZE 1024
#define STM32F10X_MD /* Medium-density device */ #define STM32F10X_MD /* Medium-density device */
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
@@ -15,19 +14,6 @@
#define GPIO_USB_SET_TO_ENABLE 10 #define GPIO_USB_SET_TO_ENABLE 10
#undef GPIO_OTHER_BASE #undef GPIO_OTHER_BASE
/* For pin-cir settings of Gnuk */
#define TIMx TIM2
#define INTR_REQ_TIM TIM2_IRQ
#define AFIO_EXTICR_INDEX 0
#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA
#define EXTI_PR EXTI_PR_PR2
#define EXTI_IMR EXTI_IMR_MR2
#define EXTI_FTSR_TR EXTI_FTSR_TR2
#define INTR_REQ_EXTI EXTI2_IRQ
#define ENABLE_RCC_APB1
#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM2EN
#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM2RST
/* /*
* Port A setup. * Port A setup.
* PA0 - input with pull-up (TIM2_CH1): AN0 for NeuG * PA0 - input with pull-up (TIM2_CH1): AN0 for NeuG
@@ -65,3 +51,34 @@
#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN) #define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST) #define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
/*
* Board specific information other than clock and GPIO initial
* setting should not be in board-*.h, but each driver should include
* information by itself.
*
* Please see NeuG's ADC driver how board specific handling is done.
*
* Given the situation of Chopstx's boards support, which is not that
* huge, this works well. If scalability and flexibility will matter,
* we will need something like device tree in which boot process can
* pass information to application program.
*
* Following constants are here, because experimental CIR driver is
* written before this design decision of Chopstx.
*
* Those will be removed soon, once such an driver will be improved
* in new style.
*/
/* For pin-cir settings of Gnuk */
#define TIMx TIM2
#define INTR_REQ_TIM TIM2_IRQ
#define AFIO_EXTICR_INDEX 0
#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR1_EXTI2_PA
#define EXTI_PR EXTI_PR_PR2
#define EXTI_IMR EXTI_IMR_MR2
#define EXTI_FTSR_TR EXTI_FTSR_TR2
#define INTR_REQ_EXTI EXTI2_IRQ
#define ENABLE_RCC_APB1
#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM2EN
#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM2RST

1
board/board-maple-mini.h
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@@ -1,7 +1,6 @@
#define BOARD_NAME "Maple Mini" #define BOARD_NAME "Maple Mini"
#define BOARD_ID 0x7a445272 #define BOARD_ID 0x7a445272
#define FLASH_PAGE_SIZE 1024
#define STM32F10X_MD /* Medium-density device */ #define STM32F10X_MD /* Medium-density device */
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1

1
board/board-olimex-stm32-h103.h
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@@ -1,7 +1,6 @@
#define BOARD_NAME "Olimex STM32-H103" #define BOARD_NAME "Olimex STM32-H103"
#define BOARD_ID 0xf92bb594 #define BOARD_ID 0xf92bb594
#define FLASH_PAGE_SIZE 1024
#define STM32F10X_MD /* Medium-density device */ #define STM32F10X_MD /* Medium-density device */
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1

33
board/board-st-dongle.h Normal file
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@@ -0,0 +1,33 @@
#define BOARD_NAME "ST Dongle"
/* echo -n "ST Dongle" | shasum -a 256 | sed -e 's/^.*\(........\) -$/\1/' */
#define BOARD_ID 0x2cd4e471
#define STM32F10X_MD /* Medium-density device */
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 9
#define STM32_HSECLK 8000000
#define GPIO_LED_BASE GPIOA_BASE
#define GPIO_LED_SET_TO_EMIT 9
#define GPIO_USB_BASE GPIOA_BASE
#define GPIO_USB_SET_TO_ENABLE 15
#undef GPIO_OTHER_BASE
/*
* Port A setup.
* PA0 - input with pull-up. AN0
* PA1 - input with pull-up. AN1
* PA9 - Push pull output 50MHz (LED 1:ON 0:OFF)
* PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM)
* PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP)
* PA15 - Push pull output 50MHz (USB 1:ON 0:OFF)
* ------------------------ Default
* PAx - input with pull-up
*/
#define VAL_GPIO_LED_ODR 0xFFFFE7FF
#define VAL_GPIO_LED_CRL 0x88888888 /* PA7...PA0 */
#define VAL_GPIO_LED_CRH 0x38811838 /* PA15...PA8 */
#define RCC_ENR_IOP_EN RCC_APB2ENR_IOPAEN
#define RCC_RSTR_IOP_RST RCC_APB2RSTR_IOPARST

1
board/board-stbee-mini.h
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@@ -1,7 +1,6 @@
#define BOARD_NAME "STBee Mini" #define BOARD_NAME "STBee Mini"
#define BOARD_ID 0x1f341961 #define BOARD_ID 0x1f341961
#define FLASH_PAGE_SIZE 1024
#define STM32F10X_MD /* Medium-density device */ #define STM32F10X_MD /* Medium-density device */
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1

2
board/board-stbee.h
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@@ -1,8 +1,6 @@
#define BOARD_NAME "STBee" #define BOARD_NAME "STBee"
#define BOARD_ID 0x945c37e8 #define BOARD_ID 0x945c37e8
#define FLASH_PAGE_SIZE 2048
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 6 #define STM32_PLLMUL_VALUE 6
#define STM32_HSECLK 12000000 #define STM32_HSECLK 12000000

2
board/board-stm32-primer2.h
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@@ -1,8 +1,6 @@
#define BOARD_NAME "STM32 Primer2" #define BOARD_NAME "STM32 Primer2"
#define BOARD_ID 0x21e5798d #define BOARD_ID 0x21e5798d
#define FLASH_PAGE_SIZE 2048
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 6 #define STM32_PLLMUL_VALUE 6
#define STM32_HSECLK 12000000 #define STM32_HSECLK 12000000

2
board/board-stm32f0-discovery.h
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@@ -9,8 +9,6 @@
/* __ARM_ARCH_6M__ */ /* __ARM_ARCH_6M__ */
#define FLASH_PAGE_SIZE 1024
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 12 #define STM32_PLLMUL_VALUE 12
#define STM32_HSICLK 8000000 #define STM32_HSICLK 8000000

35
board/board-stm8s-discovery.h
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@@ -1,7 +1,6 @@
#define BOARD_NAME "STM8S Discovery" #define BOARD_NAME "STM8S Discovery"
#define BOARD_ID 0x2f0976bb #define BOARD_ID 0x2f0976bb
#define FLASH_PAGE_SIZE 1024
#define STM32F10X_MD /* Medium-density device */ #define STM32F10X_MD /* Medium-density device */
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
@@ -10,25 +9,9 @@
#define GPIO_LED_BASE GPIOA_BASE #define GPIO_LED_BASE GPIOA_BASE
#define GPIO_LED_SET_TO_EMIT 8 #define GPIO_LED_SET_TO_EMIT 8
#undef GPIO_USB_BASE #undef GPIO_USB_BASE /* No external DISCONNECT/RENUM circuit. */
#undef GPIO_USB_CLEAR_TO_ENABLE
#define GPIO_OTHER_BASE GPIOB_BASE #define GPIO_OTHER_BASE GPIOB_BASE
/* For pin-cir settings of Gnuk */
#define TIMx TIM3
#define INTR_REQ_TIM TIM3_IRQ
#define AFIO_EXTICR_INDEX 1
#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR2_EXTI5_PB
#define EXTI_PR EXTI_PR_PR5
#define EXTI_IMR EXTI_IMR_MR5
#define EXTI_FTSR_TR EXTI_FTSR_TR5
#define INTR_REQ_EXTI EXTI9_5_IRQ
#define ENABLE_RCC_APB1
#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM3EN
#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM3RST
#define AFIO_MAPR_SOMETHING AFIO_MAPR_TIM3_REMAP_PARTIALREMAP
/* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */
/* /*
* Port A setup. * Port A setup.
* PA0 - input with pull-up. AN0 * PA0 - input with pull-up. AN0
@@ -58,3 +41,19 @@
#define VAL_GPIO_OTHER_ODR 0xFFFFFFFE #define VAL_GPIO_OTHER_ODR 0xFFFFFFFE
#define VAL_GPIO_OTHER_CRL 0x88888888 /* PB7...PB0 */ #define VAL_GPIO_OTHER_CRL 0x88888888 /* PB7...PB0 */
#define VAL_GPIO_OTHER_CRH 0x88888888 /* PB15...PB8 */ #define VAL_GPIO_OTHER_CRH 0x88888888 /* PB15...PB8 */
/* For pin-cir settings of Gnuk */
#define TIMx TIM3
#define INTR_REQ_TIM TIM3_IRQ
#define AFIO_EXTICR_INDEX 1
#define AFIO_EXTICR1_EXTIx_Py AFIO_EXTICR2_EXTI5_PB
#define EXTI_PR EXTI_PR_PR5
#define EXTI_IMR EXTI_IMR_MR5
#define EXTI_FTSR_TR EXTI_FTSR_TR5
#define INTR_REQ_EXTI EXTI9_5_IRQ
#define ENABLE_RCC_APB1
#define RCC_APBnENR_TIMxEN RCC_APB1ENR_TIM3EN
#define RCC_APBnRSTR_TIMxRST RCC_APB1RSTR_TIM3RST
#define AFIO_MAPR_SOMETHING AFIO_MAPR_TIM3_REMAP_PARTIALREMAP
/* Remap (PB4, PB5) -> (TIM3_CH1, TIM3_CH2) */