Update for STM32F103
This commit is contained in:
NIIBE Yutaka
@@ -1,5 +1,8 @@
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2016-05-30 NIIBE Yutaka <gniibe@fsij.org>
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* mcu/adc-stm32f103.c: New from NeuG.
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* mcu/stm32f103.h: New from NeuG.
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* example-cdc: Update.
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2016-05-30 NIIBE Yutaka <gniibe@fsij.org>
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329
mcu/adc-stm32f103.c
Normal file
329
mcu/adc-stm32f103.c
Normal file
@@ -0,0 +1,329 @@
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/*
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* adc_stm32f103.c - ADC driver for STM32F103
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* In this ADC driver, there are NeuG specific parts.
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* You need to modify to use this as generic ADC driver.
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*
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* Copyright (C) 2011, 2012, 2013, 2015, 2016
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* Free Software Initiative of Japan
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* Author: NIIBE Yutaka <gniibe@fsij.org>
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*
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* This file is a part of NeuG, a True Random Number Generator
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* implementation based on quantization error of ADC (for STM32F103).
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*
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* NeuG is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* NeuG is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <chopstx.h>
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#include <mcu/stm32f103.h>
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#include "adc.h"
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define ADC_SMPR1_SMP_VREF(n) ((n) << 21)
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#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18)
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#define ADC_SMPR1_SMP_AN10(n) ((n) << 0)
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#define ADC_SMPR1_SMP_AN11(n) ((n) << 3)
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#define ADC_SMPR2_SMP_AN0(n) ((n) << 0)
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#define ADC_SMPR2_SMP_AN1(n) ((n) << 3)
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#define ADC_SMPR2_SMP_AN2(n) ((n) << 6)
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#define ADC_SMPR2_SMP_AN9(n) ((n) << 27)
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#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
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#define ADC_SQR3_SQ1_N(n) ((n) << 0)
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#define ADC_SQR3_SQ2_N(n) ((n) << 5)
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#define ADC_SQR3_SQ3_N(n) ((n) << 10)
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#define ADC_SQR3_SQ4_N(n) ((n) << 15)
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#define ADC_SAMPLE_1P5 0
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#define ADC_CHANNEL_IN0 0
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#define ADC_CHANNEL_IN1 1
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#define ADC_CHANNEL_IN2 2
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#define ADC_CHANNEL_IN9 9
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#define ADC_CHANNEL_IN10 10
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#define ADC_CHANNEL_IN11 11
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#define ADC_CHANNEL_SENSOR 16
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#define ADC_CHANNEL_VREFINT 17
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#define DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
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#define DELIBARATELY_DO_IT_WRONG_START_STOP
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#ifdef DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME
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#define ADC_SAMPLE_VREF ADC_SAMPLE_1P5
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#define ADC_SAMPLE_SENSOR ADC_SAMPLE_1P5
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#else
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#define ADC_SAMPLE_VREF ADC_SAMPLE_239P5
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#define ADC_SAMPLE_SENSOR ADC_SAMPLE_239P5
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#endif
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#define NEUG_DMA_CHANNEL STM32_DMA1_STREAM1
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#define NEUG_DMA_MODE \
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( STM32_DMA_CR_PL (STM32_ADC_ADC1_DMA_PRIORITY) \
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| STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD \
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| STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE \
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| STM32_DMA_CR_TEIE )
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#define NEUG_ADC_SETTING1_SMPR1 ADC_SMPR1_SMP_VREF(ADC_SAMPLE_VREF) \
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| ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_SENSOR)
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#define NEUG_ADC_SETTING1_SMPR2 0
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#define NEUG_ADC_SETTING1_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_VREFINT) \
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| ADC_SQR3_SQ2_N(ADC_CHANNEL_SENSOR) \
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| ADC_SQR3_SQ3_N(ADC_CHANNEL_SENSOR) \
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| ADC_SQR3_SQ4_N(ADC_CHANNEL_VREFINT)
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#define NEUG_ADC_SETTING1_NUM_CHANNELS 4
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/*
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* ADC finish interrupt
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*/
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#define INTR_REQ_DMA1_Channel1 11
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static chopstx_intr_t adc_intr;
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/*
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* Do calibration for both of ADCs.
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*/
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int
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adc_init (void)
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{
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RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
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RCC->APB2RSTR = (RCC_APB2RSTR_ADC1RST | RCC_APB2RSTR_ADC2RST);
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RCC->APB2RSTR = 0;
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ADC1->CR1 = 0;
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ADC1->CR2 = ADC_CR2_ADON;
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ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
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while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
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;
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ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
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while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
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;
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ADC1->CR2 = 0;
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ADC2->CR1 = 0;
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ADC2->CR2 = ADC_CR2_ADON;
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ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
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while ((ADC2->CR2 & ADC_CR2_RSTCAL) != 0)
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;
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ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
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while ((ADC2->CR2 & ADC_CR2_CAL) != 0)
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;
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ADC2->CR2 = 0;
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RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
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chopstx_claim_irq (&adc_intr, INTR_REQ_DMA1_Channel1);
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return 0;
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}
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#include "board.h"
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#include "mcu/sys-stm32f103.h"
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#if defined(HAVE_SYS_H)
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# define SYS_BOARD_ID sys_board_id
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#else
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# define SYS_BOARD_ID BOARD_ID
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#endif
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static void
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get_adc_config (uint32_t config[4])
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{
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config[2] = ADC_SQR1_NUM_CH(2);
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switch (SYS_BOARD_ID)
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{
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case BOARD_ID_FST_01:
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config[0] = 0;
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config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
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| ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5);
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config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
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| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9);
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break;
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case BOARD_ID_OLIMEX_STM32_H103:
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case BOARD_ID_STBEE:
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config[0] = ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5)
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| ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5);
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config[1] = 0;
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config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10)
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| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11);
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break;
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case BOARD_ID_STBEE_MINI:
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config[0] = 0;
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config[1] = ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5)
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| ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5);
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config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1)
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| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2);
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break;
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case BOARD_ID_CQ_STARM:
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case BOARD_ID_FST_01_00:
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case BOARD_ID_MAPLE_MINI:
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case BOARD_ID_STM32_PRIMER2:
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case BOARD_ID_STM8S_DISCOVERY:
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case BOARD_ID_ST_DONGLE:
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case BOARD_ID_ST_NUCLEO_F103:
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case BOARD_ID_NITROKEY_START:
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default:
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config[0] = 0;
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config[1] = ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5)
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| ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5);
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config[3] = ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0)
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| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN1);
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break;
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}
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}
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void
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adc_start (void)
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{
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uint32_t config[4];
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get_adc_config (config);
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/* Use DMA channel 1. */
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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DMA1_Channel1->CCR = STM32_DMA_CCR_RESET_VALUE;
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DMA1->IFCR = 0xffffffff;
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RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
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ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
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| ADC_CR1_SCAN);
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ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
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| ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
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ADC1->SMPR1 = NEUG_ADC_SETTING1_SMPR1;
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ADC1->SMPR2 = NEUG_ADC_SETTING1_SMPR2;
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ADC1->SQR1 = ADC_SQR1_NUM_CH(NEUG_ADC_SETTING1_NUM_CHANNELS);
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ADC1->SQR2 = 0;
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ADC1->SQR3 = NEUG_ADC_SETTING1_SQR3;
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ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0
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| ADC_CR1_SCAN);
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ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
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ADC2->SMPR1 = config[0];
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ADC2->SMPR2 = config[1];
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ADC2->SQR1 = config[2];
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ADC2->SQR2 = 0;
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ADC2->SQR3 = config[3];
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#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
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/*
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* We could just let ADC run continuously always and only enable DMA
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* to receive stable data from ADC. But our purpose is not to get
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* correct data but noise. In fact, we can get more noise when we
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* start/stop ADC each time.
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*/
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ADC2->CR2 = 0;
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ADC1->CR2 = 0;
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#else
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/* Start conversion. */
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ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
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ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
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| ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
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#endif
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}
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uint32_t adc_buf[64];
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void
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adc_start_conversion (int offset, int count)
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{
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DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR; /* SetPeripheral */
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DMA1_Channel1->CMAR = (uint32_t)&adc_buf[offset]; /* SetMemory0 */
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DMA1_Channel1->CNDTR = count; /* Counter */
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DMA1_Channel1->CCR = NEUG_DMA_MODE | DMA_CCR1_EN; /* Mode */
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#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
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/* Power on */
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ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
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ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
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| ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
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/*
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* Start conversion. tSTAB is 1uS, but we don't follow the spec, to
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* get more noise.
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*/
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ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON;
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ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART
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| ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON);
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#endif
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}
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static void adc_stop_conversion (void)
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{
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DMA1_Channel1->CCR &= ~DMA_CCR1_EN;
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#ifdef DELIBARATELY_DO_IT_WRONG_START_STOP
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ADC2->CR2 = 0;
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ADC1->CR2 = 0;
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#endif
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}
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void
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adc_stop (void)
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{
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ADC1->CR1 = 0;
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ADC1->CR2 = 0;
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ADC2->CR1 = 0;
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ADC2->CR2 = 0;
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RCC->AHBENR &= ~RCC_AHBENR_DMA1EN;
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RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN);
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}
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static uint32_t adc_err;
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/*
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* Return 0 on success.
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* Return 1 on error.
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*/
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int
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adc_wait_completion (void)
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{
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uint32_t flags;
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while (1)
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{
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chopstx_poll (NULL, 1, &adc_intr);
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flags = DMA1->ISR & STM32_DMA_ISR_MASK; /* Channel 1 interrupt cause. */
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/*
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* Clear interrupt cause of channel 1.
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*
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* Note that CGIFx=0, as CGIFx=1 clears all of GIF, HTIF, TCIF
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* and TEIF.
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*/
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DMA1->IFCR = (flags & ~1);
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if ((flags & STM32_DMA_ISR_TEIF) != 0) /* DMA errors */
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{
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/* Should never happened. If any, it's coding error. */
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/* Access an unmapped address space or alignment violation. */
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adc_err++;
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adc_stop_conversion ();
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return 1;
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}
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else if ((flags & STM32_DMA_ISR_TCIF) != 0) /* Transfer complete */
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{
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adc_stop_conversion ();
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return 0;
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}
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}
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}
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204
mcu/stm32f103.h
Normal file
204
mcu/stm32f103.h
Normal file
@@ -0,0 +1,204 @@
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#define PERIPH_BASE 0x40000000
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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#define RCC_APB2RSTR_ADC1RST 0x00000200
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#define RCC_APB2RSTR_ADC2RST 0x00000400
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struct RCC {
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volatile uint32_t CR;
|
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volatile uint32_t CFGR;
|
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volatile uint32_t CIR;
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volatile uint32_t APB2RSTR;
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volatile uint32_t APB1RSTR;
|
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volatile uint32_t AHBENR;
|
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volatile uint32_t APB2ENR;
|
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volatile uint32_t APB1ENR;
|
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volatile uint32_t BDCR;
|
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volatile uint32_t CSR;
|
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};
|
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|
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#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
|
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#define RCC_AHBENR_DMA1EN 0x00000001
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#define RCC_AHBENR_CRCEN 0x00000040
|
||||
|
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#define RCC_APB2ENR_ADC1EN 0x00000200
|
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#define RCC_APB2ENR_ADC2EN 0x00000400
|
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|
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#define CRC_CR_RESET 0x00000001
|
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|
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struct CRC {
|
||||
volatile uint32_t DR;
|
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volatile uint8_t IDR;
|
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uint8_t RESERVED0;
|
||||
uint16_t RESERVED1;
|
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volatile uint32_t CR;
|
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};
|
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|
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#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
|
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static struct CRC *const CRC = ((struct CRC *const)CRC_BASE);
|
||||
|
||||
|
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struct ADC {
|
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volatile uint32_t SR;
|
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volatile uint32_t CR1;
|
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volatile uint32_t CR2;
|
||||
volatile uint32_t SMPR1;
|
||||
volatile uint32_t SMPR2;
|
||||
volatile uint32_t JOFR1;
|
||||
volatile uint32_t JOFR2;
|
||||
volatile uint32_t JOFR3;
|
||||
volatile uint32_t JOFR4;
|
||||
volatile uint32_t HTR;
|
||||
volatile uint32_t LTR;
|
||||
volatile uint32_t SQR1;
|
||||
volatile uint32_t SQR2;
|
||||
volatile uint32_t SQR3;
|
||||
volatile uint32_t JSQR;
|
||||
volatile uint32_t JDR1;
|
||||
volatile uint32_t JDR2;
|
||||
volatile uint32_t JDR3;
|
||||
volatile uint32_t JDR4;
|
||||
volatile uint32_t DR;
|
||||
};
|
||||
|
||||
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
|
||||
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
|
||||
|
||||
static struct ADC *const ADC1 = (struct ADC *const)ADC1_BASE;
|
||||
static struct ADC *const ADC2 = (struct ADC *const)ADC2_BASE;
|
||||
|
||||
#define ADC_CR1_DUALMOD_0 0x00010000
|
||||
#define ADC_CR1_DUALMOD_1 0x00020000
|
||||
#define ADC_CR1_DUALMOD_2 0x00040000
|
||||
#define ADC_CR1_DUALMOD_3 0x00080000
|
||||
|
||||
#define ADC_CR1_SCAN 0x00000100
|
||||
|
||||
#define ADC_CR2_ADON 0x00000001
|
||||
#define ADC_CR2_CONT 0x00000002
|
||||
#define ADC_CR2_CAL 0x00000004
|
||||
#define ADC_CR2_RSTCAL 0x00000008
|
||||
#define ADC_CR2_DMA 0x00000100
|
||||
#define ADC_CR2_ALIGN 0x00000800
|
||||
#define ADC_CR2_EXTSEL 0x000E0000
|
||||
#define ADC_CR2_EXTSEL_0 0x00020000
|
||||
#define ADC_CR2_EXTSEL_1 0x00040000
|
||||
#define ADC_CR2_EXTSEL_2 0x00080000
|
||||
#define ADC_CR2_EXTTRIG 0x00100000
|
||||
#define ADC_CR2_SWSTART 0x00400000
|
||||
#define ADC_CR2_TSVREFE 0x00800000
|
||||
|
||||
struct DMA_Channel {
|
||||
volatile uint32_t CCR;
|
||||
volatile uint32_t CNDTR;
|
||||
volatile uint32_t CPAR;
|
||||
volatile uint32_t CMAR;
|
||||
};
|
||||
|
||||
struct DMA {
|
||||
volatile uint32_t ISR;
|
||||
volatile uint32_t IFCR;
|
||||
};
|
||||
|
||||
#define STM32_DMA_CR_MINC DMA_CCR1_MINC
|
||||
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1
|
||||
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1
|
||||
#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE
|
||||
#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE
|
||||
#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE
|
||||
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
|
||||
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
|
||||
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
|
||||
|
||||
#define STM32_DMA_ISR_MASK 0x0F
|
||||
#define STM32_DMA_CCR_RESET_VALUE 0x00000000
|
||||
#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL
|
||||
#define STM32_DMA_CR_PL(n) ((n) << 12)
|
||||
|
||||
#define DMA_CCR1_EN 0x00000001
|
||||
#define DMA_CCR1_TCIE 0x00000002
|
||||
#define DMA_CCR1_HTIE 0x00000004
|
||||
#define DMA_CCR1_TEIE 0x00000008
|
||||
#define DMA_CCR1_DIR 0x00000010
|
||||
#define DMA_CCR1_CIRC 0x00000020
|
||||
#define DMA_CCR1_PINC 0x00000040
|
||||
#define DMA_CCR1_MINC 0x00000080
|
||||
#define DMA_CCR1_PSIZE 0x00000300
|
||||
#define DMA_CCR1_PSIZE_0 0x00000100
|
||||
#define DMA_CCR1_PSIZE_1 0x00000200
|
||||
#define DMA_CCR1_MSIZE 0x00000C00
|
||||
#define DMA_CCR1_MSIZE_0 0x00000400
|
||||
#define DMA_CCR1_MSIZE_1 0x00000800
|
||||
#define DMA_CCR1_PL 0x00003000
|
||||
#define DMA_CCR1_PL_0 0x00001000
|
||||
#define DMA_CCR1_PL_1 0x00002000
|
||||
#define DMA_CCR1_MEM2MEM 0x00004000
|
||||
|
||||
#define DMA_ISR_GIF1 0x00000001
|
||||
#define DMA_ISR_TCIF1 0x00000002
|
||||
#define DMA_ISR_HTIF1 0x00000004
|
||||
#define DMA_ISR_TEIF1 0x00000008
|
||||
#define DMA_ISR_GIF2 0x00000010
|
||||
#define DMA_ISR_TCIF2 0x00000020
|
||||
#define DMA_ISR_HTIF2 0x00000040
|
||||
#define DMA_ISR_TEIF2 0x00000080
|
||||
#define DMA_ISR_GIF3 0x00000100
|
||||
#define DMA_ISR_TCIF3 0x00000200
|
||||
#define DMA_ISR_HTIF3 0x00000400
|
||||
#define DMA_ISR_TEIF3 0x00000800
|
||||
#define DMA_ISR_GIF4 0x00001000
|
||||
#define DMA_ISR_TCIF4 0x00002000
|
||||
#define DMA_ISR_HTIF4 0x00004000
|
||||
#define DMA_ISR_TEIF4 0x00008000
|
||||
#define DMA_ISR_GIF5 0x00010000
|
||||
#define DMA_ISR_TCIF5 0x00020000
|
||||
#define DMA_ISR_HTIF5 0x00040000
|
||||
#define DMA_ISR_TEIF5 0x00080000
|
||||
#define DMA_ISR_GIF6 0x00100000
|
||||
#define DMA_ISR_TCIF6 0x00200000
|
||||
#define DMA_ISR_HTIF6 0x00400000
|
||||
#define DMA_ISR_TEIF6 0x00800000
|
||||
#define DMA_ISR_GIF7 0x01000000
|
||||
#define DMA_ISR_TCIF7 0x02000000
|
||||
#define DMA_ISR_HTIF7 0x04000000
|
||||
#define DMA_ISR_TEIF7 0x08000000
|
||||
|
||||
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
|
||||
static struct DMA *const DMA1 = (struct DMA *const)DMA1_BASE;
|
||||
|
||||
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
|
||||
static struct DMA_Channel *const DMA1_Channel1 =
|
||||
(struct DMA_Channel *const)DMA1_Channel1_BASE;
|
||||
|
||||
/* System Control Block */
|
||||
struct SCB
|
||||
{
|
||||
volatile uint32_t CPUID;
|
||||
volatile uint32_t ICSR;
|
||||
volatile uint32_t VTOR;
|
||||
volatile uint32_t AIRCR;
|
||||
volatile uint32_t SCR;
|
||||
volatile uint32_t CCR;
|
||||
volatile uint8_t SHP[12];
|
||||
volatile uint32_t SHCSR;
|
||||
volatile uint32_t CFSR;
|
||||
volatile uint32_t HFSR;
|
||||
volatile uint32_t DFSR;
|
||||
volatile uint32_t MMFAR;
|
||||
volatile uint32_t BFAR;
|
||||
volatile uint32_t AFSR;
|
||||
volatile uint32_t PFR[2];
|
||||
volatile uint32_t DFR;
|
||||
volatile uint32_t ADR;
|
||||
volatile uint32_t MMFR[4];
|
||||
volatile uint32_t ISAR[5];
|
||||
uint32_t RESERVED0[5];
|
||||
volatile uint32_t CPACR;
|
||||
};
|
||||
|
||||
#define SCS_BASE 0xE000E000
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00)
|
||||
static struct SCB *const SCB = (struct SCB *const)SCB_BASE;
|
||||
Reference in New Issue
Block a user