From a362f32cdd252ad2a1d8a56a7f8d41d6b276da1b Mon Sep 17 00:00:00 2001 From: NIIBE Yutaka Date: Fri, 17 Nov 2017 14:30:55 +0900 Subject: [PATCH] Factor out RCC definition into stm32.h (common for STM32F0/STM32F1). --- ChangeLog | 3 ++ contrib/adc-stm32f103.c | 1 + mcu/chx-stm32f0.c | 1 + mcu/clk_gpio_init-stm32.c | 81 +----------------------------- mcu/stm32.h | 100 ++++++++++++++++++++++++++++++++++++++ mcu/stm32f103.h | 44 ----------------- 6 files changed, 107 insertions(+), 123 deletions(-) diff --git a/ChangeLog b/ChangeLog index f98980c..c4d5a9a 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,8 @@ 2017-11-17 NIIBE Yutaka + * mcu/stm32f103.h (RCC), clk_gpio_init-stm32.c (RCC): Move to... + * mcu/stm32.h (RCC): ... this header file. + * example-fsm-55: Update for new sleep API. * rules.mk (CSRC): Add mcu/chx-$(CHIP).c. diff --git a/contrib/adc-stm32f103.c b/contrib/adc-stm32f103.c index a44942f..32f7e62 100644 --- a/contrib/adc-stm32f103.c +++ b/contrib/adc-stm32f103.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include "adc.h" diff --git a/mcu/chx-stm32f0.c b/mcu/chx-stm32f0.c index 492acef..00b77ee 100644 --- a/mcu/chx-stm32f0.c +++ b/mcu/chx-stm32f0.c @@ -1,5 +1,6 @@ #include #include +#define MCU_STM32F0 #include extern int chx_allow_sleep; diff --git a/mcu/clk_gpio_init-stm32.c b/mcu/clk_gpio_init-stm32.c index 08bd59b..6d50edd 100644 --- a/mcu/clk_gpio_init-stm32.c +++ b/mcu/clk_gpio_init-stm32.c @@ -26,6 +26,8 @@ * */ +#include + #define STM32_SW_HSI (0 << 0) #define STM32_SW_PLL (2 << 0) #define STM32_PLLSRC_HSI (0 << 16) @@ -74,85 +76,6 @@ #define STM32_HCLK (STM32_SYSCLK / 1) -#define PERIPH_BASE 0x40000000 -#define APBPERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) - -struct RCC { - volatile uint32_t CR; - volatile uint32_t CFGR; - volatile uint32_t CIR; - volatile uint32_t APB2RSTR; - volatile uint32_t APB1RSTR; - volatile uint32_t AHBENR; - volatile uint32_t APB2ENR; - volatile uint32_t APB1ENR; - volatile uint32_t BDCR; - volatile uint32_t CSR; -#if defined(MCU_STM32F0) - volatile uint32_t AHBRSTR; - volatile uint32_t CFGR2; - volatile uint32_t CFGR3; - volatile uint32_t CR2; -#endif -}; - -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -static struct RCC *const RCC = (struct RCC *)RCC_BASE; - -#define RCC_APB1ENR_USBEN 0x00800000 -#define RCC_APB1RSTR_USBRST 0x00800000 - -#define RCC_CR_HSION 0x00000001 -#define RCC_CR_HSIRDY 0x00000002 -#define RCC_CR_HSITRIM 0x000000F8 -#define RCC_CR_HSEON 0x00010000 -#define RCC_CR_HSERDY 0x00020000 -#define RCC_CR_PLLON 0x01000000 -#define RCC_CR_PLLRDY 0x02000000 - -#define RCC_CFGR_SWS 0x0000000C -#define RCC_CFGR_SWS_HSI 0x00000000 - -#define RCC_AHBENR_CRCEN 0x0040 - -#if defined(MCU_STM32F0) -#define RCC_AHBRSTR_IOPARST 0x00020000 -#define RCC_AHBRSTR_IOPBRST 0x00040000 -#define RCC_AHBRSTR_IOPCRST 0x00080000 -#define RCC_AHBRSTR_IOPDRST 0x00100000 -#define RCC_AHBRSTR_IOPFRST 0x00400000 - -#define RCC_AHBENR_IOPAEN 0x00020000 -#define RCC_AHBENR_IOPBEN 0x00040000 -#define RCC_AHBENR_IOPCEN 0x00080000 -#define RCC_AHBENR_IOPDEN 0x00100000 -#define RCC_AHBENR_IOPFEN 0x00400000 - -#define RCC_APB2RSTR_SYSCFGRST 0x00000001 -#define RCC_APB2ENR_SYSCFGEN 0x00000001 -#else -#define RCC_APB2RSTR_AFIORST 0x00000001 -#define RCC_APB2RSTR_IOPARST 0x00000004 -#define RCC_APB2RSTR_IOPBRST 0x00000008 -#define RCC_APB2RSTR_IOPCRST 0x00000010 -#define RCC_APB2RSTR_IOPDRST 0x00000020 -#define RCC_APB2RSTR_IOPERST 0x00000040 -#define RCC_APB2RSTR_IOPFRST 0x00000080 -#define RCC_APB2RSTR_IOPGRST 0x00000100 - -#define RCC_APB2ENR_AFIOEN 0x00000001 -#define RCC_APB2ENR_IOPAEN 0x00000004 -#define RCC_APB2ENR_IOPBEN 0x00000008 -#define RCC_APB2ENR_IOPCEN 0x00000010 -#define RCC_APB2ENR_IOPDEN 0x00000020 -#define RCC_APB2ENR_IOPEEN 0x00000040 -#define RCC_APB2ENR_IOPFEN 0x00000080 -#define RCC_APB2ENR_IOPGEN 0x00000100 -#endif - #if defined(MCU_STM32F0) struct SYSCFG { volatile uint32_t CFGR1; diff --git a/mcu/stm32.h b/mcu/stm32.h index d68189c..4d21918 100644 --- a/mcu/stm32.h +++ b/mcu/stm32.h @@ -1,3 +1,103 @@ +#define PERIPH_BASE 0x40000000 +#define APBPERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) + +struct RCC { + volatile uint32_t CR; + volatile uint32_t CFGR; + volatile uint32_t CIR; + volatile uint32_t APB2RSTR; + volatile uint32_t APB1RSTR; + volatile uint32_t AHBENR; + volatile uint32_t APB2ENR; + volatile uint32_t APB1ENR; + volatile uint32_t BDCR; + volatile uint32_t CSR; +#if defined(MCU_STM32F0) + volatile uint32_t AHBRSTR; + volatile uint32_t CFGR2; + volatile uint32_t CFGR3; + volatile uint32_t CR2; +#endif +}; + +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +static struct RCC *const RCC = (struct RCC *)RCC_BASE; + +#define RCC_APB1ENR_USBEN 0x00800000 +#define RCC_APB1RSTR_USBRST 0x00800000 + +#define RCC_CR_HSION 0x00000001 +#define RCC_CR_HSIRDY 0x00000002 +#define RCC_CR_HSITRIM 0x000000F8 +#define RCC_CR_HSEON 0x00010000 +#define RCC_CR_HSERDY 0x00020000 +#define RCC_CR_PLLON 0x01000000 +#define RCC_CR_PLLRDY 0x02000000 + +#define RCC_CFGR_SWS 0x0000000C +#define RCC_CFGR_SWS_HSI 0x00000000 + +#define RCC_AHBENR_DMA1EN 0x00000001 +#define RCC_AHBENR_CRCEN 0x00000040 + +#if defined(MCU_STM32F0) +#define RCC_AHBRSTR_IOPARST 0x00020000 +#define RCC_AHBRSTR_IOPBRST 0x00040000 +#define RCC_AHBRSTR_IOPCRST 0x00080000 +#define RCC_AHBRSTR_IOPDRST 0x00100000 +#define RCC_AHBRSTR_IOPFRST 0x00400000 + +#define RCC_AHBENR_IOPAEN 0x00020000 +#define RCC_AHBENR_IOPBEN 0x00040000 +#define RCC_AHBENR_IOPCEN 0x00080000 +#define RCC_AHBENR_IOPDEN 0x00100000 +#define RCC_AHBENR_IOPFEN 0x00400000 + +#define RCC_APB2RSTR_SYSCFGRST 0x00000001 +#define RCC_APB2ENR_SYSCFGEN 0x00000001 +#else +#define RCC_APB2ENR_ADC1EN 0x00000200 +#define RCC_APB2ENR_ADC2EN 0x00000400 +#define RCC_APB2ENR_TIM1EN 0x00000800 +#define RCC_APB1ENR_TIM2EN 0x00000001 +#define RCC_APB1ENR_TIM3EN 0x00000002 +#define RCC_APB1ENR_TIM4EN 0x00000004 + +#define RCC_APB2RSTR_ADC1RST 0x00000200 +#define RCC_APB2RSTR_ADC2RST 0x00000400 +#define RCC_APB2RSTR_TIM1RST 0x00000800 +#define RCC_APB1RSTR_TIM2RST 0x00000001 +#define RCC_APB1RSTR_TIM3RST 0x00000002 +#define RCC_APB1RSTR_TIM4RST 0x00000004 + +#define RCC_APB2RSTR_AFIORST 0x00000001 +#define RCC_APB2RSTR_IOPARST 0x00000004 +#define RCC_APB2RSTR_IOPBRST 0x00000008 +#define RCC_APB2RSTR_IOPCRST 0x00000010 +#define RCC_APB2RSTR_IOPDRST 0x00000020 +#define RCC_APB2RSTR_IOPERST 0x00000040 +#define RCC_APB2RSTR_IOPFRST 0x00000080 +#define RCC_APB2RSTR_IOPGRST 0x00000100 + +#define RCC_APB2ENR_AFIOEN 0x00000001 +#define RCC_APB2ENR_IOPAEN 0x00000004 +#define RCC_APB2ENR_IOPBEN 0x00000008 +#define RCC_APB2ENR_IOPCEN 0x00000010 +#define RCC_APB2ENR_IOPDEN 0x00000020 +#define RCC_APB2ENR_IOPEEN 0x00000040 +#define RCC_APB2ENR_IOPFEN 0x00000080 +#define RCC_APB2ENR_IOPGEN 0x00000100 +#endif + +#define RCC_CFGR_SW_HCI (0 << 0) +#define RCC_CFGR_SW_PLL (2 << 0) +#define RCC_CFGR_SW_MASK (3 << 0) +#define RCC_CFGR_SWS 0x0000000C + + struct PWR { volatile uint32_t CR; diff --git a/mcu/stm32f103.h b/mcu/stm32f103.h index 989af91..1ab8efe 100644 --- a/mcu/stm32f103.h +++ b/mcu/stm32f103.h @@ -1,47 +1,3 @@ -#define PERIPH_BASE 0x40000000 -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -struct RCC { - volatile uint32_t CR; - volatile uint32_t CFGR; - volatile uint32_t CIR; - volatile uint32_t APB2RSTR; - volatile uint32_t APB1RSTR; - volatile uint32_t AHBENR; - volatile uint32_t APB2ENR; - volatile uint32_t APB1ENR; - volatile uint32_t BDCR; - volatile uint32_t CSR; -}; - -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -static struct RCC *const RCC = (struct RCC *)RCC_BASE; - -#define RCC_AHBENR_DMA1EN 0x00000001 -#define RCC_AHBENR_CRCEN 0x00000040 - -#define RCC_APB2ENR_ADC1EN 0x00000200 -#define RCC_APB2ENR_ADC2EN 0x00000400 -#define RCC_APB2ENR_TIM1EN 0x00000800 -#define RCC_APB1ENR_TIM2EN 0x00000001 -#define RCC_APB1ENR_TIM3EN 0x00000002 -#define RCC_APB1ENR_TIM4EN 0x00000004 - -#define RCC_APB2RSTR_ADC1RST 0x00000200 -#define RCC_APB2RSTR_ADC2RST 0x00000400 -#define RCC_APB2RSTR_TIM1RST 0x00000800 -#define RCC_APB1RSTR_TIM2RST 0x00000001 -#define RCC_APB1RSTR_TIM3RST 0x00000002 -#define RCC_APB1RSTR_TIM4RST 0x00000004 - -#define RCC_CFGR_SW_HCI (0 << 0) -#define RCC_CFGR_SW_PLL (2 << 0) -#define RCC_CFGR_SW_MASK (3 << 0) -#define RCC_CFGR_SWS 0x0000000C - - #define CRC_CR_RESET 0x00000001 struct CRC {