From 66b4eb3058b78632b0568ddb0944dc707016d6f8 Mon Sep 17 00:00:00 2001 From: NIIBE Yutaka Date: Fri, 17 Nov 2017 11:36:08 +0900 Subject: [PATCH] Update mcu/stm32f103.h. --- ChangeLog | 2 ++ mcu/stm32f103.h | 45 +++++++++++++++------------------------------ 2 files changed, 17 insertions(+), 30 deletions(-) diff --git a/ChangeLog b/ChangeLog index a70ffab..6cc92c0 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,7 @@ 2017-11-17 NIIBE Yutaka + * mcu/stm32f103.h (DBGMCU): New. + * mcu/cortex-m.h: New. * mcu/sys-stm32f0.c, mcu/sys-stm32f103.c: Use mcu/cortex-m.h. diff --git a/mcu/stm32f103.h b/mcu/stm32f103.h index a8bd20c..989af91 100644 --- a/mcu/stm32f103.h +++ b/mcu/stm32f103.h @@ -36,6 +36,12 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE; #define RCC_APB1RSTR_TIM3RST 0x00000002 #define RCC_APB1RSTR_TIM4RST 0x00000004 +#define RCC_CFGR_SW_HCI (0 << 0) +#define RCC_CFGR_SW_PLL (2 << 0) +#define RCC_CFGR_SW_MASK (3 << 0) +#define RCC_CFGR_SWS 0x0000000C + + #define CRC_CR_RESET 0x00000001 struct CRC { @@ -182,36 +188,6 @@ static struct DMA *const DMA1 = (struct DMA *)DMA1_BASE; static struct DMA_Channel *const DMA1_Channel1 = (struct DMA_Channel *)DMA1_Channel1_BASE; -/* System Control Block */ -struct SCB -{ - volatile uint32_t CPUID; - volatile uint32_t ICSR; - volatile uint32_t VTOR; - volatile uint32_t AIRCR; - volatile uint32_t SCR; - volatile uint32_t CCR; - volatile uint8_t SHP[12]; - volatile uint32_t SHCSR; - volatile uint32_t CFSR; - volatile uint32_t HFSR; - volatile uint32_t DFSR; - volatile uint32_t MMFAR; - volatile uint32_t BFAR; - volatile uint32_t AFSR; - volatile uint32_t PFR[2]; - volatile uint32_t DFR; - volatile uint32_t ADR; - volatile uint32_t MMFR[4]; - volatile uint32_t ISAR[5]; - uint32_t RESERVED0[5]; - volatile uint32_t CPACR; -}; - -#define SCS_BASE 0xE000E000 -#define SCB_BASE (SCS_BASE + 0x0D00) -static struct SCB *const SCB = (struct SCB *)SCB_BASE; - /* Timer */ struct TIM { @@ -698,3 +674,12 @@ static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE; #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800 #define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000 + + +struct DBGMCU { + volatile uint32_t CR; +}; + +#define DBGMCU_BASE 0xE0042004 +#define DBG_SLEEP 1 +static struct DBGMCU *const DBGMCU = (struct DBGMCU *)DBGMCU_BASE;