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Update for FSM-55

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This commit is contained in:
NIIBE Yutaka
2015-07-07 12:31:15 +09:00
parent 43bd3bcefd
commit 4dc10d6b18
6 changed files with 29 additions and 349 deletions
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8
ChangeLog
View File

@@ -1,3 +1,9 @@
2015-07-07 Niibe Yutaka <gniibe@fsij.org>
* example-fsm-55/sys.c: Include clk_gpio_init.c.
* board/board-stm32f0-discovery.h, board/board-fsm-55.h: Update.
* clk_gpio_init.c (gpio_init): Use VAL_GPIO_LED_*.
2015-06-29 Niibe Yutaka <gniibe@fsij.org> 2015-06-29 Niibe Yutaka <gniibe@fsij.org>
* board/board-cq-starm.h: New for CQ STARM. * board/board-cq-starm.h: New for CQ STARM.
@@ -19,6 +25,8 @@
Merge cortex-m0-support branch. Merge cortex-m0-support branch.
* VERSION: 0.05.
* example-led/sys.c (gpio_init): Support MCU_STM32F0. * example-led/sys.c (gpio_init): Support MCU_STM32F0.
(reset): Support __ARM_ARCH_6M__. (reset): Support __ARM_ARCH_6M__.
* example-led/sample.ld: Change for Cortex-M0. * example-led/sample.ld: Change for Cortex-M0.

14
board/board-fsm-55.h
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@@ -12,26 +12,26 @@
#define STM32_PLLMUL_VALUE 12 #define STM32_PLLMUL_VALUE 12
#define STM32_HSICLK 8000000 #define STM32_HSICLK 8000000
#define GPIO_LED_SET_TO_EMIT 5 #define GPIO_LED_BASE GPIOA_BASE
#define GPIO_LED_SET_TO_EMIT 5
#define GPIO_OTHER_BASE GPIOF_BASE /* USER BUTTON */
/* /*
* Port A setup. * Port A setup.
* PA5 - ON (LED 1:ON 0:OFF) * PA5 - ON (LED 1:ON 0:OFF)
* PA4 - Pull DOWN * PA4 - Pull DOWN
*/ */
#define VAL_GPIO_MODER 0x00145555 /* Output Pin0-7, Pin9 and Pin10 */ #define VAL_GPIO_LED_MODER 0x00145555 /* Output Pin0-7, Pin9 and Pin10 */
#define VAL_GPIO_OTYPER 0x0000001f /* Open-drain for Pin0-4, Push-Pull*/ #define VAL_GPIO_LED_OTYPER 0x0000001f /* Open-drain for Pin0-4, Push-Pull*/
#define VAL_GPIO_OSPEEDR 0x003cffff /* High speed */ #define VAL_GPIO_LED_OSPEEDR 0x003cffff /* High speed */
#define VAL_GPIO_PUPDR 0x00000000 /* No pull-up/pull-down */ #define VAL_GPIO_LED_PUPDR 0x00000000 /* No pull-up/pull-down */
#define GPIO_LED_BASE GPIOA_BASE
#define RCC_ENR_IOP_EN (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPFEN) #define RCC_ENR_IOP_EN (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPFEN)
#define RCC_RSTR_IOP_RST (RCC_AHBRSTR_IOPARST | RCC_AHBRSTR_IOPFRST) #define RCC_RSTR_IOP_RST (RCC_AHBRSTR_IOPARST | RCC_AHBRSTR_IOPFRST)
/* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */ /* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */
#define GPIO_OTHER_BASE GPIOF_BASE /* USER BUTTON */
/* /*
* Port F setup. * Port F setup.
* PF0 - USER Button * PF0 - USER Button

14
board/board-stm32f0-discovery.h
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@@ -12,19 +12,20 @@
#define STM32_PLLMUL_VALUE 12 #define STM32_PLLMUL_VALUE 12
#define STM32_HSICLK 8000000 #define STM32_HSICLK 8000000
#define GPIO_LED_SET_TO_EMIT 8 #define GPIO_LED_BASE GPIOC_BASE
#define GPIO_LED_SET_TO_EMIT 8
#define GPIO_OTHER_BASE GPIOA_BASE /* USER BUTTON */
/* /*
* Port C setup. * Port C setup.
* PC9 - LED3 (LED 1:ON 0:OFF) * PC9 - LED3 (LED 1:ON 0:OFF)
* PC8 - LED4 (LED 1:ON 0:OFF) * PC8 - LED4 (LED 1:ON 0:OFF)
*/ */
#define VAL_GPIO_MODER 0x00050000 /* Output Pin9 and Pin8 */ #define VAL_GPIO_LED_MODER 0x00050000 /* Output Pin9 and Pin8 */
#define VAL_GPIO_OTYPER 0x00000000 /* Push-Pull */ #define VAL_GPIO_LED_OTYPER 0x00000000 /* Push-Pull */
#define VAL_GPIO_OSPEEDR 0x000f0000 /* High speed: Pin9 and Pin8 */ #define VAL_GPIO_LED_OSPEEDR 0x000f0000 /* High speed: Pin9 and Pin8 */
#define VAL_GPIO_PUPDR 0x00000000 /* No pull-up/pull-down */ #define VAL_GPIO_LED_PUPDR 0x00000000 /* No pull-up/pull-down */
#define GPIO_LED_BASE GPIOC_BASE
#if 0 #if 0
#define RCC_ENR_IOP_EN (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPCEN) #define RCC_ENR_IOP_EN (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPCEN)
@@ -36,7 +37,6 @@
/* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */ /* ??? NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */
#define GPIO_OTHER_BASE GPIOA_BASE /* USER BUTTON */
/* /*
* Port A setup. * Port A setup.
* PA0 - USER Button * PA0 - USER Button

8
clk_gpio_init.c
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@@ -328,10 +328,10 @@ gpio_init (void)
#endif #endif
#if defined(MCU_STM32F0) #if defined(MCU_STM32F0)
GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR; GPIO_LED->OSPEEDR = VAL_GPIO_LED_OSPEEDR;
GPIO_LED->OTYPER = VAL_GPIO_OTYPER; GPIO_LED->OTYPER = VAL_GPIO_LED_OTYPER;
GPIO_LED->MODER = VAL_GPIO_MODER; GPIO_LED->MODER = VAL_GPIO_LED_MODER;
GPIO_LED->PUPDR = VAL_GPIO_PUPDR; GPIO_LED->PUPDR = VAL_GPIO_LED_PUPDR;
#ifdef GPIO_OTHER_BASE #ifdef GPIO_OTHER_BASE
GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR; GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;

2
example-fsm-55/hacker-emblem.c
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@@ -1 +1 @@
debian-logo.c hh.c

332
example-fsm-55/sys.c
View File

@@ -1,7 +1,7 @@
/* /*
* sys.c - system routines for the initial page for STM32F030 / STM32F103. * sys.c - system routines for the initial page for STM32F030 / STM32F103.
* *
* Copyright (C) 2013, 2014 Flying Stone Technology * Copyright (C) 2013, 2014, 2015 Flying Stone Technology
* Author: NIIBE Yutaka <gniibe@fsij.org> * Author: NIIBE Yutaka <gniibe@fsij.org>
* *
* Copying and distribution of this file, with or without modification, * Copying and distribution of this file, with or without modification,
@@ -17,59 +17,13 @@
#include <stdlib.h> #include <stdlib.h>
#include "board.h" #include "board.h"
#include "clk_gpio_init.c"
#define CORTEX_PRIORITY_BITS 4 #define CORTEX_PRIORITY_BITS 4
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS)) #define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
#define USB_LP_CAN1_RX0_IRQn 20 #define USB_LP_CAN1_RX0_IRQn 20
#define STM32_USB_IRQ_PRIORITY 11 #define STM32_USB_IRQ_PRIORITY 11
#define STM32_SW_HSI (0 << 0)
#define STM32_SW_PLL (2 << 0)
#define STM32_PLLSRC_HSI (0 << 16)
#define STM32_PLLSRC_HSE (1 << 16)
#define STM32_PLLXTPRE_DIV1 (0 << 17)
#define STM32_PLLXTPRE_DIV2 (1 << 17)
#define STM32_HPRE_DIV1 (0 << 4)
#define STM32_PPRE1_DIV1 (0 << 8)
#define STM32_PPRE1_DIV2 (4 << 8)
#define STM32_PPRE2_DIV1 (0 << 11)
#define STM32_PPRE2_DIV2 (4 << 11)
#define STM32_ADCPRE_DIV4 (1 << 14)
#define STM32_ADCPRE_DIV6 (2 << 14)
#define STM32_USBPRE_DIV1P5 (0 << 22)
#define STM32_MCO_NOCLOCK (0 << 24)
#if MCU_STM32F0
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_FLASHBITS 0x00000011
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
#else
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_FLASHBITS 0x00000012
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
#endif
#define STM32_SW STM32_SW_PLL
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_ADCPRE STM32_ADCPRE_DIV6
#define STM32_MCOSEL STM32_MCO_NOCLOCK
#define STM32_USBPRE STM32_USBPRE_DIV1P5
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
#define STM32_SYSCLK STM32_PLLCLKOUT
#define STM32_HCLK (STM32_SYSCLK / 1)
struct NVIC { struct NVIC {
uint32_t ISER[8]; uint32_t ISER[8];
uint32_t unused1[24]; uint32_t unused1[24];
@@ -99,288 +53,6 @@ nvic_enable_vector (uint32_t n, uint32_t prio)
NVIC_ISER (n) = 1 << (n & 0x1F); NVIC_ISER (n) = 1 << (n & 0x1F);
} }
#define PERIPH_BASE 0x40000000
#define APBPERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
struct RCC {
volatile uint32_t CR;
volatile uint32_t CFGR;
volatile uint32_t CIR;
volatile uint32_t APB2RSTR;
volatile uint32_t APB1RSTR;
volatile uint32_t AHBENR;
volatile uint32_t APB2ENR;
volatile uint32_t APB1ENR;
volatile uint32_t BDCR;
volatile uint32_t CSR;
#if MCU_STM32F0
volatile uint32_t AHBRSTR;
volatile uint32_t CFGR2;
volatile uint32_t CFGR3;
volatile uint32_t CR2;
#endif
};
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
#define RCC_APB1ENR_USBEN 0x00800000
#define RCC_APB1RSTR_USBRST 0x00800000
#define RCC_CR_HSION 0x00000001
#define RCC_CR_HSIRDY 0x00000002
#define RCC_CR_HSITRIM 0x000000F8
#define RCC_CR_HSEON 0x00010000
#define RCC_CR_HSERDY 0x00020000
#define RCC_CR_PLLON 0x01000000
#define RCC_CR_PLLRDY 0x02000000
#define RCC_CFGR_SWS 0x0000000C
#define RCC_CFGR_SWS_HSI 0x00000000
#define RCC_AHBENR_CRCEN 0x0040
#if MCU_STM32F0
#define RCC_AHBRSTR_IOPARST 0x00020000
#define RCC_AHBRSTR_IOPBRST 0x00040000
#define RCC_AHBRSTR_IOPCRST 0x00080000
#define RCC_AHBRSTR_IOPDRST 0x00100000
#define RCC_AHBRSTR_IOPFRST 0x00400000
#define RCC_AHBENR_IOPAEN 0x00020000
#define RCC_AHBENR_IOPBEN 0x00040000
#define RCC_AHBENR_IOPCEN 0x00080000
#define RCC_AHBENR_IOPDEN 0x00100000
#define RCC_AHBENR_IOPFEN 0x00400000
#define RCC_APB2RSTR_SYSCFGRST 0x00000001
#define RCC_APB2ENR_SYSCFGEN 0x00000001
#else
#define RCC_APB2RSTR_AFIORST 0x00000001
#define RCC_APB2RSTR_IOPARST 0x00000004
#define RCC_APB2RSTR_IOPBRST 0x00000008
#define RCC_APB2RSTR_IOPCRST 0x00000010
#define RCC_APB2RSTR_IOPDRST 0x00000020
#define RCC_APB2ENR_AFIOEN 0x00000001
#define RCC_APB2ENR_IOPAEN 0x00000004
#define RCC_APB2ENR_IOPBEN 0x00000008
#define RCC_APB2ENR_IOPCEN 0x00000010
#define RCC_APB2ENR_IOPDEN 0x00000020
#endif
#if MCU_STM32F0
struct SYSCFG {
volatile uint32_t CFGR1;
uint32_t dummy0;
volatile uint32_t EXTICR[4];
volatile uint32_t CFGR2;
};
#define SYSCFG_CFGR1_MEM_MODE 0x03
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
#endif
struct FLASH {
volatile uint32_t ACR;
volatile uint32_t KEYR;
volatile uint32_t OPTKEYR;
volatile uint32_t SR;
volatile uint32_t CR;
volatile uint32_t AR;
volatile uint32_t RESERVED;
volatile uint32_t OBR;
volatile uint32_t WRPR;
};
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
static void
clock_init (void)
{
/* HSI setup */
RCC->CR |= RCC_CR_HSION;
while (!(RCC->CR & RCC_CR_HSIRDY))
;
/* Reset HSEON, HSEBYP, CSSON, and PLLON, not touching RCC_CR_HSITRIM */
RCC->CR &= (RCC_CR_HSITRIM | RCC_CR_HSION);
RCC->CFGR = 0;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
;
#if !MCU_STM32F0
/* HSE setup */
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
;
#endif
/* PLL setup */
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
;
/* Clock settings */
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE
| STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Switching on the configured clock source. */
RCC->CFGR |= STM32_SW;
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
/*
* We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
*/
/* Flash setup */
FLASH->ACR = STM32_FLASHBITS;
/* CRC */
RCC->AHBENR |= RCC_AHBENR_CRCEN;
#if MCU_STM32F0
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
RCC->APB2RSTR = 0;
/* Use vectors on RAM */
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE) | 3;
#endif
}
#if MCU_STM32F0
struct GPIO {
volatile uint32_t MODER;
volatile uint16_t OTYPER;
uint16_t dummy0;
volatile uint32_t OSPEEDR;
volatile uint32_t PUPDR;
volatile uint16_t IDR;
uint16_t dummy1;
volatile uint16_t ODR;
uint16_t dummy2;
volatile uint16_t BSRR;
uint16_t dummy3;
volatile uint32_t LCKR;
volatile uint32_t AFR[2];
volatile uint16_t BRR;
uint16_t dummy4;
};
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
#define GPIOA ((struct GPIO *) GPIOA_BASE)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
#define GPIOB ((struct GPIO *) GPIOB_BASE)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
#define GPIOC ((struct GPIO *) GPIOC_BASE)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
#define GPIOD ((struct GPIO *) GPIOD_BASE)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
#define GPIOF ((struct GPIO *) GPIOF_BASE)
#else
struct AFIO
{
volatile uint32_t EVCR;
volatile uint32_t MAPR;
volatile uint32_t EXTICR[4];
uint32_t RESERVED0;
volatile uint32_t MAPR2;
};
#define AFIO_BASE 0x40010000
static struct AFIO *const AFIO = (struct AFIO *const)AFIO_BASE;
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800
#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000
struct GPIO {
volatile uint32_t CRL;
volatile uint32_t CRH;
volatile uint32_t IDR;
volatile uint32_t ODR;
volatile uint32_t BSRR;
volatile uint32_t BRR;
volatile uint32_t LCKR;
};
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOA ((struct GPIO *) GPIOA_BASE)
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define GPIOB ((struct GPIO *) GPIOB_BASE)
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define GPIOC ((struct GPIO *) GPIOC_BASE)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define GPIOD ((struct GPIO *) GPIOD_BASE)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define GPIOE ((struct GPIO *) GPIOE_BASE)
#endif
static struct GPIO *const GPIO_LED = ((struct GPIO *const) GPIO_LED_BASE);
#ifdef GPIO_USB_BASE
static struct GPIO *const GPIO_USB = ((struct GPIO *const) GPIO_USB_BASE);
#endif
#ifdef GPIO_OTHER_BASE
static struct GPIO *const GPIO_OTHER = ((struct GPIO *const) GPIO_OTHER_BASE);
#endif
static void
gpio_init (void)
{
/* Enable GPIO clock. */
#if MCU_STM32F0
RCC->AHBENR |= RCC_ENR_IOP_EN;
RCC->AHBRSTR = RCC_RSTR_IOP_RST;
RCC->AHBRSTR = 0;
#else
RCC->APB2ENR |= RCC_ENR_IOP_EN;
RCC->APB2RSTR = RCC_RSTR_IOP_RST;
RCC->APB2RSTR = 0;
#endif
#if MCU_STM32F0
GPIO_LED->OSPEEDR = VAL_GPIO_OSPEEDR;
GPIO_LED->OTYPER = VAL_GPIO_OTYPER;
GPIO_LED->MODER = VAL_GPIO_MODER;
GPIO_LED->PUPDR = VAL_GPIO_PUPDR;
#ifdef GPIO_OTHER_BASE
GPIO_OTHER->OSPEEDR = VAL_GPIO_OTHER_OSPEEDR;
GPIO_OTHER->OTYPER = VAL_GPIO_OTHER_OTYPER;
GPIO_OTHER->MODER = VAL_GPIO_OTHER_MODER;
GPIO_OTHER->PUPDR = VAL_GPIO_OTHER_PUPDR;
#endif
#else
#ifdef AFIO_MAPR_SOMETHING
AFIO->MAPR |= AFIO_MAPR_SOMETHING;
#endif
GPIO_USB->ODR = VAL_GPIO_ODR;
GPIO_USB->CRH = VAL_GPIO_CRH;
GPIO_USB->CRL = VAL_GPIO_CRL;
#if GPIO_USB_BASE != GPIO_LED_BASE
GPIO_LED->ODR = VAL_GPIO_LED_ODR;
GPIO_LED->CRH = VAL_GPIO_LED_CRH;
GPIO_LED->CRL = VAL_GPIO_LED_CRL;
#endif
#ifdef GPIO_OTHER_BASE
GPIO_OTHER->ODR = VAL_GPIO_OTHER_ODR;
GPIO_OTHER->CRH = VAL_GPIO_OTHER_CRH;
GPIO_OTHER->CRL = VAL_GPIO_OTHER_CRL;
#endif
#endif
}
static void static void
usb_cable_config (int enable) usb_cable_config (int enable)
{ {