deon/chopstx
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Fix examples.

Browse Source
This commit is contained in:
NIIBE Yutaka
2018-09-26 10:47:42 +09:00
parent d4f4f80ad9
commit 43bbdb44dc
12 changed files with 49 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
contrib/adc-mkl27z.c
View File

@@ -295,19 +295,20 @@ adc_stop (void)
int
adc_wait_completion (void)
{
struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&adc_intr };
int i;
while (1)
{
/* Wait DMA completion */
chopstx_poll (NULL, 1, pd_array);
chopstx_intr_wait (&adc_intr);
DMA0->DSR_BCR = (1 << 24);
DMA1->DSR_BCR = (1 << 24);
adc_stop_conversion ();
chopstx_intr_done (&adc_intr);
for (i = 0; i < adc.count; i++)
*adc.p++ = (uint8_t)adc.buf[i];

4
contrib/adc-stm32f103.c
View File

@@ -316,11 +316,10 @@ int
adc_wait_completion (void)
{
uint32_t flags;
struct chx_poll_head *pd_array[1] = { (struct chx_poll_head *)&adc_intr };
while (1)
{
chopstx_poll (NULL, 1, pd_array);
chopstx_intr_wait (&adc_intr);
flags = DMA1->ISR & STM32_DMA_ISR_MASK; /* Channel 1 interrupt cause. */
/*
* Clear interrupt cause of channel 1.
@@ -329,6 +328,7 @@ adc_wait_completion (void)
* and TEIF.
*/
DMA1->IFCR = (flags & ~1);
chopstx_intr_done (&adc_intr);
if ((flags & STM32_DMA_ISR_TEIF) != 0) /* DMA errors */
{

10
contrib/usart-stm32f103.c
View File

@@ -541,10 +541,16 @@ usart_main (void *arg)
chopstx_poll (NULL, n, usart_poll);
if (usart2_intr.ready)
usart2_tx_ready = handle_intr (USART2, &usart2_rb_h2a, &usart2_stat);
{
usart2_tx_ready = handle_intr (USART2, &usart2_rb_h2a, &usart2_stat);
chopstx_intr_done (&usart2_intr);
}
if (usart3_intr.ready)
usart3_tx_ready = handle_intr (USART3, &usart3_rb_h2a, &usart3_stat);
{
usart3_tx_ready = handle_intr (USART3, &usart3_rb_h2a, &usart3_stat);
chopstx_intr_done (&usart3_intr);
}
if (usart2_tx_ready && usart2_app_write_event.ready)
usart2_tx_ready = handle_tx_ready (USART2,