diff --git a/ChangeLog b/ChangeLog index a87fcd1..d595cb2 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,22 @@ +2018-04-26 NIIBE Yutaka + + * board/board-blue-pill-g.h: New. Define STM32_ADCPRE and + STM32_USBPRE for 96MHz clock. + * mcu/stm32.h (STM32_USBPRE_DIV2): New for GD32F103. + * mcu/clk_gpio_init-stm32.c: Allow constants, which are defined by + board.h (STM32_ADCPRE and STM32_USBPRE). + * mcu/chx-stm32f103.c: Use STM32_ADCPRE and STM32_USBPRE. + + * mcu/usb-stm32f103.c (usb_lld_init): BTABLE setting at + initialization. + (usb_lld_reset): Not at each reset. + + * contrib/adc-stm32f103.c [MCU_STM32F1_GD32F1]: Use continuous + sampling with no DELIBARATELY_DO_IT_WRONG_START_STOP. + (adc_init): Wait after ADC_CR2_ADON. + (adc_start): Likewise. Enabling by ADC_CR2_ADON after all other + registers configuration. + 2018-01-19 NIIBE Yutaka * VERSION: 1.8. diff --git a/board/board-blue-pill-g.h b/board/board-blue-pill-g.h new file mode 100644 index 0000000..c78e38b --- /dev/null +++ b/board/board-blue-pill-g.h @@ -0,0 +1,42 @@ +#define BOARD_NAME "Blue Pill GD32F103" +/* http://wiki.stm32duino.com/index.php?title=Blue_Pill */ +/* echo -n "Blue Pill GD32F103" | shasum -a 256 | sed -e 's/^.*\(........\) -$/\1/' */ +#define BOARD_ID 0xed415594 + +#define MCU_STM32F1_GD32F1 1 +#define STM32_USBPRE STM32_USBPRE_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV8 + +#define MCU_STM32F1 1 +#define STM32F10X_MD /* Medium-density device */ + +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HSECLK 8000000 + +#define GPIO_LED_BASE GPIOC_BASE +#define GPIO_LED_CLEAR_TO_EMIT 13 +#define GPIO_USB_BASE GPIOA_BASE +#undef GPIO_OTHER_BASE + +/* + * Port A setup. + * PA11 - Push Pull output 10MHz 0 default (until USB enabled) (USBDM) + * PA12 - Push Pull output 10MHz 0 default (until USB enabled) (USBDP) + * + * Port C setup. + * PC13 - Push pull output 50MHz (LED 1:ON 0:OFF) + * ------------------------ Default + * PAx - input with pull-up + * PCx - input with pull-up + */ +#define VAL_GPIO_USB_ODR 0xFFFFE7FF +#define VAL_GPIO_USB_CRL 0x88888888 /* PA7...PA0 */ +#define VAL_GPIO_USB_CRH 0x88811888 /* PA15...PA8 */ + +#define VAL_GPIO_LED_ODR 0xFFFFFFFF +#define VAL_GPIO_LED_CRL 0x88888888 /* PC7...PC0 */ +#define VAL_GPIO_LED_CRH 0x88388888 /* PC15...PC8 */ + +#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN) +#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPCRST) diff --git a/contrib/adc-stm32f103.c b/contrib/adc-stm32f103.c index 20e058f..1f7867c 100644 --- a/contrib/adc-stm32f103.c +++ b/contrib/adc-stm32f103.c @@ -34,6 +34,8 @@ #include #include #include "adc.h" +#include "board.h" +#include "sys.h" #define STM32_ADC_ADC1_DMA_PRIORITY 2 @@ -69,7 +71,9 @@ #define ADC_CHANNEL_VREFINT 17 #define DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME +#ifndef MCU_STM32F1_GD32F1 #define DELIBARATELY_DO_IT_WRONG_START_STOP +#endif #ifdef DELIBARATELY_DO_IT_WRONG_VREF_SAMPLE_TIME #define ADC_SAMPLE_VREF ADC_SAMPLE_1P5 @@ -114,6 +118,8 @@ adc_init (void) ADC1->CR1 = 0; ADC1->CR2 = ADC_CR2_ADON; + chopstx_usec_wait (1000); + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) ; @@ -124,6 +130,8 @@ adc_init (void) ADC2->CR1 = 0; ADC2->CR2 = ADC_CR2_ADON; + chopstx_usec_wait (1000); + ADC2->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; while ((ADC2->CR2 & ADC_CR2_RSTCAL) != 0) ; @@ -137,9 +145,6 @@ adc_init (void) return 0; } -#include "board.h" -#include "sys.h" - static void get_adc_config (uint32_t config[4]) { @@ -212,24 +217,26 @@ adc_start (void) RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN); - ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0 - | ADC_CR1_SCAN); - ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART - | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON); ADC1->SMPR1 = NEUG_ADC_SETTING1_SMPR1; ADC1->SMPR2 = NEUG_ADC_SETTING1_SMPR2; ADC1->SQR1 = ADC_SQR1_NUM_CH(NEUG_ADC_SETTING1_NUM_CHANNELS); ADC1->SQR2 = 0; ADC1->SQR3 = NEUG_ADC_SETTING1_SQR3; - - ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0 + ADC1->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0 | ADC_CR1_SCAN); - ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON; + ADC1->CR2 = (ADC_CR2_TSVREFE | ADC_CR2_EXTTRIG | ADC_CR2_SWSTART + | ADC_CR2_EXTSEL | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON); + chopstx_usec_wait (1000); + ADC2->SMPR1 = config[0]; ADC2->SMPR2 = config[1]; ADC2->SQR1 = config[2]; ADC2->SQR2 = 0; ADC2->SQR3 = config[3]; + ADC2->CR1 = (ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0 + | ADC_CR1_SCAN); + ADC2->CR2 = ADC_CR2_EXTTRIG | ADC_CR2_CONT | ADC_CR2_ADON; + chopstx_usec_wait (1000); #ifdef DELIBARATELY_DO_IT_WRONG_START_STOP /* diff --git a/mcu/chx-stm32f103.c b/mcu/chx-stm32f103.c index 51d327e..0fbe8e5 100644 --- a/mcu/chx-stm32f103.c +++ b/mcu/chx-stm32f103.c @@ -6,7 +6,12 @@ extern int chx_allow_sleep; #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) - +#ifndef STM32_ADCPRE +#define STM32_ADCPRE STM32_ADCPRE_DIV6 +#endif +#ifndef STM32_USBPRE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#endif static void configure_clock (int high) @@ -16,16 +21,16 @@ configure_clock (int high) if (high) { - cfg = STM32_MCO_NOCLOCK | STM32_USBPRE_DIV1P5 + cfg = STM32_MCO_NOCLOCK | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC - | STM32_ADCPRE_DIV6 | STM32_PPRE2_DIV1 + | STM32_ADCPRE | STM32_PPRE2_DIV1 | STM32_PPRE1_DIV2 | STM32_HPRE_DIV1; cfg_sw = RCC_CFGR_SW_PLL; } else { - cfg = STM32_MCO_NOCLOCK | STM32_USBPRE_DIV1P5 + cfg = STM32_MCO_NOCLOCK | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC | STM32_ADCPRE_DIV8 | STM32_PPRE2_DIV16 | STM32_PPRE1_DIV16 | STM32_HPRE_DIV8; diff --git a/mcu/clk_gpio_init-stm32.c b/mcu/clk_gpio_init-stm32.c index ab74cdf..af4c6b5 100644 --- a/mcu/clk_gpio_init-stm32.c +++ b/mcu/clk_gpio_init-stm32.c @@ -43,9 +43,13 @@ #define STM32_SW STM32_SW_PLL #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1 +#ifndef STM32_ADCPRE #define STM32_ADCPRE STM32_ADCPRE_DIV6 +#endif #define STM32_MCOSEL STM32_MCO_NOCLOCK -#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#ifndef STM32_USBPRE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#endif #define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) #define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) diff --git a/mcu/stm32.h b/mcu/stm32.h index 1132d26..887f991 100644 --- a/mcu/stm32.h +++ b/mcu/stm32.h @@ -127,6 +127,7 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE; #define STM32_ADCPRE_DIV8 (3 << 14) #define STM32_USBPRE_DIV1P5 (0 << 22) +#define STM32_USBPRE_DIV2 (3 << 22) /* Not for STM32, but GD32F103 */ #define STM32_MCO_NOCLOCK (0 << 24) diff --git a/mcu/usb-stm32f103.c b/mcu/usb-stm32f103.c index e5a95d1..1603088 100644 --- a/mcu/usb-stm32f103.c +++ b/mcu/usb-stm32f103.c @@ -339,6 +339,9 @@ void usb_lld_init (struct usb_dev *dev, uint8_t feature) /* Clear Interrupt Status Register, and enable interrupt for USB */ st103_set_istr (0); + + st103_set_btable (); + st103_set_cntr (CNTR_CTRM | CNTR_OVRM | CNTR_ERRM | CNTR_WKUPM | CNTR_SUSPM | CNTR_RESETM); @@ -906,7 +909,6 @@ void usb_lld_reset (struct usb_dev *dev, uint8_t feature) { usb_lld_set_configuration (dev, 0); dev->feature = feature; - st103_set_btable (); st103_set_daddr (0); }