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More change for clock setting.

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This commit is contained in:
NIIBE Yutaka
2017-11-17 15:32:51 +09:00
parent 14cb38e56f
commit 3071929c62
4 changed files with 45 additions and 14 deletions
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42
mcu/chx-stm32f103.c
View File

@@ -1,21 +1,49 @@
#include <stdint.h>
#include <mcu/stm32.h>
#include <mcu/stm32f103.h>
#include "board.h"
extern int chx_allow_sleep;
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
static void
configure_clock (uint32_t cfg_sw)
configure_clock (int high)
{
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_MASK) | cfg_sw;
uint32_t cfg_sw;
uint32_t cfg;
if (high)
{
cfg = STM32_MCO_NOCLOCK | STM32_USBPRE_DIV1P5
| STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC
| STM32_ADCPRE_DIV6 | STM32_PPRE2_DIV1
| STM32_PPRE1_DIV2 | STM32_HPRE_DIV1;
cfg_sw = RCC_CFGR_SW_PLL;
}
else
{
cfg = STM32_MCO_NOCLOCK | STM32_USBPRE_DIV1P5
| STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC
| STM32_ADCPRE_DIV8 | STM32_PPRE2_DIV16
| STM32_PPRE1_DIV16 | STM32_HPRE_DIV8;
cfg_sw = RCC_CFGR_SW_HSI;
}
RCC->CFGR = cfg | cfg_sw;
while ((RCC->CFGR & RCC_CFGR_SWS) != (cfg_sw << 2))
;
}
/*
* When HOW=0 or HOW=1, clock is PLL (72MHz).
* When HOW=2, clock will be HSI (8MHz) on sleep.
* When HOW=0 or HOW=1, SYSCLK is PLL (72MHz).
* When HOW=2, SYSCLK will be 1MHz with HSI (8MHz) on sleep.
*
* With HSI clock, it can achieve lower power consumption.
* With lower clock, it can achieve lower power consumption.
*
* Implementation note: Deepsleep is only useful with RTC, Watch Dog,
* or WKUP pin. We can't use deepsleep for USB, it never wakes up.
@@ -25,7 +53,7 @@ void
chx_sleep_mode (int how)
{
if (how == 0 || how == 1)
configure_clock (RCC_CFGR_SW_PLL);
configure_clock (1);
/* how == 2: Defer setting to 8MHz clock to the idle function */
}
@@ -49,7 +77,7 @@ chx_idle (void)
else if (sleep_enabled == 2)
{
DBGMCU->CR &= ~DBG_SLEEP; /* Disable HCLK on sleep */
configure_clock (RCC_CFGR_SW_HCI);
configure_clock (0);
}
asm volatile ("cpsie i" : : : "memory");

3
mcu/clk_gpio_init-stm32.c
View File

@@ -118,9 +118,6 @@ clock_init (void)
/* Flash setup */
FLASH->ACR = STM32_FLASHBITS;
/* CRC */
RCC->AHBENR |= RCC_AHBENR_CRCEN;
/* Switching on the configured clock source. */
RCC->CFGR |= STM32_SW;
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

8
mcu/stm32.h
View File

@@ -39,6 +39,10 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE;
#define RCC_CFGR_SWS 0x0000000C
#define RCC_CFGR_SWS_HSI 0x00000000
#define RCC_CFGR_SW_HSI (0 << 0)
#define RCC_CFGR_SW_HSE (1 << 0)
#define RCC_CFGR_SW_PLL (2 << 0)
#define RCC_CFGR_SW_MASK (3 << 0)
#define RCC_AHBENR_DMA1EN 0x00000001
#define RCC_AHBENR_CRCEN 0x00000040
@@ -92,10 +96,6 @@ static struct RCC *const RCC = (struct RCC *)RCC_BASE;
#define RCC_APB2ENR_IOPGEN 0x00000100
#endif
#define RCC_CFGR_SW_HCI (0 << 0)
#define RCC_CFGR_SW_PLL (2 << 0)
#define RCC_CFGR_SW_MASK (3 << 0)
#define RCC_CFGR_SWS 0x0000000C
/* Clock setting values.
* Due to historical reason, it has the prefix of STM32_.