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ADC settings are consolidated into the driver

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This commit is contained in:
NIIBE Yutaka
2015-07-14 21:31:18 +09:00
parent a48ffaef47
commit 27f42c8522
9 changed files with 22 additions and 34 deletions
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2
board/board-cq-starm.h
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@@ -46,5 +46,3 @@
#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN|RCC_APB2ENR_IOPCEN)
#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST|RCC_APB2RSTR_IOPCRST)
/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */

2
board/board-fst-01-00.h
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@@ -31,5 +31,3 @@
#define RCC_ENR_IOP_EN RCC_APB2ENR_IOPAEN
#define RCC_RSTR_IOP_RST RCC_APB2RSTR_IOPARST
/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */

8
board/board-fst-01.h
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@@ -65,11 +65,3 @@
#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
/* NeuG settings for ADC2. */
#define NEUG_ADC_SETTING2_SMPR1 0
#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN0(ADC_SAMPLE_1P5) \
| ADC_SMPR2_SMP_AN9(ADC_SAMPLE_1P5)
#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN0) \
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN9)
#define NEUG_ADC_SETTING2_NUM_CHANNELS 2

2
board/board-maple-mini.h
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@@ -40,5 +40,3 @@
#define RCC_ENR_IOP_EN (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN)
#define RCC_RSTR_IOP_RST (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST)
/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */

8
board/board-stbee-mini.h
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@@ -112,11 +112,3 @@
#define AFIO_MAPR_SOMETHING AFIO_MAPR_SWJ_CFG_DISABLE
/* NeuG settings for ADC2. */
#define NEUG_ADC_SETTING2_SMPR1 0
#define NEUG_ADC_SETTING2_SMPR2 ADC_SMPR2_SMP_AN1(ADC_SAMPLE_1P5) \
| ADC_SMPR2_SMP_AN2(ADC_SAMPLE_1P5)
#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN1) \
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN2)
#define NEUG_ADC_SETTING2_NUM_CHANNELS 2

8
board/board-stbee.h
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@@ -34,11 +34,3 @@
#define VAL_GPIO_LED_ODR 0xFFFFFFFF
#define VAL_GPIO_LED_CRL 0x88862888 /* PD7...PD0 */
#define VAL_GPIO_LED_CRH 0x88888888 /* PD15...PD8 */
/* NeuG settings for ADC2. */
#define NEUG_ADC_SETTING2_SMPR1 ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5) \
| ADC_SMPR1_SMP_AN11(ADC_SAMPLE_1P5)
#define NEUG_ADC_SETTING2_SMPR2 0
#define NEUG_ADC_SETTING2_SQR3 ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) \
| ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11)
#define NEUG_ADC_SETTING2_NUM_CHANNELS 2

2
board/board-stm32-primer2.h
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@@ -56,5 +56,3 @@
(RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_IOPEEN)
#define RCC_RSTR_IOP_RST \
(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPDRST | RCC_APB2RSTR_IOPERST)
/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */

2
board/board-stm8s-discovery.h
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@@ -48,8 +48,6 @@
#define RCC_RSTR_IOP_RST \
(RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | RCC_APB2RSTR_AFIORST)
/* NeuG settings for ADC2 is default (PA0: Analog IN0, PA1: Analog IN1). */
/*
* Port B setup.
* PB4 - (TIM3_CH1) input with pull-up